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Elijah Orr / mbed-renbed

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TARGET_NUCLEO_F103RB/stm32f1xx_hal_eth.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 96:487b796308b0

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	96:487b796308b0	1	/**
Kojto	96:487b796308b0	2	******************************************************************************
Kojto	96:487b796308b0	3	* @file stm32f1xx_hal_eth.h
Kojto	96:487b796308b0	4	* @author MCD Application Team
Kojto	96:487b796308b0	5	* @version V1.0.0
Kojto	96:487b796308b0	6	* @date 15-December-2014
Kojto	96:487b796308b0	7	* @brief Header file of ETH HAL module.
Kojto	96:487b796308b0	8	******************************************************************************
Kojto	96:487b796308b0	9	* @attention
Kojto	96:487b796308b0	10	*
Kojto	96:487b796308b0	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	96:487b796308b0	12	*
Kojto	96:487b796308b0	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	96:487b796308b0	14	* are permitted provided that the following conditions are met:
Kojto	96:487b796308b0	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	96:487b796308b0	16	* this list of conditions and the following disclaimer.
Kojto	96:487b796308b0	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	96:487b796308b0	18	* this list of conditions and the following disclaimer in the documentation
Kojto	96:487b796308b0	19	* and/or other materials provided with the distribution.
Kojto	96:487b796308b0	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	96:487b796308b0	21	* may be used to endorse or promote products derived from this software
Kojto	96:487b796308b0	22	* without specific prior written permission.
Kojto	96:487b796308b0	23	*
Kojto	96:487b796308b0	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	96:487b796308b0	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	96:487b796308b0	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	96:487b796308b0	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	96:487b796308b0	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	96:487b796308b0	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	96:487b796308b0	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	96:487b796308b0	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	96:487b796308b0	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	96:487b796308b0	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	96:487b796308b0	34	*
Kojto	96:487b796308b0	35	******************************************************************************
Kojto	96:487b796308b0	36	*/
Kojto	96:487b796308b0	37
Kojto	96:487b796308b0	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	96:487b796308b0	39	#ifndef __STM32F1xx_HAL_ETH_H
Kojto	96:487b796308b0	40	#define __STM32F1xx_HAL_ETH_H
Kojto	96:487b796308b0	41
Kojto	96:487b796308b0	42	#ifdef __cplusplus
Kojto	96:487b796308b0	43	extern "C" {
Kojto	96:487b796308b0	44	#endif
Kojto	96:487b796308b0	45
Kojto	96:487b796308b0	46	/* Includes ------------------------------------------------------------------*/
Kojto	96:487b796308b0	47	#include "stm32f1xx_hal_def.h"
Kojto	96:487b796308b0	48
Kojto	96:487b796308b0	49	/** @addtogroup STM32F1xx_HAL_Driver
Kojto	96:487b796308b0	50	* @{
Kojto	96:487b796308b0	51	*/
Kojto	96:487b796308b0	52	#if defined (STM32F107xC)
Kojto	96:487b796308b0	53
Kojto	96:487b796308b0	54	/** @addtogroup ETH
Kojto	96:487b796308b0	55	* @{
Kojto	96:487b796308b0	56	*/
Kojto	96:487b796308b0	57
Kojto	96:487b796308b0	58	/** @addtogroup ETH_Private_Macros
Kojto	96:487b796308b0	59	* @{
Kojto	96:487b796308b0	60	*/
Kojto	96:487b796308b0	61	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
Kojto	96:487b796308b0	62	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
Kojto	96:487b796308b0	63	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
Kojto	96:487b796308b0	64	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
Kojto	96:487b796308b0	65	((SPEED) == ETH_SPEED_100M))
Kojto	96:487b796308b0	66	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
Kojto	96:487b796308b0	67	((MODE) == ETH_MODE_HALFDUPLEX))
Kojto	96:487b796308b0	68	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
Kojto	96:487b796308b0	69	((MODE) == ETH_MODE_HALFDUPLEX))
Kojto	96:487b796308b0	70	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
Kojto	96:487b796308b0	71	((MODE) == ETH_RXINTERRUPT_MODE))
Kojto	96:487b796308b0	72	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
Kojto	96:487b796308b0	73	((MODE) == ETH_RXINTERRUPT_MODE))
Kojto	96:487b796308b0	74	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
Kojto	96:487b796308b0	75	((MODE) == ETH_RXINTERRUPT_MODE))
Kojto	96:487b796308b0	76	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
Kojto	96:487b796308b0	77	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
Kojto	96:487b796308b0	78	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
Kojto	96:487b796308b0	79	((MODE) == ETH_MEDIA_INTERFACE_RMII))
Kojto	96:487b796308b0	80	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
Kojto	96:487b796308b0	81	((CMD) == ETH_WATCHDOG_DISABLE))
Kojto	96:487b796308b0	82	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
Kojto	96:487b796308b0	83	((CMD) == ETH_JABBER_DISABLE))
Kojto	96:487b796308b0	84	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
Kojto	96:487b796308b0	85	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
Kojto	96:487b796308b0	86	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
Kojto	96:487b796308b0	87	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
Kojto	96:487b796308b0	88	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
Kojto	96:487b796308b0	89	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
Kojto	96:487b796308b0	90	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
Kojto	96:487b796308b0	91	((GAP) == ETH_INTERFRAMEGAP_40BIT))
Kojto	96:487b796308b0	92	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
Kojto	96:487b796308b0	93	((CMD) == ETH_CARRIERSENCE_DISABLE))
Kojto	96:487b796308b0	94	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
Kojto	96:487b796308b0	95	((CMD) == ETH_RECEIVEOWN_DISABLE))
Kojto	96:487b796308b0	96	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
Kojto	96:487b796308b0	97	((CMD) == ETH_LOOPBACKMODE_DISABLE))
Kojto	96:487b796308b0	98	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
Kojto	96:487b796308b0	99	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
Kojto	96:487b796308b0	100	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
Kojto	96:487b796308b0	101	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
Kojto	96:487b796308b0	102	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
Kojto	96:487b796308b0	103	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
Kojto	96:487b796308b0	104	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
Kojto	96:487b796308b0	105	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
Kojto	96:487b796308b0	106	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
Kojto	96:487b796308b0	107	((LIMIT) == ETH_BACKOFFLIMIT_1))
Kojto	96:487b796308b0	108	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
Kojto	96:487b796308b0	109	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
Kojto	96:487b796308b0	110	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
Kojto	96:487b796308b0	111	((CMD) == ETH_RECEIVEAll_DISABLE))
Kojto	96:487b796308b0	112	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
Kojto	96:487b796308b0	113	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
Kojto	96:487b796308b0	114	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
Kojto	96:487b796308b0	115	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
Kojto	96:487b796308b0	116	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
Kojto	96:487b796308b0	117	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
Kojto	96:487b796308b0	118	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
Kojto	96:487b796308b0	119	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
Kojto	96:487b796308b0	120	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
Kojto	96:487b796308b0	121	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
Kojto	96:487b796308b0	122	#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) \|\| \
Kojto	96:487b796308b0	123	((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
Kojto	96:487b796308b0	124	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
Kojto	96:487b796308b0	125	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
Kojto	96:487b796308b0	126	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
Kojto	96:487b796308b0	127	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
Kojto	96:487b796308b0	128	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
Kojto	96:487b796308b0	129	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
Kojto	96:487b796308b0	130	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
Kojto	96:487b796308b0	131	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
Kojto	96:487b796308b0	132	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
Kojto	96:487b796308b0	133	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
Kojto	96:487b796308b0	134	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
Kojto	96:487b796308b0	135	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
Kojto	96:487b796308b0	136	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
Kojto	96:487b796308b0	137	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
Kojto	96:487b796308b0	138	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
Kojto	96:487b796308b0	139	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
Kojto	96:487b796308b0	140	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
Kojto	96:487b796308b0	141	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
Kojto	96:487b796308b0	142	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
Kojto	96:487b796308b0	143	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
Kojto	96:487b796308b0	144	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
Kojto	96:487b796308b0	145	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
Kojto	96:487b796308b0	146	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
Kojto	96:487b796308b0	147	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
Kojto	96:487b796308b0	148	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
Kojto	96:487b796308b0	149	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
Kojto	96:487b796308b0	150	((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto	96:487b796308b0	151	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
Kojto	96:487b796308b0	152	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
Kojto	96:487b796308b0	153	((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto	96:487b796308b0	154	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
Kojto	96:487b796308b0	155	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
Kojto	96:487b796308b0	156	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
Kojto	96:487b796308b0	157	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
Kojto	96:487b796308b0	158	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
Kojto	96:487b796308b0	159	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
Kojto	96:487b796308b0	160	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
Kojto	96:487b796308b0	161	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
Kojto	96:487b796308b0	162	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
Kojto	96:487b796308b0	163	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
Kojto	96:487b796308b0	164	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
Kojto	96:487b796308b0	165	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
Kojto	96:487b796308b0	166	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
Kojto	96:487b796308b0	167	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
Kojto	96:487b796308b0	168	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
Kojto	96:487b796308b0	169	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
Kojto	96:487b796308b0	170	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
Kojto	96:487b796308b0	171	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
Kojto	96:487b796308b0	172	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
Kojto	96:487b796308b0	173	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
Kojto	96:487b796308b0	174	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
Kojto	96:487b796308b0	175	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
Kojto	96:487b796308b0	176	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
Kojto	96:487b796308b0	177	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
Kojto	96:487b796308b0	178	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
Kojto	96:487b796308b0	179	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
Kojto	96:487b796308b0	180	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
Kojto	96:487b796308b0	181	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
Kojto	96:487b796308b0	182	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
Kojto	96:487b796308b0	183	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
Kojto	96:487b796308b0	184	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
Kojto	96:487b796308b0	185	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
Kojto	96:487b796308b0	186	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
Kojto	96:487b796308b0	187	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
Kojto	96:487b796308b0	188	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
Kojto	96:487b796308b0	189	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
Kojto	96:487b796308b0	190	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
Kojto	96:487b796308b0	191	((CMD) == ETH_FIXEDBURST_DISABLE))
Kojto	96:487b796308b0	192	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
Kojto	96:487b796308b0	193	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
Kojto	96:487b796308b0	194	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
Kojto	96:487b796308b0	195	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
Kojto	96:487b796308b0	196	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
Kojto	96:487b796308b0	197	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
Kojto	96:487b796308b0	198	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
Kojto	96:487b796308b0	199	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
Kojto	96:487b796308b0	200	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
Kojto	96:487b796308b0	201	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
Kojto	96:487b796308b0	202	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
Kojto	96:487b796308b0	203	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto	96:487b796308b0	204	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
Kojto	96:487b796308b0	205	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
Kojto	96:487b796308b0	206	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
Kojto	96:487b796308b0	207	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
Kojto	96:487b796308b0	208	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
Kojto	96:487b796308b0	209	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
Kojto	96:487b796308b0	210	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
Kojto	96:487b796308b0	211	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
Kojto	96:487b796308b0	212	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
Kojto	96:487b796308b0	213	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
Kojto	96:487b796308b0	214	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
Kojto	96:487b796308b0	215	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto	96:487b796308b0	216	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
Kojto	96:487b796308b0	217	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
Kojto	96:487b796308b0	218	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
Kojto	96:487b796308b0	219	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
Kojto	96:487b796308b0	220	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
Kojto	96:487b796308b0	221	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
Kojto	96:487b796308b0	222
Kojto	96:487b796308b0	223	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
Kojto	96:487b796308b0	224	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
Kojto	96:487b796308b0	225	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
Kojto	96:487b796308b0	226	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
Kojto	96:487b796308b0	227	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
Kojto	96:487b796308b0	228	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
Kojto	96:487b796308b0	229	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
Kojto	96:487b796308b0	230
Kojto	96:487b796308b0	231	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
Kojto	96:487b796308b0	232	((BUFFER) == ETH_DMARXDESC_BUFFER2))
Kojto	96:487b796308b0	233
Kojto	96:487b796308b0	234	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
Kojto	96:487b796308b0	235	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
Kojto	96:487b796308b0	236
Kojto	96:487b796308b0	237	/**
Kojto	96:487b796308b0	238	* @}
Kojto	96:487b796308b0	239	*/
Kojto	96:487b796308b0	240
Kojto	96:487b796308b0	241	/** @addtogroup ETH_Private_Constants
Kojto	96:487b796308b0	242	* @{
Kojto	96:487b796308b0	243	*/
Kojto	96:487b796308b0	244	/* Delay to wait when writing to some Ethernet registers */
Kojto	96:487b796308b0	245	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
Kojto	96:487b796308b0	246
Kojto	96:487b796308b0	247	/* ETHERNET Errors */
Kojto	96:487b796308b0	248	#define ETH_SUCCESS ((uint32_t)0)
Kojto	96:487b796308b0	249	#define ETH_ERROR ((uint32_t)1)
Kojto	96:487b796308b0	250
Kojto	96:487b796308b0	251	/* ETHERNET DMA Tx descriptors Collision Count Shift */
Kojto	96:487b796308b0	252	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
Kojto	96:487b796308b0	253
Kojto	96:487b796308b0	254	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
Kojto	96:487b796308b0	255	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto	96:487b796308b0	256
Kojto	96:487b796308b0	257	/* ETHERNET DMA Rx descriptors Frame Length Shift */
Kojto	96:487b796308b0	258	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
Kojto	96:487b796308b0	259
Kojto	96:487b796308b0	260	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
Kojto	96:487b796308b0	261	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto	96:487b796308b0	262
Kojto	96:487b796308b0	263	/* ETHERNET DMA Rx descriptors Frame length Shift */
Kojto	96:487b796308b0	264	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
Kojto	96:487b796308b0	265
Kojto	96:487b796308b0	266	/* ETHERNET MAC address offsets */
Kojto	96:487b796308b0	267	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
Kojto	96:487b796308b0	268	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
Kojto	96:487b796308b0	269
Kojto	96:487b796308b0	270	/* ETHERNET MACMIIAR register Mask */
Kojto	96:487b796308b0	271	#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
Kojto	96:487b796308b0	272
Kojto	96:487b796308b0	273	/* ETHERNET MACCR register Mask */
Kojto	96:487b796308b0	274	#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
Kojto	96:487b796308b0	275
Kojto	96:487b796308b0	276	/* ETHERNET MACFCR register Mask */
Kojto	96:487b796308b0	277	#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
Kojto	96:487b796308b0	278
Kojto	96:487b796308b0	279	/* ETHERNET DMAOMR register Mask */
Kojto	96:487b796308b0	280	#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
Kojto	96:487b796308b0	281
Kojto	96:487b796308b0	282	/* ETHERNET Remote Wake-up frame register length */
Kojto	96:487b796308b0	283	#define ETH_WAKEUP_REGISTER_LENGTH 8
Kojto	96:487b796308b0	284
Kojto	96:487b796308b0	285	/* ETHERNET Missed frames counter Shift */
Kojto	96:487b796308b0	286	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
Kojto	96:487b796308b0	287	/**
Kojto	96:487b796308b0	288	* @}
Kojto	96:487b796308b0	289	*/
Kojto	96:487b796308b0	290
Kojto	96:487b796308b0	291	/* Exported types ------------------------------------------------------------*/
Kojto	96:487b796308b0	292	/** @defgroup ETH_Exported_Types ETH Exported Types
Kojto	96:487b796308b0	293	* @{
Kojto	96:487b796308b0	294	*/
Kojto	96:487b796308b0	295
Kojto	96:487b796308b0	296	/**
Kojto	96:487b796308b0	297	* @brief HAL State structures definition
Kojto	96:487b796308b0	298	*/
Kojto	96:487b796308b0	299	typedef enum
Kojto	96:487b796308b0	300	{
Kojto	96:487b796308b0	301	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
Kojto	96:487b796308b0	302	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
Kojto	96:487b796308b0	303	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
Kojto	96:487b796308b0	304	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
Kojto	96:487b796308b0	305	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
Kojto	96:487b796308b0	306	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
Kojto	96:487b796308b0	307	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
Kojto	96:487b796308b0	308	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
Kojto	96:487b796308b0	309	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
Kojto	96:487b796308b0	310	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
Kojto	96:487b796308b0	311	}HAL_ETH_StateTypeDef;
Kojto	96:487b796308b0	312
Kojto	96:487b796308b0	313	/**
Kojto	96:487b796308b0	314	* @brief ETH Init Structure definition
Kojto	96:487b796308b0	315	*/
Kojto	96:487b796308b0	316
Kojto	96:487b796308b0	317	typedef struct
Kojto	96:487b796308b0	318	{
Kojto	96:487b796308b0	319	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
Kojto	96:487b796308b0	320	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
Kojto	96:487b796308b0	321	and the mode (half/full-duplex).
Kojto	96:487b796308b0	322	This parameter can be a value of @ref ETH_AutoNegotiation */
Kojto	96:487b796308b0	323
Kojto	96:487b796308b0	324	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
Kojto	96:487b796308b0	325	This parameter can be a value of @ref ETH_Speed */
Kojto	96:487b796308b0	326
Kojto	96:487b796308b0	327	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
Kojto	96:487b796308b0	328	This parameter can be a value of @ref ETH_Duplex_Mode */
Kojto	96:487b796308b0	329
Kojto	96:487b796308b0	330	uint16_t PhyAddress; /*!< Ethernet PHY address.
Kojto	96:487b796308b0	331	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
Kojto	96:487b796308b0	332
Kojto	96:487b796308b0	333	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
Kojto	96:487b796308b0	334
Kojto	96:487b796308b0	335	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
Kojto	96:487b796308b0	336	This parameter can be a value of @ref ETH_Rx_Mode */
Kojto	96:487b796308b0	337
Kojto	96:487b796308b0	338	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
Kojto	96:487b796308b0	339	This parameter can be a value of @ref ETH_Checksum_Mode */
Kojto	96:487b796308b0	340
Kojto	96:487b796308b0	341	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
Kojto	96:487b796308b0	342	This parameter can be a value of @ref ETH_Media_Interface */
Kojto	96:487b796308b0	343
Kojto	96:487b796308b0	344	} ETH_InitTypeDef;
Kojto	96:487b796308b0	345
Kojto	96:487b796308b0	346
Kojto	96:487b796308b0	347	/**
Kojto	96:487b796308b0	348	* @brief ETH MAC Configuration Structure definition
Kojto	96:487b796308b0	349	*/
Kojto	96:487b796308b0	350
Kojto	96:487b796308b0	351	typedef struct
Kojto	96:487b796308b0	352	{
Kojto	96:487b796308b0	353	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
Kojto	96:487b796308b0	354	When enabled, the MAC allows no more then 2048 bytes to be received.
Kojto	96:487b796308b0	355	When disabled, the MAC can receive up to 16384 bytes.
Kojto	96:487b796308b0	356	This parameter can be a value of @ref ETH_Watchdog */
Kojto	96:487b796308b0	357
Kojto	96:487b796308b0	358	uint32_t Jabber; /*!< Selects or not Jabber timer
Kojto	96:487b796308b0	359	When enabled, the MAC allows no more then 2048 bytes to be sent.
Kojto	96:487b796308b0	360	When disabled, the MAC can send up to 16384 bytes.
Kojto	96:487b796308b0	361	This parameter can be a value of @ref ETH_Jabber */
Kojto	96:487b796308b0	362
Kojto	96:487b796308b0	363	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
Kojto	96:487b796308b0	364	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
Kojto	96:487b796308b0	365
Kojto	96:487b796308b0	366	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
Kojto	96:487b796308b0	367	This parameter can be a value of @ref ETH_Carrier_Sense */
Kojto	96:487b796308b0	368
Kojto	96:487b796308b0	369	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
Kojto	96:487b796308b0	370	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
Kojto	96:487b796308b0	371	in Half-Duplex mode.
Kojto	96:487b796308b0	372	This parameter can be a value of @ref ETH_Receive_Own */
Kojto	96:487b796308b0	373
Kojto	96:487b796308b0	374	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
Kojto	96:487b796308b0	375	This parameter can be a value of @ref ETH_Loop_Back_Mode */
Kojto	96:487b796308b0	376
Kojto	96:487b796308b0	377	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
Kojto	96:487b796308b0	378	This parameter can be a value of @ref ETH_Checksum_Offload */
Kojto	96:487b796308b0	379
Kojto	96:487b796308b0	380	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
Kojto	96:487b796308b0	381	when a collision occurs (Half-Duplex mode).
Kojto	96:487b796308b0	382	This parameter can be a value of @ref ETH_Retry_Transmission */
Kojto	96:487b796308b0	383
Kojto	96:487b796308b0	384	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
Kojto	96:487b796308b0	385	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
Kojto	96:487b796308b0	386
Kojto	96:487b796308b0	387	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
Kojto	96:487b796308b0	388	This parameter can be a value of @ref ETH_Back_Off_Limit */
Kojto	96:487b796308b0	389
Kojto	96:487b796308b0	390	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
Kojto	96:487b796308b0	391	This parameter can be a value of @ref ETH_Deferral_Check */
Kojto	96:487b796308b0	392
Kojto	96:487b796308b0	393	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
Kojto	96:487b796308b0	394	This parameter can be a value of @ref ETH_Receive_All */
Kojto	96:487b796308b0	395
Kojto	96:487b796308b0	396	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
Kojto	96:487b796308b0	397	This parameter can be a value of @ref ETH_Source_Addr_Filter */
Kojto	96:487b796308b0	398
Kojto	96:487b796308b0	399	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
Kojto	96:487b796308b0	400	This parameter can be a value of @ref ETH_Pass_Control_Frames */
Kojto	96:487b796308b0	401
Kojto	96:487b796308b0	402	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
Kojto	96:487b796308b0	403	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
Kojto	96:487b796308b0	404
Kojto	96:487b796308b0	405	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
Kojto	96:487b796308b0	406	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
Kojto	96:487b796308b0	407
Kojto	96:487b796308b0	408	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
Kojto	96:487b796308b0	409	This parameter can be a value of @ref ETH_Promiscuous_Mode */
Kojto	96:487b796308b0	410
Kojto	96:487b796308b0	411	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
Kojto	96:487b796308b0	412	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
Kojto	96:487b796308b0	413
Kojto	96:487b796308b0	414	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
Kojto	96:487b796308b0	415	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
Kojto	96:487b796308b0	416
Kojto	96:487b796308b0	417	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
Kojto	96:487b796308b0	418	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
Kojto	96:487b796308b0	419
Kojto	96:487b796308b0	420	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
Kojto	96:487b796308b0	421	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
Kojto	96:487b796308b0	422
Kojto	96:487b796308b0	423	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
Kojto	96:487b796308b0	424	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
Kojto	96:487b796308b0	425
Kojto	96:487b796308b0	426	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
Kojto	96:487b796308b0	427	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
Kojto	96:487b796308b0	428
Kojto	96:487b796308b0	429	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
Kojto	96:487b796308b0	430	automatic retransmission of PAUSE Frame.
Kojto	96:487b796308b0	431	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
Kojto	96:487b796308b0	432
Kojto	96:487b796308b0	433	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
Kojto	96:487b796308b0	434	unicast address and unique multicast address).
Kojto	96:487b796308b0	435	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
Kojto	96:487b796308b0	436
Kojto	96:487b796308b0	437	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
Kojto	96:487b796308b0	438	disable its transmitter for a specified time (Pause Time)
Kojto	96:487b796308b0	439	This parameter can be a value of @ref ETH_Receive_Flow_Control */
Kojto	96:487b796308b0	440
Kojto	96:487b796308b0	441	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
Kojto	96:487b796308b0	442	or the MAC back-pressure operation (Half-Duplex mode)
Kojto	96:487b796308b0	443	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
Kojto	96:487b796308b0	444
Kojto	96:487b796308b0	445	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
Kojto	96:487b796308b0	446	comparison and filtering.
Kojto	96:487b796308b0	447	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
Kojto	96:487b796308b0	448
Kojto	96:487b796308b0	449	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
Kojto	96:487b796308b0	450
Kojto	96:487b796308b0	451	} ETH_MACInitTypeDef;
Kojto	96:487b796308b0	452
Kojto	96:487b796308b0	453
Kojto	96:487b796308b0	454	/**
Kojto	96:487b796308b0	455	* @brief ETH DMA Configuration Structure definition
Kojto	96:487b796308b0	456	*/
Kojto	96:487b796308b0	457
Kojto	96:487b796308b0	458	typedef struct
Kojto	96:487b796308b0	459	{
Kojto	96:487b796308b0	460	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
Kojto	96:487b796308b0	461	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
Kojto	96:487b796308b0	462
Kojto	96:487b796308b0	463	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
Kojto	96:487b796308b0	464	This parameter can be a value of @ref ETH_Receive_Store_Forward */
Kojto	96:487b796308b0	465
Kojto	96:487b796308b0	466	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
Kojto	96:487b796308b0	467	This parameter can be a value of @ref ETH_Flush_Received_Frame */
Kojto	96:487b796308b0	468
Kojto	96:487b796308b0	469	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
Kojto	96:487b796308b0	470	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
Kojto	96:487b796308b0	471
Kojto	96:487b796308b0	472	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
Kojto	96:487b796308b0	473	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
Kojto	96:487b796308b0	474
Kojto	96:487b796308b0	475	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
Kojto	96:487b796308b0	476	This parameter can be a value of @ref ETH_Forward_Error_Frames */
Kojto	96:487b796308b0	477
Kojto	96:487b796308b0	478	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
Kojto	96:487b796308b0	479	and length less than 64 bytes) including pad-bytes and CRC)
Kojto	96:487b796308b0	480	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
Kojto	96:487b796308b0	481
Kojto	96:487b796308b0	482	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
Kojto	96:487b796308b0	483	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
Kojto	96:487b796308b0	484
Kojto	96:487b796308b0	485	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
Kojto	96:487b796308b0	486	frame of Transmit data even before obtaining the status for the first frame.
Kojto	96:487b796308b0	487	This parameter can be a value of @ref ETH_Second_Frame_Operate */
Kojto	96:487b796308b0	488
Kojto	96:487b796308b0	489	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
Kojto	96:487b796308b0	490	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
Kojto	96:487b796308b0	491
Kojto	96:487b796308b0	492	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
Kojto	96:487b796308b0	493	This parameter can be a value of @ref ETH_Fixed_Burst */
Kojto	96:487b796308b0	494
Kojto	96:487b796308b0	495	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
Kojto	96:487b796308b0	496	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
Kojto	96:487b796308b0	497
Kojto	96:487b796308b0	498	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
Kojto	96:487b796308b0	499	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
Kojto	96:487b796308b0	500
Kojto	96:487b796308b0	501	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
Kojto	96:487b796308b0	502	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
Kojto	96:487b796308b0	503
Kojto	96:487b796308b0	504	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
Kojto	96:487b796308b0	505	This parameter can be a value of @ref ETH_DMA_Arbitration */
Kojto	96:487b796308b0	506	} ETH_DMAInitTypeDef;
Kojto	96:487b796308b0	507
Kojto	96:487b796308b0	508
Kojto	96:487b796308b0	509	/**
Kojto	96:487b796308b0	510	* @brief ETH DMA Descriptors data structure definition
Kojto	96:487b796308b0	511	*/
Kojto	96:487b796308b0	512
Kojto	96:487b796308b0	513	typedef struct
Kojto	96:487b796308b0	514	{
Kojto	96:487b796308b0	515	__IO uint32_t Status; /!< Status /
Kojto	96:487b796308b0	516
Kojto	96:487b796308b0	517	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
Kojto	96:487b796308b0	518
Kojto	96:487b796308b0	519	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
Kojto	96:487b796308b0	520
Kojto	96:487b796308b0	521	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
Kojto	96:487b796308b0	522
Kojto	96:487b796308b0	523	} ETH_DMADescTypeDef;
Kojto	96:487b796308b0	524
Kojto	96:487b796308b0	525
Kojto	96:487b796308b0	526	/**
Kojto	96:487b796308b0	527	* @brief Received Frame Informations structure definition
Kojto	96:487b796308b0	528	*/
Kojto	96:487b796308b0	529	typedef struct
Kojto	96:487b796308b0	530	{
Kojto	96:487b796308b0	531	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
Kojto	96:487b796308b0	532
Kojto	96:487b796308b0	533	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
Kojto	96:487b796308b0	534
Kojto	96:487b796308b0	535	uint32_t SegCount; /!< Segment count /
Kojto	96:487b796308b0	536
Kojto	96:487b796308b0	537	uint32_t length; /!< Frame length /
Kojto	96:487b796308b0	538
Kojto	96:487b796308b0	539	uint32_t buffer; /!< Frame buffer /
Kojto	96:487b796308b0	540
Kojto	96:487b796308b0	541	} ETH_DMARxFrameInfos;
Kojto	96:487b796308b0	542
Kojto	96:487b796308b0	543
Kojto	96:487b796308b0	544	/**
Kojto	96:487b796308b0	545	* @brief ETH Handle Structure definition
Kojto	96:487b796308b0	546	*/
Kojto	96:487b796308b0	547
Kojto	96:487b796308b0	548	typedef struct
Kojto	96:487b796308b0	549	{
Kojto	96:487b796308b0	550	ETH_TypeDef Instance; /!< Register base address */
Kojto	96:487b796308b0	551
Kojto	96:487b796308b0	552	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
Kojto	96:487b796308b0	553
Kojto	96:487b796308b0	554	uint32_t LinkStatus; /!< Ethernet link status /
Kojto	96:487b796308b0	555
Kojto	96:487b796308b0	556	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
Kojto	96:487b796308b0	557
Kojto	96:487b796308b0	558	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
Kojto	96:487b796308b0	559
Kojto	96:487b796308b0	560	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
Kojto	96:487b796308b0	561
Kojto	96:487b796308b0	562	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
Kojto	96:487b796308b0	563
Kojto	96:487b796308b0	564	HAL_LockTypeDef Lock; /!< ETH Lock /
Kojto	96:487b796308b0	565
Kojto	96:487b796308b0	566	} ETH_HandleTypeDef;
Kojto	96:487b796308b0	567
Kojto	96:487b796308b0	568	/**
Kojto	96:487b796308b0	569	* @}
Kojto	96:487b796308b0	570	*/
Kojto	96:487b796308b0	571
Kojto	96:487b796308b0	572	/* Exported constants --------------------------------------------------------*/
Kojto	96:487b796308b0	573	/** @defgroup ETH_Exported_Constants ETH Exported Constants
Kojto	96:487b796308b0	574	* @{
Kojto	96:487b796308b0	575	*/
Kojto	96:487b796308b0	576
Kojto	96:487b796308b0	577	/** @defgroup ETH_Buffers_setting ETH Buffers setting
Kojto	96:487b796308b0	578	* @{
Kojto	96:487b796308b0	579	*/
Kojto	96:487b796308b0	580	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC /
Kojto	96:487b796308b0	581	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
Kojto	96:487b796308b0	582	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
Kojto	96:487b796308b0	583	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
Kojto	96:487b796308b0	584	#define ETH_VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
Kojto	96:487b796308b0	585	#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
Kojto	96:487b796308b0	586	#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
Kojto	96:487b796308b0	587	#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
Kojto	96:487b796308b0	588
Kojto	96:487b796308b0	589	/* Ethernet driver receive buffers are organized in a chained linked-list, when
Kojto	96:487b796308b0	590	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
Kojto	96:487b796308b0	591	to the driver receive buffers memory.
Kojto	96:487b796308b0	592
Kojto	96:487b796308b0	593	Depending on the size of the received ethernet packet and the size of
Kojto	96:487b796308b0	594	each ethernet driver receive buffer, the received packet can take one or more
Kojto	96:487b796308b0	595	ethernet driver receive buffer.
Kojto	96:487b796308b0	596
Kojto	96:487b796308b0	597	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
Kojto	96:487b796308b0	598	and the total count of the driver receive buffers ETH_RXBUFNB.
Kojto	96:487b796308b0	599
Kojto	96:487b796308b0	600	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
Kojto	96:487b796308b0	601	example, they can be reconfigured in the application layer to fit the application
Kojto	96:487b796308b0	602	needs */
Kojto	96:487b796308b0	603
Kojto	96:487b796308b0	604	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
Kojto	96:487b796308b0	605	packet */
Kojto	96:487b796308b0	606	#ifndef ETH_RX_BUF_SIZE
Kojto	96:487b796308b0	607	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
Kojto	96:487b796308b0	608	#endif
Kojto	96:487b796308b0	609
Kojto	96:487b796308b0	610	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
Kojto	96:487b796308b0	611	#ifndef ETH_RXBUFNB
Kojto	96:487b796308b0	612	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
Kojto	96:487b796308b0	613	#endif
Kojto	96:487b796308b0	614
Kojto	96:487b796308b0	615
Kojto	96:487b796308b0	616	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
Kojto	96:487b796308b0	617	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
Kojto	96:487b796308b0	618	driver transmit buffers memory to the TxFIFO.
Kojto	96:487b796308b0	619
Kojto	96:487b796308b0	620	Depending on the size of the Ethernet packet to be transmitted and the size of
Kojto	96:487b796308b0	621	each ethernet driver transmit buffer, the packet to be transmitted can take
Kojto	96:487b796308b0	622	one or more ethernet driver transmit buffer.
Kojto	96:487b796308b0	623
Kojto	96:487b796308b0	624	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
Kojto	96:487b796308b0	625	and the total count of the driver transmit buffers ETH_TXBUFNB.
Kojto	96:487b796308b0	626
Kojto	96:487b796308b0	627	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
Kojto	96:487b796308b0	628	example, they can be reconfigured in the application layer to fit the application
Kojto	96:487b796308b0	629	needs */
Kojto	96:487b796308b0	630
Kojto	96:487b796308b0	631	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
Kojto	96:487b796308b0	632	packet */
Kojto	96:487b796308b0	633	#ifndef ETH_TX_BUF_SIZE
Kojto	96:487b796308b0	634	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
Kojto	96:487b796308b0	635	#endif
Kojto	96:487b796308b0	636
Kojto	96:487b796308b0	637	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
Kojto	96:487b796308b0	638	#ifndef ETH_TXBUFNB
Kojto	96:487b796308b0	639	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
Kojto	96:487b796308b0	640	#endif
Kojto	96:487b796308b0	641
Kojto	96:487b796308b0	642	/**
Kojto	96:487b796308b0	643	* @}
Kojto	96:487b796308b0	644	*/
Kojto	96:487b796308b0	645
Kojto	96:487b796308b0	646	/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
Kojto	96:487b796308b0	647	* @{
Kojto	96:487b796308b0	648	*/
Kojto	96:487b796308b0	649
Kojto	96:487b796308b0	650	/*
Kojto	96:487b796308b0	651	DMA Tx Desciptor
Kojto	96:487b796308b0	652	-----------------------------------------------------------------------------------------------
Kojto	96:487b796308b0	653	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
Kojto	96:487b796308b0	654	-----------------------------------------------------------------------------------------------
Kojto	96:487b796308b0	655	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
Kojto	96:487b796308b0	656	-----------------------------------------------------------------------------------------------
Kojto	96:487b796308b0	657	TDES2 \| Buffer1 Address [31:0] \|
Kojto	96:487b796308b0	658	-----------------------------------------------------------------------------------------------
Kojto	96:487b796308b0	659	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
Kojto	96:487b796308b0	660	-----------------------------------------------------------------------------------------------
Kojto	96:487b796308b0	661	*/
Kojto	96:487b796308b0	662
Kojto	96:487b796308b0	663	/**
Kojto	96:487b796308b0	664	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
Kojto	96:487b796308b0	665	*/
Kojto	96:487b796308b0	666	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
Kojto	96:487b796308b0	667	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
Kojto	96:487b796308b0	668	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
Kojto	96:487b796308b0	669	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
Kojto	96:487b796308b0	670	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
Kojto	96:487b796308b0	671	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
Kojto	96:487b796308b0	672	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
Kojto	96:487b796308b0	673	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
Kojto	96:487b796308b0	674	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
Kojto	96:487b796308b0	675	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
Kojto	96:487b796308b0	676	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
Kojto	96:487b796308b0	677	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
Kojto	96:487b796308b0	678	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
Kojto	96:487b796308b0	679	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
Kojto	96:487b796308b0	680	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
Kojto	96:487b796308b0	681	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
Kojto	96:487b796308b0	682	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
Kojto	96:487b796308b0	683	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
Kojto	96:487b796308b0	684	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
Kojto	96:487b796308b0	685	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
Kojto	96:487b796308b0	686	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
Kojto	96:487b796308b0	687	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
Kojto	96:487b796308b0	688	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
Kojto	96:487b796308b0	689	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
Kojto	96:487b796308b0	690	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
Kojto	96:487b796308b0	691	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
Kojto	96:487b796308b0	692	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
Kojto	96:487b796308b0	693	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
Kojto	96:487b796308b0	694	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
Kojto	96:487b796308b0	695
Kojto	96:487b796308b0	696	/**
Kojto	96:487b796308b0	697	* @brief Bit definition of TDES1 register
Kojto	96:487b796308b0	698	*/
Kojto	96:487b796308b0	699	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
Kojto	96:487b796308b0	700	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
Kojto	96:487b796308b0	701
Kojto	96:487b796308b0	702	/**
Kojto	96:487b796308b0	703	* @brief Bit definition of TDES2 register
Kojto	96:487b796308b0	704	*/
Kojto	96:487b796308b0	705	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
Kojto	96:487b796308b0	706
Kojto	96:487b796308b0	707	/**
Kojto	96:487b796308b0	708	* @brief Bit definition of TDES3 register
Kojto	96:487b796308b0	709	*/
Kojto	96:487b796308b0	710	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
Kojto	96:487b796308b0	711
Kojto	96:487b796308b0	712	/**
Kojto	96:487b796308b0	713	* @}
Kojto	96:487b796308b0	714	*/
Kojto	96:487b796308b0	715	/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
Kojto	96:487b796308b0	716	* @{
Kojto	96:487b796308b0	717	*/
Kojto	96:487b796308b0	718
Kojto	96:487b796308b0	719	/*
Kojto	96:487b796308b0	720	DMA Rx Descriptor
Kojto	96:487b796308b0	721	--------------------------------------------------------------------------------------------------------------------
Kojto	96:487b796308b0	722	RDES0 \| OWN(31) \| Status [30:0] \|
Kojto	96:487b796308b0	723	---------------------------------------------------------------------------------------------------------------------
Kojto	96:487b796308b0	724	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
Kojto	96:487b796308b0	725	---------------------------------------------------------------------------------------------------------------------
Kojto	96:487b796308b0	726	RDES2 \| Buffer1 Address [31:0] \|
Kojto	96:487b796308b0	727	---------------------------------------------------------------------------------------------------------------------
Kojto	96:487b796308b0	728	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
Kojto	96:487b796308b0	729	---------------------------------------------------------------------------------------------------------------------
Kojto	96:487b796308b0	730	*/
Kojto	96:487b796308b0	731
Kojto	96:487b796308b0	732	/**
Kojto	96:487b796308b0	733	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
Kojto	96:487b796308b0	734	*/
Kojto	96:487b796308b0	735	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
Kojto	96:487b796308b0	736	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
Kojto	96:487b796308b0	737	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
Kojto	96:487b796308b0	738	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
Kojto	96:487b796308b0	739	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
Kojto	96:487b796308b0	740	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
Kojto	96:487b796308b0	741	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
Kojto	96:487b796308b0	742	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
Kojto	96:487b796308b0	743	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
Kojto	96:487b796308b0	744	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
Kojto	96:487b796308b0	745	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
Kojto	96:487b796308b0	746	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
Kojto	96:487b796308b0	747	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
Kojto	96:487b796308b0	748	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
Kojto	96:487b796308b0	749	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
Kojto	96:487b796308b0	750	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
Kojto	96:487b796308b0	751	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
Kojto	96:487b796308b0	752	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
Kojto	96:487b796308b0	753	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
Kojto	96:487b796308b0	754
Kojto	96:487b796308b0	755	/**
Kojto	96:487b796308b0	756	* @brief Bit definition of RDES1 register
Kojto	96:487b796308b0	757	*/
Kojto	96:487b796308b0	758	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
Kojto	96:487b796308b0	759	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
Kojto	96:487b796308b0	760	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
Kojto	96:487b796308b0	761	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
Kojto	96:487b796308b0	762	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
Kojto	96:487b796308b0	763
Kojto	96:487b796308b0	764	/**
Kojto	96:487b796308b0	765	* @brief Bit definition of RDES2 register
Kojto	96:487b796308b0	766	*/
Kojto	96:487b796308b0	767	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
Kojto	96:487b796308b0	768
Kojto	96:487b796308b0	769	/**
Kojto	96:487b796308b0	770	* @brief Bit definition of RDES3 register
Kojto	96:487b796308b0	771	*/
Kojto	96:487b796308b0	772	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
Kojto	96:487b796308b0	773
Kojto	96:487b796308b0	774	/**
Kojto	96:487b796308b0	775	* @}
Kojto	96:487b796308b0	776	*/
Kojto	96:487b796308b0	777	/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
Kojto	96:487b796308b0	778	* @{
Kojto	96:487b796308b0	779	*/
Kojto	96:487b796308b0	780	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
Kojto	96:487b796308b0	781	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	782
Kojto	96:487b796308b0	783	/**
Kojto	96:487b796308b0	784	* @}
Kojto	96:487b796308b0	785	*/
Kojto	96:487b796308b0	786	/** @defgroup ETH_Speed ETH Speed
Kojto	96:487b796308b0	787	* @{
Kojto	96:487b796308b0	788	*/
Kojto	96:487b796308b0	789	#define ETH_SPEED_10M ((uint32_t)0x00000000)
Kojto	96:487b796308b0	790	#define ETH_SPEED_100M ((uint32_t)0x00004000)
Kojto	96:487b796308b0	791
Kojto	96:487b796308b0	792	/**
Kojto	96:487b796308b0	793	* @}
Kojto	96:487b796308b0	794	*/
Kojto	96:487b796308b0	795	/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
Kojto	96:487b796308b0	796	* @{
Kojto	96:487b796308b0	797	*/
Kojto	96:487b796308b0	798	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
Kojto	96:487b796308b0	799	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
Kojto	96:487b796308b0	800	/**
Kojto	96:487b796308b0	801	* @}
Kojto	96:487b796308b0	802	*/
Kojto	96:487b796308b0	803	/** @defgroup ETH_Rx_Mode ETH Rx Mode
Kojto	96:487b796308b0	804	* @{
Kojto	96:487b796308b0	805	*/
Kojto	96:487b796308b0	806	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	807	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
Kojto	96:487b796308b0	808	/**
Kojto	96:487b796308b0	809	* @}
Kojto	96:487b796308b0	810	*/
Kojto	96:487b796308b0	811
Kojto	96:487b796308b0	812	/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
Kojto	96:487b796308b0	813	* @{
Kojto	96:487b796308b0	814	*/
Kojto	96:487b796308b0	815	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	816	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
Kojto	96:487b796308b0	817	/**
Kojto	96:487b796308b0	818	* @}
Kojto	96:487b796308b0	819	*/
Kojto	96:487b796308b0	820
Kojto	96:487b796308b0	821	/** @defgroup ETH_Media_Interface ETH Media Interface
Kojto	96:487b796308b0	822	* @{
Kojto	96:487b796308b0	823	*/
Kojto	96:487b796308b0	824	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
Kojto	96:487b796308b0	825	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
Kojto	96:487b796308b0	826
Kojto	96:487b796308b0	827	/**
Kojto	96:487b796308b0	828	* @}
Kojto	96:487b796308b0	829	*/
Kojto	96:487b796308b0	830
Kojto	96:487b796308b0	831	/** @defgroup ETH_Watchdog ETH Watchdog
Kojto	96:487b796308b0	832	* @{
Kojto	96:487b796308b0	833	*/
Kojto	96:487b796308b0	834	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	835	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
Kojto	96:487b796308b0	836
Kojto	96:487b796308b0	837	/**
Kojto	96:487b796308b0	838	* @}
Kojto	96:487b796308b0	839	*/
Kojto	96:487b796308b0	840
Kojto	96:487b796308b0	841	/** @defgroup ETH_Jabber ETH Jabber
Kojto	96:487b796308b0	842	* @{
Kojto	96:487b796308b0	843	*/
Kojto	96:487b796308b0	844	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	845	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
Kojto	96:487b796308b0	846
Kojto	96:487b796308b0	847	/**
Kojto	96:487b796308b0	848	* @}
Kojto	96:487b796308b0	849	*/
Kojto	96:487b796308b0	850
Kojto	96:487b796308b0	851	/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
Kojto	96:487b796308b0	852	* @{
Kojto	96:487b796308b0	853	*/
Kojto	96:487b796308b0	854	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
Kojto	96:487b796308b0	855	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
Kojto	96:487b796308b0	856	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
Kojto	96:487b796308b0	857	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
Kojto	96:487b796308b0	858	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
Kojto	96:487b796308b0	859	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
Kojto	96:487b796308b0	860	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
Kojto	96:487b796308b0	861	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
Kojto	96:487b796308b0	862
Kojto	96:487b796308b0	863	/**
Kojto	96:487b796308b0	864	* @}
Kojto	96:487b796308b0	865	*/
Kojto	96:487b796308b0	866
Kojto	96:487b796308b0	867	/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
Kojto	96:487b796308b0	868	* @{
Kojto	96:487b796308b0	869	*/
Kojto	96:487b796308b0	870	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	871	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
Kojto	96:487b796308b0	872
Kojto	96:487b796308b0	873	/**
Kojto	96:487b796308b0	874	* @}
Kojto	96:487b796308b0	875	*/
Kojto	96:487b796308b0	876
Kojto	96:487b796308b0	877	/** @defgroup ETH_Receive_Own ETH Receive Own
Kojto	96:487b796308b0	878	* @{
Kojto	96:487b796308b0	879	*/
Kojto	96:487b796308b0	880	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	881	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
Kojto	96:487b796308b0	882
Kojto	96:487b796308b0	883	/**
Kojto	96:487b796308b0	884	* @}
Kojto	96:487b796308b0	885	*/
Kojto	96:487b796308b0	886
Kojto	96:487b796308b0	887	/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
Kojto	96:487b796308b0	888	* @{
Kojto	96:487b796308b0	889	*/
Kojto	96:487b796308b0	890	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
Kojto	96:487b796308b0	891	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	892
Kojto	96:487b796308b0	893	/**
Kojto	96:487b796308b0	894	* @}
Kojto	96:487b796308b0	895	*/
Kojto	96:487b796308b0	896
Kojto	96:487b796308b0	897	/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
Kojto	96:487b796308b0	898	* @{
Kojto	96:487b796308b0	899	*/
Kojto	96:487b796308b0	900	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
Kojto	96:487b796308b0	901	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	902
Kojto	96:487b796308b0	903	/**
Kojto	96:487b796308b0	904	* @}
Kojto	96:487b796308b0	905	*/
Kojto	96:487b796308b0	906
Kojto	96:487b796308b0	907	/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
Kojto	96:487b796308b0	908	* @{
Kojto	96:487b796308b0	909	*/
Kojto	96:487b796308b0	910	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	911	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
Kojto	96:487b796308b0	912
Kojto	96:487b796308b0	913	/**
Kojto	96:487b796308b0	914	* @}
Kojto	96:487b796308b0	915	*/
Kojto	96:487b796308b0	916
Kojto	96:487b796308b0	917	/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
Kojto	96:487b796308b0	918	* @{
Kojto	96:487b796308b0	919	*/
Kojto	96:487b796308b0	920	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
Kojto	96:487b796308b0	921	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	922
Kojto	96:487b796308b0	923	/**
Kojto	96:487b796308b0	924	* @}
Kojto	96:487b796308b0	925	*/
Kojto	96:487b796308b0	926
Kojto	96:487b796308b0	927	/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
Kojto	96:487b796308b0	928	* @{
Kojto	96:487b796308b0	929	*/
Kojto	96:487b796308b0	930	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
Kojto	96:487b796308b0	931	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
Kojto	96:487b796308b0	932	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
Kojto	96:487b796308b0	933	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
Kojto	96:487b796308b0	934
Kojto	96:487b796308b0	935	/**
Kojto	96:487b796308b0	936	* @}
Kojto	96:487b796308b0	937	*/
Kojto	96:487b796308b0	938
Kojto	96:487b796308b0	939	/** @defgroup ETH_Deferral_Check ETH Deferral Check
Kojto	96:487b796308b0	940	* @{
Kojto	96:487b796308b0	941	*/
Kojto	96:487b796308b0	942	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
Kojto	96:487b796308b0	943	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	944
Kojto	96:487b796308b0	945	/**
Kojto	96:487b796308b0	946	* @}
Kojto	96:487b796308b0	947	*/
Kojto	96:487b796308b0	948
Kojto	96:487b796308b0	949	/** @defgroup ETH_Receive_All ETH Receive All
Kojto	96:487b796308b0	950	* @{
Kojto	96:487b796308b0	951	*/
Kojto	96:487b796308b0	952	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
Kojto	96:487b796308b0	953	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	954
Kojto	96:487b796308b0	955	/**
Kojto	96:487b796308b0	956	* @}
Kojto	96:487b796308b0	957	*/
Kojto	96:487b796308b0	958
Kojto	96:487b796308b0	959	/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
Kojto	96:487b796308b0	960	* @{
Kojto	96:487b796308b0	961	*/
Kojto	96:487b796308b0	962	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
Kojto	96:487b796308b0	963	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
Kojto	96:487b796308b0	964	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	965
Kojto	96:487b796308b0	966	/**
Kojto	96:487b796308b0	967	* @}
Kojto	96:487b796308b0	968	*/
Kojto	96:487b796308b0	969
Kojto	96:487b796308b0	970	/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
Kojto	96:487b796308b0	971	* @{
Kojto	96:487b796308b0	972	*/
Kojto	96:487b796308b0	973	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
Kojto	96:487b796308b0	974	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
Kojto	96:487b796308b0	975	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
Kojto	96:487b796308b0	976
Kojto	96:487b796308b0	977	/**
Kojto	96:487b796308b0	978	* @}
Kojto	96:487b796308b0	979	*/
Kojto	96:487b796308b0	980
Kojto	96:487b796308b0	981	/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
Kojto	96:487b796308b0	982	* @{
Kojto	96:487b796308b0	983	*/
Kojto	96:487b796308b0	984	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	985	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
Kojto	96:487b796308b0	986
Kojto	96:487b796308b0	987	/**
Kojto	96:487b796308b0	988	* @}
Kojto	96:487b796308b0	989	*/
Kojto	96:487b796308b0	990
Kojto	96:487b796308b0	991	/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
Kojto	96:487b796308b0	992	* @{
Kojto	96:487b796308b0	993	*/
Kojto	96:487b796308b0	994	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
Kojto	96:487b796308b0	995	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
Kojto	96:487b796308b0	996
Kojto	96:487b796308b0	997	/**
Kojto	96:487b796308b0	998	* @}
Kojto	96:487b796308b0	999	*/
Kojto	96:487b796308b0	1000
Kojto	96:487b796308b0	1001	/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
Kojto	96:487b796308b0	1002	* @{
Kojto	96:487b796308b0	1003	*/
Kojto	96:487b796308b0	1004	#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
Kojto	96:487b796308b0	1005	#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1006
Kojto	96:487b796308b0	1007	/**
Kojto	96:487b796308b0	1008	* @}
Kojto	96:487b796308b0	1009	*/
Kojto	96:487b796308b0	1010
Kojto	96:487b796308b0	1011	/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
Kojto	96:487b796308b0	1012	* @{
Kojto	96:487b796308b0	1013	*/
Kojto	96:487b796308b0	1014	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
Kojto	96:487b796308b0	1015	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
Kojto	96:487b796308b0	1016	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1017	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
Kojto	96:487b796308b0	1018
Kojto	96:487b796308b0	1019	/**
Kojto	96:487b796308b0	1020	* @}
Kojto	96:487b796308b0	1021	*/
Kojto	96:487b796308b0	1022
Kojto	96:487b796308b0	1023	/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
Kojto	96:487b796308b0	1024	* @{
Kojto	96:487b796308b0	1025	*/
Kojto	96:487b796308b0	1026	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
Kojto	96:487b796308b0	1027	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
Kojto	96:487b796308b0	1028	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1029
Kojto	96:487b796308b0	1030	/**
Kojto	96:487b796308b0	1031	* @}
Kojto	96:487b796308b0	1032	*/
Kojto	96:487b796308b0	1033
Kojto	96:487b796308b0	1034	/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
Kojto	96:487b796308b0	1035	* @{
Kojto	96:487b796308b0	1036	*/
Kojto	96:487b796308b0	1037	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1038	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
Kojto	96:487b796308b0	1039
Kojto	96:487b796308b0	1040	/**
Kojto	96:487b796308b0	1041	* @}
Kojto	96:487b796308b0	1042	*/
Kojto	96:487b796308b0	1043
Kojto	96:487b796308b0	1044	/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
Kojto	96:487b796308b0	1045	* @{
Kojto	96:487b796308b0	1046	*/
Kojto	96:487b796308b0	1047	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
Kojto	96:487b796308b0	1048	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
Kojto	96:487b796308b0	1049	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
Kojto	96:487b796308b0	1050	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
Kojto	96:487b796308b0	1051
Kojto	96:487b796308b0	1052	/**
Kojto	96:487b796308b0	1053	* @}
Kojto	96:487b796308b0	1054	*/
Kojto	96:487b796308b0	1055
Kojto	96:487b796308b0	1056	/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
Kojto	96:487b796308b0	1057	* @{
Kojto	96:487b796308b0	1058	*/
Kojto	96:487b796308b0	1059	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
Kojto	96:487b796308b0	1060	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1061
Kojto	96:487b796308b0	1062	/**
Kojto	96:487b796308b0	1063	* @}
Kojto	96:487b796308b0	1064	*/
Kojto	96:487b796308b0	1065
Kojto	96:487b796308b0	1066	/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
Kojto	96:487b796308b0	1067	* @{
Kojto	96:487b796308b0	1068	*/
Kojto	96:487b796308b0	1069	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
Kojto	96:487b796308b0	1070	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1071
Kojto	96:487b796308b0	1072	/**
Kojto	96:487b796308b0	1073	* @}
Kojto	96:487b796308b0	1074	*/
Kojto	96:487b796308b0	1075
Kojto	96:487b796308b0	1076	/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
Kojto	96:487b796308b0	1077	* @{
Kojto	96:487b796308b0	1078	*/
Kojto	96:487b796308b0	1079	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
Kojto	96:487b796308b0	1080	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1081
Kojto	96:487b796308b0	1082	/**
Kojto	96:487b796308b0	1083	* @}
Kojto	96:487b796308b0	1084	*/
Kojto	96:487b796308b0	1085
Kojto	96:487b796308b0	1086	/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
Kojto	96:487b796308b0	1087	* @{
Kojto	96:487b796308b0	1088	*/
Kojto	96:487b796308b0	1089	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
Kojto	96:487b796308b0	1090	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1091
Kojto	96:487b796308b0	1092	/**
Kojto	96:487b796308b0	1093	* @}
Kojto	96:487b796308b0	1094	*/
Kojto	96:487b796308b0	1095
Kojto	96:487b796308b0	1096	/** @defgroup ETH_MAC_addresses ETH MAC addresses
Kojto	96:487b796308b0	1097	* @{
Kojto	96:487b796308b0	1098	*/
Kojto	96:487b796308b0	1099	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1100	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
Kojto	96:487b796308b0	1101	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
Kojto	96:487b796308b0	1102	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
Kojto	96:487b796308b0	1103
Kojto	96:487b796308b0	1104	/**
Kojto	96:487b796308b0	1105	* @}
Kojto	96:487b796308b0	1106	*/
Kojto	96:487b796308b0	1107
Kojto	96:487b796308b0	1108	/** @defgroup ETH_MAC_Addresses_Filter_SA_DA ETH MAC Addresses Filter SA DA
Kojto	96:487b796308b0	1109	* @{
Kojto	96:487b796308b0	1110	*/
Kojto	96:487b796308b0	1111	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1112	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
Kojto	96:487b796308b0	1113	/**
Kojto	96:487b796308b0	1114	* @}
Kojto	96:487b796308b0	1115	*/
Kojto	96:487b796308b0	1116
Kojto	96:487b796308b0	1117	/** @defgroup ETH_MAC_Addresses_Filter_Mask_Bytes ETH_MAC Addresses Filter Mask Bytes
Kojto	96:487b796308b0	1118	* @{
Kojto	96:487b796308b0	1119	*/
Kojto	96:487b796308b0	1120	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
Kojto	96:487b796308b0	1121	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
Kojto	96:487b796308b0	1122	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
Kojto	96:487b796308b0	1123	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
Kojto	96:487b796308b0	1124	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
Kojto	96:487b796308b0	1125	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
Kojto	96:487b796308b0	1126
Kojto	96:487b796308b0	1127	/**
Kojto	96:487b796308b0	1128	* @}
Kojto	96:487b796308b0	1129	*/
Kojto	96:487b796308b0	1130
Kojto	96:487b796308b0	1131	/** @defgroup ETH_MAC_Debug_Flags ETH MAC Debug Flags
Kojto	96:487b796308b0	1132	* @{
Kojto	96:487b796308b0	1133	*/
Kojto	96:487b796308b0	1134	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
Kojto	96:487b796308b0	1135	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
Kojto	96:487b796308b0	1136	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
Kojto	96:487b796308b0	1137	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
Kojto	96:487b796308b0	1138	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
Kojto	96:487b796308b0	1139	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
Kojto	96:487b796308b0	1140	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
Kojto	96:487b796308b0	1141	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
Kojto	96:487b796308b0	1142	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
Kojto	96:487b796308b0	1143	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
Kojto	96:487b796308b0	1144	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
Kojto	96:487b796308b0	1145	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
Kojto	96:487b796308b0	1146	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
Kojto	96:487b796308b0	1147	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
Kojto	96:487b796308b0	1148	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
Kojto	96:487b796308b0	1149	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
Kojto	96:487b796308b0	1150	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
Kojto	96:487b796308b0	1151	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
Kojto	96:487b796308b0	1152	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
Kojto	96:487b796308b0	1153	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
Kojto	96:487b796308b0	1154	#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
Kojto	96:487b796308b0	1155	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
Kojto	96:487b796308b0	1156	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
Kojto	96:487b796308b0	1157	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
Kojto	96:487b796308b0	1158	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
Kojto	96:487b796308b0	1159	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
Kojto	96:487b796308b0	1160	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
Kojto	96:487b796308b0	1161
Kojto	96:487b796308b0	1162	/**
Kojto	96:487b796308b0	1163	* @}
Kojto	96:487b796308b0	1164	*/
Kojto	96:487b796308b0	1165
Kojto	96:487b796308b0	1166	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
Kojto	96:487b796308b0	1167	* @{
Kojto	96:487b796308b0	1168	*/
Kojto	96:487b796308b0	1169	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1170	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
Kojto	96:487b796308b0	1171
Kojto	96:487b796308b0	1172	/**
Kojto	96:487b796308b0	1173	* @}
Kojto	96:487b796308b0	1174	*/
Kojto	96:487b796308b0	1175
Kojto	96:487b796308b0	1176	/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
Kojto	96:487b796308b0	1177	* @{
Kojto	96:487b796308b0	1178	*/
Kojto	96:487b796308b0	1179	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
Kojto	96:487b796308b0	1180	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1181
Kojto	96:487b796308b0	1182	/**
Kojto	96:487b796308b0	1183	* @}
Kojto	96:487b796308b0	1184	*/
Kojto	96:487b796308b0	1185
Kojto	96:487b796308b0	1186	/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
Kojto	96:487b796308b0	1187	* @{
Kojto	96:487b796308b0	1188	*/
Kojto	96:487b796308b0	1189	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1190	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
Kojto	96:487b796308b0	1191
Kojto	96:487b796308b0	1192	/**
Kojto	96:487b796308b0	1193	* @}
Kojto	96:487b796308b0	1194	*/
Kojto	96:487b796308b0	1195
Kojto	96:487b796308b0	1196	/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
Kojto	96:487b796308b0	1197	* @{
Kojto	96:487b796308b0	1198	*/
Kojto	96:487b796308b0	1199	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
Kojto	96:487b796308b0	1200	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1201
Kojto	96:487b796308b0	1202	/**
Kojto	96:487b796308b0	1203	* @}
Kojto	96:487b796308b0	1204	*/
Kojto	96:487b796308b0	1205
Kojto	96:487b796308b0	1206	/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
Kojto	96:487b796308b0	1207	* @{
Kojto	96:487b796308b0	1208	*/
Kojto	96:487b796308b0	1209	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
Kojto	96:487b796308b0	1210	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
Kojto	96:487b796308b0	1211	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
Kojto	96:487b796308b0	1212	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
Kojto	96:487b796308b0	1213	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
Kojto	96:487b796308b0	1214	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
Kojto	96:487b796308b0	1215	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
Kojto	96:487b796308b0	1216	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
Kojto	96:487b796308b0	1217
Kojto	96:487b796308b0	1218	/**
Kojto	96:487b796308b0	1219	* @}
Kojto	96:487b796308b0	1220	*/
Kojto	96:487b796308b0	1221
Kojto	96:487b796308b0	1222	/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
Kojto	96:487b796308b0	1223	* @{
Kojto	96:487b796308b0	1224	*/
Kojto	96:487b796308b0	1225	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
Kojto	96:487b796308b0	1226	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1227
Kojto	96:487b796308b0	1228	/**
Kojto	96:487b796308b0	1229	* @}
Kojto	96:487b796308b0	1230	*/
Kojto	96:487b796308b0	1231
Kojto	96:487b796308b0	1232	/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
Kojto	96:487b796308b0	1233	* @{
Kojto	96:487b796308b0	1234	*/
Kojto	96:487b796308b0	1235	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
Kojto	96:487b796308b0	1236	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1237
Kojto	96:487b796308b0	1238	/**
Kojto	96:487b796308b0	1239	* @}
Kojto	96:487b796308b0	1240	*/
Kojto	96:487b796308b0	1241
Kojto	96:487b796308b0	1242	/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
Kojto	96:487b796308b0	1243	* @{
Kojto	96:487b796308b0	1244	*/
Kojto	96:487b796308b0	1245	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
Kojto	96:487b796308b0	1246	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
Kojto	96:487b796308b0	1247	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
Kojto	96:487b796308b0	1248	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
Kojto	96:487b796308b0	1249
Kojto	96:487b796308b0	1250	/**
Kojto	96:487b796308b0	1251	* @}
Kojto	96:487b796308b0	1252	*/
Kojto	96:487b796308b0	1253
Kojto	96:487b796308b0	1254	/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
Kojto	96:487b796308b0	1255	* @{
Kojto	96:487b796308b0	1256	*/
Kojto	96:487b796308b0	1257	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
Kojto	96:487b796308b0	1258	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1259
Kojto	96:487b796308b0	1260	/**
Kojto	96:487b796308b0	1261	* @}
Kojto	96:487b796308b0	1262	*/
Kojto	96:487b796308b0	1263
Kojto	96:487b796308b0	1264	/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
Kojto	96:487b796308b0	1265	* @{
Kojto	96:487b796308b0	1266	*/
Kojto	96:487b796308b0	1267	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
Kojto	96:487b796308b0	1268	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1269
Kojto	96:487b796308b0	1270	/**
Kojto	96:487b796308b0	1271	* @}
Kojto	96:487b796308b0	1272	*/
Kojto	96:487b796308b0	1273
Kojto	96:487b796308b0	1274	/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
Kojto	96:487b796308b0	1275	* @{
Kojto	96:487b796308b0	1276	*/
Kojto	96:487b796308b0	1277	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
Kojto	96:487b796308b0	1278	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1279
Kojto	96:487b796308b0	1280	/**
Kojto	96:487b796308b0	1281	* @}
Kojto	96:487b796308b0	1282	*/
Kojto	96:487b796308b0	1283
Kojto	96:487b796308b0	1284	/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA_Burst Length
Kojto	96:487b796308b0	1285	* @{
Kojto	96:487b796308b0	1286	*/
Kojto	96:487b796308b0	1287	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
Kojto	96:487b796308b0	1288	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
Kojto	96:487b796308b0	1289	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
Kojto	96:487b796308b0	1290	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
Kojto	96:487b796308b0	1291	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
Kojto	96:487b796308b0	1292	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
Kojto	96:487b796308b0	1293	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
Kojto	96:487b796308b0	1294	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
Kojto	96:487b796308b0	1295	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
Kojto	96:487b796308b0	1296	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
Kojto	96:487b796308b0	1297	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
Kojto	96:487b796308b0	1298	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
Kojto	96:487b796308b0	1299
Kojto	96:487b796308b0	1300	/**
Kojto	96:487b796308b0	1301	* @}
Kojto	96:487b796308b0	1302	*/
Kojto	96:487b796308b0	1303
Kojto	96:487b796308b0	1304	/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
Kojto	96:487b796308b0	1305	* @{
Kojto	96:487b796308b0	1306	*/
Kojto	96:487b796308b0	1307	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
Kojto	96:487b796308b0	1308	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
Kojto	96:487b796308b0	1309	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
Kojto	96:487b796308b0	1310	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
Kojto	96:487b796308b0	1311	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
Kojto	96:487b796308b0	1312	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
Kojto	96:487b796308b0	1313	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
Kojto	96:487b796308b0	1314	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
Kojto	96:487b796308b0	1315	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
Kojto	96:487b796308b0	1316	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
Kojto	96:487b796308b0	1317	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
Kojto	96:487b796308b0	1318	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
Kojto	96:487b796308b0	1319
Kojto	96:487b796308b0	1320	/**
Kojto	96:487b796308b0	1321	* @}
Kojto	96:487b796308b0	1322	*/
Kojto	96:487b796308b0	1323
Kojto	96:487b796308b0	1324	/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
Kojto	96:487b796308b0	1325	* @{
Kojto	96:487b796308b0	1326	*/
Kojto	96:487b796308b0	1327	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
Kojto	96:487b796308b0	1328	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
Kojto	96:487b796308b0	1329	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
Kojto	96:487b796308b0	1330	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
Kojto	96:487b796308b0	1331	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
Kojto	96:487b796308b0	1332
Kojto	96:487b796308b0	1333	/**
Kojto	96:487b796308b0	1334	* @}
Kojto	96:487b796308b0	1335	*/
Kojto	96:487b796308b0	1336
Kojto	96:487b796308b0	1337	/** @defgroup ETH_DMA_Tx_Descriptor_Segment ETH DMA Tx Descriptor Segment
Kojto	96:487b796308b0	1338	* @{
Kojto	96:487b796308b0	1339	*/
Kojto	96:487b796308b0	1340	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
Kojto	96:487b796308b0	1341	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
Kojto	96:487b796308b0	1342
Kojto	96:487b796308b0	1343	/**
Kojto	96:487b796308b0	1344	* @}
Kojto	96:487b796308b0	1345	*/
Kojto	96:487b796308b0	1346
Kojto	96:487b796308b0	1347	/** @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control
Kojto	96:487b796308b0	1348	* @{
Kojto	96:487b796308b0	1349	*/
Kojto	96:487b796308b0	1350	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
Kojto	96:487b796308b0	1351	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
Kojto	96:487b796308b0	1352	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
Kojto	96:487b796308b0	1353	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
Kojto	96:487b796308b0	1354
Kojto	96:487b796308b0	1355	/**
Kojto	96:487b796308b0	1356	* @}
Kojto	96:487b796308b0	1357	*/
Kojto	96:487b796308b0	1358
Kojto	96:487b796308b0	1359	/** @defgroup ETH_DMA_Rx_Descriptor_Buffers ETH DMA Rx Descriptor Buffers
Kojto	96:487b796308b0	1360	* @{
Kojto	96:487b796308b0	1361	*/
Kojto	96:487b796308b0	1362	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
Kojto	96:487b796308b0	1363	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
Kojto	96:487b796308b0	1364
Kojto	96:487b796308b0	1365	/**
Kojto	96:487b796308b0	1366	* @}
Kojto	96:487b796308b0	1367	*/
Kojto	96:487b796308b0	1368
Kojto	96:487b796308b0	1369	/** @defgroup ETH_PMT_Flags ETH PMT Flags
Kojto	96:487b796308b0	1370	* @{
Kojto	96:487b796308b0	1371	*/
Kojto	96:487b796308b0	1372	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
Kojto	96:487b796308b0	1373	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
Kojto	96:487b796308b0	1374	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
Kojto	96:487b796308b0	1375
Kojto	96:487b796308b0	1376	/**
Kojto	96:487b796308b0	1377	* @}
Kojto	96:487b796308b0	1378	*/
Kojto	96:487b796308b0	1379
Kojto	96:487b796308b0	1380	/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
Kojto	96:487b796308b0	1381	* @{
Kojto	96:487b796308b0	1382	*/
Kojto	96:487b796308b0	1383	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
Kojto	96:487b796308b0	1384	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
Kojto	96:487b796308b0	1385	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
Kojto	96:487b796308b0	1386
Kojto	96:487b796308b0	1387	/**
Kojto	96:487b796308b0	1388	* @}
Kojto	96:487b796308b0	1389	*/
Kojto	96:487b796308b0	1390
Kojto	96:487b796308b0	1391	/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
Kojto	96:487b796308b0	1392	* @{
Kojto	96:487b796308b0	1393	*/
Kojto	96:487b796308b0	1394	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
Kojto	96:487b796308b0	1395	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
Kojto	96:487b796308b0	1396	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
Kojto	96:487b796308b0	1397
Kojto	96:487b796308b0	1398	/**
Kojto	96:487b796308b0	1399	* @}
Kojto	96:487b796308b0	1400	*/
Kojto	96:487b796308b0	1401
Kojto	96:487b796308b0	1402	/** @defgroup ETH_MAC_Flags ETH MAC Flags
Kojto	96:487b796308b0	1403	* @{
Kojto	96:487b796308b0	1404	*/
Kojto	96:487b796308b0	1405	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
Kojto	96:487b796308b0	1406	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
Kojto	96:487b796308b0	1407	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
Kojto	96:487b796308b0	1408	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
Kojto	96:487b796308b0	1409	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
Kojto	96:487b796308b0	1410
Kojto	96:487b796308b0	1411	/**
Kojto	96:487b796308b0	1412	* @}
Kojto	96:487b796308b0	1413	*/
Kojto	96:487b796308b0	1414
Kojto	96:487b796308b0	1415	/** @defgroup ETH_DMA_Flags ETH DMA Flags
Kojto	96:487b796308b0	1416	* @{
Kojto	96:487b796308b0	1417	*/
Kojto	96:487b796308b0	1418	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
Kojto	96:487b796308b0	1419	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
Kojto	96:487b796308b0	1420	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
Kojto	96:487b796308b0	1421	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
Kojto	96:487b796308b0	1422	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write trnsf, 1-read transfr /
Kojto	96:487b796308b0	1423	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
Kojto	96:487b796308b0	1424	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
Kojto	96:487b796308b0	1425	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
Kojto	96:487b796308b0	1426	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
Kojto	96:487b796308b0	1427	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
Kojto	96:487b796308b0	1428	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
Kojto	96:487b796308b0	1429	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
Kojto	96:487b796308b0	1430	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
Kojto	96:487b796308b0	1431	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
Kojto	96:487b796308b0	1432	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
Kojto	96:487b796308b0	1433	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
Kojto	96:487b796308b0	1434	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
Kojto	96:487b796308b0	1435	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
Kojto	96:487b796308b0	1436	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
Kojto	96:487b796308b0	1437	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
Kojto	96:487b796308b0	1438	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
Kojto	96:487b796308b0	1439
Kojto	96:487b796308b0	1440	/**
Kojto	96:487b796308b0	1441	* @}
Kojto	96:487b796308b0	1442	*/
Kojto	96:487b796308b0	1443
Kojto	96:487b796308b0	1444	/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
Kojto	96:487b796308b0	1445	* @{
Kojto	96:487b796308b0	1446	*/
Kojto	96:487b796308b0	1447	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
Kojto	96:487b796308b0	1448	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
Kojto	96:487b796308b0	1449	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
Kojto	96:487b796308b0	1450	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
Kojto	96:487b796308b0	1451	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
Kojto	96:487b796308b0	1452
Kojto	96:487b796308b0	1453	/**
Kojto	96:487b796308b0	1454	* @}
Kojto	96:487b796308b0	1455	*/
Kojto	96:487b796308b0	1456
Kojto	96:487b796308b0	1457	/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
Kojto	96:487b796308b0	1458	* @{
Kojto	96:487b796308b0	1459	*/
Kojto	96:487b796308b0	1460	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
Kojto	96:487b796308b0	1461	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
Kojto	96:487b796308b0	1462	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
Kojto	96:487b796308b0	1463	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
Kojto	96:487b796308b0	1464	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
Kojto	96:487b796308b0	1465	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
Kojto	96:487b796308b0	1466	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
Kojto	96:487b796308b0	1467	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
Kojto	96:487b796308b0	1468	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
Kojto	96:487b796308b0	1469	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
Kojto	96:487b796308b0	1470	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
Kojto	96:487b796308b0	1471	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
Kojto	96:487b796308b0	1472	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
Kojto	96:487b796308b0	1473	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
Kojto	96:487b796308b0	1474	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
Kojto	96:487b796308b0	1475	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
Kojto	96:487b796308b0	1476	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
Kojto	96:487b796308b0	1477	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
Kojto	96:487b796308b0	1478
Kojto	96:487b796308b0	1479	/**
Kojto	96:487b796308b0	1480	* @}
Kojto	96:487b796308b0	1481	*/
Kojto	96:487b796308b0	1482
Kojto	96:487b796308b0	1483	/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
Kojto	96:487b796308b0	1484	* @{
Kojto	96:487b796308b0	1485	*/
Kojto	96:487b796308b0	1486	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
Kojto	96:487b796308b0	1487	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
Kojto	96:487b796308b0	1488	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
Kojto	96:487b796308b0	1489	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
Kojto	96:487b796308b0	1490	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
Kojto	96:487b796308b0	1491	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
Kojto	96:487b796308b0	1492
Kojto	96:487b796308b0	1493	/**
Kojto	96:487b796308b0	1494	* @}
Kojto	96:487b796308b0	1495	*/
Kojto	96:487b796308b0	1496
Kojto	96:487b796308b0	1497
Kojto	96:487b796308b0	1498	/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
Kojto	96:487b796308b0	1499	* @{
Kojto	96:487b796308b0	1500	*/
Kojto	96:487b796308b0	1501	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
Kojto	96:487b796308b0	1502	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
Kojto	96:487b796308b0	1503	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
Kojto	96:487b796308b0	1504	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
Kojto	96:487b796308b0	1505	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
Kojto	96:487b796308b0	1506	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
Kojto	96:487b796308b0	1507
Kojto	96:487b796308b0	1508	/**
Kojto	96:487b796308b0	1509	* @}
Kojto	96:487b796308b0	1510	*/
Kojto	96:487b796308b0	1511
Kojto	96:487b796308b0	1512	/** @defgroup ETH_DMA_overflow ETH DMA overflow
Kojto	96:487b796308b0	1513	* @{
Kojto	96:487b796308b0	1514	*/
Kojto	96:487b796308b0	1515	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
Kojto	96:487b796308b0	1516	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
Kojto	96:487b796308b0	1517
Kojto	96:487b796308b0	1518	/**
Kojto	96:487b796308b0	1519	* @}
Kojto	96:487b796308b0	1520	*/
Kojto	96:487b796308b0	1521
Kojto	96:487b796308b0	1522	/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
Kojto	96:487b796308b0	1523	* @{
Kojto	96:487b796308b0	1524	*/
Kojto	96:487b796308b0	1525	#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /!< External interrupt line 19 Connected to the ETH EXTI Line /
Kojto	96:487b796308b0	1526
Kojto	96:487b796308b0	1527	/**
Kojto	96:487b796308b0	1528	* @}
Kojto	96:487b796308b0	1529	*/
Kojto	96:487b796308b0	1530
Kojto	96:487b796308b0	1531	/**
Kojto	96:487b796308b0	1532	* @}
Kojto	96:487b796308b0	1533	*/
Kojto	96:487b796308b0	1534
Kojto	96:487b796308b0	1535	/* Exported macro ------------------------------------------------------------*/
Kojto	96:487b796308b0	1536	/** @defgroup ETH_Exported_Macros ETH Exported Macros
Kojto	96:487b796308b0	1537	* @brief macros to handle interrupts and specific clock configurations
Kojto	96:487b796308b0	1538	* @{
Kojto	96:487b796308b0	1539	*/
Kojto	96:487b796308b0	1540
Kojto	96:487b796308b0	1541	/** @brief Reset ETH handle state
Kojto	96:487b796308b0	1542	* @param __HANDLE__: specifies the ETH handle.
Kojto	96:487b796308b0	1543	* @retval None
Kojto	96:487b796308b0	1544	*/
Kojto	96:487b796308b0	1545	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
Kojto	96:487b796308b0	1546
Kojto	96:487b796308b0	1547	/**
Kojto	96:487b796308b0	1548	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
Kojto	96:487b796308b0	1549	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1550	* @param __FLAG__: specifies the flag of TDES0 to check .
Kojto	96:487b796308b0	1551	* @retval the ETH_DMATxDescFlag (SET or RESET).
Kojto	96:487b796308b0	1552	*/
Kojto	96:487b796308b0	1553	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
Kojto	96:487b796308b0	1554
Kojto	96:487b796308b0	1555	/**
Kojto	96:487b796308b0	1556	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
Kojto	96:487b796308b0	1557	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1558	* @param __FLAG__: specifies the flag of RDES0 to check.
Kojto	96:487b796308b0	1559	* @retval the ETH_DMATxDescFlag (SET or RESET).
Kojto	96:487b796308b0	1560	*/
Kojto	96:487b796308b0	1561	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
Kojto	96:487b796308b0	1562
Kojto	96:487b796308b0	1563	/**
Kojto	96:487b796308b0	1564	* @brief Enables the specified DMA Rx Desc receive interrupt.
Kojto	96:487b796308b0	1565	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1566	* @retval None
Kojto	96:487b796308b0	1567	*/
Kojto	96:487b796308b0	1568	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
Kojto	96:487b796308b0	1569
Kojto	96:487b796308b0	1570	/**
Kojto	96:487b796308b0	1571	* @brief Disables the specified DMA Rx Desc receive interrupt.
Kojto	96:487b796308b0	1572	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1573	* @retval None
Kojto	96:487b796308b0	1574	*/
Kojto	96:487b796308b0	1575	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
Kojto	96:487b796308b0	1576
Kojto	96:487b796308b0	1577	/**
Kojto	96:487b796308b0	1578	* @brief Set the specified DMA Rx Desc Own bit.
Kojto	96:487b796308b0	1579	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1580	* @retval None
Kojto	96:487b796308b0	1581	*/
Kojto	96:487b796308b0	1582	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
Kojto	96:487b796308b0	1583
Kojto	96:487b796308b0	1584	/**
Kojto	96:487b796308b0	1585	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
Kojto	96:487b796308b0	1586	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1587	* @retval The Transmit descriptor collision counter value.
Kojto	96:487b796308b0	1588	*/
Kojto	96:487b796308b0	1589	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
Kojto	96:487b796308b0	1590
Kojto	96:487b796308b0	1591	/**
Kojto	96:487b796308b0	1592	* @brief Set the specified DMA Tx Desc Own bit.
Kojto	96:487b796308b0	1593	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1594	* @retval None
Kojto	96:487b796308b0	1595	*/
Kojto	96:487b796308b0	1596	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
Kojto	96:487b796308b0	1597
Kojto	96:487b796308b0	1598	/**
Kojto	96:487b796308b0	1599	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
Kojto	96:487b796308b0	1600	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1601	* @retval None
Kojto	96:487b796308b0	1602	*/
Kojto	96:487b796308b0	1603	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
Kojto	96:487b796308b0	1604
Kojto	96:487b796308b0	1605	/**
Kojto	96:487b796308b0	1606	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
Kojto	96:487b796308b0	1607	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1608	* @retval None
Kojto	96:487b796308b0	1609	*/
Kojto	96:487b796308b0	1610	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
Kojto	96:487b796308b0	1611
Kojto	96:487b796308b0	1612	/**
Kojto	96:487b796308b0	1613	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
Kojto	96:487b796308b0	1614	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1615	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
Kojto	96:487b796308b0	1616	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1617	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
Kojto	96:487b796308b0	1618	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
Kojto	96:487b796308b0	1619	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
Kojto	96:487b796308b0	1620	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
Kojto	96:487b796308b0	1621	* @retval None
Kojto	96:487b796308b0	1622	*/
Kojto	96:487b796308b0	1623	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
Kojto	96:487b796308b0	1624
Kojto	96:487b796308b0	1625	/**
Kojto	96:487b796308b0	1626	* @brief Enables the DMA Tx Desc CRC.
Kojto	96:487b796308b0	1627	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1628	* @retval None
Kojto	96:487b796308b0	1629	*/
Kojto	96:487b796308b0	1630	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
Kojto	96:487b796308b0	1631
Kojto	96:487b796308b0	1632	/**
Kojto	96:487b796308b0	1633	* @brief Disables the DMA Tx Desc CRC.
Kojto	96:487b796308b0	1634	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1635	* @retval None
Kojto	96:487b796308b0	1636	*/
Kojto	96:487b796308b0	1637	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
Kojto	96:487b796308b0	1638
Kojto	96:487b796308b0	1639	/**
Kojto	96:487b796308b0	1640	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
Kojto	96:487b796308b0	1641	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1642	* @retval None
Kojto	96:487b796308b0	1643	*/
Kojto	96:487b796308b0	1644	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
Kojto	96:487b796308b0	1645
Kojto	96:487b796308b0	1646	/**
Kojto	96:487b796308b0	1647	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
Kojto	96:487b796308b0	1648	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1649	* @retval None
Kojto	96:487b796308b0	1650	*/
Kojto	96:487b796308b0	1651	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
Kojto	96:487b796308b0	1652
Kojto	96:487b796308b0	1653	/**
Kojto	96:487b796308b0	1654	* @brief Enables the specified ETHERNET MAC interrupts.
Kojto	96:487b796308b0	1655	* @param __HANDLE__ : ETH Handle
Kojto	96:487b796308b0	1656	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
Kojto	96:487b796308b0	1657	* enabled or disabled.
Kojto	96:487b796308b0	1658	* This parameter can be any combination of the following values:
Kojto	96:487b796308b0	1659	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
Kojto	96:487b796308b0	1660	* @arg ETH_MAC_IT_PMT : PMT interrupt
Kojto	96:487b796308b0	1661	* @retval None
Kojto	96:487b796308b0	1662	*/
Kojto	96:487b796308b0	1663	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
Kojto	96:487b796308b0	1664
Kojto	96:487b796308b0	1665	/**
Kojto	96:487b796308b0	1666	* @brief Disables the specified ETHERNET MAC interrupts.
Kojto	96:487b796308b0	1667	* @param __HANDLE__ : ETH Handle
Kojto	96:487b796308b0	1668	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
Kojto	96:487b796308b0	1669	* enabled or disabled.
Kojto	96:487b796308b0	1670	* This parameter can be any combination of the following values:
Kojto	96:487b796308b0	1671	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
Kojto	96:487b796308b0	1672	* @arg ETH_MAC_IT_PMT : PMT interrupt
Kojto	96:487b796308b0	1673	* @retval None
Kojto	96:487b796308b0	1674	*/
Kojto	96:487b796308b0	1675	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
Kojto	96:487b796308b0	1676
Kojto	96:487b796308b0	1677	/**
Kojto	96:487b796308b0	1678	* @brief Initiate a Pause Control Frame (Full-duplex only).
Kojto	96:487b796308b0	1679	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1680	* @retval None
Kojto	96:487b796308b0	1681	*/
Kojto	96:487b796308b0	1682	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
Kojto	96:487b796308b0	1683
Kojto	96:487b796308b0	1684	/**
Kojto	96:487b796308b0	1685	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
Kojto	96:487b796308b0	1686	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1687	* @retval The new state of flow control busy status bit (SET or RESET).
Kojto	96:487b796308b0	1688	*/
Kojto	96:487b796308b0	1689	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
Kojto	96:487b796308b0	1690
Kojto	96:487b796308b0	1691	/**
Kojto	96:487b796308b0	1692	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
Kojto	96:487b796308b0	1693	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1694	* @retval None
Kojto	96:487b796308b0	1695	*/
Kojto	96:487b796308b0	1696	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
Kojto	96:487b796308b0	1697
Kojto	96:487b796308b0	1698	/**
Kojto	96:487b796308b0	1699	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
Kojto	96:487b796308b0	1700	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1701	* @retval None
Kojto	96:487b796308b0	1702	*/
Kojto	96:487b796308b0	1703	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
Kojto	96:487b796308b0	1704
Kojto	96:487b796308b0	1705	/**
Kojto	96:487b796308b0	1706	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
Kojto	96:487b796308b0	1707	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1708	* @param __FLAG__: specifies the flag to check.
Kojto	96:487b796308b0	1709	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1710	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
Kojto	96:487b796308b0	1711	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
Kojto	96:487b796308b0	1712	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
Kojto	96:487b796308b0	1713	* @arg ETH_MAC_FLAG_MMC : MMC flag
Kojto	96:487b796308b0	1714	* @arg ETH_MAC_FLAG_PMT : PMT flag
Kojto	96:487b796308b0	1715	* @retval The state of ETHERNET MAC flag.
Kojto	96:487b796308b0	1716	*/
Kojto	96:487b796308b0	1717	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
Kojto	96:487b796308b0	1718
Kojto	96:487b796308b0	1719	/**
Kojto	96:487b796308b0	1720	* @brief Enables the specified ETHERNET DMA interrupts.
Kojto	96:487b796308b0	1721	* @param __HANDLE__ : ETH Handle
Kojto	96:487b796308b0	1722	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto	96:487b796308b0	1723	* enabled @ref ETH_DMA_Interrupts
Kojto	96:487b796308b0	1724	* @retval None
Kojto	96:487b796308b0	1725	*/
Kojto	96:487b796308b0	1726	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
Kojto	96:487b796308b0	1727
Kojto	96:487b796308b0	1728	/**
Kojto	96:487b796308b0	1729	* @brief Disables the specified ETHERNET DMA interrupts.
Kojto	96:487b796308b0	1730	* @param __HANDLE__ : ETH Handle
Kojto	96:487b796308b0	1731	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto	96:487b796308b0	1732	* disabled. @ref ETH_DMA_Interrupts
Kojto	96:487b796308b0	1733	* @retval None
Kojto	96:487b796308b0	1734	*/
Kojto	96:487b796308b0	1735	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
Kojto	96:487b796308b0	1736
Kojto	96:487b796308b0	1737	/**
Kojto	96:487b796308b0	1738	* @brief Clears the ETHERNET DMA IT pending bit.
Kojto	96:487b796308b0	1739	* @param __HANDLE__ : ETH Handle
Kojto	96:487b796308b0	1740	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
Kojto	96:487b796308b0	1741	* @retval None
Kojto	96:487b796308b0	1742	*/
Kojto	96:487b796308b0	1743	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
Kojto	96:487b796308b0	1744
Kojto	96:487b796308b0	1745	/**
Kojto	96:487b796308b0	1746	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
Kojto	96:487b796308b0	1747	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1748	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
Kojto	96:487b796308b0	1749	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
Kojto	96:487b796308b0	1750	*/
Kojto	96:487b796308b0	1751	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
Kojto	96:487b796308b0	1752
Kojto	96:487b796308b0	1753	/**
Kojto	96:487b796308b0	1754	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
Kojto	96:487b796308b0	1755	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1756	* @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
Kojto	96:487b796308b0	1757	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
Kojto	96:487b796308b0	1758	*/
Kojto	96:487b796308b0	1759	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
Kojto	96:487b796308b0	1760
Kojto	96:487b796308b0	1761	/**
Kojto	96:487b796308b0	1762	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
Kojto	96:487b796308b0	1763	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1764	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
Kojto	96:487b796308b0	1765	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1766	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
Kojto	96:487b796308b0	1767	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
Kojto	96:487b796308b0	1768	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
Kojto	96:487b796308b0	1769	*/
Kojto	96:487b796308b0	1770	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
Kojto	96:487b796308b0	1771
Kojto	96:487b796308b0	1772	/**
Kojto	96:487b796308b0	1773	* @brief Set the DMA Receive status watchdog timer register value
Kojto	96:487b796308b0	1774	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1775	* @param __VALUE__: DMA Receive status watchdog timer register value
Kojto	96:487b796308b0	1776	* @retval None
Kojto	96:487b796308b0	1777	*/
Kojto	96:487b796308b0	1778	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
Kojto	96:487b796308b0	1779
Kojto	96:487b796308b0	1780	/**
Kojto	96:487b796308b0	1781	* @brief Enables any unicast packet filtered by the MAC address
Kojto	96:487b796308b0	1782	* recognition to be a wake-up frame.
Kojto	96:487b796308b0	1783	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1784	* @retval None
Kojto	96:487b796308b0	1785	*/
Kojto	96:487b796308b0	1786	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
Kojto	96:487b796308b0	1787
Kojto	96:487b796308b0	1788	/**
Kojto	96:487b796308b0	1789	* @brief Disables any unicast packet filtered by the MAC address
Kojto	96:487b796308b0	1790	* recognition to be a wake-up frame.
Kojto	96:487b796308b0	1791	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1792	* @retval None
Kojto	96:487b796308b0	1793	*/
Kojto	96:487b796308b0	1794	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
Kojto	96:487b796308b0	1795
Kojto	96:487b796308b0	1796	/**
Kojto	96:487b796308b0	1797	* @brief Enables the MAC Wake-Up Frame Detection.
Kojto	96:487b796308b0	1798	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1799	* @retval None
Kojto	96:487b796308b0	1800	*/
Kojto	96:487b796308b0	1801	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
Kojto	96:487b796308b0	1802
Kojto	96:487b796308b0	1803	/**
Kojto	96:487b796308b0	1804	* @brief Disables the MAC Wake-Up Frame Detection.
Kojto	96:487b796308b0	1805	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1806	* @retval None
Kojto	96:487b796308b0	1807	*/
Kojto	96:487b796308b0	1808	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Kojto	96:487b796308b0	1809
Kojto	96:487b796308b0	1810	/**
Kojto	96:487b796308b0	1811	* @brief Enables the MAC Magic Packet Detection.
Kojto	96:487b796308b0	1812	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1813	* @retval None
Kojto	96:487b796308b0	1814	*/
Kojto	96:487b796308b0	1815	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
Kojto	96:487b796308b0	1816
Kojto	96:487b796308b0	1817	/**
Kojto	96:487b796308b0	1818	* @brief Disables the MAC Magic Packet Detection.
Kojto	96:487b796308b0	1819	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1820	* @retval None
Kojto	96:487b796308b0	1821	*/
Kojto	96:487b796308b0	1822	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Kojto	96:487b796308b0	1823
Kojto	96:487b796308b0	1824	/**
Kojto	96:487b796308b0	1825	* @brief Enables the MAC Power Down.
Kojto	96:487b796308b0	1826	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1827	* @retval None
Kojto	96:487b796308b0	1828	*/
Kojto	96:487b796308b0	1829	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
Kojto	96:487b796308b0	1830
Kojto	96:487b796308b0	1831	/**
Kojto	96:487b796308b0	1832	* @brief Disables the MAC Power Down.
Kojto	96:487b796308b0	1833	* @param __HANDLE__: ETH Handle
Kojto	96:487b796308b0	1834	* @retval None
Kojto	96:487b796308b0	1835	*/
Kojto	96:487b796308b0	1836	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
Kojto	96:487b796308b0	1837
Kojto	96:487b796308b0	1838	/**
Kojto	96:487b796308b0	1839	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
Kojto	96:487b796308b0	1840	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1841	* @param __FLAG__: specifies the flag to check.
Kojto	96:487b796308b0	1842	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1843	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
Kojto	96:487b796308b0	1844	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
Kojto	96:487b796308b0	1845	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
Kojto	96:487b796308b0	1846	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
Kojto	96:487b796308b0	1847	*/
Kojto	96:487b796308b0	1848	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
Kojto	96:487b796308b0	1849
Kojto	96:487b796308b0	1850	/**
Kojto	96:487b796308b0	1851	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
Kojto	96:487b796308b0	1852	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1853	* @retval None
Kojto	96:487b796308b0	1854	*/
Kojto	96:487b796308b0	1855	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
Kojto	96:487b796308b0	1856
Kojto	96:487b796308b0	1857	/**
Kojto	96:487b796308b0	1858	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
Kojto	96:487b796308b0	1859	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1860	* @retval None
Kojto	96:487b796308b0	1861	*/
Kojto	96:487b796308b0	1862	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
Kojto	96:487b796308b0	1863	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
Kojto	96:487b796308b0	1864
Kojto	96:487b796308b0	1865	/**
Kojto	96:487b796308b0	1866	* @brief Enables the MMC Counter Freeze.
Kojto	96:487b796308b0	1867	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1868	* @retval None
Kojto	96:487b796308b0	1869	*/
Kojto	96:487b796308b0	1870	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
Kojto	96:487b796308b0	1871
Kojto	96:487b796308b0	1872	/**
Kojto	96:487b796308b0	1873	* @brief Disables the MMC Counter Freeze.
Kojto	96:487b796308b0	1874	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1875	* @retval None
Kojto	96:487b796308b0	1876	*/
Kojto	96:487b796308b0	1877	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
Kojto	96:487b796308b0	1878
Kojto	96:487b796308b0	1879	/**
Kojto	96:487b796308b0	1880	* @brief Enables the MMC Reset On Read.
Kojto	96:487b796308b0	1881	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1882	* @retval None
Kojto	96:487b796308b0	1883	*/
Kojto	96:487b796308b0	1884	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
Kojto	96:487b796308b0	1885
Kojto	96:487b796308b0	1886	/**
Kojto	96:487b796308b0	1887	* @brief Disables the MMC Reset On Read.
Kojto	96:487b796308b0	1888	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1889	* @retval None
Kojto	96:487b796308b0	1890	*/
Kojto	96:487b796308b0	1891	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
Kojto	96:487b796308b0	1892
Kojto	96:487b796308b0	1893	/**
Kojto	96:487b796308b0	1894	* @brief Enables the MMC Counter Stop Rollover.
Kojto	96:487b796308b0	1895	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1896	* @retval None
Kojto	96:487b796308b0	1897	*/
Kojto	96:487b796308b0	1898	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
Kojto	96:487b796308b0	1899
Kojto	96:487b796308b0	1900	/**
Kojto	96:487b796308b0	1901	* @brief Disables the MMC Counter Stop Rollover.
Kojto	96:487b796308b0	1902	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1903	* @retval None
Kojto	96:487b796308b0	1904	*/
Kojto	96:487b796308b0	1905	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
Kojto	96:487b796308b0	1906
Kojto	96:487b796308b0	1907	/**
Kojto	96:487b796308b0	1908	* @brief Resets the MMC Counters.
Kojto	96:487b796308b0	1909	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1910	* @retval None
Kojto	96:487b796308b0	1911	*/
Kojto	96:487b796308b0	1912	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
Kojto	96:487b796308b0	1913
Kojto	96:487b796308b0	1914	/**
Kojto	96:487b796308b0	1915	* @brief Enables the specified ETHERNET MMC Rx interrupts.
Kojto	96:487b796308b0	1916	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1917	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	96:487b796308b0	1918	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1919	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
Kojto	96:487b796308b0	1920	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
Kojto	96:487b796308b0	1921	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Kojto	96:487b796308b0	1922	* @retval None
Kojto	96:487b796308b0	1923	*/
Kojto	96:487b796308b0	1924	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
Kojto	96:487b796308b0	1925	/**
Kojto	96:487b796308b0	1926	* @brief Disables the specified ETHERNET MMC Rx interrupts.
Kojto	96:487b796308b0	1927	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1928	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	96:487b796308b0	1929	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1930	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
Kojto	96:487b796308b0	1931	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
Kojto	96:487b796308b0	1932	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Kojto	96:487b796308b0	1933	* @retval None
Kojto	96:487b796308b0	1934	*/
Kojto	96:487b796308b0	1935	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
Kojto	96:487b796308b0	1936	/**
Kojto	96:487b796308b0	1937	* @brief Enables the specified ETHERNET MMC Tx interrupts.
Kojto	96:487b796308b0	1938	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1939	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	96:487b796308b0	1940	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1941	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
Kojto	96:487b796308b0	1942	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
Kojto	96:487b796308b0	1943	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Kojto	96:487b796308b0	1944	* @retval None
Kojto	96:487b796308b0	1945	*/
Kojto	96:487b796308b0	1946	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
Kojto	96:487b796308b0	1947
Kojto	96:487b796308b0	1948	/**
Kojto	96:487b796308b0	1949	* @brief Disables the specified ETHERNET MMC Tx interrupts.
Kojto	96:487b796308b0	1950	* @param __HANDLE__: ETH Handle.
Kojto	96:487b796308b0	1951	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto	96:487b796308b0	1952	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1953	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
Kojto	96:487b796308b0	1954	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
Kojto	96:487b796308b0	1955	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Kojto	96:487b796308b0	1956	* @retval None
Kojto	96:487b796308b0	1957	*/
Kojto	96:487b796308b0	1958	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
Kojto	96:487b796308b0	1959
Kojto	96:487b796308b0	1960	/**
Kojto	96:487b796308b0	1961	* @brief Enables the ETH External interrupt line.
Kojto	96:487b796308b0	1962	* @retval None
Kojto	96:487b796308b0	1963	*/
Kojto	96:487b796308b0	1964	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
Kojto	96:487b796308b0	1965
Kojto	96:487b796308b0	1966	/**
Kojto	96:487b796308b0	1967	* @brief Disables the ETH External interrupt line.
Kojto	96:487b796308b0	1968	* @retval None
Kojto	96:487b796308b0	1969	*/
Kojto	96:487b796308b0	1970	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	96:487b796308b0	1971
Kojto	96:487b796308b0	1972	/**
Kojto	96:487b796308b0	1973	* @brief Enable event on ETH External event line.
Kojto	96:487b796308b0	1974	* @retval None.
Kojto	96:487b796308b0	1975	*/
Kojto	96:487b796308b0	1976	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR \|= (ETH_EXTI_LINE_WAKEUP)
Kojto	96:487b796308b0	1977
Kojto	96:487b796308b0	1978	/**
Kojto	96:487b796308b0	1979	* @brief Disable event on ETH External event line
Kojto	96:487b796308b0	1980	* @retval None.
Kojto	96:487b796308b0	1981	*/
Kojto	96:487b796308b0	1982	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	96:487b796308b0	1983
Kojto	96:487b796308b0	1984	/**
Kojto	96:487b796308b0	1985	* @brief Get flag of the ETH External interrupt line.
Kojto	96:487b796308b0	1986	* @retval None
Kojto	96:487b796308b0	1987	*/
Kojto	96:487b796308b0	1988	#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
Kojto	96:487b796308b0	1989
Kojto	96:487b796308b0	1990	/**
Kojto	96:487b796308b0	1991	* @brief Clear flag of the ETH External interrupt line.
Kojto	96:487b796308b0	1992	* @retval None
Kojto	96:487b796308b0	1993	*/
Kojto	96:487b796308b0	1994	#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
Kojto	96:487b796308b0	1995
Kojto	96:487b796308b0	1996	/**
Kojto	96:487b796308b0	1997	* @brief Enables rising edge trigger to the ETH External interrupt line.
Kojto	96:487b796308b0	1998	* @retval None
Kojto	96:487b796308b0	1999	*/
Kojto	96:487b796308b0	2000	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
Kojto	96:487b796308b0	2001
Kojto	96:487b796308b0	2002	/**
Kojto	96:487b796308b0	2003	* @brief Disables the rising edge trigger to the ETH External interrupt line.
Kojto	96:487b796308b0	2004	* @retval None
Kojto	96:487b796308b0	2005	*/
Kojto	96:487b796308b0	2006	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	96:487b796308b0	2007
Kojto	96:487b796308b0	2008	/**
Kojto	96:487b796308b0	2009	* @brief Enables falling edge trigger to the ETH External interrupt line.
Kojto	96:487b796308b0	2010	* @retval None
Kojto	96:487b796308b0	2011	*/
Kojto	96:487b796308b0	2012	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP)
Kojto	96:487b796308b0	2013
Kojto	96:487b796308b0	2014	/**
Kojto	96:487b796308b0	2015	* @brief Disables falling edge trigger to the ETH External interrupt line.
Kojto	96:487b796308b0	2016	* @retval None
Kojto	96:487b796308b0	2017	*/
Kojto	96:487b796308b0	2018	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	96:487b796308b0	2019
Kojto	96:487b796308b0	2020
Kojto	96:487b796308b0	2021	/**
Kojto	96:487b796308b0	2022	* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
Kojto	96:487b796308b0	2023	* @retval None
Kojto	96:487b796308b0	2024	*/
Kojto	96:487b796308b0	2025	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
Kojto	96:487b796308b0	2026	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP
Kojto	96:487b796308b0	2027
Kojto	96:487b796308b0	2028	/**
Kojto	96:487b796308b0	2029	* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
Kojto	96:487b796308b0	2030	* @retval None
Kojto	96:487b796308b0	2031	*/
Kojto	96:487b796308b0	2032	#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
Kojto	96:487b796308b0	2033	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto	96:487b796308b0	2034
Kojto	96:487b796308b0	2035	/**
Kojto	96:487b796308b0	2036	* @brief Generate a Software interrupt on selected EXTI line.
Kojto	96:487b796308b0	2037	* @retval None.
Kojto	96:487b796308b0	2038	*/
Kojto	96:487b796308b0	2039	#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER\|= ETH_EXTI_LINE_WAKEUP
Kojto	96:487b796308b0	2040
Kojto	96:487b796308b0	2041	/**
Kojto	96:487b796308b0	2042	* @}
Kojto	96:487b796308b0	2043	*/
Kojto	96:487b796308b0	2044
Kojto	96:487b796308b0	2045	/* Exported functions --------------------------------------------------------*/
Kojto	96:487b796308b0	2046
Kojto	96:487b796308b0	2047	/** @addtogroup ETH_Exported_Functions
Kojto	96:487b796308b0	2048	* @{
Kojto	96:487b796308b0	2049	*/
Kojto	96:487b796308b0	2050
Kojto	96:487b796308b0	2051	/* Initialization and de-initialization functions ****************************/
Kojto	96:487b796308b0	2052
Kojto	96:487b796308b0	2053	/** @addtogroup ETH_Exported_Functions_Group1
Kojto	96:487b796308b0	2054	* @{
Kojto	96:487b796308b0	2055	*/
Kojto	96:487b796308b0	2056
Kojto	96:487b796308b0	2057	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2058	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2059	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2060	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2061	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
Kojto	96:487b796308b0	2062	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
Kojto	96:487b796308b0	2063
Kojto	96:487b796308b0	2064	/**
Kojto	96:487b796308b0	2065	* @}
Kojto	96:487b796308b0	2066	*/
Kojto	96:487b796308b0	2067
Kojto	96:487b796308b0	2068	/* IO operation functions ****************************************************/
Kojto	96:487b796308b0	2069
Kojto	96:487b796308b0	2070	/** @addtogroup ETH_Exported_Functions_Group2
Kojto	96:487b796308b0	2071	* @{
Kojto	96:487b796308b0	2072	*/
Kojto	96:487b796308b0	2073	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
Kojto	96:487b796308b0	2074	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2075	/* Communication with PHY functions*/
Kojto	96:487b796308b0	2076	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
Kojto	96:487b796308b0	2077	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
Kojto	96:487b796308b0	2078	/* Non-Blocking mode: Interrupt */
Kojto	96:487b796308b0	2079	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2080	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2081	/* Callback in non blocking modes (Interrupt) */
Kojto	96:487b796308b0	2082	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2083	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2084	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2085
Kojto	96:487b796308b0	2086	/**
Kojto	96:487b796308b0	2087	* @}
Kojto	96:487b796308b0	2088	*/
Kojto	96:487b796308b0	2089
Kojto	96:487b796308b0	2090	/* Peripheral Control functions **********************************************/
Kojto	96:487b796308b0	2091
Kojto	96:487b796308b0	2092	/** @addtogroup ETH_Exported_Functions_Group3
Kojto	96:487b796308b0	2093	* @{
Kojto	96:487b796308b0	2094	*/
Kojto	96:487b796308b0	2095	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2096	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2097	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
Kojto	96:487b796308b0	2098	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
Kojto	96:487b796308b0	2099	/**
Kojto	96:487b796308b0	2100	* @}
Kojto	96:487b796308b0	2101	*/
Kojto	96:487b796308b0	2102
Kojto	96:487b796308b0	2103	/* Peripheral State functions ************************************************/
Kojto	96:487b796308b0	2104
Kojto	96:487b796308b0	2105	/** @addtogroup ETH_Exported_Functions_Group4
Kojto	96:487b796308b0	2106	* @{
Kojto	96:487b796308b0	2107	*/
Kojto	96:487b796308b0	2108	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
Kojto	96:487b796308b0	2109
Kojto	96:487b796308b0	2110	/**
Kojto	96:487b796308b0	2111	* @}
Kojto	96:487b796308b0	2112	*/
Kojto	96:487b796308b0	2113
Kojto	96:487b796308b0	2114	/**
Kojto	96:487b796308b0	2115	* @}
Kojto	96:487b796308b0	2116	*/
Kojto	96:487b796308b0	2117
Kojto	96:487b796308b0	2118	/**
Kojto	96:487b796308b0	2119	* @}
Kojto	96:487b796308b0	2120	*/
Kojto	96:487b796308b0	2121
Kojto	96:487b796308b0	2122	#endif /* STM32F107xC */
Kojto	96:487b796308b0	2123	/**
Kojto	96:487b796308b0	2124	* @}
Kojto	96:487b796308b0	2125	*/
Kojto	96:487b796308b0	2126
Kojto	96:487b796308b0	2127	#ifdef __cplusplus
Kojto	96:487b796308b0	2128	}
Kojto	96:487b796308b0	2129	#endif
Kojto	96:487b796308b0	2130
Kojto	96:487b796308b0	2131	#endif /* __STM32F1xx_HAL_ETH_H */
Kojto	96:487b796308b0	2132
Kojto	96:487b796308b0	2133
Kojto	96:487b796308b0	2134
Kojto	96:487b796308b0	2135	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F103RB/stm32f1xx_hal_eth.h@121:672067c3ada4, 2016-04-14 (annotated)

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