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TARGET_MTS_MDOT_F411RE/stm32f4xx_ll_fmc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
110:165afa46840b 
.

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Kojto 93:e188a91d3eaa 1 /**
Kojto 93:e188a91d3eaa 2 ******************************************************************************
Kojto 93:e188a91d3eaa 3 * @file stm32f4xx_ll_fmc.h
Kojto 93:e188a91d3eaa 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
Kojto 93:e188a91d3eaa 7 * @brief Header file of FMC HAL module.
Kojto 93:e188a91d3eaa 8 ******************************************************************************
Kojto 93:e188a91d3eaa 9 * @attention
Kojto 93:e188a91d3eaa 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 93:e188a91d3eaa 12 *
Kojto 93:e188a91d3eaa 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 93:e188a91d3eaa 14 * are permitted provided that the following conditions are met:
Kojto 93:e188a91d3eaa 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 93:e188a91d3eaa 16 * this list of conditions and the following disclaimer.
Kojto 93:e188a91d3eaa 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 93:e188a91d3eaa 18 * this list of conditions and the following disclaimer in the documentation
Kojto 93:e188a91d3eaa 19 * and/or other materials provided with the distribution.
Kojto 93:e188a91d3eaa 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 93:e188a91d3eaa 21 * may be used to endorse or promote products derived from this software
Kojto 93:e188a91d3eaa 22 * without specific prior written permission.
Kojto 93:e188a91d3eaa 23 *
Kojto 93:e188a91d3eaa 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 93:e188a91d3eaa 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 93:e188a91d3eaa 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 93:e188a91d3eaa 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 93:e188a91d3eaa 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 93:e188a91d3eaa 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 93:e188a91d3eaa 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 93:e188a91d3eaa 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 93:e188a91d3eaa 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 93:e188a91d3eaa 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 93:e188a91d3eaa 34 *
Kojto 93:e188a91d3eaa 35 ******************************************************************************
Kojto 93:e188a91d3eaa 36 */
Kojto 93:e188a91d3eaa 37
Kojto 93:e188a91d3eaa 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 93:e188a91d3eaa 39 #ifndef __STM32F4xx_LL_FMC_H
Kojto 93:e188a91d3eaa 40 #define __STM32F4xx_LL_FMC_H
Kojto 93:e188a91d3eaa 41
Kojto 93:e188a91d3eaa 42 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 43 extern "C" {
Kojto 93:e188a91d3eaa 44 #endif
Kojto 93:e188a91d3eaa 45
Kojto 93:e188a91d3eaa 46 /* Includes ------------------------------------------------------------------*/
Kojto 93:e188a91d3eaa 47 #include "stm32f4xx_hal_def.h"
Kojto 93:e188a91d3eaa 48
Kojto 93:e188a91d3eaa 49 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 93:e188a91d3eaa 50 * @{
Kojto 93:e188a91d3eaa 51 */
Kojto 99:dbbf35b96557 52
Kojto 99:dbbf35b96557 53 /** @addtogroup FMC_LL
Kojto 93:e188a91d3eaa 54 * @{
Kojto 93:e188a91d3eaa 55 */
Kojto 110:165afa46840b 56 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 110:165afa46840b 57 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 99:dbbf35b96557 58 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 59 /** @defgroup FMC_LL_Private_Types FMC Private Types
Kojto 99:dbbf35b96557 60 * @{
Kojto 99:dbbf35b96557 61 */
Kojto 93:e188a91d3eaa 62
Kojto 93:e188a91d3eaa 63 /**
Kojto 99:dbbf35b96557 64 * @brief FMC NORSRAM Configuration Structure definition
Kojto 93:e188a91d3eaa 65 */
Kojto 93:e188a91d3eaa 66 typedef struct
Kojto 93:e188a91d3eaa 67 {
Kojto 93:e188a91d3eaa 68 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
Kojto 93:e188a91d3eaa 69 This parameter can be a value of @ref FMC_NORSRAM_Bank */
Kojto 93:e188a91d3eaa 70
Kojto 93:e188a91d3eaa 71 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
Kojto 93:e188a91d3eaa 72 multiplexed on the data bus or not.
Kojto 93:e188a91d3eaa 73 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
Kojto 93:e188a91d3eaa 74
Kojto 93:e188a91d3eaa 75 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
Kojto 93:e188a91d3eaa 76 the corresponding memory device.
Kojto 93:e188a91d3eaa 77 This parameter can be a value of @ref FMC_Memory_Type */
Kojto 93:e188a91d3eaa 78
Kojto 93:e188a91d3eaa 79 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto 93:e188a91d3eaa 80 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
Kojto 93:e188a91d3eaa 81
Kojto 93:e188a91d3eaa 82 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
Kojto 93:e188a91d3eaa 83 valid only with synchronous burst Flash memories.
Kojto 93:e188a91d3eaa 84 This parameter can be a value of @ref FMC_Burst_Access_Mode */
Kojto 93:e188a91d3eaa 85
Kojto 93:e188a91d3eaa 86 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
Kojto 93:e188a91d3eaa 87 the Flash memory in burst mode.
Kojto 93:e188a91d3eaa 88 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
Kojto 93:e188a91d3eaa 89
Kojto 93:e188a91d3eaa 90 uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
Kojto 93:e188a91d3eaa 91 memory, valid only when accessing Flash memories in burst mode.
Kojto 99:dbbf35b96557 92 This parameter can be a value of @ref FMC_Wrap_Mode
Kojto 110:165afa46840b 93 This mode is not available for the STM32F446/467/479xx devices */
Kojto 93:e188a91d3eaa 94
Kojto 93:e188a91d3eaa 95 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
Kojto 93:e188a91d3eaa 96 clock cycle before the wait state or during the wait state,
Kojto 93:e188a91d3eaa 97 valid only when accessing memories in burst mode.
Kojto 93:e188a91d3eaa 98 This parameter can be a value of @ref FMC_Wait_Timing */
Kojto 93:e188a91d3eaa 99
Kojto 93:e188a91d3eaa 100 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
Kojto 93:e188a91d3eaa 101 This parameter can be a value of @ref FMC_Write_Operation */
Kojto 93:e188a91d3eaa 102
Kojto 93:e188a91d3eaa 103 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
Kojto 93:e188a91d3eaa 104 signal, valid for Flash memory access in burst mode.
Kojto 93:e188a91d3eaa 105 This parameter can be a value of @ref FMC_Wait_Signal */
Kojto 93:e188a91d3eaa 106
Kojto 93:e188a91d3eaa 107 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
Kojto 93:e188a91d3eaa 108 This parameter can be a value of @ref FMC_Extended_Mode */
Kojto 93:e188a91d3eaa 109
Kojto 93:e188a91d3eaa 110 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
Kojto 93:e188a91d3eaa 111 valid only with asynchronous Flash memories.
Kojto 93:e188a91d3eaa 112 This parameter can be a value of @ref FMC_AsynchronousWait */
Kojto 93:e188a91d3eaa 113
Kojto 93:e188a91d3eaa 114 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
Kojto 93:e188a91d3eaa 115 This parameter can be a value of @ref FMC_Write_Burst */
Kojto 93:e188a91d3eaa 116
Kojto 93:e188a91d3eaa 117 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
Kojto 93:e188a91d3eaa 118 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 93:e188a91d3eaa 119 through FMC_BCR2..4 registers.
Kojto 93:e188a91d3eaa 120 This parameter can be a value of @ref FMC_Continous_Clock */
Kojto 93:e188a91d3eaa 121
Kojto 99:dbbf35b96557 122 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto 99:dbbf35b96557 123 This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto 99:dbbf35b96557 124 through FMC_BCR2..4 registers.
Kojto 99:dbbf35b96557 125 This parameter can be a value of @ref FMC_Write_FIFO
Kojto 110:165afa46840b 126 This mode is available only for the STM32F446/469/479xx devices */
Kojto 99:dbbf35b96557 127
Kojto 99:dbbf35b96557 128 uint32_t PageSize; /*!< Specifies the memory page size.
Kojto 99:dbbf35b96557 129 This parameter can be a value of @ref FMC_Page_Size
Kojto 99:dbbf35b96557 130 This mode is available only for the STM32F446xx devices */
Kojto 99:dbbf35b96557 131
Kojto 93:e188a91d3eaa 132 }FMC_NORSRAM_InitTypeDef;
Kojto 93:e188a91d3eaa 133
Kojto 93:e188a91d3eaa 134 /**
Kojto 99:dbbf35b96557 135 * @brief FMC NORSRAM Timing parameters structure definition
Kojto 93:e188a91d3eaa 136 */
Kojto 93:e188a91d3eaa 137 typedef struct
Kojto 93:e188a91d3eaa 138 {
Kojto 93:e188a91d3eaa 139 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto 93:e188a91d3eaa 140 the duration of the address setup time.
Kojto 93:e188a91d3eaa 141 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto 93:e188a91d3eaa 142 @note This parameter is not used with synchronous NOR Flash memories. */
Kojto 93:e188a91d3eaa 143
Kojto 93:e188a91d3eaa 144 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
Kojto 93:e188a91d3eaa 145 the duration of the address hold time.
Kojto 93:e188a91d3eaa 146 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
Kojto 93:e188a91d3eaa 147 @note This parameter is not used with synchronous NOR Flash memories. */
Kojto 93:e188a91d3eaa 148
Kojto 93:e188a91d3eaa 149 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
Kojto 93:e188a91d3eaa 150 the duration of the data setup time.
Kojto 93:e188a91d3eaa 151 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
Kojto 93:e188a91d3eaa 152 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
Kojto 93:e188a91d3eaa 153 NOR Flash memories. */
Kojto 93:e188a91d3eaa 154
Kojto 93:e188a91d3eaa 155 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
Kojto 93:e188a91d3eaa 156 the duration of the bus turnaround.
Kojto 93:e188a91d3eaa 157 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
Kojto 93:e188a91d3eaa 158 @note This parameter is only used for multiplexed NOR Flash memories. */
Kojto 93:e188a91d3eaa 159
Kojto 93:e188a91d3eaa 160 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
Kojto 93:e188a91d3eaa 161 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
Kojto 93:e188a91d3eaa 162 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
Kojto 93:e188a91d3eaa 163 accesses. */
Kojto 93:e188a91d3eaa 164
Kojto 93:e188a91d3eaa 165 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
Kojto 93:e188a91d3eaa 166 to the memory before getting the first data.
Kojto 93:e188a91d3eaa 167 The parameter value depends on the memory type as shown below:
Kojto 93:e188a91d3eaa 168 - It must be set to 0 in case of a CRAM
Kojto 93:e188a91d3eaa 169 - It is don't care in asynchronous NOR, SRAM or ROM accesses
Kojto 93:e188a91d3eaa 170 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
Kojto 93:e188a91d3eaa 171 with synchronous burst mode enable */
Kojto 93:e188a91d3eaa 172
Kojto 93:e188a91d3eaa 173 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
Kojto 93:e188a91d3eaa 174 This parameter can be a value of @ref FMC_Access_Mode */
Kojto 93:e188a91d3eaa 175 }FMC_NORSRAM_TimingTypeDef;
Kojto 93:e188a91d3eaa 176
Kojto 93:e188a91d3eaa 177 /**
Kojto 99:dbbf35b96557 178 * @brief FMC NAND Configuration Structure definition
Kojto 93:e188a91d3eaa 179 */
Kojto 93:e188a91d3eaa 180 typedef struct
Kojto 93:e188a91d3eaa 181 {
Kojto 93:e188a91d3eaa 182 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
Kojto 93:e188a91d3eaa 183 This parameter can be a value of @ref FMC_NAND_Bank */
Kojto 93:e188a91d3eaa 184
Kojto 93:e188a91d3eaa 185 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
Kojto 93:e188a91d3eaa 186 This parameter can be any value of @ref FMC_Wait_feature */
Kojto 93:e188a91d3eaa 187
Kojto 93:e188a91d3eaa 188 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
Kojto 93:e188a91d3eaa 189 This parameter can be any value of @ref FMC_NAND_Data_Width */
Kojto 93:e188a91d3eaa 190
Kojto 93:e188a91d3eaa 191 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
Kojto 93:e188a91d3eaa 192 This parameter can be any value of @ref FMC_ECC */
Kojto 93:e188a91d3eaa 193
Kojto 93:e188a91d3eaa 194 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
Kojto 93:e188a91d3eaa 195 This parameter can be any value of @ref FMC_ECC_Page_Size */
Kojto 93:e188a91d3eaa 196
Kojto 93:e188a91d3eaa 197 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 93:e188a91d3eaa 198 delay between CLE low and RE low.
Kojto 93:e188a91d3eaa 199 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto 93:e188a91d3eaa 200
Kojto 93:e188a91d3eaa 201 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 93:e188a91d3eaa 202 delay between ALE low and RE low.
Kojto 93:e188a91d3eaa 203 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 93:e188a91d3eaa 204 }FMC_NAND_InitTypeDef;
Kojto 93:e188a91d3eaa 205
Kojto 93:e188a91d3eaa 206 /**
Kojto 99:dbbf35b96557 207 * @brief FMC NAND/PCCARD Timing parameters structure definition
Kojto 93:e188a91d3eaa 208 */
Kojto 93:e188a91d3eaa 209 typedef struct
Kojto 93:e188a91d3eaa 210 {
Kojto 93:e188a91d3eaa 211 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
Kojto 93:e188a91d3eaa 212 the command assertion for NAND-Flash read or write access
Kojto 93:e188a91d3eaa 213 to common/Attribute or I/O memory space (depending on
Kojto 93:e188a91d3eaa 214 the memory space timing to be configured).
Kojto 93:e188a91d3eaa 215 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto 93:e188a91d3eaa 216
Kojto 93:e188a91d3eaa 217 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
Kojto 93:e188a91d3eaa 218 command for NAND-Flash read or write access to
Kojto 93:e188a91d3eaa 219 common/Attribute or I/O memory space (depending on the
Kojto 93:e188a91d3eaa 220 memory space timing to be configured).
Kojto 93:e188a91d3eaa 221 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 93:e188a91d3eaa 222
Kojto 93:e188a91d3eaa 223 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
Kojto 93:e188a91d3eaa 224 (and data for write access) after the command de-assertion
Kojto 93:e188a91d3eaa 225 for NAND-Flash read or write access to common/Attribute
Kojto 93:e188a91d3eaa 226 or I/O memory space (depending on the memory space timing
Kojto 93:e188a91d3eaa 227 to be configured).
Kojto 93:e188a91d3eaa 228 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 93:e188a91d3eaa 229
Kojto 93:e188a91d3eaa 230 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
Kojto 93:e188a91d3eaa 231 data bus is kept in HiZ after the start of a NAND-Flash
Kojto 93:e188a91d3eaa 232 write access to common/Attribute or I/O memory space (depending
Kojto 93:e188a91d3eaa 233 on the memory space timing to be configured).
Kojto 93:e188a91d3eaa 234 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 93:e188a91d3eaa 235 }FMC_NAND_PCC_TimingTypeDef;
Kojto 93:e188a91d3eaa 236
Kojto 93:e188a91d3eaa 237 /**
Kojto 99:dbbf35b96557 238 * @brief FMC NAND Configuration Structure definition
Kojto 93:e188a91d3eaa 239 */
Kojto 93:e188a91d3eaa 240 typedef struct
Kojto 93:e188a91d3eaa 241 {
Kojto 93:e188a91d3eaa 242 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
Kojto 93:e188a91d3eaa 243 This parameter can be any value of @ref FMC_Wait_feature */
Kojto 93:e188a91d3eaa 244
Kojto 93:e188a91d3eaa 245 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 93:e188a91d3eaa 246 delay between CLE low and RE low.
Kojto 93:e188a91d3eaa 247 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Kojto 93:e188a91d3eaa 248
Kojto 93:e188a91d3eaa 249 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
Kojto 93:e188a91d3eaa 250 delay between ALE low and RE low.
Kojto 93:e188a91d3eaa 251 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
Kojto 93:e188a91d3eaa 252 }FMC_PCCARD_InitTypeDef;
Kojto 93:e188a91d3eaa 253
Kojto 93:e188a91d3eaa 254 /**
Kojto 99:dbbf35b96557 255 * @brief FMC SDRAM Configuration Structure definition
Kojto 93:e188a91d3eaa 256 */
Kojto 93:e188a91d3eaa 257 typedef struct
Kojto 93:e188a91d3eaa 258 {
Kojto 93:e188a91d3eaa 259 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
Kojto 93:e188a91d3eaa 260 This parameter can be a value of @ref FMC_SDRAM_Bank */
Kojto 93:e188a91d3eaa 261
Kojto 93:e188a91d3eaa 262 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
Kojto 93:e188a91d3eaa 263 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
Kojto 93:e188a91d3eaa 264
Kojto 93:e188a91d3eaa 265 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
Kojto 93:e188a91d3eaa 266 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
Kojto 93:e188a91d3eaa 267
Kojto 93:e188a91d3eaa 268 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
Kojto 93:e188a91d3eaa 269 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
Kojto 93:e188a91d3eaa 270
Kojto 93:e188a91d3eaa 271 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
Kojto 93:e188a91d3eaa 272 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
Kojto 93:e188a91d3eaa 273
Kojto 93:e188a91d3eaa 274 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
Kojto 93:e188a91d3eaa 275 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
Kojto 93:e188a91d3eaa 276
Kojto 93:e188a91d3eaa 277 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
Kojto 93:e188a91d3eaa 278 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
Kojto 93:e188a91d3eaa 279
Kojto 93:e188a91d3eaa 280 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
Kojto 93:e188a91d3eaa 281 to disable the clock before changing frequency.
Kojto 93:e188a91d3eaa 282 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
Kojto 93:e188a91d3eaa 283
Kojto 93:e188a91d3eaa 284 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
Kojto 93:e188a91d3eaa 285 commands during the CAS latency and stores data in the Read FIFO.
Kojto 93:e188a91d3eaa 286 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
Kojto 93:e188a91d3eaa 287
Kojto 93:e188a91d3eaa 288 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
Kojto 93:e188a91d3eaa 289 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
Kojto 93:e188a91d3eaa 290 }FMC_SDRAM_InitTypeDef;
Kojto 93:e188a91d3eaa 291
Kojto 93:e188a91d3eaa 292 /**
Kojto 99:dbbf35b96557 293 * @brief FMC SDRAM Timing parameters structure definition
Kojto 93:e188a91d3eaa 294 */
Kojto 93:e188a91d3eaa 295 typedef struct
Kojto 93:e188a91d3eaa 296 {
Kojto 93:e188a91d3eaa 297 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
Kojto 93:e188a91d3eaa 298 an active or Refresh command in number of memory clock cycles.
Kojto 93:e188a91d3eaa 299 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 93:e188a91d3eaa 300
Kojto 93:e188a91d3eaa 301 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
Kojto 93:e188a91d3eaa 302 issuing the Activate command in number of memory clock cycles.
Kojto 93:e188a91d3eaa 303 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 93:e188a91d3eaa 304
Kojto 93:e188a91d3eaa 305 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
Kojto 93:e188a91d3eaa 306 cycles.
Kojto 93:e188a91d3eaa 307 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 93:e188a91d3eaa 308
Kojto 93:e188a91d3eaa 309 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
Kojto 93:e188a91d3eaa 310 and the delay between two consecutive Refresh commands in number of
Kojto 93:e188a91d3eaa 311 memory clock cycles.
Kojto 93:e188a91d3eaa 312 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 93:e188a91d3eaa 313
Kojto 93:e188a91d3eaa 314 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
Kojto 93:e188a91d3eaa 315 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 93:e188a91d3eaa 316
Kojto 93:e188a91d3eaa 317 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
Kojto 93:e188a91d3eaa 318 in number of memory clock cycles.
Kojto 93:e188a91d3eaa 319 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 93:e188a91d3eaa 320
Kojto 93:e188a91d3eaa 321 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
Kojto 93:e188a91d3eaa 322 command in number of memory clock cycles.
Kojto 93:e188a91d3eaa 323 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 93:e188a91d3eaa 324 }FMC_SDRAM_TimingTypeDef;
Kojto 93:e188a91d3eaa 325
Kojto 93:e188a91d3eaa 326 /**
Kojto 99:dbbf35b96557 327 * @brief SDRAM command parameters structure definition
Kojto 93:e188a91d3eaa 328 */
Kojto 93:e188a91d3eaa 329 typedef struct
Kojto 93:e188a91d3eaa 330 {
Kojto 93:e188a91d3eaa 331 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
Kojto 93:e188a91d3eaa 332 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
Kojto 93:e188a91d3eaa 333
Kojto 93:e188a91d3eaa 334 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
Kojto 93:e188a91d3eaa 335 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
Kojto 93:e188a91d3eaa 336
Kojto 93:e188a91d3eaa 337 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
Kojto 93:e188a91d3eaa 338 in auto refresh mode.
Kojto 93:e188a91d3eaa 339 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
Kojto 93:e188a91d3eaa 340 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
Kojto 93:e188a91d3eaa 341 }FMC_SDRAM_CommandTypeDef;
Kojto 99:dbbf35b96557 342 /**
Kojto 99:dbbf35b96557 343 * @}
Kojto 99:dbbf35b96557 344 */
Kojto 93:e188a91d3eaa 345
Kojto 99:dbbf35b96557 346 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 347 /** @defgroup FMC_LL_Private_Constants FMC Private Constants
Kojto 93:e188a91d3eaa 348 * @{
Kojto 93:e188a91d3eaa 349 */
Kojto 93:e188a91d3eaa 350
Kojto 99:dbbf35b96557 351 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
Kojto 99:dbbf35b96557 352 * @{
Kojto 99:dbbf35b96557 353 */
Kojto 99:dbbf35b96557 354 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
Kojto 93:e188a91d3eaa 355 * @{
Kojto 93:e188a91d3eaa 356 */
Kojto 93:e188a91d3eaa 357 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 358 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 359 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 360 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
Kojto 93:e188a91d3eaa 361 /**
Kojto 93:e188a91d3eaa 362 * @}
Kojto 93:e188a91d3eaa 363 */
Kojto 93:e188a91d3eaa 364
Kojto 99:dbbf35b96557 365 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
Kojto 93:e188a91d3eaa 366 * @{
Kojto 93:e188a91d3eaa 367 */
Kojto 93:e188a91d3eaa 368 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 369 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 370 /**
Kojto 93:e188a91d3eaa 371 * @}
Kojto 93:e188a91d3eaa 372 */
Kojto 93:e188a91d3eaa 373
Kojto 99:dbbf35b96557 374 /** @defgroup FMC_Memory_Type FMC Memory Type
Kojto 93:e188a91d3eaa 375 * @{
Kojto 93:e188a91d3eaa 376 */
Kojto 93:e188a91d3eaa 377 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 378 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 379 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 380 /**
Kojto 93:e188a91d3eaa 381 * @}
Kojto 93:e188a91d3eaa 382 */
Kojto 93:e188a91d3eaa 383
Kojto 99:dbbf35b96557 384 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
Kojto 93:e188a91d3eaa 385 * @{
Kojto 93:e188a91d3eaa 386 */
Kojto 93:e188a91d3eaa 387 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 388 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 389 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 390 /**
Kojto 93:e188a91d3eaa 391 * @}
Kojto 93:e188a91d3eaa 392 */
Kojto 93:e188a91d3eaa 393
Kojto 99:dbbf35b96557 394 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
Kojto 93:e188a91d3eaa 395 * @{
Kojto 93:e188a91d3eaa 396 */
Kojto 93:e188a91d3eaa 397 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 398 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 399 /**
Kojto 93:e188a91d3eaa 400 * @}
Kojto 93:e188a91d3eaa 401 */
Kojto 93:e188a91d3eaa 402
Kojto 99:dbbf35b96557 403 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
Kojto 93:e188a91d3eaa 404 * @{
Kojto 93:e188a91d3eaa 405 */
Kojto 93:e188a91d3eaa 406 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 407 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 408 /**
Kojto 93:e188a91d3eaa 409 * @}
Kojto 93:e188a91d3eaa 410 */
Kojto 93:e188a91d3eaa 411
Kojto 99:dbbf35b96557 412 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
Kojto 93:e188a91d3eaa 413 * @{
Kojto 93:e188a91d3eaa 414 */
Kojto 93:e188a91d3eaa 415 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 416 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 417 /**
Kojto 93:e188a91d3eaa 418 * @}
Kojto 93:e188a91d3eaa 419 */
Kojto 93:e188a91d3eaa 420
Kojto 99:dbbf35b96557 421 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode
Kojto 93:e188a91d3eaa 422 * @{
Kojto 93:e188a91d3eaa 423 */
Kojto 110:165afa46840b 424 /** @note This mode is not available for the STM32F446/469/479xx devices
Kojto 99:dbbf35b96557 425 */
Kojto 99:dbbf35b96557 426 #define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 427 #define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
Kojto 93:e188a91d3eaa 428 /**
Kojto 93:e188a91d3eaa 429 * @}
Kojto 93:e188a91d3eaa 430 */
Kojto 93:e188a91d3eaa 431
Kojto 99:dbbf35b96557 432 /** @defgroup FMC_Wait_Timing FMC Wait Timing
Kojto 99:dbbf35b96557 433 * @{
Kojto 99:dbbf35b96557 434 */
Kojto 99:dbbf35b96557 435 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 436 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
Kojto 99:dbbf35b96557 437 /**
Kojto 99:dbbf35b96557 438 * @}
Kojto 99:dbbf35b96557 439 */
Kojto 99:dbbf35b96557 440
Kojto 99:dbbf35b96557 441 /** @defgroup FMC_Write_Operation FMC Write Operation
Kojto 93:e188a91d3eaa 442 * @{
Kojto 93:e188a91d3eaa 443 */
Kojto 93:e188a91d3eaa 444 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 445 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 446 /**
Kojto 93:e188a91d3eaa 447 * @}
Kojto 93:e188a91d3eaa 448 */
Kojto 93:e188a91d3eaa 449
Kojto 99:dbbf35b96557 450 /** @defgroup FMC_Wait_Signal FMC Wait Signal
Kojto 93:e188a91d3eaa 451 * @{
Kojto 93:e188a91d3eaa 452 */
Kojto 93:e188a91d3eaa 453 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 454 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 455 /**
Kojto 93:e188a91d3eaa 456 * @}
Kojto 93:e188a91d3eaa 457 */
Kojto 93:e188a91d3eaa 458
Kojto 99:dbbf35b96557 459 /** @defgroup FMC_Extended_Mode FMC Extended Mode
Kojto 99:dbbf35b96557 460 * @{
Kojto 99:dbbf35b96557 461 */
Kojto 99:dbbf35b96557 462 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 463 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
Kojto 99:dbbf35b96557 464 /**
Kojto 99:dbbf35b96557 465 * @}
Kojto 99:dbbf35b96557 466 */
Kojto 99:dbbf35b96557 467
Kojto 99:dbbf35b96557 468 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
Kojto 93:e188a91d3eaa 469 * @{
Kojto 93:e188a91d3eaa 470 */
Kojto 93:e188a91d3eaa 471 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 472 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
Kojto 93:e188a91d3eaa 473 /**
Kojto 93:e188a91d3eaa 474 * @}
Kojto 93:e188a91d3eaa 475 */
Kojto 93:e188a91d3eaa 476
Kojto 99:dbbf35b96557 477 /** @defgroup FMC_Page_Size FMC Page Size
Kojto 110:165afa46840b 478 * @note These values are available only for the STM32F446/469/479xx devices.
Kojto 99:dbbf35b96557 479 * @{
Kojto 99:dbbf35b96557 480 */
Kojto 99:dbbf35b96557 481 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 482 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
Kojto 99:dbbf35b96557 483 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
Kojto 99:dbbf35b96557 484 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
Kojto 99:dbbf35b96557 485 /**
Kojto 99:dbbf35b96557 486 * @}
Kojto 99:dbbf35b96557 487 */
Kojto 99:dbbf35b96557 488
Kojto 99:dbbf35b96557 489 /** @defgroup FMC_Write_FIFO FMC Write FIFO
Kojto 110:165afa46840b 490 * @note These values are available only for the STM32F446/469/479xx devices.
Kojto 99:dbbf35b96557 491 * @{
Kojto 99:dbbf35b96557 492 */
Kojto 99:dbbf35b96557 493 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 494 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
Kojto 99:dbbf35b96557 495 /**
Kojto 99:dbbf35b96557 496 * @}
Kojto 99:dbbf35b96557 497 */
Kojto 99:dbbf35b96557 498
Kojto 99:dbbf35b96557 499 /** @defgroup FMC_Write_Burst FMC Write Burst
Kojto 93:e188a91d3eaa 500 * @{
Kojto 93:e188a91d3eaa 501 */
Kojto 93:e188a91d3eaa 502 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 503 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 504 /**
Kojto 93:e188a91d3eaa 505 * @}
Kojto 93:e188a91d3eaa 506 */
Kojto 93:e188a91d3eaa 507
Kojto 99:dbbf35b96557 508 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
Kojto 93:e188a91d3eaa 509 * @{
Kojto 93:e188a91d3eaa 510 */
Kojto 99:dbbf35b96557 511 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 512 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
Kojto 93:e188a91d3eaa 513 /**
Kojto 93:e188a91d3eaa 514 * @}
Kojto 93:e188a91d3eaa 515 */
Kojto 99:dbbf35b96557 516
Kojto 99:dbbf35b96557 517 /** @defgroup FMC_Access_Mode FMC Access Mode
Kojto 93:e188a91d3eaa 518 * @{
Kojto 93:e188a91d3eaa 519 */
Kojto 93:e188a91d3eaa 520 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 521 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
Kojto 93:e188a91d3eaa 522 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
Kojto 93:e188a91d3eaa 523 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
Kojto 93:e188a91d3eaa 524 /**
Kojto 93:e188a91d3eaa 525 * @}
Kojto 93:e188a91d3eaa 526 */
Kojto 93:e188a91d3eaa 527
Kojto 93:e188a91d3eaa 528 /**
Kojto 93:e188a91d3eaa 529 * @}
Kojto 99:dbbf35b96557 530 */
Kojto 93:e188a91d3eaa 531
Kojto 99:dbbf35b96557 532 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
Kojto 93:e188a91d3eaa 533 * @{
Kojto 93:e188a91d3eaa 534 */
Kojto 99:dbbf35b96557 535 /** @defgroup FMC_NAND_Bank FMC NAND Bank
Kojto 93:e188a91d3eaa 536 * @{
Kojto 99:dbbf35b96557 537 */
Kojto 93:e188a91d3eaa 538 #define FMC_NAND_BANK2 ((uint32_t)0x00000010)
Kojto 99:dbbf35b96557 539 #define FMC_NAND_BANK3 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 540 /**
Kojto 93:e188a91d3eaa 541 * @}
Kojto 93:e188a91d3eaa 542 */
Kojto 93:e188a91d3eaa 543
Kojto 99:dbbf35b96557 544 /** @defgroup FMC_Wait_feature FMC Wait feature
Kojto 93:e188a91d3eaa 545 * @{
Kojto 93:e188a91d3eaa 546 */
Kojto 93:e188a91d3eaa 547 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 548 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 549 /**
Kojto 93:e188a91d3eaa 550 * @}
Kojto 93:e188a91d3eaa 551 */
Kojto 93:e188a91d3eaa 552
Kojto 99:dbbf35b96557 553 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
Kojto 93:e188a91d3eaa 554 * @{
Kojto 93:e188a91d3eaa 555 */
Kojto 93:e188a91d3eaa 556 #define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 557 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 558 /**
Kojto 93:e188a91d3eaa 559 * @}
Kojto 93:e188a91d3eaa 560 */
Kojto 93:e188a91d3eaa 561
Kojto 99:dbbf35b96557 562 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
Kojto 93:e188a91d3eaa 563 * @{
Kojto 93:e188a91d3eaa 564 */
Kojto 93:e188a91d3eaa 565 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 566 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 567 /**
Kojto 93:e188a91d3eaa 568 * @}
Kojto 93:e188a91d3eaa 569 */
Kojto 93:e188a91d3eaa 570
Kojto 99:dbbf35b96557 571 /** @defgroup FMC_ECC FMC ECC
Kojto 93:e188a91d3eaa 572 * @{
Kojto 93:e188a91d3eaa 573 */
Kojto 93:e188a91d3eaa 574 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 575 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 576 /**
Kojto 93:e188a91d3eaa 577 * @}
Kojto 93:e188a91d3eaa 578 */
Kojto 93:e188a91d3eaa 579
Kojto 99:dbbf35b96557 580 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
Kojto 93:e188a91d3eaa 581 * @{
Kojto 93:e188a91d3eaa 582 */
Kojto 93:e188a91d3eaa 583 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 584 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 585 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
Kojto 93:e188a91d3eaa 586 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
Kojto 93:e188a91d3eaa 587 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
Kojto 93:e188a91d3eaa 588 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
Kojto 93:e188a91d3eaa 589 /**
Kojto 93:e188a91d3eaa 590 * @}
Kojto 93:e188a91d3eaa 591 */
Kojto 99:dbbf35b96557 592
Kojto 93:e188a91d3eaa 593 /**
Kojto 93:e188a91d3eaa 594 * @}
Kojto 99:dbbf35b96557 595 */
Kojto 93:e188a91d3eaa 596
Kojto 99:dbbf35b96557 597 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
Kojto 93:e188a91d3eaa 598 * @{
Kojto 93:e188a91d3eaa 599 */
Kojto 99:dbbf35b96557 600 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
Kojto 93:e188a91d3eaa 601 * @{
Kojto 93:e188a91d3eaa 602 */
Kojto 99:dbbf35b96557 603 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 604 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 605 /**
Kojto 93:e188a91d3eaa 606 * @}
Kojto 93:e188a91d3eaa 607 */
Kojto 93:e188a91d3eaa 608
Kojto 99:dbbf35b96557 609 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
Kojto 93:e188a91d3eaa 610 * @{
Kojto 93:e188a91d3eaa 611 */
Kojto 93:e188a91d3eaa 612 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 613 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 614 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 615 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
Kojto 93:e188a91d3eaa 616 /**
Kojto 93:e188a91d3eaa 617 * @}
Kojto 93:e188a91d3eaa 618 */
Kojto 93:e188a91d3eaa 619
Kojto 99:dbbf35b96557 620 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
Kojto 93:e188a91d3eaa 621 * @{
Kojto 93:e188a91d3eaa 622 */
Kojto 93:e188a91d3eaa 623 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 624 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 625 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 626 /**
Kojto 93:e188a91d3eaa 627 * @}
Kojto 93:e188a91d3eaa 628 */
Kojto 93:e188a91d3eaa 629
Kojto 99:dbbf35b96557 630 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
Kojto 93:e188a91d3eaa 631 * @{
Kojto 93:e188a91d3eaa 632 */
Kojto 93:e188a91d3eaa 633 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 634 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 635 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 636 /**
Kojto 93:e188a91d3eaa 637 * @}
Kojto 93:e188a91d3eaa 638 */
Kojto 93:e188a91d3eaa 639
Kojto 99:dbbf35b96557 640 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
Kojto 93:e188a91d3eaa 641 * @{
Kojto 93:e188a91d3eaa 642 */
Kojto 93:e188a91d3eaa 643 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 644 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 645 /**
Kojto 93:e188a91d3eaa 646 * @}
Kojto 93:e188a91d3eaa 647 */
Kojto 93:e188a91d3eaa 648
Kojto 99:dbbf35b96557 649 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
Kojto 93:e188a91d3eaa 650 * @{
Kojto 93:e188a91d3eaa 651 */
Kojto 93:e188a91d3eaa 652 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
Kojto 93:e188a91d3eaa 653 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
Kojto 93:e188a91d3eaa 654 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
Kojto 93:e188a91d3eaa 655 /**
Kojto 93:e188a91d3eaa 656 * @}
Kojto 93:e188a91d3eaa 657 */
Kojto 93:e188a91d3eaa 658
Kojto 99:dbbf35b96557 659 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
Kojto 93:e188a91d3eaa 660 * @{
Kojto 93:e188a91d3eaa 661 */
Kojto 93:e188a91d3eaa 662 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 663 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
Kojto 93:e188a91d3eaa 664
Kojto 93:e188a91d3eaa 665 /**
Kojto 93:e188a91d3eaa 666 * @}
Kojto 93:e188a91d3eaa 667 */
Kojto 93:e188a91d3eaa 668
Kojto 99:dbbf35b96557 669 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
Kojto 93:e188a91d3eaa 670 * @{
Kojto 93:e188a91d3eaa 671 */
Kojto 93:e188a91d3eaa 672 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 673 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
Kojto 93:e188a91d3eaa 674 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
Kojto 93:e188a91d3eaa 675 /**
Kojto 93:e188a91d3eaa 676 * @}
Kojto 93:e188a91d3eaa 677 */
Kojto 93:e188a91d3eaa 678
Kojto 99:dbbf35b96557 679 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
Kojto 93:e188a91d3eaa 680 * @{
Kojto 93:e188a91d3eaa 681 */
Kojto 93:e188a91d3eaa 682 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 683 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
Kojto 93:e188a91d3eaa 684 /**
Kojto 93:e188a91d3eaa 685 * @}
Kojto 93:e188a91d3eaa 686 */
Kojto 93:e188a91d3eaa 687
Kojto 99:dbbf35b96557 688 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
Kojto 93:e188a91d3eaa 689 * @{
Kojto 93:e188a91d3eaa 690 */
Kojto 93:e188a91d3eaa 691 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 692 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
Kojto 93:e188a91d3eaa 693 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 694 /**
Kojto 93:e188a91d3eaa 695 * @}
Kojto 93:e188a91d3eaa 696 */
Kojto 93:e188a91d3eaa 697
Kojto 99:dbbf35b96557 698 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
Kojto 93:e188a91d3eaa 699 * @{
Kojto 93:e188a91d3eaa 700 */
Kojto 93:e188a91d3eaa 701 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 702 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 703 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 704 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
Kojto 93:e188a91d3eaa 705 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 706 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
Kojto 93:e188a91d3eaa 707 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
Kojto 93:e188a91d3eaa 708 /**
Kojto 93:e188a91d3eaa 709 * @}
Kojto 93:e188a91d3eaa 710 */
Kojto 93:e188a91d3eaa 711
Kojto 99:dbbf35b96557 712 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
Kojto 93:e188a91d3eaa 713 * @{
Kojto 93:e188a91d3eaa 714 */
Kojto 93:e188a91d3eaa 715 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
Kojto 93:e188a91d3eaa 716 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
Kojto 93:e188a91d3eaa 717 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
Kojto 93:e188a91d3eaa 718 /**
Kojto 93:e188a91d3eaa 719 * @}
Kojto 93:e188a91d3eaa 720 */
Kojto 93:e188a91d3eaa 721
Kojto 99:dbbf35b96557 722 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
Kojto 93:e188a91d3eaa 723 * @{
Kojto 93:e188a91d3eaa 724 */
Kojto 93:e188a91d3eaa 725 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 726 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
Kojto 93:e188a91d3eaa 727 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
Kojto 93:e188a91d3eaa 728 /**
Kojto 93:e188a91d3eaa 729 * @}
Kojto 93:e188a91d3eaa 730 */
Kojto 99:dbbf35b96557 731
Kojto 93:e188a91d3eaa 732 /**
Kojto 93:e188a91d3eaa 733 * @}
Kojto 93:e188a91d3eaa 734 */
Kojto 93:e188a91d3eaa 735
Kojto 99:dbbf35b96557 736 /** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
Kojto 93:e188a91d3eaa 737 * @{
Kojto 93:e188a91d3eaa 738 */
Kojto 93:e188a91d3eaa 739 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 740 #define FMC_IT_LEVEL ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 741 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 742 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
Kojto 93:e188a91d3eaa 743 /**
Kojto 93:e188a91d3eaa 744 * @}
Kojto 93:e188a91d3eaa 745 */
Kojto 93:e188a91d3eaa 746
Kojto 99:dbbf35b96557 747 /** @defgroup FMC_LL_Flag_definition FMC Flag definition
Kojto 93:e188a91d3eaa 748 * @{
Kojto 93:e188a91d3eaa 749 */
Kojto 93:e188a91d3eaa 750 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 751 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 752 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 753 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
Kojto 93:e188a91d3eaa 754 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
Kojto 93:e188a91d3eaa 755 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
Kojto 93:e188a91d3eaa 756 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
Kojto 93:e188a91d3eaa 757 /**
Kojto 93:e188a91d3eaa 758 * @}
Kojto 93:e188a91d3eaa 759 */
Kojto 93:e188a91d3eaa 760
Kojto 99:dbbf35b96557 761 /** @defgroup FMC_LL_Alias_definition FMC Alias definition
Kojto 99:dbbf35b96557 762 * @{
Kojto 99:dbbf35b96557 763 */
Kojto 110:165afa46840b 764 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 99:dbbf35b96557 765 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
Kojto 99:dbbf35b96557 766 #else
Kojto 99:dbbf35b96557 767 #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
Kojto 99:dbbf35b96557 768 #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
Kojto 110:165afa46840b 769 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 770 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
Kojto 99:dbbf35b96557 771 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
Kojto 99:dbbf35b96557 772 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
Kojto 99:dbbf35b96557 773
Kojto 93:e188a91d3eaa 774
Kojto 110:165afa46840b 775 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 99:dbbf35b96557 776 #define FMC_NAND_DEVICE FMC_Bank3
Kojto 99:dbbf35b96557 777 #else
Kojto 99:dbbf35b96557 778 #define FMC_NAND_DEVICE FMC_Bank2_3
Kojto 99:dbbf35b96557 779 #define FMC_PCCARD_DEVICE FMC_Bank4
Kojto 110:165afa46840b 780 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 781 #define FMC_NORSRAM_DEVICE FMC_Bank1
Kojto 99:dbbf35b96557 782 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
Kojto 99:dbbf35b96557 783 #define FMC_SDRAM_DEVICE FMC_Bank5_6
Kojto 99:dbbf35b96557 784 /**
Kojto 99:dbbf35b96557 785 * @}
Kojto 99:dbbf35b96557 786 */
Kojto 99:dbbf35b96557 787
Kojto 99:dbbf35b96557 788 /**
Kojto 99:dbbf35b96557 789 * @}
Kojto 99:dbbf35b96557 790 */
Kojto 99:dbbf35b96557 791
Kojto 99:dbbf35b96557 792 /* Private macro -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 793 /** @defgroup FMC_LL_Private_Macros FMC Private Macros
Kojto 99:dbbf35b96557 794 * @{
Kojto 99:dbbf35b96557 795 */
Kojto 99:dbbf35b96557 796
Kojto 99:dbbf35b96557 797 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
Kojto 93:e188a91d3eaa 798 * @brief macros to handle NOR device enable/disable and read/write operations
Kojto 93:e188a91d3eaa 799 * @{
Kojto 93:e188a91d3eaa 800 */
Kojto 93:e188a91d3eaa 801 /**
Kojto 93:e188a91d3eaa 802 * @brief Enable the NORSRAM device access.
Kojto 93:e188a91d3eaa 803 * @param __INSTANCE__: FMC_NORSRAM Instance
Kojto 93:e188a91d3eaa 804 * @param __BANK__: FMC_NORSRAM Bank
Kojto 93:e188a91d3eaa 805 * @retval None
Kojto 93:e188a91d3eaa 806 */
Kojto 93:e188a91d3eaa 807 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
Kojto 93:e188a91d3eaa 808
Kojto 93:e188a91d3eaa 809 /**
Kojto 93:e188a91d3eaa 810 * @brief Disable the NORSRAM device access.
Kojto 93:e188a91d3eaa 811 * @param __INSTANCE__: FMC_NORSRAM Instance
Kojto 93:e188a91d3eaa 812 * @param __BANK__: FMC_NORSRAM Bank
Kojto 93:e188a91d3eaa 813 * @retval None
Kojto 93:e188a91d3eaa 814 */
Kojto 93:e188a91d3eaa 815 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
Kojto 93:e188a91d3eaa 816 /**
Kojto 93:e188a91d3eaa 817 * @}
Kojto 93:e188a91d3eaa 818 */
Kojto 93:e188a91d3eaa 819
Kojto 99:dbbf35b96557 820 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
Kojto 93:e188a91d3eaa 821 * @brief macros to handle NAND device enable/disable
Kojto 93:e188a91d3eaa 822 * @{
Kojto 93:e188a91d3eaa 823 */
Kojto 110:165afa46840b 824 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 99:dbbf35b96557 825 /**
Kojto 99:dbbf35b96557 826 * @brief Enable the NAND device access.
Kojto 99:dbbf35b96557 827 * @param __INSTANCE__: FMC_NAND Instance
Kojto 99:dbbf35b96557 828 * @param __BANK__: FMC_NAND Bank
Kojto 99:dbbf35b96557 829 * @retval None
Kojto 99:dbbf35b96557 830 */
Kojto 99:dbbf35b96557 831 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
Kojto 99:dbbf35b96557 832
Kojto 99:dbbf35b96557 833 /**
Kojto 99:dbbf35b96557 834 * @brief Disable the NAND device access.
Kojto 99:dbbf35b96557 835 * @param __INSTANCE__: FMC_NAND Instance
Kojto 99:dbbf35b96557 836 * @param __BANK__: FMC_NAND Bank
Kojto 99:dbbf35b96557 837 * @retval None
Kojto 99:dbbf35b96557 838 */
Kojto 99:dbbf35b96557 839 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
Kojto 99:dbbf35b96557 840 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 93:e188a91d3eaa 841 /**
Kojto 93:e188a91d3eaa 842 * @brief Enable the NAND device access.
Kojto 93:e188a91d3eaa 843 * @param __INSTANCE__: FMC_NAND Instance
Kojto 93:e188a91d3eaa 844 * @param __BANK__: FMC_NAND Bank
Kojto 93:e188a91d3eaa 845 * @retval None
Kojto 93:e188a91d3eaa 846 */
Kojto 93:e188a91d3eaa 847 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
Kojto 93:e188a91d3eaa 848 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
Kojto 93:e188a91d3eaa 849
Kojto 93:e188a91d3eaa 850 /**
Kojto 93:e188a91d3eaa 851 * @brief Disable the NAND device access.
Kojto 93:e188a91d3eaa 852 * @param __INSTANCE__: FMC_NAND Instance
Kojto 93:e188a91d3eaa 853 * @param __BANK__: FMC_NAND Bank
Kojto 93:e188a91d3eaa 854 * @retval None
Kojto 93:e188a91d3eaa 855 */
Kojto 93:e188a91d3eaa 856 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
Kojto 93:e188a91d3eaa 857 ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
Kojto 99:dbbf35b96557 858
Kojto 110:165afa46840b 859 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
Kojto 93:e188a91d3eaa 860 /**
Kojto 93:e188a91d3eaa 861 * @}
Kojto 93:e188a91d3eaa 862 */
Kojto 99:dbbf35b96557 863 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 99:dbbf35b96557 864 /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
Kojto 93:e188a91d3eaa 865 * @brief macros to handle SRAM read/write operations
Kojto 93:e188a91d3eaa 866 * @{
Kojto 93:e188a91d3eaa 867 */
Kojto 93:e188a91d3eaa 868 /**
Kojto 93:e188a91d3eaa 869 * @brief Enable the PCCARD device access.
Kojto 93:e188a91d3eaa 870 * @param __INSTANCE__: FMC_PCCARD Instance
Kojto 93:e188a91d3eaa 871 * @retval None
Kojto 93:e188a91d3eaa 872 */
Kojto 93:e188a91d3eaa 873 #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
Kojto 93:e188a91d3eaa 874
Kojto 93:e188a91d3eaa 875 /**
Kojto 93:e188a91d3eaa 876 * @brief Disable the PCCARD device access.
Kojto 93:e188a91d3eaa 877 * @param __INSTANCE__: FMC_PCCARD Instance
Kojto 93:e188a91d3eaa 878 * @retval None
Kojto 93:e188a91d3eaa 879 */
Kojto 93:e188a91d3eaa 880 #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
Kojto 93:e188a91d3eaa 881 /**
Kojto 93:e188a91d3eaa 882 * @}
Kojto 93:e188a91d3eaa 883 */
Kojto 99:dbbf35b96557 884 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 99:dbbf35b96557 885
Kojto 99:dbbf35b96557 886 /** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
Kojto 99:dbbf35b96557 887 * @brief macros to handle FMC flags and interrupts
Kojto 93:e188a91d3eaa 888 * @{
Kojto 93:e188a91d3eaa 889 */
Kojto 110:165afa46840b 890 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 99:dbbf35b96557 891 /**
Kojto 99:dbbf35b96557 892 * @brief Enable the NAND device interrupt.
Kojto 99:dbbf35b96557 893 * @param __INSTANCE__: FMC_NAND instance
Kojto 99:dbbf35b96557 894 * @param __BANK__: FMC_NAND Bank
Kojto 99:dbbf35b96557 895 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 99:dbbf35b96557 896 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 897 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 898 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 899 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 900 * @retval None
Kojto 99:dbbf35b96557 901 */
Kojto 99:dbbf35b96557 902 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
Kojto 93:e188a91d3eaa 903
Kojto 93:e188a91d3eaa 904 /**
Kojto 99:dbbf35b96557 905 * @brief Disable the NAND device interrupt.
Kojto 99:dbbf35b96557 906 * @param __INSTANCE__: FMC_NAND Instance
Kojto 99:dbbf35b96557 907 * @param __BANK__: FMC_NAND Bank
Kojto 99:dbbf35b96557 908 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 99:dbbf35b96557 909 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 910 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 99:dbbf35b96557 911 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 99:dbbf35b96557 912 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 99:dbbf35b96557 913 * @retval None
Kojto 99:dbbf35b96557 914 */
Kojto 99:dbbf35b96557 915 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
Kojto 99:dbbf35b96557 916
Kojto 99:dbbf35b96557 917 /**
Kojto 99:dbbf35b96557 918 * @brief Get flag status of the NAND device.
Kojto 99:dbbf35b96557 919 * @param __INSTANCE__: FMC_NAND Instance
Kojto 99:dbbf35b96557 920 * @param __BANK__: FMC_NAND Bank
Kojto 99:dbbf35b96557 921 * @param __FLAG__: FMC_NAND flag
Kojto 99:dbbf35b96557 922 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 923 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 924 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 925 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 926 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 927 * @retval The state of FLAG (SET or RESET).
Kojto 99:dbbf35b96557 928 */
Kojto 99:dbbf35b96557 929 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
Kojto 99:dbbf35b96557 930 /**
Kojto 99:dbbf35b96557 931 * @brief Clear flag status of the NAND device.
Kojto 99:dbbf35b96557 932 * @param __INSTANCE__: FMC_NAND Instance
Kojto 99:dbbf35b96557 933 * @param __BANK__: FMC_NAND Bank
Kojto 99:dbbf35b96557 934 * @param __FLAG__: FMC_NAND flag
Kojto 99:dbbf35b96557 935 * This parameter can be any combination of the following values:
Kojto 99:dbbf35b96557 936 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 99:dbbf35b96557 937 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 99:dbbf35b96557 938 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 99:dbbf35b96557 939 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 99:dbbf35b96557 940 * @retval None
Kojto 99:dbbf35b96557 941 */
Kojto 99:dbbf35b96557 942 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
Kojto 99:dbbf35b96557 943 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 99:dbbf35b96557 944 /**
Kojto 93:e188a91d3eaa 945 * @brief Enable the NAND device interrupt.
Kojto 93:e188a91d3eaa 946 * @param __INSTANCE__: FMC_NAND instance
Kojto 93:e188a91d3eaa 947 * @param __BANK__: FMC_NAND Bank
Kojto 93:e188a91d3eaa 948 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 93:e188a91d3eaa 949 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 950 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 93:e188a91d3eaa 951 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 93:e188a91d3eaa 952 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 93:e188a91d3eaa 953 * @retval None
Kojto 93:e188a91d3eaa 954 */
Kojto 93:e188a91d3eaa 955 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
Kojto 93:e188a91d3eaa 956 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
Kojto 93:e188a91d3eaa 957
Kojto 93:e188a91d3eaa 958 /**
Kojto 93:e188a91d3eaa 959 * @brief Disable the NAND device interrupt.
Kojto 99:dbbf35b96557 960 * @param __INSTANCE__: FMC_NAND Instance
Kojto 93:e188a91d3eaa 961 * @param __BANK__: FMC_NAND Bank
Kojto 93:e188a91d3eaa 962 * @param __INTERRUPT__: FMC_NAND interrupt
Kojto 93:e188a91d3eaa 963 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 964 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 93:e188a91d3eaa 965 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 93:e188a91d3eaa 966 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 93:e188a91d3eaa 967 * @retval None
Kojto 93:e188a91d3eaa 968 */
Kojto 93:e188a91d3eaa 969 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto 93:e188a91d3eaa 970 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto 93:e188a91d3eaa 971
Kojto 93:e188a91d3eaa 972 /**
Kojto 93:e188a91d3eaa 973 * @brief Get flag status of the NAND device.
Kojto 99:dbbf35b96557 974 * @param __INSTANCE__: FMC_NAND Instance
Kojto 93:e188a91d3eaa 975 * @param __BANK__: FMC_NAND Bank
Kojto 93:e188a91d3eaa 976 * @param __FLAG__: FMC_NAND flag
Kojto 93:e188a91d3eaa 977 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 978 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 93:e188a91d3eaa 979 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 93:e188a91d3eaa 980 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 93:e188a91d3eaa 981 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 93:e188a91d3eaa 982 * @retval The state of FLAG (SET or RESET).
Kojto 93:e188a91d3eaa 983 */
Kojto 93:e188a91d3eaa 984 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto 93:e188a91d3eaa 985 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
Kojto 93:e188a91d3eaa 986 /**
Kojto 93:e188a91d3eaa 987 * @brief Clear flag status of the NAND device.
Kojto 99:dbbf35b96557 988 * @param __INSTANCE__: FMC_NAND Instance
Kojto 93:e188a91d3eaa 989 * @param __BANK__: FMC_NAND Bank
Kojto 93:e188a91d3eaa 990 * @param __FLAG__: FMC_NAND flag
Kojto 93:e188a91d3eaa 991 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 992 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 93:e188a91d3eaa 993 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 93:e188a91d3eaa 994 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 93:e188a91d3eaa 995 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 93:e188a91d3eaa 996 * @retval None
Kojto 93:e188a91d3eaa 997 */
Kojto 93:e188a91d3eaa 998 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto 99:dbbf35b96557 999 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto 110:165afa46840b 1000 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
Kojto 99:dbbf35b96557 1001
Kojto 99:dbbf35b96557 1002 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 93:e188a91d3eaa 1003 /**
Kojto 93:e188a91d3eaa 1004 * @brief Enable the PCCARD device interrupt.
Kojto 93:e188a91d3eaa 1005 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 93:e188a91d3eaa 1006 * @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto 93:e188a91d3eaa 1007 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1008 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 93:e188a91d3eaa 1009 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 93:e188a91d3eaa 1010 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 93:e188a91d3eaa 1011 * @retval None
Kojto 93:e188a91d3eaa 1012 */
Kojto 93:e188a91d3eaa 1013 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
Kojto 93:e188a91d3eaa 1014
Kojto 93:e188a91d3eaa 1015 /**
Kojto 93:e188a91d3eaa 1016 * @brief Disable the PCCARD device interrupt.
Kojto 93:e188a91d3eaa 1017 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 93:e188a91d3eaa 1018 * @param __INTERRUPT__: FMC_PCCARD interrupt
Kojto 93:e188a91d3eaa 1019 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1020 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto 93:e188a91d3eaa 1021 * @arg FMC_IT_LEVEL: Interrupt level.
Kojto 93:e188a91d3eaa 1022 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto 93:e188a91d3eaa 1023 * @retval None
Kojto 93:e188a91d3eaa 1024 */
Kojto 93:e188a91d3eaa 1025 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
Kojto 93:e188a91d3eaa 1026
Kojto 93:e188a91d3eaa 1027 /**
Kojto 93:e188a91d3eaa 1028 * @brief Get flag status of the PCCARD device.
Kojto 93:e188a91d3eaa 1029 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 93:e188a91d3eaa 1030 * @param __FLAG__: FMC_PCCARD flag
Kojto 93:e188a91d3eaa 1031 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1032 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 93:e188a91d3eaa 1033 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 93:e188a91d3eaa 1034 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 93:e188a91d3eaa 1035 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 93:e188a91d3eaa 1036 * @retval The state of FLAG (SET or RESET).
Kojto 93:e188a91d3eaa 1037 */
Kojto 93:e188a91d3eaa 1038 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
Kojto 93:e188a91d3eaa 1039
Kojto 93:e188a91d3eaa 1040 /**
Kojto 93:e188a91d3eaa 1041 * @brief Clear flag status of the PCCARD device.
Kojto 93:e188a91d3eaa 1042 * @param __INSTANCE__: FMC_PCCARD instance
Kojto 93:e188a91d3eaa 1043 * @param __FLAG__: FMC_PCCARD flag
Kojto 93:e188a91d3eaa 1044 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1045 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto 93:e188a91d3eaa 1046 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto 93:e188a91d3eaa 1047 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto 93:e188a91d3eaa 1048 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto 93:e188a91d3eaa 1049 * @retval None
Kojto 93:e188a91d3eaa 1050 */
Kojto 93:e188a91d3eaa 1051 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto 99:dbbf35b96557 1052 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
Kojto 99:dbbf35b96557 1053
Kojto 93:e188a91d3eaa 1054 /**
Kojto 93:e188a91d3eaa 1055 * @brief Enable the SDRAM device interrupt.
Kojto 93:e188a91d3eaa 1056 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 93:e188a91d3eaa 1057 * @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto 93:e188a91d3eaa 1058 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1059 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto 93:e188a91d3eaa 1060 * @retval None
Kojto 93:e188a91d3eaa 1061 */
Kojto 93:e188a91d3eaa 1062 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
Kojto 93:e188a91d3eaa 1063
Kojto 93:e188a91d3eaa 1064 /**
Kojto 93:e188a91d3eaa 1065 * @brief Disable the SDRAM device interrupt.
Kojto 93:e188a91d3eaa 1066 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 93:e188a91d3eaa 1067 * @param __INTERRUPT__: FMC_SDRAM interrupt
Kojto 93:e188a91d3eaa 1068 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1069 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
Kojto 93:e188a91d3eaa 1070 * @retval None
Kojto 93:e188a91d3eaa 1071 */
Kojto 93:e188a91d3eaa 1072 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
Kojto 93:e188a91d3eaa 1073
Kojto 93:e188a91d3eaa 1074 /**
Kojto 93:e188a91d3eaa 1075 * @brief Get flag status of the SDRAM device.
Kojto 93:e188a91d3eaa 1076 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 93:e188a91d3eaa 1077 * @param __FLAG__: FMC_SDRAM flag
Kojto 93:e188a91d3eaa 1078 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1079 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
Kojto 93:e188a91d3eaa 1080 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
Kojto 93:e188a91d3eaa 1081 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
Kojto 93:e188a91d3eaa 1082 * @retval The state of FLAG (SET or RESET).
Kojto 93:e188a91d3eaa 1083 */
Kojto 93:e188a91d3eaa 1084 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
Kojto 93:e188a91d3eaa 1085
Kojto 93:e188a91d3eaa 1086 /**
Kojto 93:e188a91d3eaa 1087 * @brief Clear flag status of the SDRAM device.
Kojto 93:e188a91d3eaa 1088 * @param __INSTANCE__: FMC_SDRAM instance
Kojto 93:e188a91d3eaa 1089 * @param __FLAG__: FMC_SDRAM flag
Kojto 93:e188a91d3eaa 1090 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 1091 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
Kojto 93:e188a91d3eaa 1092 * @retval None
Kojto 93:e188a91d3eaa 1093 */
Kojto 93:e188a91d3eaa 1094 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
Kojto 93:e188a91d3eaa 1095 /**
Kojto 93:e188a91d3eaa 1096 * @}
Kojto 99:dbbf35b96557 1097 */
Kojto 99:dbbf35b96557 1098
Kojto 99:dbbf35b96557 1099 /** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto 99:dbbf35b96557 1100 * @{
Kojto 99:dbbf35b96557 1101 */
Kojto 99:dbbf35b96557 1102 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
Kojto 99:dbbf35b96557 1103 ((BANK) == FMC_NORSRAM_BANK2) || \
Kojto 99:dbbf35b96557 1104 ((BANK) == FMC_NORSRAM_BANK3) || \
Kojto 99:dbbf35b96557 1105 ((BANK) == FMC_NORSRAM_BANK4))
Kojto 99:dbbf35b96557 1106
Kojto 99:dbbf35b96557 1107 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
Kojto 99:dbbf35b96557 1108 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
Kojto 99:dbbf35b96557 1109
Kojto 99:dbbf35b96557 1110 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
Kojto 99:dbbf35b96557 1111 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
Kojto 99:dbbf35b96557 1112 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
Kojto 99:dbbf35b96557 1113
Kojto 99:dbbf35b96557 1114 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 1115 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
Kojto 99:dbbf35b96557 1116 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto 99:dbbf35b96557 1117
Kojto 99:dbbf35b96557 1118 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
Kojto 99:dbbf35b96557 1119 ((__MODE__) == FMC_ACCESS_MODE_B) || \
Kojto 99:dbbf35b96557 1120 ((__MODE__) == FMC_ACCESS_MODE_C) || \
Kojto 99:dbbf35b96557 1121 ((__MODE__) == FMC_ACCESS_MODE_D))
Kojto 99:dbbf35b96557 1122
Kojto 99:dbbf35b96557 1123 #define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \
Kojto 99:dbbf35b96557 1124 ((BANK) == FMC_NAND_BANK3))
Kojto 99:dbbf35b96557 1125
Kojto 99:dbbf35b96557 1126 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
Kojto 99:dbbf35b96557 1127 ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto 99:dbbf35b96557 1128
Kojto 99:dbbf35b96557 1129 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 1130 ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto 99:dbbf35b96557 1131
Kojto 99:dbbf35b96557 1132 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
Kojto 99:dbbf35b96557 1133 ((STATE) == FMC_NAND_ECC_ENABLE))
Kojto 99:dbbf35b96557 1134
Kojto 99:dbbf35b96557 1135 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
Kojto 99:dbbf35b96557 1136 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
Kojto 99:dbbf35b96557 1137 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
Kojto 99:dbbf35b96557 1138 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
Kojto 99:dbbf35b96557 1139 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
Kojto 99:dbbf35b96557 1140 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto 99:dbbf35b96557 1141
Kojto 99:dbbf35b96557 1142 #define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 1143
Kojto 99:dbbf35b96557 1144 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 1145
Kojto 99:dbbf35b96557 1146 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 1147
Kojto 99:dbbf35b96557 1148 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 1149
Kojto 99:dbbf35b96557 1150 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 1151
Kojto 99:dbbf35b96557 1152 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
Kojto 99:dbbf35b96557 1153
Kojto 99:dbbf35b96557 1154 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
Kojto 99:dbbf35b96557 1155
Kojto 99:dbbf35b96557 1156 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
Kojto 99:dbbf35b96557 1157
Kojto 99:dbbf35b96557 1158 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
Kojto 99:dbbf35b96557 1159
Kojto 99:dbbf35b96557 1160 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
Kojto 99:dbbf35b96557 1161
Kojto 99:dbbf35b96557 1162 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 1163 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
Kojto 99:dbbf35b96557 1164
Kojto 99:dbbf35b96557 1165 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
Kojto 99:dbbf35b96557 1166 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto 99:dbbf35b96557 1167
Kojto 110:165afa46840b 1168 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 99:dbbf35b96557 1169 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
Kojto 110:165afa46840b 1170 ((__MODE__) == FMC_WRAP_MODE_ENABLE))
Kojto 110:165afa46840b 1171 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 99:dbbf35b96557 1172
Kojto 99:dbbf35b96557 1173 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
Kojto 99:dbbf35b96557 1174 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
Kojto 99:dbbf35b96557 1175
Kojto 99:dbbf35b96557 1176 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
Kojto 99:dbbf35b96557 1177 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
Kojto 99:dbbf35b96557 1178
Kojto 99:dbbf35b96557 1179 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
Kojto 99:dbbf35b96557 1180 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
Kojto 99:dbbf35b96557 1181
Kojto 99:dbbf35b96557 1182 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
Kojto 99:dbbf35b96557 1183 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
Kojto 99:dbbf35b96557 1184
Kojto 99:dbbf35b96557 1185 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
Kojto 99:dbbf35b96557 1186 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto 99:dbbf35b96557 1187
Kojto 99:dbbf35b96557 1188 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
Kojto 99:dbbf35b96557 1189 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
Kojto 99:dbbf35b96557 1190
Kojto 99:dbbf35b96557 1191 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
Kojto 99:dbbf35b96557 1192 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto 99:dbbf35b96557 1193
Kojto 99:dbbf35b96557 1194 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
Kojto 99:dbbf35b96557 1195
Kojto 99:dbbf35b96557 1196 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
Kojto 99:dbbf35b96557 1197
Kojto 99:dbbf35b96557 1198 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
Kojto 99:dbbf35b96557 1199
Kojto 99:dbbf35b96557 1200 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
Kojto 99:dbbf35b96557 1201
Kojto 99:dbbf35b96557 1202 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
Kojto 99:dbbf35b96557 1203
Kojto 99:dbbf35b96557 1204 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
Kojto 99:dbbf35b96557 1205
Kojto 99:dbbf35b96557 1206 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
Kojto 99:dbbf35b96557 1207 ((BANK) == FMC_SDRAM_BANK2))
Kojto 99:dbbf35b96557 1208
Kojto 99:dbbf35b96557 1209 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
Kojto 99:dbbf35b96557 1210 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
Kojto 99:dbbf35b96557 1211 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
Kojto 99:dbbf35b96557 1212 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
Kojto 99:dbbf35b96557 1213
Kojto 99:dbbf35b96557 1214 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
Kojto 99:dbbf35b96557 1215 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
Kojto 99:dbbf35b96557 1216 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
Kojto 99:dbbf35b96557 1217
Kojto 99:dbbf35b96557 1218 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
Kojto 99:dbbf35b96557 1219 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
Kojto 99:dbbf35b96557 1220 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
Kojto 99:dbbf35b96557 1221
Kojto 99:dbbf35b96557 1222 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
Kojto 99:dbbf35b96557 1223 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
Kojto 99:dbbf35b96557 1224
Kojto 99:dbbf35b96557 1225
Kojto 99:dbbf35b96557 1226 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
Kojto 99:dbbf35b96557 1227 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
Kojto 99:dbbf35b96557 1228 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
Kojto 99:dbbf35b96557 1229
Kojto 99:dbbf35b96557 1230 #define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \
Kojto 99:dbbf35b96557 1231 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \
Kojto 99:dbbf35b96557 1232 ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
Kojto 99:dbbf35b96557 1233
Kojto 99:dbbf35b96557 1234 #define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \
Kojto 99:dbbf35b96557 1235 ((RBURST) == FMC_SDRAM_RBURST_ENABLE))
Kojto 99:dbbf35b96557 1236
Kojto 99:dbbf35b96557 1237
Kojto 99:dbbf35b96557 1238 #define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \
Kojto 99:dbbf35b96557 1239 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \
Kojto 99:dbbf35b96557 1240 ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
Kojto 99:dbbf35b96557 1241
Kojto 99:dbbf35b96557 1242 #define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 99:dbbf35b96557 1243
Kojto 99:dbbf35b96557 1244 #define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 99:dbbf35b96557 1245
Kojto 99:dbbf35b96557 1246 #define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto 99:dbbf35b96557 1247
Kojto 99:dbbf35b96557 1248 #define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 99:dbbf35b96557 1249
Kojto 99:dbbf35b96557 1250 #define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
Kojto 99:dbbf35b96557 1251
Kojto 99:dbbf35b96557 1252 #define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 99:dbbf35b96557 1253
Kojto 99:dbbf35b96557 1254 #define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
Kojto 99:dbbf35b96557 1255
Kojto 99:dbbf35b96557 1256 #define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \
Kojto 99:dbbf35b96557 1257 ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \
Kojto 99:dbbf35b96557 1258 ((COMMAND) == FMC_SDRAM_CMD_PALL) || \
Kojto 99:dbbf35b96557 1259 ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
Kojto 99:dbbf35b96557 1260 ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \
Kojto 99:dbbf35b96557 1261 ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
Kojto 99:dbbf35b96557 1262 ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
Kojto 99:dbbf35b96557 1263
Kojto 99:dbbf35b96557 1264 #define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \
Kojto 99:dbbf35b96557 1265 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \
Kojto 99:dbbf35b96557 1266 ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
Kojto 99:dbbf35b96557 1267
Kojto 99:dbbf35b96557 1268 #define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
Kojto 99:dbbf35b96557 1269
Kojto 99:dbbf35b96557 1270 #define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
Kojto 99:dbbf35b96557 1271
Kojto 99:dbbf35b96557 1272 #define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
Kojto 99:dbbf35b96557 1273
Kojto 99:dbbf35b96557 1274 #define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
Kojto 99:dbbf35b96557 1275
Kojto 99:dbbf35b96557 1276 #define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
Kojto 99:dbbf35b96557 1277 ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
Kojto 99:dbbf35b96557 1278
Kojto 110:165afa46840b 1279 #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 99:dbbf35b96557 1280 #define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \
Kojto 99:dbbf35b96557 1281 ((SIZE) == FMC_PAGE_SIZE_128) || \
Kojto 99:dbbf35b96557 1282 ((SIZE) == FMC_PAGE_SIZE_256) || \
Kojto 99:dbbf35b96557 1283 ((SIZE) == FMC_PAGE_SIZE_1024))
Kojto 99:dbbf35b96557 1284
Kojto 99:dbbf35b96557 1285 #define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \
Kojto 99:dbbf35b96557 1286 ((FIFO) == FMC_WRITE_FIFO_ENABLE))
Kojto 110:165afa46840b 1287 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 1288
Kojto 99:dbbf35b96557 1289 /**
Kojto 99:dbbf35b96557 1290 * @}
Kojto 99:dbbf35b96557 1291 */
Kojto 99:dbbf35b96557 1292
Kojto 99:dbbf35b96557 1293 /**
Kojto 99:dbbf35b96557 1294 * @}
Kojto 93:e188a91d3eaa 1295 */
Kojto 93:e188a91d3eaa 1296
Kojto 99:dbbf35b96557 1297 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 1298 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
Kojto 99:dbbf35b96557 1299 * @{
Kojto 99:dbbf35b96557 1300 */
Kojto 93:e188a91d3eaa 1301
Kojto 99:dbbf35b96557 1302 /** @defgroup FMC_LL_NORSRAM NOR SRAM
Kojto 99:dbbf35b96557 1303 * @{
Kojto 99:dbbf35b96557 1304 */
Kojto 99:dbbf35b96557 1305 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto 99:dbbf35b96557 1306 * @{
Kojto 99:dbbf35b96557 1307 */
Kojto 93:e188a91d3eaa 1308 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
Kojto 93:e188a91d3eaa 1309 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
Kojto 93:e188a91d3eaa 1310 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
Kojto 93:e188a91d3eaa 1311 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
Kojto 99:dbbf35b96557 1312 /**
Kojto 99:dbbf35b96557 1313 * @}
Kojto 99:dbbf35b96557 1314 */
Kojto 93:e188a91d3eaa 1315
Kojto 99:dbbf35b96557 1316 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto 99:dbbf35b96557 1317 * @{
Kojto 99:dbbf35b96557 1318 */
Kojto 93:e188a91d3eaa 1319 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 93:e188a91d3eaa 1320 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 1321 /**
Kojto 99:dbbf35b96557 1322 * @}
Kojto 99:dbbf35b96557 1323 */
Kojto 99:dbbf35b96557 1324 /**
Kojto 99:dbbf35b96557 1325 * @}
Kojto 99:dbbf35b96557 1326 */
Kojto 93:e188a91d3eaa 1327
Kojto 99:dbbf35b96557 1328 /** @defgroup FMC_LL_NAND NAND
Kojto 99:dbbf35b96557 1329 * @{
Kojto 99:dbbf35b96557 1330 */
Kojto 99:dbbf35b96557 1331 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto 99:dbbf35b96557 1332 * @{
Kojto 99:dbbf35b96557 1333 */
Kojto 93:e188a91d3eaa 1334 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
Kojto 93:e188a91d3eaa 1335 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 93:e188a91d3eaa 1336 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
Kojto 93:e188a91d3eaa 1337 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 1338 /**
Kojto 99:dbbf35b96557 1339 * @}
Kojto 99:dbbf35b96557 1340 */
Kojto 93:e188a91d3eaa 1341
Kojto 99:dbbf35b96557 1342 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto 99:dbbf35b96557 1343 * @{
Kojto 99:dbbf35b96557 1344 */
Kojto 93:e188a91d3eaa 1345 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 93:e188a91d3eaa 1346 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto 93:e188a91d3eaa 1347 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
Kojto 93:e188a91d3eaa 1348
Kojto 99:dbbf35b96557 1349 /**
Kojto 99:dbbf35b96557 1350 * @}
Kojto 99:dbbf35b96557 1351 */
Kojto 99:dbbf35b96557 1352 /**
Kojto 99:dbbf35b96557 1353 * @}
Kojto 99:dbbf35b96557 1354 */
Kojto 99:dbbf35b96557 1355 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 99:dbbf35b96557 1356 /** @defgroup FMC_LL_PCCARD PCCARD
Kojto 99:dbbf35b96557 1357 * @{
Kojto 99:dbbf35b96557 1358 */
Kojto 99:dbbf35b96557 1359 /** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto 99:dbbf35b96557 1360 * @{
Kojto 99:dbbf35b96557 1361 */
Kojto 93:e188a91d3eaa 1362 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
Kojto 93:e188a91d3eaa 1363 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 93:e188a91d3eaa 1364 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 93:e188a91d3eaa 1365 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
Kojto 93:e188a91d3eaa 1366 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
Kojto 99:dbbf35b96557 1367 /**
Kojto 99:dbbf35b96557 1368 * @}
Kojto 99:dbbf35b96557 1369 */
Kojto 99:dbbf35b96557 1370 /**
Kojto 99:dbbf35b96557 1371 * @}
Kojto 99:dbbf35b96557 1372 */
Kojto 99:dbbf35b96557 1373 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 93:e188a91d3eaa 1374
Kojto 99:dbbf35b96557 1375 /** @defgroup FMC_LL_SDRAM SDRAM
Kojto 99:dbbf35b96557 1376 * @{
Kojto 99:dbbf35b96557 1377 */
Kojto 99:dbbf35b96557 1378 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
Kojto 99:dbbf35b96557 1379 * @{
Kojto 99:dbbf35b96557 1380 */
Kojto 93:e188a91d3eaa 1381 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
Kojto 93:e188a91d3eaa 1382 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
Kojto 93:e188a91d3eaa 1383 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 99:dbbf35b96557 1384 /**
Kojto 99:dbbf35b96557 1385 * @}
Kojto 99:dbbf35b96557 1386 */
Kojto 93:e188a91d3eaa 1387
Kojto 99:dbbf35b96557 1388 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
Kojto 99:dbbf35b96557 1389 * @{
Kojto 99:dbbf35b96557 1390 */
Kojto 93:e188a91d3eaa 1391 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 93:e188a91d3eaa 1392 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 93:e188a91d3eaa 1393 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
Kojto 93:e188a91d3eaa 1394 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
Kojto 93:e188a91d3eaa 1395 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
Kojto 93:e188a91d3eaa 1396 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto 93:e188a91d3eaa 1397 /**
Kojto 93:e188a91d3eaa 1398 * @}
Kojto 99:dbbf35b96557 1399 */
Kojto 99:dbbf35b96557 1400 /**
Kojto 99:dbbf35b96557 1401 * @}
Kojto 99:dbbf35b96557 1402 */
Kojto 93:e188a91d3eaa 1403
Kojto 93:e188a91d3eaa 1404 /**
Kojto 93:e188a91d3eaa 1405 * @}
Kojto 93:e188a91d3eaa 1406 */
Kojto 99:dbbf35b96557 1407
Kojto 110:165afa46840b 1408 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 1409 /**
Kojto 99:dbbf35b96557 1410 * @}
Kojto 99:dbbf35b96557 1411 */
Kojto 99:dbbf35b96557 1412
Kojto 99:dbbf35b96557 1413 /**
Kojto 99:dbbf35b96557 1414 * @}
Kojto 99:dbbf35b96557 1415 */
Kojto 93:e188a91d3eaa 1416 #ifdef __cplusplus
Kojto 93:e188a91d3eaa 1417 }
Kojto 93:e188a91d3eaa 1418 #endif
Kojto 93:e188a91d3eaa 1419
Kojto 93:e188a91d3eaa 1420 #endif /* __STM32F4xx_LL_FMC_H */
Kojto 93:e188a91d3eaa 1421
Kojto 93:e188a91d3eaa 1422 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/