CC3000HostDriver for device TI CC3000 some changes were made due to mbed compiler and the use of void*
spi.cpp@0:9cb694f00b7b, 2013-08-02 (annotated)
- Committer:
- dflet
- Date:
- Fri Aug 02 15:06:15 2013 +0000
- Revision:
- 0:9cb694f00b7b
First commit TI CC3000HostDriver library
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
dflet | 0:9cb694f00b7b | 1 | |
dflet | 0:9cb694f00b7b | 2 | /***************************************************************************** |
dflet | 0:9cb694f00b7b | 3 | * |
dflet | 0:9cb694f00b7b | 4 | * spi.c - CC3000 Host Driver Implementation. |
dflet | 0:9cb694f00b7b | 5 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
dflet | 0:9cb694f00b7b | 6 | * |
dflet | 0:9cb694f00b7b | 7 | * Redistribution and use in source and binary forms, with or without |
dflet | 0:9cb694f00b7b | 8 | * modification, are permitted provided that the following conditions |
dflet | 0:9cb694f00b7b | 9 | * are met: |
dflet | 0:9cb694f00b7b | 10 | * |
dflet | 0:9cb694f00b7b | 11 | * Redistributions of source code must retain the above copyright |
dflet | 0:9cb694f00b7b | 12 | * notice, this list of conditions and the following disclaimer. |
dflet | 0:9cb694f00b7b | 13 | * |
dflet | 0:9cb694f00b7b | 14 | * Redistributions in binary form must reproduce the above copyright |
dflet | 0:9cb694f00b7b | 15 | * notice, this list of conditions and the following disclaimer in the |
dflet | 0:9cb694f00b7b | 16 | * documentation and/or other materials provided with the |
dflet | 0:9cb694f00b7b | 17 | * distribution. |
dflet | 0:9cb694f00b7b | 18 | * |
dflet | 0:9cb694f00b7b | 19 | * Neither the name of Texas Instruments Incorporated nor the names of |
dflet | 0:9cb694f00b7b | 20 | * its contributors may be used to endorse or promote products derived |
dflet | 0:9cb694f00b7b | 21 | * from this software without specific prior written permission. |
dflet | 0:9cb694f00b7b | 22 | * |
dflet | 0:9cb694f00b7b | 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
dflet | 0:9cb694f00b7b | 24 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
dflet | 0:9cb694f00b7b | 25 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
dflet | 0:9cb694f00b7b | 26 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
dflet | 0:9cb694f00b7b | 27 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
dflet | 0:9cb694f00b7b | 28 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
dflet | 0:9cb694f00b7b | 29 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
dflet | 0:9cb694f00b7b | 30 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
dflet | 0:9cb694f00b7b | 31 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
dflet | 0:9cb694f00b7b | 32 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
dflet | 0:9cb694f00b7b | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
dflet | 0:9cb694f00b7b | 34 | * |
dflet | 0:9cb694f00b7b | 35 | *****************************************************************************/ |
dflet | 0:9cb694f00b7b | 36 | |
dflet | 0:9cb694f00b7b | 37 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 38 | // |
dflet | 0:9cb694f00b7b | 39 | //! \addtogroup link_buff_api |
dflet | 0:9cb694f00b7b | 40 | //! @{ |
dflet | 0:9cb694f00b7b | 41 | // |
dflet | 0:9cb694f00b7b | 42 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 43 | #include "hci.h" |
dflet | 0:9cb694f00b7b | 44 | #include "spi.h" |
dflet | 0:9cb694f00b7b | 45 | #include "evnt_handler.h" |
dflet | 0:9cb694f00b7b | 46 | #include "mbed.h" |
dflet | 0:9cb694f00b7b | 47 | #include "CC3000Core.h" |
dflet | 0:9cb694f00b7b | 48 | //#include "board.h" |
dflet | 0:9cb694f00b7b | 49 | //#include <msp430.h> |
dflet | 0:9cb694f00b7b | 50 | |
dflet | 0:9cb694f00b7b | 51 | SPI spi(p5, p6, p7); // mosi, miso, sclk |
dflet | 0:9cb694f00b7b | 52 | DigitalOut cs(p8); // chip select |
dflet | 0:9cb694f00b7b | 53 | |
dflet | 0:9cb694f00b7b | 54 | |
dflet | 0:9cb694f00b7b | 55 | #define READ 3 |
dflet | 0:9cb694f00b7b | 56 | #define WRITE 1 |
dflet | 0:9cb694f00b7b | 57 | |
dflet | 0:9cb694f00b7b | 58 | #define HI(value) (((value) & 0xFF00) >> 8) |
dflet | 0:9cb694f00b7b | 59 | #define LO(value) ((value) & 0x00FF) |
dflet | 0:9cb694f00b7b | 60 | |
dflet | 0:9cb694f00b7b | 61 | #define ASSERT_CS() (cs = 0)//(RF_CS_OUT &= ~RF_CS) |
dflet | 0:9cb694f00b7b | 62 | |
dflet | 0:9cb694f00b7b | 63 | #define DEASSERT_CS() (cs = 1)//(RF_CS_OUT |= RF_CS) |
dflet | 0:9cb694f00b7b | 64 | |
dflet | 0:9cb694f00b7b | 65 | #define HEADERS_SIZE_EVNT (SPI_HEADER_SIZE + 5) |
dflet | 0:9cb694f00b7b | 66 | |
dflet | 0:9cb694f00b7b | 67 | #define SPI_HEADER_SIZE (5) |
dflet | 0:9cb694f00b7b | 68 | |
dflet | 0:9cb694f00b7b | 69 | #define eSPI_STATE_POWERUP (0) |
dflet | 0:9cb694f00b7b | 70 | #define eSPI_STATE_INITIALIZED (1) |
dflet | 0:9cb694f00b7b | 71 | #define eSPI_STATE_IDLE (2) |
dflet | 0:9cb694f00b7b | 72 | #define eSPI_STATE_WRITE_IRQ (3) |
dflet | 0:9cb694f00b7b | 73 | #define eSPI_STATE_WRITE_FIRST_PORTION (4) |
dflet | 0:9cb694f00b7b | 74 | #define eSPI_STATE_WRITE_EOT (5) |
dflet | 0:9cb694f00b7b | 75 | #define eSPI_STATE_READ_IRQ (6) |
dflet | 0:9cb694f00b7b | 76 | #define eSPI_STATE_READ_FIRST_PORTION (7) |
dflet | 0:9cb694f00b7b | 77 | #define eSPI_STATE_READ_EOT (8) |
dflet | 0:9cb694f00b7b | 78 | |
dflet | 0:9cb694f00b7b | 79 | |
dflet | 0:9cb694f00b7b | 80 | typedef struct |
dflet | 0:9cb694f00b7b | 81 | { |
dflet | 0:9cb694f00b7b | 82 | gcSpiHandleRx SPIRxHandler; |
dflet | 0:9cb694f00b7b | 83 | unsigned short usTxPacketLength; |
dflet | 0:9cb694f00b7b | 84 | unsigned short usRxPacketLength; |
dflet | 0:9cb694f00b7b | 85 | unsigned long ulSpiState; |
dflet | 0:9cb694f00b7b | 86 | unsigned char *pTxPacket; |
dflet | 0:9cb694f00b7b | 87 | unsigned char *pRxPacket; |
dflet | 0:9cb694f00b7b | 88 | |
dflet | 0:9cb694f00b7b | 89 | }tSpiInformation; |
dflet | 0:9cb694f00b7b | 90 | |
dflet | 0:9cb694f00b7b | 91 | |
dflet | 0:9cb694f00b7b | 92 | tSpiInformation sSpiInformation; |
dflet | 0:9cb694f00b7b | 93 | |
dflet | 0:9cb694f00b7b | 94 | |
dflet | 0:9cb694f00b7b | 95 | // buffer for 5 bytes of SPI HEADER |
dflet | 0:9cb694f00b7b | 96 | unsigned char tSpiReadHeader[] = {READ, 0, 0, 0, 0}; |
dflet | 0:9cb694f00b7b | 97 | |
dflet | 0:9cb694f00b7b | 98 | |
dflet | 0:9cb694f00b7b | 99 | void SpiWriteDataSynchronous(unsigned char *data, unsigned short size); |
dflet | 0:9cb694f00b7b | 100 | void SpiWriteAsync(const unsigned char *data, unsigned short size); |
dflet | 0:9cb694f00b7b | 101 | void SpiPauseSpi(void); |
dflet | 0:9cb694f00b7b | 102 | void SpiResumeSpi(void); |
dflet | 0:9cb694f00b7b | 103 | void SSIContReadOperation(void); |
dflet | 0:9cb694f00b7b | 104 | |
dflet | 0:9cb694f00b7b | 105 | // The magic number that resides at the end of the TX/RX buffer (1 byte after |
dflet | 0:9cb694f00b7b | 106 | // the allocated size) for the purpose of detection of the overrun. The location |
dflet | 0:9cb694f00b7b | 107 | // of the memory where the magic number resides shall never be written. In case |
dflet | 0:9cb694f00b7b | 108 | // it is written - the overrun occurred and either receive function or send |
dflet | 0:9cb694f00b7b | 109 | // function will stuck forever. |
dflet | 0:9cb694f00b7b | 110 | #define CC3000_BUFFER_MAGIC_NUMBER (0xDE) |
dflet | 0:9cb694f00b7b | 111 | |
dflet | 0:9cb694f00b7b | 112 | /////////////////////////////////////////////////////////////////////////////////////////////////////////// |
dflet | 0:9cb694f00b7b | 113 | //__no_init is used to prevent the buffer initialization in order to prevent hardware WDT expiration /// |
dflet | 0:9cb694f00b7b | 114 | // before entering to 'main()'. /// |
dflet | 0:9cb694f00b7b | 115 | //for every IDE, different syntax exists : 1. __CCS__ for CCS v5 /// |
dflet | 0:9cb694f00b7b | 116 | // 2. __IAR_SYSTEMS_ICC__ for IAR Embedded Workbench /// |
dflet | 0:9cb694f00b7b | 117 | // *CCS does not initialize variables - therefore, __no_init is not needed. /// |
dflet | 0:9cb694f00b7b | 118 | /////////////////////////////////////////////////////////////////////////////////////////////////////////// |
dflet | 0:9cb694f00b7b | 119 | |
dflet | 0:9cb694f00b7b | 120 | //#ifdef __CCS__ |
dflet | 0:9cb694f00b7b | 121 | char spi_buffer[CC3000_RX_BUFFER_SIZE]; |
dflet | 0:9cb694f00b7b | 122 | |
dflet | 0:9cb694f00b7b | 123 | //#elif __IAR_SYSTEMS_ICC__ |
dflet | 0:9cb694f00b7b | 124 | //__no_init char spi_buffer[CC3000_RX_BUFFER_SIZE]; |
dflet | 0:9cb694f00b7b | 125 | //#endif |
dflet | 0:9cb694f00b7b | 126 | |
dflet | 0:9cb694f00b7b | 127 | //#ifdef __CCS__ |
dflet | 0:9cb694f00b7b | 128 | unsigned char wlan_tx_buffer[CC3000_TX_BUFFER_SIZE]; |
dflet | 0:9cb694f00b7b | 129 | |
dflet | 0:9cb694f00b7b | 130 | //#elif __IAR_SYSTEMS_ICC__ |
dflet | 0:9cb694f00b7b | 131 | //__no_init unsigned char wlan_tx_buffer[CC3000_TX_BUFFER_SIZE]; |
dflet | 0:9cb694f00b7b | 132 | //#endif |
dflet | 0:9cb694f00b7b | 133 | |
dflet | 0:9cb694f00b7b | 134 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 135 | // |
dflet | 0:9cb694f00b7b | 136 | //! SpiCleanGPIOISR |
dflet | 0:9cb694f00b7b | 137 | //! |
dflet | 0:9cb694f00b7b | 138 | //! \param none |
dflet | 0:9cb694f00b7b | 139 | //! |
dflet | 0:9cb694f00b7b | 140 | //! \return none |
dflet | 0:9cb694f00b7b | 141 | //! |
dflet | 0:9cb694f00b7b | 142 | //! \brief This function get the reason for the GPIO interrupt and clear |
dflet | 0:9cb694f00b7b | 143 | //! corresponding interrupt flag |
dflet | 0:9cb694f00b7b | 144 | // |
dflet | 0:9cb694f00b7b | 145 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 146 | void |
dflet | 0:9cb694f00b7b | 147 | SpiCleanGPIOISR(void) |
dflet | 0:9cb694f00b7b | 148 | { |
dflet | 0:9cb694f00b7b | 149 | WlanInterruptDisable(); |
dflet | 0:9cb694f00b7b | 150 | //SPI_IFG_PORT &= ~SPI_IRQ_PIN; |
dflet | 0:9cb694f00b7b | 151 | } |
dflet | 0:9cb694f00b7b | 152 | |
dflet | 0:9cb694f00b7b | 153 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 154 | // |
dflet | 0:9cb694f00b7b | 155 | //! SpiClose |
dflet | 0:9cb694f00b7b | 156 | //! |
dflet | 0:9cb694f00b7b | 157 | //! @param none |
dflet | 0:9cb694f00b7b | 158 | //! |
dflet | 0:9cb694f00b7b | 159 | //! @return none |
dflet | 0:9cb694f00b7b | 160 | //! |
dflet | 0:9cb694f00b7b | 161 | //! @brief Close Spi interface |
dflet | 0:9cb694f00b7b | 162 | // |
dflet | 0:9cb694f00b7b | 163 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 164 | void |
dflet | 0:9cb694f00b7b | 165 | SpiClose(void) |
dflet | 0:9cb694f00b7b | 166 | { |
dflet | 0:9cb694f00b7b | 167 | if (sSpiInformation.pRxPacket) |
dflet | 0:9cb694f00b7b | 168 | { |
dflet | 0:9cb694f00b7b | 169 | sSpiInformation.pRxPacket = 0; |
dflet | 0:9cb694f00b7b | 170 | } |
dflet | 0:9cb694f00b7b | 171 | |
dflet | 0:9cb694f00b7b | 172 | // Disable Interrupt |
dflet | 0:9cb694f00b7b | 173 | tSLInformation.WlanInterruptDisable(); |
dflet | 0:9cb694f00b7b | 174 | } |
dflet | 0:9cb694f00b7b | 175 | |
dflet | 0:9cb694f00b7b | 176 | |
dflet | 0:9cb694f00b7b | 177 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 178 | // |
dflet | 0:9cb694f00b7b | 179 | //! SpiOpen |
dflet | 0:9cb694f00b7b | 180 | //! |
dflet | 0:9cb694f00b7b | 181 | //! @param none |
dflet | 0:9cb694f00b7b | 182 | //! |
dflet | 0:9cb694f00b7b | 183 | //! @return none |
dflet | 0:9cb694f00b7b | 184 | //! |
dflet | 0:9cb694f00b7b | 185 | //! @brief Open Spi interface |
dflet | 0:9cb694f00b7b | 186 | // |
dflet | 0:9cb694f00b7b | 187 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 188 | void |
dflet | 0:9cb694f00b7b | 189 | SpiOpen(gcSpiHandleRx pfRxHandler) |
dflet | 0:9cb694f00b7b | 190 | { |
dflet | 0:9cb694f00b7b | 191 | sSpiInformation.ulSpiState = eSPI_STATE_POWERUP; |
dflet | 0:9cb694f00b7b | 192 | sSpiInformation.SPIRxHandler = pfRxHandler; |
dflet | 0:9cb694f00b7b | 193 | sSpiInformation.usTxPacketLength = 0; |
dflet | 0:9cb694f00b7b | 194 | sSpiInformation.pTxPacket = NULL; |
dflet | 0:9cb694f00b7b | 195 | sSpiInformation.pRxPacket = (unsigned char *)spi_buffer; |
dflet | 0:9cb694f00b7b | 196 | sSpiInformation.usRxPacketLength = 0; |
dflet | 0:9cb694f00b7b | 197 | spi_buffer[CC3000_RX_BUFFER_SIZE - 1] = CC3000_BUFFER_MAGIC_NUMBER; |
dflet | 0:9cb694f00b7b | 198 | wlan_tx_buffer[CC3000_TX_BUFFER_SIZE - 1] = CC3000_BUFFER_MAGIC_NUMBER; |
dflet | 0:9cb694f00b7b | 199 | |
dflet | 0:9cb694f00b7b | 200 | // Enable interrupt on WLAN IRQ pin |
dflet | 0:9cb694f00b7b | 201 | tSLInformation.WlanInterruptEnable(); |
dflet | 0:9cb694f00b7b | 202 | } |
dflet | 0:9cb694f00b7b | 203 | |
dflet | 0:9cb694f00b7b | 204 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 205 | // |
dflet | 0:9cb694f00b7b | 206 | //! init_spi |
dflet | 0:9cb694f00b7b | 207 | //! |
dflet | 0:9cb694f00b7b | 208 | //! @param none |
dflet | 0:9cb694f00b7b | 209 | //! |
dflet | 0:9cb694f00b7b | 210 | //! @return none |
dflet | 0:9cb694f00b7b | 211 | //! |
dflet | 0:9cb694f00b7b | 212 | //! @brief initializes an SPI interface |
dflet | 0:9cb694f00b7b | 213 | // |
dflet | 0:9cb694f00b7b | 214 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 215 | |
dflet | 0:9cb694f00b7b | 216 | int init_spi(void) |
dflet | 0:9cb694f00b7b | 217 | { |
dflet | 0:9cb694f00b7b | 218 | |
dflet | 0:9cb694f00b7b | 219 | spi.frequency(16000000); |
dflet | 0:9cb694f00b7b | 220 | spi.format(8, 1); |
dflet | 0:9cb694f00b7b | 221 | cs = 1; |
dflet | 0:9cb694f00b7b | 222 | |
dflet | 0:9cb694f00b7b | 223 | //UCB0CTL1 |= UCSWRST; // Put state machine in reset |
dflet | 0:9cb694f00b7b | 224 | //UCB0CTL0 = UCMSB + UCMST + UCMODE_0 + UCSYNC; // 3-pin, 8-bit SPI master |
dflet | 0:9cb694f00b7b | 225 | |
dflet | 0:9cb694f00b7b | 226 | //UCB0CTL1 = UCSWRST + UCSSEL_2; // Use SMCLK, keep RESET |
dflet | 0:9cb694f00b7b | 227 | |
dflet | 0:9cb694f00b7b | 228 | // Set SPI clock |
dflet | 0:9cb694f00b7b | 229 | //UCB0CTL1 |= UCSWRST; // Put state machine in reset |
dflet | 0:9cb694f00b7b | 230 | //UCB0BR0 = 2; // f_UCxCLK = 25MHz/2 = 12.5MHz |
dflet | 0:9cb694f00b7b | 231 | //UCB0BR1 = 0; |
dflet | 0:9cb694f00b7b | 232 | //UCB0CTL1 &= ~UCSWRST; |
dflet | 0:9cb694f00b7b | 233 | |
dflet | 0:9cb694f00b7b | 234 | return(ESUCCESS); |
dflet | 0:9cb694f00b7b | 235 | } |
dflet | 0:9cb694f00b7b | 236 | |
dflet | 0:9cb694f00b7b | 237 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 238 | // |
dflet | 0:9cb694f00b7b | 239 | //! SpiFirstWrite |
dflet | 0:9cb694f00b7b | 240 | //! |
dflet | 0:9cb694f00b7b | 241 | //! @param ucBuf buffer to write |
dflet | 0:9cb694f00b7b | 242 | //! @param usLength buffer's length |
dflet | 0:9cb694f00b7b | 243 | //! |
dflet | 0:9cb694f00b7b | 244 | //! @return none |
dflet | 0:9cb694f00b7b | 245 | //! |
dflet | 0:9cb694f00b7b | 246 | //! @brief enter point for first write flow |
dflet | 0:9cb694f00b7b | 247 | // |
dflet | 0:9cb694f00b7b | 248 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 249 | long |
dflet | 0:9cb694f00b7b | 250 | SpiFirstWrite(unsigned char *ucBuf, unsigned short usLength) |
dflet | 0:9cb694f00b7b | 251 | { |
dflet | 0:9cb694f00b7b | 252 | // workaround for first transaction |
dflet | 0:9cb694f00b7b | 253 | ASSERT_CS(); |
dflet | 0:9cb694f00b7b | 254 | |
dflet | 0:9cb694f00b7b | 255 | // Assuming we are running on 24 MHz ~50 micro delay is 1200 cycles; |
dflet | 0:9cb694f00b7b | 256 | //__delay_cycles(1200); |
dflet | 0:9cb694f00b7b | 257 | wait_us(50); |
dflet | 0:9cb694f00b7b | 258 | |
dflet | 0:9cb694f00b7b | 259 | // SPI writes first 4 bytes of data |
dflet | 0:9cb694f00b7b | 260 | SpiWriteDataSynchronous(ucBuf, 4); |
dflet | 0:9cb694f00b7b | 261 | |
dflet | 0:9cb694f00b7b | 262 | //__delay_cycles(1200); |
dflet | 0:9cb694f00b7b | 263 | wait_us(50); |
dflet | 0:9cb694f00b7b | 264 | SpiWriteDataSynchronous(ucBuf + 4, usLength - 4); |
dflet | 0:9cb694f00b7b | 265 | |
dflet | 0:9cb694f00b7b | 266 | // From this point on - operate in a regular way |
dflet | 0:9cb694f00b7b | 267 | sSpiInformation.ulSpiState = eSPI_STATE_IDLE; |
dflet | 0:9cb694f00b7b | 268 | |
dflet | 0:9cb694f00b7b | 269 | DEASSERT_CS(); |
dflet | 0:9cb694f00b7b | 270 | |
dflet | 0:9cb694f00b7b | 271 | return(0); |
dflet | 0:9cb694f00b7b | 272 | } |
dflet | 0:9cb694f00b7b | 273 | |
dflet | 0:9cb694f00b7b | 274 | |
dflet | 0:9cb694f00b7b | 275 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 276 | // |
dflet | 0:9cb694f00b7b | 277 | //! SpiWrite |
dflet | 0:9cb694f00b7b | 278 | //! |
dflet | 0:9cb694f00b7b | 279 | //! @param pUserBuffer buffer to write |
dflet | 0:9cb694f00b7b | 280 | //! @param usLength buffer's length |
dflet | 0:9cb694f00b7b | 281 | //! |
dflet | 0:9cb694f00b7b | 282 | //! @return none |
dflet | 0:9cb694f00b7b | 283 | //! |
dflet | 0:9cb694f00b7b | 284 | //! @brief Spi write operation |
dflet | 0:9cb694f00b7b | 285 | // |
dflet | 0:9cb694f00b7b | 286 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 287 | long |
dflet | 0:9cb694f00b7b | 288 | SpiWrite(unsigned char *pUserBuffer, unsigned short usLength) |
dflet | 0:9cb694f00b7b | 289 | { |
dflet | 0:9cb694f00b7b | 290 | unsigned char ucPad = 0; |
dflet | 0:9cb694f00b7b | 291 | |
dflet | 0:9cb694f00b7b | 292 | // Figure out the total length of the packet in order to figure out if there |
dflet | 0:9cb694f00b7b | 293 | // is padding or not |
dflet | 0:9cb694f00b7b | 294 | if(!(usLength & 0x0001)) |
dflet | 0:9cb694f00b7b | 295 | { |
dflet | 0:9cb694f00b7b | 296 | ucPad++; |
dflet | 0:9cb694f00b7b | 297 | } |
dflet | 0:9cb694f00b7b | 298 | |
dflet | 0:9cb694f00b7b | 299 | pUserBuffer[0] = WRITE; |
dflet | 0:9cb694f00b7b | 300 | pUserBuffer[1] = HI(usLength + ucPad); |
dflet | 0:9cb694f00b7b | 301 | pUserBuffer[2] = LO(usLength + ucPad); |
dflet | 0:9cb694f00b7b | 302 | pUserBuffer[3] = 0; |
dflet | 0:9cb694f00b7b | 303 | pUserBuffer[4] = 0; |
dflet | 0:9cb694f00b7b | 304 | |
dflet | 0:9cb694f00b7b | 305 | usLength += (SPI_HEADER_SIZE + ucPad); |
dflet | 0:9cb694f00b7b | 306 | |
dflet | 0:9cb694f00b7b | 307 | // The magic number that resides at the end of the TX/RX buffer (1 byte after |
dflet | 0:9cb694f00b7b | 308 | // the allocated size) for the purpose of detection of the overrun. If the |
dflet | 0:9cb694f00b7b | 309 | // magic number is overwritten - buffer overrun occurred - and we will stuck |
dflet | 0:9cb694f00b7b | 310 | // here forever! |
dflet | 0:9cb694f00b7b | 311 | if (wlan_tx_buffer[CC3000_TX_BUFFER_SIZE - 1] != CC3000_BUFFER_MAGIC_NUMBER) |
dflet | 0:9cb694f00b7b | 312 | { |
dflet | 0:9cb694f00b7b | 313 | while (1) |
dflet | 0:9cb694f00b7b | 314 | { |
dflet | 0:9cb694f00b7b | 315 | printf("Buffer over run\r\n"); |
dflet | 0:9cb694f00b7b | 316 | }// ; |
dflet | 0:9cb694f00b7b | 317 | } |
dflet | 0:9cb694f00b7b | 318 | |
dflet | 0:9cb694f00b7b | 319 | if (sSpiInformation.ulSpiState == eSPI_STATE_POWERUP) |
dflet | 0:9cb694f00b7b | 320 | { |
dflet | 0:9cb694f00b7b | 321 | while (sSpiInformation.ulSpiState != eSPI_STATE_INITIALIZED) |
dflet | 0:9cb694f00b7b | 322 | ; |
dflet | 0:9cb694f00b7b | 323 | } |
dflet | 0:9cb694f00b7b | 324 | |
dflet | 0:9cb694f00b7b | 325 | if (sSpiInformation.ulSpiState == eSPI_STATE_INITIALIZED) |
dflet | 0:9cb694f00b7b | 326 | { |
dflet | 0:9cb694f00b7b | 327 | // This is time for first TX/RX transactions over SPI: the IRQ is down - |
dflet | 0:9cb694f00b7b | 328 | // so need to send read buffer size command |
dflet | 0:9cb694f00b7b | 329 | SpiFirstWrite(pUserBuffer, usLength); |
dflet | 0:9cb694f00b7b | 330 | |
dflet | 0:9cb694f00b7b | 331 | } |
dflet | 0:9cb694f00b7b | 332 | else |
dflet | 0:9cb694f00b7b | 333 | { |
dflet | 0:9cb694f00b7b | 334 | // We need to prevent here race that can occur in case 2 back to back |
dflet | 0:9cb694f00b7b | 335 | // packets are sent to the device, so the state will move to IDLE and once |
dflet | 0:9cb694f00b7b | 336 | //again to not IDLE due to IRQ |
dflet | 0:9cb694f00b7b | 337 | tSLInformation.WlanInterruptDisable(); |
dflet | 0:9cb694f00b7b | 338 | |
dflet | 0:9cb694f00b7b | 339 | while (sSpiInformation.ulSpiState != eSPI_STATE_IDLE) |
dflet | 0:9cb694f00b7b | 340 | { |
dflet | 0:9cb694f00b7b | 341 | printf("Wait for eSPI_STATE_IDLE\r\n"); |
dflet | 0:9cb694f00b7b | 342 | } |
dflet | 0:9cb694f00b7b | 343 | |
dflet | 0:9cb694f00b7b | 344 | sSpiInformation.ulSpiState = eSPI_STATE_WRITE_IRQ; |
dflet | 0:9cb694f00b7b | 345 | sSpiInformation.pTxPacket = pUserBuffer; |
dflet | 0:9cb694f00b7b | 346 | sSpiInformation.usTxPacketLength = usLength; |
dflet | 0:9cb694f00b7b | 347 | |
dflet | 0:9cb694f00b7b | 348 | // Assert the CS line and wait till SSI IRQ line is active and then |
dflet | 0:9cb694f00b7b | 349 | // initialize write operation |
dflet | 0:9cb694f00b7b | 350 | ASSERT_CS(); |
dflet | 0:9cb694f00b7b | 351 | |
dflet | 0:9cb694f00b7b | 352 | // Re-enable IRQ - if it was not disabled - this is not a problem... |
dflet | 0:9cb694f00b7b | 353 | tSLInformation.WlanInterruptEnable(); |
dflet | 0:9cb694f00b7b | 354 | |
dflet | 0:9cb694f00b7b | 355 | // check for a missing interrupt between the CS assertion and enabling back the interrupts |
dflet | 0:9cb694f00b7b | 356 | if (tSLInformation.ReadWlanInterruptPin() == 0) |
dflet | 0:9cb694f00b7b | 357 | { |
dflet | 0:9cb694f00b7b | 358 | SpiWriteDataSynchronous(sSpiInformation.pTxPacket, sSpiInformation.usTxPacketLength); |
dflet | 0:9cb694f00b7b | 359 | |
dflet | 0:9cb694f00b7b | 360 | sSpiInformation.ulSpiState = eSPI_STATE_IDLE; |
dflet | 0:9cb694f00b7b | 361 | |
dflet | 0:9cb694f00b7b | 362 | DEASSERT_CS(); |
dflet | 0:9cb694f00b7b | 363 | } |
dflet | 0:9cb694f00b7b | 364 | } |
dflet | 0:9cb694f00b7b | 365 | |
dflet | 0:9cb694f00b7b | 366 | // Due to the fact that we are currently implementing a blocking situation |
dflet | 0:9cb694f00b7b | 367 | // here we will wait till end of transaction |
dflet | 0:9cb694f00b7b | 368 | while (eSPI_STATE_IDLE != sSpiInformation.ulSpiState) |
dflet | 0:9cb694f00b7b | 369 | ; |
dflet | 0:9cb694f00b7b | 370 | |
dflet | 0:9cb694f00b7b | 371 | return(0); |
dflet | 0:9cb694f00b7b | 372 | } |
dflet | 0:9cb694f00b7b | 373 | |
dflet | 0:9cb694f00b7b | 374 | |
dflet | 0:9cb694f00b7b | 375 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 376 | // |
dflet | 0:9cb694f00b7b | 377 | //! SpiWriteDataSynchronous |
dflet | 0:9cb694f00b7b | 378 | //! |
dflet | 0:9cb694f00b7b | 379 | //! @param data buffer to write |
dflet | 0:9cb694f00b7b | 380 | //! @param size buffer's size |
dflet | 0:9cb694f00b7b | 381 | //! |
dflet | 0:9cb694f00b7b | 382 | //! @return none |
dflet | 0:9cb694f00b7b | 383 | //! |
dflet | 0:9cb694f00b7b | 384 | //! @brief Spi write operation |
dflet | 0:9cb694f00b7b | 385 | // |
dflet | 0:9cb694f00b7b | 386 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 387 | void |
dflet | 0:9cb694f00b7b | 388 | SpiWriteDataSynchronous(unsigned char *data, unsigned short size) |
dflet | 0:9cb694f00b7b | 389 | { |
dflet | 0:9cb694f00b7b | 390 | while (size) |
dflet | 0:9cb694f00b7b | 391 | { |
dflet | 0:9cb694f00b7b | 392 | |
dflet | 0:9cb694f00b7b | 393 | //while (!(TXBufferIsEmpty())); |
dflet | 0:9cb694f00b7b | 394 | //UCB0TXBUF = *data; |
dflet | 0:9cb694f00b7b | 395 | spi.write(*data); |
dflet | 0:9cb694f00b7b | 396 | //while (!(RXBufferIsEmpty())); |
dflet | 0:9cb694f00b7b | 397 | //spi.write(0x00); |
dflet | 0:9cb694f00b7b | 398 | //UCB0RXBUF; |
dflet | 0:9cb694f00b7b | 399 | size --; |
dflet | 0:9cb694f00b7b | 400 | //printf("data %x\r\n",*data); |
dflet | 0:9cb694f00b7b | 401 | data++; |
dflet | 0:9cb694f00b7b | 402 | } |
dflet | 0:9cb694f00b7b | 403 | } |
dflet | 0:9cb694f00b7b | 404 | |
dflet | 0:9cb694f00b7b | 405 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 406 | // |
dflet | 0:9cb694f00b7b | 407 | //! SpiReadDataSynchronous |
dflet | 0:9cb694f00b7b | 408 | //! |
dflet | 0:9cb694f00b7b | 409 | //! @param data buffer to read |
dflet | 0:9cb694f00b7b | 410 | //! @param size buffer's size |
dflet | 0:9cb694f00b7b | 411 | //! |
dflet | 0:9cb694f00b7b | 412 | //! @return none |
dflet | 0:9cb694f00b7b | 413 | //! |
dflet | 0:9cb694f00b7b | 414 | //! @brief Spi read operation |
dflet | 0:9cb694f00b7b | 415 | // |
dflet | 0:9cb694f00b7b | 416 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 417 | void |
dflet | 0:9cb694f00b7b | 418 | SpiReadDataSynchronous(unsigned char *data, unsigned short size) |
dflet | 0:9cb694f00b7b | 419 | { |
dflet | 0:9cb694f00b7b | 420 | |
dflet | 0:9cb694f00b7b | 421 | unsigned char *data_to_send = tSpiReadHeader; |
dflet | 0:9cb694f00b7b | 422 | //printf("SPI Read..\r\n"); |
dflet | 0:9cb694f00b7b | 423 | for (int i = 0; i < size; i ++) |
dflet | 0:9cb694f00b7b | 424 | { |
dflet | 0:9cb694f00b7b | 425 | //while (!(TXBufferIsEmpty())); |
dflet | 0:9cb694f00b7b | 426 | //Dummy write to trigger the clock |
dflet | 0:9cb694f00b7b | 427 | //UCB0TXBUF = data_to_send[0]; |
dflet | 0:9cb694f00b7b | 428 | //spi.write(data_to_send[0]); |
dflet | 0:9cb694f00b7b | 429 | //while (!(RXBufferIsEmpty())); |
dflet | 0:9cb694f00b7b | 430 | data[i] = spi.write(data_to_send[0]); |
dflet | 0:9cb694f00b7b | 431 | //data[i] = UCB0RXBUF; |
dflet | 0:9cb694f00b7b | 432 | //printf("SPI Read..%x\r\n",data[i]); |
dflet | 0:9cb694f00b7b | 433 | } |
dflet | 0:9cb694f00b7b | 434 | } |
dflet | 0:9cb694f00b7b | 435 | |
dflet | 0:9cb694f00b7b | 436 | |
dflet | 0:9cb694f00b7b | 437 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 438 | // |
dflet | 0:9cb694f00b7b | 439 | //! SpiReadHeader |
dflet | 0:9cb694f00b7b | 440 | //! |
dflet | 0:9cb694f00b7b | 441 | //! \param buffer |
dflet | 0:9cb694f00b7b | 442 | //! |
dflet | 0:9cb694f00b7b | 443 | //! \return none |
dflet | 0:9cb694f00b7b | 444 | //! |
dflet | 0:9cb694f00b7b | 445 | //! \brief This function enter point for read flow: first we read minimal 5 |
dflet | 0:9cb694f00b7b | 446 | //! SPI header bytes and 5 Event Data bytes |
dflet | 0:9cb694f00b7b | 447 | // |
dflet | 0:9cb694f00b7b | 448 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 449 | void |
dflet | 0:9cb694f00b7b | 450 | SpiReadHeader(void) |
dflet | 0:9cb694f00b7b | 451 | { |
dflet | 0:9cb694f00b7b | 452 | SpiReadDataSynchronous(sSpiInformation.pRxPacket, 10); |
dflet | 0:9cb694f00b7b | 453 | } |
dflet | 0:9cb694f00b7b | 454 | |
dflet | 0:9cb694f00b7b | 455 | |
dflet | 0:9cb694f00b7b | 456 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 457 | // |
dflet | 0:9cb694f00b7b | 458 | //! SpiReadDataCont |
dflet | 0:9cb694f00b7b | 459 | //! |
dflet | 0:9cb694f00b7b | 460 | //! @param None |
dflet | 0:9cb694f00b7b | 461 | //! |
dflet | 0:9cb694f00b7b | 462 | //! @return None |
dflet | 0:9cb694f00b7b | 463 | //! |
dflet | 0:9cb694f00b7b | 464 | //! @brief This function processes received SPI Header and in accordance with |
dflet | 0:9cb694f00b7b | 465 | //! it - continues reading the packet |
dflet | 0:9cb694f00b7b | 466 | // |
dflet | 0:9cb694f00b7b | 467 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 468 | long |
dflet | 0:9cb694f00b7b | 469 | SpiReadDataCont(void) |
dflet | 0:9cb694f00b7b | 470 | { |
dflet | 0:9cb694f00b7b | 471 | long data_to_recv; |
dflet | 0:9cb694f00b7b | 472 | unsigned char *evnt_buff, type; |
dflet | 0:9cb694f00b7b | 473 | |
dflet | 0:9cb694f00b7b | 474 | //determine what type of packet we have |
dflet | 0:9cb694f00b7b | 475 | evnt_buff = sSpiInformation.pRxPacket; |
dflet | 0:9cb694f00b7b | 476 | data_to_recv = 0; |
dflet | 0:9cb694f00b7b | 477 | STREAM_TO_UINT8((char *)(evnt_buff + SPI_HEADER_SIZE), HCI_PACKET_TYPE_OFFSET, type); |
dflet | 0:9cb694f00b7b | 478 | |
dflet | 0:9cb694f00b7b | 479 | switch(type) |
dflet | 0:9cb694f00b7b | 480 | { |
dflet | 0:9cb694f00b7b | 481 | case HCI_TYPE_DATA: |
dflet | 0:9cb694f00b7b | 482 | { |
dflet | 0:9cb694f00b7b | 483 | // We need to read the rest of data.. |
dflet | 0:9cb694f00b7b | 484 | STREAM_TO_UINT16((char *)(evnt_buff + SPI_HEADER_SIZE), HCI_DATA_LENGTH_OFFSET, data_to_recv); |
dflet | 0:9cb694f00b7b | 485 | if (!((HEADERS_SIZE_EVNT + data_to_recv) & 1)) |
dflet | 0:9cb694f00b7b | 486 | { |
dflet | 0:9cb694f00b7b | 487 | data_to_recv++; |
dflet | 0:9cb694f00b7b | 488 | } |
dflet | 0:9cb694f00b7b | 489 | |
dflet | 0:9cb694f00b7b | 490 | if (data_to_recv) |
dflet | 0:9cb694f00b7b | 491 | { |
dflet | 0:9cb694f00b7b | 492 | SpiReadDataSynchronous(evnt_buff + 10, data_to_recv); |
dflet | 0:9cb694f00b7b | 493 | } |
dflet | 0:9cb694f00b7b | 494 | break; |
dflet | 0:9cb694f00b7b | 495 | } |
dflet | 0:9cb694f00b7b | 496 | case HCI_TYPE_EVNT: |
dflet | 0:9cb694f00b7b | 497 | { |
dflet | 0:9cb694f00b7b | 498 | // Calculate the rest length of the data |
dflet | 0:9cb694f00b7b | 499 | STREAM_TO_UINT8((char *)(evnt_buff + SPI_HEADER_SIZE), |
dflet | 0:9cb694f00b7b | 500 | HCI_EVENT_LENGTH_OFFSET, data_to_recv); |
dflet | 0:9cb694f00b7b | 501 | data_to_recv -= 1; |
dflet | 0:9cb694f00b7b | 502 | |
dflet | 0:9cb694f00b7b | 503 | // Add padding byte if needed |
dflet | 0:9cb694f00b7b | 504 | if ((HEADERS_SIZE_EVNT + data_to_recv) & 1) |
dflet | 0:9cb694f00b7b | 505 | { |
dflet | 0:9cb694f00b7b | 506 | |
dflet | 0:9cb694f00b7b | 507 | data_to_recv++; |
dflet | 0:9cb694f00b7b | 508 | } |
dflet | 0:9cb694f00b7b | 509 | |
dflet | 0:9cb694f00b7b | 510 | if (data_to_recv) |
dflet | 0:9cb694f00b7b | 511 | { |
dflet | 0:9cb694f00b7b | 512 | SpiReadDataSynchronous(evnt_buff + 10, data_to_recv); |
dflet | 0:9cb694f00b7b | 513 | } |
dflet | 0:9cb694f00b7b | 514 | |
dflet | 0:9cb694f00b7b | 515 | sSpiInformation.ulSpiState = eSPI_STATE_READ_EOT; |
dflet | 0:9cb694f00b7b | 516 | break; |
dflet | 0:9cb694f00b7b | 517 | } |
dflet | 0:9cb694f00b7b | 518 | } |
dflet | 0:9cb694f00b7b | 519 | |
dflet | 0:9cb694f00b7b | 520 | return (0); |
dflet | 0:9cb694f00b7b | 521 | } |
dflet | 0:9cb694f00b7b | 522 | |
dflet | 0:9cb694f00b7b | 523 | |
dflet | 0:9cb694f00b7b | 524 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 525 | // |
dflet | 0:9cb694f00b7b | 526 | //! SpiPauseSpi |
dflet | 0:9cb694f00b7b | 527 | //! |
dflet | 0:9cb694f00b7b | 528 | //! @param none |
dflet | 0:9cb694f00b7b | 529 | //! |
dflet | 0:9cb694f00b7b | 530 | //! @return none |
dflet | 0:9cb694f00b7b | 531 | //! |
dflet | 0:9cb694f00b7b | 532 | //! @brief Spi pause operation |
dflet | 0:9cb694f00b7b | 533 | // |
dflet | 0:9cb694f00b7b | 534 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 535 | |
dflet | 0:9cb694f00b7b | 536 | void |
dflet | 0:9cb694f00b7b | 537 | SpiPauseSpi(void) |
dflet | 0:9cb694f00b7b | 538 | { |
dflet | 0:9cb694f00b7b | 539 | WlanInterruptDisable(); |
dflet | 0:9cb694f00b7b | 540 | //SPI_IRQ_IE &= ~SPI_IRQ_PIN; |
dflet | 0:9cb694f00b7b | 541 | } |
dflet | 0:9cb694f00b7b | 542 | |
dflet | 0:9cb694f00b7b | 543 | |
dflet | 0:9cb694f00b7b | 544 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 545 | // |
dflet | 0:9cb694f00b7b | 546 | //! SpiResumeSpi |
dflet | 0:9cb694f00b7b | 547 | //! |
dflet | 0:9cb694f00b7b | 548 | //! @param none |
dflet | 0:9cb694f00b7b | 549 | //! |
dflet | 0:9cb694f00b7b | 550 | //! @return none |
dflet | 0:9cb694f00b7b | 551 | //! |
dflet | 0:9cb694f00b7b | 552 | //! @brief Spi resume operation |
dflet | 0:9cb694f00b7b | 553 | // |
dflet | 0:9cb694f00b7b | 554 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 555 | |
dflet | 0:9cb694f00b7b | 556 | void |
dflet | 0:9cb694f00b7b | 557 | SpiResumeSpi(void) |
dflet | 0:9cb694f00b7b | 558 | { |
dflet | 0:9cb694f00b7b | 559 | WlanInterruptEnable(); |
dflet | 0:9cb694f00b7b | 560 | //SPI_IRQ_IE |= SPI_IRQ_PIN; |
dflet | 0:9cb694f00b7b | 561 | } |
dflet | 0:9cb694f00b7b | 562 | |
dflet | 0:9cb694f00b7b | 563 | |
dflet | 0:9cb694f00b7b | 564 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 565 | // |
dflet | 0:9cb694f00b7b | 566 | //! SpiTriggerRxProcessing |
dflet | 0:9cb694f00b7b | 567 | //! |
dflet | 0:9cb694f00b7b | 568 | //! @param none |
dflet | 0:9cb694f00b7b | 569 | //! |
dflet | 0:9cb694f00b7b | 570 | //! @return none |
dflet | 0:9cb694f00b7b | 571 | //! |
dflet | 0:9cb694f00b7b | 572 | //! @brief Spi RX processing |
dflet | 0:9cb694f00b7b | 573 | // |
dflet | 0:9cb694f00b7b | 574 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 575 | void |
dflet | 0:9cb694f00b7b | 576 | SpiTriggerRxProcessing(void) |
dflet | 0:9cb694f00b7b | 577 | { |
dflet | 0:9cb694f00b7b | 578 | |
dflet | 0:9cb694f00b7b | 579 | // Trigger Rx processing |
dflet | 0:9cb694f00b7b | 580 | SpiPauseSpi(); |
dflet | 0:9cb694f00b7b | 581 | DEASSERT_CS(); |
dflet | 0:9cb694f00b7b | 582 | |
dflet | 0:9cb694f00b7b | 583 | // The magic number that resides at the end of the TX/RX buffer (1 byte after |
dflet | 0:9cb694f00b7b | 584 | // the allocated size) for the purpose of detection of the overrun. If the |
dflet | 0:9cb694f00b7b | 585 | // magic number is overwritten - buffer overrun occurred - and we will stuck |
dflet | 0:9cb694f00b7b | 586 | // here forever! |
dflet | 0:9cb694f00b7b | 587 | if (sSpiInformation.pRxPacket[CC3000_RX_BUFFER_SIZE - 1] != CC3000_BUFFER_MAGIC_NUMBER) |
dflet | 0:9cb694f00b7b | 588 | { |
dflet | 0:9cb694f00b7b | 589 | while (1) |
dflet | 0:9cb694f00b7b | 590 | printf("Buffer Over run....\r\n"); |
dflet | 0:9cb694f00b7b | 591 | ; |
dflet | 0:9cb694f00b7b | 592 | } |
dflet | 0:9cb694f00b7b | 593 | |
dflet | 0:9cb694f00b7b | 594 | sSpiInformation.ulSpiState = eSPI_STATE_IDLE; |
dflet | 0:9cb694f00b7b | 595 | sSpiInformation.SPIRxHandler(sSpiInformation.pRxPacket + SPI_HEADER_SIZE); |
dflet | 0:9cb694f00b7b | 596 | } |
dflet | 0:9cb694f00b7b | 597 | |
dflet | 0:9cb694f00b7b | 598 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 599 | // |
dflet | 0:9cb694f00b7b | 600 | //! IntSpiGPIOHandler |
dflet | 0:9cb694f00b7b | 601 | //! |
dflet | 0:9cb694f00b7b | 602 | //! @param none |
dflet | 0:9cb694f00b7b | 603 | //! |
dflet | 0:9cb694f00b7b | 604 | //! @return none |
dflet | 0:9cb694f00b7b | 605 | //! |
dflet | 0:9cb694f00b7b | 606 | //! @brief GPIO A interrupt handler. When the external SSI WLAN device is |
dflet | 0:9cb694f00b7b | 607 | //! ready to interact with Host CPU it generates an interrupt signal. |
dflet | 0:9cb694f00b7b | 608 | //! After that Host CPU has registered this interrupt request |
dflet | 0:9cb694f00b7b | 609 | //! it set the corresponding /CS in active state. |
dflet | 0:9cb694f00b7b | 610 | // |
dflet | 0:9cb694f00b7b | 611 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 612 | //#pragma vector=PORT2_VECTOR |
dflet | 0:9cb694f00b7b | 613 | //__interrupt void IntSpiGPIOHandler(void) |
dflet | 0:9cb694f00b7b | 614 | void IntSpiGPIOHandler(void) |
dflet | 0:9cb694f00b7b | 615 | { |
dflet | 0:9cb694f00b7b | 616 | //switch(__even_in_range(P2IV, P2IV_P2IFG7)) |
dflet | 0:9cb694f00b7b | 617 | //printf("IRQ ISR\r\n"); |
dflet | 0:9cb694f00b7b | 618 | //{ |
dflet | 0:9cb694f00b7b | 619 | //case event: |
dflet | 0:9cb694f00b7b | 620 | if (sSpiInformation.ulSpiState == eSPI_STATE_POWERUP) |
dflet | 0:9cb694f00b7b | 621 | { |
dflet | 0:9cb694f00b7b | 622 | //This means IRQ line was low call a callback of HCI Layer to inform |
dflet | 0:9cb694f00b7b | 623 | //on event |
dflet | 0:9cb694f00b7b | 624 | sSpiInformation.ulSpiState = eSPI_STATE_INITIALIZED; |
dflet | 0:9cb694f00b7b | 625 | } |
dflet | 0:9cb694f00b7b | 626 | else if (sSpiInformation.ulSpiState == eSPI_STATE_IDLE) |
dflet | 0:9cb694f00b7b | 627 | { |
dflet | 0:9cb694f00b7b | 628 | sSpiInformation.ulSpiState = eSPI_STATE_READ_IRQ; |
dflet | 0:9cb694f00b7b | 629 | |
dflet | 0:9cb694f00b7b | 630 | /* IRQ line goes down - we are start reception */ |
dflet | 0:9cb694f00b7b | 631 | ASSERT_CS(); |
dflet | 0:9cb694f00b7b | 632 | |
dflet | 0:9cb694f00b7b | 633 | // Wait for TX/RX Compete which will come as DMA interrupt |
dflet | 0:9cb694f00b7b | 634 | SpiReadHeader(); |
dflet | 0:9cb694f00b7b | 635 | |
dflet | 0:9cb694f00b7b | 636 | sSpiInformation.ulSpiState = eSPI_STATE_READ_EOT; |
dflet | 0:9cb694f00b7b | 637 | |
dflet | 0:9cb694f00b7b | 638 | SSIContReadOperation(); |
dflet | 0:9cb694f00b7b | 639 | } |
dflet | 0:9cb694f00b7b | 640 | else if (sSpiInformation.ulSpiState == eSPI_STATE_WRITE_IRQ) |
dflet | 0:9cb694f00b7b | 641 | { |
dflet | 0:9cb694f00b7b | 642 | SpiWriteDataSynchronous(sSpiInformation.pTxPacket, sSpiInformation.usTxPacketLength); |
dflet | 0:9cb694f00b7b | 643 | |
dflet | 0:9cb694f00b7b | 644 | sSpiInformation.ulSpiState = eSPI_STATE_IDLE; |
dflet | 0:9cb694f00b7b | 645 | |
dflet | 0:9cb694f00b7b | 646 | DEASSERT_CS(); |
dflet | 0:9cb694f00b7b | 647 | } |
dflet | 0:9cb694f00b7b | 648 | // break; |
dflet | 0:9cb694f00b7b | 649 | //default: |
dflet | 0:9cb694f00b7b | 650 | // break; |
dflet | 0:9cb694f00b7b | 651 | //} |
dflet | 0:9cb694f00b7b | 652 | |
dflet | 0:9cb694f00b7b | 653 | } |
dflet | 0:9cb694f00b7b | 654 | |
dflet | 0:9cb694f00b7b | 655 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 656 | // |
dflet | 0:9cb694f00b7b | 657 | //! SSIContReadOperation |
dflet | 0:9cb694f00b7b | 658 | //! |
dflet | 0:9cb694f00b7b | 659 | //! @param none |
dflet | 0:9cb694f00b7b | 660 | //! |
dflet | 0:9cb694f00b7b | 661 | //! @return none |
dflet | 0:9cb694f00b7b | 662 | //! |
dflet | 0:9cb694f00b7b | 663 | //! @brief SPI read operation |
dflet | 0:9cb694f00b7b | 664 | // |
dflet | 0:9cb694f00b7b | 665 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 666 | |
dflet | 0:9cb694f00b7b | 667 | void |
dflet | 0:9cb694f00b7b | 668 | SSIContReadOperation(void) |
dflet | 0:9cb694f00b7b | 669 | { |
dflet | 0:9cb694f00b7b | 670 | // The header was read - continue with the payload read |
dflet | 0:9cb694f00b7b | 671 | if (!SpiReadDataCont()) |
dflet | 0:9cb694f00b7b | 672 | { |
dflet | 0:9cb694f00b7b | 673 | // All the data was read - finalize handling by switching to the task |
dflet | 0:9cb694f00b7b | 674 | // and calling from task Event Handler |
dflet | 0:9cb694f00b7b | 675 | SpiTriggerRxProcessing(); |
dflet | 0:9cb694f00b7b | 676 | } |
dflet | 0:9cb694f00b7b | 677 | } |
dflet | 0:9cb694f00b7b | 678 | |
dflet | 0:9cb694f00b7b | 679 | |
dflet | 0:9cb694f00b7b | 680 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 681 | // |
dflet | 0:9cb694f00b7b | 682 | //! TXBufferIsEmpty |
dflet | 0:9cb694f00b7b | 683 | //! |
dflet | 0:9cb694f00b7b | 684 | //! @param |
dflet | 0:9cb694f00b7b | 685 | //! |
dflet | 0:9cb694f00b7b | 686 | //! @return returns 1 if buffer is empty, 0 otherwise |
dflet | 0:9cb694f00b7b | 687 | //! |
dflet | 0:9cb694f00b7b | 688 | //! @brief Indication if TX SPI buffer is empty |
dflet | 0:9cb694f00b7b | 689 | // |
dflet | 0:9cb694f00b7b | 690 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 691 | |
dflet | 0:9cb694f00b7b | 692 | long TXBufferIsEmpty(void) |
dflet | 0:9cb694f00b7b | 693 | { |
dflet | 0:9cb694f00b7b | 694 | //return (UCB0IFG&UCTXIFG); |
dflet | 0:9cb694f00b7b | 695 | return (1); |
dflet | 0:9cb694f00b7b | 696 | } |
dflet | 0:9cb694f00b7b | 697 | |
dflet | 0:9cb694f00b7b | 698 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 699 | // |
dflet | 0:9cb694f00b7b | 700 | //! RXBufferIsEmpty |
dflet | 0:9cb694f00b7b | 701 | //! |
dflet | 0:9cb694f00b7b | 702 | //! @param none |
dflet | 0:9cb694f00b7b | 703 | //! |
dflet | 0:9cb694f00b7b | 704 | //! @return returns 1 if buffer is empty, 0 otherwise |
dflet | 0:9cb694f00b7b | 705 | //! |
dflet | 0:9cb694f00b7b | 706 | //! @brief Indication if RX SPI buffer is empty |
dflet | 0:9cb694f00b7b | 707 | // |
dflet | 0:9cb694f00b7b | 708 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 709 | |
dflet | 0:9cb694f00b7b | 710 | long RXBufferIsEmpty(void) |
dflet | 0:9cb694f00b7b | 711 | { |
dflet | 0:9cb694f00b7b | 712 | //return (UCB0IFG&UCRXIFG); |
dflet | 0:9cb694f00b7b | 713 | return (0); |
dflet | 0:9cb694f00b7b | 714 | } |
dflet | 0:9cb694f00b7b | 715 | |
dflet | 0:9cb694f00b7b | 716 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 717 | // |
dflet | 0:9cb694f00b7b | 718 | // Close the Doxygen group. |
dflet | 0:9cb694f00b7b | 719 | //! @} |
dflet | 0:9cb694f00b7b | 720 | // |
dflet | 0:9cb694f00b7b | 721 | //***************************************************************************** |
dflet | 0:9cb694f00b7b | 722 |