clemente di caprio / FRDM_MMA8451Q

Added code to manage Orientation, FreeFall and Motion Detection. Data is also available via IRQ.

Dependents:   Test_FRDM_MMA8451Q AccelTest FRDM-KL46-Template KL25Z_Demo ... more

Fork of MMA8451Q by Emilio Monti

MMA8451Q.cpp@9:2aa9b1668d14, 2013-05-28 (annotated)

Committer:
clemente
Date:
Tue May 28 20:19:38 2013 +0000
Revision:
9:2aa9b1668d14
Parent:
8:7e6013f11b10
Child:
10:fa532bf396fb
Data ready using IRQ. Tested: OK.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
samux 1:d2630136d51e 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
samux 1:d2630136d51e 2 *
samux 1:d2630136d51e 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
samux 1:d2630136d51e 4 * and associated documentation files (the "Software"), to deal in the Software without
samux 1:d2630136d51e 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
samux 1:d2630136d51e 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
samux 1:d2630136d51e 7 * Software is furnished to do so, subject to the following conditions:
samux 1:d2630136d51e 8 *
samux 1:d2630136d51e 9 * The above copyright notice and this permission notice shall be included in all copies or
samux 1:d2630136d51e 10 * substantial portions of the Software.
samux 1:d2630136d51e 11 *
samux 1:d2630136d51e 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
samux 1:d2630136d51e 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
samux 1:d2630136d51e 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
samux 1:d2630136d51e 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
samux 1:d2630136d51e 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
samux 1:d2630136d51e 17 */
samux 1:d2630136d51e 18
emilmont 0:6149091f755d 19 #include "MMA8451Q.h"
emilmont 0:6149091f755d 20
samux 1:d2630136d51e 21 #define REG_WHO_AM_I 0x0D
samux 1:d2630136d51e 22 #define REG_CTRL_REG_1 0x2A
clemente 8:7e6013f11b10 23 #define REG_CTRL_REG_2 0x2B
clemente 5:695063448f2a 24 #define REG_CTRL_REG_4 0x2D
clemente 5:695063448f2a 25 #define REG_CTRL_REG_5 0x2E
clemente 5:695063448f2a 26 #define REG_INT_SRC 0x0C
clemente 5:695063448f2a 27 #define REG_FF_MT_CFG 0x15
clemente 5:695063448f2a 28 #define REG_FF_MT_SRC 0x16
clemente 5:695063448f2a 29 #define REG_FF_MT_THS 0x17
clemente 5:695063448f2a 30 #define REG_FF_MT_CNT 0x18
clemente 6:c52175d13e0a 31 #define REG_DBCNTM 0x11
clemente 6:c52175d13e0a 32 #define REG_DBNCE 0x12
clemente 6:c52175d13e0a 33 #define REG_BKFR 0x13
clemente 6:c52175d13e0a 34 #define REG_P_L_THS 0x14
clemente 7:ba0016258d5d 35 #define REG_PL_STATUS 0x10
clemente 7:ba0016258d5d 36
clemente 5:695063448f2a 37 //
emilmont 0:6149091f755d 38 #define REG_OUT_X_MSB 0x01
emilmont 0:6149091f755d 39 #define REG_OUT_Y_MSB 0x03
emilmont 0:6149091f755d 40 #define REG_OUT_Z_MSB 0x05
emilmont 0:6149091f755d 41
samux 1:d2630136d51e 42 #define UINT14_MAX 16383
emilmont 0:6149091f755d 43
clemente 7:ba0016258d5d 44 /** Interrupt schema
clemente 8:7e6013f11b10 45 *
clemente 8:7e6013f11b10 46 * :: The FreeFall and Motion detection share the same IRQ2.
clemente 8:7e6013f11b10 47 *
clemente 8:7e6013f11b10 48 * FreeFall --+ +-- Fall_IRQ -----+
clemente 8:7e6013f11b10 49 * \ / \
clemente 8:7e6013f11b10 50 * +-- MMA8451Q_Int2.fall ---+ +--- user2_fptr
clemente 8:7e6013f11b10 51 * / \ /
clemente 8:7e6013f11b10 52 * Motion ----+ +-- Motion_IRQ ---+
clemente 8:7e6013f11b10 53 *
clemente 8:7e6013f11b10 54 * :: The Orientation Detect use the IRQ1
clemente 8:7e6013f11b10 55 *
clemente 8:7e6013f11b10 56 * Orientation Detect -- MMA8451Q_Int1.fall --- Orientation_IRQ --- user1_fptr
clemente 8:7e6013f11b10 57 *
clemente 9:2aa9b1668d14 58 *
clemente 9:2aa9b1668d14 59 * :: The data ready use the IRQ2
clemente 9:2aa9b1668d14 60 *
clemente 9:2aa9b1668d14 61 * Data Ready -- MMA8451Q_Int2.fall --- DataReady_IRQ --- usr2_fptr
clemente 9:2aa9b1668d14 62 *
clemente 8:7e6013f11b10 63 */
clemente 8:7e6013f11b10 64 void (*user2_fptr)(void); // Pointers to user function called after
clemente 8:7e6013f11b10 65 void (*user1_fptr)(void); // IRQ assertion.
clemente 5:695063448f2a 66
clemente 5:695063448f2a 67 //
clemente 8:7e6013f11b10 68 InterruptIn MMA8451Q_Int1( PTA14); // INT1
clemente 8:7e6013f11b10 69 InterruptIn MMA8451Q_Int2( PTA15); // INT2
clemente 5:695063448f2a 70
emilmont 0:6149091f755d 71 MMA8451Q::MMA8451Q(PinName sda, PinName scl, int addr) : m_i2c(sda, scl), m_addr(addr) {
clemente 8:7e6013f11b10 72
clemente 8:7e6013f11b10 73 MMA8451Q_Int1.fall( NULL);
clemente 8:7e6013f11b10 74 MMA8451Q_Int2.fall( NULL);
clemente 8:7e6013f11b10 75 user2_fptr = NULL;
clemente 8:7e6013f11b10 76 user1_fptr = NULL;
clemente 8:7e6013f11b10 77
clemente 8:7e6013f11b10 78 Reset();
clemente 8:7e6013f11b10 79 Active();
emilmont 0:6149091f755d 80 }
emilmont 0:6149091f755d 81
clemente 5:695063448f2a 82 MMA8451Q::~MMA8451Q()
clemente 5:695063448f2a 83 {
clemente 5:695063448f2a 84 MMA8451Q_Int1.fall( NULL);
clemente 5:695063448f2a 85 MMA8451Q_Int2.fall( NULL);
clemente 7:ba0016258d5d 86 user2_fptr = NULL;
clemente 7:ba0016258d5d 87 user1_fptr = NULL;
clemente 5:695063448f2a 88 }
clemente 5:695063448f2a 89
clemente 8:7e6013f11b10 90 void MMA8451Q::Reset( void)
clemente 5:695063448f2a 91 {
clemente 8:7e6013f11b10 92 // Soft reset
clemente 8:7e6013f11b10 93 uint8_t data[2] = {REG_CTRL_REG_2, 0x40};
clemente 8:7e6013f11b10 94 writeRegs(data, 2);
clemente 8:7e6013f11b10 95 wait( 0.1);
clemente 8:7e6013f11b10 96 }
clemente 8:7e6013f11b10 97
clemente 8:7e6013f11b10 98 void MMA8451Q::FreeFallDetection( void(*fptr)(void))
clemente 8:7e6013f11b10 99 {
clemente 8:7e6013f11b10 100 // Soft Reset
clemente 8:7e6013f11b10 101 Reset();
clemente 8:7e6013f11b10 102
clemente 5:695063448f2a 103 // Example Steps for Configuring Linear Freefall Detection
clemente 5:695063448f2a 104 // X AND Y AND Z < 0.2g using MFF Function, 50 Hz ODR
clemente 5:695063448f2a 105 // Step 1: Put the device in Standby Mode: Register 0x2A CTRL_REG1
clemente 5:695063448f2a 106 unsigned char data[2] = {REG_CTRL_REG_1, 0x20};
clemente 5:695063448f2a 107 writeRegs(data, 2);
clemente 5:695063448f2a 108
clemente 5:695063448f2a 109 // Step 2: Configuration Register set for Freefall Detection enabling “AND” condition, OAE = 0, Enabling X,
clemente 5:695063448f2a 110 // Y, Z and the Latch
clemente 5:695063448f2a 111 data[0] = REG_FF_MT_CFG;
clemente 5:695063448f2a 112 data[1] = 0x01;
clemente 5:695063448f2a 113 writeRegs(data, 2);
clemente 5:695063448f2a 114
clemente 5:695063448f2a 115 // Step 3: Threshold Setting Value for the resulting acceleration < 0.2g
clemente 5:695063448f2a 116 // Note: The step count is 0.063g/count
clemente 5:695063448f2a 117 // • 0.2g/0.063g = 3.17 counts //Round to 3 counts
clemente 5:695063448f2a 118 data[0] = REG_FF_MT_THS;
clemente 5:695063448f2a 119 data[1] = 0x03;
clemente 5:695063448f2a 120 writeRegs(data, 2);
clemente 5:695063448f2a 121
clemente 5:695063448f2a 122 // Step 4: Set the debounce counter to eliminate false positive readings for 50Hz sample rate with a
clemente 5:695063448f2a 123 // requirement of 120 ms timer, assuming Normal Mode.
clemente 5:695063448f2a 124 // Note: 120 ms/20 ms (steps) = 6 counts
clemente 5:695063448f2a 125 data[0] = REG_FF_MT_CNT;
clemente 5:695063448f2a 126 data[1] = 0x06;
clemente 5:695063448f2a 127 writeRegs(data, 2);
clemente 5:695063448f2a 128
clemente 5:695063448f2a 129 // Step 5: Enable Motion/Freefall Interrupt Function in the System (CTRL_REG4)
clemente 5:695063448f2a 130 data[0] = REG_CTRL_REG_4;
clemente 5:695063448f2a 131 data[1] = 0x04;
clemente 5:695063448f2a 132 writeRegs(data, 2);
clemente 5:695063448f2a 133
clemente 5:695063448f2a 134 // Step 6: Route the Motion/Freefall Interrupt Function to INT2 hardware pin (CTRL_REG5)
clemente 5:695063448f2a 135 data[0] = REG_CTRL_REG_5;
clemente 5:695063448f2a 136 data[1] = 0x00;
clemente 5:695063448f2a 137 writeRegs(data, 2);
clemente 5:695063448f2a 138
clemente 5:695063448f2a 139 // Step 7: Put the device in Active Mode, 50 Hz
clemente 5:695063448f2a 140 data[0] = REG_CTRL_REG_1;
clemente 5:695063448f2a 141 data[1] = 0x21;
clemente 5:695063448f2a 142 writeRegs(data, 2);
clemente 5:695063448f2a 143
clemente 7:ba0016258d5d 144 user2_fptr = fptr;
clemente 5:695063448f2a 145 MMA8451Q_Int2.fall( this, &MMA8451Q::Fall_IRQ);
clemente 5:695063448f2a 146 }
clemente 5:695063448f2a 147
clemente 5:695063448f2a 148 void MMA8451Q::Fall_IRQ( void)
clemente 5:695063448f2a 149 {
clemente 5:695063448f2a 150 unsigned char t;
clemente 5:695063448f2a 151
clemente 5:695063448f2a 152 // Determine source of the interrupt by first reading the system interrupt
clemente 5:695063448f2a 153 readRegs( REG_INT_SRC, &t, 1);
clemente 5:695063448f2a 154 //
clemente 5:695063448f2a 155 if ( (t & 0x04) == 0x04) {
clemente 5:695063448f2a 156 // Read the Motion/Freefall Function to clear the interrupt
clemente 5:695063448f2a 157 readRegs( REG_FF_MT_SRC, &t, 1);
clemente 5:695063448f2a 158 // Run the user supplied function
clemente 7:ba0016258d5d 159 user2_fptr();
clemente 5:695063448f2a 160 }
clemente 5:695063448f2a 161 }
clemente 5:695063448f2a 162
clemente 5:695063448f2a 163 void MMA8451Q::MotionDetection( void(*fptr)(void))
clemente 5:695063448f2a 164 {
clemente 8:7e6013f11b10 165 // Soft Reset
clemente 8:7e6013f11b10 166 Reset();
clemente 8:7e6013f11b10 167
clemente 5:695063448f2a 168 // 6.1 Example Steps for Configuring Motion Detection
clemente 5:695063448f2a 169 // X or Y > 3g using MFF Function 4g, 100 Hz ODR, Normal Mode
clemente 5:695063448f2a 170 // Step 1: Put the device into Standby Mode: Register 0x2A CTRL_REG1
clemente 5:695063448f2a 171 unsigned char data[2] = {REG_CTRL_REG_1, 0x18}; // Set the device in 100 Hz ODR, Standby
clemente 5:695063448f2a 172 writeRegs(data, 2);
clemente 5:695063448f2a 173
clemente 5:695063448f2a 174
clemente 5:695063448f2a 175 // Step 2: Set Configuration Register for Motion Detection by setting the “OR” condition OAE = 1, enabling
clemente 5:695063448f2a 176 // X, Y, and the latch
clemente 5:695063448f2a 177 data[0] = REG_FF_MT_CFG;
clemente 5:695063448f2a 178 data[1] = 0xD8;
clemente 5:695063448f2a 179 writeRegs(data, 2);
clemente 5:695063448f2a 180
clemente 5:695063448f2a 181 // Step 3: Threshold Setting Value for the Motion detection of > 2g
clemente 5:695063448f2a 182 // Note: The step count is 0.063g/ count
clemente 8:7e6013f11b10 183 // • 1g/0.063g = 15.8; //Round up to 16
clemente 5:695063448f2a 184 data[0] = REG_FF_MT_THS;
clemente 8:7e6013f11b10 185 data[1] = 0x10;
clemente 5:695063448f2a 186 writeRegs(data, 2);
clemente 5:695063448f2a 187
clemente 5:695063448f2a 188 // Step 4: Set the debounce counter to eliminate false readings for 100 Hz sample rate with a requirement
clemente 5:695063448f2a 189 // of 100 ms timer.
clemente 5:695063448f2a 190 // Note: 100 ms/10 ms (steps) = 10 counts
clemente 5:695063448f2a 191 data[0] = REG_FF_MT_CNT;
clemente 5:695063448f2a 192 data[1] = 0x0A;
clemente 5:695063448f2a 193 writeRegs(data, 2);
clemente 5:695063448f2a 194
clemente 5:695063448f2a 195 // Step 5: Enable Motion/Freefall Interrupt Function in the System (CTRL_REG4)
clemente 5:695063448f2a 196 data[0] = REG_CTRL_REG_4;
clemente 5:695063448f2a 197 data[1] = 0x04;
clemente 5:695063448f2a 198 writeRegs(data, 2);
clemente 5:695063448f2a 199
clemente 7:ba0016258d5d 200 // Step 6: Route the Motion/Freefall Interrupt Function to INT2 hardware pin (CTRL_REG5)
clemente 5:695063448f2a 201 data[0] = REG_CTRL_REG_5;
clemente 7:ba0016258d5d 202 data[1] = 0x00;
clemente 5:695063448f2a 203 writeRegs(data, 2);
clemente 5:695063448f2a 204
clemente 5:695063448f2a 205 // Step 7: Put the device in Active Mode
clemente 5:695063448f2a 206 data[0] = REG_CTRL_REG_1;
clemente 5:695063448f2a 207 data[1] = 0x19;
clemente 5:695063448f2a 208 writeRegs(data, 2);
clemente 5:695063448f2a 209
clemente 7:ba0016258d5d 210 user2_fptr = fptr;
clemente 7:ba0016258d5d 211 MMA8451Q_Int2.fall( this, &MMA8451Q::Motion_IRQ);
clemente 5:695063448f2a 212
clemente 5:695063448f2a 213 }
clemente 5:695063448f2a 214
clemente 5:695063448f2a 215 void MMA8451Q::Motion_IRQ( void)
clemente 5:695063448f2a 216 {
clemente 5:695063448f2a 217 unsigned char t;
clemente 5:695063448f2a 218
clemente 5:695063448f2a 219 // Determine source of the interrupt by first reading the system interrupt
clemente 5:695063448f2a 220 readRegs( REG_INT_SRC, &t, 1);
clemente 5:695063448f2a 221 //
clemente 5:695063448f2a 222 if ( (t & 0x04) == 0x04) {
clemente 5:695063448f2a 223 // Read the Motion/Freefall Function to clear the interrupt
clemente 5:695063448f2a 224 readRegs( REG_FF_MT_SRC, &t, 1);
clemente 5:695063448f2a 225 // Run the user supplied function
clemente 7:ba0016258d5d 226 user2_fptr();
clemente 5:695063448f2a 227 }
clemente 5:695063448f2a 228 }
clemente 5:695063448f2a 229
clemente 7:ba0016258d5d 230 void MMA8451Q::OrientationDetect( void(*fptr)(void))
clemente 6:c52175d13e0a 231 {
clemente 7:ba0016258d5d 232 OrientationDetect( fptr, Z_LOCKOUT_14, Z_BKFR_80, PL_THS_15, PL_HYS_0);
clemente 6:c52175d13e0a 233 }
clemente 6:c52175d13e0a 234
clemente 7:ba0016258d5d 235 void MMA8451Q::OrientationDetect( void(*fptr)(void), unsigned int Z_LockOut, unsigned int Z_BkFr, unsigned int PL_Thsld, unsigned int PL_Hyst)
clemente 6:c52175d13e0a 236 {
clemente 6:c52175d13e0a 237 unsigned char t;
clemente 8:7e6013f11b10 238
clemente 8:7e6013f11b10 239 // Soft Reset
clemente 8:7e6013f11b10 240 Reset();
clemente 8:7e6013f11b10 241
clemente 8:7e6013f11b10 242 // Reset orientation value.
clemente 8:7e6013f11b10 243 OrientationState = 0;
clemente 8:7e6013f11b10 244 OrientationStateUpdated = 0;
clemente 6:c52175d13e0a 245
clemente 6:c52175d13e0a 246 // Step 1: Put the part into Standby Mode
clemente 6:c52175d13e0a 247 Standby();
clemente 6:c52175d13e0a 248
clemente 6:c52175d13e0a 249 // Step 2: Set the data rate to 50 Hz (for example, but can choose any sample rate).
clemente 6:c52175d13e0a 250 readRegs( REG_CTRL_REG_1, &t, 1); // Note: Can combine this step with above
clemente 6:c52175d13e0a 251 t &= 0xC7; // Clear the sample rate bits
clemente 6:c52175d13e0a 252 t |= 0x20; // Set the sample rate bits to 50 Hz
clemente 6:c52175d13e0a 253 unsigned char data[2] = {REG_CTRL_REG_1, t};
clemente 6:c52175d13e0a 254 writeRegs(data, 2); // Write updated value into the register.
clemente 6:c52175d13e0a 255
clemente 6:c52175d13e0a 256
clemente 6:c52175d13e0a 257 // Step 3: Set the PL_EN bit in Register 0x11 PL_CFG. This will enable the orientation detection.
clemente 6:c52175d13e0a 258 readRegs( REG_DBCNTM, &t, 1);
clemente 6:c52175d13e0a 259 data[0] = REG_DBCNTM;
clemente 6:c52175d13e0a 260 data[1] = t | 0x40;
clemente 6:c52175d13e0a 261 writeRegs(data, 2);
clemente 6:c52175d13e0a 262
clemente 6:c52175d13e0a 263 // Step 4: Set the Back/Front Angle trip points in register 0x13 following the table in the data sheet.
clemente 6:c52175d13e0a 264 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 265 // MMA8451Q.
clemente 6:c52175d13e0a 266 readRegs( REG_BKFR, &t, 1);
clemente 6:c52175d13e0a 267 t &= 0x3F; // Clear bit 7 and 6
clemente 6:c52175d13e0a 268 data[0] = REG_BKFR;
clemente 6:c52175d13e0a 269 data[1] = t | Z_BkFr;
clemente 6:c52175d13e0a 270 writeRegs(data, 2); // Write in the updated Back/Front Angle
clemente 6:c52175d13e0a 271
clemente 6:c52175d13e0a 272 // Step 5: Set the Z-Lockout angle trip point in register 0x13 following the table in the data sheet.
clemente 6:c52175d13e0a 273 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 274 // MMA8451Q.
clemente 6:c52175d13e0a 275 readRegs( REG_BKFR, &t, 1);
clemente 6:c52175d13e0a 276 t &= 0xF8; // Clear the last three bits of the register
clemente 6:c52175d13e0a 277 data[0] = REG_BKFR;
clemente 6:c52175d13e0a 278 data[1] = t | Z_LockOut;
clemente 6:c52175d13e0a 279 writeRegs(data, 2); // Write in the updated Z-lockout angle
clemente 6:c52175d13e0a 280
clemente 6:c52175d13e0a 281 // Step 6: Set the Trip Threshold Angle
clemente 6:c52175d13e0a 282 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 283 // MMA8451Q.
clemente 6:c52175d13e0a 284 // Select the angle desired in the table, and,
clemente 6:c52175d13e0a 285 // Enter in the values given in the table for the corresponding angle.
clemente 6:c52175d13e0a 286 // Refer to Figure 7 for the reference frame of the trip angles.
clemente 6:c52175d13e0a 287 readRegs( REG_P_L_THS, &t, 1);
clemente 6:c52175d13e0a 288 t &= 0x07; // Clear the Threshold values
clemente 6:c52175d13e0a 289 data[0] = REG_P_L_THS;
clemente 6:c52175d13e0a 290 data[1] = t | (PL_Thsld<<3);
clemente 6:c52175d13e0a 291 writeRegs(data, 2);
clemente 6:c52175d13e0a 292
clemente 6:c52175d13e0a 293 // Step 7: Set the Hysteresis Angle
clemente 6:c52175d13e0a 294 // NOTE: This register is readable in all versions of MMA845xQ but it is only modifiable in the
clemente 6:c52175d13e0a 295 // MMA8451Q.
clemente 6:c52175d13e0a 296 // Select the hysteresis value based on the desired final trip points (threshold + hysteresis)
clemente 6:c52175d13e0a 297 // Enter in the values given in the table for that corresponding angle.
clemente 6:c52175d13e0a 298 // Note: Care must be taken. Review the final resulting angles. Make sure there isn’t a resulting trip value
clemente 6:c52175d13e0a 299 // greater than 90 or less than 0.
clemente 6:c52175d13e0a 300 // The following are the options for setting the hysteresis.
clemente 6:c52175d13e0a 301 readRegs( REG_P_L_THS, &t, 1);
clemente 6:c52175d13e0a 302 t &= 0xF8; // Clear the Hysteresis values
clemente 6:c52175d13e0a 303 data[0] = REG_P_L_THS;
clemente 6:c52175d13e0a 304 data[1] = t | PL_Hyst;
clemente 6:c52175d13e0a 305 writeRegs(data, 2);
clemente 6:c52175d13e0a 306
clemente 6:c52175d13e0a 307 // Step 8: Register 0x2D, Control Register 4 configures all embedded features for interrupt
clemente 6:c52175d13e0a 308 // detection.
clemente 6:c52175d13e0a 309 // To set this device up to run an interrupt service routine:
clemente 6:c52175d13e0a 310 // Program the Orientation Detection bit in Control Register 4.
clemente 6:c52175d13e0a 311 // Set bit 4 to enable the orientation detection “INT_EN_LNDPRT”.
clemente 6:c52175d13e0a 312 readRegs( REG_CTRL_REG_4, &t, 1);
clemente 6:c52175d13e0a 313 data[0] = REG_CTRL_REG_4;
clemente 6:c52175d13e0a 314 data[1] = t | 0x10; // Set bit 4
clemente 6:c52175d13e0a 315 writeRegs(data, 2);
clemente 6:c52175d13e0a 316
clemente 6:c52175d13e0a 317 // Step 9: Register 0x2E is Control Register 5 which gives the option of routing the interrupt to
clemente 6:c52175d13e0a 318 // either INT1 or INT2
clemente 6:c52175d13e0a 319 // Depending on which interrupt pin is enabled and configured to the processor:
clemente 6:c52175d13e0a 320 // Set bit 4 “INT_CFG_LNDPRT” to configure INT1, or,
clemente 6:c52175d13e0a 321 // Leave the bit clear to configure INT2.
clemente 6:c52175d13e0a 322 readRegs( REG_CTRL_REG_5, &t, 1);
clemente 6:c52175d13e0a 323 data[0] = REG_CTRL_REG_5;
clemente 6:c52175d13e0a 324 data[1] = t | 0x10; // Set bit 4 to choose the interrupt to route to INT1
clemente 6:c52175d13e0a 325 writeRegs(data, 2);
clemente 6:c52175d13e0a 326
clemente 6:c52175d13e0a 327 // Step 10: Set the debounce counter in register 0x12
clemente 6:c52175d13e0a 328 // This value will scale depending on the application-specific required ODR.
clemente 6:c52175d13e0a 329 // If the device is set to go to sleep, reset the debounce counter before the device goes to sleep. This setting
clemente 6:c52175d13e0a 330 // helps avoid long delays since the debounce will always scale with the current sample rate. The debounce
clemente 6:c52175d13e0a 331 // can be set between 50 ms - 100 ms to avoid long delays.
clemente 6:c52175d13e0a 332 data[0] = REG_DBNCE;
clemente 6:c52175d13e0a 333 data[1] = 0x05; // This sets the debounce counter to 100 ms at 50 Hz
clemente 6:c52175d13e0a 334 writeRegs(data, 2);
clemente 6:c52175d13e0a 335
clemente 6:c52175d13e0a 336 // Step 11: Put the device in Active Mode
clemente 6:c52175d13e0a 337 Active();
clemente 7:ba0016258d5d 338
clemente 7:ba0016258d5d 339 user1_fptr = fptr;
clemente 7:ba0016258d5d 340 MMA8451Q_Int1.fall( this, &MMA8451Q::Orientation_IRQ);
clemente 7:ba0016258d5d 341
clemente 7:ba0016258d5d 342 }
clemente 7:ba0016258d5d 343
clemente 7:ba0016258d5d 344 void MMA8451Q::Orientation_IRQ( void)
clemente 7:ba0016258d5d 345 {
clemente 7:ba0016258d5d 346 unsigned char t;
clemente 6:c52175d13e0a 347
clemente 7:ba0016258d5d 348 // Determine source of the interrupt by first reading the system interrupt
clemente 7:ba0016258d5d 349 readRegs( REG_INT_SRC, &t, 1);
clemente 7:ba0016258d5d 350 //
clemente 7:ba0016258d5d 351 if ( (t & 0x10) == 0x10) {
clemente 7:ba0016258d5d 352 // Read the PL State from the Status Register, clear the interrupt
clemente 7:ba0016258d5d 353 readRegs( REG_PL_STATUS, &t, 1);
clemente 8:7e6013f11b10 354 // Set the orientation state variable
clemente 8:7e6013f11b10 355 OrientationState = t;
clemente 8:7e6013f11b10 356 OrientationStateUpdated = 1;
clemente 7:ba0016258d5d 357 // Run the user supplied function
clemente 7:ba0016258d5d 358 user1_fptr();
clemente 7:ba0016258d5d 359 }
clemente 6:c52175d13e0a 360 }
clemente 6:c52175d13e0a 361
clemente 8:7e6013f11b10 362 unsigned char MMA8451Q::GetOrientationState( void)
clemente 8:7e6013f11b10 363 {
clemente 8:7e6013f11b10 364 if ( OrientationStateUpdated) {
clemente 8:7e6013f11b10 365 OrientationStateUpdated = 0;
clemente 8:7e6013f11b10 366 return OrientationState;
clemente 8:7e6013f11b10 367 }
clemente 8:7e6013f11b10 368 //
clemente 8:7e6013f11b10 369 return 0;
clemente 8:7e6013f11b10 370 }
clemente 8:7e6013f11b10 371
clemente 9:2aa9b1668d14 372 void MMA8451Q::DataReady( void(*fptr)(void), unsigned char ODR)
clemente 9:2aa9b1668d14 373 {
clemente 9:2aa9b1668d14 374 // Soft Reset
clemente 9:2aa9b1668d14 375 Reset();
clemente 9:2aa9b1668d14 376
clemente 9:2aa9b1668d14 377 // Step 1: Put the device into Standby Mode: Register 0x2A CTRL_REG1
clemente 9:2aa9b1668d14 378 // Set the device ODR value and Standby
clemente 9:2aa9b1668d14 379 unsigned char data[2] = {REG_CTRL_REG_1, ((ODR<<3) & 0xFE)};
clemente 9:2aa9b1668d14 380 writeRegs(data, 2);
clemente 9:2aa9b1668d14 381
clemente 9:2aa9b1668d14 382 // Step 2: Enable Data Ready Interrupt Function in the System (CTRL_REG4)
clemente 9:2aa9b1668d14 383 data[0] = REG_CTRL_REG_4;
clemente 9:2aa9b1668d14 384 data[1] = 0x01;
clemente 9:2aa9b1668d14 385 writeRegs(data, 2);
clemente 9:2aa9b1668d14 386
clemente 9:2aa9b1668d14 387 // Step 6: Route the Data Ready Interrupt Function to INT2 hardware pin (CTRL_REG5)
clemente 9:2aa9b1668d14 388 data[0] = REG_CTRL_REG_5;
clemente 9:2aa9b1668d14 389 data[1] = 0x00;
clemente 9:2aa9b1668d14 390 writeRegs(data, 2);
clemente 9:2aa9b1668d14 391
clemente 9:2aa9b1668d14 392 // Step 7: Put the device in Active Mode
clemente 9:2aa9b1668d14 393 data[0] = REG_CTRL_REG_1;
clemente 9:2aa9b1668d14 394 data[1] = ((ODR<<3) | 0x01);
clemente 9:2aa9b1668d14 395 writeRegs(data, 2);
clemente 9:2aa9b1668d14 396
clemente 9:2aa9b1668d14 397 user2_fptr = fptr;
clemente 9:2aa9b1668d14 398 MMA8451Q_Int2.fall( this, &MMA8451Q::DataReady_IRQ);
clemente 9:2aa9b1668d14 399
clemente 9:2aa9b1668d14 400 }
clemente 9:2aa9b1668d14 401
clemente 9:2aa9b1668d14 402 void MMA8451Q::DataReady_IRQ( void)
clemente 9:2aa9b1668d14 403 {
clemente 9:2aa9b1668d14 404 unsigned char t;
clemente 9:2aa9b1668d14 405
clemente 9:2aa9b1668d14 406 // Determine source of the interrupt by first reading the system interrupt
clemente 9:2aa9b1668d14 407 readRegs( REG_INT_SRC, &t, 1);
clemente 9:2aa9b1668d14 408 //
clemente 9:2aa9b1668d14 409 if ( (t & 0x01) == 0x01) {
clemente 9:2aa9b1668d14 410 // Read the DataReady_IRQ Function to clear the interrupt
clemente 9:2aa9b1668d14 411 readRegs( REG_FF_MT_SRC, &t, 1);
clemente 9:2aa9b1668d14 412 // Run the user supplied function
clemente 9:2aa9b1668d14 413 user2_fptr();
clemente 9:2aa9b1668d14 414 }
clemente 9:2aa9b1668d14 415 }
clemente 9:2aa9b1668d14 416
clemente 9:2aa9b1668d14 417
clemente 5:695063448f2a 418 void MMA8451Q::Active( void)
clemente 5:695063448f2a 419 {
clemente 5:695063448f2a 420 unsigned char t;
clemente 5:695063448f2a 421
clemente 5:695063448f2a 422 // Activate the peripheral
clemente 5:695063448f2a 423 readRegs(REG_CTRL_REG_1, &t, 1);
clemente 5:695063448f2a 424 unsigned char data[2] = {REG_CTRL_REG_1, t|0x01};
clemente 5:695063448f2a 425 writeRegs(data, 2);
clemente 5:695063448f2a 426 }
clemente 5:695063448f2a 427
clemente 5:695063448f2a 428 void MMA8451Q::Standby( void)
clemente 5:695063448f2a 429 {
clemente 5:695063448f2a 430 unsigned char t;
clemente 5:695063448f2a 431
clemente 5:695063448f2a 432 // Standby
clemente 5:695063448f2a 433 readRegs(REG_CTRL_REG_1, &t, 1);
clemente 5:695063448f2a 434 unsigned char data[2] = {REG_CTRL_REG_1, t&0xFE};
clemente 5:695063448f2a 435 writeRegs(data, 2);
clemente 5:695063448f2a 436 }
emilmont 0:6149091f755d 437
emilmont 0:6149091f755d 438 uint8_t MMA8451Q::getWhoAmI() {
emilmont 0:6149091f755d 439 uint8_t who_am_i = 0;
samux 1:d2630136d51e 440 readRegs(REG_WHO_AM_I, &who_am_i, 1);
emilmont 0:6149091f755d 441 return who_am_i;
emilmont 0:6149091f755d 442 }
emilmont 0:6149091f755d 443
chris 3:db7126dbd63f 444 float MMA8451Q::getAccX() {
chris 3:db7126dbd63f 445 return (float(getAccAxis(REG_OUT_X_MSB))/4096.0);
emilmont 0:6149091f755d 446 }
emilmont 0:6149091f755d 447
chris 3:db7126dbd63f 448 float MMA8451Q::getAccY() {
chris 3:db7126dbd63f 449 return (float(getAccAxis(REG_OUT_Y_MSB))/4096.0);
emilmont 0:6149091f755d 450 }
emilmont 0:6149091f755d 451
chris 3:db7126dbd63f 452 float MMA8451Q::getAccZ() {
chris 3:db7126dbd63f 453 return (float(getAccAxis(REG_OUT_Z_MSB))/4096.0);
emilmont 0:6149091f755d 454 }
emilmont 0:6149091f755d 455
chris 3:db7126dbd63f 456 void MMA8451Q::getAccAllAxis(float * res) {
emilmont 0:6149091f755d 457 res[0] = getAccX();
emilmont 0:6149091f755d 458 res[1] = getAccY();
emilmont 0:6149091f755d 459 res[2] = getAccZ();
emilmont 0:6149091f755d 460 }
emilmont 0:6149091f755d 461
emilmont 0:6149091f755d 462 int16_t MMA8451Q::getAccAxis(uint8_t addr) {
emilmont 0:6149091f755d 463 int16_t acc;
emilmont 0:6149091f755d 464 uint8_t res[2];
samux 1:d2630136d51e 465 readRegs(addr, res, 2);
emilmont 0:6149091f755d 466
emilmont 0:6149091f755d 467 acc = (res[0] << 6) | (res[1] >> 2);
emilmont 0:6149091f755d 468 if (acc > UINT14_MAX/2)
emilmont 0:6149091f755d 469 acc -= UINT14_MAX;
emilmont 0:6149091f755d 470
emilmont 0:6149091f755d 471 return acc;
emilmont 0:6149091f755d 472 }
emilmont 0:6149091f755d 473
samux 1:d2630136d51e 474 void MMA8451Q::readRegs(int addr, uint8_t * data, int len) {
emilmont 0:6149091f755d 475 char t[1] = {addr};
emilmont 0:6149091f755d 476 m_i2c.write(m_addr, t, 1, true);
emilmont 0:6149091f755d 477 m_i2c.read(m_addr, (char *)data, len);
emilmont 0:6149091f755d 478 }
emilmont 0:6149091f755d 479
samux 1:d2630136d51e 480 void MMA8451Q::writeRegs(uint8_t * data, int len) {
emilmont 0:6149091f755d 481 m_i2c.write(m_addr, (char *)data, len);
emilmont 0:6149091f755d 482 }