port for ece459
Fork of BurstSPI by
BurstSPI_LPC1768.cpp@7:9faa78fb128a, 2014-08-05 (annotated)
- Committer:
- mcapewel
- Date:
- Tue Aug 05 19:35:37 2014 +0000
- Revision:
- 7:9faa78fb128a
- Parent:
- 3:7d9b64d67b22
- Child:
- 8:97d75b6d5028
Add LPC1114 as target supported by LPC1768 code.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mcapewel | 7:9faa78fb128a | 1 | #if defined(TARGET_LPC1768) || defined(TARGET_LPC1114) |
Sissors | 0:600eecd89a78 | 2 | #include "BurstSPI.h" |
Sissors | 0:600eecd89a78 | 3 | |
Sissors | 0:600eecd89a78 | 4 | void BurstSPI::fastWrite(int data) { |
Sissors | 0:600eecd89a78 | 5 | //Wait until FIFO has space |
Sissors | 0:600eecd89a78 | 6 | while(((_spi.spi->SR) & 0x02) == 0); |
Sissors | 0:600eecd89a78 | 7 | |
Sissors | 0:600eecd89a78 | 8 | //transmit data |
Sissors | 0:600eecd89a78 | 9 | _spi.spi->DR = data; |
Sissors | 0:600eecd89a78 | 10 | } |
Sissors | 0:600eecd89a78 | 11 | |
Sissors | 0:600eecd89a78 | 12 | void BurstSPI::clearRX( void ) { |
Sissors | 0:600eecd89a78 | 13 | //Do it while either data in RX buffer, or while it is busy |
Sissors | 0:600eecd89a78 | 14 | while(((_spi.spi->SR) & ((1<<4) + (1<<2))) != 0) { |
Sissors | 0:600eecd89a78 | 15 | //Wait until data in RX buffer |
Sissors | 0:600eecd89a78 | 16 | while(((_spi.spi->SR) & (1<<2)) == 0); |
Sissors | 0:600eecd89a78 | 17 | int dummy = _spi.spi->DR; |
Sissors | 0:600eecd89a78 | 18 | } |
Sissors | 3:7d9b64d67b22 | 19 | } |
Sissors | 3:7d9b64d67b22 | 20 | #endif |