Abdessamad El Abbassi / mbed-src-temp

mbed library sources

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/system_stm32f4xx.c@87:085cde657901, 2014-02-08 (annotated)

Committer:
mbed_official
Date:
Sat Feb 08 19:45:06 2014 +0000
Revision:
87:085cde657901
Child:
106:ced8cbb51063
Synchronized with git revision 9272cdeb45ec7e6077641536509413da8fd2ebc2



Full URL: https://github.com/mbedmicro/mbed/commit/9272cdeb45ec7e6077641536509413da8fd2ebc2/



Add NUCLEO_F401RE, improvements

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file system_stm32f4xx.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 87:085cde657901 5 * @version V0.8.0
mbed_official 87:085cde657901 6 * @date 03-January-2014
mbed_official 87:085cde657901 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 87:085cde657901 8 *
mbed_official 87:085cde657901 9 * This file provides two functions and one global variable to be called from
mbed_official 87:085cde657901 10 * user application:
mbed_official 87:085cde657901 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 87:085cde657901 12 * before branch to main program. This call is made inside
mbed_official 87:085cde657901 13 * the "startup_stm32f4xx.s" file.
mbed_official 87:085cde657901 14 *
mbed_official 87:085cde657901 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 87:085cde657901 16 * by the user application to setup the SysTick
mbed_official 87:085cde657901 17 * timer or configure other parameters.
mbed_official 87:085cde657901 18 *
mbed_official 87:085cde657901 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 87:085cde657901 20 * be called whenever the core clock is changed
mbed_official 87:085cde657901 21 * during program execution.
mbed_official 87:085cde657901 22 *
mbed_official 87:085cde657901 23 *
mbed_official 87:085cde657901 24 ******************************************************************************
mbed_official 87:085cde657901 25 * @attention
mbed_official 87:085cde657901 26 *
mbed_official 87:085cde657901 27 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 28 *
mbed_official 87:085cde657901 29 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
mbed_official 87:085cde657901 30 * You may not use this file except in compliance with the License.
mbed_official 87:085cde657901 31 * You may obtain a copy of the License at:
mbed_official 87:085cde657901 32 *
mbed_official 87:085cde657901 33 * http://www.st.com/software_license_agreement_liberty_v2
mbed_official 87:085cde657901 34 *
mbed_official 87:085cde657901 35 * Unless required by applicable law or agreed to in writing, software
mbed_official 87:085cde657901 36 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 87:085cde657901 37 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 87:085cde657901 38 * See the License for the specific language governing permissions and
mbed_official 87:085cde657901 39 * limitations under the License.
mbed_official 87:085cde657901 40 *
mbed_official 87:085cde657901 41 ******************************************************************************
mbed_official 87:085cde657901 42 */
mbed_official 87:085cde657901 43
mbed_official 87:085cde657901 44 /** @addtogroup CMSIS
mbed_official 87:085cde657901 45 * @{
mbed_official 87:085cde657901 46 */
mbed_official 87:085cde657901 47
mbed_official 87:085cde657901 48 /** @addtogroup stm32f4xx_system
mbed_official 87:085cde657901 49 * @{
mbed_official 87:085cde657901 50 */
mbed_official 87:085cde657901 51
mbed_official 87:085cde657901 52 /** @addtogroup STM32F4xx_System_Private_Includes
mbed_official 87:085cde657901 53 * @{
mbed_official 87:085cde657901 54 */
mbed_official 87:085cde657901 55
mbed_official 87:085cde657901 56 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 57
mbed_official 87:085cde657901 58 /**
mbed_official 87:085cde657901 59 * @}
mbed_official 87:085cde657901 60 */
mbed_official 87:085cde657901 61
mbed_official 87:085cde657901 62 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
mbed_official 87:085cde657901 63 * @{
mbed_official 87:085cde657901 64 */
mbed_official 87:085cde657901 65
mbed_official 87:085cde657901 66 /**
mbed_official 87:085cde657901 67 * @}
mbed_official 87:085cde657901 68 */
mbed_official 87:085cde657901 69
mbed_official 87:085cde657901 70 /** @addtogroup STM32F4xx_System_Private_Defines
mbed_official 87:085cde657901 71 * @{
mbed_official 87:085cde657901 72 */
mbed_official 87:085cde657901 73
mbed_official 87:085cde657901 74 /************************* Miscellaneous Configuration ************************/
mbed_official 87:085cde657901 75 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
mbed_official 87:085cde657901 76 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
mbed_official 87:085cde657901 77 /* #define DATA_IN_ExtSRAM */
mbed_official 87:085cde657901 78 /* #define DATA_IN_ExtSDRAM */
mbed_official 87:085cde657901 79 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
mbed_official 87:085cde657901 80 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
mbed_official 87:085cde657901 81 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
mbed_official 87:085cde657901 82
mbed_official 87:085cde657901 83 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 87:085cde657901 84 Internal SRAM. */
mbed_official 87:085cde657901 85 /* #define VECT_TAB_SRAM */
mbed_official 87:085cde657901 86 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 87:085cde657901 87 This value must be a multiple of 0x200. */
mbed_official 87:085cde657901 88 /******************************************************************************/
mbed_official 87:085cde657901 89
mbed_official 87:085cde657901 90 /**
mbed_official 87:085cde657901 91 * @}
mbed_official 87:085cde657901 92 */
mbed_official 87:085cde657901 93
mbed_official 87:085cde657901 94 /** @addtogroup STM32F4xx_System_Private_Macros
mbed_official 87:085cde657901 95 * @{
mbed_official 87:085cde657901 96 */
mbed_official 87:085cde657901 97
mbed_official 87:085cde657901 98 /**
mbed_official 87:085cde657901 99 * @}
mbed_official 87:085cde657901 100 */
mbed_official 87:085cde657901 101
mbed_official 87:085cde657901 102 /** @addtogroup STM32F4xx_System_Private_Variables
mbed_official 87:085cde657901 103 * @{
mbed_official 87:085cde657901 104 */
mbed_official 87:085cde657901 105 /* This variable is updated in three ways:
mbed_official 87:085cde657901 106 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 87:085cde657901 107 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 87:085cde657901 108 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 87:085cde657901 109 Note: If you use this function to configure the system clock; then there
mbed_official 87:085cde657901 110 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 87:085cde657901 111 variable is updated automatically.
mbed_official 87:085cde657901 112 */
mbed_official 87:085cde657901 113 uint32_t SystemCoreClock = 16000000;
mbed_official 87:085cde657901 114 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 87:085cde657901 115
mbed_official 87:085cde657901 116 /**
mbed_official 87:085cde657901 117 * @}
mbed_official 87:085cde657901 118 */
mbed_official 87:085cde657901 119
mbed_official 87:085cde657901 120 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
mbed_official 87:085cde657901 121 * @{
mbed_official 87:085cde657901 122 */
mbed_official 87:085cde657901 123
mbed_official 87:085cde657901 124 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 87:085cde657901 125 static void SystemInit_ExtMemCtl(void);
mbed_official 87:085cde657901 126 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 87:085cde657901 127
mbed_official 87:085cde657901 128 /**
mbed_official 87:085cde657901 129 * @}
mbed_official 87:085cde657901 130 */
mbed_official 87:085cde657901 131
mbed_official 87:085cde657901 132 /** @addtogroup STM32F4xx_System_Private_Functions
mbed_official 87:085cde657901 133 * @{
mbed_official 87:085cde657901 134 */
mbed_official 87:085cde657901 135
mbed_official 87:085cde657901 136 /**
mbed_official 87:085cde657901 137 * @brief Setup the microcontroller system
mbed_official 87:085cde657901 138 * Initialize the FPU setting, vector table location and External memory
mbed_official 87:085cde657901 139 * configuration.
mbed_official 87:085cde657901 140 * @param None
mbed_official 87:085cde657901 141 * @retval None
mbed_official 87:085cde657901 142 */
mbed_official 87:085cde657901 143 void SystemInit(void)
mbed_official 87:085cde657901 144 {
mbed_official 87:085cde657901 145 /* FPU settings ------------------------------------------------------------*/
mbed_official 87:085cde657901 146 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 87:085cde657901 147 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 87:085cde657901 148 #endif
mbed_official 87:085cde657901 149 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 87:085cde657901 150 /* Set HSION bit */
mbed_official 87:085cde657901 151 RCC->CR |= (uint32_t)0x00000001;
mbed_official 87:085cde657901 152
mbed_official 87:085cde657901 153 /* Reset CFGR register */
mbed_official 87:085cde657901 154 RCC->CFGR = 0x00000000;
mbed_official 87:085cde657901 155
mbed_official 87:085cde657901 156 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 87:085cde657901 157 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 87:085cde657901 158
mbed_official 87:085cde657901 159 /* Reset PLLCFGR register */
mbed_official 87:085cde657901 160 RCC->PLLCFGR = 0x24003010;
mbed_official 87:085cde657901 161
mbed_official 87:085cde657901 162 /* Reset HSEBYP bit */
mbed_official 87:085cde657901 163 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 87:085cde657901 164
mbed_official 87:085cde657901 165 /* Disable all interrupts */
mbed_official 87:085cde657901 166 RCC->CIR = 0x00000000;
mbed_official 87:085cde657901 167
mbed_official 87:085cde657901 168 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 87:085cde657901 169 SystemInit_ExtMemCtl();
mbed_official 87:085cde657901 170 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 87:085cde657901 171
mbed_official 87:085cde657901 172 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 87:085cde657901 173 #ifdef VECT_TAB_SRAM
mbed_official 87:085cde657901 174 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 87:085cde657901 175 #else
mbed_official 87:085cde657901 176 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 87:085cde657901 177 #endif
mbed_official 87:085cde657901 178
mbed_official 87:085cde657901 179 // [ADDED FOR MBED]
mbed_official 87:085cde657901 180 HAL_Init();
mbed_official 87:085cde657901 181 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 87:085cde657901 182 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 87:085cde657901 183 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
mbed_official 87:085cde657901 184 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 16 MHz
mbed_official 87:085cde657901 185 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 16 MHz
mbed_official 87:085cde657901 186 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 8 MHz for the SPI
mbed_official 87:085cde657901 187 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
mbed_official 87:085cde657901 188 }
mbed_official 87:085cde657901 189
mbed_official 87:085cde657901 190 // [ADDED FOR MBED]
mbed_official 87:085cde657901 191 void SysTick_Handler(void)
mbed_official 87:085cde657901 192 {
mbed_official 87:085cde657901 193 HAL_IncTick();
mbed_official 87:085cde657901 194 }
mbed_official 87:085cde657901 195
mbed_official 87:085cde657901 196 /**
mbed_official 87:085cde657901 197 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 87:085cde657901 198 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 87:085cde657901 199 * be used by the user application to setup the SysTick timer or configure
mbed_official 87:085cde657901 200 * other parameters.
mbed_official 87:085cde657901 201 *
mbed_official 87:085cde657901 202 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 87:085cde657901 203 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 87:085cde657901 204 * based on this variable will be incorrect.
mbed_official 87:085cde657901 205 *
mbed_official 87:085cde657901 206 * @note - The system frequency computed by this function is not the real
mbed_official 87:085cde657901 207 * frequency in the chip. It is calculated based on the predefined
mbed_official 87:085cde657901 208 * constant and the selected clock source:
mbed_official 87:085cde657901 209 *
mbed_official 87:085cde657901 210 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 87:085cde657901 211 *
mbed_official 87:085cde657901 212 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 87:085cde657901 213 *
mbed_official 87:085cde657901 214 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 87:085cde657901 215 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 87:085cde657901 216 *
mbed_official 87:085cde657901 217 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal.h file (default value
mbed_official 87:085cde657901 218 * 16 MHz) but the real value may vary depending on the variations
mbed_official 87:085cde657901 219 * in voltage and temperature.
mbed_official 87:085cde657901 220 *
mbed_official 87:085cde657901 221 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal.h file (default value
mbed_official 87:085cde657901 222 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 87:085cde657901 223 * frequency of the crystal used. Otherwise, this function may
mbed_official 87:085cde657901 224 * have wrong result.
mbed_official 87:085cde657901 225 *
mbed_official 87:085cde657901 226 * - The result of this function could be not correct when using fractional
mbed_official 87:085cde657901 227 * value for HSE crystal.
mbed_official 87:085cde657901 228 *
mbed_official 87:085cde657901 229 * @param None
mbed_official 87:085cde657901 230 * @retval None
mbed_official 87:085cde657901 231 */
mbed_official 87:085cde657901 232 void SystemCoreClockUpdate(void)
mbed_official 87:085cde657901 233 {
mbed_official 87:085cde657901 234 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official 87:085cde657901 235
mbed_official 87:085cde657901 236 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 87:085cde657901 237 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 87:085cde657901 238
mbed_official 87:085cde657901 239 switch (tmp)
mbed_official 87:085cde657901 240 {
mbed_official 87:085cde657901 241 case 0x00: /* HSI used as system clock source */
mbed_official 87:085cde657901 242 SystemCoreClock = HSI_VALUE;
mbed_official 87:085cde657901 243 break;
mbed_official 87:085cde657901 244 case 0x04: /* HSE used as system clock source */
mbed_official 87:085cde657901 245 SystemCoreClock = HSE_VALUE;
mbed_official 87:085cde657901 246 break;
mbed_official 87:085cde657901 247 case 0x08: /* PLL used as system clock source */
mbed_official 87:085cde657901 248
mbed_official 87:085cde657901 249 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official 87:085cde657901 250 SYSCLK = PLL_VCO / PLL_P
mbed_official 87:085cde657901 251 */
mbed_official 87:085cde657901 252 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official 87:085cde657901 253 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 87:085cde657901 254
mbed_official 87:085cde657901 255 if (pllsource != 0)
mbed_official 87:085cde657901 256 {
mbed_official 87:085cde657901 257 /* HSE used as PLL clock source */
mbed_official 87:085cde657901 258 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 87:085cde657901 259 }
mbed_official 87:085cde657901 260 else
mbed_official 87:085cde657901 261 {
mbed_official 87:085cde657901 262 /* HSI used as PLL clock source */
mbed_official 87:085cde657901 263 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 87:085cde657901 264 }
mbed_official 87:085cde657901 265
mbed_official 87:085cde657901 266 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official 87:085cde657901 267 SystemCoreClock = pllvco/pllp;
mbed_official 87:085cde657901 268 break;
mbed_official 87:085cde657901 269 default:
mbed_official 87:085cde657901 270 SystemCoreClock = HSI_VALUE;
mbed_official 87:085cde657901 271 break;
mbed_official 87:085cde657901 272 }
mbed_official 87:085cde657901 273 /* Compute HCLK frequency --------------------------------------------------*/
mbed_official 87:085cde657901 274 /* Get HCLK prescaler */
mbed_official 87:085cde657901 275 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 87:085cde657901 276 /* HCLK frequency */
mbed_official 87:085cde657901 277 SystemCoreClock >>= tmp;
mbed_official 87:085cde657901 278 }
mbed_official 87:085cde657901 279
mbed_official 87:085cde657901 280 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 87:085cde657901 281 /**
mbed_official 87:085cde657901 282 * @brief Setup the external memory controller.
mbed_official 87:085cde657901 283 * Called in startup_stm32f4xx.s before jump to main.
mbed_official 87:085cde657901 284 * This function configures the external memories (SRAM/SDRAM)
mbed_official 87:085cde657901 285 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official 87:085cde657901 286 * @param None
mbed_official 87:085cde657901 287 * @retval None
mbed_official 87:085cde657901 288 */
mbed_official 87:085cde657901 289 void SystemInit_ExtMemCtl(void)
mbed_official 87:085cde657901 290 {
mbed_official 87:085cde657901 291 #if defined (DATA_IN_ExtSDRAM)
mbed_official 87:085cde657901 292 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 87:085cde657901 293 register uint32_t index;
mbed_official 87:085cde657901 294
mbed_official 87:085cde657901 295 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 87:085cde657901 296 clock */
mbed_official 87:085cde657901 297 RCC->AHB1ENR |= 0x000001FC;
mbed_official 87:085cde657901 298
mbed_official 87:085cde657901 299 /* Connect PCx pins to FMC Alternate function */
mbed_official 87:085cde657901 300 GPIOC->AFR[0] = 0x0000000c;
mbed_official 87:085cde657901 301 GPIOC->AFR[1] = 0x00007700;
mbed_official 87:085cde657901 302 /* Configure PCx pins in Alternate function mode */
mbed_official 87:085cde657901 303 GPIOC->MODER = 0x00a00002;
mbed_official 87:085cde657901 304 /* Configure PCx pins speed to 50 MHz */
mbed_official 87:085cde657901 305 GPIOC->OSPEEDR = 0x00a00002;
mbed_official 87:085cde657901 306 /* Configure PCx pins Output type to push-pull */
mbed_official 87:085cde657901 307 GPIOC->OTYPER = 0x00000000;
mbed_official 87:085cde657901 308 /* No pull-up, pull-down for PCx pins */
mbed_official 87:085cde657901 309 GPIOC->PUPDR = 0x00500000;
mbed_official 87:085cde657901 310
mbed_official 87:085cde657901 311 /* Connect PDx pins to FMC Alternate function */
mbed_official 87:085cde657901 312 GPIOD->AFR[0] = 0x000000CC;
mbed_official 87:085cde657901 313 GPIOD->AFR[1] = 0xCC000CCC;
mbed_official 87:085cde657901 314 /* Configure PDx pins in Alternate function mode */
mbed_official 87:085cde657901 315 GPIOD->MODER = 0xA02A000A;
mbed_official 87:085cde657901 316 /* Configure PDx pins speed to 50 MHz */
mbed_official 87:085cde657901 317 GPIOD->OSPEEDR = 0xA02A000A;
mbed_official 87:085cde657901 318 /* Configure PDx pins Output type to push-pull */
mbed_official 87:085cde657901 319 GPIOD->OTYPER = 0x00000000;
mbed_official 87:085cde657901 320 /* No pull-up, pull-down for PDx pins */
mbed_official 87:085cde657901 321 GPIOD->PUPDR = 0x00000000;
mbed_official 87:085cde657901 322
mbed_official 87:085cde657901 323 /* Connect PEx pins to FMC Alternate function */
mbed_official 87:085cde657901 324 GPIOE->AFR[0] = 0xC00000CC;
mbed_official 87:085cde657901 325 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 87:085cde657901 326 /* Configure PEx pins in Alternate function mode */
mbed_official 87:085cde657901 327 GPIOE->MODER = 0xAAAA800A;
mbed_official 87:085cde657901 328 /* Configure PEx pins speed to 50 MHz */
mbed_official 87:085cde657901 329 GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official 87:085cde657901 330 /* Configure PEx pins Output type to push-pull */
mbed_official 87:085cde657901 331 GPIOE->OTYPER = 0x00000000;
mbed_official 87:085cde657901 332 /* No pull-up, pull-down for PEx pins */
mbed_official 87:085cde657901 333 GPIOE->PUPDR = 0x00000000;
mbed_official 87:085cde657901 334
mbed_official 87:085cde657901 335 /* Connect PFx pins to FMC Alternate function */
mbed_official 87:085cde657901 336 GPIOF->AFR[0] = 0xcccccccc;
mbed_official 87:085cde657901 337 GPIOF->AFR[1] = 0xcccccccc;
mbed_official 87:085cde657901 338 /* Configure PFx pins in Alternate function mode */
mbed_official 87:085cde657901 339 GPIOF->MODER = 0xAA800AAA;
mbed_official 87:085cde657901 340 /* Configure PFx pins speed to 50 MHz */
mbed_official 87:085cde657901 341 GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official 87:085cde657901 342 /* Configure PFx pins Output type to push-pull */
mbed_official 87:085cde657901 343 GPIOF->OTYPER = 0x00000000;
mbed_official 87:085cde657901 344 /* No pull-up, pull-down for PFx pins */
mbed_official 87:085cde657901 345 GPIOF->PUPDR = 0x00000000;
mbed_official 87:085cde657901 346
mbed_official 87:085cde657901 347 /* Connect PGx pins to FMC Alternate function */
mbed_official 87:085cde657901 348 GPIOG->AFR[0] = 0xcccccccc;
mbed_official 87:085cde657901 349 GPIOG->AFR[1] = 0xcccccccc;
mbed_official 87:085cde657901 350 /* Configure PGx pins in Alternate function mode */
mbed_official 87:085cde657901 351 GPIOG->MODER = 0xaaaaaaaa;
mbed_official 87:085cde657901 352 /* Configure PGx pins speed to 50 MHz */
mbed_official 87:085cde657901 353 GPIOG->OSPEEDR = 0xaaaaaaaa;
mbed_official 87:085cde657901 354 /* Configure PGx pins Output type to push-pull */
mbed_official 87:085cde657901 355 GPIOG->OTYPER = 0x00000000;
mbed_official 87:085cde657901 356 /* No pull-up, pull-down for PGx pins */
mbed_official 87:085cde657901 357 GPIOG->PUPDR = 0x00000000;
mbed_official 87:085cde657901 358
mbed_official 87:085cde657901 359 /* Connect PHx pins to FMC Alternate function */
mbed_official 87:085cde657901 360 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 87:085cde657901 361 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 87:085cde657901 362 /* Configure PHx pins in Alternate function mode */
mbed_official 87:085cde657901 363 GPIOH->MODER = 0xAAAA08A0;
mbed_official 87:085cde657901 364 /* Configure PHx pins speed to 50 MHz */
mbed_official 87:085cde657901 365 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 87:085cde657901 366 /* Configure PHx pins Output type to push-pull */
mbed_official 87:085cde657901 367 GPIOH->OTYPER = 0x00000000;
mbed_official 87:085cde657901 368 /* No pull-up, pull-down for PHx pins */
mbed_official 87:085cde657901 369 GPIOH->PUPDR = 0x00000000;
mbed_official 87:085cde657901 370
mbed_official 87:085cde657901 371 /* Connect PIx pins to FMC Alternate function */
mbed_official 87:085cde657901 372 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 87:085cde657901 373 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 87:085cde657901 374 /* Configure PIx pins in Alternate function mode */
mbed_official 87:085cde657901 375 GPIOI->MODER = 0x0028AAAA;
mbed_official 87:085cde657901 376 /* Configure PIx pins speed to 50 MHz */
mbed_official 87:085cde657901 377 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 87:085cde657901 378 /* Configure PIx pins Output type to push-pull */
mbed_official 87:085cde657901 379 GPIOI->OTYPER = 0x00000000;
mbed_official 87:085cde657901 380 /* No pull-up, pull-down for PIx pins */
mbed_official 87:085cde657901 381 GPIOI->PUPDR = 0x00000000;
mbed_official 87:085cde657901 382
mbed_official 87:085cde657901 383 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 87:085cde657901 384 /* Enable the FMC interface clock */
mbed_official 87:085cde657901 385 RCC->AHB3ENR |= 0x00000001;
mbed_official 87:085cde657901 386
mbed_official 87:085cde657901 387 /* Configure and enable SDRAM bank1 */
mbed_official 87:085cde657901 388 FMC_Bank5_6->SDCR[0] = 0x000029D0;
mbed_official 87:085cde657901 389 FMC_Bank5_6->SDTR[0] = 0x01115351;
mbed_official 87:085cde657901 390
mbed_official 87:085cde657901 391 /* SDRAM initialization sequence */
mbed_official 87:085cde657901 392 /* Clock enable command */
mbed_official 87:085cde657901 393 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 87:085cde657901 394 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 87:085cde657901 395 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 87:085cde657901 396 {
mbed_official 87:085cde657901 397 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 87:085cde657901 398 }
mbed_official 87:085cde657901 399
mbed_official 87:085cde657901 400 /* Delay */
mbed_official 87:085cde657901 401 for (index = 0; index<1000; index++);
mbed_official 87:085cde657901 402
mbed_official 87:085cde657901 403 /* PALL command */
mbed_official 87:085cde657901 404 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 87:085cde657901 405 timeout = 0xFFFF;
mbed_official 87:085cde657901 406 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 87:085cde657901 407 {
mbed_official 87:085cde657901 408 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 87:085cde657901 409 }
mbed_official 87:085cde657901 410
mbed_official 87:085cde657901 411 /* Auto refresh command */
mbed_official 87:085cde657901 412 FMC_Bank5_6->SDCMR = 0x00000073;
mbed_official 87:085cde657901 413 timeout = 0xFFFF;
mbed_official 87:085cde657901 414 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 87:085cde657901 415 {
mbed_official 87:085cde657901 416 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 87:085cde657901 417 }
mbed_official 87:085cde657901 418
mbed_official 87:085cde657901 419 /* MRD register program */
mbed_official 87:085cde657901 420 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 87:085cde657901 421 timeout = 0xFFFF;
mbed_official 87:085cde657901 422 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 87:085cde657901 423 {
mbed_official 87:085cde657901 424 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 87:085cde657901 425 }
mbed_official 87:085cde657901 426
mbed_official 87:085cde657901 427 /* Set refresh count */
mbed_official 87:085cde657901 428 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 87:085cde657901 429 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
mbed_official 87:085cde657901 430
mbed_official 87:085cde657901 431 /* Disable write protection */
mbed_official 87:085cde657901 432 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 87:085cde657901 433 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 87:085cde657901 434 #endif /* DATA_IN_ExtSDRAM */
mbed_official 87:085cde657901 435
mbed_official 87:085cde657901 436 #if defined(DATA_IN_ExtSRAM)
mbed_official 87:085cde657901 437 /*-- GPIOs Configuration -----------------------------------------------------*/
mbed_official 87:085cde657901 438 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official 87:085cde657901 439 RCC->AHB1ENR |= 0x00000078;
mbed_official 87:085cde657901 440
mbed_official 87:085cde657901 441 /* Connect PDx pins to FMC Alternate function */
mbed_official 87:085cde657901 442 GPIOD->AFR[0] = 0x00ccc0cc;
mbed_official 87:085cde657901 443 GPIOD->AFR[1] = 0xcccccccc;
mbed_official 87:085cde657901 444 /* Configure PDx pins in Alternate function mode */
mbed_official 87:085cde657901 445 GPIOD->MODER = 0xaaaa0a8a;
mbed_official 87:085cde657901 446 /* Configure PDx pins speed to 100 MHz */
mbed_official 87:085cde657901 447 GPIOD->OSPEEDR = 0xffff0fcf;
mbed_official 87:085cde657901 448 /* Configure PDx pins Output type to push-pull */
mbed_official 87:085cde657901 449 GPIOD->OTYPER = 0x00000000;
mbed_official 87:085cde657901 450 /* No pull-up, pull-down for PDx pins */
mbed_official 87:085cde657901 451 GPIOD->PUPDR = 0x00000000;
mbed_official 87:085cde657901 452
mbed_official 87:085cde657901 453 /* Connect PEx pins to FMC Alternate function */
mbed_official 87:085cde657901 454 GPIOE->AFR[0] = 0xc00cc0cc;
mbed_official 87:085cde657901 455 GPIOE->AFR[1] = 0xcccccccc;
mbed_official 87:085cde657901 456 /* Configure PEx pins in Alternate function mode */
mbed_official 87:085cde657901 457 GPIOE->MODER = 0xaaaa828a;
mbed_official 87:085cde657901 458 /* Configure PEx pins speed to 100 MHz */
mbed_official 87:085cde657901 459 GPIOE->OSPEEDR = 0xffffc3cf;
mbed_official 87:085cde657901 460 /* Configure PEx pins Output type to push-pull */
mbed_official 87:085cde657901 461 GPIOE->OTYPER = 0x00000000;
mbed_official 87:085cde657901 462 /* No pull-up, pull-down for PEx pins */
mbed_official 87:085cde657901 463 GPIOE->PUPDR = 0x00000000;
mbed_official 87:085cde657901 464
mbed_official 87:085cde657901 465 /* Connect PFx pins to FMC Alternate function */
mbed_official 87:085cde657901 466 GPIOF->AFR[0] = 0x00cccccc;
mbed_official 87:085cde657901 467 GPIOF->AFR[1] = 0xcccc0000;
mbed_official 87:085cde657901 468 /* Configure PFx pins in Alternate function mode */
mbed_official 87:085cde657901 469 GPIOF->MODER = 0xaa000aaa;
mbed_official 87:085cde657901 470 /* Configure PFx pins speed to 100 MHz */
mbed_official 87:085cde657901 471 GPIOF->OSPEEDR = 0xff000fff;
mbed_official 87:085cde657901 472 /* Configure PFx pins Output type to push-pull */
mbed_official 87:085cde657901 473 GPIOF->OTYPER = 0x00000000;
mbed_official 87:085cde657901 474 /* No pull-up, pull-down for PFx pins */
mbed_official 87:085cde657901 475 GPIOF->PUPDR = 0x00000000;
mbed_official 87:085cde657901 476
mbed_official 87:085cde657901 477 /* Connect PGx pins to FMC Alternate function */
mbed_official 87:085cde657901 478 GPIOG->AFR[0] = 0x00cccccc;
mbed_official 87:085cde657901 479 GPIOG->AFR[1] = 0x000000c0;
mbed_official 87:085cde657901 480 /* Configure PGx pins in Alternate function mode */
mbed_official 87:085cde657901 481 GPIOG->MODER = 0x00085aaa;
mbed_official 87:085cde657901 482 /* Configure PGx pins speed to 100 MHz */
mbed_official 87:085cde657901 483 GPIOG->OSPEEDR = 0x000cafff;
mbed_official 87:085cde657901 484 /* Configure PGx pins Output type to push-pull */
mbed_official 87:085cde657901 485 GPIOG->OTYPER = 0x00000000;
mbed_official 87:085cde657901 486 /* No pull-up, pull-down for PGx pins */
mbed_official 87:085cde657901 487 GPIOG->PUPDR = 0x00000000;
mbed_official 87:085cde657901 488
mbed_official 87:085cde657901 489 /*-- FMC/FSMC Configuration --------------------------------------------------*/
mbed_official 87:085cde657901 490 /* Enable the FMC/FSMC interface clock */
mbed_official 87:085cde657901 491 RCC->AHB3ENR |= 0x00000001;
mbed_official 87:085cde657901 492
mbed_official 87:085cde657901 493 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 494 /* Configure and enable Bank1_SRAM2 */
mbed_official 87:085cde657901 495 FMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 87:085cde657901 496 FMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 87:085cde657901 497 FMC_Bank1E->BWTR[2] = 0x0fffffff;
mbed_official 87:085cde657901 498 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 499
mbed_official 87:085cde657901 500 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 87:085cde657901 501 /* Configure and enable Bank1_SRAM2 */
mbed_official 87:085cde657901 502 FSMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 87:085cde657901 503 FSMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 87:085cde657901 504 FSMC_Bank1E->BWTR[2] = 0x0fffffff;
mbed_official 87:085cde657901 505 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 87:085cde657901 506
mbed_official 87:085cde657901 507 #endif /* DATA_IN_ExtSRAM */
mbed_official 87:085cde657901 508
mbed_official 87:085cde657901 509 }
mbed_official 87:085cde657901 510 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 87:085cde657901 511 /**
mbed_official 87:085cde657901 512 * @}
mbed_official 87:085cde657901 513 */
mbed_official 87:085cde657901 514
mbed_official 87:085cde657901 515 /**
mbed_official 87:085cde657901 516 * @}
mbed_official 87:085cde657901 517 */
mbed_official 87:085cde657901 518
mbed_official 87:085cde657901 519 /**
mbed_official 87:085cde657901 520 * @}
mbed_official 87:085cde657901 521 */
mbed_official 87:085cde657901 522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/