Gonzalo Brusco
Real Time FIR Filter - Distinctive Excellence award winner :)
timer.c@0:b3e50e98acac, 2011-08-13 (annotated)
- Committer:
- Gonzakpo
- Date:
- Sat Aug 13 17:35:52 2011 +0000
- Revision:
- 0:b3e50e98acac
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Gonzakpo | 0:b3e50e98acac | 1 | |
| Gonzakpo | 0:b3e50e98acac | 2 | #include "timer.h" |
| Gonzakpo | 0:b3e50e98acac | 3 | #include "leds_mbed.h" |
| Gonzakpo | 0:b3e50e98acac | 4 | |
| Gonzakpo | 0:b3e50e98acac | 5 | void init_timer(void) |
| Gonzakpo | 0:b3e50e98acac | 6 | { |
| Gonzakpo | 0:b3e50e98acac | 7 | /* Configuro el MAT0.0 para que genere el clock de muestreo de |
| Gonzakpo | 0:b3e50e98acac | 8 | * tanto el DAC como el ADC (mediante el manejo de los DMA requests) */ |
| Gonzakpo | 0:b3e50e98acac | 9 | |
| Gonzakpo | 0:b3e50e98acac | 10 | LPC_SC->PCONP |= 1 << 1; /* Enciendo modulo Timer 0 */ |
| Gonzakpo | 0:b3e50e98acac | 11 | |
| Gonzakpo | 0:b3e50e98acac | 12 | LPC_SC->PCLKSEL0 &= ~(0x03 << 2); /* Clock del Timer 0: */ |
| Gonzakpo | 0:b3e50e98acac | 13 | /* 00 = CLCK/4 */ |
| Gonzakpo | 0:b3e50e98acac | 14 | /* 01 = CLCK */ |
| Gonzakpo | 0:b3e50e98acac | 15 | /* 10 = CLCK/2 */ |
| Gonzakpo | 0:b3e50e98acac | 16 | /* 11 = CLCK/8 */ |
| Gonzakpo | 0:b3e50e98acac | 17 | /* Actualmente configurado en CLCK/4 */ |
| Gonzakpo | 0:b3e50e98acac | 18 | |
| Gonzakpo | 0:b3e50e98acac | 19 | /* Interrupt register */ |
| Gonzakpo | 0:b3e50e98acac | 20 | LPC_TIM0->IR = 0x0; /* Limpio cualquier interrupcion previa */ |
| Gonzakpo | 0:b3e50e98acac | 21 | |
| Gonzakpo | 0:b3e50e98acac | 22 | /* Timer Control Register */ |
| Gonzakpo | 0:b3e50e98acac | 23 | LPC_TIM0->TCR = 0x2; /* Reseteo contadores y deshabilito el timer */ |
| Gonzakpo | 0:b3e50e98acac | 24 | |
| Gonzakpo | 0:b3e50e98acac | 25 | /* Count Control Register */ |
| Gonzakpo | 0:b3e50e98acac | 26 | LPC_TIM0->CTCR = 0x0; /* Modo timer (NO contador!) */ |
| Gonzakpo | 0:b3e50e98acac | 27 | |
| Gonzakpo | 0:b3e50e98acac | 28 | /* Preescale Register */ |
| Gonzakpo | 0:b3e50e98acac | 29 | LPC_TIM0->PR = 0x1; /* Es la cantidad de clocks que deben pasar para incrementar el Timer 0 */ |
| Gonzakpo | 0:b3e50e98acac | 30 | /* Si PR=0, el timer incrementa en cada CLK. Si PR=1, el timer incrementa cada dos CLK, etc. */ |
| Gonzakpo | 0:b3e50e98acac | 31 | |
| Gonzakpo | 0:b3e50e98acac | 32 | /* Match Register 0 */ |
| Gonzakpo | 0:b3e50e98acac | 33 | LPC_TIM0->MR0 = SAMPLING_DIV; /* El valor del Match Register se comparará continuamente con el valor del Timer. |
| Gonzakpo | 0:b3e50e98acac | 34 | * Cuando sean iguales se producira un DMA request desde el ADC y hacia el DAC. |
| Gonzakpo | 0:b3e50e98acac | 35 | * Es por eso que este valor determina la frecuencia de muestreo de ambos. |
| Gonzakpo | 0:b3e50e98acac | 36 | * Para calcular el valor hay que hacer lo siguiente: Suponiendo una frecuencia |
| Gonzakpo | 0:b3e50e98acac | 37 | * de muestreo deseada de Fx, y un clock (preescaler igual a cero) de CLK/8 |
| Gonzakpo | 0:b3e50e98acac | 38 | * el valor de MR0 necesario será = (CLK/8)/Fx */ |
| Gonzakpo | 0:b3e50e98acac | 39 | /* Con 283 tenemos una frecuencia de muestreo de ~44.1KHz */ |
| Gonzakpo | 0:b3e50e98acac | 40 | /* Con 125 tenemos una frecuencia de muestreo de 100KHz */ |
| Gonzakpo | 0:b3e50e98acac | 41 | |
| Gonzakpo | 0:b3e50e98acac | 42 | /* Match Control Register. */ |
| Gonzakpo | 0:b3e50e98acac | 43 | LPC_TIM0->MCR = (0 << 0) | /* Interrupcion por Match 0 deshabilitada */ |
| Gonzakpo | 0:b3e50e98acac | 44 | (1 << 1) | /* Resetear el timer cuando haya un match 0 */ |
| Gonzakpo | 0:b3e50e98acac | 45 | (0 << 2); /* No parar el timer cuando hay un match 0 */ |
| Gonzakpo | 0:b3e50e98acac | 46 | |
| Gonzakpo | 0:b3e50e98acac | 47 | /* Inicio el Timer 0 */ |
| Gonzakpo | 0:b3e50e98acac | 48 | LPC_TIM0->TCR = 0x1; |
| Gonzakpo | 0:b3e50e98acac | 49 | |
| Gonzakpo | 0:b3e50e98acac | 50 | } |
| Gonzakpo | 0:b3e50e98acac | 51 | |
| Gonzakpo | 0:b3e50e98acac | 52 |