Benoît Locher / mbedNet

Rewrite from scratch a TCP/IP stack for mbed. So far the following parts are usable: Drivers: - EMAC driver (from CMSIS 2.0) Protocols: - Ethernet protocol - ARP over ethernet for IPv4 - IPv4 over Ethernet - ICMPv4 over IPv4 - UDPv4 over IPv4 APIs: - Sockets for UDPv4 The structure of this stack is designed to be very modular. Each protocol can register one or more protocol to handle its payload, and in each protocol, an API can be hooked (like Sockets for example). This is an early release.

lpc17xx_clkpwr.h@7:8e12f7357b9f, 2011-06-26 (annotated)

Committer:
Benoit
Date:
Sun Jun 26 09:56:31 2011 +0000
Revision:
7:8e12f7357b9f
Parent:
5:3cd83fcb1467 
Added IPv4 global broadcast address to processed frames inside IPv4 layer.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Benoit 4:cb3dc3361be5 1 /* @cond */
Benoit 0:19f5f51584de 2 /***********************************************************************//**
Benoit 0:19f5f51584de 3 * @file lpc17xx_clkpwr.h
Benoit 0:19f5f51584de 4 * @brief Contains all macro definitions and function prototypes
Benoit 0:19f5f51584de 5 * support for Clock and Power Control firmware library on LPC17xx
Benoit 0:19f5f51584de 6 * @version 2.0
Benoit 0:19f5f51584de 7 * @date 21. May. 2010
Benoit 0:19f5f51584de 8 * @author NXP MCU SW Application Team
Benoit 0:19f5f51584de 9 **************************************************************************
Benoit 0:19f5f51584de 10 * Software that is described herein is for illustrative purposes only
Benoit 0:19f5f51584de 11 * which provides customers with programming information regarding the
Benoit 0:19f5f51584de 12 * products. This software is supplied "AS IS" without any warranties.
Benoit 0:19f5f51584de 13 * NXP Semiconductors assumes no responsibility or liability for the
Benoit 0:19f5f51584de 14 * use of the software, conveys no license or title under any patent,
Benoit 0:19f5f51584de 15 * copyright, or mask work right to the product. NXP Semiconductors
Benoit 0:19f5f51584de 16 * reserves the right to make changes in the software without
Benoit 0:19f5f51584de 17 * notification. NXP Semiconductors also make no representation or
Benoit 0:19f5f51584de 18 * warranty that such application will be suitable for the specified
Benoit 0:19f5f51584de 19 * use without further testing or modification.
Benoit 0:19f5f51584de 20 **************************************************************************/
Benoit 0:19f5f51584de 21
Benoit 0:19f5f51584de 22 /* Peripheral group ----------------------------------------------------------- */
Benoit 0:19f5f51584de 23 /** @defgroup CLKPWR CLKPWR
Benoit 0:19f5f51584de 24 * @ingroup LPC1700CMSIS_FwLib_Drivers
Benoit 0:19f5f51584de 25 * @{
Benoit 0:19f5f51584de 26 */
Benoit 0:19f5f51584de 27
Benoit 0:19f5f51584de 28 #ifndef LPC17XX_CLKPWR_H_
Benoit 0:19f5f51584de 29 #define LPC17XX_CLKPWR_H_
Benoit 0:19f5f51584de 30
Benoit 0:19f5f51584de 31 /* Includes ------------------------------------------------------------------- */
Benoit 0:19f5f51584de 32 #include "lpc17xx.h"
Benoit 0:19f5f51584de 33 #include "lpc_types.h"
Benoit 0:19f5f51584de 34
Benoit 0:19f5f51584de 35 #ifdef __cplusplus
Benoit 0:19f5f51584de 36 extern "C"
Benoit 0:19f5f51584de 37 {
Benoit 0:19f5f51584de 38 #endif
Benoit 0:19f5f51584de 39
Benoit 0:19f5f51584de 40 /* Public Macros -------------------------------------------------------------- */
Benoit 0:19f5f51584de 41 /** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
Benoit 0:19f5f51584de 42 * @{
Benoit 0:19f5f51584de 43 */
Benoit 0:19f5f51584de 44
Benoit 0:19f5f51584de 45 /**********************************************************************
Benoit 0:19f5f51584de 46 * Peripheral Clock Selection Definitions
Benoit 0:19f5f51584de 47 **********************************************************************/
Benoit 0:19f5f51584de 48 /** Peripheral clock divider bit position for WDT */
Benoit 0:19f5f51584de 49 #define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
Benoit 0:19f5f51584de 50 /** Peripheral clock divider bit position for TIMER0 */
Benoit 0:19f5f51584de 51 #define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
Benoit 0:19f5f51584de 52 /** Peripheral clock divider bit position for TIMER1 */
Benoit 0:19f5f51584de 53 #define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
Benoit 0:19f5f51584de 54 /** Peripheral clock divider bit position for UART0 */
Benoit 0:19f5f51584de 55 #define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
Benoit 0:19f5f51584de 56 /** Peripheral clock divider bit position for UART1 */
Benoit 0:19f5f51584de 57 #define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
Benoit 0:19f5f51584de 58 /** Peripheral clock divider bit position for PWM1 */
Benoit 0:19f5f51584de 59 #define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
Benoit 0:19f5f51584de 60 /** Peripheral clock divider bit position for I2C0 */
Benoit 0:19f5f51584de 61 #define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
Benoit 0:19f5f51584de 62 /** Peripheral clock divider bit position for SPI */
Benoit 0:19f5f51584de 63 #define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
Benoit 0:19f5f51584de 64 /** Peripheral clock divider bit position for SSP1 */
Benoit 0:19f5f51584de 65 #define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
Benoit 0:19f5f51584de 66 /** Peripheral clock divider bit position for DAC */
Benoit 0:19f5f51584de 67 #define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
Benoit 0:19f5f51584de 68 /** Peripheral clock divider bit position for ADC */
Benoit 0:19f5f51584de 69 #define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
Benoit 0:19f5f51584de 70 /** Peripheral clock divider bit position for CAN1 */
Benoit 0:19f5f51584de 71 #define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
Benoit 0:19f5f51584de 72 /** Peripheral clock divider bit position for CAN2 */
Benoit 0:19f5f51584de 73 #define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
Benoit 0:19f5f51584de 74 /** Peripheral clock divider bit position for ACF */
Benoit 0:19f5f51584de 75 #define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
Benoit 0:19f5f51584de 76 /** Peripheral clock divider bit position for QEI */
Benoit 0:19f5f51584de 77 #define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
Benoit 0:19f5f51584de 78 /** Peripheral clock divider bit position for PCB */
Benoit 0:19f5f51584de 79 #define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
Benoit 0:19f5f51584de 80 /** Peripheral clock divider bit position for I2C1 */
Benoit 0:19f5f51584de 81 #define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
Benoit 0:19f5f51584de 82 /** Peripheral clock divider bit position for SSP0 */
Benoit 0:19f5f51584de 83 #define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
Benoit 0:19f5f51584de 84 /** Peripheral clock divider bit position for TIMER2 */
Benoit 0:19f5f51584de 85 #define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
Benoit 0:19f5f51584de 86 /** Peripheral clock divider bit position for TIMER3 */
Benoit 0:19f5f51584de 87 #define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
Benoit 0:19f5f51584de 88 /** Peripheral clock divider bit position for UART2 */
Benoit 0:19f5f51584de 89 #define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
Benoit 0:19f5f51584de 90 /** Peripheral clock divider bit position for UART3 */
Benoit 0:19f5f51584de 91 #define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
Benoit 0:19f5f51584de 92 /** Peripheral clock divider bit position for I2C2 */
Benoit 0:19f5f51584de 93 #define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
Benoit 0:19f5f51584de 94 /** Peripheral clock divider bit position for I2S */
Benoit 0:19f5f51584de 95 #define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
Benoit 0:19f5f51584de 96 /** Peripheral clock divider bit position for RIT */
Benoit 0:19f5f51584de 97 #define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
Benoit 0:19f5f51584de 98 /** Peripheral clock divider bit position for SYSCON */
Benoit 0:19f5f51584de 99 #define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
Benoit 0:19f5f51584de 100 /** Peripheral clock divider bit position for MC */
Benoit 0:19f5f51584de 101 #define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
Benoit 0:19f5f51584de 102
Benoit 0:19f5f51584de 103 /** Macro for Peripheral Clock Selection register bit values
Benoit 1:f4040665bc61 104 * Note: When CCLK_DIV_8, Peripheral�s clock is selected to
Benoit 0:19f5f51584de 105 * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
Benoit 1:f4040665bc61 106 * when �11�selects PCLK_xyz = CCLK/6 */
Benoit 0:19f5f51584de 107 /* Peripheral clock divider is set to 4 from CCLK */
Benoit 0:19f5f51584de 108 #define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
Benoit 0:19f5f51584de 109 /** Peripheral clock divider is the same with CCLK */
Benoit 0:19f5f51584de 110 #define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
Benoit 0:19f5f51584de 111 /** Peripheral clock divider is set to 2 from CCLK */
Benoit 0:19f5f51584de 112 #define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
Benoit 0:19f5f51584de 113
Benoit 0:19f5f51584de 114
Benoit 0:19f5f51584de 115 /********************************************************************
Benoit 0:19f5f51584de 116 * Power Control for Peripherals Definitions
Benoit 0:19f5f51584de 117 **********************************************************************/
Benoit 0:19f5f51584de 118 /** Timer/Counter 0 power/clock control bit */
Benoit 0:19f5f51584de 119 #define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
Benoit 0:19f5f51584de 120 /* Timer/Counter 1 power/clock control bit */
Benoit 0:19f5f51584de 121 #define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
Benoit 0:19f5f51584de 122 /** UART0 power/clock control bit */
Benoit 0:19f5f51584de 123 #define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
Benoit 0:19f5f51584de 124 /** UART1 power/clock control bit */
Benoit 0:19f5f51584de 125 #define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
Benoit 0:19f5f51584de 126 /** PWM1 power/clock control bit */
Benoit 0:19f5f51584de 127 #define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
Benoit 0:19f5f51584de 128 /** The I2C0 interface power/clock control bit */
Benoit 0:19f5f51584de 129 #define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
Benoit 0:19f5f51584de 130 /** The SPI interface power/clock control bit */
Benoit 0:19f5f51584de 131 #define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
Benoit 0:19f5f51584de 132 /** The RTC power/clock control bit */
Benoit 0:19f5f51584de 133 #define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
Benoit 0:19f5f51584de 134 /** The SSP1 interface power/clock control bit */
Benoit 0:19f5f51584de 135 #define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
Benoit 0:19f5f51584de 136 /** A/D converter 0 (ADC0) power/clock control bit */
Benoit 0:19f5f51584de 137 #define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
Benoit 0:19f5f51584de 138 /** CAN Controller 1 power/clock control bit */
Benoit 0:19f5f51584de 139 #define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
Benoit 0:19f5f51584de 140 /** CAN Controller 2 power/clock control bit */
Benoit 0:19f5f51584de 141 #define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
Benoit 0:19f5f51584de 142 /** GPIO power/clock control bit */
Benoit 0:19f5f51584de 143 #define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
Benoit 0:19f5f51584de 144 /** Repetitive Interrupt Timer power/clock control bit */
Benoit 0:19f5f51584de 145 #define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
Benoit 0:19f5f51584de 146 /** Motor Control PWM */
Benoit 0:19f5f51584de 147 #define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
Benoit 0:19f5f51584de 148 /** Quadrature Encoder Interface power/clock control bit */
Benoit 0:19f5f51584de 149 #define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
Benoit 0:19f5f51584de 150 /** The I2C1 interface power/clock control bit */
Benoit 0:19f5f51584de 151 #define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
Benoit 0:19f5f51584de 152 /** The SSP0 interface power/clock control bit */
Benoit 0:19f5f51584de 153 #define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
Benoit 0:19f5f51584de 154 /** Timer 2 power/clock control bit */
Benoit 0:19f5f51584de 155 #define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
Benoit 0:19f5f51584de 156 /** Timer 3 power/clock control bit */
Benoit 0:19f5f51584de 157 #define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
Benoit 0:19f5f51584de 158 /** UART 2 power/clock control bit */
Benoit 0:19f5f51584de 159 #define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
Benoit 0:19f5f51584de 160 /** UART 3 power/clock control bit */
Benoit 0:19f5f51584de 161 #define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
Benoit 0:19f5f51584de 162 /** I2C interface 2 power/clock control bit */
Benoit 0:19f5f51584de 163 #define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
Benoit 0:19f5f51584de 164 /** I2S interface power/clock control bit*/
Benoit 0:19f5f51584de 165 #define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
Benoit 0:19f5f51584de 166 /** GP DMA function power/clock control bit*/
Benoit 0:19f5f51584de 167 #define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
Benoit 0:19f5f51584de 168 /** Ethernet block power/clock control bit*/
Benoit 0:19f5f51584de 169 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
Benoit 0:19f5f51584de 170 /** USB interface power/clock control bit*/
Benoit 0:19f5f51584de 171 #define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
Benoit 0:19f5f51584de 172
Benoit 0:19f5f51584de 173
Benoit 0:19f5f51584de 174 /**
Benoit 0:19f5f51584de 175 * @}
Benoit 0:19f5f51584de 176 */
Benoit 0:19f5f51584de 177 /* Private Macros ------------------------------------------------------------- */
Benoit 0:19f5f51584de 178 /** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
Benoit 0:19f5f51584de 179 * @{
Benoit 0:19f5f51584de 180 */
Benoit 0:19f5f51584de 181
Benoit 0:19f5f51584de 182 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Benoit 0:19f5f51584de 183 /*********************************************************************//**
Benoit 0:19f5f51584de 184 * Macro defines for Clock Source Select Register
Benoit 0:19f5f51584de 185 **********************************************************************/
Benoit 0:19f5f51584de 186 /** Internal RC oscillator */
Benoit 0:19f5f51584de 187 #define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
Benoit 0:19f5f51584de 188 /** Main oscillator */
Benoit 0:19f5f51584de 189 #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
Benoit 0:19f5f51584de 190 /** RTC oscillator */
Benoit 0:19f5f51584de 191 #define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
Benoit 0:19f5f51584de 192 /** Clock source selection bit mask */
Benoit 0:19f5f51584de 193 #define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
Benoit 0:19f5f51584de 194
Benoit 0:19f5f51584de 195 /*********************************************************************//**
Benoit 0:19f5f51584de 196 * Macro defines for Clock Output Configuration Register
Benoit 0:19f5f51584de 197 **********************************************************************/
Benoit 0:19f5f51584de 198 /* Clock Output Configuration register definition */
Benoit 0:19f5f51584de 199 /** Selects the CPU clock as the CLKOUT source */
Benoit 0:19f5f51584de 200 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
Benoit 0:19f5f51584de 201 /** Selects the main oscillator as the CLKOUT source */
Benoit 0:19f5f51584de 202 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
Benoit 0:19f5f51584de 203 /** Selects the Internal RC oscillator as the CLKOUT source */
Benoit 0:19f5f51584de 204 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
Benoit 0:19f5f51584de 205 /** Selects the USB clock as the CLKOUT source */
Benoit 0:19f5f51584de 206 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
Benoit 0:19f5f51584de 207 /** Selects the RTC oscillator as the CLKOUT source */
Benoit 0:19f5f51584de 208 #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
Benoit 0:19f5f51584de 209 /** Integer value to divide the output clock by, minus one */
Benoit 0:19f5f51584de 210 #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
Benoit 0:19f5f51584de 211 /** CLKOUT enable control */
Benoit 0:19f5f51584de 212 #define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
Benoit 0:19f5f51584de 213 /** CLKOUT activity indication */
Benoit 0:19f5f51584de 214 #define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
Benoit 0:19f5f51584de 215 /** Clock source selection bit mask */
Benoit 0:19f5f51584de 216 #define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
Benoit 0:19f5f51584de 217
Benoit 0:19f5f51584de 218 /*********************************************************************//**
Benoit 0:19f5f51584de 219 * Macro defines for PPL0 Control Register
Benoit 0:19f5f51584de 220 **********************************************************************/
Benoit 0:19f5f51584de 221 /** PLL 0 control enable */
Benoit 0:19f5f51584de 222 #define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
Benoit 0:19f5f51584de 223 /** PLL 0 control connect */
Benoit 0:19f5f51584de 224 #define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
Benoit 0:19f5f51584de 225 /** PLL 0 control bit mask */
Benoit 0:19f5f51584de 226 #define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
Benoit 0:19f5f51584de 227
Benoit 0:19f5f51584de 228 /*********************************************************************//**
Benoit 0:19f5f51584de 229 * Macro defines for PPL0 Configuration Register
Benoit 0:19f5f51584de 230 **********************************************************************/
Benoit 0:19f5f51584de 231 /** PLL 0 Configuration MSEL field */
Benoit 0:19f5f51584de 232 #define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
Benoit 0:19f5f51584de 233 /** PLL 0 Configuration NSEL field */
Benoit 0:19f5f51584de 234 #define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
Benoit 0:19f5f51584de 235 /** PLL 0 Configuration bit mask */
Benoit 0:19f5f51584de 236 #define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
Benoit 0:19f5f51584de 237
Benoit 0:19f5f51584de 238
Benoit 0:19f5f51584de 239 /*********************************************************************//**
Benoit 0:19f5f51584de 240 * Macro defines for PPL0 Status Register
Benoit 0:19f5f51584de 241 **********************************************************************/
Benoit 0:19f5f51584de 242 /** PLL 0 MSEL value */
Benoit 0:19f5f51584de 243 #define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
Benoit 0:19f5f51584de 244 /** PLL NSEL get value */
Benoit 0:19f5f51584de 245 #define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
Benoit 0:19f5f51584de 246 /** PLL status enable bit */
Benoit 0:19f5f51584de 247 #define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
Benoit 0:19f5f51584de 248 /** PLL status Connect bit */
Benoit 0:19f5f51584de 249 #define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
Benoit 0:19f5f51584de 250 /** PLL status lock */
Benoit 0:19f5f51584de 251 #define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
Benoit 0:19f5f51584de 252
Benoit 0:19f5f51584de 253 /*********************************************************************//**
Benoit 0:19f5f51584de 254 * Macro defines for PPL0 Feed Register
Benoit 0:19f5f51584de 255 **********************************************************************/
Benoit 0:19f5f51584de 256 /** PLL0 Feed bit mask */
Benoit 0:19f5f51584de 257 #define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
Benoit 0:19f5f51584de 258
Benoit 0:19f5f51584de 259 /*********************************************************************//**
Benoit 0:19f5f51584de 260 * Macro defines for PLL1 Control Register
Benoit 0:19f5f51584de 261 **********************************************************************/
Benoit 0:19f5f51584de 262 /** USB PLL control enable */
Benoit 0:19f5f51584de 263 #define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
Benoit 0:19f5f51584de 264 /** USB PLL control connect */
Benoit 0:19f5f51584de 265 #define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
Benoit 0:19f5f51584de 266 /** USB PLL control bit mask */
Benoit 0:19f5f51584de 267 #define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
Benoit 0:19f5f51584de 268
Benoit 0:19f5f51584de 269 /*********************************************************************//**
Benoit 0:19f5f51584de 270 * Macro defines for PLL1 Configuration Register
Benoit 0:19f5f51584de 271 **********************************************************************/
Benoit 0:19f5f51584de 272 /** USB PLL MSEL set value */
Benoit 0:19f5f51584de 273 #define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
Benoit 0:19f5f51584de 274 /** USB PLL PSEL set value */
Benoit 0:19f5f51584de 275 #define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
Benoit 0:19f5f51584de 276 /** USB PLL configuration bit mask */
Benoit 0:19f5f51584de 277 #define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
Benoit 0:19f5f51584de 278
Benoit 0:19f5f51584de 279 /*********************************************************************//**
Benoit 0:19f5f51584de 280 * Macro defines for PLL1 Status Register
Benoit 0:19f5f51584de 281 **********************************************************************/
Benoit 0:19f5f51584de 282 /** USB PLL MSEL get value */
Benoit 0:19f5f51584de 283 #define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
Benoit 0:19f5f51584de 284 /** USB PLL PSEL get value */
Benoit 0:19f5f51584de 285 #define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
Benoit 0:19f5f51584de 286 /** USB PLL status enable bit */
Benoit 0:19f5f51584de 287 #define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
Benoit 0:19f5f51584de 288 /** USB PLL status Connect bit */
Benoit 0:19f5f51584de 289 #define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
Benoit 0:19f5f51584de 290 /** USB PLL status lock */
Benoit 0:19f5f51584de 291 #define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
Benoit 0:19f5f51584de 292
Benoit 0:19f5f51584de 293 /*********************************************************************//**
Benoit 0:19f5f51584de 294 * Macro defines for PLL1 Feed Register
Benoit 0:19f5f51584de 295 **********************************************************************/
Benoit 0:19f5f51584de 296 /** PLL1 Feed bit mask */
Benoit 0:19f5f51584de 297 #define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
Benoit 0:19f5f51584de 298
Benoit 0:19f5f51584de 299 /*********************************************************************//**
Benoit 0:19f5f51584de 300 * Macro defines for CPU Clock Configuration Register
Benoit 0:19f5f51584de 301 **********************************************************************/
Benoit 0:19f5f51584de 302 /** CPU Clock configuration bit mask */
Benoit 0:19f5f51584de 303 #define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
Benoit 0:19f5f51584de 304
Benoit 0:19f5f51584de 305 /*********************************************************************//**
Benoit 0:19f5f51584de 306 * Macro defines for USB Clock Configuration Register
Benoit 0:19f5f51584de 307 **********************************************************************/
Benoit 0:19f5f51584de 308 /** USB Clock Configuration bit mask */
Benoit 0:19f5f51584de 309 #define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
Benoit 0:19f5f51584de 310
Benoit 0:19f5f51584de 311 /*********************************************************************//**
Benoit 0:19f5f51584de 312 * Macro defines for IRC Trim Register
Benoit 0:19f5f51584de 313 **********************************************************************/
Benoit 0:19f5f51584de 314 /** IRC Trim bit mask */
Benoit 0:19f5f51584de 315 #define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
Benoit 0:19f5f51584de 316
Benoit 0:19f5f51584de 317 /*********************************************************************//**
Benoit 0:19f5f51584de 318 * Macro defines for Peripheral Clock Selection Register 0 and 1
Benoit 0:19f5f51584de 319 **********************************************************************/
Benoit 0:19f5f51584de 320 /** Peripheral Clock Selection 0 mask bit */
Benoit 0:19f5f51584de 321 #define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
Benoit 0:19f5f51584de 322 /** Peripheral Clock Selection 1 mask bit */
Benoit 0:19f5f51584de 323 #define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
Benoit 0:19f5f51584de 324 /** Macro to set peripheral clock of each type
Benoit 0:19f5f51584de 325 * p: position of two bits that hold divider of peripheral clock
Benoit 0:19f5f51584de 326 * n: value of divider of peripheral clock to be set */
Benoit 0:19f5f51584de 327 #define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
Benoit 0:19f5f51584de 328 /** Macro to mask peripheral clock of each type */
Benoit 0:19f5f51584de 329 #define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
Benoit 0:19f5f51584de 330 /** Macro to get peripheral clock of each type */
Benoit 0:19f5f51584de 331 #define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
Benoit 0:19f5f51584de 332
Benoit 0:19f5f51584de 333 /*********************************************************************//**
Benoit 0:19f5f51584de 334 * Macro defines for Power Mode Control Register
Benoit 0:19f5f51584de 335 **********************************************************************/
Benoit 0:19f5f51584de 336 /** Power mode control bit 0 */
Benoit 0:19f5f51584de 337 #define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
Benoit 0:19f5f51584de 338 /** Power mode control bit 1 */
Benoit 0:19f5f51584de 339 #define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
Benoit 0:19f5f51584de 340 /** Brown-Out Reduced Power Mode */
Benoit 0:19f5f51584de 341 #define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
Benoit 0:19f5f51584de 342 /** Brown-Out Global Disable */
Benoit 0:19f5f51584de 343 #define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
Benoit 0:19f5f51584de 344 /** Brown Out Reset Disable */
Benoit 0:19f5f51584de 345 #define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
Benoit 0:19f5f51584de 346 /** Sleep Mode entry flag */
Benoit 0:19f5f51584de 347 #define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
Benoit 0:19f5f51584de 348 /** Deep Sleep entry flag */
Benoit 0:19f5f51584de 349 #define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
Benoit 0:19f5f51584de 350 /** Power-down entry flag */
Benoit 0:19f5f51584de 351 #define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
Benoit 0:19f5f51584de 352 /** Deep Power-down entry flag */
Benoit 0:19f5f51584de 353 #define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
Benoit 0:19f5f51584de 354
Benoit 0:19f5f51584de 355 /*********************************************************************//**
Benoit 0:19f5f51584de 356 * Macro defines for Power Control for Peripheral Register
Benoit 0:19f5f51584de 357 **********************************************************************/
Benoit 0:19f5f51584de 358 /** Power Control for Peripherals bit mask */
Benoit 0:19f5f51584de 359 #define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
Benoit 0:19f5f51584de 360
Benoit 0:19f5f51584de 361 /**
Benoit 0:19f5f51584de 362 * @}
Benoit 0:19f5f51584de 363 */
Benoit 0:19f5f51584de 364
Benoit 0:19f5f51584de 365
Benoit 0:19f5f51584de 366 /* Public Functions ----------------------------------------------------------- */
Benoit 0:19f5f51584de 367 /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
Benoit 0:19f5f51584de 368 * @{
Benoit 0:19f5f51584de 369 */
Benoit 0:19f5f51584de 370
Benoit 0:19f5f51584de 371 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
Benoit 0:19f5f51584de 372 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
Benoit 0:19f5f51584de 373 uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
Benoit 0:19f5f51584de 374 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
Benoit 0:19f5f51584de 375 void CLKPWR_Sleep(void);
Benoit 0:19f5f51584de 376 void CLKPWR_DeepSleep(void);
Benoit 0:19f5f51584de 377 void CLKPWR_PowerDown(void);
Benoit 0:19f5f51584de 378 void CLKPWR_DeepPowerDown(void);
Benoit 0:19f5f51584de 379
Benoit 0:19f5f51584de 380 /**
Benoit 0:19f5f51584de 381 * @}
Benoit 0:19f5f51584de 382 */
Benoit 0:19f5f51584de 383
Benoit 0:19f5f51584de 384
Benoit 0:19f5f51584de 385 #ifdef __cplusplus
Benoit 0:19f5f51584de 386 }
Benoit 0:19f5f51584de 387 #endif
Benoit 0:19f5f51584de 388
Benoit 0:19f5f51584de 389 #endif /* LPC17XX_CLKPWR_H_ */
Benoit 0:19f5f51584de 390
Benoit 0:19f5f51584de 391 /**
Benoit 0:19f5f51584de 392 * @}
Benoit 0:19f5f51584de 393 */
Benoit 0:19f5f51584de 394
Benoit 0:19f5f51584de 395 /* --------------------------------- End Of File ------------------------------ */
Benoit 5:3cd83fcb1467 396 /* @endcond */