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Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h@82:0b31dbcd4769, 2014-01-31 (annotated)

Committer:
mbed_official
Date:
Fri Jan 31 10:00:06 2014 +0000
Revision:
82:0b31dbcd4769
Synchronized with git revision 74409cbd593d1daab530a57baaa563f30b04b018



Full URL: https://github.com/mbedmicro/mbed/commit/74409cbd593d1daab530a57baaa563f30b04b018/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 82:0b31dbcd4769 1 /*
mbed_official 82:0b31dbcd4769 2 ** ###################################################################
mbed_official 82:0b31dbcd4769 3 ** Processors: MKL05Z32FK4
mbed_official 82:0b31dbcd4769 4 ** MKL05Z32LC4
mbed_official 82:0b31dbcd4769 5 ** MKL05Z32VLF4
mbed_official 82:0b31dbcd4769 6 **
mbed_official 82:0b31dbcd4769 7 ** Compilers: ARM Compiler
mbed_official 82:0b31dbcd4769 8 ** Freescale C/C++ for Embedded ARM
mbed_official 82:0b31dbcd4769 9 ** GNU C Compiler
mbed_official 82:0b31dbcd4769 10 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 82:0b31dbcd4769 11 **
mbed_official 82:0b31dbcd4769 12 ** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
mbed_official 82:0b31dbcd4769 13 ** Version: rev. 1.3, 2012-10-04
mbed_official 82:0b31dbcd4769 14 **
mbed_official 82:0b31dbcd4769 15 ** Abstract:
mbed_official 82:0b31dbcd4769 16 ** CMSIS Peripheral Access Layer for MKL05Z4
mbed_official 82:0b31dbcd4769 17 **
mbed_official 82:0b31dbcd4769 18 ** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
mbed_official 82:0b31dbcd4769 19 **
mbed_official 82:0b31dbcd4769 20 ** http: www.freescale.com
mbed_official 82:0b31dbcd4769 21 ** mail: support@freescale.com
mbed_official 82:0b31dbcd4769 22 **
mbed_official 82:0b31dbcd4769 23 ** Revisions:
mbed_official 82:0b31dbcd4769 24 ** - rev. 1.0 (2012-06-08)
mbed_official 82:0b31dbcd4769 25 ** Initial version.
mbed_official 82:0b31dbcd4769 26 ** - rev. 1.1 (2012-06-21)
mbed_official 82:0b31dbcd4769 27 ** Update according to reference manual rev. 1.
mbed_official 82:0b31dbcd4769 28 ** - rev. 1.2 (2012-08-01)
mbed_official 82:0b31dbcd4769 29 ** Device type UARTLP changed to UART0.
mbed_official 82:0b31dbcd4769 30 ** Missing PORTB_IRQn interrupt number definition added.
mbed_official 82:0b31dbcd4769 31 ** - rev. 1.3 (2012-10-04)
mbed_official 82:0b31dbcd4769 32 ** Update according to reference manual rev. 3.
mbed_official 82:0b31dbcd4769 33 **
mbed_official 82:0b31dbcd4769 34 ** ###################################################################
mbed_official 82:0b31dbcd4769 35 */
mbed_official 82:0b31dbcd4769 36
mbed_official 82:0b31dbcd4769 37 /**
mbed_official 82:0b31dbcd4769 38 * @file MKL05Z4.h
mbed_official 82:0b31dbcd4769 39 * @version 1.3
mbed_official 82:0b31dbcd4769 40 * @date 2012-10-04
mbed_official 82:0b31dbcd4769 41 * @brief CMSIS Peripheral Access Layer for MKL05Z4
mbed_official 82:0b31dbcd4769 42 *
mbed_official 82:0b31dbcd4769 43 * CMSIS Peripheral Access Layer for MKL05Z4
mbed_official 82:0b31dbcd4769 44 */
mbed_official 82:0b31dbcd4769 45
mbed_official 82:0b31dbcd4769 46 #if !defined(MKL05Z4_H_)
mbed_official 82:0b31dbcd4769 47 #define MKL05Z4_H_ /**< Symbol preventing repeated inclusion */
mbed_official 82:0b31dbcd4769 48
mbed_official 82:0b31dbcd4769 49 /** Memory map major version (memory maps with equal major version number are
mbed_official 82:0b31dbcd4769 50 * compatible) */
mbed_official 82:0b31dbcd4769 51 #define MCU_MEM_MAP_VERSION 0x0100u
mbed_official 82:0b31dbcd4769 52 /** Memory map minor version */
mbed_official 82:0b31dbcd4769 53 #define MCU_MEM_MAP_VERSION_MINOR 0x0003u
mbed_official 82:0b31dbcd4769 54
mbed_official 82:0b31dbcd4769 55
mbed_official 82:0b31dbcd4769 56 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 57 -- Interrupt vector numbers
mbed_official 82:0b31dbcd4769 58 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 59
mbed_official 82:0b31dbcd4769 60 /**
mbed_official 82:0b31dbcd4769 61 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
mbed_official 82:0b31dbcd4769 62 * @{
mbed_official 82:0b31dbcd4769 63 */
mbed_official 82:0b31dbcd4769 64
mbed_official 82:0b31dbcd4769 65 /** Interrupt Number Definitions */
mbed_official 82:0b31dbcd4769 66 typedef enum IRQn {
mbed_official 82:0b31dbcd4769 67 /* Core interrupts */
mbed_official 82:0b31dbcd4769 68 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
mbed_official 82:0b31dbcd4769 69 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
mbed_official 82:0b31dbcd4769 70 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
mbed_official 82:0b31dbcd4769 71 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
mbed_official 82:0b31dbcd4769 72 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
mbed_official 82:0b31dbcd4769 73
mbed_official 82:0b31dbcd4769 74 /* Device specific interrupts */
mbed_official 82:0b31dbcd4769 75 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
mbed_official 82:0b31dbcd4769 76 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
mbed_official 82:0b31dbcd4769 77 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
mbed_official 82:0b31dbcd4769 78 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
mbed_official 82:0b31dbcd4769 79 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
mbed_official 82:0b31dbcd4769 80 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
mbed_official 82:0b31dbcd4769 81 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
mbed_official 82:0b31dbcd4769 82 LLW_IRQn = 7, /**< Low Leakage Wakeup */
mbed_official 82:0b31dbcd4769 83 I2C0_IRQn = 8, /**< I2C0 interrupt */
mbed_official 82:0b31dbcd4769 84 Reserved25_IRQn = 9, /**< Reserved interrupt 25 */
mbed_official 82:0b31dbcd4769 85 SPI0_IRQn = 10, /**< SPI0 interrupt */
mbed_official 82:0b31dbcd4769 86 Reserved27_IRQn = 11, /**< Reserved interrupt 27 */
mbed_official 82:0b31dbcd4769 87 UART0_IRQn = 12, /**< UART0 status/error interrupt */
mbed_official 82:0b31dbcd4769 88 Reserved29_IRQn = 13, /**< Reserved interrupt 29 */
mbed_official 82:0b31dbcd4769 89 Reserved30_IRQn = 14, /**< Reserved interrupt 30 */
mbed_official 82:0b31dbcd4769 90 ADC0_IRQn = 15, /**< ADC0 interrupt */
mbed_official 82:0b31dbcd4769 91 CMP0_IRQn = 16, /**< CMP0 interrupt */
mbed_official 82:0b31dbcd4769 92 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
mbed_official 82:0b31dbcd4769 93 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
mbed_official 82:0b31dbcd4769 94 Reserved35_IRQn = 19, /**< Reserved interrupt 35 */
mbed_official 82:0b31dbcd4769 95 RTC_IRQn = 20, /**< RTC interrupt */
mbed_official 82:0b31dbcd4769 96 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
mbed_official 82:0b31dbcd4769 97 PIT_IRQn = 22, /**< PIT timer interrupt */
mbed_official 82:0b31dbcd4769 98 Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
mbed_official 82:0b31dbcd4769 99 Reserved40_IRQn = 24, /**< Reserved interrupt 40 */
mbed_official 82:0b31dbcd4769 100 DAC0_IRQn = 25, /**< DAC0 interrupt */
mbed_official 82:0b31dbcd4769 101 TSI0_IRQn = 26, /**< TSI0 interrupt */
mbed_official 82:0b31dbcd4769 102 MCG_IRQn = 27, /**< MCG interrupt */
mbed_official 82:0b31dbcd4769 103 LPTimer_IRQn = 28, /**< LPTimer interrupt */
mbed_official 82:0b31dbcd4769 104 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
mbed_official 82:0b31dbcd4769 105 PORTA_IRQn = 30, /**< Port A interrupt */
mbed_official 82:0b31dbcd4769 106 PORTB_IRQn = 31 /**< Port B interrupt */
mbed_official 82:0b31dbcd4769 107 } IRQn_Type;
mbed_official 82:0b31dbcd4769 108
mbed_official 82:0b31dbcd4769 109 /**
mbed_official 82:0b31dbcd4769 110 * @}
mbed_official 82:0b31dbcd4769 111 */ /* end of group Interrupt_vector_numbers */
mbed_official 82:0b31dbcd4769 112
mbed_official 82:0b31dbcd4769 113
mbed_official 82:0b31dbcd4769 114 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 115 -- Cortex M0 Core Configuration
mbed_official 82:0b31dbcd4769 116 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 117
mbed_official 82:0b31dbcd4769 118 /**
mbed_official 82:0b31dbcd4769 119 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
mbed_official 82:0b31dbcd4769 120 * @{
mbed_official 82:0b31dbcd4769 121 */
mbed_official 82:0b31dbcd4769 122
mbed_official 82:0b31dbcd4769 123 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
mbed_official 82:0b31dbcd4769 124 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
mbed_official 82:0b31dbcd4769 125 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
mbed_official 82:0b31dbcd4769 126 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
mbed_official 82:0b31dbcd4769 127 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
mbed_official 82:0b31dbcd4769 128
mbed_official 82:0b31dbcd4769 129 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
mbed_official 82:0b31dbcd4769 130 #include "system_MKL05Z4.h" /* Device specific configuration file */
mbed_official 82:0b31dbcd4769 131
mbed_official 82:0b31dbcd4769 132 /**
mbed_official 82:0b31dbcd4769 133 * @}
mbed_official 82:0b31dbcd4769 134 */ /* end of group Cortex_Core_Configuration */
mbed_official 82:0b31dbcd4769 135
mbed_official 82:0b31dbcd4769 136
mbed_official 82:0b31dbcd4769 137 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 138 -- Device Peripheral Access Layer
mbed_official 82:0b31dbcd4769 139 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 140
mbed_official 82:0b31dbcd4769 141 /**
mbed_official 82:0b31dbcd4769 142 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
mbed_official 82:0b31dbcd4769 143 * @{
mbed_official 82:0b31dbcd4769 144 */
mbed_official 82:0b31dbcd4769 145
mbed_official 82:0b31dbcd4769 146
mbed_official 82:0b31dbcd4769 147 /*
mbed_official 82:0b31dbcd4769 148 ** Start of section using anonymous unions
mbed_official 82:0b31dbcd4769 149 */
mbed_official 82:0b31dbcd4769 150
mbed_official 82:0b31dbcd4769 151 #if defined(__ARMCC_VERSION)
mbed_official 82:0b31dbcd4769 152 #pragma push
mbed_official 82:0b31dbcd4769 153 #pragma anon_unions
mbed_official 82:0b31dbcd4769 154 #elif defined(__CWCC__)
mbed_official 82:0b31dbcd4769 155 #pragma push
mbed_official 82:0b31dbcd4769 156 #pragma cpp_extensions on
mbed_official 82:0b31dbcd4769 157 #elif defined(__GNUC__)
mbed_official 82:0b31dbcd4769 158 /* anonymous unions are enabled by default */
mbed_official 82:0b31dbcd4769 159 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 82:0b31dbcd4769 160 #pragma language=extended
mbed_official 82:0b31dbcd4769 161 #else
mbed_official 82:0b31dbcd4769 162 #error Not supported compiler type
mbed_official 82:0b31dbcd4769 163 #endif
mbed_official 82:0b31dbcd4769 164
mbed_official 82:0b31dbcd4769 165 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 166 -- ADC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 167 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 168
mbed_official 82:0b31dbcd4769 169 /**
mbed_official 82:0b31dbcd4769 170 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 171 * @{
mbed_official 82:0b31dbcd4769 172 */
mbed_official 82:0b31dbcd4769 173
mbed_official 82:0b31dbcd4769 174 /** ADC - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 175 typedef struct {
mbed_official 82:0b31dbcd4769 176 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
mbed_official 82:0b31dbcd4769 177 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
mbed_official 82:0b31dbcd4769 178 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
mbed_official 82:0b31dbcd4769 179 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
mbed_official 82:0b31dbcd4769 180 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
mbed_official 82:0b31dbcd4769 181 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
mbed_official 82:0b31dbcd4769 182 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
mbed_official 82:0b31dbcd4769 183 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
mbed_official 82:0b31dbcd4769 184 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
mbed_official 82:0b31dbcd4769 185 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
mbed_official 82:0b31dbcd4769 186 uint8_t RESERVED_0[4];
mbed_official 82:0b31dbcd4769 187 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
mbed_official 82:0b31dbcd4769 188 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
mbed_official 82:0b31dbcd4769 189 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
mbed_official 82:0b31dbcd4769 190 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
mbed_official 82:0b31dbcd4769 191 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
mbed_official 82:0b31dbcd4769 192 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
mbed_official 82:0b31dbcd4769 193 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
mbed_official 82:0b31dbcd4769 194 } ADC_Type;
mbed_official 82:0b31dbcd4769 195
mbed_official 82:0b31dbcd4769 196 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 197 -- ADC Register Masks
mbed_official 82:0b31dbcd4769 198 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 199
mbed_official 82:0b31dbcd4769 200 /**
mbed_official 82:0b31dbcd4769 201 * @addtogroup ADC_Register_Masks ADC Register Masks
mbed_official 82:0b31dbcd4769 202 * @{
mbed_official 82:0b31dbcd4769 203 */
mbed_official 82:0b31dbcd4769 204
mbed_official 82:0b31dbcd4769 205 /* SC1 Bit Fields */
mbed_official 82:0b31dbcd4769 206 #define ADC_SC1_ADCH_MASK 0x1Fu
mbed_official 82:0b31dbcd4769 207 #define ADC_SC1_ADCH_SHIFT 0
mbed_official 82:0b31dbcd4769 208 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
mbed_official 82:0b31dbcd4769 209 #define ADC_SC1_AIEN_MASK 0x40u
mbed_official 82:0b31dbcd4769 210 #define ADC_SC1_AIEN_SHIFT 6
mbed_official 82:0b31dbcd4769 211 #define ADC_SC1_COCO_MASK 0x80u
mbed_official 82:0b31dbcd4769 212 #define ADC_SC1_COCO_SHIFT 7
mbed_official 82:0b31dbcd4769 213 /* CFG1 Bit Fields */
mbed_official 82:0b31dbcd4769 214 #define ADC_CFG1_ADICLK_MASK 0x3u
mbed_official 82:0b31dbcd4769 215 #define ADC_CFG1_ADICLK_SHIFT 0
mbed_official 82:0b31dbcd4769 216 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
mbed_official 82:0b31dbcd4769 217 #define ADC_CFG1_MODE_MASK 0xCu
mbed_official 82:0b31dbcd4769 218 #define ADC_CFG1_MODE_SHIFT 2
mbed_official 82:0b31dbcd4769 219 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
mbed_official 82:0b31dbcd4769 220 #define ADC_CFG1_ADLSMP_MASK 0x10u
mbed_official 82:0b31dbcd4769 221 #define ADC_CFG1_ADLSMP_SHIFT 4
mbed_official 82:0b31dbcd4769 222 #define ADC_CFG1_ADIV_MASK 0x60u
mbed_official 82:0b31dbcd4769 223 #define ADC_CFG1_ADIV_SHIFT 5
mbed_official 82:0b31dbcd4769 224 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
mbed_official 82:0b31dbcd4769 225 #define ADC_CFG1_ADLPC_MASK 0x80u
mbed_official 82:0b31dbcd4769 226 #define ADC_CFG1_ADLPC_SHIFT 7
mbed_official 82:0b31dbcd4769 227 /* CFG2 Bit Fields */
mbed_official 82:0b31dbcd4769 228 #define ADC_CFG2_ADLSTS_MASK 0x3u
mbed_official 82:0b31dbcd4769 229 #define ADC_CFG2_ADLSTS_SHIFT 0
mbed_official 82:0b31dbcd4769 230 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
mbed_official 82:0b31dbcd4769 231 #define ADC_CFG2_ADHSC_MASK 0x4u
mbed_official 82:0b31dbcd4769 232 #define ADC_CFG2_ADHSC_SHIFT 2
mbed_official 82:0b31dbcd4769 233 #define ADC_CFG2_ADACKEN_MASK 0x8u
mbed_official 82:0b31dbcd4769 234 #define ADC_CFG2_ADACKEN_SHIFT 3
mbed_official 82:0b31dbcd4769 235 #define ADC_CFG2_MUXSEL_MASK 0x10u
mbed_official 82:0b31dbcd4769 236 #define ADC_CFG2_MUXSEL_SHIFT 4
mbed_official 82:0b31dbcd4769 237 /* R Bit Fields */
mbed_official 82:0b31dbcd4769 238 #define ADC_R_D_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 239 #define ADC_R_D_SHIFT 0
mbed_official 82:0b31dbcd4769 240 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
mbed_official 82:0b31dbcd4769 241 /* CV1 Bit Fields */
mbed_official 82:0b31dbcd4769 242 #define ADC_CV1_CV_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 243 #define ADC_CV1_CV_SHIFT 0
mbed_official 82:0b31dbcd4769 244 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
mbed_official 82:0b31dbcd4769 245 /* CV2 Bit Fields */
mbed_official 82:0b31dbcd4769 246 #define ADC_CV2_CV_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 247 #define ADC_CV2_CV_SHIFT 0
mbed_official 82:0b31dbcd4769 248 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
mbed_official 82:0b31dbcd4769 249 /* SC2 Bit Fields */
mbed_official 82:0b31dbcd4769 250 #define ADC_SC2_REFSEL_MASK 0x3u
mbed_official 82:0b31dbcd4769 251 #define ADC_SC2_REFSEL_SHIFT 0
mbed_official 82:0b31dbcd4769 252 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
mbed_official 82:0b31dbcd4769 253 #define ADC_SC2_DMAEN_MASK 0x4u
mbed_official 82:0b31dbcd4769 254 #define ADC_SC2_DMAEN_SHIFT 2
mbed_official 82:0b31dbcd4769 255 #define ADC_SC2_ACREN_MASK 0x8u
mbed_official 82:0b31dbcd4769 256 #define ADC_SC2_ACREN_SHIFT 3
mbed_official 82:0b31dbcd4769 257 #define ADC_SC2_ACFGT_MASK 0x10u
mbed_official 82:0b31dbcd4769 258 #define ADC_SC2_ACFGT_SHIFT 4
mbed_official 82:0b31dbcd4769 259 #define ADC_SC2_ACFE_MASK 0x20u
mbed_official 82:0b31dbcd4769 260 #define ADC_SC2_ACFE_SHIFT 5
mbed_official 82:0b31dbcd4769 261 #define ADC_SC2_ADTRG_MASK 0x40u
mbed_official 82:0b31dbcd4769 262 #define ADC_SC2_ADTRG_SHIFT 6
mbed_official 82:0b31dbcd4769 263 #define ADC_SC2_ADACT_MASK 0x80u
mbed_official 82:0b31dbcd4769 264 #define ADC_SC2_ADACT_SHIFT 7
mbed_official 82:0b31dbcd4769 265 /* SC3 Bit Fields */
mbed_official 82:0b31dbcd4769 266 #define ADC_SC3_AVGS_MASK 0x3u
mbed_official 82:0b31dbcd4769 267 #define ADC_SC3_AVGS_SHIFT 0
mbed_official 82:0b31dbcd4769 268 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
mbed_official 82:0b31dbcd4769 269 #define ADC_SC3_AVGE_MASK 0x4u
mbed_official 82:0b31dbcd4769 270 #define ADC_SC3_AVGE_SHIFT 2
mbed_official 82:0b31dbcd4769 271 #define ADC_SC3_ADCO_MASK 0x8u
mbed_official 82:0b31dbcd4769 272 #define ADC_SC3_ADCO_SHIFT 3
mbed_official 82:0b31dbcd4769 273 #define ADC_SC3_CALF_MASK 0x40u
mbed_official 82:0b31dbcd4769 274 #define ADC_SC3_CALF_SHIFT 6
mbed_official 82:0b31dbcd4769 275 #define ADC_SC3_CAL_MASK 0x80u
mbed_official 82:0b31dbcd4769 276 #define ADC_SC3_CAL_SHIFT 7
mbed_official 82:0b31dbcd4769 277 /* OFS Bit Fields */
mbed_official 82:0b31dbcd4769 278 #define ADC_OFS_OFS_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 279 #define ADC_OFS_OFS_SHIFT 0
mbed_official 82:0b31dbcd4769 280 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
mbed_official 82:0b31dbcd4769 281 /* PG Bit Fields */
mbed_official 82:0b31dbcd4769 282 #define ADC_PG_PG_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 283 #define ADC_PG_PG_SHIFT 0
mbed_official 82:0b31dbcd4769 284 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
mbed_official 82:0b31dbcd4769 285 /* CLPD Bit Fields */
mbed_official 82:0b31dbcd4769 286 #define ADC_CLPD_CLPD_MASK 0x3Fu
mbed_official 82:0b31dbcd4769 287 #define ADC_CLPD_CLPD_SHIFT 0
mbed_official 82:0b31dbcd4769 288 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
mbed_official 82:0b31dbcd4769 289 /* CLPS Bit Fields */
mbed_official 82:0b31dbcd4769 290 #define ADC_CLPS_CLPS_MASK 0x3Fu
mbed_official 82:0b31dbcd4769 291 #define ADC_CLPS_CLPS_SHIFT 0
mbed_official 82:0b31dbcd4769 292 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
mbed_official 82:0b31dbcd4769 293 /* CLP4 Bit Fields */
mbed_official 82:0b31dbcd4769 294 #define ADC_CLP4_CLP4_MASK 0x3FFu
mbed_official 82:0b31dbcd4769 295 #define ADC_CLP4_CLP4_SHIFT 0
mbed_official 82:0b31dbcd4769 296 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
mbed_official 82:0b31dbcd4769 297 /* CLP3 Bit Fields */
mbed_official 82:0b31dbcd4769 298 #define ADC_CLP3_CLP3_MASK 0x1FFu
mbed_official 82:0b31dbcd4769 299 #define ADC_CLP3_CLP3_SHIFT 0
mbed_official 82:0b31dbcd4769 300 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
mbed_official 82:0b31dbcd4769 301 /* CLP2 Bit Fields */
mbed_official 82:0b31dbcd4769 302 #define ADC_CLP2_CLP2_MASK 0xFFu
mbed_official 82:0b31dbcd4769 303 #define ADC_CLP2_CLP2_SHIFT 0
mbed_official 82:0b31dbcd4769 304 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
mbed_official 82:0b31dbcd4769 305 /* CLP1 Bit Fields */
mbed_official 82:0b31dbcd4769 306 #define ADC_CLP1_CLP1_MASK 0x7Fu
mbed_official 82:0b31dbcd4769 307 #define ADC_CLP1_CLP1_SHIFT 0
mbed_official 82:0b31dbcd4769 308 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
mbed_official 82:0b31dbcd4769 309 /* CLP0 Bit Fields */
mbed_official 82:0b31dbcd4769 310 #define ADC_CLP0_CLP0_MASK 0x3Fu
mbed_official 82:0b31dbcd4769 311 #define ADC_CLP0_CLP0_SHIFT 0
mbed_official 82:0b31dbcd4769 312 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
mbed_official 82:0b31dbcd4769 313
mbed_official 82:0b31dbcd4769 314 /**
mbed_official 82:0b31dbcd4769 315 * @}
mbed_official 82:0b31dbcd4769 316 */ /* end of group ADC_Register_Masks */
mbed_official 82:0b31dbcd4769 317
mbed_official 82:0b31dbcd4769 318
mbed_official 82:0b31dbcd4769 319 /* ADC - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 320 /** Peripheral ADC0 base address */
mbed_official 82:0b31dbcd4769 321 #define ADC0_BASE (0x4003B000u)
mbed_official 82:0b31dbcd4769 322 /** Peripheral ADC0 base pointer */
mbed_official 82:0b31dbcd4769 323 #define ADC0 ((ADC_Type *)ADC0_BASE)
mbed_official 82:0b31dbcd4769 324 /** Array initializer of ADC peripheral base pointers */
mbed_official 82:0b31dbcd4769 325 #define ADC_BASES { ADC0 }
mbed_official 82:0b31dbcd4769 326
mbed_official 82:0b31dbcd4769 327 /**
mbed_official 82:0b31dbcd4769 328 * @}
mbed_official 82:0b31dbcd4769 329 */ /* end of group ADC_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 330
mbed_official 82:0b31dbcd4769 331
mbed_official 82:0b31dbcd4769 332 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 333 -- CMP Peripheral Access Layer
mbed_official 82:0b31dbcd4769 334 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 335
mbed_official 82:0b31dbcd4769 336 /**
mbed_official 82:0b31dbcd4769 337 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
mbed_official 82:0b31dbcd4769 338 * @{
mbed_official 82:0b31dbcd4769 339 */
mbed_official 82:0b31dbcd4769 340
mbed_official 82:0b31dbcd4769 341 /** CMP - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 342 typedef struct {
mbed_official 82:0b31dbcd4769 343 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
mbed_official 82:0b31dbcd4769 344 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
mbed_official 82:0b31dbcd4769 345 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
mbed_official 82:0b31dbcd4769 346 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
mbed_official 82:0b31dbcd4769 347 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 348 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
mbed_official 82:0b31dbcd4769 349 } CMP_Type;
mbed_official 82:0b31dbcd4769 350
mbed_official 82:0b31dbcd4769 351 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 352 -- CMP Register Masks
mbed_official 82:0b31dbcd4769 353 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 354
mbed_official 82:0b31dbcd4769 355 /**
mbed_official 82:0b31dbcd4769 356 * @addtogroup CMP_Register_Masks CMP Register Masks
mbed_official 82:0b31dbcd4769 357 * @{
mbed_official 82:0b31dbcd4769 358 */
mbed_official 82:0b31dbcd4769 359
mbed_official 82:0b31dbcd4769 360 /* CR0 Bit Fields */
mbed_official 82:0b31dbcd4769 361 #define CMP_CR0_HYSTCTR_MASK 0x3u
mbed_official 82:0b31dbcd4769 362 #define CMP_CR0_HYSTCTR_SHIFT 0
mbed_official 82:0b31dbcd4769 363 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
mbed_official 82:0b31dbcd4769 364 #define CMP_CR0_FILTER_CNT_MASK 0x70u
mbed_official 82:0b31dbcd4769 365 #define CMP_CR0_FILTER_CNT_SHIFT 4
mbed_official 82:0b31dbcd4769 366 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
mbed_official 82:0b31dbcd4769 367 /* CR1 Bit Fields */
mbed_official 82:0b31dbcd4769 368 #define CMP_CR1_EN_MASK 0x1u
mbed_official 82:0b31dbcd4769 369 #define CMP_CR1_EN_SHIFT 0
mbed_official 82:0b31dbcd4769 370 #define CMP_CR1_OPE_MASK 0x2u
mbed_official 82:0b31dbcd4769 371 #define CMP_CR1_OPE_SHIFT 1
mbed_official 82:0b31dbcd4769 372 #define CMP_CR1_COS_MASK 0x4u
mbed_official 82:0b31dbcd4769 373 #define CMP_CR1_COS_SHIFT 2
mbed_official 82:0b31dbcd4769 374 #define CMP_CR1_INV_MASK 0x8u
mbed_official 82:0b31dbcd4769 375 #define CMP_CR1_INV_SHIFT 3
mbed_official 82:0b31dbcd4769 376 #define CMP_CR1_PMODE_MASK 0x10u
mbed_official 82:0b31dbcd4769 377 #define CMP_CR1_PMODE_SHIFT 4
mbed_official 82:0b31dbcd4769 378 #define CMP_CR1_TRIGM_MASK 0x20u
mbed_official 82:0b31dbcd4769 379 #define CMP_CR1_TRIGM_SHIFT 5
mbed_official 82:0b31dbcd4769 380 #define CMP_CR1_WE_MASK 0x40u
mbed_official 82:0b31dbcd4769 381 #define CMP_CR1_WE_SHIFT 6
mbed_official 82:0b31dbcd4769 382 #define CMP_CR1_SE_MASK 0x80u
mbed_official 82:0b31dbcd4769 383 #define CMP_CR1_SE_SHIFT 7
mbed_official 82:0b31dbcd4769 384 /* FPR Bit Fields */
mbed_official 82:0b31dbcd4769 385 #define CMP_FPR_FILT_PER_MASK 0xFFu
mbed_official 82:0b31dbcd4769 386 #define CMP_FPR_FILT_PER_SHIFT 0
mbed_official 82:0b31dbcd4769 387 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
mbed_official 82:0b31dbcd4769 388 /* SCR Bit Fields */
mbed_official 82:0b31dbcd4769 389 #define CMP_SCR_COUT_MASK 0x1u
mbed_official 82:0b31dbcd4769 390 #define CMP_SCR_COUT_SHIFT 0
mbed_official 82:0b31dbcd4769 391 #define CMP_SCR_CFF_MASK 0x2u
mbed_official 82:0b31dbcd4769 392 #define CMP_SCR_CFF_SHIFT 1
mbed_official 82:0b31dbcd4769 393 #define CMP_SCR_CFR_MASK 0x4u
mbed_official 82:0b31dbcd4769 394 #define CMP_SCR_CFR_SHIFT 2
mbed_official 82:0b31dbcd4769 395 #define CMP_SCR_IEF_MASK 0x8u
mbed_official 82:0b31dbcd4769 396 #define CMP_SCR_IEF_SHIFT 3
mbed_official 82:0b31dbcd4769 397 #define CMP_SCR_IER_MASK 0x10u
mbed_official 82:0b31dbcd4769 398 #define CMP_SCR_IER_SHIFT 4
mbed_official 82:0b31dbcd4769 399 #define CMP_SCR_DMAEN_MASK 0x40u
mbed_official 82:0b31dbcd4769 400 #define CMP_SCR_DMAEN_SHIFT 6
mbed_official 82:0b31dbcd4769 401 /* DACCR Bit Fields */
mbed_official 82:0b31dbcd4769 402 #define CMP_DACCR_VOSEL_MASK 0x3Fu
mbed_official 82:0b31dbcd4769 403 #define CMP_DACCR_VOSEL_SHIFT 0
mbed_official 82:0b31dbcd4769 404 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
mbed_official 82:0b31dbcd4769 405 #define CMP_DACCR_VRSEL_MASK 0x40u
mbed_official 82:0b31dbcd4769 406 #define CMP_DACCR_VRSEL_SHIFT 6
mbed_official 82:0b31dbcd4769 407 #define CMP_DACCR_DACEN_MASK 0x80u
mbed_official 82:0b31dbcd4769 408 #define CMP_DACCR_DACEN_SHIFT 7
mbed_official 82:0b31dbcd4769 409 /* MUXCR Bit Fields */
mbed_official 82:0b31dbcd4769 410 #define CMP_MUXCR_MSEL_MASK 0x7u
mbed_official 82:0b31dbcd4769 411 #define CMP_MUXCR_MSEL_SHIFT 0
mbed_official 82:0b31dbcd4769 412 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
mbed_official 82:0b31dbcd4769 413 #define CMP_MUXCR_PSEL_MASK 0x38u
mbed_official 82:0b31dbcd4769 414 #define CMP_MUXCR_PSEL_SHIFT 3
mbed_official 82:0b31dbcd4769 415 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
mbed_official 82:0b31dbcd4769 416 #define CMP_MUXCR_PSTM_MASK 0x80u
mbed_official 82:0b31dbcd4769 417 #define CMP_MUXCR_PSTM_SHIFT 7
mbed_official 82:0b31dbcd4769 418
mbed_official 82:0b31dbcd4769 419 /**
mbed_official 82:0b31dbcd4769 420 * @}
mbed_official 82:0b31dbcd4769 421 */ /* end of group CMP_Register_Masks */
mbed_official 82:0b31dbcd4769 422
mbed_official 82:0b31dbcd4769 423
mbed_official 82:0b31dbcd4769 424 /* CMP - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 425 /** Peripheral CMP0 base address */
mbed_official 82:0b31dbcd4769 426 #define CMP0_BASE (0x40073000u)
mbed_official 82:0b31dbcd4769 427 /** Peripheral CMP0 base pointer */
mbed_official 82:0b31dbcd4769 428 #define CMP0 ((CMP_Type *)CMP0_BASE)
mbed_official 82:0b31dbcd4769 429 /** Array initializer of CMP peripheral base pointers */
mbed_official 82:0b31dbcd4769 430 #define CMP_BASES { CMP0 }
mbed_official 82:0b31dbcd4769 431
mbed_official 82:0b31dbcd4769 432 /**
mbed_official 82:0b31dbcd4769 433 * @}
mbed_official 82:0b31dbcd4769 434 */ /* end of group CMP_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 435
mbed_official 82:0b31dbcd4769 436
mbed_official 82:0b31dbcd4769 437 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 438 -- DAC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 439 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 440
mbed_official 82:0b31dbcd4769 441 /**
mbed_official 82:0b31dbcd4769 442 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 443 * @{
mbed_official 82:0b31dbcd4769 444 */
mbed_official 82:0b31dbcd4769 445
mbed_official 82:0b31dbcd4769 446 /** DAC - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 447 typedef struct {
mbed_official 82:0b31dbcd4769 448 struct { /* offset: 0x0, array step: 0x2 */
mbed_official 82:0b31dbcd4769 449 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
mbed_official 82:0b31dbcd4769 450 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
mbed_official 82:0b31dbcd4769 451 } DAT[2];
mbed_official 82:0b31dbcd4769 452 uint8_t RESERVED_0[28];
mbed_official 82:0b31dbcd4769 453 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
mbed_official 82:0b31dbcd4769 454 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
mbed_official 82:0b31dbcd4769 455 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
mbed_official 82:0b31dbcd4769 456 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
mbed_official 82:0b31dbcd4769 457 } DAC_Type;
mbed_official 82:0b31dbcd4769 458
mbed_official 82:0b31dbcd4769 459 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 460 -- DAC Register Masks
mbed_official 82:0b31dbcd4769 461 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 462
mbed_official 82:0b31dbcd4769 463 /**
mbed_official 82:0b31dbcd4769 464 * @addtogroup DAC_Register_Masks DAC Register Masks
mbed_official 82:0b31dbcd4769 465 * @{
mbed_official 82:0b31dbcd4769 466 */
mbed_official 82:0b31dbcd4769 467
mbed_official 82:0b31dbcd4769 468 /* DATL Bit Fields */
mbed_official 82:0b31dbcd4769 469 #define DAC_DATL_DATA0_MASK 0xFFu
mbed_official 82:0b31dbcd4769 470 #define DAC_DATL_DATA0_SHIFT 0
mbed_official 82:0b31dbcd4769 471 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
mbed_official 82:0b31dbcd4769 472 /* DATH Bit Fields */
mbed_official 82:0b31dbcd4769 473 #define DAC_DATH_DATA1_MASK 0xFu
mbed_official 82:0b31dbcd4769 474 #define DAC_DATH_DATA1_SHIFT 0
mbed_official 82:0b31dbcd4769 475 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
mbed_official 82:0b31dbcd4769 476 /* SR Bit Fields */
mbed_official 82:0b31dbcd4769 477 #define DAC_SR_DACBFRPBF_MASK 0x1u
mbed_official 82:0b31dbcd4769 478 #define DAC_SR_DACBFRPBF_SHIFT 0
mbed_official 82:0b31dbcd4769 479 #define DAC_SR_DACBFRPTF_MASK 0x2u
mbed_official 82:0b31dbcd4769 480 #define DAC_SR_DACBFRPTF_SHIFT 1
mbed_official 82:0b31dbcd4769 481 /* C0 Bit Fields */
mbed_official 82:0b31dbcd4769 482 #define DAC_C0_DACBBIEN_MASK 0x1u
mbed_official 82:0b31dbcd4769 483 #define DAC_C0_DACBBIEN_SHIFT 0
mbed_official 82:0b31dbcd4769 484 #define DAC_C0_DACBTIEN_MASK 0x2u
mbed_official 82:0b31dbcd4769 485 #define DAC_C0_DACBTIEN_SHIFT 1
mbed_official 82:0b31dbcd4769 486 #define DAC_C0_LPEN_MASK 0x8u
mbed_official 82:0b31dbcd4769 487 #define DAC_C0_LPEN_SHIFT 3
mbed_official 82:0b31dbcd4769 488 #define DAC_C0_DACSWTRG_MASK 0x10u
mbed_official 82:0b31dbcd4769 489 #define DAC_C0_DACSWTRG_SHIFT 4
mbed_official 82:0b31dbcd4769 490 #define DAC_C0_DACTRGSEL_MASK 0x20u
mbed_official 82:0b31dbcd4769 491 #define DAC_C0_DACTRGSEL_SHIFT 5
mbed_official 82:0b31dbcd4769 492 #define DAC_C0_DACRFS_MASK 0x40u
mbed_official 82:0b31dbcd4769 493 #define DAC_C0_DACRFS_SHIFT 6
mbed_official 82:0b31dbcd4769 494 #define DAC_C0_DACEN_MASK 0x80u
mbed_official 82:0b31dbcd4769 495 #define DAC_C0_DACEN_SHIFT 7
mbed_official 82:0b31dbcd4769 496 /* C1 Bit Fields */
mbed_official 82:0b31dbcd4769 497 #define DAC_C1_DACBFEN_MASK 0x1u
mbed_official 82:0b31dbcd4769 498 #define DAC_C1_DACBFEN_SHIFT 0
mbed_official 82:0b31dbcd4769 499 #define DAC_C1_DACBFMD_MASK 0x4u
mbed_official 82:0b31dbcd4769 500 #define DAC_C1_DACBFMD_SHIFT 2
mbed_official 82:0b31dbcd4769 501 #define DAC_C1_DMAEN_MASK 0x80u
mbed_official 82:0b31dbcd4769 502 #define DAC_C1_DMAEN_SHIFT 7
mbed_official 82:0b31dbcd4769 503 /* C2 Bit Fields */
mbed_official 82:0b31dbcd4769 504 #define DAC_C2_DACBFUP_MASK 0x1u
mbed_official 82:0b31dbcd4769 505 #define DAC_C2_DACBFUP_SHIFT 0
mbed_official 82:0b31dbcd4769 506 #define DAC_C2_DACBFRP_MASK 0x10u
mbed_official 82:0b31dbcd4769 507 #define DAC_C2_DACBFRP_SHIFT 4
mbed_official 82:0b31dbcd4769 508
mbed_official 82:0b31dbcd4769 509 /**
mbed_official 82:0b31dbcd4769 510 * @}
mbed_official 82:0b31dbcd4769 511 */ /* end of group DAC_Register_Masks */
mbed_official 82:0b31dbcd4769 512
mbed_official 82:0b31dbcd4769 513
mbed_official 82:0b31dbcd4769 514 /* DAC - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 515 /** Peripheral DAC0 base address */
mbed_official 82:0b31dbcd4769 516 #define DAC0_BASE (0x4003F000u)
mbed_official 82:0b31dbcd4769 517 /** Peripheral DAC0 base pointer */
mbed_official 82:0b31dbcd4769 518 #define DAC0 ((DAC_Type *)DAC0_BASE)
mbed_official 82:0b31dbcd4769 519 /** Array initializer of DAC peripheral base pointers */
mbed_official 82:0b31dbcd4769 520 #define DAC_BASES { DAC0 }
mbed_official 82:0b31dbcd4769 521
mbed_official 82:0b31dbcd4769 522 /**
mbed_official 82:0b31dbcd4769 523 * @}
mbed_official 82:0b31dbcd4769 524 */ /* end of group DAC_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 525
mbed_official 82:0b31dbcd4769 526
mbed_official 82:0b31dbcd4769 527 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 528 -- DMA Peripheral Access Layer
mbed_official 82:0b31dbcd4769 529 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 530
mbed_official 82:0b31dbcd4769 531 /**
mbed_official 82:0b31dbcd4769 532 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
mbed_official 82:0b31dbcd4769 533 * @{
mbed_official 82:0b31dbcd4769 534 */
mbed_official 82:0b31dbcd4769 535
mbed_official 82:0b31dbcd4769 536 /** DMA - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 537 typedef struct {
mbed_official 82:0b31dbcd4769 538 uint8_t RESERVED_0[256];
mbed_official 82:0b31dbcd4769 539 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 82:0b31dbcd4769 540 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
mbed_official 82:0b31dbcd4769 541 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
mbed_official 82:0b31dbcd4769 542 union { /* offset: 0x108, array step: 0x10 */
mbed_official 82:0b31dbcd4769 543 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
mbed_official 82:0b31dbcd4769 544 struct { /* offset: 0x108, array step: 0x10 */
mbed_official 82:0b31dbcd4769 545 uint8_t RESERVED_0[3];
mbed_official 82:0b31dbcd4769 546 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
mbed_official 82:0b31dbcd4769 547 } DMA_DSR_ACCESS8BIT;
mbed_official 82:0b31dbcd4769 548 };
mbed_official 82:0b31dbcd4769 549 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
mbed_official 82:0b31dbcd4769 550 } DMA[4];
mbed_official 82:0b31dbcd4769 551 } DMA_Type;
mbed_official 82:0b31dbcd4769 552
mbed_official 82:0b31dbcd4769 553 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 554 -- DMA Register Masks
mbed_official 82:0b31dbcd4769 555 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 556
mbed_official 82:0b31dbcd4769 557 /**
mbed_official 82:0b31dbcd4769 558 * @addtogroup DMA_Register_Masks DMA Register Masks
mbed_official 82:0b31dbcd4769 559 * @{
mbed_official 82:0b31dbcd4769 560 */
mbed_official 82:0b31dbcd4769 561
mbed_official 82:0b31dbcd4769 562 /* SAR Bit Fields */
mbed_official 82:0b31dbcd4769 563 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 564 #define DMA_SAR_SAR_SHIFT 0
mbed_official 82:0b31dbcd4769 565 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
mbed_official 82:0b31dbcd4769 566 /* DAR Bit Fields */
mbed_official 82:0b31dbcd4769 567 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 568 #define DMA_DAR_DAR_SHIFT 0
mbed_official 82:0b31dbcd4769 569 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
mbed_official 82:0b31dbcd4769 570 /* DSR_BCR Bit Fields */
mbed_official 82:0b31dbcd4769 571 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
mbed_official 82:0b31dbcd4769 572 #define DMA_DSR_BCR_BCR_SHIFT 0
mbed_official 82:0b31dbcd4769 573 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
mbed_official 82:0b31dbcd4769 574 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
mbed_official 82:0b31dbcd4769 575 #define DMA_DSR_BCR_DONE_SHIFT 24
mbed_official 82:0b31dbcd4769 576 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
mbed_official 82:0b31dbcd4769 577 #define DMA_DSR_BCR_BSY_SHIFT 25
mbed_official 82:0b31dbcd4769 578 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
mbed_official 82:0b31dbcd4769 579 #define DMA_DSR_BCR_REQ_SHIFT 26
mbed_official 82:0b31dbcd4769 580 #define DMA_DSR_BCR_BED_MASK 0x10000000u
mbed_official 82:0b31dbcd4769 581 #define DMA_DSR_BCR_BED_SHIFT 28
mbed_official 82:0b31dbcd4769 582 #define DMA_DSR_BCR_BES_MASK 0x20000000u
mbed_official 82:0b31dbcd4769 583 #define DMA_DSR_BCR_BES_SHIFT 29
mbed_official 82:0b31dbcd4769 584 #define DMA_DSR_BCR_CE_MASK 0x40000000u
mbed_official 82:0b31dbcd4769 585 #define DMA_DSR_BCR_CE_SHIFT 30
mbed_official 82:0b31dbcd4769 586 /* DCR Bit Fields */
mbed_official 82:0b31dbcd4769 587 #define DMA_DCR_LCH2_MASK 0x3u
mbed_official 82:0b31dbcd4769 588 #define DMA_DCR_LCH2_SHIFT 0
mbed_official 82:0b31dbcd4769 589 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
mbed_official 82:0b31dbcd4769 590 #define DMA_DCR_LCH1_MASK 0xCu
mbed_official 82:0b31dbcd4769 591 #define DMA_DCR_LCH1_SHIFT 2
mbed_official 82:0b31dbcd4769 592 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
mbed_official 82:0b31dbcd4769 593 #define DMA_DCR_LINKCC_MASK 0x30u
mbed_official 82:0b31dbcd4769 594 #define DMA_DCR_LINKCC_SHIFT 4
mbed_official 82:0b31dbcd4769 595 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
mbed_official 82:0b31dbcd4769 596 #define DMA_DCR_D_REQ_MASK 0x80u
mbed_official 82:0b31dbcd4769 597 #define DMA_DCR_D_REQ_SHIFT 7
mbed_official 82:0b31dbcd4769 598 #define DMA_DCR_DMOD_MASK 0xF00u
mbed_official 82:0b31dbcd4769 599 #define DMA_DCR_DMOD_SHIFT 8
mbed_official 82:0b31dbcd4769 600 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
mbed_official 82:0b31dbcd4769 601 #define DMA_DCR_SMOD_MASK 0xF000u
mbed_official 82:0b31dbcd4769 602 #define DMA_DCR_SMOD_SHIFT 12
mbed_official 82:0b31dbcd4769 603 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
mbed_official 82:0b31dbcd4769 604 #define DMA_DCR_START_MASK 0x10000u
mbed_official 82:0b31dbcd4769 605 #define DMA_DCR_START_SHIFT 16
mbed_official 82:0b31dbcd4769 606 #define DMA_DCR_DSIZE_MASK 0x60000u
mbed_official 82:0b31dbcd4769 607 #define DMA_DCR_DSIZE_SHIFT 17
mbed_official 82:0b31dbcd4769 608 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
mbed_official 82:0b31dbcd4769 609 #define DMA_DCR_DINC_MASK 0x80000u
mbed_official 82:0b31dbcd4769 610 #define DMA_DCR_DINC_SHIFT 19
mbed_official 82:0b31dbcd4769 611 #define DMA_DCR_SSIZE_MASK 0x300000u
mbed_official 82:0b31dbcd4769 612 #define DMA_DCR_SSIZE_SHIFT 20
mbed_official 82:0b31dbcd4769 613 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
mbed_official 82:0b31dbcd4769 614 #define DMA_DCR_SINC_MASK 0x400000u
mbed_official 82:0b31dbcd4769 615 #define DMA_DCR_SINC_SHIFT 22
mbed_official 82:0b31dbcd4769 616 #define DMA_DCR_EADREQ_MASK 0x800000u
mbed_official 82:0b31dbcd4769 617 #define DMA_DCR_EADREQ_SHIFT 23
mbed_official 82:0b31dbcd4769 618 #define DMA_DCR_AA_MASK 0x10000000u
mbed_official 82:0b31dbcd4769 619 #define DMA_DCR_AA_SHIFT 28
mbed_official 82:0b31dbcd4769 620 #define DMA_DCR_CS_MASK 0x20000000u
mbed_official 82:0b31dbcd4769 621 #define DMA_DCR_CS_SHIFT 29
mbed_official 82:0b31dbcd4769 622 #define DMA_DCR_ERQ_MASK 0x40000000u
mbed_official 82:0b31dbcd4769 623 #define DMA_DCR_ERQ_SHIFT 30
mbed_official 82:0b31dbcd4769 624 #define DMA_DCR_EINT_MASK 0x80000000u
mbed_official 82:0b31dbcd4769 625 #define DMA_DCR_EINT_SHIFT 31
mbed_official 82:0b31dbcd4769 626
mbed_official 82:0b31dbcd4769 627 /**
mbed_official 82:0b31dbcd4769 628 * @}
mbed_official 82:0b31dbcd4769 629 */ /* end of group DMA_Register_Masks */
mbed_official 82:0b31dbcd4769 630
mbed_official 82:0b31dbcd4769 631
mbed_official 82:0b31dbcd4769 632 /* DMA - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 633 /** Peripheral DMA base address */
mbed_official 82:0b31dbcd4769 634 #define DMA_BASE (0x40008000u)
mbed_official 82:0b31dbcd4769 635 /** Peripheral DMA base pointer */
mbed_official 82:0b31dbcd4769 636 #define DMA0 ((DMA_Type *)DMA_BASE)
mbed_official 82:0b31dbcd4769 637 /** Array initializer of DMA peripheral base pointers */
mbed_official 82:0b31dbcd4769 638 #define DMA_BASES { DMA0 }
mbed_official 82:0b31dbcd4769 639
mbed_official 82:0b31dbcd4769 640 /**
mbed_official 82:0b31dbcd4769 641 * @}
mbed_official 82:0b31dbcd4769 642 */ /* end of group DMA_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 643
mbed_official 82:0b31dbcd4769 644
mbed_official 82:0b31dbcd4769 645 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 646 -- DMAMUX Peripheral Access Layer
mbed_official 82:0b31dbcd4769 647 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 648
mbed_official 82:0b31dbcd4769 649 /**
mbed_official 82:0b31dbcd4769 650 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
mbed_official 82:0b31dbcd4769 651 * @{
mbed_official 82:0b31dbcd4769 652 */
mbed_official 82:0b31dbcd4769 653
mbed_official 82:0b31dbcd4769 654 /** DMAMUX - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 655 typedef struct {
mbed_official 82:0b31dbcd4769 656 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
mbed_official 82:0b31dbcd4769 657 } DMAMUX_Type;
mbed_official 82:0b31dbcd4769 658
mbed_official 82:0b31dbcd4769 659 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 660 -- DMAMUX Register Masks
mbed_official 82:0b31dbcd4769 661 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 662
mbed_official 82:0b31dbcd4769 663 /**
mbed_official 82:0b31dbcd4769 664 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
mbed_official 82:0b31dbcd4769 665 * @{
mbed_official 82:0b31dbcd4769 666 */
mbed_official 82:0b31dbcd4769 667
mbed_official 82:0b31dbcd4769 668 /* CHCFG Bit Fields */
mbed_official 82:0b31dbcd4769 669 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
mbed_official 82:0b31dbcd4769 670 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
mbed_official 82:0b31dbcd4769 671 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
mbed_official 82:0b31dbcd4769 672 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
mbed_official 82:0b31dbcd4769 673 #define DMAMUX_CHCFG_TRIG_SHIFT 6
mbed_official 82:0b31dbcd4769 674 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
mbed_official 82:0b31dbcd4769 675 #define DMAMUX_CHCFG_ENBL_SHIFT 7
mbed_official 82:0b31dbcd4769 676
mbed_official 82:0b31dbcd4769 677 /**
mbed_official 82:0b31dbcd4769 678 * @}
mbed_official 82:0b31dbcd4769 679 */ /* end of group DMAMUX_Register_Masks */
mbed_official 82:0b31dbcd4769 680
mbed_official 82:0b31dbcd4769 681
mbed_official 82:0b31dbcd4769 682 /* DMAMUX - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 683 /** Peripheral DMAMUX0 base address */
mbed_official 82:0b31dbcd4769 684 #define DMAMUX0_BASE (0x40021000u)
mbed_official 82:0b31dbcd4769 685 /** Peripheral DMAMUX0 base pointer */
mbed_official 82:0b31dbcd4769 686 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
mbed_official 82:0b31dbcd4769 687 /** Array initializer of DMAMUX peripheral base pointers */
mbed_official 82:0b31dbcd4769 688 #define DMAMUX_BASES { DMAMUX0 }
mbed_official 82:0b31dbcd4769 689
mbed_official 82:0b31dbcd4769 690 /**
mbed_official 82:0b31dbcd4769 691 * @}
mbed_official 82:0b31dbcd4769 692 */ /* end of group DMAMUX_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 693
mbed_official 82:0b31dbcd4769 694
mbed_official 82:0b31dbcd4769 695 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 696 -- FGPIO Peripheral Access Layer
mbed_official 82:0b31dbcd4769 697 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 698
mbed_official 82:0b31dbcd4769 699 /**
mbed_official 82:0b31dbcd4769 700 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
mbed_official 82:0b31dbcd4769 701 * @{
mbed_official 82:0b31dbcd4769 702 */
mbed_official 82:0b31dbcd4769 703
mbed_official 82:0b31dbcd4769 704 /** FGPIO - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 705 typedef struct {
mbed_official 82:0b31dbcd4769 706 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 707 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 708 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 82:0b31dbcd4769 709 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 82:0b31dbcd4769 710 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 82:0b31dbcd4769 711 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 82:0b31dbcd4769 712 } FGPIO_Type;
mbed_official 82:0b31dbcd4769 713
mbed_official 82:0b31dbcd4769 714 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 715 -- FGPIO Register Masks
mbed_official 82:0b31dbcd4769 716 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 717
mbed_official 82:0b31dbcd4769 718 /**
mbed_official 82:0b31dbcd4769 719 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
mbed_official 82:0b31dbcd4769 720 * @{
mbed_official 82:0b31dbcd4769 721 */
mbed_official 82:0b31dbcd4769 722
mbed_official 82:0b31dbcd4769 723 /* PDOR Bit Fields */
mbed_official 82:0b31dbcd4769 724 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 725 #define FGPIO_PDOR_PDO_SHIFT 0
mbed_official 82:0b31dbcd4769 726 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
mbed_official 82:0b31dbcd4769 727 /* PSOR Bit Fields */
mbed_official 82:0b31dbcd4769 728 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 729 #define FGPIO_PSOR_PTSO_SHIFT 0
mbed_official 82:0b31dbcd4769 730 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
mbed_official 82:0b31dbcd4769 731 /* PCOR Bit Fields */
mbed_official 82:0b31dbcd4769 732 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 733 #define FGPIO_PCOR_PTCO_SHIFT 0
mbed_official 82:0b31dbcd4769 734 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
mbed_official 82:0b31dbcd4769 735 /* PTOR Bit Fields */
mbed_official 82:0b31dbcd4769 736 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 737 #define FGPIO_PTOR_PTTO_SHIFT 0
mbed_official 82:0b31dbcd4769 738 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
mbed_official 82:0b31dbcd4769 739 /* PDIR Bit Fields */
mbed_official 82:0b31dbcd4769 740 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 741 #define FGPIO_PDIR_PDI_SHIFT 0
mbed_official 82:0b31dbcd4769 742 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
mbed_official 82:0b31dbcd4769 743 /* PDDR Bit Fields */
mbed_official 82:0b31dbcd4769 744 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 745 #define FGPIO_PDDR_PDD_SHIFT 0
mbed_official 82:0b31dbcd4769 746 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
mbed_official 82:0b31dbcd4769 747
mbed_official 82:0b31dbcd4769 748 /**
mbed_official 82:0b31dbcd4769 749 * @}
mbed_official 82:0b31dbcd4769 750 */ /* end of group FGPIO_Register_Masks */
mbed_official 82:0b31dbcd4769 751
mbed_official 82:0b31dbcd4769 752
mbed_official 82:0b31dbcd4769 753 /* FGPIO - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 754 /** Peripheral FPTA base address */
mbed_official 82:0b31dbcd4769 755 #define FPTA_BASE (0xF80FF000u)
mbed_official 82:0b31dbcd4769 756 /** Peripheral FPTA base pointer */
mbed_official 82:0b31dbcd4769 757 #define FPTA ((FGPIO_Type *)FPTA_BASE)
mbed_official 82:0b31dbcd4769 758 /** Peripheral FPTB base address */
mbed_official 82:0b31dbcd4769 759 #define FPTB_BASE (0xF80FF040u)
mbed_official 82:0b31dbcd4769 760 /** Peripheral FPTB base pointer */
mbed_official 82:0b31dbcd4769 761 #define FPTB ((FGPIO_Type *)FPTB_BASE)
mbed_official 82:0b31dbcd4769 762 /** Array initializer of FGPIO peripheral base pointers */
mbed_official 82:0b31dbcd4769 763 #define FGPIO_BASES { FPTA, FPTB }
mbed_official 82:0b31dbcd4769 764
mbed_official 82:0b31dbcd4769 765 /**
mbed_official 82:0b31dbcd4769 766 * @}
mbed_official 82:0b31dbcd4769 767 */ /* end of group FGPIO_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 768
mbed_official 82:0b31dbcd4769 769
mbed_official 82:0b31dbcd4769 770 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 771 -- FTFA Peripheral Access Layer
mbed_official 82:0b31dbcd4769 772 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 773
mbed_official 82:0b31dbcd4769 774 /**
mbed_official 82:0b31dbcd4769 775 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
mbed_official 82:0b31dbcd4769 776 * @{
mbed_official 82:0b31dbcd4769 777 */
mbed_official 82:0b31dbcd4769 778
mbed_official 82:0b31dbcd4769 779 /** FTFA - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 780 typedef struct {
mbed_official 82:0b31dbcd4769 781 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 782 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
mbed_official 82:0b31dbcd4769 783 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
mbed_official 82:0b31dbcd4769 784 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
mbed_official 82:0b31dbcd4769 785 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
mbed_official 82:0b31dbcd4769 786 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
mbed_official 82:0b31dbcd4769 787 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
mbed_official 82:0b31dbcd4769 788 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
mbed_official 82:0b31dbcd4769 789 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
mbed_official 82:0b31dbcd4769 790 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
mbed_official 82:0b31dbcd4769 791 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
mbed_official 82:0b31dbcd4769 792 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
mbed_official 82:0b31dbcd4769 793 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
mbed_official 82:0b31dbcd4769 794 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
mbed_official 82:0b31dbcd4769 795 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
mbed_official 82:0b31dbcd4769 796 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
mbed_official 82:0b31dbcd4769 797 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
mbed_official 82:0b31dbcd4769 798 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
mbed_official 82:0b31dbcd4769 799 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
mbed_official 82:0b31dbcd4769 800 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
mbed_official 82:0b31dbcd4769 801 } FTFA_Type;
mbed_official 82:0b31dbcd4769 802
mbed_official 82:0b31dbcd4769 803 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 804 -- FTFA Register Masks
mbed_official 82:0b31dbcd4769 805 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 806
mbed_official 82:0b31dbcd4769 807 /**
mbed_official 82:0b31dbcd4769 808 * @addtogroup FTFA_Register_Masks FTFA Register Masks
mbed_official 82:0b31dbcd4769 809 * @{
mbed_official 82:0b31dbcd4769 810 */
mbed_official 82:0b31dbcd4769 811
mbed_official 82:0b31dbcd4769 812 /* FSTAT Bit Fields */
mbed_official 82:0b31dbcd4769 813 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
mbed_official 82:0b31dbcd4769 814 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
mbed_official 82:0b31dbcd4769 815 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
mbed_official 82:0b31dbcd4769 816 #define FTFA_FSTAT_FPVIOL_SHIFT 4
mbed_official 82:0b31dbcd4769 817 #define FTFA_FSTAT_ACCERR_MASK 0x20u
mbed_official 82:0b31dbcd4769 818 #define FTFA_FSTAT_ACCERR_SHIFT 5
mbed_official 82:0b31dbcd4769 819 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
mbed_official 82:0b31dbcd4769 820 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
mbed_official 82:0b31dbcd4769 821 #define FTFA_FSTAT_CCIF_MASK 0x80u
mbed_official 82:0b31dbcd4769 822 #define FTFA_FSTAT_CCIF_SHIFT 7
mbed_official 82:0b31dbcd4769 823 /* FCNFG Bit Fields */
mbed_official 82:0b31dbcd4769 824 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
mbed_official 82:0b31dbcd4769 825 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
mbed_official 82:0b31dbcd4769 826 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
mbed_official 82:0b31dbcd4769 827 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
mbed_official 82:0b31dbcd4769 828 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
mbed_official 82:0b31dbcd4769 829 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
mbed_official 82:0b31dbcd4769 830 #define FTFA_FCNFG_CCIE_MASK 0x80u
mbed_official 82:0b31dbcd4769 831 #define FTFA_FCNFG_CCIE_SHIFT 7
mbed_official 82:0b31dbcd4769 832 /* FSEC Bit Fields */
mbed_official 82:0b31dbcd4769 833 #define FTFA_FSEC_SEC_MASK 0x3u
mbed_official 82:0b31dbcd4769 834 #define FTFA_FSEC_SEC_SHIFT 0
mbed_official 82:0b31dbcd4769 835 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
mbed_official 82:0b31dbcd4769 836 #define FTFA_FSEC_FSLACC_MASK 0xCu
mbed_official 82:0b31dbcd4769 837 #define FTFA_FSEC_FSLACC_SHIFT 2
mbed_official 82:0b31dbcd4769 838 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
mbed_official 82:0b31dbcd4769 839 #define FTFA_FSEC_MEEN_MASK 0x30u
mbed_official 82:0b31dbcd4769 840 #define FTFA_FSEC_MEEN_SHIFT 4
mbed_official 82:0b31dbcd4769 841 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
mbed_official 82:0b31dbcd4769 842 #define FTFA_FSEC_KEYEN_MASK 0xC0u
mbed_official 82:0b31dbcd4769 843 #define FTFA_FSEC_KEYEN_SHIFT 6
mbed_official 82:0b31dbcd4769 844 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
mbed_official 82:0b31dbcd4769 845 /* FOPT Bit Fields */
mbed_official 82:0b31dbcd4769 846 #define FTFA_FOPT_OPT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 847 #define FTFA_FOPT_OPT_SHIFT 0
mbed_official 82:0b31dbcd4769 848 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
mbed_official 82:0b31dbcd4769 849 /* FCCOB3 Bit Fields */
mbed_official 82:0b31dbcd4769 850 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 851 #define FTFA_FCCOB3_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 852 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 853 /* FCCOB2 Bit Fields */
mbed_official 82:0b31dbcd4769 854 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 855 #define FTFA_FCCOB2_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 856 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 857 /* FCCOB1 Bit Fields */
mbed_official 82:0b31dbcd4769 858 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 859 #define FTFA_FCCOB1_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 860 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 861 /* FCCOB0 Bit Fields */
mbed_official 82:0b31dbcd4769 862 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 863 #define FTFA_FCCOB0_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 864 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 865 /* FCCOB7 Bit Fields */
mbed_official 82:0b31dbcd4769 866 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 867 #define FTFA_FCCOB7_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 868 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 869 /* FCCOB6 Bit Fields */
mbed_official 82:0b31dbcd4769 870 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 871 #define FTFA_FCCOB6_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 872 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 873 /* FCCOB5 Bit Fields */
mbed_official 82:0b31dbcd4769 874 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 875 #define FTFA_FCCOB5_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 876 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 877 /* FCCOB4 Bit Fields */
mbed_official 82:0b31dbcd4769 878 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 879 #define FTFA_FCCOB4_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 880 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 881 /* FCCOBB Bit Fields */
mbed_official 82:0b31dbcd4769 882 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 883 #define FTFA_FCCOBB_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 884 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 885 /* FCCOBA Bit Fields */
mbed_official 82:0b31dbcd4769 886 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 887 #define FTFA_FCCOBA_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 888 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 889 /* FCCOB9 Bit Fields */
mbed_official 82:0b31dbcd4769 890 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 891 #define FTFA_FCCOB9_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 892 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 893 /* FCCOB8 Bit Fields */
mbed_official 82:0b31dbcd4769 894 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
mbed_official 82:0b31dbcd4769 895 #define FTFA_FCCOB8_CCOBn_SHIFT 0
mbed_official 82:0b31dbcd4769 896 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
mbed_official 82:0b31dbcd4769 897 /* FPROT3 Bit Fields */
mbed_official 82:0b31dbcd4769 898 #define FTFA_FPROT3_PROT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 899 #define FTFA_FPROT3_PROT_SHIFT 0
mbed_official 82:0b31dbcd4769 900 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
mbed_official 82:0b31dbcd4769 901 /* FPROT2 Bit Fields */
mbed_official 82:0b31dbcd4769 902 #define FTFA_FPROT2_PROT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 903 #define FTFA_FPROT2_PROT_SHIFT 0
mbed_official 82:0b31dbcd4769 904 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
mbed_official 82:0b31dbcd4769 905 /* FPROT1 Bit Fields */
mbed_official 82:0b31dbcd4769 906 #define FTFA_FPROT1_PROT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 907 #define FTFA_FPROT1_PROT_SHIFT 0
mbed_official 82:0b31dbcd4769 908 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
mbed_official 82:0b31dbcd4769 909 /* FPROT0 Bit Fields */
mbed_official 82:0b31dbcd4769 910 #define FTFA_FPROT0_PROT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 911 #define FTFA_FPROT0_PROT_SHIFT 0
mbed_official 82:0b31dbcd4769 912 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
mbed_official 82:0b31dbcd4769 913
mbed_official 82:0b31dbcd4769 914 /**
mbed_official 82:0b31dbcd4769 915 * @}
mbed_official 82:0b31dbcd4769 916 */ /* end of group FTFA_Register_Masks */
mbed_official 82:0b31dbcd4769 917
mbed_official 82:0b31dbcd4769 918
mbed_official 82:0b31dbcd4769 919 /* FTFA - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 920 /** Peripheral FTFA base address */
mbed_official 82:0b31dbcd4769 921 #define FTFA_BASE (0x40020000u)
mbed_official 82:0b31dbcd4769 922 /** Peripheral FTFA base pointer */
mbed_official 82:0b31dbcd4769 923 #define FTFA ((FTFA_Type *)FTFA_BASE)
mbed_official 82:0b31dbcd4769 924 /** Array initializer of FTFA peripheral base pointers */
mbed_official 82:0b31dbcd4769 925 #define FTFA_BASES { FTFA }
mbed_official 82:0b31dbcd4769 926
mbed_official 82:0b31dbcd4769 927 /**
mbed_official 82:0b31dbcd4769 928 * @}
mbed_official 82:0b31dbcd4769 929 */ /* end of group FTFA_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 930
mbed_official 82:0b31dbcd4769 931
mbed_official 82:0b31dbcd4769 932 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 933 -- GPIO Peripheral Access Layer
mbed_official 82:0b31dbcd4769 934 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 935
mbed_official 82:0b31dbcd4769 936 /**
mbed_official 82:0b31dbcd4769 937 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
mbed_official 82:0b31dbcd4769 938 * @{
mbed_official 82:0b31dbcd4769 939 */
mbed_official 82:0b31dbcd4769 940
mbed_official 82:0b31dbcd4769 941 /** GPIO - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 942 typedef struct {
mbed_official 82:0b31dbcd4769 943 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 944 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 945 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 82:0b31dbcd4769 946 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 82:0b31dbcd4769 947 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 82:0b31dbcd4769 948 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 82:0b31dbcd4769 949 } GPIO_Type;
mbed_official 82:0b31dbcd4769 950
mbed_official 82:0b31dbcd4769 951 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 952 -- GPIO Register Masks
mbed_official 82:0b31dbcd4769 953 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 954
mbed_official 82:0b31dbcd4769 955 /**
mbed_official 82:0b31dbcd4769 956 * @addtogroup GPIO_Register_Masks GPIO Register Masks
mbed_official 82:0b31dbcd4769 957 * @{
mbed_official 82:0b31dbcd4769 958 */
mbed_official 82:0b31dbcd4769 959
mbed_official 82:0b31dbcd4769 960 /* PDOR Bit Fields */
mbed_official 82:0b31dbcd4769 961 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 962 #define GPIO_PDOR_PDO_SHIFT 0
mbed_official 82:0b31dbcd4769 963 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
mbed_official 82:0b31dbcd4769 964 /* PSOR Bit Fields */
mbed_official 82:0b31dbcd4769 965 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 966 #define GPIO_PSOR_PTSO_SHIFT 0
mbed_official 82:0b31dbcd4769 967 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
mbed_official 82:0b31dbcd4769 968 /* PCOR Bit Fields */
mbed_official 82:0b31dbcd4769 969 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 970 #define GPIO_PCOR_PTCO_SHIFT 0
mbed_official 82:0b31dbcd4769 971 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
mbed_official 82:0b31dbcd4769 972 /* PTOR Bit Fields */
mbed_official 82:0b31dbcd4769 973 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 974 #define GPIO_PTOR_PTTO_SHIFT 0
mbed_official 82:0b31dbcd4769 975 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
mbed_official 82:0b31dbcd4769 976 /* PDIR Bit Fields */
mbed_official 82:0b31dbcd4769 977 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 978 #define GPIO_PDIR_PDI_SHIFT 0
mbed_official 82:0b31dbcd4769 979 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
mbed_official 82:0b31dbcd4769 980 /* PDDR Bit Fields */
mbed_official 82:0b31dbcd4769 981 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 982 #define GPIO_PDDR_PDD_SHIFT 0
mbed_official 82:0b31dbcd4769 983 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
mbed_official 82:0b31dbcd4769 984
mbed_official 82:0b31dbcd4769 985 /**
mbed_official 82:0b31dbcd4769 986 * @}
mbed_official 82:0b31dbcd4769 987 */ /* end of group GPIO_Register_Masks */
mbed_official 82:0b31dbcd4769 988
mbed_official 82:0b31dbcd4769 989
mbed_official 82:0b31dbcd4769 990 /* GPIO - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 991 /** Peripheral PTA base address */
mbed_official 82:0b31dbcd4769 992 #define PTA_BASE (0x400FF000u)
mbed_official 82:0b31dbcd4769 993 /** Peripheral PTA base pointer */
mbed_official 82:0b31dbcd4769 994 #define PTA ((GPIO_Type *)PTA_BASE)
mbed_official 82:0b31dbcd4769 995 /** Peripheral PTB base address */
mbed_official 82:0b31dbcd4769 996 #define PTB_BASE (0x400FF040u)
mbed_official 82:0b31dbcd4769 997 /** Peripheral PTB base pointer */
mbed_official 82:0b31dbcd4769 998 #define PTB ((GPIO_Type *)PTB_BASE)
mbed_official 82:0b31dbcd4769 999 /** Array initializer of GPIO peripheral base pointers */
mbed_official 82:0b31dbcd4769 1000 #define GPIO_BASES { PTA, PTB }
mbed_official 82:0b31dbcd4769 1001
mbed_official 82:0b31dbcd4769 1002 /**
mbed_official 82:0b31dbcd4769 1003 * @}
mbed_official 82:0b31dbcd4769 1004 */ /* end of group GPIO_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 1005
mbed_official 82:0b31dbcd4769 1006
mbed_official 82:0b31dbcd4769 1007 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1008 -- I2C Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1009 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1010
mbed_official 82:0b31dbcd4769 1011 /**
mbed_official 82:0b31dbcd4769 1012 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1013 * @{
mbed_official 82:0b31dbcd4769 1014 */
mbed_official 82:0b31dbcd4769 1015
mbed_official 82:0b31dbcd4769 1016 /** I2C - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 1017 typedef struct {
mbed_official 82:0b31dbcd4769 1018 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
mbed_official 82:0b31dbcd4769 1019 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
mbed_official 82:0b31dbcd4769 1020 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
mbed_official 82:0b31dbcd4769 1021 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
mbed_official 82:0b31dbcd4769 1022 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 1023 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
mbed_official 82:0b31dbcd4769 1024 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
mbed_official 82:0b31dbcd4769 1025 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
mbed_official 82:0b31dbcd4769 1026 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
mbed_official 82:0b31dbcd4769 1027 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
mbed_official 82:0b31dbcd4769 1028 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
mbed_official 82:0b31dbcd4769 1029 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
mbed_official 82:0b31dbcd4769 1030 } I2C_Type;
mbed_official 82:0b31dbcd4769 1031
mbed_official 82:0b31dbcd4769 1032 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1033 -- I2C Register Masks
mbed_official 82:0b31dbcd4769 1034 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1035
mbed_official 82:0b31dbcd4769 1036 /**
mbed_official 82:0b31dbcd4769 1037 * @addtogroup I2C_Register_Masks I2C Register Masks
mbed_official 82:0b31dbcd4769 1038 * @{
mbed_official 82:0b31dbcd4769 1039 */
mbed_official 82:0b31dbcd4769 1040
mbed_official 82:0b31dbcd4769 1041 /* A1 Bit Fields */
mbed_official 82:0b31dbcd4769 1042 #define I2C_A1_AD_MASK 0xFEu
mbed_official 82:0b31dbcd4769 1043 #define I2C_A1_AD_SHIFT 1
mbed_official 82:0b31dbcd4769 1044 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
mbed_official 82:0b31dbcd4769 1045 /* F Bit Fields */
mbed_official 82:0b31dbcd4769 1046 #define I2C_F_ICR_MASK 0x3Fu
mbed_official 82:0b31dbcd4769 1047 #define I2C_F_ICR_SHIFT 0
mbed_official 82:0b31dbcd4769 1048 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
mbed_official 82:0b31dbcd4769 1049 #define I2C_F_MULT_MASK 0xC0u
mbed_official 82:0b31dbcd4769 1050 #define I2C_F_MULT_SHIFT 6
mbed_official 82:0b31dbcd4769 1051 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
mbed_official 82:0b31dbcd4769 1052 /* C1 Bit Fields */
mbed_official 82:0b31dbcd4769 1053 #define I2C_C1_DMAEN_MASK 0x1u
mbed_official 82:0b31dbcd4769 1054 #define I2C_C1_DMAEN_SHIFT 0
mbed_official 82:0b31dbcd4769 1055 #define I2C_C1_WUEN_MASK 0x2u
mbed_official 82:0b31dbcd4769 1056 #define I2C_C1_WUEN_SHIFT 1
mbed_official 82:0b31dbcd4769 1057 #define I2C_C1_RSTA_MASK 0x4u
mbed_official 82:0b31dbcd4769 1058 #define I2C_C1_RSTA_SHIFT 2
mbed_official 82:0b31dbcd4769 1059 #define I2C_C1_TXAK_MASK 0x8u
mbed_official 82:0b31dbcd4769 1060 #define I2C_C1_TXAK_SHIFT 3
mbed_official 82:0b31dbcd4769 1061 #define I2C_C1_TX_MASK 0x10u
mbed_official 82:0b31dbcd4769 1062 #define I2C_C1_TX_SHIFT 4
mbed_official 82:0b31dbcd4769 1063 #define I2C_C1_MST_MASK 0x20u
mbed_official 82:0b31dbcd4769 1064 #define I2C_C1_MST_SHIFT 5
mbed_official 82:0b31dbcd4769 1065 #define I2C_C1_IICIE_MASK 0x40u
mbed_official 82:0b31dbcd4769 1066 #define I2C_C1_IICIE_SHIFT 6
mbed_official 82:0b31dbcd4769 1067 #define I2C_C1_IICEN_MASK 0x80u
mbed_official 82:0b31dbcd4769 1068 #define I2C_C1_IICEN_SHIFT 7
mbed_official 82:0b31dbcd4769 1069 /* S Bit Fields */
mbed_official 82:0b31dbcd4769 1070 #define I2C_S_RXAK_MASK 0x1u
mbed_official 82:0b31dbcd4769 1071 #define I2C_S_RXAK_SHIFT 0
mbed_official 82:0b31dbcd4769 1072 #define I2C_S_IICIF_MASK 0x2u
mbed_official 82:0b31dbcd4769 1073 #define I2C_S_IICIF_SHIFT 1
mbed_official 82:0b31dbcd4769 1074 #define I2C_S_SRW_MASK 0x4u
mbed_official 82:0b31dbcd4769 1075 #define I2C_S_SRW_SHIFT 2
mbed_official 82:0b31dbcd4769 1076 #define I2C_S_RAM_MASK 0x8u
mbed_official 82:0b31dbcd4769 1077 #define I2C_S_RAM_SHIFT 3
mbed_official 82:0b31dbcd4769 1078 #define I2C_S_ARBL_MASK 0x10u
mbed_official 82:0b31dbcd4769 1079 #define I2C_S_ARBL_SHIFT 4
mbed_official 82:0b31dbcd4769 1080 #define I2C_S_BUSY_MASK 0x20u
mbed_official 82:0b31dbcd4769 1081 #define I2C_S_BUSY_SHIFT 5
mbed_official 82:0b31dbcd4769 1082 #define I2C_S_IAAS_MASK 0x40u
mbed_official 82:0b31dbcd4769 1083 #define I2C_S_IAAS_SHIFT 6
mbed_official 82:0b31dbcd4769 1084 #define I2C_S_TCF_MASK 0x80u
mbed_official 82:0b31dbcd4769 1085 #define I2C_S_TCF_SHIFT 7
mbed_official 82:0b31dbcd4769 1086 /* D Bit Fields */
mbed_official 82:0b31dbcd4769 1087 #define I2C_D_DATA_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1088 #define I2C_D_DATA_SHIFT 0
mbed_official 82:0b31dbcd4769 1089 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
mbed_official 82:0b31dbcd4769 1090 /* C2 Bit Fields */
mbed_official 82:0b31dbcd4769 1091 #define I2C_C2_AD_MASK 0x7u
mbed_official 82:0b31dbcd4769 1092 #define I2C_C2_AD_SHIFT 0
mbed_official 82:0b31dbcd4769 1093 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
mbed_official 82:0b31dbcd4769 1094 #define I2C_C2_RMEN_MASK 0x8u
mbed_official 82:0b31dbcd4769 1095 #define I2C_C2_RMEN_SHIFT 3
mbed_official 82:0b31dbcd4769 1096 #define I2C_C2_SBRC_MASK 0x10u
mbed_official 82:0b31dbcd4769 1097 #define I2C_C2_SBRC_SHIFT 4
mbed_official 82:0b31dbcd4769 1098 #define I2C_C2_HDRS_MASK 0x20u
mbed_official 82:0b31dbcd4769 1099 #define I2C_C2_HDRS_SHIFT 5
mbed_official 82:0b31dbcd4769 1100 #define I2C_C2_ADEXT_MASK 0x40u
mbed_official 82:0b31dbcd4769 1101 #define I2C_C2_ADEXT_SHIFT 6
mbed_official 82:0b31dbcd4769 1102 #define I2C_C2_GCAEN_MASK 0x80u
mbed_official 82:0b31dbcd4769 1103 #define I2C_C2_GCAEN_SHIFT 7
mbed_official 82:0b31dbcd4769 1104 /* FLT Bit Fields */
mbed_official 82:0b31dbcd4769 1105 #define I2C_FLT_FLT_MASK 0x1Fu
mbed_official 82:0b31dbcd4769 1106 #define I2C_FLT_FLT_SHIFT 0
mbed_official 82:0b31dbcd4769 1107 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
mbed_official 82:0b31dbcd4769 1108 #define I2C_FLT_STOPIE_MASK 0x20u
mbed_official 82:0b31dbcd4769 1109 #define I2C_FLT_STOPIE_SHIFT 5
mbed_official 82:0b31dbcd4769 1110 #define I2C_FLT_STOPF_MASK 0x40u
mbed_official 82:0b31dbcd4769 1111 #define I2C_FLT_STOPF_SHIFT 6
mbed_official 82:0b31dbcd4769 1112 #define I2C_FLT_SHEN_MASK 0x80u
mbed_official 82:0b31dbcd4769 1113 #define I2C_FLT_SHEN_SHIFT 7
mbed_official 82:0b31dbcd4769 1114 /* RA Bit Fields */
mbed_official 82:0b31dbcd4769 1115 #define I2C_RA_RAD_MASK 0xFEu
mbed_official 82:0b31dbcd4769 1116 #define I2C_RA_RAD_SHIFT 1
mbed_official 82:0b31dbcd4769 1117 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
mbed_official 82:0b31dbcd4769 1118 /* SMB Bit Fields */
mbed_official 82:0b31dbcd4769 1119 #define I2C_SMB_SHTF2IE_MASK 0x1u
mbed_official 82:0b31dbcd4769 1120 #define I2C_SMB_SHTF2IE_SHIFT 0
mbed_official 82:0b31dbcd4769 1121 #define I2C_SMB_SHTF2_MASK 0x2u
mbed_official 82:0b31dbcd4769 1122 #define I2C_SMB_SHTF2_SHIFT 1
mbed_official 82:0b31dbcd4769 1123 #define I2C_SMB_SHTF1_MASK 0x4u
mbed_official 82:0b31dbcd4769 1124 #define I2C_SMB_SHTF1_SHIFT 2
mbed_official 82:0b31dbcd4769 1125 #define I2C_SMB_SLTF_MASK 0x8u
mbed_official 82:0b31dbcd4769 1126 #define I2C_SMB_SLTF_SHIFT 3
mbed_official 82:0b31dbcd4769 1127 #define I2C_SMB_TCKSEL_MASK 0x10u
mbed_official 82:0b31dbcd4769 1128 #define I2C_SMB_TCKSEL_SHIFT 4
mbed_official 82:0b31dbcd4769 1129 #define I2C_SMB_SIICAEN_MASK 0x20u
mbed_official 82:0b31dbcd4769 1130 #define I2C_SMB_SIICAEN_SHIFT 5
mbed_official 82:0b31dbcd4769 1131 #define I2C_SMB_ALERTEN_MASK 0x40u
mbed_official 82:0b31dbcd4769 1132 #define I2C_SMB_ALERTEN_SHIFT 6
mbed_official 82:0b31dbcd4769 1133 #define I2C_SMB_FACK_MASK 0x80u
mbed_official 82:0b31dbcd4769 1134 #define I2C_SMB_FACK_SHIFT 7
mbed_official 82:0b31dbcd4769 1135 /* A2 Bit Fields */
mbed_official 82:0b31dbcd4769 1136 #define I2C_A2_SAD_MASK 0xFEu
mbed_official 82:0b31dbcd4769 1137 #define I2C_A2_SAD_SHIFT 1
mbed_official 82:0b31dbcd4769 1138 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
mbed_official 82:0b31dbcd4769 1139 /* SLTH Bit Fields */
mbed_official 82:0b31dbcd4769 1140 #define I2C_SLTH_SSLT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1141 #define I2C_SLTH_SSLT_SHIFT 0
mbed_official 82:0b31dbcd4769 1142 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
mbed_official 82:0b31dbcd4769 1143 /* SLTL Bit Fields */
mbed_official 82:0b31dbcd4769 1144 #define I2C_SLTL_SSLT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1145 #define I2C_SLTL_SSLT_SHIFT 0
mbed_official 82:0b31dbcd4769 1146 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
mbed_official 82:0b31dbcd4769 1147
mbed_official 82:0b31dbcd4769 1148 /**
mbed_official 82:0b31dbcd4769 1149 * @}
mbed_official 82:0b31dbcd4769 1150 */ /* end of group I2C_Register_Masks */
mbed_official 82:0b31dbcd4769 1151
mbed_official 82:0b31dbcd4769 1152
mbed_official 82:0b31dbcd4769 1153 /* I2C - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 1154 /** Peripheral I2C0 base address */
mbed_official 82:0b31dbcd4769 1155 #define I2C0_BASE (0x40066000u)
mbed_official 82:0b31dbcd4769 1156 /** Peripheral I2C0 base pointer */
mbed_official 82:0b31dbcd4769 1157 #define I2C0 ((I2C_Type *)I2C0_BASE)
mbed_official 82:0b31dbcd4769 1158 /** Array initializer of I2C peripheral base pointers */
mbed_official 82:0b31dbcd4769 1159 #define I2C_BASES { I2C0 }
mbed_official 82:0b31dbcd4769 1160
mbed_official 82:0b31dbcd4769 1161 /**
mbed_official 82:0b31dbcd4769 1162 * @}
mbed_official 82:0b31dbcd4769 1163 */ /* end of group I2C_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 1164
mbed_official 82:0b31dbcd4769 1165
mbed_official 82:0b31dbcd4769 1166 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1167 -- LLWU Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1168 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1169
mbed_official 82:0b31dbcd4769 1170 /**
mbed_official 82:0b31dbcd4769 1171 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1172 * @{
mbed_official 82:0b31dbcd4769 1173 */
mbed_official 82:0b31dbcd4769 1174
mbed_official 82:0b31dbcd4769 1175 /** LLWU - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 1176 typedef struct {
mbed_official 82:0b31dbcd4769 1177 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 1178 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
mbed_official 82:0b31dbcd4769 1179 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x2 */
mbed_official 82:0b31dbcd4769 1180 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x3 */
mbed_official 82:0b31dbcd4769 1181 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 1182 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x5 */
mbed_official 82:0b31dbcd4769 1183 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x6 */
mbed_official 82:0b31dbcd4769 1184 } LLWU_Type;
mbed_official 82:0b31dbcd4769 1185
mbed_official 82:0b31dbcd4769 1186 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1187 -- LLWU Register Masks
mbed_official 82:0b31dbcd4769 1188 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1189
mbed_official 82:0b31dbcd4769 1190 /**
mbed_official 82:0b31dbcd4769 1191 * @addtogroup LLWU_Register_Masks LLWU Register Masks
mbed_official 82:0b31dbcd4769 1192 * @{
mbed_official 82:0b31dbcd4769 1193 */
mbed_official 82:0b31dbcd4769 1194
mbed_official 82:0b31dbcd4769 1195 /* PE1 Bit Fields */
mbed_official 82:0b31dbcd4769 1196 #define LLWU_PE1_WUPE0_MASK 0x3u
mbed_official 82:0b31dbcd4769 1197 #define LLWU_PE1_WUPE0_SHIFT 0
mbed_official 82:0b31dbcd4769 1198 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
mbed_official 82:0b31dbcd4769 1199 #define LLWU_PE1_WUPE1_MASK 0xCu
mbed_official 82:0b31dbcd4769 1200 #define LLWU_PE1_WUPE1_SHIFT 2
mbed_official 82:0b31dbcd4769 1201 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
mbed_official 82:0b31dbcd4769 1202 #define LLWU_PE1_WUPE2_MASK 0x30u
mbed_official 82:0b31dbcd4769 1203 #define LLWU_PE1_WUPE2_SHIFT 4
mbed_official 82:0b31dbcd4769 1204 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
mbed_official 82:0b31dbcd4769 1205 #define LLWU_PE1_WUPE3_MASK 0xC0u
mbed_official 82:0b31dbcd4769 1206 #define LLWU_PE1_WUPE3_SHIFT 6
mbed_official 82:0b31dbcd4769 1207 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
mbed_official 82:0b31dbcd4769 1208 /* PE2 Bit Fields */
mbed_official 82:0b31dbcd4769 1209 #define LLWU_PE2_WUPE4_MASK 0x3u
mbed_official 82:0b31dbcd4769 1210 #define LLWU_PE2_WUPE4_SHIFT 0
mbed_official 82:0b31dbcd4769 1211 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
mbed_official 82:0b31dbcd4769 1212 #define LLWU_PE2_WUPE5_MASK 0xCu
mbed_official 82:0b31dbcd4769 1213 #define LLWU_PE2_WUPE5_SHIFT 2
mbed_official 82:0b31dbcd4769 1214 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
mbed_official 82:0b31dbcd4769 1215 #define LLWU_PE2_WUPE6_MASK 0x30u
mbed_official 82:0b31dbcd4769 1216 #define LLWU_PE2_WUPE6_SHIFT 4
mbed_official 82:0b31dbcd4769 1217 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
mbed_official 82:0b31dbcd4769 1218 #define LLWU_PE2_WUPE7_MASK 0xC0u
mbed_official 82:0b31dbcd4769 1219 #define LLWU_PE2_WUPE7_SHIFT 6
mbed_official 82:0b31dbcd4769 1220 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
mbed_official 82:0b31dbcd4769 1221 /* ME Bit Fields */
mbed_official 82:0b31dbcd4769 1222 #define LLWU_ME_WUME0_MASK 0x1u
mbed_official 82:0b31dbcd4769 1223 #define LLWU_ME_WUME0_SHIFT 0
mbed_official 82:0b31dbcd4769 1224 #define LLWU_ME_WUME1_MASK 0x2u
mbed_official 82:0b31dbcd4769 1225 #define LLWU_ME_WUME1_SHIFT 1
mbed_official 82:0b31dbcd4769 1226 #define LLWU_ME_WUME2_MASK 0x4u
mbed_official 82:0b31dbcd4769 1227 #define LLWU_ME_WUME2_SHIFT 2
mbed_official 82:0b31dbcd4769 1228 #define LLWU_ME_WUME3_MASK 0x8u
mbed_official 82:0b31dbcd4769 1229 #define LLWU_ME_WUME3_SHIFT 3
mbed_official 82:0b31dbcd4769 1230 #define LLWU_ME_WUME4_MASK 0x10u
mbed_official 82:0b31dbcd4769 1231 #define LLWU_ME_WUME4_SHIFT 4
mbed_official 82:0b31dbcd4769 1232 #define LLWU_ME_WUME5_MASK 0x20u
mbed_official 82:0b31dbcd4769 1233 #define LLWU_ME_WUME5_SHIFT 5
mbed_official 82:0b31dbcd4769 1234 #define LLWU_ME_WUME6_MASK 0x40u
mbed_official 82:0b31dbcd4769 1235 #define LLWU_ME_WUME6_SHIFT 6
mbed_official 82:0b31dbcd4769 1236 #define LLWU_ME_WUME7_MASK 0x80u
mbed_official 82:0b31dbcd4769 1237 #define LLWU_ME_WUME7_SHIFT 7
mbed_official 82:0b31dbcd4769 1238 /* F1 Bit Fields */
mbed_official 82:0b31dbcd4769 1239 #define LLWU_F1_WUF0_MASK 0x1u
mbed_official 82:0b31dbcd4769 1240 #define LLWU_F1_WUF0_SHIFT 0
mbed_official 82:0b31dbcd4769 1241 #define LLWU_F1_WUF1_MASK 0x2u
mbed_official 82:0b31dbcd4769 1242 #define LLWU_F1_WUF1_SHIFT 1
mbed_official 82:0b31dbcd4769 1243 #define LLWU_F1_WUF2_MASK 0x4u
mbed_official 82:0b31dbcd4769 1244 #define LLWU_F1_WUF2_SHIFT 2
mbed_official 82:0b31dbcd4769 1245 #define LLWU_F1_WUF3_MASK 0x8u
mbed_official 82:0b31dbcd4769 1246 #define LLWU_F1_WUF3_SHIFT 3
mbed_official 82:0b31dbcd4769 1247 #define LLWU_F1_WUF4_MASK 0x10u
mbed_official 82:0b31dbcd4769 1248 #define LLWU_F1_WUF4_SHIFT 4
mbed_official 82:0b31dbcd4769 1249 #define LLWU_F1_WUF5_MASK 0x20u
mbed_official 82:0b31dbcd4769 1250 #define LLWU_F1_WUF5_SHIFT 5
mbed_official 82:0b31dbcd4769 1251 #define LLWU_F1_WUF6_MASK 0x40u
mbed_official 82:0b31dbcd4769 1252 #define LLWU_F1_WUF6_SHIFT 6
mbed_official 82:0b31dbcd4769 1253 #define LLWU_F1_WUF7_MASK 0x80u
mbed_official 82:0b31dbcd4769 1254 #define LLWU_F1_WUF7_SHIFT 7
mbed_official 82:0b31dbcd4769 1255 /* F3 Bit Fields */
mbed_official 82:0b31dbcd4769 1256 #define LLWU_F3_MWUF0_MASK 0x1u
mbed_official 82:0b31dbcd4769 1257 #define LLWU_F3_MWUF0_SHIFT 0
mbed_official 82:0b31dbcd4769 1258 #define LLWU_F3_MWUF1_MASK 0x2u
mbed_official 82:0b31dbcd4769 1259 #define LLWU_F3_MWUF1_SHIFT 1
mbed_official 82:0b31dbcd4769 1260 #define LLWU_F3_MWUF2_MASK 0x4u
mbed_official 82:0b31dbcd4769 1261 #define LLWU_F3_MWUF2_SHIFT 2
mbed_official 82:0b31dbcd4769 1262 #define LLWU_F3_MWUF3_MASK 0x8u
mbed_official 82:0b31dbcd4769 1263 #define LLWU_F3_MWUF3_SHIFT 3
mbed_official 82:0b31dbcd4769 1264 #define LLWU_F3_MWUF4_MASK 0x10u
mbed_official 82:0b31dbcd4769 1265 #define LLWU_F3_MWUF4_SHIFT 4
mbed_official 82:0b31dbcd4769 1266 #define LLWU_F3_MWUF5_MASK 0x20u
mbed_official 82:0b31dbcd4769 1267 #define LLWU_F3_MWUF5_SHIFT 5
mbed_official 82:0b31dbcd4769 1268 #define LLWU_F3_MWUF6_MASK 0x40u
mbed_official 82:0b31dbcd4769 1269 #define LLWU_F3_MWUF6_SHIFT 6
mbed_official 82:0b31dbcd4769 1270 #define LLWU_F3_MWUF7_MASK 0x80u
mbed_official 82:0b31dbcd4769 1271 #define LLWU_F3_MWUF7_SHIFT 7
mbed_official 82:0b31dbcd4769 1272 /* FILT1 Bit Fields */
mbed_official 82:0b31dbcd4769 1273 #define LLWU_FILT1_FILTSEL_MASK 0xFu
mbed_official 82:0b31dbcd4769 1274 #define LLWU_FILT1_FILTSEL_SHIFT 0
mbed_official 82:0b31dbcd4769 1275 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
mbed_official 82:0b31dbcd4769 1276 #define LLWU_FILT1_FILTE_MASK 0x60u
mbed_official 82:0b31dbcd4769 1277 #define LLWU_FILT1_FILTE_SHIFT 5
mbed_official 82:0b31dbcd4769 1278 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
mbed_official 82:0b31dbcd4769 1279 #define LLWU_FILT1_FILTF_MASK 0x80u
mbed_official 82:0b31dbcd4769 1280 #define LLWU_FILT1_FILTF_SHIFT 7
mbed_official 82:0b31dbcd4769 1281 /* FILT2 Bit Fields */
mbed_official 82:0b31dbcd4769 1282 #define LLWU_FILT2_FILTSEL_MASK 0xFu
mbed_official 82:0b31dbcd4769 1283 #define LLWU_FILT2_FILTSEL_SHIFT 0
mbed_official 82:0b31dbcd4769 1284 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
mbed_official 82:0b31dbcd4769 1285 #define LLWU_FILT2_FILTE_MASK 0x60u
mbed_official 82:0b31dbcd4769 1286 #define LLWU_FILT2_FILTE_SHIFT 5
mbed_official 82:0b31dbcd4769 1287 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
mbed_official 82:0b31dbcd4769 1288 #define LLWU_FILT2_FILTF_MASK 0x80u
mbed_official 82:0b31dbcd4769 1289 #define LLWU_FILT2_FILTF_SHIFT 7
mbed_official 82:0b31dbcd4769 1290
mbed_official 82:0b31dbcd4769 1291 /**
mbed_official 82:0b31dbcd4769 1292 * @}
mbed_official 82:0b31dbcd4769 1293 */ /* end of group LLWU_Register_Masks */
mbed_official 82:0b31dbcd4769 1294
mbed_official 82:0b31dbcd4769 1295
mbed_official 82:0b31dbcd4769 1296 /* LLWU - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 1297 /** Peripheral LLWU base address */
mbed_official 82:0b31dbcd4769 1298 #define LLWU_BASE (0x4007C000u)
mbed_official 82:0b31dbcd4769 1299 /** Peripheral LLWU base pointer */
mbed_official 82:0b31dbcd4769 1300 #define LLWU ((LLWU_Type *)LLWU_BASE)
mbed_official 82:0b31dbcd4769 1301 /** Array initializer of LLWU peripheral base pointers */
mbed_official 82:0b31dbcd4769 1302 #define LLWU_BASES { LLWU }
mbed_official 82:0b31dbcd4769 1303
mbed_official 82:0b31dbcd4769 1304 /**
mbed_official 82:0b31dbcd4769 1305 * @}
mbed_official 82:0b31dbcd4769 1306 */ /* end of group LLWU_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 1307
mbed_official 82:0b31dbcd4769 1308
mbed_official 82:0b31dbcd4769 1309 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1310 -- LPTMR Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1311 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1312
mbed_official 82:0b31dbcd4769 1313 /**
mbed_official 82:0b31dbcd4769 1314 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1315 * @{
mbed_official 82:0b31dbcd4769 1316 */
mbed_official 82:0b31dbcd4769 1317
mbed_official 82:0b31dbcd4769 1318 /** LPTMR - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 1319 typedef struct {
mbed_official 82:0b31dbcd4769 1320 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 1321 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 1322 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
mbed_official 82:0b31dbcd4769 1323 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
mbed_official 82:0b31dbcd4769 1324 } LPTMR_Type;
mbed_official 82:0b31dbcd4769 1325
mbed_official 82:0b31dbcd4769 1326 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1327 -- LPTMR Register Masks
mbed_official 82:0b31dbcd4769 1328 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1329
mbed_official 82:0b31dbcd4769 1330 /**
mbed_official 82:0b31dbcd4769 1331 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
mbed_official 82:0b31dbcd4769 1332 * @{
mbed_official 82:0b31dbcd4769 1333 */
mbed_official 82:0b31dbcd4769 1334
mbed_official 82:0b31dbcd4769 1335 /* CSR Bit Fields */
mbed_official 82:0b31dbcd4769 1336 #define LPTMR_CSR_TEN_MASK 0x1u
mbed_official 82:0b31dbcd4769 1337 #define LPTMR_CSR_TEN_SHIFT 0
mbed_official 82:0b31dbcd4769 1338 #define LPTMR_CSR_TMS_MASK 0x2u
mbed_official 82:0b31dbcd4769 1339 #define LPTMR_CSR_TMS_SHIFT 1
mbed_official 82:0b31dbcd4769 1340 #define LPTMR_CSR_TFC_MASK 0x4u
mbed_official 82:0b31dbcd4769 1341 #define LPTMR_CSR_TFC_SHIFT 2
mbed_official 82:0b31dbcd4769 1342 #define LPTMR_CSR_TPP_MASK 0x8u
mbed_official 82:0b31dbcd4769 1343 #define LPTMR_CSR_TPP_SHIFT 3
mbed_official 82:0b31dbcd4769 1344 #define LPTMR_CSR_TPS_MASK 0x30u
mbed_official 82:0b31dbcd4769 1345 #define LPTMR_CSR_TPS_SHIFT 4
mbed_official 82:0b31dbcd4769 1346 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
mbed_official 82:0b31dbcd4769 1347 #define LPTMR_CSR_TIE_MASK 0x40u
mbed_official 82:0b31dbcd4769 1348 #define LPTMR_CSR_TIE_SHIFT 6
mbed_official 82:0b31dbcd4769 1349 #define LPTMR_CSR_TCF_MASK 0x80u
mbed_official 82:0b31dbcd4769 1350 #define LPTMR_CSR_TCF_SHIFT 7
mbed_official 82:0b31dbcd4769 1351 /* PSR Bit Fields */
mbed_official 82:0b31dbcd4769 1352 #define LPTMR_PSR_PCS_MASK 0x3u
mbed_official 82:0b31dbcd4769 1353 #define LPTMR_PSR_PCS_SHIFT 0
mbed_official 82:0b31dbcd4769 1354 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
mbed_official 82:0b31dbcd4769 1355 #define LPTMR_PSR_PBYP_MASK 0x4u
mbed_official 82:0b31dbcd4769 1356 #define LPTMR_PSR_PBYP_SHIFT 2
mbed_official 82:0b31dbcd4769 1357 #define LPTMR_PSR_PRESCALE_MASK 0x78u
mbed_official 82:0b31dbcd4769 1358 #define LPTMR_PSR_PRESCALE_SHIFT 3
mbed_official 82:0b31dbcd4769 1359 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
mbed_official 82:0b31dbcd4769 1360 /* CMR Bit Fields */
mbed_official 82:0b31dbcd4769 1361 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 1362 #define LPTMR_CMR_COMPARE_SHIFT 0
mbed_official 82:0b31dbcd4769 1363 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
mbed_official 82:0b31dbcd4769 1364 /* CNR Bit Fields */
mbed_official 82:0b31dbcd4769 1365 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 1366 #define LPTMR_CNR_COUNTER_SHIFT 0
mbed_official 82:0b31dbcd4769 1367 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
mbed_official 82:0b31dbcd4769 1368
mbed_official 82:0b31dbcd4769 1369 /**
mbed_official 82:0b31dbcd4769 1370 * @}
mbed_official 82:0b31dbcd4769 1371 */ /* end of group LPTMR_Register_Masks */
mbed_official 82:0b31dbcd4769 1372
mbed_official 82:0b31dbcd4769 1373
mbed_official 82:0b31dbcd4769 1374 /* LPTMR - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 1375 /** Peripheral LPTMR0 base address */
mbed_official 82:0b31dbcd4769 1376 #define LPTMR0_BASE (0x40040000u)
mbed_official 82:0b31dbcd4769 1377 /** Peripheral LPTMR0 base pointer */
mbed_official 82:0b31dbcd4769 1378 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
mbed_official 82:0b31dbcd4769 1379 /** Array initializer of LPTMR peripheral base pointers */
mbed_official 82:0b31dbcd4769 1380 #define LPTMR_BASES { LPTMR0 }
mbed_official 82:0b31dbcd4769 1381
mbed_official 82:0b31dbcd4769 1382 /**
mbed_official 82:0b31dbcd4769 1383 * @}
mbed_official 82:0b31dbcd4769 1384 */ /* end of group LPTMR_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 1385
mbed_official 82:0b31dbcd4769 1386
mbed_official 82:0b31dbcd4769 1387 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1388 -- MCG Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1389 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1390
mbed_official 82:0b31dbcd4769 1391 /**
mbed_official 82:0b31dbcd4769 1392 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1393 * @{
mbed_official 82:0b31dbcd4769 1394 */
mbed_official 82:0b31dbcd4769 1395
mbed_official 82:0b31dbcd4769 1396 /** MCG - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 1397 typedef struct {
mbed_official 82:0b31dbcd4769 1398 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 1399 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
mbed_official 82:0b31dbcd4769 1400 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
mbed_official 82:0b31dbcd4769 1401 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
mbed_official 82:0b31dbcd4769 1402 __I uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 1403 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
mbed_official 82:0b31dbcd4769 1404 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
mbed_official 82:0b31dbcd4769 1405 uint8_t RESERVED_0[1];
mbed_official 82:0b31dbcd4769 1406 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
mbed_official 82:0b31dbcd4769 1407 uint8_t RESERVED_1[1];
mbed_official 82:0b31dbcd4769 1408 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
mbed_official 82:0b31dbcd4769 1409 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
mbed_official 82:0b31dbcd4769 1410 } MCG_Type;
mbed_official 82:0b31dbcd4769 1411
mbed_official 82:0b31dbcd4769 1412 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1413 -- MCG Register Masks
mbed_official 82:0b31dbcd4769 1414 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1415
mbed_official 82:0b31dbcd4769 1416 /**
mbed_official 82:0b31dbcd4769 1417 * @addtogroup MCG_Register_Masks MCG Register Masks
mbed_official 82:0b31dbcd4769 1418 * @{
mbed_official 82:0b31dbcd4769 1419 */
mbed_official 82:0b31dbcd4769 1420
mbed_official 82:0b31dbcd4769 1421 /* C1 Bit Fields */
mbed_official 82:0b31dbcd4769 1422 #define MCG_C1_IREFSTEN_MASK 0x1u
mbed_official 82:0b31dbcd4769 1423 #define MCG_C1_IREFSTEN_SHIFT 0
mbed_official 82:0b31dbcd4769 1424 #define MCG_C1_IRCLKEN_MASK 0x2u
mbed_official 82:0b31dbcd4769 1425 #define MCG_C1_IRCLKEN_SHIFT 1
mbed_official 82:0b31dbcd4769 1426 #define MCG_C1_IREFS_MASK 0x4u
mbed_official 82:0b31dbcd4769 1427 #define MCG_C1_IREFS_SHIFT 2
mbed_official 82:0b31dbcd4769 1428 #define MCG_C1_FRDIV_MASK 0x38u
mbed_official 82:0b31dbcd4769 1429 #define MCG_C1_FRDIV_SHIFT 3
mbed_official 82:0b31dbcd4769 1430 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
mbed_official 82:0b31dbcd4769 1431 #define MCG_C1_CLKS_MASK 0xC0u
mbed_official 82:0b31dbcd4769 1432 #define MCG_C1_CLKS_SHIFT 6
mbed_official 82:0b31dbcd4769 1433 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
mbed_official 82:0b31dbcd4769 1434 /* C2 Bit Fields */
mbed_official 82:0b31dbcd4769 1435 #define MCG_C2_IRCS_MASK 0x1u
mbed_official 82:0b31dbcd4769 1436 #define MCG_C2_IRCS_SHIFT 0
mbed_official 82:0b31dbcd4769 1437 #define MCG_C2_LP_MASK 0x2u
mbed_official 82:0b31dbcd4769 1438 #define MCG_C2_LP_SHIFT 1
mbed_official 82:0b31dbcd4769 1439 #define MCG_C2_EREFS0_MASK 0x4u
mbed_official 82:0b31dbcd4769 1440 #define MCG_C2_EREFS0_SHIFT 2
mbed_official 82:0b31dbcd4769 1441 #define MCG_C2_HGO0_MASK 0x8u
mbed_official 82:0b31dbcd4769 1442 #define MCG_C2_HGO0_SHIFT 3
mbed_official 82:0b31dbcd4769 1443 #define MCG_C2_RANGE0_MASK 0x30u
mbed_official 82:0b31dbcd4769 1444 #define MCG_C2_RANGE0_SHIFT 4
mbed_official 82:0b31dbcd4769 1445 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
mbed_official 82:0b31dbcd4769 1446 #define MCG_C2_LOCRE0_MASK 0x80u
mbed_official 82:0b31dbcd4769 1447 #define MCG_C2_LOCRE0_SHIFT 7
mbed_official 82:0b31dbcd4769 1448 /* C3 Bit Fields */
mbed_official 82:0b31dbcd4769 1449 #define MCG_C3_SCTRIM_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1450 #define MCG_C3_SCTRIM_SHIFT 0
mbed_official 82:0b31dbcd4769 1451 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
mbed_official 82:0b31dbcd4769 1452 /* C4 Bit Fields */
mbed_official 82:0b31dbcd4769 1453 #define MCG_C4_SCFTRIM_MASK 0x1u
mbed_official 82:0b31dbcd4769 1454 #define MCG_C4_SCFTRIM_SHIFT 0
mbed_official 82:0b31dbcd4769 1455 #define MCG_C4_FCTRIM_MASK 0x1Eu
mbed_official 82:0b31dbcd4769 1456 #define MCG_C4_FCTRIM_SHIFT 1
mbed_official 82:0b31dbcd4769 1457 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
mbed_official 82:0b31dbcd4769 1458 #define MCG_C4_DRST_DRS_MASK 0x60u
mbed_official 82:0b31dbcd4769 1459 #define MCG_C4_DRST_DRS_SHIFT 5
mbed_official 82:0b31dbcd4769 1460 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
mbed_official 82:0b31dbcd4769 1461 #define MCG_C4_DMX32_MASK 0x80u
mbed_official 82:0b31dbcd4769 1462 #define MCG_C4_DMX32_SHIFT 7
mbed_official 82:0b31dbcd4769 1463 /* C6 Bit Fields */
mbed_official 82:0b31dbcd4769 1464 #define MCG_C6_CME_MASK 0x20u
mbed_official 82:0b31dbcd4769 1465 #define MCG_C6_CME_SHIFT 5
mbed_official 82:0b31dbcd4769 1466 /* S Bit Fields */
mbed_official 82:0b31dbcd4769 1467 #define MCG_S_IRCST_MASK 0x1u
mbed_official 82:0b31dbcd4769 1468 #define MCG_S_IRCST_SHIFT 0
mbed_official 82:0b31dbcd4769 1469 #define MCG_S_OSCINIT0_MASK 0x2u
mbed_official 82:0b31dbcd4769 1470 #define MCG_S_OSCINIT0_SHIFT 1
mbed_official 82:0b31dbcd4769 1471 #define MCG_S_CLKST_MASK 0xCu
mbed_official 82:0b31dbcd4769 1472 #define MCG_S_CLKST_SHIFT 2
mbed_official 82:0b31dbcd4769 1473 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
mbed_official 82:0b31dbcd4769 1474 #define MCG_S_IREFST_MASK 0x10u
mbed_official 82:0b31dbcd4769 1475 #define MCG_S_IREFST_SHIFT 4
mbed_official 82:0b31dbcd4769 1476 /* SC Bit Fields */
mbed_official 82:0b31dbcd4769 1477 #define MCG_SC_LOCS0_MASK 0x1u
mbed_official 82:0b31dbcd4769 1478 #define MCG_SC_LOCS0_SHIFT 0
mbed_official 82:0b31dbcd4769 1479 #define MCG_SC_FCRDIV_MASK 0xEu
mbed_official 82:0b31dbcd4769 1480 #define MCG_SC_FCRDIV_SHIFT 1
mbed_official 82:0b31dbcd4769 1481 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
mbed_official 82:0b31dbcd4769 1482 #define MCG_SC_FLTPRSRV_MASK 0x10u
mbed_official 82:0b31dbcd4769 1483 #define MCG_SC_FLTPRSRV_SHIFT 4
mbed_official 82:0b31dbcd4769 1484 #define MCG_SC_ATMF_MASK 0x20u
mbed_official 82:0b31dbcd4769 1485 #define MCG_SC_ATMF_SHIFT 5
mbed_official 82:0b31dbcd4769 1486 #define MCG_SC_ATMS_MASK 0x40u
mbed_official 82:0b31dbcd4769 1487 #define MCG_SC_ATMS_SHIFT 6
mbed_official 82:0b31dbcd4769 1488 #define MCG_SC_ATME_MASK 0x80u
mbed_official 82:0b31dbcd4769 1489 #define MCG_SC_ATME_SHIFT 7
mbed_official 82:0b31dbcd4769 1490 /* ATCVH Bit Fields */
mbed_official 82:0b31dbcd4769 1491 #define MCG_ATCVH_ATCVH_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1492 #define MCG_ATCVH_ATCVH_SHIFT 0
mbed_official 82:0b31dbcd4769 1493 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
mbed_official 82:0b31dbcd4769 1494 /* ATCVL Bit Fields */
mbed_official 82:0b31dbcd4769 1495 #define MCG_ATCVL_ATCVL_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1496 #define MCG_ATCVL_ATCVL_SHIFT 0
mbed_official 82:0b31dbcd4769 1497 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
mbed_official 82:0b31dbcd4769 1498
mbed_official 82:0b31dbcd4769 1499 /**
mbed_official 82:0b31dbcd4769 1500 * @}
mbed_official 82:0b31dbcd4769 1501 */ /* end of group MCG_Register_Masks */
mbed_official 82:0b31dbcd4769 1502
mbed_official 82:0b31dbcd4769 1503
mbed_official 82:0b31dbcd4769 1504 /* MCG - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 1505 /** Peripheral MCG base address */
mbed_official 82:0b31dbcd4769 1506 #define MCG_BASE (0x40064000u)
mbed_official 82:0b31dbcd4769 1507 /** Peripheral MCG base pointer */
mbed_official 82:0b31dbcd4769 1508 #define MCG ((MCG_Type *)MCG_BASE)
mbed_official 82:0b31dbcd4769 1509 /** Array initializer of MCG peripheral base pointers */
mbed_official 82:0b31dbcd4769 1510 #define MCG_BASES { MCG }
mbed_official 82:0b31dbcd4769 1511
mbed_official 82:0b31dbcd4769 1512 /**
mbed_official 82:0b31dbcd4769 1513 * @}
mbed_official 82:0b31dbcd4769 1514 */ /* end of group MCG_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 1515
mbed_official 82:0b31dbcd4769 1516
mbed_official 82:0b31dbcd4769 1517 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1518 -- MCM Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1519 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1520
mbed_official 82:0b31dbcd4769 1521 /**
mbed_official 82:0b31dbcd4769 1522 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1523 * @{
mbed_official 82:0b31dbcd4769 1524 */
mbed_official 82:0b31dbcd4769 1525
mbed_official 82:0b31dbcd4769 1526 /** MCM - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 1527 typedef struct {
mbed_official 82:0b31dbcd4769 1528 uint8_t RESERVED_0[8];
mbed_official 82:0b31dbcd4769 1529 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
mbed_official 82:0b31dbcd4769 1530 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
mbed_official 82:0b31dbcd4769 1531 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
mbed_official 82:0b31dbcd4769 1532 uint8_t RESERVED_1[48];
mbed_official 82:0b31dbcd4769 1533 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
mbed_official 82:0b31dbcd4769 1534 } MCM_Type;
mbed_official 82:0b31dbcd4769 1535
mbed_official 82:0b31dbcd4769 1536 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1537 -- MCM Register Masks
mbed_official 82:0b31dbcd4769 1538 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1539
mbed_official 82:0b31dbcd4769 1540 /**
mbed_official 82:0b31dbcd4769 1541 * @addtogroup MCM_Register_Masks MCM Register Masks
mbed_official 82:0b31dbcd4769 1542 * @{
mbed_official 82:0b31dbcd4769 1543 */
mbed_official 82:0b31dbcd4769 1544
mbed_official 82:0b31dbcd4769 1545 /* PLASC Bit Fields */
mbed_official 82:0b31dbcd4769 1546 #define MCM_PLASC_ASC_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1547 #define MCM_PLASC_ASC_SHIFT 0
mbed_official 82:0b31dbcd4769 1548 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
mbed_official 82:0b31dbcd4769 1549 /* PLAMC Bit Fields */
mbed_official 82:0b31dbcd4769 1550 #define MCM_PLAMC_AMC_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1551 #define MCM_PLAMC_AMC_SHIFT 0
mbed_official 82:0b31dbcd4769 1552 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
mbed_official 82:0b31dbcd4769 1553 /* PLACR Bit Fields */
mbed_official 82:0b31dbcd4769 1554 #define MCM_PLACR_ARB_MASK 0x200u
mbed_official 82:0b31dbcd4769 1555 #define MCM_PLACR_ARB_SHIFT 9
mbed_official 82:0b31dbcd4769 1556 #define MCM_PLACR_CFCC_MASK 0x400u
mbed_official 82:0b31dbcd4769 1557 #define MCM_PLACR_CFCC_SHIFT 10
mbed_official 82:0b31dbcd4769 1558 #define MCM_PLACR_DFCDA_MASK 0x800u
mbed_official 82:0b31dbcd4769 1559 #define MCM_PLACR_DFCDA_SHIFT 11
mbed_official 82:0b31dbcd4769 1560 #define MCM_PLACR_DFCIC_MASK 0x1000u
mbed_official 82:0b31dbcd4769 1561 #define MCM_PLACR_DFCIC_SHIFT 12
mbed_official 82:0b31dbcd4769 1562 #define MCM_PLACR_DFCC_MASK 0x2000u
mbed_official 82:0b31dbcd4769 1563 #define MCM_PLACR_DFCC_SHIFT 13
mbed_official 82:0b31dbcd4769 1564 #define MCM_PLACR_EFDS_MASK 0x4000u
mbed_official 82:0b31dbcd4769 1565 #define MCM_PLACR_EFDS_SHIFT 14
mbed_official 82:0b31dbcd4769 1566 #define MCM_PLACR_DFCS_MASK 0x8000u
mbed_official 82:0b31dbcd4769 1567 #define MCM_PLACR_DFCS_SHIFT 15
mbed_official 82:0b31dbcd4769 1568 #define MCM_PLACR_ESFC_MASK 0x10000u
mbed_official 82:0b31dbcd4769 1569 #define MCM_PLACR_ESFC_SHIFT 16
mbed_official 82:0b31dbcd4769 1570 /* CPO Bit Fields */
mbed_official 82:0b31dbcd4769 1571 #define MCM_CPO_CPOREQ_MASK 0x1u
mbed_official 82:0b31dbcd4769 1572 #define MCM_CPO_CPOREQ_SHIFT 0
mbed_official 82:0b31dbcd4769 1573 #define MCM_CPO_CPOACK_MASK 0x2u
mbed_official 82:0b31dbcd4769 1574 #define MCM_CPO_CPOACK_SHIFT 1
mbed_official 82:0b31dbcd4769 1575 #define MCM_CPO_CPOWOI_MASK 0x4u
mbed_official 82:0b31dbcd4769 1576 #define MCM_CPO_CPOWOI_SHIFT 2
mbed_official 82:0b31dbcd4769 1577
mbed_official 82:0b31dbcd4769 1578 /**
mbed_official 82:0b31dbcd4769 1579 * @}
mbed_official 82:0b31dbcd4769 1580 */ /* end of group MCM_Register_Masks */
mbed_official 82:0b31dbcd4769 1581
mbed_official 82:0b31dbcd4769 1582
mbed_official 82:0b31dbcd4769 1583 /* MCM - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 1584 /** Peripheral MCM base address */
mbed_official 82:0b31dbcd4769 1585 #define MCM_BASE (0xF0003000u)
mbed_official 82:0b31dbcd4769 1586 /** Peripheral MCM base pointer */
mbed_official 82:0b31dbcd4769 1587 #define MCM ((MCM_Type *)MCM_BASE)
mbed_official 82:0b31dbcd4769 1588 /** Array initializer of MCM peripheral base pointers */
mbed_official 82:0b31dbcd4769 1589 #define MCM_BASES { MCM }
mbed_official 82:0b31dbcd4769 1590
mbed_official 82:0b31dbcd4769 1591 /**
mbed_official 82:0b31dbcd4769 1592 * @}
mbed_official 82:0b31dbcd4769 1593 */ /* end of group MCM_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 1594
mbed_official 82:0b31dbcd4769 1595
mbed_official 82:0b31dbcd4769 1596 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1597 -- MTB Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1598 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1599
mbed_official 82:0b31dbcd4769 1600 /**
mbed_official 82:0b31dbcd4769 1601 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1602 * @{
mbed_official 82:0b31dbcd4769 1603 */
mbed_official 82:0b31dbcd4769 1604
mbed_official 82:0b31dbcd4769 1605 /** MTB - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 1606 typedef struct {
mbed_official 82:0b31dbcd4769 1607 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 1608 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 1609 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
mbed_official 82:0b31dbcd4769 1610 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
mbed_official 82:0b31dbcd4769 1611 uint8_t RESERVED_0[3824];
mbed_official 82:0b31dbcd4769 1612 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
mbed_official 82:0b31dbcd4769 1613 uint8_t RESERVED_1[156];
mbed_official 82:0b31dbcd4769 1614 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
mbed_official 82:0b31dbcd4769 1615 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
mbed_official 82:0b31dbcd4769 1616 uint8_t RESERVED_2[8];
mbed_official 82:0b31dbcd4769 1617 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
mbed_official 82:0b31dbcd4769 1618 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
mbed_official 82:0b31dbcd4769 1619 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
mbed_official 82:0b31dbcd4769 1620 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
mbed_official 82:0b31dbcd4769 1621 uint8_t RESERVED_3[8];
mbed_official 82:0b31dbcd4769 1622 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
mbed_official 82:0b31dbcd4769 1623 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
mbed_official 82:0b31dbcd4769 1624 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
mbed_official 82:0b31dbcd4769 1625 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 82:0b31dbcd4769 1626 } MTB_Type;
mbed_official 82:0b31dbcd4769 1627
mbed_official 82:0b31dbcd4769 1628 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1629 -- MTB Register Masks
mbed_official 82:0b31dbcd4769 1630 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1631
mbed_official 82:0b31dbcd4769 1632 /**
mbed_official 82:0b31dbcd4769 1633 * @addtogroup MTB_Register_Masks MTB Register Masks
mbed_official 82:0b31dbcd4769 1634 * @{
mbed_official 82:0b31dbcd4769 1635 */
mbed_official 82:0b31dbcd4769 1636
mbed_official 82:0b31dbcd4769 1637 /* POSITION Bit Fields */
mbed_official 82:0b31dbcd4769 1638 #define MTB_POSITION_WRAP_MASK 0x4u
mbed_official 82:0b31dbcd4769 1639 #define MTB_POSITION_WRAP_SHIFT 2
mbed_official 82:0b31dbcd4769 1640 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
mbed_official 82:0b31dbcd4769 1641 #define MTB_POSITION_POINTER_SHIFT 3
mbed_official 82:0b31dbcd4769 1642 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
mbed_official 82:0b31dbcd4769 1643 /* MASTER Bit Fields */
mbed_official 82:0b31dbcd4769 1644 #define MTB_MASTER_MASK_MASK 0x1Fu
mbed_official 82:0b31dbcd4769 1645 #define MTB_MASTER_MASK_SHIFT 0
mbed_official 82:0b31dbcd4769 1646 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
mbed_official 82:0b31dbcd4769 1647 #define MTB_MASTER_TSTARTEN_MASK 0x20u
mbed_official 82:0b31dbcd4769 1648 #define MTB_MASTER_TSTARTEN_SHIFT 5
mbed_official 82:0b31dbcd4769 1649 #define MTB_MASTER_TSTOPEN_MASK 0x40u
mbed_official 82:0b31dbcd4769 1650 #define MTB_MASTER_TSTOPEN_SHIFT 6
mbed_official 82:0b31dbcd4769 1651 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
mbed_official 82:0b31dbcd4769 1652 #define MTB_MASTER_SFRWPRIV_SHIFT 7
mbed_official 82:0b31dbcd4769 1653 #define MTB_MASTER_RAMPRIV_MASK 0x100u
mbed_official 82:0b31dbcd4769 1654 #define MTB_MASTER_RAMPRIV_SHIFT 8
mbed_official 82:0b31dbcd4769 1655 #define MTB_MASTER_HALTREQ_MASK 0x200u
mbed_official 82:0b31dbcd4769 1656 #define MTB_MASTER_HALTREQ_SHIFT 9
mbed_official 82:0b31dbcd4769 1657 #define MTB_MASTER_EN_MASK 0x80000000u
mbed_official 82:0b31dbcd4769 1658 #define MTB_MASTER_EN_SHIFT 31
mbed_official 82:0b31dbcd4769 1659 /* FLOW Bit Fields */
mbed_official 82:0b31dbcd4769 1660 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
mbed_official 82:0b31dbcd4769 1661 #define MTB_FLOW_AUTOSTOP_SHIFT 0
mbed_official 82:0b31dbcd4769 1662 #define MTB_FLOW_AUTOHALT_MASK 0x2u
mbed_official 82:0b31dbcd4769 1663 #define MTB_FLOW_AUTOHALT_SHIFT 1
mbed_official 82:0b31dbcd4769 1664 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
mbed_official 82:0b31dbcd4769 1665 #define MTB_FLOW_WATERMARK_SHIFT 3
mbed_official 82:0b31dbcd4769 1666 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
mbed_official 82:0b31dbcd4769 1667 /* BASE Bit Fields */
mbed_official 82:0b31dbcd4769 1668 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1669 #define MTB_BASE_BASEADDR_SHIFT 0
mbed_official 82:0b31dbcd4769 1670 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
mbed_official 82:0b31dbcd4769 1671 /* MODECTRL Bit Fields */
mbed_official 82:0b31dbcd4769 1672 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1673 #define MTB_MODECTRL_MODECTRL_SHIFT 0
mbed_official 82:0b31dbcd4769 1674 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
mbed_official 82:0b31dbcd4769 1675 /* TAGSET Bit Fields */
mbed_official 82:0b31dbcd4769 1676 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1677 #define MTB_TAGSET_TAGSET_SHIFT 0
mbed_official 82:0b31dbcd4769 1678 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
mbed_official 82:0b31dbcd4769 1679 /* TAGCLEAR Bit Fields */
mbed_official 82:0b31dbcd4769 1680 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1681 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
mbed_official 82:0b31dbcd4769 1682 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
mbed_official 82:0b31dbcd4769 1683 /* LOCKACCESS Bit Fields */
mbed_official 82:0b31dbcd4769 1684 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1685 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
mbed_official 82:0b31dbcd4769 1686 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
mbed_official 82:0b31dbcd4769 1687 /* LOCKSTAT Bit Fields */
mbed_official 82:0b31dbcd4769 1688 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1689 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
mbed_official 82:0b31dbcd4769 1690 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
mbed_official 82:0b31dbcd4769 1691 /* AUTHSTAT Bit Fields */
mbed_official 82:0b31dbcd4769 1692 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
mbed_official 82:0b31dbcd4769 1693 #define MTB_AUTHSTAT_BIT0_SHIFT 0
mbed_official 82:0b31dbcd4769 1694 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
mbed_official 82:0b31dbcd4769 1695 #define MTB_AUTHSTAT_BIT1_SHIFT 1
mbed_official 82:0b31dbcd4769 1696 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
mbed_official 82:0b31dbcd4769 1697 #define MTB_AUTHSTAT_BIT2_SHIFT 2
mbed_official 82:0b31dbcd4769 1698 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
mbed_official 82:0b31dbcd4769 1699 #define MTB_AUTHSTAT_BIT3_SHIFT 3
mbed_official 82:0b31dbcd4769 1700 /* DEVICEARCH Bit Fields */
mbed_official 82:0b31dbcd4769 1701 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1702 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
mbed_official 82:0b31dbcd4769 1703 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
mbed_official 82:0b31dbcd4769 1704 /* DEVICECFG Bit Fields */
mbed_official 82:0b31dbcd4769 1705 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1706 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
mbed_official 82:0b31dbcd4769 1707 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
mbed_official 82:0b31dbcd4769 1708 /* DEVICETYPID Bit Fields */
mbed_official 82:0b31dbcd4769 1709 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1710 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
mbed_official 82:0b31dbcd4769 1711 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
mbed_official 82:0b31dbcd4769 1712 /* PERIPHID Bit Fields */
mbed_official 82:0b31dbcd4769 1713 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1714 #define MTB_PERIPHID_PERIPHID_SHIFT 0
mbed_official 82:0b31dbcd4769 1715 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
mbed_official 82:0b31dbcd4769 1716 /* COMPID Bit Fields */
mbed_official 82:0b31dbcd4769 1717 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1718 #define MTB_COMPID_COMPID_SHIFT 0
mbed_official 82:0b31dbcd4769 1719 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
mbed_official 82:0b31dbcd4769 1720
mbed_official 82:0b31dbcd4769 1721 /**
mbed_official 82:0b31dbcd4769 1722 * @}
mbed_official 82:0b31dbcd4769 1723 */ /* end of group MTB_Register_Masks */
mbed_official 82:0b31dbcd4769 1724
mbed_official 82:0b31dbcd4769 1725
mbed_official 82:0b31dbcd4769 1726 /* MTB - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 1727 /** Peripheral MTB base address */
mbed_official 82:0b31dbcd4769 1728 #define MTB_BASE (0xF0000000u)
mbed_official 82:0b31dbcd4769 1729 /** Peripheral MTB base pointer */
mbed_official 82:0b31dbcd4769 1730 #define MTB ((MTB_Type *)MTB_BASE)
mbed_official 82:0b31dbcd4769 1731 /** Array initializer of MTB peripheral base pointers */
mbed_official 82:0b31dbcd4769 1732 #define MTB_BASES { MTB }
mbed_official 82:0b31dbcd4769 1733
mbed_official 82:0b31dbcd4769 1734 /**
mbed_official 82:0b31dbcd4769 1735 * @}
mbed_official 82:0b31dbcd4769 1736 */ /* end of group MTB_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 1737
mbed_official 82:0b31dbcd4769 1738
mbed_official 82:0b31dbcd4769 1739 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1740 -- MTBDWT Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1741 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1742
mbed_official 82:0b31dbcd4769 1743 /**
mbed_official 82:0b31dbcd4769 1744 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1745 * @{
mbed_official 82:0b31dbcd4769 1746 */
mbed_official 82:0b31dbcd4769 1747
mbed_official 82:0b31dbcd4769 1748 /** MTBDWT - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 1749 typedef struct {
mbed_official 82:0b31dbcd4769 1750 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 1751 uint8_t RESERVED_0[28];
mbed_official 82:0b31dbcd4769 1752 struct { /* offset: 0x20, array step: 0x10 */
mbed_official 82:0b31dbcd4769 1753 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
mbed_official 82:0b31dbcd4769 1754 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
mbed_official 82:0b31dbcd4769 1755 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
mbed_official 82:0b31dbcd4769 1756 uint8_t RESERVED_0[4];
mbed_official 82:0b31dbcd4769 1757 } COMPARATOR[2];
mbed_official 82:0b31dbcd4769 1758 uint8_t RESERVED_1[448];
mbed_official 82:0b31dbcd4769 1759 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
mbed_official 82:0b31dbcd4769 1760 uint8_t RESERVED_2[3524];
mbed_official 82:0b31dbcd4769 1761 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
mbed_official 82:0b31dbcd4769 1762 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
mbed_official 82:0b31dbcd4769 1763 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
mbed_official 82:0b31dbcd4769 1764 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 82:0b31dbcd4769 1765 } MTBDWT_Type;
mbed_official 82:0b31dbcd4769 1766
mbed_official 82:0b31dbcd4769 1767 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1768 -- MTBDWT Register Masks
mbed_official 82:0b31dbcd4769 1769 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1770
mbed_official 82:0b31dbcd4769 1771 /**
mbed_official 82:0b31dbcd4769 1772 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
mbed_official 82:0b31dbcd4769 1773 * @{
mbed_official 82:0b31dbcd4769 1774 */
mbed_official 82:0b31dbcd4769 1775
mbed_official 82:0b31dbcd4769 1776 /* CTRL Bit Fields */
mbed_official 82:0b31dbcd4769 1777 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
mbed_official 82:0b31dbcd4769 1778 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
mbed_official 82:0b31dbcd4769 1779 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
mbed_official 82:0b31dbcd4769 1780 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
mbed_official 82:0b31dbcd4769 1781 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
mbed_official 82:0b31dbcd4769 1782 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
mbed_official 82:0b31dbcd4769 1783 /* COMP Bit Fields */
mbed_official 82:0b31dbcd4769 1784 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1785 #define MTBDWT_COMP_COMP_SHIFT 0
mbed_official 82:0b31dbcd4769 1786 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
mbed_official 82:0b31dbcd4769 1787 /* MASK Bit Fields */
mbed_official 82:0b31dbcd4769 1788 #define MTBDWT_MASK_MASK_MASK 0x1Fu
mbed_official 82:0b31dbcd4769 1789 #define MTBDWT_MASK_MASK_SHIFT 0
mbed_official 82:0b31dbcd4769 1790 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
mbed_official 82:0b31dbcd4769 1791 /* FCT Bit Fields */
mbed_official 82:0b31dbcd4769 1792 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
mbed_official 82:0b31dbcd4769 1793 #define MTBDWT_FCT_FUNCTION_SHIFT 0
mbed_official 82:0b31dbcd4769 1794 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
mbed_official 82:0b31dbcd4769 1795 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
mbed_official 82:0b31dbcd4769 1796 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
mbed_official 82:0b31dbcd4769 1797 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
mbed_official 82:0b31dbcd4769 1798 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
mbed_official 82:0b31dbcd4769 1799 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
mbed_official 82:0b31dbcd4769 1800 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
mbed_official 82:0b31dbcd4769 1801 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
mbed_official 82:0b31dbcd4769 1802 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
mbed_official 82:0b31dbcd4769 1803 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
mbed_official 82:0b31dbcd4769 1804 #define MTBDWT_FCT_MATCHED_SHIFT 24
mbed_official 82:0b31dbcd4769 1805 /* TBCTRL Bit Fields */
mbed_official 82:0b31dbcd4769 1806 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
mbed_official 82:0b31dbcd4769 1807 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
mbed_official 82:0b31dbcd4769 1808 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
mbed_official 82:0b31dbcd4769 1809 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
mbed_official 82:0b31dbcd4769 1810 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
mbed_official 82:0b31dbcd4769 1811 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
mbed_official 82:0b31dbcd4769 1812 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
mbed_official 82:0b31dbcd4769 1813 /* DEVICECFG Bit Fields */
mbed_official 82:0b31dbcd4769 1814 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1815 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
mbed_official 82:0b31dbcd4769 1816 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
mbed_official 82:0b31dbcd4769 1817 /* DEVICETYPID Bit Fields */
mbed_official 82:0b31dbcd4769 1818 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1819 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
mbed_official 82:0b31dbcd4769 1820 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
mbed_official 82:0b31dbcd4769 1821 /* PERIPHID Bit Fields */
mbed_official 82:0b31dbcd4769 1822 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1823 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
mbed_official 82:0b31dbcd4769 1824 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
mbed_official 82:0b31dbcd4769 1825 /* COMPID Bit Fields */
mbed_official 82:0b31dbcd4769 1826 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 1827 #define MTBDWT_COMPID_COMPID_SHIFT 0
mbed_official 82:0b31dbcd4769 1828 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
mbed_official 82:0b31dbcd4769 1829
mbed_official 82:0b31dbcd4769 1830 /**
mbed_official 82:0b31dbcd4769 1831 * @}
mbed_official 82:0b31dbcd4769 1832 */ /* end of group MTBDWT_Register_Masks */
mbed_official 82:0b31dbcd4769 1833
mbed_official 82:0b31dbcd4769 1834
mbed_official 82:0b31dbcd4769 1835 /* MTBDWT - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 1836 /** Peripheral MTBDWT base address */
mbed_official 82:0b31dbcd4769 1837 #define MTBDWT_BASE (0xF0001000u)
mbed_official 82:0b31dbcd4769 1838 /** Peripheral MTBDWT base pointer */
mbed_official 82:0b31dbcd4769 1839 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
mbed_official 82:0b31dbcd4769 1840 /** Array initializer of MTBDWT peripheral base pointers */
mbed_official 82:0b31dbcd4769 1841 #define MTBDWT_BASES { MTBDWT }
mbed_official 82:0b31dbcd4769 1842
mbed_official 82:0b31dbcd4769 1843 /**
mbed_official 82:0b31dbcd4769 1844 * @}
mbed_official 82:0b31dbcd4769 1845 */ /* end of group MTBDWT_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 1846
mbed_official 82:0b31dbcd4769 1847
mbed_official 82:0b31dbcd4769 1848 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1849 -- NV Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1850 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1851
mbed_official 82:0b31dbcd4769 1852 /**
mbed_official 82:0b31dbcd4769 1853 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1854 * @{
mbed_official 82:0b31dbcd4769 1855 */
mbed_official 82:0b31dbcd4769 1856
mbed_official 82:0b31dbcd4769 1857 /** NV - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 1858 typedef struct {
mbed_official 82:0b31dbcd4769 1859 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
mbed_official 82:0b31dbcd4769 1860 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
mbed_official 82:0b31dbcd4769 1861 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
mbed_official 82:0b31dbcd4769 1862 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
mbed_official 82:0b31dbcd4769 1863 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
mbed_official 82:0b31dbcd4769 1864 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
mbed_official 82:0b31dbcd4769 1865 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
mbed_official 82:0b31dbcd4769 1866 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
mbed_official 82:0b31dbcd4769 1867 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
mbed_official 82:0b31dbcd4769 1868 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
mbed_official 82:0b31dbcd4769 1869 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
mbed_official 82:0b31dbcd4769 1870 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
mbed_official 82:0b31dbcd4769 1871 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
mbed_official 82:0b31dbcd4769 1872 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
mbed_official 82:0b31dbcd4769 1873 } NV_Type;
mbed_official 82:0b31dbcd4769 1874
mbed_official 82:0b31dbcd4769 1875 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1876 -- NV Register Masks
mbed_official 82:0b31dbcd4769 1877 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1878
mbed_official 82:0b31dbcd4769 1879 /**
mbed_official 82:0b31dbcd4769 1880 * @addtogroup NV_Register_Masks NV Register Masks
mbed_official 82:0b31dbcd4769 1881 * @{
mbed_official 82:0b31dbcd4769 1882 */
mbed_official 82:0b31dbcd4769 1883
mbed_official 82:0b31dbcd4769 1884 /* BACKKEY3 Bit Fields */
mbed_official 82:0b31dbcd4769 1885 #define NV_BACKKEY3_KEY_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1886 #define NV_BACKKEY3_KEY_SHIFT 0
mbed_official 82:0b31dbcd4769 1887 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
mbed_official 82:0b31dbcd4769 1888 /* BACKKEY2 Bit Fields */
mbed_official 82:0b31dbcd4769 1889 #define NV_BACKKEY2_KEY_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1890 #define NV_BACKKEY2_KEY_SHIFT 0
mbed_official 82:0b31dbcd4769 1891 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
mbed_official 82:0b31dbcd4769 1892 /* BACKKEY1 Bit Fields */
mbed_official 82:0b31dbcd4769 1893 #define NV_BACKKEY1_KEY_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1894 #define NV_BACKKEY1_KEY_SHIFT 0
mbed_official 82:0b31dbcd4769 1895 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
mbed_official 82:0b31dbcd4769 1896 /* BACKKEY0 Bit Fields */
mbed_official 82:0b31dbcd4769 1897 #define NV_BACKKEY0_KEY_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1898 #define NV_BACKKEY0_KEY_SHIFT 0
mbed_official 82:0b31dbcd4769 1899 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
mbed_official 82:0b31dbcd4769 1900 /* BACKKEY7 Bit Fields */
mbed_official 82:0b31dbcd4769 1901 #define NV_BACKKEY7_KEY_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1902 #define NV_BACKKEY7_KEY_SHIFT 0
mbed_official 82:0b31dbcd4769 1903 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
mbed_official 82:0b31dbcd4769 1904 /* BACKKEY6 Bit Fields */
mbed_official 82:0b31dbcd4769 1905 #define NV_BACKKEY6_KEY_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1906 #define NV_BACKKEY6_KEY_SHIFT 0
mbed_official 82:0b31dbcd4769 1907 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
mbed_official 82:0b31dbcd4769 1908 /* BACKKEY5 Bit Fields */
mbed_official 82:0b31dbcd4769 1909 #define NV_BACKKEY5_KEY_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1910 #define NV_BACKKEY5_KEY_SHIFT 0
mbed_official 82:0b31dbcd4769 1911 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
mbed_official 82:0b31dbcd4769 1912 /* BACKKEY4 Bit Fields */
mbed_official 82:0b31dbcd4769 1913 #define NV_BACKKEY4_KEY_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1914 #define NV_BACKKEY4_KEY_SHIFT 0
mbed_official 82:0b31dbcd4769 1915 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
mbed_official 82:0b31dbcd4769 1916 /* FPROT3 Bit Fields */
mbed_official 82:0b31dbcd4769 1917 #define NV_FPROT3_PROT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1918 #define NV_FPROT3_PROT_SHIFT 0
mbed_official 82:0b31dbcd4769 1919 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
mbed_official 82:0b31dbcd4769 1920 /* FPROT2 Bit Fields */
mbed_official 82:0b31dbcd4769 1921 #define NV_FPROT2_PROT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1922 #define NV_FPROT2_PROT_SHIFT 0
mbed_official 82:0b31dbcd4769 1923 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
mbed_official 82:0b31dbcd4769 1924 /* FPROT1 Bit Fields */
mbed_official 82:0b31dbcd4769 1925 #define NV_FPROT1_PROT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1926 #define NV_FPROT1_PROT_SHIFT 0
mbed_official 82:0b31dbcd4769 1927 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
mbed_official 82:0b31dbcd4769 1928 /* FPROT0 Bit Fields */
mbed_official 82:0b31dbcd4769 1929 #define NV_FPROT0_PROT_MASK 0xFFu
mbed_official 82:0b31dbcd4769 1930 #define NV_FPROT0_PROT_SHIFT 0
mbed_official 82:0b31dbcd4769 1931 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
mbed_official 82:0b31dbcd4769 1932 /* FSEC Bit Fields */
mbed_official 82:0b31dbcd4769 1933 #define NV_FSEC_SEC_MASK 0x3u
mbed_official 82:0b31dbcd4769 1934 #define NV_FSEC_SEC_SHIFT 0
mbed_official 82:0b31dbcd4769 1935 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
mbed_official 82:0b31dbcd4769 1936 #define NV_FSEC_FSLACC_MASK 0xCu
mbed_official 82:0b31dbcd4769 1937 #define NV_FSEC_FSLACC_SHIFT 2
mbed_official 82:0b31dbcd4769 1938 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
mbed_official 82:0b31dbcd4769 1939 #define NV_FSEC_MEEN_MASK 0x30u
mbed_official 82:0b31dbcd4769 1940 #define NV_FSEC_MEEN_SHIFT 4
mbed_official 82:0b31dbcd4769 1941 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
mbed_official 82:0b31dbcd4769 1942 #define NV_FSEC_KEYEN_MASK 0xC0u
mbed_official 82:0b31dbcd4769 1943 #define NV_FSEC_KEYEN_SHIFT 6
mbed_official 82:0b31dbcd4769 1944 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
mbed_official 82:0b31dbcd4769 1945 /* FOPT Bit Fields */
mbed_official 82:0b31dbcd4769 1946 #define NV_FOPT_LPBOOT0_MASK 0x1u
mbed_official 82:0b31dbcd4769 1947 #define NV_FOPT_LPBOOT0_SHIFT 0
mbed_official 82:0b31dbcd4769 1948 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
mbed_official 82:0b31dbcd4769 1949 #define NV_FOPT_EZPORT_DIS_SHIFT 1
mbed_official 82:0b31dbcd4769 1950 #define NV_FOPT_NMI_DIS_MASK 0x4u
mbed_official 82:0b31dbcd4769 1951 #define NV_FOPT_NMI_DIS_SHIFT 2
mbed_official 82:0b31dbcd4769 1952 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
mbed_official 82:0b31dbcd4769 1953 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
mbed_official 82:0b31dbcd4769 1954 #define NV_FOPT_LPBOOT1_MASK 0x10u
mbed_official 82:0b31dbcd4769 1955 #define NV_FOPT_LPBOOT1_SHIFT 4
mbed_official 82:0b31dbcd4769 1956 #define NV_FOPT_FAST_INIT_MASK 0x20u
mbed_official 82:0b31dbcd4769 1957 #define NV_FOPT_FAST_INIT_SHIFT 5
mbed_official 82:0b31dbcd4769 1958
mbed_official 82:0b31dbcd4769 1959 /**
mbed_official 82:0b31dbcd4769 1960 * @}
mbed_official 82:0b31dbcd4769 1961 */ /* end of group NV_Register_Masks */
mbed_official 82:0b31dbcd4769 1962
mbed_official 82:0b31dbcd4769 1963
mbed_official 82:0b31dbcd4769 1964 /* NV - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 1965 /** Peripheral FTFA_FlashConfig base address */
mbed_official 82:0b31dbcd4769 1966 #define FTFA_FlashConfig_BASE (0x400u)
mbed_official 82:0b31dbcd4769 1967 /** Peripheral FTFA_FlashConfig base pointer */
mbed_official 82:0b31dbcd4769 1968 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
mbed_official 82:0b31dbcd4769 1969 /** Array initializer of NV peripheral base pointers */
mbed_official 82:0b31dbcd4769 1970 #define NV_BASES { FTFA_FlashConfig }
mbed_official 82:0b31dbcd4769 1971
mbed_official 82:0b31dbcd4769 1972 /**
mbed_official 82:0b31dbcd4769 1973 * @}
mbed_official 82:0b31dbcd4769 1974 */ /* end of group NV_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 1975
mbed_official 82:0b31dbcd4769 1976
mbed_official 82:0b31dbcd4769 1977 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1978 -- OSC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1979 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1980
mbed_official 82:0b31dbcd4769 1981 /**
mbed_official 82:0b31dbcd4769 1982 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 1983 * @{
mbed_official 82:0b31dbcd4769 1984 */
mbed_official 82:0b31dbcd4769 1985
mbed_official 82:0b31dbcd4769 1986 /** OSC - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 1987 typedef struct {
mbed_official 82:0b31dbcd4769 1988 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 1989 } OSC_Type;
mbed_official 82:0b31dbcd4769 1990
mbed_official 82:0b31dbcd4769 1991 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 1992 -- OSC Register Masks
mbed_official 82:0b31dbcd4769 1993 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 1994
mbed_official 82:0b31dbcd4769 1995 /**
mbed_official 82:0b31dbcd4769 1996 * @addtogroup OSC_Register_Masks OSC Register Masks
mbed_official 82:0b31dbcd4769 1997 * @{
mbed_official 82:0b31dbcd4769 1998 */
mbed_official 82:0b31dbcd4769 1999
mbed_official 82:0b31dbcd4769 2000 /* CR Bit Fields */
mbed_official 82:0b31dbcd4769 2001 #define OSC_CR_SC16P_MASK 0x1u
mbed_official 82:0b31dbcd4769 2002 #define OSC_CR_SC16P_SHIFT 0
mbed_official 82:0b31dbcd4769 2003 #define OSC_CR_SC8P_MASK 0x2u
mbed_official 82:0b31dbcd4769 2004 #define OSC_CR_SC8P_SHIFT 1
mbed_official 82:0b31dbcd4769 2005 #define OSC_CR_SC4P_MASK 0x4u
mbed_official 82:0b31dbcd4769 2006 #define OSC_CR_SC4P_SHIFT 2
mbed_official 82:0b31dbcd4769 2007 #define OSC_CR_SC2P_MASK 0x8u
mbed_official 82:0b31dbcd4769 2008 #define OSC_CR_SC2P_SHIFT 3
mbed_official 82:0b31dbcd4769 2009 #define OSC_CR_EREFSTEN_MASK 0x20u
mbed_official 82:0b31dbcd4769 2010 #define OSC_CR_EREFSTEN_SHIFT 5
mbed_official 82:0b31dbcd4769 2011 #define OSC_CR_ERCLKEN_MASK 0x80u
mbed_official 82:0b31dbcd4769 2012 #define OSC_CR_ERCLKEN_SHIFT 7
mbed_official 82:0b31dbcd4769 2013
mbed_official 82:0b31dbcd4769 2014 /**
mbed_official 82:0b31dbcd4769 2015 * @}
mbed_official 82:0b31dbcd4769 2016 */ /* end of group OSC_Register_Masks */
mbed_official 82:0b31dbcd4769 2017
mbed_official 82:0b31dbcd4769 2018
mbed_official 82:0b31dbcd4769 2019 /* OSC - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 2020 /** Peripheral OSC0 base address */
mbed_official 82:0b31dbcd4769 2021 #define OSC0_BASE (0x40065000u)
mbed_official 82:0b31dbcd4769 2022 /** Peripheral OSC0 base pointer */
mbed_official 82:0b31dbcd4769 2023 #define OSC0 ((OSC_Type *)OSC0_BASE)
mbed_official 82:0b31dbcd4769 2024 /** Array initializer of OSC peripheral base pointers */
mbed_official 82:0b31dbcd4769 2025 #define OSC_BASES { OSC0 }
mbed_official 82:0b31dbcd4769 2026
mbed_official 82:0b31dbcd4769 2027 /**
mbed_official 82:0b31dbcd4769 2028 * @}
mbed_official 82:0b31dbcd4769 2029 */ /* end of group OSC_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 2030
mbed_official 82:0b31dbcd4769 2031
mbed_official 82:0b31dbcd4769 2032 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2033 -- PIT Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2034 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2035
mbed_official 82:0b31dbcd4769 2036 /**
mbed_official 82:0b31dbcd4769 2037 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2038 * @{
mbed_official 82:0b31dbcd4769 2039 */
mbed_official 82:0b31dbcd4769 2040
mbed_official 82:0b31dbcd4769 2041 /** PIT - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 2042 typedef struct {
mbed_official 82:0b31dbcd4769 2043 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 2044 uint8_t RESERVED_0[220];
mbed_official 82:0b31dbcd4769 2045 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
mbed_official 82:0b31dbcd4769 2046 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
mbed_official 82:0b31dbcd4769 2047 uint8_t RESERVED_1[24];
mbed_official 82:0b31dbcd4769 2048 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 82:0b31dbcd4769 2049 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
mbed_official 82:0b31dbcd4769 2050 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
mbed_official 82:0b31dbcd4769 2051 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
mbed_official 82:0b31dbcd4769 2052 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
mbed_official 82:0b31dbcd4769 2053 } CHANNEL[2];
mbed_official 82:0b31dbcd4769 2054 } PIT_Type;
mbed_official 82:0b31dbcd4769 2055
mbed_official 82:0b31dbcd4769 2056 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2057 -- PIT Register Masks
mbed_official 82:0b31dbcd4769 2058 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2059
mbed_official 82:0b31dbcd4769 2060 /**
mbed_official 82:0b31dbcd4769 2061 * @addtogroup PIT_Register_Masks PIT Register Masks
mbed_official 82:0b31dbcd4769 2062 * @{
mbed_official 82:0b31dbcd4769 2063 */
mbed_official 82:0b31dbcd4769 2064
mbed_official 82:0b31dbcd4769 2065 /* MCR Bit Fields */
mbed_official 82:0b31dbcd4769 2066 #define PIT_MCR_FRZ_MASK 0x1u
mbed_official 82:0b31dbcd4769 2067 #define PIT_MCR_FRZ_SHIFT 0
mbed_official 82:0b31dbcd4769 2068 #define PIT_MCR_MDIS_MASK 0x2u
mbed_official 82:0b31dbcd4769 2069 #define PIT_MCR_MDIS_SHIFT 1
mbed_official 82:0b31dbcd4769 2070 /* LTMR64H Bit Fields */
mbed_official 82:0b31dbcd4769 2071 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2072 #define PIT_LTMR64H_LTH_SHIFT 0
mbed_official 82:0b31dbcd4769 2073 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
mbed_official 82:0b31dbcd4769 2074 /* LTMR64L Bit Fields */
mbed_official 82:0b31dbcd4769 2075 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2076 #define PIT_LTMR64L_LTL_SHIFT 0
mbed_official 82:0b31dbcd4769 2077 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
mbed_official 82:0b31dbcd4769 2078 /* LDVAL Bit Fields */
mbed_official 82:0b31dbcd4769 2079 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2080 #define PIT_LDVAL_TSV_SHIFT 0
mbed_official 82:0b31dbcd4769 2081 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
mbed_official 82:0b31dbcd4769 2082 /* CVAL Bit Fields */
mbed_official 82:0b31dbcd4769 2083 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2084 #define PIT_CVAL_TVL_SHIFT 0
mbed_official 82:0b31dbcd4769 2085 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
mbed_official 82:0b31dbcd4769 2086 /* TCTRL Bit Fields */
mbed_official 82:0b31dbcd4769 2087 #define PIT_TCTRL_TEN_MASK 0x1u
mbed_official 82:0b31dbcd4769 2088 #define PIT_TCTRL_TEN_SHIFT 0
mbed_official 82:0b31dbcd4769 2089 #define PIT_TCTRL_TIE_MASK 0x2u
mbed_official 82:0b31dbcd4769 2090 #define PIT_TCTRL_TIE_SHIFT 1
mbed_official 82:0b31dbcd4769 2091 #define PIT_TCTRL_CHN_MASK 0x4u
mbed_official 82:0b31dbcd4769 2092 #define PIT_TCTRL_CHN_SHIFT 2
mbed_official 82:0b31dbcd4769 2093 /* TFLG Bit Fields */
mbed_official 82:0b31dbcd4769 2094 #define PIT_TFLG_TIF_MASK 0x1u
mbed_official 82:0b31dbcd4769 2095 #define PIT_TFLG_TIF_SHIFT 0
mbed_official 82:0b31dbcd4769 2096
mbed_official 82:0b31dbcd4769 2097 /**
mbed_official 82:0b31dbcd4769 2098 * @}
mbed_official 82:0b31dbcd4769 2099 */ /* end of group PIT_Register_Masks */
mbed_official 82:0b31dbcd4769 2100
mbed_official 82:0b31dbcd4769 2101
mbed_official 82:0b31dbcd4769 2102 /* PIT - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 2103 /** Peripheral PIT base address */
mbed_official 82:0b31dbcd4769 2104 #define PIT_BASE (0x40037000u)
mbed_official 82:0b31dbcd4769 2105 /** Peripheral PIT base pointer */
mbed_official 82:0b31dbcd4769 2106 #define PIT ((PIT_Type *)PIT_BASE)
mbed_official 82:0b31dbcd4769 2107 /** Array initializer of PIT peripheral base pointers */
mbed_official 82:0b31dbcd4769 2108 #define PIT_BASES { PIT }
mbed_official 82:0b31dbcd4769 2109
mbed_official 82:0b31dbcd4769 2110 /**
mbed_official 82:0b31dbcd4769 2111 * @}
mbed_official 82:0b31dbcd4769 2112 */ /* end of group PIT_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 2113
mbed_official 82:0b31dbcd4769 2114
mbed_official 82:0b31dbcd4769 2115 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2116 -- PMC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2117 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2118
mbed_official 82:0b31dbcd4769 2119 /**
mbed_official 82:0b31dbcd4769 2120 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2121 * @{
mbed_official 82:0b31dbcd4769 2122 */
mbed_official 82:0b31dbcd4769 2123
mbed_official 82:0b31dbcd4769 2124 /** PMC - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 2125 typedef struct {
mbed_official 82:0b31dbcd4769 2126 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 2127 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
mbed_official 82:0b31dbcd4769 2128 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
mbed_official 82:0b31dbcd4769 2129 } PMC_Type;
mbed_official 82:0b31dbcd4769 2130
mbed_official 82:0b31dbcd4769 2131 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2132 -- PMC Register Masks
mbed_official 82:0b31dbcd4769 2133 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2134
mbed_official 82:0b31dbcd4769 2135 /**
mbed_official 82:0b31dbcd4769 2136 * @addtogroup PMC_Register_Masks PMC Register Masks
mbed_official 82:0b31dbcd4769 2137 * @{
mbed_official 82:0b31dbcd4769 2138 */
mbed_official 82:0b31dbcd4769 2139
mbed_official 82:0b31dbcd4769 2140 /* LVDSC1 Bit Fields */
mbed_official 82:0b31dbcd4769 2141 #define PMC_LVDSC1_LVDV_MASK 0x3u
mbed_official 82:0b31dbcd4769 2142 #define PMC_LVDSC1_LVDV_SHIFT 0
mbed_official 82:0b31dbcd4769 2143 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
mbed_official 82:0b31dbcd4769 2144 #define PMC_LVDSC1_LVDRE_MASK 0x10u
mbed_official 82:0b31dbcd4769 2145 #define PMC_LVDSC1_LVDRE_SHIFT 4
mbed_official 82:0b31dbcd4769 2146 #define PMC_LVDSC1_LVDIE_MASK 0x20u
mbed_official 82:0b31dbcd4769 2147 #define PMC_LVDSC1_LVDIE_SHIFT 5
mbed_official 82:0b31dbcd4769 2148 #define PMC_LVDSC1_LVDACK_MASK 0x40u
mbed_official 82:0b31dbcd4769 2149 #define PMC_LVDSC1_LVDACK_SHIFT 6
mbed_official 82:0b31dbcd4769 2150 #define PMC_LVDSC1_LVDF_MASK 0x80u
mbed_official 82:0b31dbcd4769 2151 #define PMC_LVDSC1_LVDF_SHIFT 7
mbed_official 82:0b31dbcd4769 2152 /* LVDSC2 Bit Fields */
mbed_official 82:0b31dbcd4769 2153 #define PMC_LVDSC2_LVWV_MASK 0x3u
mbed_official 82:0b31dbcd4769 2154 #define PMC_LVDSC2_LVWV_SHIFT 0
mbed_official 82:0b31dbcd4769 2155 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
mbed_official 82:0b31dbcd4769 2156 #define PMC_LVDSC2_LVWIE_MASK 0x20u
mbed_official 82:0b31dbcd4769 2157 #define PMC_LVDSC2_LVWIE_SHIFT 5
mbed_official 82:0b31dbcd4769 2158 #define PMC_LVDSC2_LVWACK_MASK 0x40u
mbed_official 82:0b31dbcd4769 2159 #define PMC_LVDSC2_LVWACK_SHIFT 6
mbed_official 82:0b31dbcd4769 2160 #define PMC_LVDSC2_LVWF_MASK 0x80u
mbed_official 82:0b31dbcd4769 2161 #define PMC_LVDSC2_LVWF_SHIFT 7
mbed_official 82:0b31dbcd4769 2162 /* REGSC Bit Fields */
mbed_official 82:0b31dbcd4769 2163 #define PMC_REGSC_BGBE_MASK 0x1u
mbed_official 82:0b31dbcd4769 2164 #define PMC_REGSC_BGBE_SHIFT 0
mbed_official 82:0b31dbcd4769 2165 #define PMC_REGSC_REGONS_MASK 0x4u
mbed_official 82:0b31dbcd4769 2166 #define PMC_REGSC_REGONS_SHIFT 2
mbed_official 82:0b31dbcd4769 2167 #define PMC_REGSC_ACKISO_MASK 0x8u
mbed_official 82:0b31dbcd4769 2168 #define PMC_REGSC_ACKISO_SHIFT 3
mbed_official 82:0b31dbcd4769 2169 #define PMC_REGSC_BGEN_MASK 0x10u
mbed_official 82:0b31dbcd4769 2170 #define PMC_REGSC_BGEN_SHIFT 4
mbed_official 82:0b31dbcd4769 2171
mbed_official 82:0b31dbcd4769 2172 /**
mbed_official 82:0b31dbcd4769 2173 * @}
mbed_official 82:0b31dbcd4769 2174 */ /* end of group PMC_Register_Masks */
mbed_official 82:0b31dbcd4769 2175
mbed_official 82:0b31dbcd4769 2176
mbed_official 82:0b31dbcd4769 2177 /* PMC - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 2178 /** Peripheral PMC base address */
mbed_official 82:0b31dbcd4769 2179 #define PMC_BASE (0x4007D000u)
mbed_official 82:0b31dbcd4769 2180 /** Peripheral PMC base pointer */
mbed_official 82:0b31dbcd4769 2181 #define PMC ((PMC_Type *)PMC_BASE)
mbed_official 82:0b31dbcd4769 2182 /** Array initializer of PMC peripheral base pointers */
mbed_official 82:0b31dbcd4769 2183 #define PMC_BASES { PMC }
mbed_official 82:0b31dbcd4769 2184
mbed_official 82:0b31dbcd4769 2185 /**
mbed_official 82:0b31dbcd4769 2186 * @}
mbed_official 82:0b31dbcd4769 2187 */ /* end of group PMC_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 2188
mbed_official 82:0b31dbcd4769 2189
mbed_official 82:0b31dbcd4769 2190 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2191 -- PORT Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2192 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2193
mbed_official 82:0b31dbcd4769 2194 /**
mbed_official 82:0b31dbcd4769 2195 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2196 * @{
mbed_official 82:0b31dbcd4769 2197 */
mbed_official 82:0b31dbcd4769 2198
mbed_official 82:0b31dbcd4769 2199 /** PORT - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 2200 typedef struct {
mbed_official 82:0b31dbcd4769 2201 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
mbed_official 82:0b31dbcd4769 2202 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
mbed_official 82:0b31dbcd4769 2203 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
mbed_official 82:0b31dbcd4769 2204 uint8_t RESERVED_0[24];
mbed_official 82:0b31dbcd4769 2205 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
mbed_official 82:0b31dbcd4769 2206 } PORT_Type;
mbed_official 82:0b31dbcd4769 2207
mbed_official 82:0b31dbcd4769 2208 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2209 -- PORT Register Masks
mbed_official 82:0b31dbcd4769 2210 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2211
mbed_official 82:0b31dbcd4769 2212 /**
mbed_official 82:0b31dbcd4769 2213 * @addtogroup PORT_Register_Masks PORT Register Masks
mbed_official 82:0b31dbcd4769 2214 * @{
mbed_official 82:0b31dbcd4769 2215 */
mbed_official 82:0b31dbcd4769 2216
mbed_official 82:0b31dbcd4769 2217 /* PCR Bit Fields */
mbed_official 82:0b31dbcd4769 2218 #define PORT_PCR_PS_MASK 0x1u
mbed_official 82:0b31dbcd4769 2219 #define PORT_PCR_PS_SHIFT 0
mbed_official 82:0b31dbcd4769 2220 #define PORT_PCR_PE_MASK 0x2u
mbed_official 82:0b31dbcd4769 2221 #define PORT_PCR_PE_SHIFT 1
mbed_official 82:0b31dbcd4769 2222 #define PORT_PCR_SRE_MASK 0x4u
mbed_official 82:0b31dbcd4769 2223 #define PORT_PCR_SRE_SHIFT 2
mbed_official 82:0b31dbcd4769 2224 #define PORT_PCR_PFE_MASK 0x10u
mbed_official 82:0b31dbcd4769 2225 #define PORT_PCR_PFE_SHIFT 4
mbed_official 82:0b31dbcd4769 2226 #define PORT_PCR_DSE_MASK 0x40u
mbed_official 82:0b31dbcd4769 2227 #define PORT_PCR_DSE_SHIFT 6
mbed_official 82:0b31dbcd4769 2228 #define PORT_PCR_MUX_MASK 0x700u
mbed_official 82:0b31dbcd4769 2229 #define PORT_PCR_MUX_SHIFT 8
mbed_official 82:0b31dbcd4769 2230 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
mbed_official 82:0b31dbcd4769 2231 #define PORT_PCR_IRQC_MASK 0xF0000u
mbed_official 82:0b31dbcd4769 2232 #define PORT_PCR_IRQC_SHIFT 16
mbed_official 82:0b31dbcd4769 2233 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
mbed_official 82:0b31dbcd4769 2234 #define PORT_PCR_ISF_MASK 0x1000000u
mbed_official 82:0b31dbcd4769 2235 #define PORT_PCR_ISF_SHIFT 24
mbed_official 82:0b31dbcd4769 2236 /* GPCLR Bit Fields */
mbed_official 82:0b31dbcd4769 2237 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 2238 #define PORT_GPCLR_GPWD_SHIFT 0
mbed_official 82:0b31dbcd4769 2239 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
mbed_official 82:0b31dbcd4769 2240 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
mbed_official 82:0b31dbcd4769 2241 #define PORT_GPCLR_GPWE_SHIFT 16
mbed_official 82:0b31dbcd4769 2242 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
mbed_official 82:0b31dbcd4769 2243 /* GPCHR Bit Fields */
mbed_official 82:0b31dbcd4769 2244 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 2245 #define PORT_GPCHR_GPWD_SHIFT 0
mbed_official 82:0b31dbcd4769 2246 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
mbed_official 82:0b31dbcd4769 2247 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
mbed_official 82:0b31dbcd4769 2248 #define PORT_GPCHR_GPWE_SHIFT 16
mbed_official 82:0b31dbcd4769 2249 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
mbed_official 82:0b31dbcd4769 2250 /* ISFR Bit Fields */
mbed_official 82:0b31dbcd4769 2251 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2252 #define PORT_ISFR_ISF_SHIFT 0
mbed_official 82:0b31dbcd4769 2253 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
mbed_official 82:0b31dbcd4769 2254
mbed_official 82:0b31dbcd4769 2255 /**
mbed_official 82:0b31dbcd4769 2256 * @}
mbed_official 82:0b31dbcd4769 2257 */ /* end of group PORT_Register_Masks */
mbed_official 82:0b31dbcd4769 2258
mbed_official 82:0b31dbcd4769 2259
mbed_official 82:0b31dbcd4769 2260 /* PORT - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 2261 /** Peripheral PORTA base address */
mbed_official 82:0b31dbcd4769 2262 #define PORTA_BASE (0x40049000u)
mbed_official 82:0b31dbcd4769 2263 /** Peripheral PORTA base pointer */
mbed_official 82:0b31dbcd4769 2264 #define PORTA ((PORT_Type *)PORTA_BASE)
mbed_official 82:0b31dbcd4769 2265 /** Peripheral PORTB base address */
mbed_official 82:0b31dbcd4769 2266 #define PORTB_BASE (0x4004A000u)
mbed_official 82:0b31dbcd4769 2267 /** Peripheral PORTB base pointer */
mbed_official 82:0b31dbcd4769 2268 #define PORTB ((PORT_Type *)PORTB_BASE)
mbed_official 82:0b31dbcd4769 2269 /** Array initializer of PORT peripheral base pointers */
mbed_official 82:0b31dbcd4769 2270 #define PORT_BASES { PORTA, PORTB }
mbed_official 82:0b31dbcd4769 2271
mbed_official 82:0b31dbcd4769 2272 /**
mbed_official 82:0b31dbcd4769 2273 * @}
mbed_official 82:0b31dbcd4769 2274 */ /* end of group PORT_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 2275
mbed_official 82:0b31dbcd4769 2276
mbed_official 82:0b31dbcd4769 2277 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2278 -- RCM Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2279 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2280
mbed_official 82:0b31dbcd4769 2281 /**
mbed_official 82:0b31dbcd4769 2282 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2283 * @{
mbed_official 82:0b31dbcd4769 2284 */
mbed_official 82:0b31dbcd4769 2285
mbed_official 82:0b31dbcd4769 2286 /** RCM - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 2287 typedef struct {
mbed_official 82:0b31dbcd4769 2288 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
mbed_official 82:0b31dbcd4769 2289 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
mbed_official 82:0b31dbcd4769 2290 uint8_t RESERVED_0[2];
mbed_official 82:0b31dbcd4769 2291 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 2292 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
mbed_official 82:0b31dbcd4769 2293 } RCM_Type;
mbed_official 82:0b31dbcd4769 2294
mbed_official 82:0b31dbcd4769 2295 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2296 -- RCM Register Masks
mbed_official 82:0b31dbcd4769 2297 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2298
mbed_official 82:0b31dbcd4769 2299 /**
mbed_official 82:0b31dbcd4769 2300 * @addtogroup RCM_Register_Masks RCM Register Masks
mbed_official 82:0b31dbcd4769 2301 * @{
mbed_official 82:0b31dbcd4769 2302 */
mbed_official 82:0b31dbcd4769 2303
mbed_official 82:0b31dbcd4769 2304 /* SRS0 Bit Fields */
mbed_official 82:0b31dbcd4769 2305 #define RCM_SRS0_WAKEUP_MASK 0x1u
mbed_official 82:0b31dbcd4769 2306 #define RCM_SRS0_WAKEUP_SHIFT 0
mbed_official 82:0b31dbcd4769 2307 #define RCM_SRS0_LVD_MASK 0x2u
mbed_official 82:0b31dbcd4769 2308 #define RCM_SRS0_LVD_SHIFT 1
mbed_official 82:0b31dbcd4769 2309 #define RCM_SRS0_LOC_MASK 0x4u
mbed_official 82:0b31dbcd4769 2310 #define RCM_SRS0_LOC_SHIFT 2
mbed_official 82:0b31dbcd4769 2311 #define RCM_SRS0_WDOG_MASK 0x20u
mbed_official 82:0b31dbcd4769 2312 #define RCM_SRS0_WDOG_SHIFT 5
mbed_official 82:0b31dbcd4769 2313 #define RCM_SRS0_PIN_MASK 0x40u
mbed_official 82:0b31dbcd4769 2314 #define RCM_SRS0_PIN_SHIFT 6
mbed_official 82:0b31dbcd4769 2315 #define RCM_SRS0_POR_MASK 0x80u
mbed_official 82:0b31dbcd4769 2316 #define RCM_SRS0_POR_SHIFT 7
mbed_official 82:0b31dbcd4769 2317 /* SRS1 Bit Fields */
mbed_official 82:0b31dbcd4769 2318 #define RCM_SRS1_LOCKUP_MASK 0x2u
mbed_official 82:0b31dbcd4769 2319 #define RCM_SRS1_LOCKUP_SHIFT 1
mbed_official 82:0b31dbcd4769 2320 #define RCM_SRS1_SW_MASK 0x4u
mbed_official 82:0b31dbcd4769 2321 #define RCM_SRS1_SW_SHIFT 2
mbed_official 82:0b31dbcd4769 2322 #define RCM_SRS1_MDM_AP_MASK 0x8u
mbed_official 82:0b31dbcd4769 2323 #define RCM_SRS1_MDM_AP_SHIFT 3
mbed_official 82:0b31dbcd4769 2324 #define RCM_SRS1_SACKERR_MASK 0x20u
mbed_official 82:0b31dbcd4769 2325 #define RCM_SRS1_SACKERR_SHIFT 5
mbed_official 82:0b31dbcd4769 2326 /* RPFC Bit Fields */
mbed_official 82:0b31dbcd4769 2327 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
mbed_official 82:0b31dbcd4769 2328 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
mbed_official 82:0b31dbcd4769 2329 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
mbed_official 82:0b31dbcd4769 2330 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
mbed_official 82:0b31dbcd4769 2331 #define RCM_RPFC_RSTFLTSS_SHIFT 2
mbed_official 82:0b31dbcd4769 2332 /* RPFW Bit Fields */
mbed_official 82:0b31dbcd4769 2333 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
mbed_official 82:0b31dbcd4769 2334 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
mbed_official 82:0b31dbcd4769 2335 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
mbed_official 82:0b31dbcd4769 2336
mbed_official 82:0b31dbcd4769 2337 /**
mbed_official 82:0b31dbcd4769 2338 * @}
mbed_official 82:0b31dbcd4769 2339 */ /* end of group RCM_Register_Masks */
mbed_official 82:0b31dbcd4769 2340
mbed_official 82:0b31dbcd4769 2341
mbed_official 82:0b31dbcd4769 2342 /* RCM - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 2343 /** Peripheral RCM base address */
mbed_official 82:0b31dbcd4769 2344 #define RCM_BASE (0x4007F000u)
mbed_official 82:0b31dbcd4769 2345 /** Peripheral RCM base pointer */
mbed_official 82:0b31dbcd4769 2346 #define RCM ((RCM_Type *)RCM_BASE)
mbed_official 82:0b31dbcd4769 2347 /** Array initializer of RCM peripheral base pointers */
mbed_official 82:0b31dbcd4769 2348 #define RCM_BASES { RCM }
mbed_official 82:0b31dbcd4769 2349
mbed_official 82:0b31dbcd4769 2350 /**
mbed_official 82:0b31dbcd4769 2351 * @}
mbed_official 82:0b31dbcd4769 2352 */ /* end of group RCM_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 2353
mbed_official 82:0b31dbcd4769 2354
mbed_official 82:0b31dbcd4769 2355 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2356 -- ROM Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2357 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2358
mbed_official 82:0b31dbcd4769 2359 /**
mbed_official 82:0b31dbcd4769 2360 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2361 * @{
mbed_official 82:0b31dbcd4769 2362 */
mbed_official 82:0b31dbcd4769 2363
mbed_official 82:0b31dbcd4769 2364 /** ROM - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 2365 typedef struct {
mbed_official 82:0b31dbcd4769 2366 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
mbed_official 82:0b31dbcd4769 2367 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
mbed_official 82:0b31dbcd4769 2368 uint8_t RESERVED_0[4028];
mbed_official 82:0b31dbcd4769 2369 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
mbed_official 82:0b31dbcd4769 2370 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
mbed_official 82:0b31dbcd4769 2371 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
mbed_official 82:0b31dbcd4769 2372 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
mbed_official 82:0b31dbcd4769 2373 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
mbed_official 82:0b31dbcd4769 2374 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
mbed_official 82:0b31dbcd4769 2375 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
mbed_official 82:0b31dbcd4769 2376 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
mbed_official 82:0b31dbcd4769 2377 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
mbed_official 82:0b31dbcd4769 2378 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 82:0b31dbcd4769 2379 } ROM_Type;
mbed_official 82:0b31dbcd4769 2380
mbed_official 82:0b31dbcd4769 2381 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2382 -- ROM Register Masks
mbed_official 82:0b31dbcd4769 2383 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2384
mbed_official 82:0b31dbcd4769 2385 /**
mbed_official 82:0b31dbcd4769 2386 * @addtogroup ROM_Register_Masks ROM Register Masks
mbed_official 82:0b31dbcd4769 2387 * @{
mbed_official 82:0b31dbcd4769 2388 */
mbed_official 82:0b31dbcd4769 2389
mbed_official 82:0b31dbcd4769 2390 /* ENTRY Bit Fields */
mbed_official 82:0b31dbcd4769 2391 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2392 #define ROM_ENTRY_ENTRY_SHIFT 0
mbed_official 82:0b31dbcd4769 2393 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
mbed_official 82:0b31dbcd4769 2394 /* TABLEMARK Bit Fields */
mbed_official 82:0b31dbcd4769 2395 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2396 #define ROM_TABLEMARK_MARK_SHIFT 0
mbed_official 82:0b31dbcd4769 2397 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
mbed_official 82:0b31dbcd4769 2398 /* SYSACCESS Bit Fields */
mbed_official 82:0b31dbcd4769 2399 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2400 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
mbed_official 82:0b31dbcd4769 2401 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
mbed_official 82:0b31dbcd4769 2402 /* PERIPHID4 Bit Fields */
mbed_official 82:0b31dbcd4769 2403 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2404 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
mbed_official 82:0b31dbcd4769 2405 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
mbed_official 82:0b31dbcd4769 2406 /* PERIPHID5 Bit Fields */
mbed_official 82:0b31dbcd4769 2407 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2408 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
mbed_official 82:0b31dbcd4769 2409 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
mbed_official 82:0b31dbcd4769 2410 /* PERIPHID6 Bit Fields */
mbed_official 82:0b31dbcd4769 2411 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2412 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
mbed_official 82:0b31dbcd4769 2413 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
mbed_official 82:0b31dbcd4769 2414 /* PERIPHID7 Bit Fields */
mbed_official 82:0b31dbcd4769 2415 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2416 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
mbed_official 82:0b31dbcd4769 2417 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
mbed_official 82:0b31dbcd4769 2418 /* PERIPHID0 Bit Fields */
mbed_official 82:0b31dbcd4769 2419 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2420 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
mbed_official 82:0b31dbcd4769 2421 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
mbed_official 82:0b31dbcd4769 2422 /* PERIPHID1 Bit Fields */
mbed_official 82:0b31dbcd4769 2423 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2424 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
mbed_official 82:0b31dbcd4769 2425 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
mbed_official 82:0b31dbcd4769 2426 /* PERIPHID2 Bit Fields */
mbed_official 82:0b31dbcd4769 2427 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2428 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
mbed_official 82:0b31dbcd4769 2429 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
mbed_official 82:0b31dbcd4769 2430 /* PERIPHID3 Bit Fields */
mbed_official 82:0b31dbcd4769 2431 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2432 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
mbed_official 82:0b31dbcd4769 2433 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
mbed_official 82:0b31dbcd4769 2434 /* COMPID Bit Fields */
mbed_official 82:0b31dbcd4769 2435 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2436 #define ROM_COMPID_COMPID_SHIFT 0
mbed_official 82:0b31dbcd4769 2437 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
mbed_official 82:0b31dbcd4769 2438
mbed_official 82:0b31dbcd4769 2439 /**
mbed_official 82:0b31dbcd4769 2440 * @}
mbed_official 82:0b31dbcd4769 2441 */ /* end of group ROM_Register_Masks */
mbed_official 82:0b31dbcd4769 2442
mbed_official 82:0b31dbcd4769 2443
mbed_official 82:0b31dbcd4769 2444 /* ROM - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 2445 /** Peripheral ROM base address */
mbed_official 82:0b31dbcd4769 2446 #define ROM_BASE (0xF0002000u)
mbed_official 82:0b31dbcd4769 2447 /** Peripheral ROM base pointer */
mbed_official 82:0b31dbcd4769 2448 #define ROM ((ROM_Type *)ROM_BASE)
mbed_official 82:0b31dbcd4769 2449 /** Array initializer of ROM peripheral base pointers */
mbed_official 82:0b31dbcd4769 2450 #define ROM_BASES { ROM }
mbed_official 82:0b31dbcd4769 2451
mbed_official 82:0b31dbcd4769 2452 /**
mbed_official 82:0b31dbcd4769 2453 * @}
mbed_official 82:0b31dbcd4769 2454 */ /* end of group ROM_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 2455
mbed_official 82:0b31dbcd4769 2456
mbed_official 82:0b31dbcd4769 2457 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2458 -- RTC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2459 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2460
mbed_official 82:0b31dbcd4769 2461 /**
mbed_official 82:0b31dbcd4769 2462 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2463 * @{
mbed_official 82:0b31dbcd4769 2464 */
mbed_official 82:0b31dbcd4769 2465
mbed_official 82:0b31dbcd4769 2466 /** RTC - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 2467 typedef struct {
mbed_official 82:0b31dbcd4769 2468 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 2469 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 2470 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
mbed_official 82:0b31dbcd4769 2471 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
mbed_official 82:0b31dbcd4769 2472 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
mbed_official 82:0b31dbcd4769 2473 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
mbed_official 82:0b31dbcd4769 2474 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
mbed_official 82:0b31dbcd4769 2475 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
mbed_official 82:0b31dbcd4769 2476 } RTC_Type;
mbed_official 82:0b31dbcd4769 2477
mbed_official 82:0b31dbcd4769 2478 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2479 -- RTC Register Masks
mbed_official 82:0b31dbcd4769 2480 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2481
mbed_official 82:0b31dbcd4769 2482 /**
mbed_official 82:0b31dbcd4769 2483 * @addtogroup RTC_Register_Masks RTC Register Masks
mbed_official 82:0b31dbcd4769 2484 * @{
mbed_official 82:0b31dbcd4769 2485 */
mbed_official 82:0b31dbcd4769 2486
mbed_official 82:0b31dbcd4769 2487 /* TSR Bit Fields */
mbed_official 82:0b31dbcd4769 2488 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2489 #define RTC_TSR_TSR_SHIFT 0
mbed_official 82:0b31dbcd4769 2490 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
mbed_official 82:0b31dbcd4769 2491 /* TPR Bit Fields */
mbed_official 82:0b31dbcd4769 2492 #define RTC_TPR_TPR_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 2493 #define RTC_TPR_TPR_SHIFT 0
mbed_official 82:0b31dbcd4769 2494 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
mbed_official 82:0b31dbcd4769 2495 /* TAR Bit Fields */
mbed_official 82:0b31dbcd4769 2496 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2497 #define RTC_TAR_TAR_SHIFT 0
mbed_official 82:0b31dbcd4769 2498 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
mbed_official 82:0b31dbcd4769 2499 /* TCR Bit Fields */
mbed_official 82:0b31dbcd4769 2500 #define RTC_TCR_TCR_MASK 0xFFu
mbed_official 82:0b31dbcd4769 2501 #define RTC_TCR_TCR_SHIFT 0
mbed_official 82:0b31dbcd4769 2502 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
mbed_official 82:0b31dbcd4769 2503 #define RTC_TCR_CIR_MASK 0xFF00u
mbed_official 82:0b31dbcd4769 2504 #define RTC_TCR_CIR_SHIFT 8
mbed_official 82:0b31dbcd4769 2505 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
mbed_official 82:0b31dbcd4769 2506 #define RTC_TCR_TCV_MASK 0xFF0000u
mbed_official 82:0b31dbcd4769 2507 #define RTC_TCR_TCV_SHIFT 16
mbed_official 82:0b31dbcd4769 2508 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
mbed_official 82:0b31dbcd4769 2509 #define RTC_TCR_CIC_MASK 0xFF000000u
mbed_official 82:0b31dbcd4769 2510 #define RTC_TCR_CIC_SHIFT 24
mbed_official 82:0b31dbcd4769 2511 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
mbed_official 82:0b31dbcd4769 2512 /* CR Bit Fields */
mbed_official 82:0b31dbcd4769 2513 #define RTC_CR_SWR_MASK 0x1u
mbed_official 82:0b31dbcd4769 2514 #define RTC_CR_SWR_SHIFT 0
mbed_official 82:0b31dbcd4769 2515 #define RTC_CR_WPE_MASK 0x2u
mbed_official 82:0b31dbcd4769 2516 #define RTC_CR_WPE_SHIFT 1
mbed_official 82:0b31dbcd4769 2517 #define RTC_CR_SUP_MASK 0x4u
mbed_official 82:0b31dbcd4769 2518 #define RTC_CR_SUP_SHIFT 2
mbed_official 82:0b31dbcd4769 2519 #define RTC_CR_UM_MASK 0x8u
mbed_official 82:0b31dbcd4769 2520 #define RTC_CR_UM_SHIFT 3
mbed_official 82:0b31dbcd4769 2521 #define RTC_CR_OSCE_MASK 0x100u
mbed_official 82:0b31dbcd4769 2522 #define RTC_CR_OSCE_SHIFT 8
mbed_official 82:0b31dbcd4769 2523 #define RTC_CR_CLKO_MASK 0x200u
mbed_official 82:0b31dbcd4769 2524 #define RTC_CR_CLKO_SHIFT 9
mbed_official 82:0b31dbcd4769 2525 #define RTC_CR_SC16P_MASK 0x400u
mbed_official 82:0b31dbcd4769 2526 #define RTC_CR_SC16P_SHIFT 10
mbed_official 82:0b31dbcd4769 2527 #define RTC_CR_SC8P_MASK 0x800u
mbed_official 82:0b31dbcd4769 2528 #define RTC_CR_SC8P_SHIFT 11
mbed_official 82:0b31dbcd4769 2529 #define RTC_CR_SC4P_MASK 0x1000u
mbed_official 82:0b31dbcd4769 2530 #define RTC_CR_SC4P_SHIFT 12
mbed_official 82:0b31dbcd4769 2531 #define RTC_CR_SC2P_MASK 0x2000u
mbed_official 82:0b31dbcd4769 2532 #define RTC_CR_SC2P_SHIFT 13
mbed_official 82:0b31dbcd4769 2533 /* SR Bit Fields */
mbed_official 82:0b31dbcd4769 2534 #define RTC_SR_TIF_MASK 0x1u
mbed_official 82:0b31dbcd4769 2535 #define RTC_SR_TIF_SHIFT 0
mbed_official 82:0b31dbcd4769 2536 #define RTC_SR_TOF_MASK 0x2u
mbed_official 82:0b31dbcd4769 2537 #define RTC_SR_TOF_SHIFT 1
mbed_official 82:0b31dbcd4769 2538 #define RTC_SR_TAF_MASK 0x4u
mbed_official 82:0b31dbcd4769 2539 #define RTC_SR_TAF_SHIFT 2
mbed_official 82:0b31dbcd4769 2540 #define RTC_SR_TCE_MASK 0x10u
mbed_official 82:0b31dbcd4769 2541 #define RTC_SR_TCE_SHIFT 4
mbed_official 82:0b31dbcd4769 2542 /* LR Bit Fields */
mbed_official 82:0b31dbcd4769 2543 #define RTC_LR_TCL_MASK 0x8u
mbed_official 82:0b31dbcd4769 2544 #define RTC_LR_TCL_SHIFT 3
mbed_official 82:0b31dbcd4769 2545 #define RTC_LR_CRL_MASK 0x10u
mbed_official 82:0b31dbcd4769 2546 #define RTC_LR_CRL_SHIFT 4
mbed_official 82:0b31dbcd4769 2547 #define RTC_LR_SRL_MASK 0x20u
mbed_official 82:0b31dbcd4769 2548 #define RTC_LR_SRL_SHIFT 5
mbed_official 82:0b31dbcd4769 2549 #define RTC_LR_LRL_MASK 0x40u
mbed_official 82:0b31dbcd4769 2550 #define RTC_LR_LRL_SHIFT 6
mbed_official 82:0b31dbcd4769 2551 /* IER Bit Fields */
mbed_official 82:0b31dbcd4769 2552 #define RTC_IER_TIIE_MASK 0x1u
mbed_official 82:0b31dbcd4769 2553 #define RTC_IER_TIIE_SHIFT 0
mbed_official 82:0b31dbcd4769 2554 #define RTC_IER_TOIE_MASK 0x2u
mbed_official 82:0b31dbcd4769 2555 #define RTC_IER_TOIE_SHIFT 1
mbed_official 82:0b31dbcd4769 2556 #define RTC_IER_TAIE_MASK 0x4u
mbed_official 82:0b31dbcd4769 2557 #define RTC_IER_TAIE_SHIFT 2
mbed_official 82:0b31dbcd4769 2558 #define RTC_IER_TSIE_MASK 0x10u
mbed_official 82:0b31dbcd4769 2559 #define RTC_IER_TSIE_SHIFT 4
mbed_official 82:0b31dbcd4769 2560 #define RTC_IER_WPON_MASK 0x80u
mbed_official 82:0b31dbcd4769 2561 #define RTC_IER_WPON_SHIFT 7
mbed_official 82:0b31dbcd4769 2562
mbed_official 82:0b31dbcd4769 2563 /**
mbed_official 82:0b31dbcd4769 2564 * @}
mbed_official 82:0b31dbcd4769 2565 */ /* end of group RTC_Register_Masks */
mbed_official 82:0b31dbcd4769 2566
mbed_official 82:0b31dbcd4769 2567
mbed_official 82:0b31dbcd4769 2568 /* RTC - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 2569 /** Peripheral RTC base address */
mbed_official 82:0b31dbcd4769 2570 #define RTC_BASE (0x4003D000u)
mbed_official 82:0b31dbcd4769 2571 /** Peripheral RTC base pointer */
mbed_official 82:0b31dbcd4769 2572 #define RTC ((RTC_Type *)RTC_BASE)
mbed_official 82:0b31dbcd4769 2573 /** Array initializer of RTC peripheral base pointers */
mbed_official 82:0b31dbcd4769 2574 #define RTC_BASES { RTC }
mbed_official 82:0b31dbcd4769 2575
mbed_official 82:0b31dbcd4769 2576 /**
mbed_official 82:0b31dbcd4769 2577 * @}
mbed_official 82:0b31dbcd4769 2578 */ /* end of group RTC_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 2579
mbed_official 82:0b31dbcd4769 2580
mbed_official 82:0b31dbcd4769 2581 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2582 -- SIM Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2583 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2584
mbed_official 82:0b31dbcd4769 2585 /**
mbed_official 82:0b31dbcd4769 2586 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2587 * @{
mbed_official 82:0b31dbcd4769 2588 */
mbed_official 82:0b31dbcd4769 2589
mbed_official 82:0b31dbcd4769 2590 /** SIM - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 2591 typedef struct {
mbed_official 82:0b31dbcd4769 2592 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
mbed_official 82:0b31dbcd4769 2593 __I uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 2594 uint8_t RESERVED_0[4092];
mbed_official 82:0b31dbcd4769 2595 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
mbed_official 82:0b31dbcd4769 2596 uint8_t RESERVED_1[4];
mbed_official 82:0b31dbcd4769 2597 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
mbed_official 82:0b31dbcd4769 2598 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
mbed_official 82:0b31dbcd4769 2599 uint8_t RESERVED_2[4];
mbed_official 82:0b31dbcd4769 2600 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
mbed_official 82:0b31dbcd4769 2601 uint8_t RESERVED_3[8];
mbed_official 82:0b31dbcd4769 2602 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
mbed_official 82:0b31dbcd4769 2603 uint8_t RESERVED_4[12];
mbed_official 82:0b31dbcd4769 2604 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
mbed_official 82:0b31dbcd4769 2605 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
mbed_official 82:0b31dbcd4769 2606 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
mbed_official 82:0b31dbcd4769 2607 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
mbed_official 82:0b31dbcd4769 2608 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
mbed_official 82:0b31dbcd4769 2609 uint8_t RESERVED_5[4];
mbed_official 82:0b31dbcd4769 2610 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
mbed_official 82:0b31dbcd4769 2611 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
mbed_official 82:0b31dbcd4769 2612 uint8_t RESERVED_6[4];
mbed_official 82:0b31dbcd4769 2613 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
mbed_official 82:0b31dbcd4769 2614 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
mbed_official 82:0b31dbcd4769 2615 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
mbed_official 82:0b31dbcd4769 2616 uint8_t RESERVED_7[156];
mbed_official 82:0b31dbcd4769 2617 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
mbed_official 82:0b31dbcd4769 2618 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
mbed_official 82:0b31dbcd4769 2619 } SIM_Type;
mbed_official 82:0b31dbcd4769 2620
mbed_official 82:0b31dbcd4769 2621 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2622 -- SIM Register Masks
mbed_official 82:0b31dbcd4769 2623 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2624
mbed_official 82:0b31dbcd4769 2625 /**
mbed_official 82:0b31dbcd4769 2626 * @addtogroup SIM_Register_Masks SIM Register Masks
mbed_official 82:0b31dbcd4769 2627 * @{
mbed_official 82:0b31dbcd4769 2628 */
mbed_official 82:0b31dbcd4769 2629
mbed_official 82:0b31dbcd4769 2630 /* SOPT1 Bit Fields */
mbed_official 82:0b31dbcd4769 2631 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
mbed_official 82:0b31dbcd4769 2632 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
mbed_official 82:0b31dbcd4769 2633 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
mbed_official 82:0b31dbcd4769 2634 /* SOPT2 Bit Fields */
mbed_official 82:0b31dbcd4769 2635 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
mbed_official 82:0b31dbcd4769 2636 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
mbed_official 82:0b31dbcd4769 2637 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
mbed_official 82:0b31dbcd4769 2638 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
mbed_official 82:0b31dbcd4769 2639 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
mbed_official 82:0b31dbcd4769 2640 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
mbed_official 82:0b31dbcd4769 2641 #define SIM_SOPT2_TPMSRC_SHIFT 24
mbed_official 82:0b31dbcd4769 2642 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
mbed_official 82:0b31dbcd4769 2643 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u
mbed_official 82:0b31dbcd4769 2644 #define SIM_SOPT2_UART0SRC_SHIFT 26
mbed_official 82:0b31dbcd4769 2645 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
mbed_official 82:0b31dbcd4769 2646 /* SOPT4 Bit Fields */
mbed_official 82:0b31dbcd4769 2647 #define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
mbed_official 82:0b31dbcd4769 2648 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
mbed_official 82:0b31dbcd4769 2649 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
mbed_official 82:0b31dbcd4769 2650 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
mbed_official 82:0b31dbcd4769 2651 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
mbed_official 82:0b31dbcd4769 2652 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
mbed_official 82:0b31dbcd4769 2653 /* SOPT5 Bit Fields */
mbed_official 82:0b31dbcd4769 2654 #define SIM_SOPT5_UART0TXSRC_MASK 0x1u
mbed_official 82:0b31dbcd4769 2655 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
mbed_official 82:0b31dbcd4769 2656 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u
mbed_official 82:0b31dbcd4769 2657 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
mbed_official 82:0b31dbcd4769 2658 #define SIM_SOPT5_UART0ODE_MASK 0x10000u
mbed_official 82:0b31dbcd4769 2659 #define SIM_SOPT5_UART0ODE_SHIFT 16
mbed_official 82:0b31dbcd4769 2660 /* SOPT7 Bit Fields */
mbed_official 82:0b31dbcd4769 2661 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
mbed_official 82:0b31dbcd4769 2662 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
mbed_official 82:0b31dbcd4769 2663 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
mbed_official 82:0b31dbcd4769 2664 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
mbed_official 82:0b31dbcd4769 2665 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
mbed_official 82:0b31dbcd4769 2666 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
mbed_official 82:0b31dbcd4769 2667 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
mbed_official 82:0b31dbcd4769 2668 /* SDID Bit Fields */
mbed_official 82:0b31dbcd4769 2669 #define SIM_SDID_PINID_MASK 0xFu
mbed_official 82:0b31dbcd4769 2670 #define SIM_SDID_PINID_SHIFT 0
mbed_official 82:0b31dbcd4769 2671 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
mbed_official 82:0b31dbcd4769 2672 #define SIM_SDID_DIEID_MASK 0xF80u
mbed_official 82:0b31dbcd4769 2673 #define SIM_SDID_DIEID_SHIFT 7
mbed_official 82:0b31dbcd4769 2674 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
mbed_official 82:0b31dbcd4769 2675 #define SIM_SDID_REVID_MASK 0xF000u
mbed_official 82:0b31dbcd4769 2676 #define SIM_SDID_REVID_SHIFT 12
mbed_official 82:0b31dbcd4769 2677 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
mbed_official 82:0b31dbcd4769 2678 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
mbed_official 82:0b31dbcd4769 2679 #define SIM_SDID_SRAMSIZE_SHIFT 16
mbed_official 82:0b31dbcd4769 2680 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
mbed_official 82:0b31dbcd4769 2681 #define SIM_SDID_SERIESID_MASK 0xF00000u
mbed_official 82:0b31dbcd4769 2682 #define SIM_SDID_SERIESID_SHIFT 20
mbed_official 82:0b31dbcd4769 2683 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
mbed_official 82:0b31dbcd4769 2684 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
mbed_official 82:0b31dbcd4769 2685 #define SIM_SDID_SUBFAMID_SHIFT 24
mbed_official 82:0b31dbcd4769 2686 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
mbed_official 82:0b31dbcd4769 2687 #define SIM_SDID_FAMID_MASK 0xF0000000u
mbed_official 82:0b31dbcd4769 2688 #define SIM_SDID_FAMID_SHIFT 28
mbed_official 82:0b31dbcd4769 2689 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
mbed_official 82:0b31dbcd4769 2690 /* SCGC4 Bit Fields */
mbed_official 82:0b31dbcd4769 2691 #define SIM_SCGC4_I2C0_MASK 0x40u
mbed_official 82:0b31dbcd4769 2692 #define SIM_SCGC4_I2C0_SHIFT 6
mbed_official 82:0b31dbcd4769 2693 #define SIM_SCGC4_UART0_MASK 0x400u
mbed_official 82:0b31dbcd4769 2694 #define SIM_SCGC4_UART0_SHIFT 10
mbed_official 82:0b31dbcd4769 2695 #define SIM_SCGC4_CMP_MASK 0x80000u
mbed_official 82:0b31dbcd4769 2696 #define SIM_SCGC4_CMP_SHIFT 19
mbed_official 82:0b31dbcd4769 2697 #define SIM_SCGC4_SPI0_MASK 0x400000u
mbed_official 82:0b31dbcd4769 2698 #define SIM_SCGC4_SPI0_SHIFT 22
mbed_official 82:0b31dbcd4769 2699 /* SCGC5 Bit Fields */
mbed_official 82:0b31dbcd4769 2700 #define SIM_SCGC5_LPTMR_MASK 0x1u
mbed_official 82:0b31dbcd4769 2701 #define SIM_SCGC5_LPTMR_SHIFT 0
mbed_official 82:0b31dbcd4769 2702 #define SIM_SCGC5_TSI_MASK 0x20u
mbed_official 82:0b31dbcd4769 2703 #define SIM_SCGC5_TSI_SHIFT 5
mbed_official 82:0b31dbcd4769 2704 #define SIM_SCGC5_PORTA_MASK 0x200u
mbed_official 82:0b31dbcd4769 2705 #define SIM_SCGC5_PORTA_SHIFT 9
mbed_official 82:0b31dbcd4769 2706 #define SIM_SCGC5_PORTB_MASK 0x400u
mbed_official 82:0b31dbcd4769 2707 #define SIM_SCGC5_PORTB_SHIFT 10
mbed_official 82:0b31dbcd4769 2708 /* SCGC6 Bit Fields */
mbed_official 82:0b31dbcd4769 2709 #define SIM_SCGC6_FTF_MASK 0x1u
mbed_official 82:0b31dbcd4769 2710 #define SIM_SCGC6_FTF_SHIFT 0
mbed_official 82:0b31dbcd4769 2711 #define SIM_SCGC6_DMAMUX_MASK 0x2u
mbed_official 82:0b31dbcd4769 2712 #define SIM_SCGC6_DMAMUX_SHIFT 1
mbed_official 82:0b31dbcd4769 2713 #define SIM_SCGC6_PIT_MASK 0x800000u
mbed_official 82:0b31dbcd4769 2714 #define SIM_SCGC6_PIT_SHIFT 23
mbed_official 82:0b31dbcd4769 2715 #define SIM_SCGC6_TPM0_MASK 0x1000000u
mbed_official 82:0b31dbcd4769 2716 #define SIM_SCGC6_TPM0_SHIFT 24
mbed_official 82:0b31dbcd4769 2717 #define SIM_SCGC6_TPM1_MASK 0x2000000u
mbed_official 82:0b31dbcd4769 2718 #define SIM_SCGC6_TPM1_SHIFT 25
mbed_official 82:0b31dbcd4769 2719 #define SIM_SCGC6_ADC0_MASK 0x8000000u
mbed_official 82:0b31dbcd4769 2720 #define SIM_SCGC6_ADC0_SHIFT 27
mbed_official 82:0b31dbcd4769 2721 #define SIM_SCGC6_RTC_MASK 0x20000000u
mbed_official 82:0b31dbcd4769 2722 #define SIM_SCGC6_RTC_SHIFT 29
mbed_official 82:0b31dbcd4769 2723 #define SIM_SCGC6_DAC0_MASK 0x80000000u
mbed_official 82:0b31dbcd4769 2724 #define SIM_SCGC6_DAC0_SHIFT 31
mbed_official 82:0b31dbcd4769 2725 /* SCGC7 Bit Fields */
mbed_official 82:0b31dbcd4769 2726 #define SIM_SCGC7_DMA_MASK 0x100u
mbed_official 82:0b31dbcd4769 2727 #define SIM_SCGC7_DMA_SHIFT 8
mbed_official 82:0b31dbcd4769 2728 /* CLKDIV1 Bit Fields */
mbed_official 82:0b31dbcd4769 2729 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
mbed_official 82:0b31dbcd4769 2730 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
mbed_official 82:0b31dbcd4769 2731 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
mbed_official 82:0b31dbcd4769 2732 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
mbed_official 82:0b31dbcd4769 2733 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
mbed_official 82:0b31dbcd4769 2734 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
mbed_official 82:0b31dbcd4769 2735 /* FCFG1 Bit Fields */
mbed_official 82:0b31dbcd4769 2736 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
mbed_official 82:0b31dbcd4769 2737 #define SIM_FCFG1_FLASHDIS_SHIFT 0
mbed_official 82:0b31dbcd4769 2738 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
mbed_official 82:0b31dbcd4769 2739 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
mbed_official 82:0b31dbcd4769 2740 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
mbed_official 82:0b31dbcd4769 2741 #define SIM_FCFG1_PFSIZE_SHIFT 24
mbed_official 82:0b31dbcd4769 2742 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
mbed_official 82:0b31dbcd4769 2743 /* FCFG2 Bit Fields */
mbed_official 82:0b31dbcd4769 2744 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
mbed_official 82:0b31dbcd4769 2745 #define SIM_FCFG2_MAXADDR0_SHIFT 24
mbed_official 82:0b31dbcd4769 2746 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
mbed_official 82:0b31dbcd4769 2747 /* UIDMH Bit Fields */
mbed_official 82:0b31dbcd4769 2748 #define SIM_UIDMH_UID_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 2749 #define SIM_UIDMH_UID_SHIFT 0
mbed_official 82:0b31dbcd4769 2750 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
mbed_official 82:0b31dbcd4769 2751 /* UIDML Bit Fields */
mbed_official 82:0b31dbcd4769 2752 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2753 #define SIM_UIDML_UID_SHIFT 0
mbed_official 82:0b31dbcd4769 2754 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
mbed_official 82:0b31dbcd4769 2755 /* UIDL Bit Fields */
mbed_official 82:0b31dbcd4769 2756 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
mbed_official 82:0b31dbcd4769 2757 #define SIM_UIDL_UID_SHIFT 0
mbed_official 82:0b31dbcd4769 2758 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
mbed_official 82:0b31dbcd4769 2759 /* COPC Bit Fields */
mbed_official 82:0b31dbcd4769 2760 #define SIM_COPC_COPW_MASK 0x1u
mbed_official 82:0b31dbcd4769 2761 #define SIM_COPC_COPW_SHIFT 0
mbed_official 82:0b31dbcd4769 2762 #define SIM_COPC_COPCLKS_MASK 0x2u
mbed_official 82:0b31dbcd4769 2763 #define SIM_COPC_COPCLKS_SHIFT 1
mbed_official 82:0b31dbcd4769 2764 #define SIM_COPC_COPT_MASK 0xCu
mbed_official 82:0b31dbcd4769 2765 #define SIM_COPC_COPT_SHIFT 2
mbed_official 82:0b31dbcd4769 2766 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
mbed_official 82:0b31dbcd4769 2767 /* SRVCOP Bit Fields */
mbed_official 82:0b31dbcd4769 2768 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
mbed_official 82:0b31dbcd4769 2769 #define SIM_SRVCOP_SRVCOP_SHIFT 0
mbed_official 82:0b31dbcd4769 2770 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
mbed_official 82:0b31dbcd4769 2771
mbed_official 82:0b31dbcd4769 2772 /**
mbed_official 82:0b31dbcd4769 2773 * @}
mbed_official 82:0b31dbcd4769 2774 */ /* end of group SIM_Register_Masks */
mbed_official 82:0b31dbcd4769 2775
mbed_official 82:0b31dbcd4769 2776
mbed_official 82:0b31dbcd4769 2777 /* SIM - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 2778 /** Peripheral SIM base address */
mbed_official 82:0b31dbcd4769 2779 #define SIM_BASE (0x40047000u)
mbed_official 82:0b31dbcd4769 2780 /** Peripheral SIM base pointer */
mbed_official 82:0b31dbcd4769 2781 #define SIM ((SIM_Type *)SIM_BASE)
mbed_official 82:0b31dbcd4769 2782 /** Array initializer of SIM peripheral base pointers */
mbed_official 82:0b31dbcd4769 2783 #define SIM_BASES { SIM }
mbed_official 82:0b31dbcd4769 2784
mbed_official 82:0b31dbcd4769 2785 /**
mbed_official 82:0b31dbcd4769 2786 * @}
mbed_official 82:0b31dbcd4769 2787 */ /* end of group SIM_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 2788
mbed_official 82:0b31dbcd4769 2789
mbed_official 82:0b31dbcd4769 2790 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2791 -- SMC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2792 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2793
mbed_official 82:0b31dbcd4769 2794 /**
mbed_official 82:0b31dbcd4769 2795 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2796 * @{
mbed_official 82:0b31dbcd4769 2797 */
mbed_official 82:0b31dbcd4769 2798
mbed_official 82:0b31dbcd4769 2799 /** SMC - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 2800 typedef struct {
mbed_official 82:0b31dbcd4769 2801 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 2802 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
mbed_official 82:0b31dbcd4769 2803 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
mbed_official 82:0b31dbcd4769 2804 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
mbed_official 82:0b31dbcd4769 2805 } SMC_Type;
mbed_official 82:0b31dbcd4769 2806
mbed_official 82:0b31dbcd4769 2807 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2808 -- SMC Register Masks
mbed_official 82:0b31dbcd4769 2809 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2810
mbed_official 82:0b31dbcd4769 2811 /**
mbed_official 82:0b31dbcd4769 2812 * @addtogroup SMC_Register_Masks SMC Register Masks
mbed_official 82:0b31dbcd4769 2813 * @{
mbed_official 82:0b31dbcd4769 2814 */
mbed_official 82:0b31dbcd4769 2815
mbed_official 82:0b31dbcd4769 2816 /* PMPROT Bit Fields */
mbed_official 82:0b31dbcd4769 2817 #define SMC_PMPROT_AVLLS_MASK 0x2u
mbed_official 82:0b31dbcd4769 2818 #define SMC_PMPROT_AVLLS_SHIFT 1
mbed_official 82:0b31dbcd4769 2819 #define SMC_PMPROT_ALLS_MASK 0x8u
mbed_official 82:0b31dbcd4769 2820 #define SMC_PMPROT_ALLS_SHIFT 3
mbed_official 82:0b31dbcd4769 2821 #define SMC_PMPROT_AVLP_MASK 0x20u
mbed_official 82:0b31dbcd4769 2822 #define SMC_PMPROT_AVLP_SHIFT 5
mbed_official 82:0b31dbcd4769 2823 /* PMCTRL Bit Fields */
mbed_official 82:0b31dbcd4769 2824 #define SMC_PMCTRL_STOPM_MASK 0x7u
mbed_official 82:0b31dbcd4769 2825 #define SMC_PMCTRL_STOPM_SHIFT 0
mbed_official 82:0b31dbcd4769 2826 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
mbed_official 82:0b31dbcd4769 2827 #define SMC_PMCTRL_STOPA_MASK 0x8u
mbed_official 82:0b31dbcd4769 2828 #define SMC_PMCTRL_STOPA_SHIFT 3
mbed_official 82:0b31dbcd4769 2829 #define SMC_PMCTRL_RUNM_MASK 0x60u
mbed_official 82:0b31dbcd4769 2830 #define SMC_PMCTRL_RUNM_SHIFT 5
mbed_official 82:0b31dbcd4769 2831 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
mbed_official 82:0b31dbcd4769 2832 /* STOPCTRL Bit Fields */
mbed_official 82:0b31dbcd4769 2833 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
mbed_official 82:0b31dbcd4769 2834 #define SMC_STOPCTRL_VLLSM_SHIFT 0
mbed_official 82:0b31dbcd4769 2835 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
mbed_official 82:0b31dbcd4769 2836 #define SMC_STOPCTRL_PORPO_MASK 0x20u
mbed_official 82:0b31dbcd4769 2837 #define SMC_STOPCTRL_PORPO_SHIFT 5
mbed_official 82:0b31dbcd4769 2838 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
mbed_official 82:0b31dbcd4769 2839 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
mbed_official 82:0b31dbcd4769 2840 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
mbed_official 82:0b31dbcd4769 2841 /* PMSTAT Bit Fields */
mbed_official 82:0b31dbcd4769 2842 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
mbed_official 82:0b31dbcd4769 2843 #define SMC_PMSTAT_PMSTAT_SHIFT 0
mbed_official 82:0b31dbcd4769 2844 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
mbed_official 82:0b31dbcd4769 2845
mbed_official 82:0b31dbcd4769 2846 /**
mbed_official 82:0b31dbcd4769 2847 * @}
mbed_official 82:0b31dbcd4769 2848 */ /* end of group SMC_Register_Masks */
mbed_official 82:0b31dbcd4769 2849
mbed_official 82:0b31dbcd4769 2850
mbed_official 82:0b31dbcd4769 2851 /* SMC - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 2852 /** Peripheral SMC base address */
mbed_official 82:0b31dbcd4769 2853 #define SMC_BASE (0x4007E000u)
mbed_official 82:0b31dbcd4769 2854 /** Peripheral SMC base pointer */
mbed_official 82:0b31dbcd4769 2855 #define SMC ((SMC_Type *)SMC_BASE)
mbed_official 82:0b31dbcd4769 2856 /** Array initializer of SMC peripheral base pointers */
mbed_official 82:0b31dbcd4769 2857 #define SMC_BASES { SMC }
mbed_official 82:0b31dbcd4769 2858
mbed_official 82:0b31dbcd4769 2859 /**
mbed_official 82:0b31dbcd4769 2860 * @}
mbed_official 82:0b31dbcd4769 2861 */ /* end of group SMC_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 2862
mbed_official 82:0b31dbcd4769 2863
mbed_official 82:0b31dbcd4769 2864 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2865 -- SPI Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2866 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2867
mbed_official 82:0b31dbcd4769 2868 /**
mbed_official 82:0b31dbcd4769 2869 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2870 * @{
mbed_official 82:0b31dbcd4769 2871 */
mbed_official 82:0b31dbcd4769 2872
mbed_official 82:0b31dbcd4769 2873 /** SPI - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 2874 typedef struct {
mbed_official 82:0b31dbcd4769 2875 __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
mbed_official 82:0b31dbcd4769 2876 __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
mbed_official 82:0b31dbcd4769 2877 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
mbed_official 82:0b31dbcd4769 2878 __I uint8_t S; /**< SPI status register, offset: 0x3 */
mbed_official 82:0b31dbcd4769 2879 uint8_t RESERVED_0[1];
mbed_official 82:0b31dbcd4769 2880 __IO uint8_t D; /**< SPI data register, offset: 0x5 */
mbed_official 82:0b31dbcd4769 2881 uint8_t RESERVED_1[1];
mbed_official 82:0b31dbcd4769 2882 __IO uint8_t M; /**< SPI match register, offset: 0x7 */
mbed_official 82:0b31dbcd4769 2883 } SPI_Type;
mbed_official 82:0b31dbcd4769 2884
mbed_official 82:0b31dbcd4769 2885 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2886 -- SPI Register Masks
mbed_official 82:0b31dbcd4769 2887 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2888
mbed_official 82:0b31dbcd4769 2889 /**
mbed_official 82:0b31dbcd4769 2890 * @addtogroup SPI_Register_Masks SPI Register Masks
mbed_official 82:0b31dbcd4769 2891 * @{
mbed_official 82:0b31dbcd4769 2892 */
mbed_official 82:0b31dbcd4769 2893
mbed_official 82:0b31dbcd4769 2894 /* C1 Bit Fields */
mbed_official 82:0b31dbcd4769 2895 #define SPI_C1_LSBFE_MASK 0x1u
mbed_official 82:0b31dbcd4769 2896 #define SPI_C1_LSBFE_SHIFT 0
mbed_official 82:0b31dbcd4769 2897 #define SPI_C1_SSOE_MASK 0x2u
mbed_official 82:0b31dbcd4769 2898 #define SPI_C1_SSOE_SHIFT 1
mbed_official 82:0b31dbcd4769 2899 #define SPI_C1_CPHA_MASK 0x4u
mbed_official 82:0b31dbcd4769 2900 #define SPI_C1_CPHA_SHIFT 2
mbed_official 82:0b31dbcd4769 2901 #define SPI_C1_CPOL_MASK 0x8u
mbed_official 82:0b31dbcd4769 2902 #define SPI_C1_CPOL_SHIFT 3
mbed_official 82:0b31dbcd4769 2903 #define SPI_C1_MSTR_MASK 0x10u
mbed_official 82:0b31dbcd4769 2904 #define SPI_C1_MSTR_SHIFT 4
mbed_official 82:0b31dbcd4769 2905 #define SPI_C1_SPTIE_MASK 0x20u
mbed_official 82:0b31dbcd4769 2906 #define SPI_C1_SPTIE_SHIFT 5
mbed_official 82:0b31dbcd4769 2907 #define SPI_C1_SPE_MASK 0x40u
mbed_official 82:0b31dbcd4769 2908 #define SPI_C1_SPE_SHIFT 6
mbed_official 82:0b31dbcd4769 2909 #define SPI_C1_SPIE_MASK 0x80u
mbed_official 82:0b31dbcd4769 2910 #define SPI_C1_SPIE_SHIFT 7
mbed_official 82:0b31dbcd4769 2911 /* C2 Bit Fields */
mbed_official 82:0b31dbcd4769 2912 #define SPI_C2_SPC0_MASK 0x1u
mbed_official 82:0b31dbcd4769 2913 #define SPI_C2_SPC0_SHIFT 0
mbed_official 82:0b31dbcd4769 2914 #define SPI_C2_SPISWAI_MASK 0x2u
mbed_official 82:0b31dbcd4769 2915 #define SPI_C2_SPISWAI_SHIFT 1
mbed_official 82:0b31dbcd4769 2916 #define SPI_C2_RXDMAE_MASK 0x4u
mbed_official 82:0b31dbcd4769 2917 #define SPI_C2_RXDMAE_SHIFT 2
mbed_official 82:0b31dbcd4769 2918 #define SPI_C2_BIDIROE_MASK 0x8u
mbed_official 82:0b31dbcd4769 2919 #define SPI_C2_BIDIROE_SHIFT 3
mbed_official 82:0b31dbcd4769 2920 #define SPI_C2_MODFEN_MASK 0x10u
mbed_official 82:0b31dbcd4769 2921 #define SPI_C2_MODFEN_SHIFT 4
mbed_official 82:0b31dbcd4769 2922 #define SPI_C2_TXDMAE_MASK 0x20u
mbed_official 82:0b31dbcd4769 2923 #define SPI_C2_TXDMAE_SHIFT 5
mbed_official 82:0b31dbcd4769 2924 #define SPI_C2_SPMIE_MASK 0x80u
mbed_official 82:0b31dbcd4769 2925 #define SPI_C2_SPMIE_SHIFT 7
mbed_official 82:0b31dbcd4769 2926 /* BR Bit Fields */
mbed_official 82:0b31dbcd4769 2927 #define SPI_BR_SPR_MASK 0xFu
mbed_official 82:0b31dbcd4769 2928 #define SPI_BR_SPR_SHIFT 0
mbed_official 82:0b31dbcd4769 2929 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
mbed_official 82:0b31dbcd4769 2930 #define SPI_BR_SPPR_MASK 0x70u
mbed_official 82:0b31dbcd4769 2931 #define SPI_BR_SPPR_SHIFT 4
mbed_official 82:0b31dbcd4769 2932 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
mbed_official 82:0b31dbcd4769 2933 /* S Bit Fields */
mbed_official 82:0b31dbcd4769 2934 #define SPI_S_MODF_MASK 0x10u
mbed_official 82:0b31dbcd4769 2935 #define SPI_S_MODF_SHIFT 4
mbed_official 82:0b31dbcd4769 2936 #define SPI_S_SPTEF_MASK 0x20u
mbed_official 82:0b31dbcd4769 2937 #define SPI_S_SPTEF_SHIFT 5
mbed_official 82:0b31dbcd4769 2938 #define SPI_S_SPMF_MASK 0x40u
mbed_official 82:0b31dbcd4769 2939 #define SPI_S_SPMF_SHIFT 6
mbed_official 82:0b31dbcd4769 2940 #define SPI_S_SPRF_MASK 0x80u
mbed_official 82:0b31dbcd4769 2941 #define SPI_S_SPRF_SHIFT 7
mbed_official 82:0b31dbcd4769 2942 /* D Bit Fields */
mbed_official 82:0b31dbcd4769 2943 #define SPI_D_Bits_MASK 0xFFu
mbed_official 82:0b31dbcd4769 2944 #define SPI_D_Bits_SHIFT 0
mbed_official 82:0b31dbcd4769 2945 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
mbed_official 82:0b31dbcd4769 2946 /* M Bit Fields */
mbed_official 82:0b31dbcd4769 2947 #define SPI_M_Bits_MASK 0xFFu
mbed_official 82:0b31dbcd4769 2948 #define SPI_M_Bits_SHIFT 0
mbed_official 82:0b31dbcd4769 2949 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
mbed_official 82:0b31dbcd4769 2950
mbed_official 82:0b31dbcd4769 2951 /**
mbed_official 82:0b31dbcd4769 2952 * @}
mbed_official 82:0b31dbcd4769 2953 */ /* end of group SPI_Register_Masks */
mbed_official 82:0b31dbcd4769 2954
mbed_official 82:0b31dbcd4769 2955
mbed_official 82:0b31dbcd4769 2956 /* SPI - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 2957 /** Peripheral SPI0 base address */
mbed_official 82:0b31dbcd4769 2958 #define SPI0_BASE (0x40076000u)
mbed_official 82:0b31dbcd4769 2959 /** Peripheral SPI0 base pointer */
mbed_official 82:0b31dbcd4769 2960 #define SPI0 ((SPI_Type *)SPI0_BASE)
mbed_official 82:0b31dbcd4769 2961 /** Array initializer of SPI peripheral base pointers */
mbed_official 82:0b31dbcd4769 2962 #define SPI_BASES { SPI0 }
mbed_official 82:0b31dbcd4769 2963
mbed_official 82:0b31dbcd4769 2964 /**
mbed_official 82:0b31dbcd4769 2965 * @}
mbed_official 82:0b31dbcd4769 2966 */ /* end of group SPI_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 2967
mbed_official 82:0b31dbcd4769 2968
mbed_official 82:0b31dbcd4769 2969 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2970 -- TPM Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2971 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2972
mbed_official 82:0b31dbcd4769 2973 /**
mbed_official 82:0b31dbcd4769 2974 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
mbed_official 82:0b31dbcd4769 2975 * @{
mbed_official 82:0b31dbcd4769 2976 */
mbed_official 82:0b31dbcd4769 2977
mbed_official 82:0b31dbcd4769 2978 /** TPM - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 2979 typedef struct {
mbed_official 82:0b31dbcd4769 2980 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
mbed_official 82:0b31dbcd4769 2981 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
mbed_official 82:0b31dbcd4769 2982 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
mbed_official 82:0b31dbcd4769 2983 struct { /* offset: 0xC, array step: 0x8 */
mbed_official 82:0b31dbcd4769 2984 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
mbed_official 82:0b31dbcd4769 2985 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
mbed_official 82:0b31dbcd4769 2986 } CONTROLS[6];
mbed_official 82:0b31dbcd4769 2987 uint8_t RESERVED_0[20];
mbed_official 82:0b31dbcd4769 2988 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
mbed_official 82:0b31dbcd4769 2989 uint8_t RESERVED_1[48];
mbed_official 82:0b31dbcd4769 2990 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
mbed_official 82:0b31dbcd4769 2991 } TPM_Type;
mbed_official 82:0b31dbcd4769 2992
mbed_official 82:0b31dbcd4769 2993 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 2994 -- TPM Register Masks
mbed_official 82:0b31dbcd4769 2995 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 2996
mbed_official 82:0b31dbcd4769 2997 /**
mbed_official 82:0b31dbcd4769 2998 * @addtogroup TPM_Register_Masks TPM Register Masks
mbed_official 82:0b31dbcd4769 2999 * @{
mbed_official 82:0b31dbcd4769 3000 */
mbed_official 82:0b31dbcd4769 3001
mbed_official 82:0b31dbcd4769 3002 /* SC Bit Fields */
mbed_official 82:0b31dbcd4769 3003 #define TPM_SC_PS_MASK 0x7u
mbed_official 82:0b31dbcd4769 3004 #define TPM_SC_PS_SHIFT 0
mbed_official 82:0b31dbcd4769 3005 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
mbed_official 82:0b31dbcd4769 3006 #define TPM_SC_CMOD_MASK 0x18u
mbed_official 82:0b31dbcd4769 3007 #define TPM_SC_CMOD_SHIFT 3
mbed_official 82:0b31dbcd4769 3008 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
mbed_official 82:0b31dbcd4769 3009 #define TPM_SC_CPWMS_MASK 0x20u
mbed_official 82:0b31dbcd4769 3010 #define TPM_SC_CPWMS_SHIFT 5
mbed_official 82:0b31dbcd4769 3011 #define TPM_SC_TOIE_MASK 0x40u
mbed_official 82:0b31dbcd4769 3012 #define TPM_SC_TOIE_SHIFT 6
mbed_official 82:0b31dbcd4769 3013 #define TPM_SC_TOF_MASK 0x80u
mbed_official 82:0b31dbcd4769 3014 #define TPM_SC_TOF_SHIFT 7
mbed_official 82:0b31dbcd4769 3015 #define TPM_SC_DMA_MASK 0x100u
mbed_official 82:0b31dbcd4769 3016 #define TPM_SC_DMA_SHIFT 8
mbed_official 82:0b31dbcd4769 3017 /* CNT Bit Fields */
mbed_official 82:0b31dbcd4769 3018 #define TPM_CNT_COUNT_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 3019 #define TPM_CNT_COUNT_SHIFT 0
mbed_official 82:0b31dbcd4769 3020 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
mbed_official 82:0b31dbcd4769 3021 /* MOD Bit Fields */
mbed_official 82:0b31dbcd4769 3022 #define TPM_MOD_MOD_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 3023 #define TPM_MOD_MOD_SHIFT 0
mbed_official 82:0b31dbcd4769 3024 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
mbed_official 82:0b31dbcd4769 3025 /* CnSC Bit Fields */
mbed_official 82:0b31dbcd4769 3026 #define TPM_CnSC_DMA_MASK 0x1u
mbed_official 82:0b31dbcd4769 3027 #define TPM_CnSC_DMA_SHIFT 0
mbed_official 82:0b31dbcd4769 3028 #define TPM_CnSC_ELSA_MASK 0x4u
mbed_official 82:0b31dbcd4769 3029 #define TPM_CnSC_ELSA_SHIFT 2
mbed_official 82:0b31dbcd4769 3030 #define TPM_CnSC_ELSB_MASK 0x8u
mbed_official 82:0b31dbcd4769 3031 #define TPM_CnSC_ELSB_SHIFT 3
mbed_official 82:0b31dbcd4769 3032 #define TPM_CnSC_MSA_MASK 0x10u
mbed_official 82:0b31dbcd4769 3033 #define TPM_CnSC_MSA_SHIFT 4
mbed_official 82:0b31dbcd4769 3034 #define TPM_CnSC_MSB_MASK 0x20u
mbed_official 82:0b31dbcd4769 3035 #define TPM_CnSC_MSB_SHIFT 5
mbed_official 82:0b31dbcd4769 3036 #define TPM_CnSC_CHIE_MASK 0x40u
mbed_official 82:0b31dbcd4769 3037 #define TPM_CnSC_CHIE_SHIFT 6
mbed_official 82:0b31dbcd4769 3038 #define TPM_CnSC_CHF_MASK 0x80u
mbed_official 82:0b31dbcd4769 3039 #define TPM_CnSC_CHF_SHIFT 7
mbed_official 82:0b31dbcd4769 3040 /* CnV Bit Fields */
mbed_official 82:0b31dbcd4769 3041 #define TPM_CnV_VAL_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 3042 #define TPM_CnV_VAL_SHIFT 0
mbed_official 82:0b31dbcd4769 3043 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
mbed_official 82:0b31dbcd4769 3044 /* STATUS Bit Fields */
mbed_official 82:0b31dbcd4769 3045 #define TPM_STATUS_CH0F_MASK 0x1u
mbed_official 82:0b31dbcd4769 3046 #define TPM_STATUS_CH0F_SHIFT 0
mbed_official 82:0b31dbcd4769 3047 #define TPM_STATUS_CH1F_MASK 0x2u
mbed_official 82:0b31dbcd4769 3048 #define TPM_STATUS_CH1F_SHIFT 1
mbed_official 82:0b31dbcd4769 3049 #define TPM_STATUS_CH2F_MASK 0x4u
mbed_official 82:0b31dbcd4769 3050 #define TPM_STATUS_CH2F_SHIFT 2
mbed_official 82:0b31dbcd4769 3051 #define TPM_STATUS_CH3F_MASK 0x8u
mbed_official 82:0b31dbcd4769 3052 #define TPM_STATUS_CH3F_SHIFT 3
mbed_official 82:0b31dbcd4769 3053 #define TPM_STATUS_CH4F_MASK 0x10u
mbed_official 82:0b31dbcd4769 3054 #define TPM_STATUS_CH4F_SHIFT 4
mbed_official 82:0b31dbcd4769 3055 #define TPM_STATUS_CH5F_MASK 0x20u
mbed_official 82:0b31dbcd4769 3056 #define TPM_STATUS_CH5F_SHIFT 5
mbed_official 82:0b31dbcd4769 3057 #define TPM_STATUS_TOF_MASK 0x100u
mbed_official 82:0b31dbcd4769 3058 #define TPM_STATUS_TOF_SHIFT 8
mbed_official 82:0b31dbcd4769 3059 /* CONF Bit Fields */
mbed_official 82:0b31dbcd4769 3060 #define TPM_CONF_DOZEEN_MASK 0x20u
mbed_official 82:0b31dbcd4769 3061 #define TPM_CONF_DOZEEN_SHIFT 5
mbed_official 82:0b31dbcd4769 3062 #define TPM_CONF_DBGMODE_MASK 0xC0u
mbed_official 82:0b31dbcd4769 3063 #define TPM_CONF_DBGMODE_SHIFT 6
mbed_official 82:0b31dbcd4769 3064 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
mbed_official 82:0b31dbcd4769 3065 #define TPM_CONF_GTBEEN_MASK 0x200u
mbed_official 82:0b31dbcd4769 3066 #define TPM_CONF_GTBEEN_SHIFT 9
mbed_official 82:0b31dbcd4769 3067 #define TPM_CONF_CSOT_MASK 0x10000u
mbed_official 82:0b31dbcd4769 3068 #define TPM_CONF_CSOT_SHIFT 16
mbed_official 82:0b31dbcd4769 3069 #define TPM_CONF_CSOO_MASK 0x20000u
mbed_official 82:0b31dbcd4769 3070 #define TPM_CONF_CSOO_SHIFT 17
mbed_official 82:0b31dbcd4769 3071 #define TPM_CONF_CROT_MASK 0x40000u
mbed_official 82:0b31dbcd4769 3072 #define TPM_CONF_CROT_SHIFT 18
mbed_official 82:0b31dbcd4769 3073 #define TPM_CONF_TRGSEL_MASK 0xF000000u
mbed_official 82:0b31dbcd4769 3074 #define TPM_CONF_TRGSEL_SHIFT 24
mbed_official 82:0b31dbcd4769 3075 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
mbed_official 82:0b31dbcd4769 3076
mbed_official 82:0b31dbcd4769 3077 /**
mbed_official 82:0b31dbcd4769 3078 * @}
mbed_official 82:0b31dbcd4769 3079 */ /* end of group TPM_Register_Masks */
mbed_official 82:0b31dbcd4769 3080
mbed_official 82:0b31dbcd4769 3081
mbed_official 82:0b31dbcd4769 3082 /* TPM - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 3083 /** Peripheral TPM0 base address */
mbed_official 82:0b31dbcd4769 3084 #define TPM0_BASE (0x40038000u)
mbed_official 82:0b31dbcd4769 3085 /** Peripheral TPM0 base pointer */
mbed_official 82:0b31dbcd4769 3086 #define TPM0 ((TPM_Type *)TPM0_BASE)
mbed_official 82:0b31dbcd4769 3087 /** Peripheral TPM1 base address */
mbed_official 82:0b31dbcd4769 3088 #define TPM1_BASE (0x40039000u)
mbed_official 82:0b31dbcd4769 3089 /** Peripheral TPM1 base pointer */
mbed_official 82:0b31dbcd4769 3090 #define TPM1 ((TPM_Type *)TPM1_BASE)
mbed_official 82:0b31dbcd4769 3091 /** Array initializer of TPM peripheral base pointers */
mbed_official 82:0b31dbcd4769 3092 #define TPM_BASES { TPM0, TPM1 }
mbed_official 82:0b31dbcd4769 3093
mbed_official 82:0b31dbcd4769 3094 /**
mbed_official 82:0b31dbcd4769 3095 * @}
mbed_official 82:0b31dbcd4769 3096 */ /* end of group TPM_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 3097
mbed_official 82:0b31dbcd4769 3098
mbed_official 82:0b31dbcd4769 3099 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 3100 -- TSI Peripheral Access Layer
mbed_official 82:0b31dbcd4769 3101 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 3102
mbed_official 82:0b31dbcd4769 3103 /**
mbed_official 82:0b31dbcd4769 3104 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
mbed_official 82:0b31dbcd4769 3105 * @{
mbed_official 82:0b31dbcd4769 3106 */
mbed_official 82:0b31dbcd4769 3107
mbed_official 82:0b31dbcd4769 3108 /** TSI - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 3109 typedef struct {
mbed_official 82:0b31dbcd4769 3110 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
mbed_official 82:0b31dbcd4769 3111 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
mbed_official 82:0b31dbcd4769 3112 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
mbed_official 82:0b31dbcd4769 3113 } TSI_Type;
mbed_official 82:0b31dbcd4769 3114
mbed_official 82:0b31dbcd4769 3115 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 3116 -- TSI Register Masks
mbed_official 82:0b31dbcd4769 3117 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 3118
mbed_official 82:0b31dbcd4769 3119 /**
mbed_official 82:0b31dbcd4769 3120 * @addtogroup TSI_Register_Masks TSI Register Masks
mbed_official 82:0b31dbcd4769 3121 * @{
mbed_official 82:0b31dbcd4769 3122 */
mbed_official 82:0b31dbcd4769 3123
mbed_official 82:0b31dbcd4769 3124 /* GENCS Bit Fields */
mbed_official 82:0b31dbcd4769 3125 #define TSI_GENCS_CURSW_MASK 0x2u
mbed_official 82:0b31dbcd4769 3126 #define TSI_GENCS_CURSW_SHIFT 1
mbed_official 82:0b31dbcd4769 3127 #define TSI_GENCS_EOSF_MASK 0x4u
mbed_official 82:0b31dbcd4769 3128 #define TSI_GENCS_EOSF_SHIFT 2
mbed_official 82:0b31dbcd4769 3129 #define TSI_GENCS_SCNIP_MASK 0x8u
mbed_official 82:0b31dbcd4769 3130 #define TSI_GENCS_SCNIP_SHIFT 3
mbed_official 82:0b31dbcd4769 3131 #define TSI_GENCS_STM_MASK 0x10u
mbed_official 82:0b31dbcd4769 3132 #define TSI_GENCS_STM_SHIFT 4
mbed_official 82:0b31dbcd4769 3133 #define TSI_GENCS_STPE_MASK 0x20u
mbed_official 82:0b31dbcd4769 3134 #define TSI_GENCS_STPE_SHIFT 5
mbed_official 82:0b31dbcd4769 3135 #define TSI_GENCS_TSIIEN_MASK 0x40u
mbed_official 82:0b31dbcd4769 3136 #define TSI_GENCS_TSIIEN_SHIFT 6
mbed_official 82:0b31dbcd4769 3137 #define TSI_GENCS_TSIEN_MASK 0x80u
mbed_official 82:0b31dbcd4769 3138 #define TSI_GENCS_TSIEN_SHIFT 7
mbed_official 82:0b31dbcd4769 3139 #define TSI_GENCS_NSCN_MASK 0x1F00u
mbed_official 82:0b31dbcd4769 3140 #define TSI_GENCS_NSCN_SHIFT 8
mbed_official 82:0b31dbcd4769 3141 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
mbed_official 82:0b31dbcd4769 3142 #define TSI_GENCS_PS_MASK 0xE000u
mbed_official 82:0b31dbcd4769 3143 #define TSI_GENCS_PS_SHIFT 13
mbed_official 82:0b31dbcd4769 3144 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
mbed_official 82:0b31dbcd4769 3145 #define TSI_GENCS_EXTCHRG_MASK 0x70000u
mbed_official 82:0b31dbcd4769 3146 #define TSI_GENCS_EXTCHRG_SHIFT 16
mbed_official 82:0b31dbcd4769 3147 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
mbed_official 82:0b31dbcd4769 3148 #define TSI_GENCS_DVOLT_MASK 0x180000u
mbed_official 82:0b31dbcd4769 3149 #define TSI_GENCS_DVOLT_SHIFT 19
mbed_official 82:0b31dbcd4769 3150 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
mbed_official 82:0b31dbcd4769 3151 #define TSI_GENCS_REFCHRG_MASK 0xE00000u
mbed_official 82:0b31dbcd4769 3152 #define TSI_GENCS_REFCHRG_SHIFT 21
mbed_official 82:0b31dbcd4769 3153 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
mbed_official 82:0b31dbcd4769 3154 #define TSI_GENCS_MODE_MASK 0xF000000u
mbed_official 82:0b31dbcd4769 3155 #define TSI_GENCS_MODE_SHIFT 24
mbed_official 82:0b31dbcd4769 3156 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
mbed_official 82:0b31dbcd4769 3157 #define TSI_GENCS_ESOR_MASK 0x10000000u
mbed_official 82:0b31dbcd4769 3158 #define TSI_GENCS_ESOR_SHIFT 28
mbed_official 82:0b31dbcd4769 3159 #define TSI_GENCS_OUTRGF_MASK 0x80000000u
mbed_official 82:0b31dbcd4769 3160 #define TSI_GENCS_OUTRGF_SHIFT 31
mbed_official 82:0b31dbcd4769 3161 /* DATA Bit Fields */
mbed_official 82:0b31dbcd4769 3162 #define TSI_DATA_TSICNT_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 3163 #define TSI_DATA_TSICNT_SHIFT 0
mbed_official 82:0b31dbcd4769 3164 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
mbed_official 82:0b31dbcd4769 3165 #define TSI_DATA_SWTS_MASK 0x400000u
mbed_official 82:0b31dbcd4769 3166 #define TSI_DATA_SWTS_SHIFT 22
mbed_official 82:0b31dbcd4769 3167 #define TSI_DATA_DMAEN_MASK 0x800000u
mbed_official 82:0b31dbcd4769 3168 #define TSI_DATA_DMAEN_SHIFT 23
mbed_official 82:0b31dbcd4769 3169 #define TSI_DATA_TSICH_MASK 0xF0000000u
mbed_official 82:0b31dbcd4769 3170 #define TSI_DATA_TSICH_SHIFT 28
mbed_official 82:0b31dbcd4769 3171 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
mbed_official 82:0b31dbcd4769 3172 /* TSHD Bit Fields */
mbed_official 82:0b31dbcd4769 3173 #define TSI_TSHD_THRESL_MASK 0xFFFFu
mbed_official 82:0b31dbcd4769 3174 #define TSI_TSHD_THRESL_SHIFT 0
mbed_official 82:0b31dbcd4769 3175 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
mbed_official 82:0b31dbcd4769 3176 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u
mbed_official 82:0b31dbcd4769 3177 #define TSI_TSHD_THRESH_SHIFT 16
mbed_official 82:0b31dbcd4769 3178 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
mbed_official 82:0b31dbcd4769 3179
mbed_official 82:0b31dbcd4769 3180 /**
mbed_official 82:0b31dbcd4769 3181 * @}
mbed_official 82:0b31dbcd4769 3182 */ /* end of group TSI_Register_Masks */
mbed_official 82:0b31dbcd4769 3183
mbed_official 82:0b31dbcd4769 3184
mbed_official 82:0b31dbcd4769 3185 /* TSI - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 3186 /** Peripheral TSI0 base address */
mbed_official 82:0b31dbcd4769 3187 #define TSI0_BASE (0x40045000u)
mbed_official 82:0b31dbcd4769 3188 /** Peripheral TSI0 base pointer */
mbed_official 82:0b31dbcd4769 3189 #define TSI0 ((TSI_Type *)TSI0_BASE)
mbed_official 82:0b31dbcd4769 3190 /** Array initializer of TSI peripheral base pointers */
mbed_official 82:0b31dbcd4769 3191 #define TSI_BASES { TSI0 }
mbed_official 82:0b31dbcd4769 3192
mbed_official 82:0b31dbcd4769 3193 /**
mbed_official 82:0b31dbcd4769 3194 * @}
mbed_official 82:0b31dbcd4769 3195 */ /* end of group TSI_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 3196
mbed_official 82:0b31dbcd4769 3197
mbed_official 82:0b31dbcd4769 3198 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 3199 -- UART0 Peripheral Access Layer
mbed_official 82:0b31dbcd4769 3200 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 3201
mbed_official 82:0b31dbcd4769 3202 /**
mbed_official 82:0b31dbcd4769 3203 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
mbed_official 82:0b31dbcd4769 3204 * @{
mbed_official 82:0b31dbcd4769 3205 */
mbed_official 82:0b31dbcd4769 3206
mbed_official 82:0b31dbcd4769 3207 /** UART0 - Register Layout Typedef */
mbed_official 82:0b31dbcd4769 3208 typedef struct {
mbed_official 82:0b31dbcd4769 3209 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
mbed_official 82:0b31dbcd4769 3210 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
mbed_official 82:0b31dbcd4769 3211 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mbed_official 82:0b31dbcd4769 3212 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mbed_official 82:0b31dbcd4769 3213 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mbed_official 82:0b31dbcd4769 3214 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mbed_official 82:0b31dbcd4769 3215 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mbed_official 82:0b31dbcd4769 3216 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mbed_official 82:0b31dbcd4769 3217 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
mbed_official 82:0b31dbcd4769 3218 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
mbed_official 82:0b31dbcd4769 3219 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
mbed_official 82:0b31dbcd4769 3220 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
mbed_official 82:0b31dbcd4769 3221 } UART0_Type;
mbed_official 82:0b31dbcd4769 3222
mbed_official 82:0b31dbcd4769 3223 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 3224 -- UART0 Register Masks
mbed_official 82:0b31dbcd4769 3225 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 3226
mbed_official 82:0b31dbcd4769 3227 /**
mbed_official 82:0b31dbcd4769 3228 * @addtogroup UART0_Register_Masks UART0 Register Masks
mbed_official 82:0b31dbcd4769 3229 * @{
mbed_official 82:0b31dbcd4769 3230 */
mbed_official 82:0b31dbcd4769 3231
mbed_official 82:0b31dbcd4769 3232 /* BDH Bit Fields */
mbed_official 82:0b31dbcd4769 3233 #define UART0_BDH_SBR_MASK 0x1Fu
mbed_official 82:0b31dbcd4769 3234 #define UART0_BDH_SBR_SHIFT 0
mbed_official 82:0b31dbcd4769 3235 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
mbed_official 82:0b31dbcd4769 3236 #define UART0_BDH_SBNS_MASK 0x20u
mbed_official 82:0b31dbcd4769 3237 #define UART0_BDH_SBNS_SHIFT 5
mbed_official 82:0b31dbcd4769 3238 #define UART0_BDH_RXEDGIE_MASK 0x40u
mbed_official 82:0b31dbcd4769 3239 #define UART0_BDH_RXEDGIE_SHIFT 6
mbed_official 82:0b31dbcd4769 3240 #define UART0_BDH_LBKDIE_MASK 0x80u
mbed_official 82:0b31dbcd4769 3241 #define UART0_BDH_LBKDIE_SHIFT 7
mbed_official 82:0b31dbcd4769 3242 /* BDL Bit Fields */
mbed_official 82:0b31dbcd4769 3243 #define UART0_BDL_SBR_MASK 0xFFu
mbed_official 82:0b31dbcd4769 3244 #define UART0_BDL_SBR_SHIFT 0
mbed_official 82:0b31dbcd4769 3245 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
mbed_official 82:0b31dbcd4769 3246 /* C1 Bit Fields */
mbed_official 82:0b31dbcd4769 3247 #define UART0_C1_PT_MASK 0x1u
mbed_official 82:0b31dbcd4769 3248 #define UART0_C1_PT_SHIFT 0
mbed_official 82:0b31dbcd4769 3249 #define UART0_C1_PE_MASK 0x2u
mbed_official 82:0b31dbcd4769 3250 #define UART0_C1_PE_SHIFT 1
mbed_official 82:0b31dbcd4769 3251 #define UART0_C1_ILT_MASK 0x4u
mbed_official 82:0b31dbcd4769 3252 #define UART0_C1_ILT_SHIFT 2
mbed_official 82:0b31dbcd4769 3253 #define UART0_C1_WAKE_MASK 0x8u
mbed_official 82:0b31dbcd4769 3254 #define UART0_C1_WAKE_SHIFT 3
mbed_official 82:0b31dbcd4769 3255 #define UART0_C1_M_MASK 0x10u
mbed_official 82:0b31dbcd4769 3256 #define UART0_C1_M_SHIFT 4
mbed_official 82:0b31dbcd4769 3257 #define UART0_C1_RSRC_MASK 0x20u
mbed_official 82:0b31dbcd4769 3258 #define UART0_C1_RSRC_SHIFT 5
mbed_official 82:0b31dbcd4769 3259 #define UART0_C1_DOZEEN_MASK 0x40u
mbed_official 82:0b31dbcd4769 3260 #define UART0_C1_DOZEEN_SHIFT 6
mbed_official 82:0b31dbcd4769 3261 #define UART0_C1_LOOPS_MASK 0x80u
mbed_official 82:0b31dbcd4769 3262 #define UART0_C1_LOOPS_SHIFT 7
mbed_official 82:0b31dbcd4769 3263 /* C2 Bit Fields */
mbed_official 82:0b31dbcd4769 3264 #define UART0_C2_SBK_MASK 0x1u
mbed_official 82:0b31dbcd4769 3265 #define UART0_C2_SBK_SHIFT 0
mbed_official 82:0b31dbcd4769 3266 #define UART0_C2_RWU_MASK 0x2u
mbed_official 82:0b31dbcd4769 3267 #define UART0_C2_RWU_SHIFT 1
mbed_official 82:0b31dbcd4769 3268 #define UART0_C2_RE_MASK 0x4u
mbed_official 82:0b31dbcd4769 3269 #define UART0_C2_RE_SHIFT 2
mbed_official 82:0b31dbcd4769 3270 #define UART0_C2_TE_MASK 0x8u
mbed_official 82:0b31dbcd4769 3271 #define UART0_C2_TE_SHIFT 3
mbed_official 82:0b31dbcd4769 3272 #define UART0_C2_ILIE_MASK 0x10u
mbed_official 82:0b31dbcd4769 3273 #define UART0_C2_ILIE_SHIFT 4
mbed_official 82:0b31dbcd4769 3274 #define UART0_C2_RIE_MASK 0x20u
mbed_official 82:0b31dbcd4769 3275 #define UART0_C2_RIE_SHIFT 5
mbed_official 82:0b31dbcd4769 3276 #define UART0_C2_TCIE_MASK 0x40u
mbed_official 82:0b31dbcd4769 3277 #define UART0_C2_TCIE_SHIFT 6
mbed_official 82:0b31dbcd4769 3278 #define UART0_C2_TIE_MASK 0x80u
mbed_official 82:0b31dbcd4769 3279 #define UART0_C2_TIE_SHIFT 7
mbed_official 82:0b31dbcd4769 3280 /* S1 Bit Fields */
mbed_official 82:0b31dbcd4769 3281 #define UART0_S1_PF_MASK 0x1u
mbed_official 82:0b31dbcd4769 3282 #define UART0_S1_PF_SHIFT 0
mbed_official 82:0b31dbcd4769 3283 #define UART0_S1_FE_MASK 0x2u
mbed_official 82:0b31dbcd4769 3284 #define UART0_S1_FE_SHIFT 1
mbed_official 82:0b31dbcd4769 3285 #define UART0_S1_NF_MASK 0x4u
mbed_official 82:0b31dbcd4769 3286 #define UART0_S1_NF_SHIFT 2
mbed_official 82:0b31dbcd4769 3287 #define UART0_S1_OR_MASK 0x8u
mbed_official 82:0b31dbcd4769 3288 #define UART0_S1_OR_SHIFT 3
mbed_official 82:0b31dbcd4769 3289 #define UART0_S1_IDLE_MASK 0x10u
mbed_official 82:0b31dbcd4769 3290 #define UART0_S1_IDLE_SHIFT 4
mbed_official 82:0b31dbcd4769 3291 #define UART0_S1_RDRF_MASK 0x20u
mbed_official 82:0b31dbcd4769 3292 #define UART0_S1_RDRF_SHIFT 5
mbed_official 82:0b31dbcd4769 3293 #define UART0_S1_TC_MASK 0x40u
mbed_official 82:0b31dbcd4769 3294 #define UART0_S1_TC_SHIFT 6
mbed_official 82:0b31dbcd4769 3295 #define UART0_S1_TDRE_MASK 0x80u
mbed_official 82:0b31dbcd4769 3296 #define UART0_S1_TDRE_SHIFT 7
mbed_official 82:0b31dbcd4769 3297 /* S2 Bit Fields */
mbed_official 82:0b31dbcd4769 3298 #define UART0_S2_RAF_MASK 0x1u
mbed_official 82:0b31dbcd4769 3299 #define UART0_S2_RAF_SHIFT 0
mbed_official 82:0b31dbcd4769 3300 #define UART0_S2_LBKDE_MASK 0x2u
mbed_official 82:0b31dbcd4769 3301 #define UART0_S2_LBKDE_SHIFT 1
mbed_official 82:0b31dbcd4769 3302 #define UART0_S2_BRK13_MASK 0x4u
mbed_official 82:0b31dbcd4769 3303 #define UART0_S2_BRK13_SHIFT 2
mbed_official 82:0b31dbcd4769 3304 #define UART0_S2_RWUID_MASK 0x8u
mbed_official 82:0b31dbcd4769 3305 #define UART0_S2_RWUID_SHIFT 3
mbed_official 82:0b31dbcd4769 3306 #define UART0_S2_RXINV_MASK 0x10u
mbed_official 82:0b31dbcd4769 3307 #define UART0_S2_RXINV_SHIFT 4
mbed_official 82:0b31dbcd4769 3308 #define UART0_S2_MSBF_MASK 0x20u
mbed_official 82:0b31dbcd4769 3309 #define UART0_S2_MSBF_SHIFT 5
mbed_official 82:0b31dbcd4769 3310 #define UART0_S2_RXEDGIF_MASK 0x40u
mbed_official 82:0b31dbcd4769 3311 #define UART0_S2_RXEDGIF_SHIFT 6
mbed_official 82:0b31dbcd4769 3312 #define UART0_S2_LBKDIF_MASK 0x80u
mbed_official 82:0b31dbcd4769 3313 #define UART0_S2_LBKDIF_SHIFT 7
mbed_official 82:0b31dbcd4769 3314 /* C3 Bit Fields */
mbed_official 82:0b31dbcd4769 3315 #define UART0_C3_PEIE_MASK 0x1u
mbed_official 82:0b31dbcd4769 3316 #define UART0_C3_PEIE_SHIFT 0
mbed_official 82:0b31dbcd4769 3317 #define UART0_C3_FEIE_MASK 0x2u
mbed_official 82:0b31dbcd4769 3318 #define UART0_C3_FEIE_SHIFT 1
mbed_official 82:0b31dbcd4769 3319 #define UART0_C3_NEIE_MASK 0x4u
mbed_official 82:0b31dbcd4769 3320 #define UART0_C3_NEIE_SHIFT 2
mbed_official 82:0b31dbcd4769 3321 #define UART0_C3_ORIE_MASK 0x8u
mbed_official 82:0b31dbcd4769 3322 #define UART0_C3_ORIE_SHIFT 3
mbed_official 82:0b31dbcd4769 3323 #define UART0_C3_TXINV_MASK 0x10u
mbed_official 82:0b31dbcd4769 3324 #define UART0_C3_TXINV_SHIFT 4
mbed_official 82:0b31dbcd4769 3325 #define UART0_C3_TXDIR_MASK 0x20u
mbed_official 82:0b31dbcd4769 3326 #define UART0_C3_TXDIR_SHIFT 5
mbed_official 82:0b31dbcd4769 3327 #define UART0_C3_R9T8_MASK 0x40u
mbed_official 82:0b31dbcd4769 3328 #define UART0_C3_R9T8_SHIFT 6
mbed_official 82:0b31dbcd4769 3329 #define UART0_C3_R8T9_MASK 0x80u
mbed_official 82:0b31dbcd4769 3330 #define UART0_C3_R8T9_SHIFT 7
mbed_official 82:0b31dbcd4769 3331 /* D Bit Fields */
mbed_official 82:0b31dbcd4769 3332 #define UART0_D_R0T0_MASK 0x1u
mbed_official 82:0b31dbcd4769 3333 #define UART0_D_R0T0_SHIFT 0
mbed_official 82:0b31dbcd4769 3334 #define UART0_D_R1T1_MASK 0x2u
mbed_official 82:0b31dbcd4769 3335 #define UART0_D_R1T1_SHIFT 1
mbed_official 82:0b31dbcd4769 3336 #define UART0_D_R2T2_MASK 0x4u
mbed_official 82:0b31dbcd4769 3337 #define UART0_D_R2T2_SHIFT 2
mbed_official 82:0b31dbcd4769 3338 #define UART0_D_R3T3_MASK 0x8u
mbed_official 82:0b31dbcd4769 3339 #define UART0_D_R3T3_SHIFT 3
mbed_official 82:0b31dbcd4769 3340 #define UART0_D_R4T4_MASK 0x10u
mbed_official 82:0b31dbcd4769 3341 #define UART0_D_R4T4_SHIFT 4
mbed_official 82:0b31dbcd4769 3342 #define UART0_D_R5T5_MASK 0x20u
mbed_official 82:0b31dbcd4769 3343 #define UART0_D_R5T5_SHIFT 5
mbed_official 82:0b31dbcd4769 3344 #define UART0_D_R6T6_MASK 0x40u
mbed_official 82:0b31dbcd4769 3345 #define UART0_D_R6T6_SHIFT 6
mbed_official 82:0b31dbcd4769 3346 #define UART0_D_R7T7_MASK 0x80u
mbed_official 82:0b31dbcd4769 3347 #define UART0_D_R7T7_SHIFT 7
mbed_official 82:0b31dbcd4769 3348 /* MA1 Bit Fields */
mbed_official 82:0b31dbcd4769 3349 #define UART0_MA1_MA_MASK 0xFFu
mbed_official 82:0b31dbcd4769 3350 #define UART0_MA1_MA_SHIFT 0
mbed_official 82:0b31dbcd4769 3351 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
mbed_official 82:0b31dbcd4769 3352 /* MA2 Bit Fields */
mbed_official 82:0b31dbcd4769 3353 #define UART0_MA2_MA_MASK 0xFFu
mbed_official 82:0b31dbcd4769 3354 #define UART0_MA2_MA_SHIFT 0
mbed_official 82:0b31dbcd4769 3355 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
mbed_official 82:0b31dbcd4769 3356 /* C4 Bit Fields */
mbed_official 82:0b31dbcd4769 3357 #define UART0_C4_OSR_MASK 0x1Fu
mbed_official 82:0b31dbcd4769 3358 #define UART0_C4_OSR_SHIFT 0
mbed_official 82:0b31dbcd4769 3359 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
mbed_official 82:0b31dbcd4769 3360 #define UART0_C4_M10_MASK 0x20u
mbed_official 82:0b31dbcd4769 3361 #define UART0_C4_M10_SHIFT 5
mbed_official 82:0b31dbcd4769 3362 #define UART0_C4_MAEN2_MASK 0x40u
mbed_official 82:0b31dbcd4769 3363 #define UART0_C4_MAEN2_SHIFT 6
mbed_official 82:0b31dbcd4769 3364 #define UART0_C4_MAEN1_MASK 0x80u
mbed_official 82:0b31dbcd4769 3365 #define UART0_C4_MAEN1_SHIFT 7
mbed_official 82:0b31dbcd4769 3366 /* C5 Bit Fields */
mbed_official 82:0b31dbcd4769 3367 #define UART0_C5_RESYNCDIS_MASK 0x1u
mbed_official 82:0b31dbcd4769 3368 #define UART0_C5_RESYNCDIS_SHIFT 0
mbed_official 82:0b31dbcd4769 3369 #define UART0_C5_BOTHEDGE_MASK 0x2u
mbed_official 82:0b31dbcd4769 3370 #define UART0_C5_BOTHEDGE_SHIFT 1
mbed_official 82:0b31dbcd4769 3371 #define UART0_C5_RDMAE_MASK 0x20u
mbed_official 82:0b31dbcd4769 3372 #define UART0_C5_RDMAE_SHIFT 5
mbed_official 82:0b31dbcd4769 3373 #define UART0_C5_TDMAE_MASK 0x80u
mbed_official 82:0b31dbcd4769 3374 #define UART0_C5_TDMAE_SHIFT 7
mbed_official 82:0b31dbcd4769 3375
mbed_official 82:0b31dbcd4769 3376 /**
mbed_official 82:0b31dbcd4769 3377 * @}
mbed_official 82:0b31dbcd4769 3378 */ /* end of group UART0_Register_Masks */
mbed_official 82:0b31dbcd4769 3379
mbed_official 82:0b31dbcd4769 3380
mbed_official 82:0b31dbcd4769 3381 /* UART0 - Peripheral instance base addresses */
mbed_official 82:0b31dbcd4769 3382 /** Peripheral UART0 base address */
mbed_official 82:0b31dbcd4769 3383 #define UART0_BASE (0x4006A000u)
mbed_official 82:0b31dbcd4769 3384 /** Peripheral UART0 base pointer */
mbed_official 82:0b31dbcd4769 3385 #define UART0 ((UART0_Type *)UART0_BASE)
mbed_official 82:0b31dbcd4769 3386 /** Array initializer of UART0 peripheral base pointers */
mbed_official 82:0b31dbcd4769 3387 #define UART0_BASES { UART0 }
mbed_official 82:0b31dbcd4769 3388
mbed_official 82:0b31dbcd4769 3389 /**
mbed_official 82:0b31dbcd4769 3390 * @}
mbed_official 82:0b31dbcd4769 3391 */ /* end of group UART0_Peripheral_Access_Layer */
mbed_official 82:0b31dbcd4769 3392
mbed_official 82:0b31dbcd4769 3393
mbed_official 82:0b31dbcd4769 3394 /*
mbed_official 82:0b31dbcd4769 3395 ** End of section using anonymous unions
mbed_official 82:0b31dbcd4769 3396 */
mbed_official 82:0b31dbcd4769 3397
mbed_official 82:0b31dbcd4769 3398 #if defined(__ARMCC_VERSION)
mbed_official 82:0b31dbcd4769 3399 #pragma pop
mbed_official 82:0b31dbcd4769 3400 #elif defined(__CWCC__)
mbed_official 82:0b31dbcd4769 3401 #pragma pop
mbed_official 82:0b31dbcd4769 3402 #elif defined(__GNUC__)
mbed_official 82:0b31dbcd4769 3403 /* leave anonymous unions enabled */
mbed_official 82:0b31dbcd4769 3404 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 82:0b31dbcd4769 3405 #pragma language=default
mbed_official 82:0b31dbcd4769 3406 #else
mbed_official 82:0b31dbcd4769 3407 #error Not supported compiler type
mbed_official 82:0b31dbcd4769 3408 #endif
mbed_official 82:0b31dbcd4769 3409
mbed_official 82:0b31dbcd4769 3410 /**
mbed_official 82:0b31dbcd4769 3411 * @}
mbed_official 82:0b31dbcd4769 3412 */ /* end of group Peripheral_access_layer */
mbed_official 82:0b31dbcd4769 3413
mbed_official 82:0b31dbcd4769 3414
mbed_official 82:0b31dbcd4769 3415 /* ----------------------------------------------------------------------------
mbed_official 82:0b31dbcd4769 3416 -- Backward Compatibility
mbed_official 82:0b31dbcd4769 3417 ---------------------------------------------------------------------------- */
mbed_official 82:0b31dbcd4769 3418
mbed_official 82:0b31dbcd4769 3419 /**
mbed_official 82:0b31dbcd4769 3420 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
mbed_official 82:0b31dbcd4769 3421 * @{
mbed_official 82:0b31dbcd4769 3422 */
mbed_official 82:0b31dbcd4769 3423
mbed_official 82:0b31dbcd4769 3424 #define DMA_REQC_ARR_DMAC_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3425 #define DMA_REQC_ARR_DMAC_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3426 #define DMA_REQC_ARR_DMAC(x) This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3427 #define DMA_REQC_ARR_CFSM_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3428 #define DMA_REQC_ARR_CFSM_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3429 #define DMA_REQC0 This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3430 #define DMA_REQC1 This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3431 #define DMA_REQC2 This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3432 #define DMA_REQC3 This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3433 #define MCG_C6_CME0_MASK MCG_C6_CME_MASK
mbed_official 82:0b31dbcd4769 3434 #define MCG_C6_CME0_SHIFT MCG_C6_CME_SHIFT
mbed_official 82:0b31dbcd4769 3435 #define MCM_MATCR_ATC0_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3436 #define MCM_MATCR_ATC0_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3437 #define MCM_MATCR_ATC0(x) This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3438 #define MCM_MATCR_RO0_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3439 #define MCM_MATCR_RO0_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3440 #define MCM_MATCR_ATC1_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3441 #define MCM_MATCR_ATC1_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3442 #define MCM_MATCR_ATC1(x) This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3443 #define MCM_MATCR_RO1_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3444 #define MCM_MATCR_RO1_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3445 #define MCM_MATCR_ATC2_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3446 #define MCM_MATCR_ATC2_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3447 #define MCM_MATCR_ATC2(x) This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3448 #define MCM_MATCR_RO2_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3449 #define MCM_MATCR_RO2_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3450 #define MCM_MATCR_ATC3_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3451 #define MCM_MATCR_ATC3_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3452 #define MCM_MATCR_ATC3(x) This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3453 #define MCM_MATCR_RO3_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3454 #define MCM_MATCR_RO3_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3455 #define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK
mbed_official 82:0b31dbcd4769 3456 #define SIM_FCFG2_MAXADDR_SHIFT SIM_FCFG2_MAXADDR0_SHIFT
mbed_official 82:0b31dbcd4769 3457 #define SIM_FCFG2_MAXADDR SIM_FCFG2_MAXADDR0
mbed_official 82:0b31dbcd4769 3458 #define SPI_C2_SPLPIE_MASK This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3459 #define SPI_C2_SPLPIE_SHIFT This_symbol_has_been_deprecated
mbed_official 82:0b31dbcd4769 3460 #define UARTLP_Type UART0_Type
mbed_official 82:0b31dbcd4769 3461 #define UARTLP_BDH_REG UART0_BDH_REG
mbed_official 82:0b31dbcd4769 3462 #define UARTLP_BDL_REG UART0_BDL_REG
mbed_official 82:0b31dbcd4769 3463 #define UARTLP_C1_REG UART0_C1_REG
mbed_official 82:0b31dbcd4769 3464 #define UARTLP_C2_REG UART0_C2_REG
mbed_official 82:0b31dbcd4769 3465 #define UARTLP_S1_REG UART0_S1_REG
mbed_official 82:0b31dbcd4769 3466 #define UARTLP_S2_REG UART0_S2_REG
mbed_official 82:0b31dbcd4769 3467 #define UARTLP_C3_REG UART0_C3_REG
mbed_official 82:0b31dbcd4769 3468 #define UARTLP_D_REG UART0_D_REG
mbed_official 82:0b31dbcd4769 3469 #define UARTLP_MA1_REG UART0_MA1_REG
mbed_official 82:0b31dbcd4769 3470 #define UARTLP_MA2_REG UART0_MA2_REG
mbed_official 82:0b31dbcd4769 3471 #define UARTLP_C4_REG UART0_C4_REG
mbed_official 82:0b31dbcd4769 3472 #define UARTLP_C5_REG UART0_C5_REG
mbed_official 82:0b31dbcd4769 3473 #define UARTLP_BDH_SBR_MASK UART0_BDH_SBR_MASK
mbed_official 82:0b31dbcd4769 3474 #define UARTLP_BDH_SBR_SHIFT UART0_BDH_SBR_SHIFT
mbed_official 82:0b31dbcd4769 3475 #define UARTLP_BDH_SBR(x) UART0_BDH_SBR(x)
mbed_official 82:0b31dbcd4769 3476 #define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
mbed_official 82:0b31dbcd4769 3477 #define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
mbed_official 82:0b31dbcd4769 3478 #define UARTLP_BDH_RXEDGIE_MASK UART0_BDH_RXEDGIE_MASK
mbed_official 82:0b31dbcd4769 3479 #define UARTLP_BDH_RXEDGIE_SHIFT UART0_BDH_RXEDGIE_SHIFT
mbed_official 82:0b31dbcd4769 3480 #define UARTLP_BDH_LBKDIE_MASK UART0_BDH_LBKDIE_MASK
mbed_official 82:0b31dbcd4769 3481 #define UARTLP_BDH_LBKDIE_SHIFT UART0_BDH_LBKDIE_SHIFT
mbed_official 82:0b31dbcd4769 3482 #define UARTLP_BDL_SBR_MASK UART0_BDL_SBR_MASK
mbed_official 82:0b31dbcd4769 3483 #define UARTLP_BDL_SBR_SHIFT UART0_BDL_SBR_SHIFT
mbed_official 82:0b31dbcd4769 3484 #define UARTLP_BDL_SBR(x) UART0_BDL_SBR(x)
mbed_official 82:0b31dbcd4769 3485 #define UARTLP_C1_PT_MASK UART0_C1_PT_MASK
mbed_official 82:0b31dbcd4769 3486 #define UARTLP_C1_PT_SHIFT UART0_C1_PT_SHIFT
mbed_official 82:0b31dbcd4769 3487 #define UARTLP_C1_PE_MASK UART0_C1_PE_MASK
mbed_official 82:0b31dbcd4769 3488 #define UARTLP_C1_PE_SHIFT UART0_C1_PE_SHIFT
mbed_official 82:0b31dbcd4769 3489 #define UARTLP_C1_ILT_MASK UART0_C1_ILT_MASK
mbed_official 82:0b31dbcd4769 3490 #define UARTLP_C1_ILT_SHIFT UART0_C1_ILT_SHIFT
mbed_official 82:0b31dbcd4769 3491 #define UARTLP_C1_WAKE_MASK UART0_C1_WAKE_MASK
mbed_official 82:0b31dbcd4769 3492 #define UARTLP_C1_WAKE_SHIFT UART0_C1_WAKE_SHIFT
mbed_official 82:0b31dbcd4769 3493 #define UARTLP_C1_M_MASK UART0_C1_M_MASK
mbed_official 82:0b31dbcd4769 3494 #define UARTLP_C1_M_SHIFT UART0_C1_M_SHIFT
mbed_official 82:0b31dbcd4769 3495 #define UARTLP_C1_RSRC_MASK UART0_C1_RSRC_MASK
mbed_official 82:0b31dbcd4769 3496 #define UARTLP_C1_RSRC_SHIFT UART0_C1_RSRC_SHIFT
mbed_official 82:0b31dbcd4769 3497 #define UARTLP_C1_DOZEEN_MASK UART0_C1_DOZEEN_MASK
mbed_official 82:0b31dbcd4769 3498 #define UARTLP_C1_DOZEEN_SHIFT UART0_C1_DOZEEN_SHIFT
mbed_official 82:0b31dbcd4769 3499 #define UARTLP_C1_LOOPS_MASK UART0_C1_LOOPS_MASK
mbed_official 82:0b31dbcd4769 3500 #define UARTLP_C1_LOOPS_SHIFT UART0_C1_LOOPS_SHIFT
mbed_official 82:0b31dbcd4769 3501 #define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
mbed_official 82:0b31dbcd4769 3502 #define UARTLP_C2_SBK_SHIFT UART0_C2_SBK_SHIFT
mbed_official 82:0b31dbcd4769 3503 #define UARTLP_C2_RWU_MASK UART0_C2_RWU_MASK
mbed_official 82:0b31dbcd4769 3504 #define UARTLP_C2_RWU_SHIFT UART0_C2_RWU_SHIFT
mbed_official 82:0b31dbcd4769 3505 #define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
mbed_official 82:0b31dbcd4769 3506 #define UARTLP_C2_RE_SHIFT UART0_C2_RE_SHIFT
mbed_official 82:0b31dbcd4769 3507 #define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
mbed_official 82:0b31dbcd4769 3508 #define UARTLP_C2_TE_SHIFT UART0_C2_TE_SHIFT
mbed_official 82:0b31dbcd4769 3509 #define UARTLP_C2_ILIE_MASK UART0_C2_ILIE_MASK
mbed_official 82:0b31dbcd4769 3510 #define UARTLP_C2_ILIE_SHIFT UART0_C2_ILIE_SHIFT
mbed_official 82:0b31dbcd4769 3511 #define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
mbed_official 82:0b31dbcd4769 3512 #define UARTLP_C2_RIE_SHIFT UART0_C2_RIE_SHIFT
mbed_official 82:0b31dbcd4769 3513 #define UARTLP_C2_TCIE_MASK UART0_C2_TCIE_MASK
mbed_official 82:0b31dbcd4769 3514 #define UARTLP_C2_TCIE_SHIFT UART0_C2_TCIE_SHIFT
mbed_official 82:0b31dbcd4769 3515 #define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
mbed_official 82:0b31dbcd4769 3516 #define UARTLP_C2_TIE_SHIFT UART0_C2_TIE_SHIFT
mbed_official 82:0b31dbcd4769 3517 #define UARTLP_S1_PF_MASK UART0_S1_PF_MASK
mbed_official 82:0b31dbcd4769 3518 #define UARTLP_S1_PF_SHIFT UART0_S1_PF_SHIFT
mbed_official 82:0b31dbcd4769 3519 #define UARTLP_S1_FE_MASK UART0_S1_FE_MASK
mbed_official 82:0b31dbcd4769 3520 #define UARTLP_S1_FE_SHIFT UART0_S1_FE_SHIFT
mbed_official 82:0b31dbcd4769 3521 #define UARTLP_S1_NF_MASK UART0_S1_NF_MASK
mbed_official 82:0b31dbcd4769 3522 #define UARTLP_S1_NF_SHIFT UART0_S1_NF_SHIFT
mbed_official 82:0b31dbcd4769 3523 #define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
mbed_official 82:0b31dbcd4769 3524 #define UARTLP_S1_OR_SHIFT UART0_S1_OR_SHIFT
mbed_official 82:0b31dbcd4769 3525 #define UARTLP_S1_IDLE_MASK UART0_S1_IDLE_MASK
mbed_official 82:0b31dbcd4769 3526 #define UARTLP_S1_IDLE_SHIFT UART0_S1_IDLE_SHIFT
mbed_official 82:0b31dbcd4769 3527 #define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
mbed_official 82:0b31dbcd4769 3528 #define UARTLP_S1_RDRF_SHIFT UART0_S1_RDRF_SHIFT
mbed_official 82:0b31dbcd4769 3529 #define UARTLP_S1_TC_MASK UART0_S1_TC_MASK
mbed_official 82:0b31dbcd4769 3530 #define UARTLP_S1_TC_SHIFT UART0_S1_TC_SHIFT
mbed_official 82:0b31dbcd4769 3531 #define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
mbed_official 82:0b31dbcd4769 3532 #define UARTLP_S1_TDRE_SHIFT UART0_S1_TDRE_SHIFT
mbed_official 82:0b31dbcd4769 3533 #define UARTLP_S2_RAF_MASK UART0_S2_RAF_MASK
mbed_official 82:0b31dbcd4769 3534 #define UARTLP_S2_RAF_SHIFT UART0_S2_RAF_SHIFT
mbed_official 82:0b31dbcd4769 3535 #define UARTLP_S2_LBKDE_MASK UART0_S2_LBKDE_MASK
mbed_official 82:0b31dbcd4769 3536 #define UARTLP_S2_LBKDE_SHIFT UART0_S2_LBKDE_SHIFT
mbed_official 82:0b31dbcd4769 3537 #define UARTLP_S2_BRK13_MASK UART0_S2_BRK13_MASK
mbed_official 82:0b31dbcd4769 3538 #define UARTLP_S2_BRK13_SHIFT UART0_S2_BRK13_SHIFT
mbed_official 82:0b31dbcd4769 3539 #define UARTLP_S2_RWUID_MASK UART0_S2_RWUID_MASK
mbed_official 82:0b31dbcd4769 3540 #define UARTLP_S2_RWUID_SHIFT UART0_S2_RWUID_SHIFT
mbed_official 82:0b31dbcd4769 3541 #define UARTLP_S2_RXINV_MASK UART0_S2_RXINV_MASK
mbed_official 82:0b31dbcd4769 3542 #define UARTLP_S2_RXINV_SHIFT UART0_S2_RXINV_SHIFT
mbed_official 82:0b31dbcd4769 3543 #define UARTLP_S2_MSBF_MASK UART0_S2_MSBF_MASK
mbed_official 82:0b31dbcd4769 3544 #define UARTLP_S2_MSBF_SHIFT UART0_S2_MSBF_SHIFT
mbed_official 82:0b31dbcd4769 3545 #define UARTLP_S2_RXEDGIF_MASK UART0_S2_RXEDGIF_MASK
mbed_official 82:0b31dbcd4769 3546 #define UARTLP_S2_RXEDGIF_SHIFT UART0_S2_RXEDGIF_SHIFT
mbed_official 82:0b31dbcd4769 3547 #define UARTLP_S2_LBKDIF_MASK UART0_S2_LBKDIF_MASK
mbed_official 82:0b31dbcd4769 3548 #define UARTLP_S2_LBKDIF_SHIFT UART0_S2_LBKDIF_SHIFT
mbed_official 82:0b31dbcd4769 3549 #define UARTLP_C3_PEIE_MASK UART0_C3_PEIE_MASK
mbed_official 82:0b31dbcd4769 3550 #define UARTLP_C3_PEIE_SHIFT UART0_C3_PEIE_SHIFT
mbed_official 82:0b31dbcd4769 3551 #define UARTLP_C3_FEIE_MASK UART0_C3_FEIE_MASK
mbed_official 82:0b31dbcd4769 3552 #define UARTLP_C3_FEIE_SHIFT UART0_C3_FEIE_SHIFT
mbed_official 82:0b31dbcd4769 3553 #define UARTLP_C3_NEIE_MASK UART0_C3_NEIE_MASK
mbed_official 82:0b31dbcd4769 3554 #define UARTLP_C3_NEIE_SHIFT UART0_C3_NEIE_SHIFT
mbed_official 82:0b31dbcd4769 3555 #define UARTLP_C3_ORIE_MASK UART0_C3_ORIE_MASK
mbed_official 82:0b31dbcd4769 3556 #define UARTLP_C3_ORIE_SHIFT UART0_C3_ORIE_SHIFT
mbed_official 82:0b31dbcd4769 3557 #define UARTLP_C3_TXINV_MASK UART0_C3_TXINV_MASK
mbed_official 82:0b31dbcd4769 3558 #define UARTLP_C3_TXINV_SHIFT UART0_C3_TXINV_SHIFT
mbed_official 82:0b31dbcd4769 3559 #define UARTLP_C3_TXDIR_MASK UART0_C3_TXDIR_MASK
mbed_official 82:0b31dbcd4769 3560 #define UARTLP_C3_TXDIR_SHIFT UART0_C3_TXDIR_SHIFT
mbed_official 82:0b31dbcd4769 3561 #define UARTLP_C3_R9T8_MASK UART0_C3_R9T8_MASK
mbed_official 82:0b31dbcd4769 3562 #define UARTLP_C3_R9T8_SHIFT UART0_C3_R9T8_SHIFT
mbed_official 82:0b31dbcd4769 3563 #define UARTLP_C3_R8T9_MASK UART0_C3_R8T9_MASK
mbed_official 82:0b31dbcd4769 3564 #define UARTLP_C3_R8T9_SHIFT UART0_C3_R8T9_SHIFT
mbed_official 82:0b31dbcd4769 3565 #define UARTLP_D_R0T0_MASK UART0_D_R0T0_MASK
mbed_official 82:0b31dbcd4769 3566 #define UARTLP_D_R0T0_SHIFT UART0_D_R0T0_SHIFT
mbed_official 82:0b31dbcd4769 3567 #define UARTLP_D_R1T1_MASK UART0_D_R1T1_MASK
mbed_official 82:0b31dbcd4769 3568 #define UARTLP_D_R1T1_SHIFT UART0_D_R1T1_SHIFT
mbed_official 82:0b31dbcd4769 3569 #define UARTLP_D_R2T2_MASK UART0_D_R2T2_MASK
mbed_official 82:0b31dbcd4769 3570 #define UARTLP_D_R2T2_SHIFT UART0_D_R2T2_SHIFT
mbed_official 82:0b31dbcd4769 3571 #define UARTLP_D_R3T3_MASK UART0_D_R3T3_MASK
mbed_official 82:0b31dbcd4769 3572 #define UARTLP_D_R3T3_SHIFT UART0_D_R3T3_SHIFT
mbed_official 82:0b31dbcd4769 3573 #define UARTLP_D_R4T4_MASK UART0_D_R4T4_MASK
mbed_official 82:0b31dbcd4769 3574 #define UARTLP_D_R4T4_SHIFT UART0_D_R4T4_SHIFT
mbed_official 82:0b31dbcd4769 3575 #define UARTLP_D_R5T5_MASK UART0_D_R5T5_MASK
mbed_official 82:0b31dbcd4769 3576 #define UARTLP_D_R5T5_SHIFT UART0_D_R5T5_SHIFT
mbed_official 82:0b31dbcd4769 3577 #define UARTLP_D_R6T6_MASK UART0_D_R6T6_MASK
mbed_official 82:0b31dbcd4769 3578 #define UARTLP_D_R6T6_SHIFT UART0_D_R6T6_SHIFT
mbed_official 82:0b31dbcd4769 3579 #define UARTLP_D_R7T7_MASK UART0_D_R7T7_MASK
mbed_official 82:0b31dbcd4769 3580 #define UARTLP_D_R7T7_SHIFT UART0_D_R7T7_SHIFT
mbed_official 82:0b31dbcd4769 3581 #define UARTLP_MA1_MA_MASK UART0_MA1_MA_MASK
mbed_official 82:0b31dbcd4769 3582 #define UARTLP_MA1_MA_SHIFT UART0_MA1_MA_SHIFT
mbed_official 82:0b31dbcd4769 3583 #define UARTLP_MA1_MA(x) UART0_MA1_MA(x)
mbed_official 82:0b31dbcd4769 3584 #define UARTLP_MA2_MA_MASK UART0_MA2_MA_MASK
mbed_official 82:0b31dbcd4769 3585 #define UARTLP_MA2_MA_SHIFT UART0_MA2_MA_SHIFT
mbed_official 82:0b31dbcd4769 3586 #define UARTLP_MA2_MA(x) UART0_MA2_MA(x)
mbed_official 82:0b31dbcd4769 3587 #define UARTLP_C4_OSR_MASK UART0_C4_OSR_MASK
mbed_official 82:0b31dbcd4769 3588 #define UARTLP_C4_OSR_SHIFT UART0_C4_OSR_SHIFT
mbed_official 82:0b31dbcd4769 3589 #define UARTLP_C4_OSR(x) UART0_C4_OSR(x)
mbed_official 82:0b31dbcd4769 3590 #define UARTLP_C4_M10_MASK UART0_C4_M10_MASK
mbed_official 82:0b31dbcd4769 3591 #define UARTLP_C4_M10_SHIFT UART0_C4_M10_SHIFT
mbed_official 82:0b31dbcd4769 3592 #define UARTLP_C4_MAEN2_MASK UART0_C4_MAEN2_MASK
mbed_official 82:0b31dbcd4769 3593 #define UARTLP_C4_MAEN2_SHIFT UART0_C4_MAEN2_SHIFT
mbed_official 82:0b31dbcd4769 3594 #define UARTLP_C4_MAEN1_MASK UART0_C4_MAEN1_MASK
mbed_official 82:0b31dbcd4769 3595 #define UARTLP_C4_MAEN1_SHIFT UART0_C4_MAEN1_SHIFT
mbed_official 82:0b31dbcd4769 3596 #define UARTLP_C5_RESYNCDIS_MASK UART0_C5_RESYNCDIS_MASK
mbed_official 82:0b31dbcd4769 3597 #define UARTLP_C5_RESYNCDIS_SHIFT UART0_C5_RESYNCDIS_SHIFT
mbed_official 82:0b31dbcd4769 3598 #define UARTLP_C5_BOTHEDGE_MASK UART0_C5_BOTHEDGE_MASK
mbed_official 82:0b31dbcd4769 3599 #define UARTLP_C5_BOTHEDGE_SHIFT UART0_C5_BOTHEDGE_SHIFT
mbed_official 82:0b31dbcd4769 3600 #define UARTLP_C5_RDMAE_MASK UART0_C5_RDMAE_MASK
mbed_official 82:0b31dbcd4769 3601 #define UARTLP_C5_RDMAE_SHIFT UART0_C5_RDMAE_SHIFT
mbed_official 82:0b31dbcd4769 3602 #define UARTLP_C5_TDMAE_MASK UART0_C5_TDMAE_MASK
mbed_official 82:0b31dbcd4769 3603 #define UARTLP_C5_TDMAE_SHIFT UART0_C5_TDMAE_SHIFT
mbed_official 82:0b31dbcd4769 3604 #define UARTLP_BASES UARTLP_BASES
mbed_official 82:0b31dbcd4769 3605
mbed_official 82:0b31dbcd4769 3606 /**
mbed_official 82:0b31dbcd4769 3607 * @}
mbed_official 82:0b31dbcd4769 3608 */ /* end of group Backward_Compatibility_Symbols */
mbed_official 82:0b31dbcd4769 3609
mbed_official 82:0b31dbcd4769 3610
mbed_official 82:0b31dbcd4769 3611 #endif /* #if !defined(MKL05Z4_H_) */
mbed_official 82:0b31dbcd4769 3612
mbed_official 82:0b31dbcd4769 3613 /* MKL05Z4.h, eof. */