Project5_Software / RTOS

Versie 0.2 Het versturen via de NRF werkt nog niet helemaal omdat er per 4 bytes verstuurd moet worden. Wordt gefixt d.m.v. dynamic stuff!

Dependencies:   BufferedSerial

Dependents:   rtos_basic rtos_basic

Fork of mbed-rtos by mbed official

rtx/TARGET_CORTEX_M/rt_HAL_CM.h@49:77c8e4604045, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 13:00:11 2014 +0000
Revision:
49:77c8e4604045
Synchronized with git revision 7b90c2ba137baaf9769219e0e8a7b8e8d1299c4f



Full URL: https://github.com/mbedmicro/mbed/commit/7b90c2ba137baaf9769219e0e8a7b8e8d1299c4f/



This target is not yet tested, so it can't be released as part of the official

SDK build for now.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 49:77c8e4604045 1 /*----------------------------------------------------------------------------
mbed_official 49:77c8e4604045 2 * RL-ARM - RTX
mbed_official 49:77c8e4604045 3 *----------------------------------------------------------------------------
mbed_official 49:77c8e4604045 4 * Name: RT_HAL_CM.H
mbed_official 49:77c8e4604045 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
mbed_official 49:77c8e4604045 6 * Rev.: V4.60
mbed_official 49:77c8e4604045 7 *----------------------------------------------------------------------------
mbed_official 49:77c8e4604045 8 *
mbed_official 49:77c8e4604045 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
mbed_official 49:77c8e4604045 10 * All rights reserved.
mbed_official 49:77c8e4604045 11 * Redistribution and use in source and binary forms, with or without
mbed_official 49:77c8e4604045 12 * modification, are permitted provided that the following conditions are met:
mbed_official 49:77c8e4604045 13 * - Redistributions of source code must retain the above copyright
mbed_official 49:77c8e4604045 14 * notice, this list of conditions and the following disclaimer.
mbed_official 49:77c8e4604045 15 * - Redistributions in binary form must reproduce the above copyright
mbed_official 49:77c8e4604045 16 * notice, this list of conditions and the following disclaimer in the
mbed_official 49:77c8e4604045 17 * documentation and/or other materials provided with the distribution.
mbed_official 49:77c8e4604045 18 * - Neither the name of ARM nor the names of its contributors may be used
mbed_official 49:77c8e4604045 19 * to endorse or promote products derived from this software without
mbed_official 49:77c8e4604045 20 * specific prior written permission.
mbed_official 49:77c8e4604045 21 *
mbed_official 49:77c8e4604045 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 49:77c8e4604045 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 49:77c8e4604045 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 49:77c8e4604045 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 49:77c8e4604045 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 49:77c8e4604045 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 49:77c8e4604045 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 49:77c8e4604045 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 49:77c8e4604045 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 49:77c8e4604045 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 49:77c8e4604045 32 * POSSIBILITY OF SUCH DAMAGE.
mbed_official 49:77c8e4604045 33 *---------------------------------------------------------------------------*/
mbed_official 49:77c8e4604045 34
mbed_official 49:77c8e4604045 35 /* Definitions */
mbed_official 49:77c8e4604045 36 #define INITIAL_xPSR 0x01000000
mbed_official 49:77c8e4604045 37 #define DEMCR_TRCENA 0x01000000
mbed_official 49:77c8e4604045 38 #define ITM_ITMENA 0x00000001
mbed_official 49:77c8e4604045 39 #define MAGIC_WORD 0xE25A2EA5
mbed_official 49:77c8e4604045 40
mbed_official 49:77c8e4604045 41 #if defined (__CC_ARM) /* ARM Compiler */
mbed_official 49:77c8e4604045 42
mbed_official 49:77c8e4604045 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
mbed_official 49:77c8e4604045 44 #define __USE_EXCLUSIVE_ACCESS
mbed_official 49:77c8e4604045 45 #else
mbed_official 49:77c8e4604045 46 #undef __USE_EXCLUSIVE_ACCESS
mbed_official 49:77c8e4604045 47 #endif
mbed_official 49:77c8e4604045 48
mbed_official 49:77c8e4604045 49 #elif defined (__GNUC__) /* GNU Compiler */
mbed_official 49:77c8e4604045 50
mbed_official 49:77c8e4604045 51 #undef __USE_EXCLUSIVE_ACCESS
mbed_official 49:77c8e4604045 52
mbed_official 49:77c8e4604045 53 #if defined (__CORTEX_M0) || defined (__CORTEX_M0PLUS)
mbed_official 49:77c8e4604045 54 #define __TARGET_ARCH_6S_M 1
mbed_official 49:77c8e4604045 55 #else
mbed_official 49:77c8e4604045 56 #define __TARGET_ARCH_6S_M 0
mbed_official 49:77c8e4604045 57 #endif
mbed_official 49:77c8e4604045 58
mbed_official 49:77c8e4604045 59 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official 49:77c8e4604045 60 #define __TARGET_FPU_VFP 1
mbed_official 49:77c8e4604045 61 #else
mbed_official 49:77c8e4604045 62 #define __TARGET_FPU_VFP 0
mbed_official 49:77c8e4604045 63 #endif
mbed_official 49:77c8e4604045 64
mbed_official 49:77c8e4604045 65 #define __inline inline
mbed_official 49:77c8e4604045 66 #define __weak __attribute__((weak))
mbed_official 49:77c8e4604045 67
mbed_official 49:77c8e4604045 68 #ifndef __CMSIS_GENERIC
mbed_official 49:77c8e4604045 69
mbed_official 49:77c8e4604045 70 __attribute__((always_inline)) static inline void __enable_irq(void)
mbed_official 49:77c8e4604045 71 {
mbed_official 49:77c8e4604045 72 __asm volatile ("cpsie i");
mbed_official 49:77c8e4604045 73 }
mbed_official 49:77c8e4604045 74
mbed_official 49:77c8e4604045 75 __attribute__((always_inline)) static inline U32 __disable_irq(void)
mbed_official 49:77c8e4604045 76 {
mbed_official 49:77c8e4604045 77 U32 result;
mbed_official 49:77c8e4604045 78
mbed_official 49:77c8e4604045 79 __asm volatile ("mrs %0, primask" : "=r" (result));
mbed_official 49:77c8e4604045 80 __asm volatile ("cpsid i");
mbed_official 49:77c8e4604045 81 return(result & 1);
mbed_official 49:77c8e4604045 82 }
mbed_official 49:77c8e4604045 83
mbed_official 49:77c8e4604045 84 #endif
mbed_official 49:77c8e4604045 85
mbed_official 49:77c8e4604045 86 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
mbed_official 49:77c8e4604045 87 {
mbed_official 49:77c8e4604045 88 U8 result;
mbed_official 49:77c8e4604045 89
mbed_official 49:77c8e4604045 90 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
mbed_official 49:77c8e4604045 91 return(result);
mbed_official 49:77c8e4604045 92 }
mbed_official 49:77c8e4604045 93
mbed_official 49:77c8e4604045 94 #elif defined (__ICCARM__) /* IAR Compiler */
mbed_official 49:77c8e4604045 95
mbed_official 49:77c8e4604045 96 #undef __USE_EXCLUSIVE_ACCESS
mbed_official 49:77c8e4604045 97
mbed_official 49:77c8e4604045 98 #if (__CORE__ == __ARM6M__)
mbed_official 49:77c8e4604045 99 #define __TARGET_ARCH_6S_M 1
mbed_official 49:77c8e4604045 100 #else
mbed_official 49:77c8e4604045 101 #define __TARGET_ARCH_6S_M 0
mbed_official 49:77c8e4604045 102 #endif
mbed_official 49:77c8e4604045 103
mbed_official 49:77c8e4604045 104 #if defined __ARMVFP__
mbed_official 49:77c8e4604045 105 #define __TARGET_FPU_VFP 1
mbed_official 49:77c8e4604045 106 #else
mbed_official 49:77c8e4604045 107 #define __TARGET_FPU_VFP 0
mbed_official 49:77c8e4604045 108 #endif
mbed_official 49:77c8e4604045 109
mbed_official 49:77c8e4604045 110 #define __inline inline
mbed_official 49:77c8e4604045 111
mbed_official 49:77c8e4604045 112 #ifndef __CMSIS_GENERIC
mbed_official 49:77c8e4604045 113
mbed_official 49:77c8e4604045 114 static inline void __enable_irq(void)
mbed_official 49:77c8e4604045 115 {
mbed_official 49:77c8e4604045 116 __asm volatile ("cpsie i");
mbed_official 49:77c8e4604045 117 }
mbed_official 49:77c8e4604045 118
mbed_official 49:77c8e4604045 119 static inline U32 __disable_irq(void)
mbed_official 49:77c8e4604045 120 {
mbed_official 49:77c8e4604045 121 U32 result;
mbed_official 49:77c8e4604045 122
mbed_official 49:77c8e4604045 123 __asm volatile ("mrs %0, primask" : "=r" (result));
mbed_official 49:77c8e4604045 124 __asm volatile ("cpsid i");
mbed_official 49:77c8e4604045 125 return(result & 1);
mbed_official 49:77c8e4604045 126 }
mbed_official 49:77c8e4604045 127
mbed_official 49:77c8e4604045 128 #endif
mbed_official 49:77c8e4604045 129
mbed_official 49:77c8e4604045 130 static inline U8 __clz(U32 value)
mbed_official 49:77c8e4604045 131 {
mbed_official 49:77c8e4604045 132 U8 result;
mbed_official 49:77c8e4604045 133
mbed_official 49:77c8e4604045 134 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
mbed_official 49:77c8e4604045 135 return(result);
mbed_official 49:77c8e4604045 136 }
mbed_official 49:77c8e4604045 137
mbed_official 49:77c8e4604045 138 #endif
mbed_official 49:77c8e4604045 139
mbed_official 49:77c8e4604045 140 /* NVIC registers */
mbed_official 49:77c8e4604045 141 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
mbed_official 49:77c8e4604045 142 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
mbed_official 49:77c8e4604045 143 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
mbed_official 49:77c8e4604045 144 #define NVIC_ISER ((volatile U32 *)0xE000E100)
mbed_official 49:77c8e4604045 145 #define NVIC_ICER ((volatile U32 *)0xE000E180)
mbed_official 49:77c8e4604045 146 #if (__TARGET_ARCH_6S_M)
mbed_official 49:77c8e4604045 147 #define NVIC_IP ((volatile U32 *)0xE000E400)
mbed_official 49:77c8e4604045 148 #else
mbed_official 49:77c8e4604045 149 #define NVIC_IP ((volatile U8 *)0xE000E400)
mbed_official 49:77c8e4604045 150 #endif
mbed_official 49:77c8e4604045 151 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
mbed_official 49:77c8e4604045 152 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
mbed_official 49:77c8e4604045 153 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
mbed_official 49:77c8e4604045 154 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
mbed_official 49:77c8e4604045 155
mbed_official 49:77c8e4604045 156 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
mbed_official 49:77c8e4604045 157 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
mbed_official 49:77c8e4604045 158 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
mbed_official 49:77c8e4604045 159 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
mbed_official 49:77c8e4604045 160 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
mbed_official 49:77c8e4604045 161 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
mbed_official 49:77c8e4604045 162
mbed_official 49:77c8e4604045 163 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
mbed_official 49:77c8e4604045 164 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
mbed_official 49:77c8e4604045 165 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
mbed_official 49:77c8e4604045 166 #if (__TARGET_ARCH_6S_M)
mbed_official 49:77c8e4604045 167 #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
mbed_official 49:77c8e4604045 168 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
mbed_official 49:77c8e4604045 169 #else
mbed_official 49:77c8e4604045 170 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
mbed_official 49:77c8e4604045 171 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
mbed_official 49:77c8e4604045 172 #endif
mbed_official 49:77c8e4604045 173 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
mbed_official 49:77c8e4604045 174 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
mbed_official 49:77c8e4604045 175
mbed_official 49:77c8e4604045 176 /* Core Debug registers */
mbed_official 49:77c8e4604045 177 #define DEMCR (*((volatile U32 *)0xE000EDFC))
mbed_official 49:77c8e4604045 178
mbed_official 49:77c8e4604045 179 /* ITM registers */
mbed_official 49:77c8e4604045 180 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
mbed_official 49:77c8e4604045 181 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
mbed_official 49:77c8e4604045 182 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
mbed_official 49:77c8e4604045 183 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
mbed_official 49:77c8e4604045 184 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
mbed_official 49:77c8e4604045 185 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
mbed_official 49:77c8e4604045 186
mbed_official 49:77c8e4604045 187 /* Variables */
mbed_official 49:77c8e4604045 188 extern BIT dbg_msg;
mbed_official 49:77c8e4604045 189
mbed_official 49:77c8e4604045 190 /* Functions */
mbed_official 49:77c8e4604045 191 #ifdef __USE_EXCLUSIVE_ACCESS
mbed_official 49:77c8e4604045 192 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
mbed_official 49:77c8e4604045 193 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
mbed_official 49:77c8e4604045 194 #else
mbed_official 49:77c8e4604045 195 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
mbed_official 49:77c8e4604045 196 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
mbed_official 49:77c8e4604045 197 #endif
mbed_official 49:77c8e4604045 198
mbed_official 49:77c8e4604045 199 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
mbed_official 49:77c8e4604045 200 U32 cnt,c2;
mbed_official 49:77c8e4604045 201 #ifdef __USE_EXCLUSIVE_ACCESS
mbed_official 49:77c8e4604045 202 do {
mbed_official 49:77c8e4604045 203 if ((cnt = __ldrex(count)) == size) {
mbed_official 49:77c8e4604045 204 __clrex();
mbed_official 49:77c8e4604045 205 return (cnt); }
mbed_official 49:77c8e4604045 206 } while (__strex(cnt+1, count));
mbed_official 49:77c8e4604045 207 do {
mbed_official 49:77c8e4604045 208 c2 = (cnt = __ldrex(first)) + 1;
mbed_official 49:77c8e4604045 209 if (c2 == size) c2 = 0;
mbed_official 49:77c8e4604045 210 } while (__strex(c2, first));
mbed_official 49:77c8e4604045 211 #else
mbed_official 49:77c8e4604045 212 __disable_irq();
mbed_official 49:77c8e4604045 213 if ((cnt = *count) < size) {
mbed_official 49:77c8e4604045 214 *count = cnt+1;
mbed_official 49:77c8e4604045 215 c2 = (cnt = *first) + 1;
mbed_official 49:77c8e4604045 216 if (c2 == size) c2 = 0;
mbed_official 49:77c8e4604045 217 *first = c2;
mbed_official 49:77c8e4604045 218 }
mbed_official 49:77c8e4604045 219 __enable_irq ();
mbed_official 49:77c8e4604045 220 #endif
mbed_official 49:77c8e4604045 221 return (cnt);
mbed_official 49:77c8e4604045 222 }
mbed_official 49:77c8e4604045 223
mbed_official 49:77c8e4604045 224 __inline static void rt_systick_init (void) {
mbed_official 49:77c8e4604045 225 NVIC_ST_RELOAD = os_trv;
mbed_official 49:77c8e4604045 226 NVIC_ST_CURRENT = 0;
mbed_official 49:77c8e4604045 227 NVIC_ST_CTRL = 0x0007;
mbed_official 49:77c8e4604045 228 NVIC_SYS_PRI3 |= 0xFF000000;
mbed_official 49:77c8e4604045 229 }
mbed_official 49:77c8e4604045 230
mbed_official 49:77c8e4604045 231 __inline static void rt_svc_init (void) {
mbed_official 49:77c8e4604045 232 #if !(__TARGET_ARCH_6S_M)
mbed_official 49:77c8e4604045 233 int sh,prigroup;
mbed_official 49:77c8e4604045 234 #endif
mbed_official 49:77c8e4604045 235 NVIC_SYS_PRI3 |= 0x00FF0000;
mbed_official 49:77c8e4604045 236 #if (__TARGET_ARCH_6S_M)
mbed_official 49:77c8e4604045 237 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
mbed_official 49:77c8e4604045 238 #else
mbed_official 49:77c8e4604045 239 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
mbed_official 49:77c8e4604045 240 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
mbed_official 49:77c8e4604045 241 if (prigroup >= sh) {
mbed_official 49:77c8e4604045 242 sh = prigroup + 1;
mbed_official 49:77c8e4604045 243 }
mbed_official 49:77c8e4604045 244 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
mbed_official 49:77c8e4604045 245 #endif
mbed_official 49:77c8e4604045 246 }
mbed_official 49:77c8e4604045 247
mbed_official 49:77c8e4604045 248 extern void rt_set_PSP (U32 stack);
mbed_official 49:77c8e4604045 249 extern U32 rt_get_PSP (void);
mbed_official 49:77c8e4604045 250 extern void os_set_env (void);
mbed_official 49:77c8e4604045 251 extern void *_alloc_box (void *box_mem);
mbed_official 49:77c8e4604045 252 extern int _free_box (void *box_mem, void *box);
mbed_official 49:77c8e4604045 253
mbed_official 49:77c8e4604045 254 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
mbed_official 49:77c8e4604045 255 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
mbed_official 49:77c8e4604045 256 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
mbed_official 49:77c8e4604045 257
mbed_official 49:77c8e4604045 258 extern void dbg_init (void);
mbed_official 49:77c8e4604045 259 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
mbed_official 49:77c8e4604045 260 extern void dbg_task_switch (U32 task_id);
mbed_official 49:77c8e4604045 261
mbed_official 49:77c8e4604045 262 #ifdef DBG_MSG
mbed_official 49:77c8e4604045 263 #define DBG_INIT() dbg_init()
mbed_official 49:77c8e4604045 264 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
mbed_official 49:77c8e4604045 265 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
mbed_official 49:77c8e4604045 266 dbg_task_switch(task_id)
mbed_official 49:77c8e4604045 267 #else
mbed_official 49:77c8e4604045 268 #define DBG_INIT()
mbed_official 49:77c8e4604045 269 #define DBG_TASK_NOTIFY(p_tcb,create)
mbed_official 49:77c8e4604045 270 #define DBG_TASK_SWITCH(task_id)
mbed_official 49:77c8e4604045 271 #endif
mbed_official 49:77c8e4604045 272
mbed_official 49:77c8e4604045 273 /*----------------------------------------------------------------------------
mbed_official 49:77c8e4604045 274 * end of file
mbed_official 49:77c8e4604045 275 *---------------------------------------------------------------------------*/
mbed_official 49:77c8e4604045 276