max3133x - Driver for MAX31331 and MAX31334 Real Time Clock …

Maxim Integrated » Code » max3133x

Driver for MAX31331 and MAX31334 Real Time Clock ICs.

max3133x.cpp@0:4a2754e462db, 22 months ago (annotated)

Committer:: Sinan Divarci
Date:: Tue Aug 02 18:20:54 2022 +0300
Revision:: 0:4a2754e462db

Initial Commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
Sinan Divarci	0:4a2754e462db	1	/*******************************************************************************
Sinan Divarci	0:4a2754e462db	2	* Copyright(C) Analog Devices Inc., All Rights Reserved.
Sinan Divarci	0:4a2754e462db	3	*
Sinan Divarci	0:4a2754e462db	4	* Permission is hereby granted, free of charge, to any person obtaining a
Sinan Divarci	0:4a2754e462db	5	* copy of this software and associated documentation files(the "Software"),
Sinan Divarci	0:4a2754e462db	6	* to deal in the Software without restriction, including without limitation
Sinan Divarci	0:4a2754e462db	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
Sinan Divarci	0:4a2754e462db	8	* and/or sell copies of the Software, and to permit persons to whom the
Sinan Divarci	0:4a2754e462db	9	* Software is furnished to do so, subject to the following conditions:
Sinan Divarci	0:4a2754e462db	10	*
Sinan Divarci	0:4a2754e462db	11	* The above copyright notice and this permission notice shall be included
Sinan Divarci	0:4a2754e462db	12	* in all copies or substantial portions of the Software.
Sinan Divarci	0:4a2754e462db	13	*
Sinan Divarci	0:4a2754e462db	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Sinan Divarci	0:4a2754e462db	15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Sinan Divarci	0:4a2754e462db	16	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Sinan Divarci	0:4a2754e462db	17	* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Sinan Divarci	0:4a2754e462db	18	* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Sinan Divarci	0:4a2754e462db	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Sinan Divarci	0:4a2754e462db	20	* OTHER DEALINGS IN THE SOFTWARE.
Sinan Divarci	0:4a2754e462db	21	*
Sinan Divarci	0:4a2754e462db	22	* Except as contained in this notice, the name of Analog Devices Inc.
Sinan Divarci	0:4a2754e462db	23	* shall not be used except as stated in the Analog Devices Inc.
Sinan Divarci	0:4a2754e462db	24	* Branding Policy.
Sinan Divarci	0:4a2754e462db	25	*
Sinan Divarci	0:4a2754e462db	26	* The mere transfer of this software does not imply any licenses
Sinan Divarci	0:4a2754e462db	27	* of trade secrets, proprietary technology, copyrights, patents,
Sinan Divarci	0:4a2754e462db	28	* trademarks, maskwork rights, or any other form of intellectual
Sinan Divarci	0:4a2754e462db	29	* property whatsoever. Analog Devices Inc.retains all ownership rights.
Sinan Divarci	0:4a2754e462db	30	*******************************************************************************
Sinan Divarci	0:4a2754e462db	31	*/
Sinan Divarci	0:4a2754e462db	32
Sinan Divarci	0:4a2754e462db	33	#include "max3133x.hpp"
Sinan Divarci	0:4a2754e462db	34	#include <iostream>
Sinan Divarci	0:4a2754e462db	35
Sinan Divarci	0:4a2754e462db	36	#define pr_err(fmt, ...) if(1) printf(fmt " (%s:%d)\r\n", ## __VA_ARGS__, __func__, __LINE__)
Sinan Divarci	0:4a2754e462db	37	#define pr_debug(fmt, ...) if(0) printf(fmt " (%s:%d)\r\n", ## __VA_ARGS__, __func__, __LINE__)
Sinan Divarci	0:4a2754e462db	38
Sinan Divarci	0:4a2754e462db	39	#define BCD2BIN(val) (((val) & 15) + ((val) >> 4) * 10)
Sinan Divarci	0:4a2754e462db	40	#define BIN2BCD(val) ((((val) / 10) << 4) + (val) % 10)
Sinan Divarci	0:4a2754e462db	41	#define SWAPBYTES(val) (((val & 0xFF) << 8) \| ((val & 0xFF00) >> 8))
Sinan Divarci	0:4a2754e462db	42
Sinan Divarci	0:4a2754e462db	43	#define POST_INTR_WORK_SIGNAL_ID 0x1
Sinan Divarci	0:4a2754e462db	44
Sinan Divarci	0:4a2754e462db	45	MAX3133X::MAX3133X(const reg_addr_t reg_addr, I2C i2c, PinName inta_pin, PinName intb_pin)
Sinan Divarci	0:4a2754e462db	46	{
Sinan Divarci	0:4a2754e462db	47	int ret;
Sinan Divarci	0:4a2754e462db	48	if (i2c == NULL \|\| reg_addr == NULL) {
Sinan Divarci	0:4a2754e462db	49	pr_err("i2c object is invalid!");
Sinan Divarci	0:4a2754e462db	50	return;
Sinan Divarci	0:4a2754e462db	51	}
Sinan Divarci	0:4a2754e462db	52
Sinan Divarci	0:4a2754e462db	53	this->reg_addr = reg_addr;
Sinan Divarci	0:4a2754e462db	54	i2c_handler = i2c;
Sinan Divarci	0:4a2754e462db	55
Sinan Divarci	0:4a2754e462db	56	ret = interrupt_disable(INT_ALL);
Sinan Divarci	0:4a2754e462db	57	if (ret != MAX3133X_NO_ERR) {
Sinan Divarci	0:4a2754e462db	58	pr_err("interrupt_disable failed!");
Sinan Divarci	0:4a2754e462db	59	return;
Sinan Divarci	0:4a2754e462db	60	}
Sinan Divarci	0:4a2754e462db	61
Sinan Divarci	0:4a2754e462db	62	for (int i = 0; i < NUM_OF_INTR_ID; i++) {
Sinan Divarci	0:4a2754e462db	63	interrupt_handler_list[i].func = NULL;
Sinan Divarci	0:4a2754e462db	64	interrupt_handler_list[i].cb = NULL;
Sinan Divarci	0:4a2754e462db	65	}
Sinan Divarci	0:4a2754e462db	66
Sinan Divarci	0:4a2754e462db	67	if (inta_pin != NC) {
Sinan Divarci	0:4a2754e462db	68	this->inta_pin = new InterruptIn(inta_pin);
Sinan Divarci	0:4a2754e462db	69	this->inta_pin->fall(Callback<void()>(this, &MAX3133X::interrupt_handler));
Sinan Divarci	0:4a2754e462db	70	this->inta_pin->enable_irq();
Sinan Divarci	0:4a2754e462db	71	} else
Sinan Divarci	0:4a2754e462db	72	this->inta_pin = NULL;
Sinan Divarci	0:4a2754e462db	73
Sinan Divarci	0:4a2754e462db	74	if (intb_pin != NC) {
Sinan Divarci	0:4a2754e462db	75	this->intb_pin = new InterruptIn(intb_pin);
Sinan Divarci	0:4a2754e462db	76	this->intb_pin->fall(Callback<void()>(this, &MAX3133X::interrupt_handler));
Sinan Divarci	0:4a2754e462db	77	this->intb_pin->enable_irq();
Sinan Divarci	0:4a2754e462db	78	} else
Sinan Divarci	0:4a2754e462db	79	this->intb_pin = NULL;
Sinan Divarci	0:4a2754e462db	80
Sinan Divarci	0:4a2754e462db	81	if (inta_pin != NC \|\| intb_pin != NC)
Sinan Divarci	0:4a2754e462db	82	{
Sinan Divarci	0:4a2754e462db	83	post_intr_work_thread = new Thread();
Sinan Divarci	0:4a2754e462db	84	post_intr_work_thread->start(Callback<void()>(this, &MAX3133X::post_interrupt_work));
Sinan Divarci	0:4a2754e462db	85	}
Sinan Divarci	0:4a2754e462db	86	}
Sinan Divarci	0:4a2754e462db	87
Sinan Divarci	0:4a2754e462db	88	int MAX3133X::read_register(uint8_t reg, uint8_t *value, uint8_t len)
Sinan Divarci	0:4a2754e462db	89	{
Sinan Divarci	0:4a2754e462db	90	int rtn_val;
Sinan Divarci	0:4a2754e462db	91
Sinan Divarci	0:4a2754e462db	92	if (value == NULL)
Sinan Divarci	0:4a2754e462db	93	return MAX3133X_NULL_VALUE_ERR;
Sinan Divarci	0:4a2754e462db	94
Sinan Divarci	0:4a2754e462db	95	rtn_val = i2c_handler->write(MAX3133X_I2C_W, (const char *)&reg, 1, true);
Sinan Divarci	0:4a2754e462db	96	if (rtn_val != 0)
Sinan Divarci	0:4a2754e462db	97	return MAX3133X_WRITE_REG_ERR;
Sinan Divarci	0:4a2754e462db	98
Sinan Divarci	0:4a2754e462db	99	rtn_val = i2c_handler->read(MAX3133X_I2C_R, (char *) value, len, false);
Sinan Divarci	0:4a2754e462db	100	if (rtn_val != 0)
Sinan Divarci	0:4a2754e462db	101	return MAX3133X_READ_REG_ERR;
Sinan Divarci	0:4a2754e462db	102
Sinan Divarci	0:4a2754e462db	103	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	104	}
Sinan Divarci	0:4a2754e462db	105
Sinan Divarci	0:4a2754e462db	106	int MAX3133X::write_register(uint8_t reg, const uint8_t *value, uint8_t len)
Sinan Divarci	0:4a2754e462db	107	{
Sinan Divarci	0:4a2754e462db	108	int rtn_val;
Sinan Divarci	0:4a2754e462db	109	uint8_t *local_data;
Sinan Divarci	0:4a2754e462db	110
Sinan Divarci	0:4a2754e462db	111	if (value == NULL)
Sinan Divarci	0:4a2754e462db	112	return MAX3133X_NULL_VALUE_ERR;
Sinan Divarci	0:4a2754e462db	113
Sinan Divarci	0:4a2754e462db	114	local_data = new uint8_t[1 + len];
Sinan Divarci	0:4a2754e462db	115	local_data[0] = reg;
Sinan Divarci	0:4a2754e462db	116
Sinan Divarci	0:4a2754e462db	117	memcpy(&local_data[1], value, len);
Sinan Divarci	0:4a2754e462db	118
Sinan Divarci	0:4a2754e462db	119	rtn_val = i2c_handler->write(MAX3133X_I2C_W, (const char *)local_data, 1 + len);
Sinan Divarci	0:4a2754e462db	120	delete[] local_data; //delete local_data anymore not used
Sinan Divarci	0:4a2754e462db	121
Sinan Divarci	0:4a2754e462db	122	if (rtn_val != 0)
Sinan Divarci	0:4a2754e462db	123	return MAX3133X_WRITE_REG_ERR;
Sinan Divarci	0:4a2754e462db	124
Sinan Divarci	0:4a2754e462db	125	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	126	}
Sinan Divarci	0:4a2754e462db	127
Sinan Divarci	0:4a2754e462db	128	#define SET_BIT_FIELD(address, reg_name, bit_field_name, value) \
Sinan Divarci	0:4a2754e462db	129	{ int ret; \
Sinan Divarci	0:4a2754e462db	130	ret = read_register(address, (uint8_t *)&(reg_name), 1); \
Sinan Divarci	0:4a2754e462db	131	if (ret != MAX3133X_NO_ERR) { \
Sinan Divarci	0:4a2754e462db	132	return ret; \
Sinan Divarci	0:4a2754e462db	133	} \
Sinan Divarci	0:4a2754e462db	134	if (bit_field_name != value) { \
Sinan Divarci	0:4a2754e462db	135	bit_field_name = value; \
Sinan Divarci	0:4a2754e462db	136	ret = write_register(address, (uint8_t *)&(reg_name), 1); \
Sinan Divarci	0:4a2754e462db	137	if (ret != MAX3133X_NO_ERR) { \
Sinan Divarci	0:4a2754e462db	138	return ret; \
Sinan Divarci	0:4a2754e462db	139	} \
Sinan Divarci	0:4a2754e462db	140	} \
Sinan Divarci	0:4a2754e462db	141	}
Sinan Divarci	0:4a2754e462db	142
Sinan Divarci	0:4a2754e462db	143	inline void MAX3133X::rtc_regs_to_time(struct tm time, const max3133x_rtc_time_regs_t regs, uint16_t *sub_sec)
Sinan Divarci	0:4a2754e462db	144	{
Sinan Divarci	0:4a2754e462db	145	if (sub_sec != NULL)
Sinan Divarci	0:4a2754e462db	146	sub_sec = (1000 regs->seconds_1_128_reg.raw) / 128.0;
Sinan Divarci	0:4a2754e462db	147
Sinan Divarci	0:4a2754e462db	148	/* tm_sec seconds [0,61] */
Sinan Divarci	0:4a2754e462db	149	time->tm_sec = BCD2BIN(regs->seconds_reg.bcd.value);
Sinan Divarci	0:4a2754e462db	150
Sinan Divarci	0:4a2754e462db	151	/* tm_min minutes [0,59] */
Sinan Divarci	0:4a2754e462db	152	time->tm_min = BCD2BIN(regs->minutes_reg.bcd.value);
Sinan Divarci	0:4a2754e462db	153
Sinan Divarci	0:4a2754e462db	154	/* tm_hour hour [0,23] */
Sinan Divarci	0:4a2754e462db	155	hour_format_t format = regs->hours_reg.bits_24hr.f_24_12 == 1 ? HOUR12 : HOUR24;
Sinan Divarci	0:4a2754e462db	156	if (format == HOUR24)
Sinan Divarci	0:4a2754e462db	157	time->tm_hour = BCD2BIN(regs->hours_reg.bcd_24hr.value);
Sinan Divarci	0:4a2754e462db	158	else if (format == HOUR12) {
Sinan Divarci	0:4a2754e462db	159	uint8_t hr24 = to_24hr(BCD2BIN(regs->hours_reg.bcd_12hr.value), regs->hours_reg.bits_12hr.am_pm);
Sinan Divarci	0:4a2754e462db	160	time->tm_hour = hr24;
Sinan Divarci	0:4a2754e462db	161	}
Sinan Divarci	0:4a2754e462db	162
Sinan Divarci	0:4a2754e462db	163	/* tm_wday day of week [0,6] (Sunday = 0) */
Sinan Divarci	0:4a2754e462db	164	time->tm_wday = BCD2BIN(regs->day_reg.bcd.value) - 1;
Sinan Divarci	0:4a2754e462db	165
Sinan Divarci	0:4a2754e462db	166	/* tm_mday day of month [1,31] */
Sinan Divarci	0:4a2754e462db	167	time->tm_mday = BCD2BIN(regs->date_reg.bcd.value);
Sinan Divarci	0:4a2754e462db	168
Sinan Divarci	0:4a2754e462db	169	/* tm_mon month of year [0,11] */
Sinan Divarci	0:4a2754e462db	170	time->tm_mon = BCD2BIN(regs->month_reg.bcd.value) - 1;
Sinan Divarci	0:4a2754e462db	171
Sinan Divarci	0:4a2754e462db	172	/* tm_year years since 2000 */
Sinan Divarci	0:4a2754e462db	173	if (regs->month_reg.bits.century)
Sinan Divarci	0:4a2754e462db	174	time->tm_year = BCD2BIN(regs->year_reg.bcd.value) + 200;
Sinan Divarci	0:4a2754e462db	175	else
Sinan Divarci	0:4a2754e462db	176	time->tm_year = BCD2BIN(regs->year_reg.bcd.value) + 100;
Sinan Divarci	0:4a2754e462db	177
Sinan Divarci	0:4a2754e462db	178	/* tm_yday day of year [0,365] */
Sinan Divarci	0:4a2754e462db	179	time->tm_yday = 0;
Sinan Divarci	0:4a2754e462db	180
Sinan Divarci	0:4a2754e462db	181	/* tm_isdst daylight savings flag */
Sinan Divarci	0:4a2754e462db	182	time->tm_isdst = 0;
Sinan Divarci	0:4a2754e462db	183	}
Sinan Divarci	0:4a2754e462db	184
Sinan Divarci	0:4a2754e462db	185	inline int MAX3133X::time_to_rtc_regs(max3133x_rtc_time_regs_t regs, const struct tm time, hour_format_t format)
Sinan Divarci	0:4a2754e462db	186	{
Sinan Divarci	0:4a2754e462db	187	/*********************************************************
Sinan Divarci	0:4a2754e462db	188	* +----------+------+---------------------------+-------+
Sinan Divarci	0:4a2754e462db	189	* \| Member \| Type \| Meaning \| Range \|
Sinan Divarci	0:4a2754e462db	190	* +----------+------+---------------------------+-------+
Sinan Divarci	0:4a2754e462db	191	* \| tm_sec \| int \| seconds after the minute \| 0-61* \|
Sinan Divarci	0:4a2754e462db	192	* \| tm_min \| int \| minutes after the hour \| 0-59 \|
Sinan Divarci	0:4a2754e462db	193	* \| tm_hour \| int \| hours since midnight \| 0-23 \|
Sinan Divarci	0:4a2754e462db	194	* \| tm_mday \| int \| day of the month \| 1-31 \|
Sinan Divarci	0:4a2754e462db	195	* \| tm_mon \| int \| months since January \| 0-11 \|
Sinan Divarci	0:4a2754e462db	196	* \| tm_year \| int \| years since 1900 \| \|
Sinan Divarci	0:4a2754e462db	197	* \| tm_wday \| int \| days since Sunday \| 0-6 \|
Sinan Divarci	0:4a2754e462db	198	* \| tm_yday \| int \| days since January 1 \| 0-365 \|
Sinan Divarci	0:4a2754e462db	199	* \| tm_isdst \| int \| Daylight Saving Time flag \| \|
Sinan Divarci	0:4a2754e462db	200	* +----------+------+---------------------------+-------+
Sinan Divarci	0:4a2754e462db	201	* * tm_sec is generally 0-59. The extra range is to accommodate for leap
Sinan Divarci	0:4a2754e462db	202	* seconds in certain systems.
Sinan Divarci	0:4a2754e462db	203	*********************************************************/
Sinan Divarci	0:4a2754e462db	204	regs->seconds_reg.bcd.value = BIN2BCD(time->tm_sec);
Sinan Divarci	0:4a2754e462db	205
Sinan Divarci	0:4a2754e462db	206	regs->minutes_reg.bcd.value = BIN2BCD(time->tm_min);
Sinan Divarci	0:4a2754e462db	207
Sinan Divarci	0:4a2754e462db	208	if (format == HOUR24) {
Sinan Divarci	0:4a2754e462db	209	regs->hours_reg.bcd_24hr.value = BIN2BCD(time->tm_hour);
Sinan Divarci	0:4a2754e462db	210	regs->hours_reg.bits_24hr.f_24_12 = HOUR24;
Sinan Divarci	0:4a2754e462db	211	} else if (format == HOUR12) {
Sinan Divarci	0:4a2754e462db	212	uint8_t hr_12, pm;
Sinan Divarci	0:4a2754e462db	213	to_12hr(time->tm_hour, &hr_12, &pm);
Sinan Divarci	0:4a2754e462db	214	regs->hours_reg.bcd_12hr.value = BIN2BCD(hr_12);
Sinan Divarci	0:4a2754e462db	215	regs->hours_reg.bits_12hr.f_24_12 = HOUR12;
Sinan Divarci	0:4a2754e462db	216	regs->hours_reg.bits_12hr.am_pm = pm;
Sinan Divarci	0:4a2754e462db	217	} else {
Sinan Divarci	0:4a2754e462db	218	pr_err("Invalid Hour Format!");
Sinan Divarci	0:4a2754e462db	219	return MAX3133X_INVALID_TIME_ERR;
Sinan Divarci	0:4a2754e462db	220	}
Sinan Divarci	0:4a2754e462db	221
Sinan Divarci	0:4a2754e462db	222	regs->day_reg.bcd.value = BIN2BCD(time->tm_wday + 1);
Sinan Divarci	0:4a2754e462db	223	regs->date_reg.bcd.value = BIN2BCD(time->tm_mday);
Sinan Divarci	0:4a2754e462db	224	regs->month_reg.bcd.value = BIN2BCD(time->tm_mon + 1);
Sinan Divarci	0:4a2754e462db	225
Sinan Divarci	0:4a2754e462db	226	if (time->tm_year >= 200) {
Sinan Divarci	0:4a2754e462db	227	regs->month_reg.bits.century = 1;
Sinan Divarci	0:4a2754e462db	228	regs->year_reg.bcd.value = BIN2BCD(time->tm_year - 200);
Sinan Divarci	0:4a2754e462db	229	} else if (time->tm_year >= 100) {
Sinan Divarci	0:4a2754e462db	230	regs->month_reg.bits.century = 0;
Sinan Divarci	0:4a2754e462db	231	regs->year_reg.bcd.value = BIN2BCD(time->tm_year - 100);
Sinan Divarci	0:4a2754e462db	232	} else {
Sinan Divarci	0:4a2754e462db	233	pr_err("Invalid set date!");
Sinan Divarci	0:4a2754e462db	234	return MAX3133X_INVALID_DATE_ERR;
Sinan Divarci	0:4a2754e462db	235	}
Sinan Divarci	0:4a2754e462db	236
Sinan Divarci	0:4a2754e462db	237	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	238	}
Sinan Divarci	0:4a2754e462db	239
Sinan Divarci	0:4a2754e462db	240	int MAX3133X::get_time(struct tm time, uint16_t sub_sec)
Sinan Divarci	0:4a2754e462db	241	{
Sinan Divarci	0:4a2754e462db	242	int ret;
Sinan Divarci	0:4a2754e462db	243	max3133x_rtc_time_regs_t max3133x_rtc_time_regs = {};
Sinan Divarci	0:4a2754e462db	244	if (time == NULL) {
Sinan Divarci	0:4a2754e462db	245	pr_err("rtc_ctime is invalid!");
Sinan Divarci	0:4a2754e462db	246	return MAX3133X_NULL_VALUE_ERR;
Sinan Divarci	0:4a2754e462db	247	}
Sinan Divarci	0:4a2754e462db	248
Sinan Divarci	0:4a2754e462db	249	ret = read_register(reg_addr->seconds_1_128_reg_addr, (uint8_t *) &max3133x_rtc_time_regs.seconds_1_128_reg, sizeof(max3133x_rtc_time_regs));
Sinan Divarci	0:4a2754e462db	250	if (ret != MAX3133X_NO_ERR) {
Sinan Divarci	0:4a2754e462db	251	pr_err("read time registers failed!");
Sinan Divarci	0:4a2754e462db	252	return ret;
Sinan Divarci	0:4a2754e462db	253	}
Sinan Divarci	0:4a2754e462db	254
Sinan Divarci	0:4a2754e462db	255	rtc_regs_to_time(time, &max3133x_rtc_time_regs, sub_sec);
Sinan Divarci	0:4a2754e462db	256	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	257	}
Sinan Divarci	0:4a2754e462db	258
Sinan Divarci	0:4a2754e462db	259	int MAX3133X::set_time(const struct tm *time, hour_format_t format)
Sinan Divarci	0:4a2754e462db	260	{
Sinan Divarci	0:4a2754e462db	261	int ret;
Sinan Divarci	0:4a2754e462db	262	max3133x_rtc_time_regs_t max3133x_rtc_time_regs = {};
Sinan Divarci	0:4a2754e462db	263
Sinan Divarci	0:4a2754e462db	264	if (time == NULL) {
Sinan Divarci	0:4a2754e462db	265	pr_err("rtc_ctime is invalid!");
Sinan Divarci	0:4a2754e462db	266	return MAX3133X_NULL_VALUE_ERR;
Sinan Divarci	0:4a2754e462db	267	}
Sinan Divarci	0:4a2754e462db	268
Sinan Divarci	0:4a2754e462db	269	ret = time_to_rtc_regs(&max3133x_rtc_time_regs, time, format);
Sinan Divarci	0:4a2754e462db	270	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	271	return ret;
Sinan Divarci	0:4a2754e462db	272
Sinan Divarci	0:4a2754e462db	273	ret = write_register(reg_addr->seconds_reg_addr, (uint8_t *)&max3133x_rtc_time_regs.seconds_reg.raw, sizeof(max3133x_rtc_time_regs)-1);
Sinan Divarci	0:4a2754e462db	274	if (ret != MAX3133X_NO_ERR) {
Sinan Divarci	0:4a2754e462db	275	pr_err("write time registers failed!");
Sinan Divarci	0:4a2754e462db	276	return ret;
Sinan Divarci	0:4a2754e462db	277	}
Sinan Divarci	0:4a2754e462db	278
Sinan Divarci	0:4a2754e462db	279	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	280	}
Sinan Divarci	0:4a2754e462db	281
Sinan Divarci	0:4a2754e462db	282	inline void MAX3133X::timestamp_regs_to_time(timestamp_t timestamp, const max3133x_ts_regs_t timestamp_reg)
Sinan Divarci	0:4a2754e462db	283	{
Sinan Divarci	0:4a2754e462db	284	/* tm_sec seconds [0,61] */
Sinan Divarci	0:4a2754e462db	285	timestamp->ctime.tm_sec = BCD2BIN(timestamp_reg->ts_sec_reg.bcd.value);
Sinan Divarci	0:4a2754e462db	286
Sinan Divarci	0:4a2754e462db	287	/* tm_min minutes [0,59] */
Sinan Divarci	0:4a2754e462db	288	timestamp->ctime.tm_min = BCD2BIN(timestamp_reg->ts_min_reg.bcd.value);
Sinan Divarci	0:4a2754e462db	289
Sinan Divarci	0:4a2754e462db	290	/* tm_hour hour [0,23] */
Sinan Divarci	0:4a2754e462db	291	hour_format_t format = timestamp_reg->ts_hour_reg.bits_24hr.f_24_12 ? HOUR12 : HOUR24;
Sinan Divarci	0:4a2754e462db	292	if (format == HOUR24)
Sinan Divarci	0:4a2754e462db	293	timestamp->ctime.tm_hour = BCD2BIN(timestamp_reg->ts_hour_reg.bcd_24hr.value);
Sinan Divarci	0:4a2754e462db	294	else if (format == HOUR12) {
Sinan Divarci	0:4a2754e462db	295	uint8_t hr24 = to_24hr(BCD2BIN(timestamp_reg->ts_hour_reg.bcd_12hr.value), timestamp_reg->ts_hour_reg.bits_12hr.am_pm);
Sinan Divarci	0:4a2754e462db	296	timestamp->ctime.tm_hour = hr24;
Sinan Divarci	0:4a2754e462db	297	}
Sinan Divarci	0:4a2754e462db	298
Sinan Divarci	0:4a2754e462db	299	/* tm_mday day of month [1,31] */
Sinan Divarci	0:4a2754e462db	300	timestamp->ctime.tm_mday = BCD2BIN(timestamp_reg->ts_date_reg.bcd.value);
Sinan Divarci	0:4a2754e462db	301
Sinan Divarci	0:4a2754e462db	302	/* tm_mon month of year [0,11] */
Sinan Divarci	0:4a2754e462db	303	timestamp->ctime.tm_mon = BCD2BIN(timestamp_reg->ts_month_reg.bcd.value) - 1;
Sinan Divarci	0:4a2754e462db	304
Sinan Divarci	0:4a2754e462db	305	/* tm_year years since 2000 */
Sinan Divarci	0:4a2754e462db	306	if (timestamp_reg->ts_month_reg.bits.century)
Sinan Divarci	0:4a2754e462db	307	timestamp->ctime.tm_year = BCD2BIN(timestamp_reg->ts_year_reg.bcd.value) + 200;
Sinan Divarci	0:4a2754e462db	308	else
Sinan Divarci	0:4a2754e462db	309	timestamp->ctime.tm_year = BCD2BIN(timestamp_reg->ts_year_reg.bcd.value) + 100;
Sinan Divarci	0:4a2754e462db	310
Sinan Divarci	0:4a2754e462db	311	/* tm_yday day of year [0,365] */
Sinan Divarci	0:4a2754e462db	312	timestamp->ctime.tm_yday = 0; /* TODO */
Sinan Divarci	0:4a2754e462db	313
Sinan Divarci	0:4a2754e462db	314	/* tm_isdst daylight savings flag */
Sinan Divarci	0:4a2754e462db	315	timestamp->ctime.tm_isdst = 0; /* TODO */
Sinan Divarci	0:4a2754e462db	316
Sinan Divarci	0:4a2754e462db	317	timestamp->sub_sec = (1000 * timestamp_reg->ts_sec_1_128_reg.raw) / 128.0;
Sinan Divarci	0:4a2754e462db	318	}
Sinan Divarci	0:4a2754e462db	319
Sinan Divarci	0:4a2754e462db	320	int MAX3133X::get_status_reg(max3133x_status_reg_t * status_reg)
Sinan Divarci	0:4a2754e462db	321	{
Sinan Divarci	0:4a2754e462db	322	return read_register(reg_addr->status_reg_addr, &status_reg->raw, 1);
Sinan Divarci	0:4a2754e462db	323	}
Sinan Divarci	0:4a2754e462db	324
Sinan Divarci	0:4a2754e462db	325	int MAX3133X::get_interrupt_reg(max3133x_int_en_reg_t * int_en_reg)
Sinan Divarci	0:4a2754e462db	326	{
Sinan Divarci	0:4a2754e462db	327	return read_register(reg_addr->int_en_reg_addr, &int_en_reg->raw, 1);
Sinan Divarci	0:4a2754e462db	328	}
Sinan Divarci	0:4a2754e462db	329
Sinan Divarci	0:4a2754e462db	330	int MAX3133X::interrupt_enable(uint8_t mask)
Sinan Divarci	0:4a2754e462db	331	{
Sinan Divarci	0:4a2754e462db	332	int ret;
Sinan Divarci	0:4a2754e462db	333	max3133x_int_en_reg_t int_en_reg = {};
Sinan Divarci	0:4a2754e462db	334
Sinan Divarci	0:4a2754e462db	335	ret = read_register(reg_addr->int_en_reg_addr, &int_en_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	336	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	337	return ret;
Sinan Divarci	0:4a2754e462db	338
Sinan Divarci	0:4a2754e462db	339	int_en_reg.raw \|= mask;
Sinan Divarci	0:4a2754e462db	340	return write_register(reg_addr->int_en_reg_addr, &int_en_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	341	}
Sinan Divarci	0:4a2754e462db	342
Sinan Divarci	0:4a2754e462db	343	int MAX3133X::interrupt_disable(uint8_t mask)
Sinan Divarci	0:4a2754e462db	344	{
Sinan Divarci	0:4a2754e462db	345	int ret;
Sinan Divarci	0:4a2754e462db	346	max3133x_int_en_reg_t int_en_reg = {};
Sinan Divarci	0:4a2754e462db	347
Sinan Divarci	0:4a2754e462db	348	ret = read_register(reg_addr->int_en_reg_addr, &int_en_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	349	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	350	return ret;
Sinan Divarci	0:4a2754e462db	351
Sinan Divarci	0:4a2754e462db	352	int_en_reg.raw &= ~mask;
Sinan Divarci	0:4a2754e462db	353	return write_register(reg_addr->int_en_reg_addr, &int_en_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	354	}
Sinan Divarci	0:4a2754e462db	355
Sinan Divarci	0:4a2754e462db	356	int MAX3133X::sw_reset_assert()
Sinan Divarci	0:4a2754e462db	357	{
Sinan Divarci	0:4a2754e462db	358	max3133x_rtc_reset_reg_t rtc_reset_reg = {};
Sinan Divarci	0:4a2754e462db	359	SET_BIT_FIELD(reg_addr->rtc_reset_reg_addr, rtc_reset_reg, rtc_reset_reg.bits.swrst, 1);
Sinan Divarci	0:4a2754e462db	360	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	361	}
Sinan Divarci	0:4a2754e462db	362
Sinan Divarci	0:4a2754e462db	363	int MAX3133X::sw_reset_release()
Sinan Divarci	0:4a2754e462db	364	{
Sinan Divarci	0:4a2754e462db	365	max3133x_rtc_reset_reg_t rtc_reset_reg = {};
Sinan Divarci	0:4a2754e462db	366	SET_BIT_FIELD(reg_addr->rtc_reset_reg_addr, rtc_reset_reg, rtc_reset_reg.bits.swrst, 0);
Sinan Divarci	0:4a2754e462db	367	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	368	}
Sinan Divarci	0:4a2754e462db	369
Sinan Divarci	0:4a2754e462db	370	int MAX3133X::sw_reset()
Sinan Divarci	0:4a2754e462db	371	{
Sinan Divarci	0:4a2754e462db	372	int ret;
Sinan Divarci	0:4a2754e462db	373	ret = sw_reset_assert();
Sinan Divarci	0:4a2754e462db	374	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	375	return ret;
Sinan Divarci	0:4a2754e462db	376
Sinan Divarci	0:4a2754e462db	377	ThisThread::sleep_for(5);
Sinan Divarci	0:4a2754e462db	378	return sw_reset_release();
Sinan Divarci	0:4a2754e462db	379	}
Sinan Divarci	0:4a2754e462db	380
Sinan Divarci	0:4a2754e462db	381	int MAX31331::rtc_config(rtc_config_t *max31331_config)
Sinan Divarci	0:4a2754e462db	382	{
Sinan Divarci	0:4a2754e462db	383	int ret;
Sinan Divarci	0:4a2754e462db	384	max3133x_rtc_config1_reg_t rtc_config1_reg = {};
Sinan Divarci	0:4a2754e462db	385	max31331_rtc_config2_reg_t rtc_config2_reg = {};
Sinan Divarci	0:4a2754e462db	386
Sinan Divarci	0:4a2754e462db	387	rtc_config1_reg.bits.a1ac = max31331_config->a1ac;
Sinan Divarci	0:4a2754e462db	388	rtc_config1_reg.bits.dip = max31331_config->dip;
Sinan Divarci	0:4a2754e462db	389	rtc_config1_reg.bits.data_ret = max31331_config->data_ret;
Sinan Divarci	0:4a2754e462db	390	rtc_config1_reg.bits.i2c_timeout = max31331_config->i2c_timeout;
Sinan Divarci	0:4a2754e462db	391	rtc_config1_reg.bits.en_osc = max31331_config->en_osc;
Sinan Divarci	0:4a2754e462db	392
Sinan Divarci	0:4a2754e462db	393	ret = write_register(reg_addr.rtc_config1_reg_addr, &rtc_config1_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	394	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	395	return ret;
Sinan Divarci	0:4a2754e462db	396
Sinan Divarci	0:4a2754e462db	397	rtc_config2_reg.bits.clko_hz = max31331_config->clko_hz;
Sinan Divarci	0:4a2754e462db	398	rtc_config2_reg.bits.enclko = max31331_config->enclko;
Sinan Divarci	0:4a2754e462db	399
Sinan Divarci	0:4a2754e462db	400	return write_register(reg_addr.rtc_config2_reg_addr, &rtc_config2_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	401	}
Sinan Divarci	0:4a2754e462db	402
Sinan Divarci	0:4a2754e462db	403	int MAX31334::rtc_config(rtc_config_t *max31334_config)
Sinan Divarci	0:4a2754e462db	404	{
Sinan Divarci	0:4a2754e462db	405	int ret;
Sinan Divarci	0:4a2754e462db	406	max3133x_rtc_config1_reg_t rtc_config1_reg = {};
Sinan Divarci	0:4a2754e462db	407	max31334_rtc_config2_reg_t rtc_config2_reg = {};
Sinan Divarci	0:4a2754e462db	408
Sinan Divarci	0:4a2754e462db	409	rtc_config1_reg.bits.a1ac = max31334_config->a1ac;
Sinan Divarci	0:4a2754e462db	410	rtc_config1_reg.bits.dip = max31334_config->dip;
Sinan Divarci	0:4a2754e462db	411	rtc_config1_reg.bits.data_ret = max31334_config->data_ret;
Sinan Divarci	0:4a2754e462db	412	rtc_config1_reg.bits.i2c_timeout = max31334_config->i2c_timeout;
Sinan Divarci	0:4a2754e462db	413	rtc_config1_reg.bits.en_osc = max31334_config->en_osc;
Sinan Divarci	0:4a2754e462db	414
Sinan Divarci	0:4a2754e462db	415	ret = write_register(reg_addr.rtc_config1_reg_addr, &rtc_config1_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	416	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	417	return ret;
Sinan Divarci	0:4a2754e462db	418
Sinan Divarci	0:4a2754e462db	419	rtc_config2_reg.bits.clko_hz = max31334_config->clko_hz;
Sinan Divarci	0:4a2754e462db	420	rtc_config2_reg.bits.enclko = max31334_config->enclko;
Sinan Divarci	0:4a2754e462db	421	rtc_config2_reg.bits.ddb = max31334_config->ddb;
Sinan Divarci	0:4a2754e462db	422	rtc_config2_reg.bits.dse = max31334_config->dse;
Sinan Divarci	0:4a2754e462db	423
Sinan Divarci	0:4a2754e462db	424	return write_register(reg_addr.rtc_config2_reg_addr, &rtc_config2_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	425	}
Sinan Divarci	0:4a2754e462db	426
Sinan Divarci	0:4a2754e462db	427	int MAX31331::get_rtc_config(rtc_config_t *max31331_config)
Sinan Divarci	0:4a2754e462db	428	{
Sinan Divarci	0:4a2754e462db	429	int ret;
Sinan Divarci	0:4a2754e462db	430	max3133x_rtc_config1_reg_t rtc_config1_reg = {};
Sinan Divarci	0:4a2754e462db	431	max31331_rtc_config2_reg_t rtc_config2_reg = {};
Sinan Divarci	0:4a2754e462db	432
Sinan Divarci	0:4a2754e462db	433	ret = read_register(reg_addr.rtc_config1_reg_addr, &rtc_config1_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	434	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	435	return ret;
Sinan Divarci	0:4a2754e462db	436
Sinan Divarci	0:4a2754e462db	437	max31331_config->a1ac = (a1ac_t)rtc_config1_reg.bits.a1ac;
Sinan Divarci	0:4a2754e462db	438	max31331_config->dip = (dip_t)rtc_config1_reg.bits.dip;
Sinan Divarci	0:4a2754e462db	439	max31331_config->data_ret = (data_ret_t)rtc_config1_reg.bits.data_ret;
Sinan Divarci	0:4a2754e462db	440	max31331_config->i2c_timeout = (i2c_timeout_t)rtc_config1_reg.bits.i2c_timeout;
Sinan Divarci	0:4a2754e462db	441	max31331_config->en_osc = (en_osc_t)rtc_config1_reg.bits.en_osc;
Sinan Divarci	0:4a2754e462db	442
Sinan Divarci	0:4a2754e462db	443	ret = read_register(reg_addr.rtc_config2_reg_addr, &rtc_config2_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	444	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	445	return ret;
Sinan Divarci	0:4a2754e462db	446
Sinan Divarci	0:4a2754e462db	447	max31331_config->clko_hz = (clko_hz_t)rtc_config2_reg.bits.clko_hz;
Sinan Divarci	0:4a2754e462db	448	max31331_config->enclko = (enclko_t)rtc_config2_reg.bits.enclko;
Sinan Divarci	0:4a2754e462db	449	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	450	}
Sinan Divarci	0:4a2754e462db	451
Sinan Divarci	0:4a2754e462db	452	int MAX31334::get_rtc_config(rtc_config_t *max31334_config)
Sinan Divarci	0:4a2754e462db	453	{
Sinan Divarci	0:4a2754e462db	454	int ret;
Sinan Divarci	0:4a2754e462db	455	max3133x_rtc_config1_reg_t rtc_config1_reg = {};
Sinan Divarci	0:4a2754e462db	456	max31334_rtc_config2_reg_t rtc_config2_reg = {};
Sinan Divarci	0:4a2754e462db	457
Sinan Divarci	0:4a2754e462db	458	ret = read_register(reg_addr.rtc_config1_reg_addr, &rtc_config1_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	459	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	460	return ret;
Sinan Divarci	0:4a2754e462db	461
Sinan Divarci	0:4a2754e462db	462	max31334_config->a1ac = (a1ac_t)rtc_config1_reg.bits.a1ac;
Sinan Divarci	0:4a2754e462db	463	max31334_config->dip = (dip_t)rtc_config1_reg.bits.dip;
Sinan Divarci	0:4a2754e462db	464	max31334_config->data_ret = (data_ret_t)rtc_config1_reg.bits.data_ret;
Sinan Divarci	0:4a2754e462db	465	max31334_config->i2c_timeout = (i2c_timeout_t)rtc_config1_reg.bits.i2c_timeout;
Sinan Divarci	0:4a2754e462db	466	max31334_config->en_osc = (en_osc_t)rtc_config1_reg.bits.en_osc;
Sinan Divarci	0:4a2754e462db	467
Sinan Divarci	0:4a2754e462db	468	ret = read_register(reg_addr.rtc_config2_reg_addr, &rtc_config2_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	469	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	470	return ret;
Sinan Divarci	0:4a2754e462db	471
Sinan Divarci	0:4a2754e462db	472	max31334_config->clko_hz = (clko_hz_t)rtc_config2_reg.bits.clko_hz;
Sinan Divarci	0:4a2754e462db	473	max31334_config->ddb = (ddb_t)rtc_config2_reg.bits.ddb;
Sinan Divarci	0:4a2754e462db	474	max31334_config->dse = (dse_t)rtc_config2_reg.bits.dse;
Sinan Divarci	0:4a2754e462db	475	max31334_config->enclko = (enclko_t)rtc_config2_reg.bits.enclko;
Sinan Divarci	0:4a2754e462db	476
Sinan Divarci	0:4a2754e462db	477	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	478	}
Sinan Divarci	0:4a2754e462db	479
Sinan Divarci	0:4a2754e462db	480	int MAX3133X::set_alarm1_auto_clear(a1ac_t a1ac)
Sinan Divarci	0:4a2754e462db	481	{
Sinan Divarci	0:4a2754e462db	482	max3133x_rtc_config1_reg_t rtc_config1_reg = {};
Sinan Divarci	0:4a2754e462db	483	SET_BIT_FIELD(reg_addr->rtc_config1_reg_addr, rtc_config1_reg, rtc_config1_reg.bits.a1ac, a1ac);
Sinan Divarci	0:4a2754e462db	484	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	485	}
Sinan Divarci	0:4a2754e462db	486
Sinan Divarci	0:4a2754e462db	487	int MAX3133X::set_din_polarity(dip_t dip)
Sinan Divarci	0:4a2754e462db	488	{
Sinan Divarci	0:4a2754e462db	489	max3133x_rtc_config1_reg_t rtc_config1_reg = {};
Sinan Divarci	0:4a2754e462db	490	SET_BIT_FIELD(reg_addr->rtc_config1_reg_addr, rtc_config1_reg, rtc_config1_reg.bits.dip, dip);
Sinan Divarci	0:4a2754e462db	491	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	492	}
Sinan Divarci	0:4a2754e462db	493
Sinan Divarci	0:4a2754e462db	494	int MAX3133X::data_retention_mode_config(bool enable)
Sinan Divarci	0:4a2754e462db	495	{
Sinan Divarci	0:4a2754e462db	496	max3133x_rtc_config1_reg_t rtc_config1_reg = {};
Sinan Divarci	0:4a2754e462db	497	SET_BIT_FIELD(reg_addr->rtc_config1_reg_addr, rtc_config1_reg, rtc_config1_reg.bits.data_ret, enable);
Sinan Divarci	0:4a2754e462db	498	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	499	}
Sinan Divarci	0:4a2754e462db	500
Sinan Divarci	0:4a2754e462db	501	int MAX3133X::data_retention_mode_enter()
Sinan Divarci	0:4a2754e462db	502	{
Sinan Divarci	0:4a2754e462db	503	return data_retention_mode_config(1);
Sinan Divarci	0:4a2754e462db	504	}
Sinan Divarci	0:4a2754e462db	505
Sinan Divarci	0:4a2754e462db	506	int MAX3133X::data_retention_mode_exit()
Sinan Divarci	0:4a2754e462db	507	{
Sinan Divarci	0:4a2754e462db	508	return data_retention_mode_config(0);
Sinan Divarci	0:4a2754e462db	509	}
Sinan Divarci	0:4a2754e462db	510
Sinan Divarci	0:4a2754e462db	511	int MAX3133X::i2c_timeout_config(bool enable)
Sinan Divarci	0:4a2754e462db	512	{
Sinan Divarci	0:4a2754e462db	513	max3133x_rtc_config1_reg_t rtc_config1_reg = {};
Sinan Divarci	0:4a2754e462db	514	SET_BIT_FIELD(reg_addr->rtc_config1_reg_addr, rtc_config1_reg, rtc_config1_reg.bits.i2c_timeout, enable);
Sinan Divarci	0:4a2754e462db	515	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	516	}
Sinan Divarci	0:4a2754e462db	517
Sinan Divarci	0:4a2754e462db	518	int MAX3133X::i2c_timeout_enable()
Sinan Divarci	0:4a2754e462db	519	{
Sinan Divarci	0:4a2754e462db	520	return i2c_timeout_config(1);
Sinan Divarci	0:4a2754e462db	521	}
Sinan Divarci	0:4a2754e462db	522
Sinan Divarci	0:4a2754e462db	523	int MAX3133X::i2c_timeout_disable()
Sinan Divarci	0:4a2754e462db	524	{
Sinan Divarci	0:4a2754e462db	525	return i2c_timeout_config(0);
Sinan Divarci	0:4a2754e462db	526	}
Sinan Divarci	0:4a2754e462db	527
Sinan Divarci	0:4a2754e462db	528	int MAX3133X::oscillator_config(bool enable)
Sinan Divarci	0:4a2754e462db	529	{
Sinan Divarci	0:4a2754e462db	530	max3133x_rtc_config1_reg_t rtc_config1_reg = {};
Sinan Divarci	0:4a2754e462db	531	SET_BIT_FIELD(reg_addr->rtc_config1_reg_addr, rtc_config1_reg, rtc_config1_reg.bits.en_osc, enable);
Sinan Divarci	0:4a2754e462db	532	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	533	}
Sinan Divarci	0:4a2754e462db	534
Sinan Divarci	0:4a2754e462db	535	int MAX3133X::oscillator_enable()
Sinan Divarci	0:4a2754e462db	536	{
Sinan Divarci	0:4a2754e462db	537	return oscillator_config(1);
Sinan Divarci	0:4a2754e462db	538	}
Sinan Divarci	0:4a2754e462db	539
Sinan Divarci	0:4a2754e462db	540	int MAX3133X::oscillator_disable()
Sinan Divarci	0:4a2754e462db	541	{
Sinan Divarci	0:4a2754e462db	542	return oscillator_config(0);
Sinan Divarci	0:4a2754e462db	543	}
Sinan Divarci	0:4a2754e462db	544
Sinan Divarci	0:4a2754e462db	545	int MAX31334::get_sleep_state()
Sinan Divarci	0:4a2754e462db	546	{
Sinan Divarci	0:4a2754e462db	547	int ret;
Sinan Divarci	0:4a2754e462db	548	max31334_rtc_config2_reg_t rtc_config2_reg = {};
Sinan Divarci	0:4a2754e462db	549
Sinan Divarci	0:4a2754e462db	550	ret = read_register(reg_addr.rtc_config2_reg_addr, &rtc_config2_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	551	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	552	return ret;
Sinan Divarci	0:4a2754e462db	553
Sinan Divarci	0:4a2754e462db	554	return rtc_config2_reg.bits.slst;
Sinan Divarci	0:4a2754e462db	555	}
Sinan Divarci	0:4a2754e462db	556
Sinan Divarci	0:4a2754e462db	557	int MAX31334::din_sleep_entry_config(bool enable)
Sinan Divarci	0:4a2754e462db	558	{
Sinan Divarci	0:4a2754e462db	559	max31334_rtc_config2_reg_t rtc_config2_reg = {};
Sinan Divarci	0:4a2754e462db	560	SET_BIT_FIELD(reg_addr.rtc_config2_reg_addr, rtc_config2_reg, rtc_config2_reg.bits.dse, enable);
Sinan Divarci	0:4a2754e462db	561	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	562	}
Sinan Divarci	0:4a2754e462db	563
Sinan Divarci	0:4a2754e462db	564	int MAX31334::din_sleep_entry_enable()
Sinan Divarci	0:4a2754e462db	565	{
Sinan Divarci	0:4a2754e462db	566	return din_sleep_entry_config(1);
Sinan Divarci	0:4a2754e462db	567	}
Sinan Divarci	0:4a2754e462db	568
Sinan Divarci	0:4a2754e462db	569	int MAX31334::din_sleep_entry_disable()
Sinan Divarci	0:4a2754e462db	570	{
Sinan Divarci	0:4a2754e462db	571	return din_sleep_entry_config(0);
Sinan Divarci	0:4a2754e462db	572	}
Sinan Divarci	0:4a2754e462db	573
Sinan Divarci	0:4a2754e462db	574	int MAX31334::din_pin_debounce_config(bool enable)
Sinan Divarci	0:4a2754e462db	575	{
Sinan Divarci	0:4a2754e462db	576	max31334_rtc_config2_reg_t rtc_config2_reg = {};
Sinan Divarci	0:4a2754e462db	577	SET_BIT_FIELD(reg_addr.rtc_config2_reg_addr, rtc_config2_reg, rtc_config2_reg.bits.ddb, enable);
Sinan Divarci	0:4a2754e462db	578	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	579	}
Sinan Divarci	0:4a2754e462db	580
Sinan Divarci	0:4a2754e462db	581	int MAX31334::din_pin_debounce_enable()
Sinan Divarci	0:4a2754e462db	582	{
Sinan Divarci	0:4a2754e462db	583	return din_pin_debounce_config(1);
Sinan Divarci	0:4a2754e462db	584	}
Sinan Divarci	0:4a2754e462db	585
Sinan Divarci	0:4a2754e462db	586	int MAX31334::din_pin_debounce_disable()
Sinan Divarci	0:4a2754e462db	587	{
Sinan Divarci	0:4a2754e462db	588	return din_pin_debounce_config(0);
Sinan Divarci	0:4a2754e462db	589	}
Sinan Divarci	0:4a2754e462db	590
Sinan Divarci	0:4a2754e462db	591	int MAX3133X::clkout_config(bool enable)
Sinan Divarci	0:4a2754e462db	592	{
Sinan Divarci	0:4a2754e462db	593	max31334_rtc_config2_reg_t rtc_config2_reg = {};
Sinan Divarci	0:4a2754e462db	594	SET_BIT_FIELD(reg_addr->rtc_config2_reg_addr, rtc_config2_reg, rtc_config2_reg.bits.enclko, enable);
Sinan Divarci	0:4a2754e462db	595	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	596	}
Sinan Divarci	0:4a2754e462db	597
Sinan Divarci	0:4a2754e462db	598	int MAX3133X::clkout_enable()
Sinan Divarci	0:4a2754e462db	599	{
Sinan Divarci	0:4a2754e462db	600	return clkout_config(1);
Sinan Divarci	0:4a2754e462db	601	}
Sinan Divarci	0:4a2754e462db	602
Sinan Divarci	0:4a2754e462db	603	int MAX3133X::clkout_disable()
Sinan Divarci	0:4a2754e462db	604	{
Sinan Divarci	0:4a2754e462db	605	return clkout_config(0);
Sinan Divarci	0:4a2754e462db	606	}
Sinan Divarci	0:4a2754e462db	607
Sinan Divarci	0:4a2754e462db	608	int MAX3133X::set_clko_freq(clko_hz_t clko_hz)
Sinan Divarci	0:4a2754e462db	609	{
Sinan Divarci	0:4a2754e462db	610	max31334_rtc_config2_reg_t rtc_config2_reg = {};
Sinan Divarci	0:4a2754e462db	611	SET_BIT_FIELD(reg_addr->rtc_config2_reg_addr, rtc_config2_reg, rtc_config2_reg.bits.clko_hz, clko_hz);
Sinan Divarci	0:4a2754e462db	612	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	613	}
Sinan Divarci	0:4a2754e462db	614
Sinan Divarci	0:4a2754e462db	615	int MAX3133X::get_clko_freq(clko_hz_t *clko_hz)
Sinan Divarci	0:4a2754e462db	616	{
Sinan Divarci	0:4a2754e462db	617	int ret;
Sinan Divarci	0:4a2754e462db	618	max31334_rtc_config2_reg_t rtc_config2_reg = {};
Sinan Divarci	0:4a2754e462db	619
Sinan Divarci	0:4a2754e462db	620	ret = read_register(reg_addr->rtc_config2_reg_addr, &rtc_config2_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	621	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	622	return ret;
Sinan Divarci	0:4a2754e462db	623
Sinan Divarci	0:4a2754e462db	624	*clko_hz = (clko_hz_t)rtc_config2_reg.bits.clko_hz;
Sinan Divarci	0:4a2754e462db	625	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	626	}
Sinan Divarci	0:4a2754e462db	627
Sinan Divarci	0:4a2754e462db	628	int MAX3133X::timestamp_function_enable()
Sinan Divarci	0:4a2754e462db	629	{
Sinan Divarci	0:4a2754e462db	630	max3133x_timestamp_config_reg_t timestamp_config_reg = {};
Sinan Divarci	0:4a2754e462db	631	SET_BIT_FIELD(reg_addr->timestamp_config_reg_addr, timestamp_config_reg, timestamp_config_reg.bits.tse, 1);
Sinan Divarci	0:4a2754e462db	632	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	633	}
Sinan Divarci	0:4a2754e462db	634
Sinan Divarci	0:4a2754e462db	635	int MAX3133X::timestamp_function_disable()
Sinan Divarci	0:4a2754e462db	636	{
Sinan Divarci	0:4a2754e462db	637	max3133x_timestamp_config_reg_t timestamp_config_reg = {};
Sinan Divarci	0:4a2754e462db	638	SET_BIT_FIELD(reg_addr->timestamp_config_reg_addr, timestamp_config_reg, timestamp_config_reg.bits.tse, 0);
Sinan Divarci	0:4a2754e462db	639	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	640	}
Sinan Divarci	0:4a2754e462db	641
Sinan Divarci	0:4a2754e462db	642	int MAX3133X::timestamp_registers_reset()
Sinan Divarci	0:4a2754e462db	643	{
Sinan Divarci	0:4a2754e462db	644	max3133x_timestamp_config_reg_t timestamp_config_reg = {};
Sinan Divarci	0:4a2754e462db	645	SET_BIT_FIELD(reg_addr->timestamp_config_reg_addr, timestamp_config_reg, timestamp_config_reg.bits.tsr, 1);
Sinan Divarci	0:4a2754e462db	646	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	647	}
Sinan Divarci	0:4a2754e462db	648
Sinan Divarci	0:4a2754e462db	649	int MAX3133X::timestamp_overwrite_config(bool enable)
Sinan Divarci	0:4a2754e462db	650	{
Sinan Divarci	0:4a2754e462db	651	max3133x_timestamp_config_reg_t timestamp_config_reg = {};
Sinan Divarci	0:4a2754e462db	652	SET_BIT_FIELD(reg_addr->timestamp_config_reg_addr, timestamp_config_reg, timestamp_config_reg.bits.tsow, enable);
Sinan Divarci	0:4a2754e462db	653	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	654	}
Sinan Divarci	0:4a2754e462db	655
Sinan Divarci	0:4a2754e462db	656	int MAX3133X::timestamp_overwrite_enable()
Sinan Divarci	0:4a2754e462db	657	{
Sinan Divarci	0:4a2754e462db	658	return timestamp_overwrite_config(1);
Sinan Divarci	0:4a2754e462db	659	}
Sinan Divarci	0:4a2754e462db	660
Sinan Divarci	0:4a2754e462db	661	int MAX3133X::timestamp_overwrite_disable()
Sinan Divarci	0:4a2754e462db	662	{
Sinan Divarci	0:4a2754e462db	663	return timestamp_overwrite_config(0);
Sinan Divarci	0:4a2754e462db	664	}
Sinan Divarci	0:4a2754e462db	665
Sinan Divarci	0:4a2754e462db	666	int MAX3133X::timestamp_record_enable(uint8_t record_enable_mask)
Sinan Divarci	0:4a2754e462db	667	{
Sinan Divarci	0:4a2754e462db	668	int ret;
Sinan Divarci	0:4a2754e462db	669	max3133x_timestamp_config_reg_t timestamp_config_reg = {};
Sinan Divarci	0:4a2754e462db	670
Sinan Divarci	0:4a2754e462db	671	if (record_enable_mask > (TSVLOW \| TSPWM \| TSDIN))
Sinan Divarci	0:4a2754e462db	672	return MAX3133X_INVALID_MASK_ERR;
Sinan Divarci	0:4a2754e462db	673
Sinan Divarci	0:4a2754e462db	674	ret = read_register(reg_addr->timestamp_config_reg_addr, &timestamp_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	675	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	676	return ret;
Sinan Divarci	0:4a2754e462db	677
Sinan Divarci	0:4a2754e462db	678	timestamp_config_reg.raw \|= record_enable_mask;
Sinan Divarci	0:4a2754e462db	679	return write_register(reg_addr->timestamp_config_reg_addr, &timestamp_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	680	}
Sinan Divarci	0:4a2754e462db	681
Sinan Divarci	0:4a2754e462db	682	int MAX3133X::timestamp_record_disable(uint8_t record_disable_mask)
Sinan Divarci	0:4a2754e462db	683	{
Sinan Divarci	0:4a2754e462db	684	int ret;
Sinan Divarci	0:4a2754e462db	685	max3133x_timestamp_config_reg_t timestamp_config_reg = {};
Sinan Divarci	0:4a2754e462db	686
Sinan Divarci	0:4a2754e462db	687	if (record_disable_mask > (TSVLOW \| TSPWM \| TSDIN))
Sinan Divarci	0:4a2754e462db	688	return MAX3133X_INVALID_MASK_ERR;
Sinan Divarci	0:4a2754e462db	689
Sinan Divarci	0:4a2754e462db	690	ret = read_register(reg_addr->timestamp_config_reg_addr, &timestamp_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	691	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	692	return ret;
Sinan Divarci	0:4a2754e462db	693
Sinan Divarci	0:4a2754e462db	694	timestamp_config_reg.raw &= ~record_disable_mask;
Sinan Divarci	0:4a2754e462db	695	return write_register(reg_addr->timestamp_config_reg_addr, &timestamp_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	696	}
Sinan Divarci	0:4a2754e462db	697
Sinan Divarci	0:4a2754e462db	698	int MAX31331::timer_init(uint8_t timer_init, bool repeat, timer_freq_t freq)
Sinan Divarci	0:4a2754e462db	699	{
Sinan Divarci	0:4a2754e462db	700	int ret;
Sinan Divarci	0:4a2754e462db	701	max3133x_timer_config_reg_t timer_config_reg = {};
Sinan Divarci	0:4a2754e462db	702
Sinan Divarci	0:4a2754e462db	703	ret = read_register(reg_addr.timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	704	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	705	return ret;
Sinan Divarci	0:4a2754e462db	706
Sinan Divarci	0:4a2754e462db	707	timer_config_reg.bits.te = 0; /* timer is reset */
Sinan Divarci	0:4a2754e462db	708	timer_config_reg.bits.tpause = 1; /* timer is paused */
Sinan Divarci	0:4a2754e462db	709	timer_config_reg.bits.trpt = repeat ? 1 : 0; /* Timer repeat mode */
Sinan Divarci	0:4a2754e462db	710	timer_config_reg.bits.tfs = freq; /* Timer frequency */
Sinan Divarci	0:4a2754e462db	711
Sinan Divarci	0:4a2754e462db	712	ret = write_register(reg_addr.timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	713	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	714	return ret;
Sinan Divarci	0:4a2754e462db	715
Sinan Divarci	0:4a2754e462db	716	return write_register(reg_addr.timer_init_reg_addr, &timer_init, 1);
Sinan Divarci	0:4a2754e462db	717	}
Sinan Divarci	0:4a2754e462db	718
Sinan Divarci	0:4a2754e462db	719	int MAX31334::timer_init(uint16_t timer_init, bool repeat, timer_freq_t freq)
Sinan Divarci	0:4a2754e462db	720	{
Sinan Divarci	0:4a2754e462db	721	int ret;
Sinan Divarci	0:4a2754e462db	722	max3133x_timer_config_reg_t timer_config_reg = {};
Sinan Divarci	0:4a2754e462db	723
Sinan Divarci	0:4a2754e462db	724	ret = read_register(reg_addr.timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	725	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	726	return ret;
Sinan Divarci	0:4a2754e462db	727
Sinan Divarci	0:4a2754e462db	728	timer_config_reg.bits.te = 0; /* timer is reset */
Sinan Divarci	0:4a2754e462db	729	timer_config_reg.bits.tpause = 1; /* timer is paused */
Sinan Divarci	0:4a2754e462db	730	timer_config_reg.bits.trpt = repeat ? 1 : 0; /* Timer repeat mode */
Sinan Divarci	0:4a2754e462db	731	timer_config_reg.bits.tfs = freq; /* Timer frequency */
Sinan Divarci	0:4a2754e462db	732
Sinan Divarci	0:4a2754e462db	733	ret = write_register(reg_addr.timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	734	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	735	return ret;
Sinan Divarci	0:4a2754e462db	736
Sinan Divarci	0:4a2754e462db	737	timer_init = SWAPBYTES(timer_init);
Sinan Divarci	0:4a2754e462db	738
Sinan Divarci	0:4a2754e462db	739	return write_register(reg_addr.timer_init2_reg_addr, (uint8_t *)&timer_init, 2);
Sinan Divarci	0:4a2754e462db	740	}
Sinan Divarci	0:4a2754e462db	741
Sinan Divarci	0:4a2754e462db	742	int MAX31331::timer_get()
Sinan Divarci	0:4a2754e462db	743	{
Sinan Divarci	0:4a2754e462db	744	int ret;
Sinan Divarci	0:4a2754e462db	745	uint8_t timer_count;
Sinan Divarci	0:4a2754e462db	746
Sinan Divarci	0:4a2754e462db	747	ret = read_register(reg_addr.timer_count_reg_addr, &timer_count, 1);
Sinan Divarci	0:4a2754e462db	748	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	749	return ret;
Sinan Divarci	0:4a2754e462db	750
Sinan Divarci	0:4a2754e462db	751	return timer_count;
Sinan Divarci	0:4a2754e462db	752	}
Sinan Divarci	0:4a2754e462db	753
Sinan Divarci	0:4a2754e462db	754	int MAX31334::timer_get()
Sinan Divarci	0:4a2754e462db	755	{
Sinan Divarci	0:4a2754e462db	756	int ret;
Sinan Divarci	0:4a2754e462db	757	uint16_t timer_count;
Sinan Divarci	0:4a2754e462db	758
Sinan Divarci	0:4a2754e462db	759	ret = read_register(reg_addr.timer_count2_reg_addr, (uint8_t *)&timer_count, 2);
Sinan Divarci	0:4a2754e462db	760	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	761	return ret;
Sinan Divarci	0:4a2754e462db	762
Sinan Divarci	0:4a2754e462db	763	return SWAPBYTES(timer_count);
Sinan Divarci	0:4a2754e462db	764	}
Sinan Divarci	0:4a2754e462db	765
Sinan Divarci	0:4a2754e462db	766	int MAX3133X::timer_start()
Sinan Divarci	0:4a2754e462db	767	{
Sinan Divarci	0:4a2754e462db	768	int ret;
Sinan Divarci	0:4a2754e462db	769	max3133x_timer_config_reg_t timer_config_reg = {};
Sinan Divarci	0:4a2754e462db	770
Sinan Divarci	0:4a2754e462db	771	ret = read_register(reg_addr->timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	772	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	773	return ret;
Sinan Divarci	0:4a2754e462db	774
Sinan Divarci	0:4a2754e462db	775	timer_config_reg.bits.te = 1;
Sinan Divarci	0:4a2754e462db	776	timer_config_reg.bits.tpause = 0;
Sinan Divarci	0:4a2754e462db	777
Sinan Divarci	0:4a2754e462db	778	return write_register(reg_addr->timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	779	}
Sinan Divarci	0:4a2754e462db	780
Sinan Divarci	0:4a2754e462db	781	int MAX3133X::timer_pause()
Sinan Divarci	0:4a2754e462db	782	{
Sinan Divarci	0:4a2754e462db	783	int ret;
Sinan Divarci	0:4a2754e462db	784	max3133x_timer_config_reg_t timer_config_reg = {};
Sinan Divarci	0:4a2754e462db	785
Sinan Divarci	0:4a2754e462db	786	ret = read_register(reg_addr->timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	787	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	788	return ret;
Sinan Divarci	0:4a2754e462db	789
Sinan Divarci	0:4a2754e462db	790	timer_config_reg.bits.te = 1;
Sinan Divarci	0:4a2754e462db	791	timer_config_reg.bits.tpause = 1;
Sinan Divarci	0:4a2754e462db	792
Sinan Divarci	0:4a2754e462db	793	return write_register(reg_addr->timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	794	}
Sinan Divarci	0:4a2754e462db	795
Sinan Divarci	0:4a2754e462db	796	int MAX3133X::timer_continue()
Sinan Divarci	0:4a2754e462db	797	{
Sinan Divarci	0:4a2754e462db	798	int ret;
Sinan Divarci	0:4a2754e462db	799	max3133x_timer_config_reg_t timer_config_reg = {};
Sinan Divarci	0:4a2754e462db	800
Sinan Divarci	0:4a2754e462db	801	ret = read_register(reg_addr->timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	802	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	803	return ret;
Sinan Divarci	0:4a2754e462db	804
Sinan Divarci	0:4a2754e462db	805	timer_config_reg.bits.te = 1;
Sinan Divarci	0:4a2754e462db	806	timer_config_reg.bits.tpause = 0;
Sinan Divarci	0:4a2754e462db	807
Sinan Divarci	0:4a2754e462db	808	return write_register(reg_addr->timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	809	}
Sinan Divarci	0:4a2754e462db	810
Sinan Divarci	0:4a2754e462db	811	int MAX3133X::timer_stop()
Sinan Divarci	0:4a2754e462db	812	{
Sinan Divarci	0:4a2754e462db	813	int ret;
Sinan Divarci	0:4a2754e462db	814	max3133x_timer_config_reg_t timer_config_reg = {};
Sinan Divarci	0:4a2754e462db	815
Sinan Divarci	0:4a2754e462db	816	ret = read_register(reg_addr->timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	817	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	818	return ret;
Sinan Divarci	0:4a2754e462db	819
Sinan Divarci	0:4a2754e462db	820	timer_config_reg.bits.te = 0;
Sinan Divarci	0:4a2754e462db	821	timer_config_reg.bits.tpause = 1;
Sinan Divarci	0:4a2754e462db	822
Sinan Divarci	0:4a2754e462db	823	return write_register(reg_addr->timer_config_reg_addr, &timer_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	824	}
Sinan Divarci	0:4a2754e462db	825
Sinan Divarci	0:4a2754e462db	826	int MAX31334::sleep_enter()
Sinan Divarci	0:4a2754e462db	827	{
Sinan Divarci	0:4a2754e462db	828	max31334_sleep_config_reg_t sleep_config_reg = {};
Sinan Divarci	0:4a2754e462db	829	SET_BIT_FIELD(reg_addr.sleep_config_reg_addr, sleep_config_reg, sleep_config_reg.bits.slp, 1);
Sinan Divarci	0:4a2754e462db	830	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	831	}
Sinan Divarci	0:4a2754e462db	832
Sinan Divarci	0:4a2754e462db	833	int MAX31334::sleep_exit()
Sinan Divarci	0:4a2754e462db	834	{
Sinan Divarci	0:4a2754e462db	835	max31334_sleep_config_reg_t sleep_config_reg = {};
Sinan Divarci	0:4a2754e462db	836	SET_BIT_FIELD(reg_addr.sleep_config_reg_addr, sleep_config_reg, sleep_config_reg.bits.slp, 0);
Sinan Divarci	0:4a2754e462db	837	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	838	}
Sinan Divarci	0:4a2754e462db	839
Sinan Divarci	0:4a2754e462db	840	int MAX31334::set_wait_state_timeout(wsto_t wsto)
Sinan Divarci	0:4a2754e462db	841	{
Sinan Divarci	0:4a2754e462db	842	max31334_sleep_config_reg_t sleep_config_reg = {};
Sinan Divarci	0:4a2754e462db	843	SET_BIT_FIELD(reg_addr.sleep_config_reg_addr, sleep_config_reg, sleep_config_reg.bits.wsto, wsto);
Sinan Divarci	0:4a2754e462db	844	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	845	}
Sinan Divarci	0:4a2754e462db	846
Sinan Divarci	0:4a2754e462db	847	int MAX31334::get_wait_state_timeout(wsto_t* wsto)
Sinan Divarci	0:4a2754e462db	848	{
Sinan Divarci	0:4a2754e462db	849	int ret;
Sinan Divarci	0:4a2754e462db	850	max31334_sleep_config_reg_t sleep_config_reg = {};
Sinan Divarci	0:4a2754e462db	851
Sinan Divarci	0:4a2754e462db	852	ret = read_register(reg_addr.sleep_config_reg_addr, &sleep_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	853	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	854	return ret;
Sinan Divarci	0:4a2754e462db	855
Sinan Divarci	0:4a2754e462db	856	*wsto = (wsto_t)sleep_config_reg.bits.wsto;
Sinan Divarci	0:4a2754e462db	857	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	858	}
Sinan Divarci	0:4a2754e462db	859
Sinan Divarci	0:4a2754e462db	860	int MAX31334::wakeup_enable(uint8_t wakeup_enable_mask)
Sinan Divarci	0:4a2754e462db	861	{
Sinan Divarci	0:4a2754e462db	862	int ret;
Sinan Divarci	0:4a2754e462db	863	max31334_sleep_config_reg_t sleep_config_reg = {};
Sinan Divarci	0:4a2754e462db	864
Sinan Divarci	0:4a2754e462db	865	ret = read_register(reg_addr.sleep_config_reg_addr, &sleep_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	866	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	867	return ret;
Sinan Divarci	0:4a2754e462db	868
Sinan Divarci	0:4a2754e462db	869	sleep_config_reg.raw \|= wakeup_enable_mask;
Sinan Divarci	0:4a2754e462db	870	return write_register(reg_addr.sleep_config_reg_addr, &sleep_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	871	}
Sinan Divarci	0:4a2754e462db	872
Sinan Divarci	0:4a2754e462db	873	int MAX31334::wakeup_disable(uint8_t wakeup_disable_mask)
Sinan Divarci	0:4a2754e462db	874	{
Sinan Divarci	0:4a2754e462db	875	int ret;
Sinan Divarci	0:4a2754e462db	876	max31334_sleep_config_reg_t sleep_config_reg = {};
Sinan Divarci	0:4a2754e462db	877
Sinan Divarci	0:4a2754e462db	878	ret = read_register(reg_addr.sleep_config_reg_addr, &sleep_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	879	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	880	return ret;
Sinan Divarci	0:4a2754e462db	881
Sinan Divarci	0:4a2754e462db	882	sleep_config_reg.raw &= ~wakeup_disable_mask;
Sinan Divarci	0:4a2754e462db	883	return write_register(reg_addr.sleep_config_reg_addr, &sleep_config_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	884	}
Sinan Divarci	0:4a2754e462db	885
Sinan Divarci	0:4a2754e462db	886	int MAX3133X::battery_voltage_detector_config(bool enable)
Sinan Divarci	0:4a2754e462db	887	{
Sinan Divarci	0:4a2754e462db	888	max3133x_pwr_mgmt_reg_t pwr_mgmt_reg = {};
Sinan Divarci	0:4a2754e462db	889	SET_BIT_FIELD(reg_addr->pwr_mgmt_reg_addr, pwr_mgmt_reg, pwr_mgmt_reg.bits.en_vbat_detect, enable);
Sinan Divarci	0:4a2754e462db	890	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	891	}
Sinan Divarci	0:4a2754e462db	892
Sinan Divarci	0:4a2754e462db	893	int MAX3133X::battery_voltage_detector_enable()
Sinan Divarci	0:4a2754e462db	894	{
Sinan Divarci	0:4a2754e462db	895	return battery_voltage_detector_config(1);
Sinan Divarci	0:4a2754e462db	896	}
Sinan Divarci	0:4a2754e462db	897
Sinan Divarci	0:4a2754e462db	898	int MAX3133X::battery_voltage_detector_disable()
Sinan Divarci	0:4a2754e462db	899	{
Sinan Divarci	0:4a2754e462db	900	return battery_voltage_detector_config(0);
Sinan Divarci	0:4a2754e462db	901	}
Sinan Divarci	0:4a2754e462db	902
Sinan Divarci	0:4a2754e462db	903	int MAX3133X::supply_select(power_mgmt_supply_t supply)
Sinan Divarci	0:4a2754e462db	904	{
Sinan Divarci	0:4a2754e462db	905	int ret;
Sinan Divarci	0:4a2754e462db	906	max3133x_pwr_mgmt_reg_t pwr_mgmt_reg = {};
Sinan Divarci	0:4a2754e462db	907
Sinan Divarci	0:4a2754e462db	908	ret = read_register(reg_addr->pwr_mgmt_reg_addr, &pwr_mgmt_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	909	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	910	return ret;
Sinan Divarci	0:4a2754e462db	911
Sinan Divarci	0:4a2754e462db	912	switch (supply) {
Sinan Divarci	0:4a2754e462db	913	case POW_MGMT_SUPPLY_SEL_VCC:
Sinan Divarci	0:4a2754e462db	914	pwr_mgmt_reg.bits.manual_sel = 1;
Sinan Divarci	0:4a2754e462db	915	pwr_mgmt_reg.bits.vback_sel = 0;
Sinan Divarci	0:4a2754e462db	916	break;
Sinan Divarci	0:4a2754e462db	917	case POW_MGMT_SUPPLY_SEL_VBAT:
Sinan Divarci	0:4a2754e462db	918	pwr_mgmt_reg.bits.manual_sel = 1;
Sinan Divarci	0:4a2754e462db	919	pwr_mgmt_reg.bits.vback_sel = 1;
Sinan Divarci	0:4a2754e462db	920	break;
Sinan Divarci	0:4a2754e462db	921	case POW_MGMT_SUPPLY_SEL_AUTO:
Sinan Divarci	0:4a2754e462db	922	default:
Sinan Divarci	0:4a2754e462db	923	pwr_mgmt_reg.bits.manual_sel = 0;
Sinan Divarci	0:4a2754e462db	924	break;
Sinan Divarci	0:4a2754e462db	925	}
Sinan Divarci	0:4a2754e462db	926
Sinan Divarci	0:4a2754e462db	927	return write_register(reg_addr->pwr_mgmt_reg_addr, &pwr_mgmt_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	928	}
Sinan Divarci	0:4a2754e462db	929
Sinan Divarci	0:4a2754e462db	930	int MAX3133X::trickle_charger_enable(trickle_charger_ohm_t res, bool diode)
Sinan Divarci	0:4a2754e462db	931	{
Sinan Divarci	0:4a2754e462db	932	max3133x_trickle_reg_reg_t trickle_reg_reg = {};
Sinan Divarci	0:4a2754e462db	933	trickle_reg_reg.bits.trickle = res;
Sinan Divarci	0:4a2754e462db	934
Sinan Divarci	0:4a2754e462db	935	if (diode)
Sinan Divarci	0:4a2754e462db	936	trickle_reg_reg.bits.trickle \|= 0x04;
Sinan Divarci	0:4a2754e462db	937
Sinan Divarci	0:4a2754e462db	938	trickle_reg_reg.bits.en_trickle = true;
Sinan Divarci	0:4a2754e462db	939
Sinan Divarci	0:4a2754e462db	940	return write_register(reg_addr->trickle_reg_addr, &trickle_reg_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	941	}
Sinan Divarci	0:4a2754e462db	942
Sinan Divarci	0:4a2754e462db	943	int MAX3133X::trickle_charger_disable()
Sinan Divarci	0:4a2754e462db	944	{
Sinan Divarci	0:4a2754e462db	945	max3133x_trickle_reg_reg_t trickle_reg_reg = {};
Sinan Divarci	0:4a2754e462db	946	SET_BIT_FIELD(reg_addr->trickle_reg_addr, trickle_reg_reg, trickle_reg_reg.bits.en_trickle, 0);
Sinan Divarci	0:4a2754e462db	947	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	948	}
Sinan Divarci	0:4a2754e462db	949
Sinan Divarci	0:4a2754e462db	950	int MAX3133X::get_timestamp(int ts_num, timestamp_t *timestamp)
Sinan Divarci	0:4a2754e462db	951	{
Sinan Divarci	0:4a2754e462db	952	int ret;
Sinan Divarci	0:4a2754e462db	953	max3133x_ts_regs_t timestamp_reg;
Sinan Divarci	0:4a2754e462db	954	max3133x_ts_flags_reg_t ts_flags_reg;
Sinan Divarci	0:4a2754e462db	955	uint8_t ts_reg_addr;
Sinan Divarci	0:4a2754e462db	956	uint8_t ts_flag_reg_addr = reg_addr->ts0_flags_reg_addr + sizeof(max3133x_ts_regs_t)*ts_num;
Sinan Divarci	0:4a2754e462db	957
Sinan Divarci	0:4a2754e462db	958	ret = read_register(ts_flag_reg_addr, (uint8_t *)&ts_flags_reg, 1);
Sinan Divarci	0:4a2754e462db	959	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	960	return ret;
Sinan Divarci	0:4a2754e462db	961
Sinan Divarci	0:4a2754e462db	962	timestamp->ts_num = (ts_num_t)ts_num;
Sinan Divarci	0:4a2754e462db	963	timestamp->ts_trigger = (ts_trigger_t)(ts_flags_reg.raw & 0xF);
Sinan Divarci	0:4a2754e462db	964
Sinan Divarci	0:4a2754e462db	965	if (ts_flags_reg.raw == NOT_TRIGGERED) // no need to read timestamp register
Sinan Divarci	0:4a2754e462db	966	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	967
Sinan Divarci	0:4a2754e462db	968	ts_reg_addr = reg_addr->ts0_sec_1_128_reg_addr + sizeof(max3133x_ts_regs_t)*ts_num;
Sinan Divarci	0:4a2754e462db	969	ret = read_register(ts_reg_addr, (uint8_t *)&timestamp_reg, sizeof(max3133x_ts_regs_t)-1);
Sinan Divarci	0:4a2754e462db	970	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	971	return ret;
Sinan Divarci	0:4a2754e462db	972
Sinan Divarci	0:4a2754e462db	973	timestamp_regs_to_time(timestamp, &timestamp_reg);
Sinan Divarci	0:4a2754e462db	974	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	975	}
Sinan Divarci	0:4a2754e462db	976
Sinan Divarci	0:4a2754e462db	977	int MAX3133X::offset_configuration(int meas)
Sinan Divarci	0:4a2754e462db	978	{
Sinan Divarci	0:4a2754e462db	979	short int offset;
Sinan Divarci	0:4a2754e462db	980	double acc = (meas - 32768)*30.5175;
Sinan Divarci	0:4a2754e462db	981
Sinan Divarci	0:4a2754e462db	982	offset = (short int)(acc/0.477);
Sinan Divarci	0:4a2754e462db	983
Sinan Divarci	0:4a2754e462db	984	return write_register(reg_addr->offset_high_reg_addr, (uint8_t *)&offset, 2);
Sinan Divarci	0:4a2754e462db	985	}
Sinan Divarci	0:4a2754e462db	986
Sinan Divarci	0:4a2754e462db	987	int MAX3133X::oscillator_flag_config(bool enable)
Sinan Divarci	0:4a2754e462db	988	{
Sinan Divarci	0:4a2754e462db	989	max3133x_int_en_reg_t int_en_reg = {};
Sinan Divarci	0:4a2754e462db	990	SET_BIT_FIELD(reg_addr->int_en_reg_addr, int_en_reg, int_en_reg.bits.dosf, !enable);
Sinan Divarci	0:4a2754e462db	991	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	992	}
Sinan Divarci	0:4a2754e462db	993
Sinan Divarci	0:4a2754e462db	994	void MAX3133X::set_intr_handler(intr_id_t id, interrupt_handler_function func, void *cb)
Sinan Divarci	0:4a2754e462db	995	{
Sinan Divarci	0:4a2754e462db	996	interrupt_handler_list[id].func = func;
Sinan Divarci	0:4a2754e462db	997	interrupt_handler_list[id].cb = cb;
Sinan Divarci	0:4a2754e462db	998	}
Sinan Divarci	0:4a2754e462db	999
Sinan Divarci	0:4a2754e462db	1000	void MAX3133X::post_interrupt_work()
Sinan Divarci	0:4a2754e462db	1001	{
Sinan Divarci	0:4a2754e462db	1002	int ret;
Sinan Divarci	0:4a2754e462db	1003	uint8_t mask;
Sinan Divarci	0:4a2754e462db	1004	max3133x_int_en_reg_t int_en_reg = {};
Sinan Divarci	0:4a2754e462db	1005	max3133x_status_reg_t status_reg = {};
Sinan Divarci	0:4a2754e462db	1006
Sinan Divarci	0:4a2754e462db	1007	while (true) {
Sinan Divarci	0:4a2754e462db	1008	ThisThread::flags_wait_any(POST_INTR_WORK_SIGNAL_ID);
Sinan Divarci	0:4a2754e462db	1009
Sinan Divarci	0:4a2754e462db	1010	ret = read_register(reg_addr->status_reg_addr, &status_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	1011	if (ret != MAX3133X_NO_ERR) {
Sinan Divarci	0:4a2754e462db	1012	pr_err("Read status register failed!");
Sinan Divarci	0:4a2754e462db	1013	continue;
Sinan Divarci	0:4a2754e462db	1014	}
Sinan Divarci	0:4a2754e462db	1015
Sinan Divarci	0:4a2754e462db	1016	ret = read_register(reg_addr->int_en_reg_addr, &int_en_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	1017	if (ret != MAX3133X_NO_ERR) {
Sinan Divarci	0:4a2754e462db	1018	pr_err("Read interrupt enable register failed!");
Sinan Divarci	0:4a2754e462db	1019	continue;
Sinan Divarci	0:4a2754e462db	1020	}
Sinan Divarci	0:4a2754e462db	1021
Sinan Divarci	0:4a2754e462db	1022	for (int i = 0; i < NUM_OF_INTR_ID; i++) {
Sinan Divarci	0:4a2754e462db	1023	mask = (1 << i);
Sinan Divarci	0:4a2754e462db	1024	if ((status_reg.raw & mask) && (int_en_reg.raw & mask)) {
Sinan Divarci	0:4a2754e462db	1025	if (interrupt_handler_list[i].func != NULL)
Sinan Divarci	0:4a2754e462db	1026	interrupt_handler_list[i].func(interrupt_handler_list[i].cb);
Sinan Divarci	0:4a2754e462db	1027	}
Sinan Divarci	0:4a2754e462db	1028	}
Sinan Divarci	0:4a2754e462db	1029	}
Sinan Divarci	0:4a2754e462db	1030	}
Sinan Divarci	0:4a2754e462db	1031
Sinan Divarci	0:4a2754e462db	1032	void MAX3133X::interrupt_handler()
Sinan Divarci	0:4a2754e462db	1033	{
Sinan Divarci	0:4a2754e462db	1034	post_intr_work_thread->flags_set(POST_INTR_WORK_SIGNAL_ID);
Sinan Divarci	0:4a2754e462db	1035	}
Sinan Divarci	0:4a2754e462db	1036
Sinan Divarci	0:4a2754e462db	1037	uint8_t MAX3133X::to_24hr(uint8_t hr, uint8_t pm) {
Sinan Divarci	0:4a2754e462db	1038	if (pm) {
Sinan Divarci	0:4a2754e462db	1039	if (hr < 12)
Sinan Divarci	0:4a2754e462db	1040	hr += 12;
Sinan Divarci	0:4a2754e462db	1041	} else {
Sinan Divarci	0:4a2754e462db	1042	if (hr == 12)
Sinan Divarci	0:4a2754e462db	1043	hr -= 12;
Sinan Divarci	0:4a2754e462db	1044	}
Sinan Divarci	0:4a2754e462db	1045	return hr;
Sinan Divarci	0:4a2754e462db	1046	}
Sinan Divarci	0:4a2754e462db	1047
Sinan Divarci	0:4a2754e462db	1048	void MAX3133X::to_12hr(uint8_t hr, uint8_t hr_12, uint8_t pm) {
Sinan Divarci	0:4a2754e462db	1049	if (hr == 0) {
Sinan Divarci	0:4a2754e462db	1050	*hr_12 = 12;
Sinan Divarci	0:4a2754e462db	1051	*pm = 0;
Sinan Divarci	0:4a2754e462db	1052	} else if (hr < 12) {
Sinan Divarci	0:4a2754e462db	1053	*hr_12 = hr;
Sinan Divarci	0:4a2754e462db	1054	*pm = 0;
Sinan Divarci	0:4a2754e462db	1055	} else if (hr == 12) {
Sinan Divarci	0:4a2754e462db	1056	*hr_12 = 12;
Sinan Divarci	0:4a2754e462db	1057	*pm = 1;
Sinan Divarci	0:4a2754e462db	1058	} else {
Sinan Divarci	0:4a2754e462db	1059	*hr_12 = hr - 12;
Sinan Divarci	0:4a2754e462db	1060	*pm = 1;
Sinan Divarci	0:4a2754e462db	1061	}
Sinan Divarci	0:4a2754e462db	1062	}
Sinan Divarci	0:4a2754e462db	1063
Sinan Divarci	0:4a2754e462db	1064	int MAX3133X::set_alarm_period(alarm_no_t alarm_no, max3133x_alarm_regs_t &regs, alarm_period_t period)
Sinan Divarci	0:4a2754e462db	1065	{
Sinan Divarci	0:4a2754e462db	1066	regs.sec.bits.am1 = 1;
Sinan Divarci	0:4a2754e462db	1067	regs.min.bits.am2 = 1;
Sinan Divarci	0:4a2754e462db	1068	regs.hrs.bits_24hr.am3 = 1;
Sinan Divarci	0:4a2754e462db	1069	regs.day_date.bits.am4 = 1;
Sinan Divarci	0:4a2754e462db	1070	regs.mon.bits.am5 = 1;
Sinan Divarci	0:4a2754e462db	1071	regs.mon.bits.am6 = 1;
Sinan Divarci	0:4a2754e462db	1072	regs.day_date.bits.dy_dt_match = 1;
Sinan Divarci	0:4a2754e462db	1073
Sinan Divarci	0:4a2754e462db	1074	switch (period) {
Sinan Divarci	0:4a2754e462db	1075	case ALARM_PERIOD_ONETIME:
Sinan Divarci	0:4a2754e462db	1076	if (alarm_no == ALARM2) /* not supported! */
Sinan Divarci	0:4a2754e462db	1077	return MAX3133X_ALARM_ONETIME_NOT_SUPP_ERR;
Sinan Divarci	0:4a2754e462db	1078	regs.mon.bits.am6 = 0;
Sinan Divarci	0:4a2754e462db	1079	case ALARM_PERIOD_YEARLY:
Sinan Divarci	0:4a2754e462db	1080	if (alarm_no == ALARM2) /* not supported! */
Sinan Divarci	0:4a2754e462db	1081	return MAX3133X_ALARM_YEARLY_NOT_SUPP_ERR;
Sinan Divarci	0:4a2754e462db	1082	regs.mon.bits.am5 = 0;
Sinan Divarci	0:4a2754e462db	1083	case ALARM_PERIOD_MONTHLY:
Sinan Divarci	0:4a2754e462db	1084	regs.day_date.bits.dy_dt_match = 0;
Sinan Divarci	0:4a2754e462db	1085	case ALARM_PERIOD_WEEKLY:
Sinan Divarci	0:4a2754e462db	1086	regs.day_date.bits.am4 = 0;
Sinan Divarci	0:4a2754e462db	1087	case ALARM_PERIOD_DAILY:
Sinan Divarci	0:4a2754e462db	1088	regs.hrs.bits_24hr.am3 = 0;
Sinan Divarci	0:4a2754e462db	1089	case ALARM_PERIOD_HOURLY:
Sinan Divarci	0:4a2754e462db	1090	regs.min.bits.am2 = 0;
Sinan Divarci	0:4a2754e462db	1091	case ALARM_PERIOD_EVERYMINUTE:
Sinan Divarci	0:4a2754e462db	1092	if ((alarm_no == ALARM2) && (period == ALARM_PERIOD_EVERYMINUTE))
Sinan Divarci	0:4a2754e462db	1093	return MAX3133X_ALARM_EVERYMINUTE_NOT_SUPP_ERR; /* Alarm2 does not support "every minute" alarm*/
Sinan Divarci	0:4a2754e462db	1094	regs.sec.bits.am1 = 0;
Sinan Divarci	0:4a2754e462db	1095	case ALARM_PERIOD_EVERYSECOND:
Sinan Divarci	0:4a2754e462db	1096	if ((alarm_no == ALARM2) && (period == ALARM_PERIOD_EVERYSECOND))
Sinan Divarci	0:4a2754e462db	1097	return MAX3133X_ALARM_EVERYSECOND_NOT_SUPP_ERR; /* Alarm2 does not support "once per second" alarm*/
Sinan Divarci	0:4a2754e462db	1098	break;
Sinan Divarci	0:4a2754e462db	1099	default:
Sinan Divarci	0:4a2754e462db	1100	return MAX3133X_INVALID_ALARM_PERIOD_ERR;
Sinan Divarci	0:4a2754e462db	1101	}
Sinan Divarci	0:4a2754e462db	1102
Sinan Divarci	0:4a2754e462db	1103	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	1104	}
Sinan Divarci	0:4a2754e462db	1105
Sinan Divarci	0:4a2754e462db	1106	int MAX3133X::time_to_alarm_regs(max3133x_alarm_regs_t &regs, const struct tm *alarm_time, hour_format_t format)
Sinan Divarci	0:4a2754e462db	1107	{
Sinan Divarci	0:4a2754e462db	1108	regs.sec.bcd.value = BIN2BCD(alarm_time->tm_sec);
Sinan Divarci	0:4a2754e462db	1109	regs.min.bcd.value = BIN2BCD(alarm_time->tm_min);
Sinan Divarci	0:4a2754e462db	1110
Sinan Divarci	0:4a2754e462db	1111	if (format == HOUR24)
Sinan Divarci	0:4a2754e462db	1112	regs.hrs.bcd_24hr.value = BIN2BCD(alarm_time->tm_hour);
Sinan Divarci	0:4a2754e462db	1113	else if (format == HOUR12) {
Sinan Divarci	0:4a2754e462db	1114	uint8_t hr_12, pm;
Sinan Divarci	0:4a2754e462db	1115	to_12hr(alarm_time->tm_hour, &hr_12, &pm);
Sinan Divarci	0:4a2754e462db	1116	regs.hrs.bcd_12hr.value = BIN2BCD(hr_12);
Sinan Divarci	0:4a2754e462db	1117	regs.hrs.bits_12hr.am_pm = pm;
Sinan Divarci	0:4a2754e462db	1118	} else {
Sinan Divarci	0:4a2754e462db	1119	pr_err("Invalid Hour Format!");
Sinan Divarci	0:4a2754e462db	1120	return MAX3133X_INVALID_TIME_ERR;
Sinan Divarci	0:4a2754e462db	1121	}
Sinan Divarci	0:4a2754e462db	1122
Sinan Divarci	0:4a2754e462db	1123	if (regs.day_date.bits.dy_dt_match == 0)/* Date match */
Sinan Divarci	0:4a2754e462db	1124	regs.day_date.bcd_date.value = BIN2BCD(alarm_time->tm_mday);
Sinan Divarci	0:4a2754e462db	1125	else /* Day match */
Sinan Divarci	0:4a2754e462db	1126	regs.day_date.bcd_day.value = BIN2BCD(alarm_time->tm_wday);
Sinan Divarci	0:4a2754e462db	1127
Sinan Divarci	0:4a2754e462db	1128	regs.mon.bcd.value = BIN2BCD(alarm_time->tm_mon + 1);
Sinan Divarci	0:4a2754e462db	1129
Sinan Divarci	0:4a2754e462db	1130	if (alarm_time->tm_year >= 200)
Sinan Divarci	0:4a2754e462db	1131	regs.year.bcd.value = BIN2BCD(alarm_time->tm_year - 200);
Sinan Divarci	0:4a2754e462db	1132	else if (alarm_time->tm_year >= 100)
Sinan Divarci	0:4a2754e462db	1133	regs.year.bcd.value = BIN2BCD(alarm_time->tm_year - 100);
Sinan Divarci	0:4a2754e462db	1134	else {
Sinan Divarci	0:4a2754e462db	1135	pr_err("Invalid set year!");
Sinan Divarci	0:4a2754e462db	1136	return MAX3133X_INVALID_DATE_ERR;
Sinan Divarci	0:4a2754e462db	1137	}
Sinan Divarci	0:4a2754e462db	1138
Sinan Divarci	0:4a2754e462db	1139	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	1140	}
Sinan Divarci	0:4a2754e462db	1141
Sinan Divarci	0:4a2754e462db	1142	int MAX3133X::set_alarm_regs(alarm_no_t alarm_no, const max3133x_alarm_regs_t *regs)
Sinan Divarci	0:4a2754e462db	1143	{
Sinan Divarci	0:4a2754e462db	1144	uint8_t len = sizeof(max3133x_alarm_regs_t);
Sinan Divarci	0:4a2754e462db	1145
Sinan Divarci	0:4a2754e462db	1146	if (alarm_no == ALARM1)
Sinan Divarci	0:4a2754e462db	1147	return write_register(reg_addr->alm1_sec_reg_addr, (uint8_t *)&regs->sec.raw, len);
Sinan Divarci	0:4a2754e462db	1148	else
Sinan Divarci	0:4a2754e462db	1149	return write_register(reg_addr->alm2_min_reg_addr, (uint8_t *)&regs->min.raw, len-3);
Sinan Divarci	0:4a2754e462db	1150	}
Sinan Divarci	0:4a2754e462db	1151
Sinan Divarci	0:4a2754e462db	1152	int MAX3133X::get_rtc_time_format(hour_format_t *format)
Sinan Divarci	0:4a2754e462db	1153	{
Sinan Divarci	0:4a2754e462db	1154	int ret;
Sinan Divarci	0:4a2754e462db	1155	max3133x_hours_reg_t hours_reg = {};
Sinan Divarci	0:4a2754e462db	1156	ret = read_register(reg_addr->hours_reg_addr, (uint8_t *)&hours_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	1157	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	1158	return ret;
Sinan Divarci	0:4a2754e462db	1159
Sinan Divarci	0:4a2754e462db	1160	*format = (hour_format_t)hours_reg.bits_24hr.f_24_12;
Sinan Divarci	0:4a2754e462db	1161
Sinan Divarci	0:4a2754e462db	1162	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	1163	}
Sinan Divarci	0:4a2754e462db	1164
Sinan Divarci	0:4a2754e462db	1165	int MAX3133X::set_alarm(alarm_no_t alarm_no, const struct tm *alarm_time, alarm_period_t period)
Sinan Divarci	0:4a2754e462db	1166	{
Sinan Divarci	0:4a2754e462db	1167	int ret;
Sinan Divarci	0:4a2754e462db	1168	max3133x_alarm_regs_t alarm_regs = {};
Sinan Divarci	0:4a2754e462db	1169	hour_format_t format = {};
Sinan Divarci	0:4a2754e462db	1170
Sinan Divarci	0:4a2754e462db	1171	ret = set_alarm_period(alarm_no, alarm_regs, period);
Sinan Divarci	0:4a2754e462db	1172	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	1173	return ret;
Sinan Divarci	0:4a2754e462db	1174
Sinan Divarci	0:4a2754e462db	1175	ret = get_rtc_time_format(&format);
Sinan Divarci	0:4a2754e462db	1176	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	1177	return ret;
Sinan Divarci	0:4a2754e462db	1178
Sinan Divarci	0:4a2754e462db	1179	/* Convert time structure to alarm registers */
Sinan Divarci	0:4a2754e462db	1180	ret = time_to_alarm_regs(alarm_regs, alarm_time, format);
Sinan Divarci	0:4a2754e462db	1181	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	1182	return ret;
Sinan Divarci	0:4a2754e462db	1183
Sinan Divarci	0:4a2754e462db	1184	return set_alarm_regs(alarm_no, &alarm_regs);
Sinan Divarci	0:4a2754e462db	1185	}
Sinan Divarci	0:4a2754e462db	1186
Sinan Divarci	0:4a2754e462db	1187	inline void MAX3133X::alarm_regs_to_time(alarm_no_t alarm_no, struct tm alarm_time, const max3133x_alarm_regs_t regs, hour_format_t format)
Sinan Divarci	0:4a2754e462db	1188	{
Sinan Divarci	0:4a2754e462db	1189	alarm_time->tm_min = BCD2BIN(regs->min.bcd.value);
Sinan Divarci	0:4a2754e462db	1190
Sinan Divarci	0:4a2754e462db	1191	if (format == HOUR24)
Sinan Divarci	0:4a2754e462db	1192	alarm_time->tm_hour = BCD2BIN(regs->hrs.bcd_24hr.value);
Sinan Divarci	0:4a2754e462db	1193	else if (format == HOUR12)
Sinan Divarci	0:4a2754e462db	1194	alarm_time->tm_hour = to_24hr(BCD2BIN(regs->hrs.bcd_12hr.value), regs->hrs.bits_12hr.am_pm);
Sinan Divarci	0:4a2754e462db	1195
Sinan Divarci	0:4a2754e462db	1196	if (regs->day_date.bits.dy_dt_match == 0) { /* date */
Sinan Divarci	0:4a2754e462db	1197	alarm_time->tm_mday = BCD2BIN(regs->day_date.bcd_date.value);
Sinan Divarci	0:4a2754e462db	1198	alarm_time->tm_wday = 0;
Sinan Divarci	0:4a2754e462db	1199	} else { /* day */
Sinan Divarci	0:4a2754e462db	1200	alarm_time->tm_wday = BCD2BIN(regs->day_date.bcd_day.value);
Sinan Divarci	0:4a2754e462db	1201	alarm_time->tm_mday = 0;
Sinan Divarci	0:4a2754e462db	1202	}
Sinan Divarci	0:4a2754e462db	1203
Sinan Divarci	0:4a2754e462db	1204	if (alarm_no == ALARM1) {
Sinan Divarci	0:4a2754e462db	1205	alarm_time->tm_sec = BCD2BIN(regs->sec.bcd.value);
Sinan Divarci	0:4a2754e462db	1206	alarm_time->tm_mon = BCD2BIN(regs->mon.bcd.value) - 1;
Sinan Divarci	0:4a2754e462db	1207	alarm_time->tm_year = BCD2BIN(regs->year.bcd.value) + 100; /* XXX no century bit */
Sinan Divarci	0:4a2754e462db	1208	}
Sinan Divarci	0:4a2754e462db	1209	}
Sinan Divarci	0:4a2754e462db	1210
Sinan Divarci	0:4a2754e462db	1211	int MAX3133X::get_alarm(alarm_no_t alarm_no, struct tm alarm_time, alarm_period_t period, bool *is_enabled)
Sinan Divarci	0:4a2754e462db	1212	{
Sinan Divarci	0:4a2754e462db	1213	int ret;
Sinan Divarci	0:4a2754e462db	1214	max3133x_alarm_regs_t alarm_regs = {};
Sinan Divarci	0:4a2754e462db	1215	max3133x_int_en_reg_t int_en_reg = {};
Sinan Divarci	0:4a2754e462db	1216	uint8_t len = sizeof(max3133x_alarm_regs_t);
Sinan Divarci	0:4a2754e462db	1217	hour_format_t format;
Sinan Divarci	0:4a2754e462db	1218
Sinan Divarci	0:4a2754e462db	1219	ret = get_rtc_time_format(&format);
Sinan Divarci	0:4a2754e462db	1220	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	1221	return ret;
Sinan Divarci	0:4a2754e462db	1222
Sinan Divarci	0:4a2754e462db	1223	if (alarm_no == ALARM1)
Sinan Divarci	0:4a2754e462db	1224	ret = read_register(reg_addr->alm1_sec_reg_addr, &alarm_regs.sec.raw, len);
Sinan Divarci	0:4a2754e462db	1225	else
Sinan Divarci	0:4a2754e462db	1226	ret = read_register(reg_addr->alm2_min_reg_addr, &alarm_regs.min.raw, len-3);
Sinan Divarci	0:4a2754e462db	1227
Sinan Divarci	0:4a2754e462db	1228	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	1229	return ret;
Sinan Divarci	0:4a2754e462db	1230
Sinan Divarci	0:4a2754e462db	1231	/* Convert alarm registers to time structure */
Sinan Divarci	0:4a2754e462db	1232	alarm_regs_to_time(alarm_no, alarm_time, &alarm_regs, format);
Sinan Divarci	0:4a2754e462db	1233
Sinan Divarci	0:4a2754e462db	1234	*period = ALARM_PERIOD_EVERYSECOND;
Sinan Divarci	0:4a2754e462db	1235
Sinan Divarci	0:4a2754e462db	1236	if (alarm_no == ALARM1) {
Sinan Divarci	0:4a2754e462db	1237	if (alarm_regs.sec.bits.am1 == 0)
Sinan Divarci	0:4a2754e462db	1238	*period = ALARM_PERIOD_EVERYMINUTE;
Sinan Divarci	0:4a2754e462db	1239	}
Sinan Divarci	0:4a2754e462db	1240
Sinan Divarci	0:4a2754e462db	1241	if (alarm_regs.min.bits.am2 == 0)
Sinan Divarci	0:4a2754e462db	1242	*period = ALARM_PERIOD_HOURLY;
Sinan Divarci	0:4a2754e462db	1243	if (alarm_regs.hrs.bits_24hr.am3 == 0)
Sinan Divarci	0:4a2754e462db	1244	*period = ALARM_PERIOD_DAILY;
Sinan Divarci	0:4a2754e462db	1245	if (alarm_regs.day_date.bits.am4 == 0)
Sinan Divarci	0:4a2754e462db	1246	*period = ALARM_PERIOD_WEEKLY;
Sinan Divarci	0:4a2754e462db	1247	if (alarm_regs.day_date.bits.dy_dt_match == 0)
Sinan Divarci	0:4a2754e462db	1248	*period = ALARM_PERIOD_MONTHLY;
Sinan Divarci	0:4a2754e462db	1249	if (alarm_no == ALARM1) {
Sinan Divarci	0:4a2754e462db	1250	if (alarm_regs.mon.bits.am5 == 0)
Sinan Divarci	0:4a2754e462db	1251	*period = ALARM_PERIOD_YEARLY;
Sinan Divarci	0:4a2754e462db	1252	if (alarm_regs.mon.bits.am6 == 0)
Sinan Divarci	0:4a2754e462db	1253	*period = ALARM_PERIOD_ONETIME;
Sinan Divarci	0:4a2754e462db	1254	}
Sinan Divarci	0:4a2754e462db	1255
Sinan Divarci	0:4a2754e462db	1256	ret = read_register(reg_addr->int_en_reg_addr, (uint8_t *)&int_en_reg.raw, 1);
Sinan Divarci	0:4a2754e462db	1257	if (ret != MAX3133X_NO_ERR)
Sinan Divarci	0:4a2754e462db	1258	return ret;
Sinan Divarci	0:4a2754e462db	1259
Sinan Divarci	0:4a2754e462db	1260	if (alarm_no == ALARM1)
Sinan Divarci	0:4a2754e462db	1261	*is_enabled = ((int_en_reg.raw & A1IE) == A1IE);
Sinan Divarci	0:4a2754e462db	1262	else
Sinan Divarci	0:4a2754e462db	1263	*is_enabled = ((int_en_reg.raw & A2IE) == A2IE);
Sinan Divarci	0:4a2754e462db	1264
Sinan Divarci	0:4a2754e462db	1265	return MAX3133X_NO_ERR;
Sinan Divarci	0:4a2754e462db	1266	}
Sinan Divarci	0:4a2754e462db	1267
Sinan Divarci	0:4a2754e462db	1268	const MAX3133X::reg_addr_t MAX31334::reg_addr = {
Sinan Divarci	0:4a2754e462db	1269	MAX31334_STATUS,
Sinan Divarci	0:4a2754e462db	1270	MAX31334_INT_EN,
Sinan Divarci	0:4a2754e462db	1271	MAX31334_RTC_RESET,
Sinan Divarci	0:4a2754e462db	1272	MAX31334_RTC_CONFIG1,
Sinan Divarci	0:4a2754e462db	1273	MAX31334_RTC_CONFIG2,
Sinan Divarci	0:4a2754e462db	1274	MAX31334_TIMESTAMP_CONFIG,
Sinan Divarci	0:4a2754e462db	1275	MAX31334_TIMER_CONFIG,
Sinan Divarci	0:4a2754e462db	1276	MAX31334_SLEEP_CONFIG,
Sinan Divarci	0:4a2754e462db	1277	MAX31334_SECONDS_1_128,
Sinan Divarci	0:4a2754e462db	1278	MAX31334_SECONDS,
Sinan Divarci	0:4a2754e462db	1279	MAX31334_MINUTES,
Sinan Divarci	0:4a2754e462db	1280	MAX31334_HOURS,
Sinan Divarci	0:4a2754e462db	1281	MAX31334_DAY,
Sinan Divarci	0:4a2754e462db	1282	MAX31334_DATE,
Sinan Divarci	0:4a2754e462db	1283	MAX31334_MONTH,
Sinan Divarci	0:4a2754e462db	1284	MAX31334_YEAR,
Sinan Divarci	0:4a2754e462db	1285	MAX31334_ALM1_SEC,
Sinan Divarci	0:4a2754e462db	1286	MAX31334_ALM1_MIN,
Sinan Divarci	0:4a2754e462db	1287	MAX31334_ALM1_HRS,
Sinan Divarci	0:4a2754e462db	1288	MAX31334_ALM1_DAY_DATE,
Sinan Divarci	0:4a2754e462db	1289	MAX31334_ALM1_MON,
Sinan Divarci	0:4a2754e462db	1290	MAX31334_ALM1_YEAR,
Sinan Divarci	0:4a2754e462db	1291	MAX31334_ALM2_MIN,
Sinan Divarci	0:4a2754e462db	1292	MAX31334_ALM2_HRS,
Sinan Divarci	0:4a2754e462db	1293	MAX31334_ALM2_DAY_DATE,
Sinan Divarci	0:4a2754e462db	1294	REG_NOT_AVAILABLE,
Sinan Divarci	0:4a2754e462db	1295	MAX31334_TIMER_COUNT2,
Sinan Divarci	0:4a2754e462db	1296	MAX31334_TIMER_COUNT1,
Sinan Divarci	0:4a2754e462db	1297	REG_NOT_AVAILABLE,
Sinan Divarci	0:4a2754e462db	1298	MAX31334_TIMER_INIT2,
Sinan Divarci	0:4a2754e462db	1299	MAX31334_TIMER_INIT1,
Sinan Divarci	0:4a2754e462db	1300	MAX31334_PWR_MGMT,
Sinan Divarci	0:4a2754e462db	1301	MAX31334_TRICKLE_REG,
Sinan Divarci	0:4a2754e462db	1302	MAX31334_OFFSET_HIGH,
Sinan Divarci	0:4a2754e462db	1303	MAX31334_OFFSET_LOW,
Sinan Divarci	0:4a2754e462db	1304	MAX31334_TS0_SEC_1_128,
Sinan Divarci	0:4a2754e462db	1305	MAX31334_TS0_SEC,
Sinan Divarci	0:4a2754e462db	1306	MAX31334_TS0_MIN,
Sinan Divarci	0:4a2754e462db	1307	MAX31334_TS0_HOUR,
Sinan Divarci	0:4a2754e462db	1308	MAX31334_TS0_DATE,
Sinan Divarci	0:4a2754e462db	1309	MAX31334_TS0_MONTH,
Sinan Divarci	0:4a2754e462db	1310	MAX31334_TS0_YEAR,
Sinan Divarci	0:4a2754e462db	1311	MAX31334_TS0_FLAGS,
Sinan Divarci	0:4a2754e462db	1312	MAX31334_TS1_SEC_1_128,
Sinan Divarci	0:4a2754e462db	1313	MAX31334_TS1_SEC,
Sinan Divarci	0:4a2754e462db	1314	MAX31334_TS1_MIN,
Sinan Divarci	0:4a2754e462db	1315	MAX31334_TS1_HOUR,
Sinan Divarci	0:4a2754e462db	1316	MAX31334_TS1_DATE,
Sinan Divarci	0:4a2754e462db	1317	MAX31334_TS1_MONTH,
Sinan Divarci	0:4a2754e462db	1318	MAX31334_TS1_YEAR,
Sinan Divarci	0:4a2754e462db	1319	MAX31334_TS1_FLAGS,
Sinan Divarci	0:4a2754e462db	1320	MAX31334_TS2_SEC_1_128,
Sinan Divarci	0:4a2754e462db	1321	MAX31334_TS2_SEC,
Sinan Divarci	0:4a2754e462db	1322	MAX31334_TS2_MIN,
Sinan Divarci	0:4a2754e462db	1323	MAX31334_TS2_HOUR,
Sinan Divarci	0:4a2754e462db	1324	MAX31334_TS2_DATE,
Sinan Divarci	0:4a2754e462db	1325	MAX31334_TS2_MONTH,
Sinan Divarci	0:4a2754e462db	1326	MAX31334_TS2_YEAR,
Sinan Divarci	0:4a2754e462db	1327	MAX31334_TS2_FLAGS,
Sinan Divarci	0:4a2754e462db	1328	MAX31334_TS3_SEC_1_128,
Sinan Divarci	0:4a2754e462db	1329	MAX31334_TS3_SEC,
Sinan Divarci	0:4a2754e462db	1330	MAX31334_TS3_MIN,
Sinan Divarci	0:4a2754e462db	1331	MAX31334_TS3_HOUR,
Sinan Divarci	0:4a2754e462db	1332	MAX31334_TS3_DATE,
Sinan Divarci	0:4a2754e462db	1333	MAX31334_TS3_MONTH,
Sinan Divarci	0:4a2754e462db	1334	MAX31334_TS3_YEAR,
Sinan Divarci	0:4a2754e462db	1335	MAX31334_TS3_FLAGS
Sinan Divarci	0:4a2754e462db	1336	};
Sinan Divarci	0:4a2754e462db	1337
Sinan Divarci	0:4a2754e462db	1338	const MAX3133X::reg_addr_t MAX31331::reg_addr = {
Sinan Divarci	0:4a2754e462db	1339	MAX31331_STATUS,
Sinan Divarci	0:4a2754e462db	1340	MAX31331_INT_EN,
Sinan Divarci	0:4a2754e462db	1341	MAX31331_RTC_RESET,
Sinan Divarci	0:4a2754e462db	1342	MAX31331_RTC_CONFIG1,
Sinan Divarci	0:4a2754e462db	1343	MAX31331_RTC_CONFIG2,
Sinan Divarci	0:4a2754e462db	1344	MAX31331_TIMESTAMP_CONFIG,
Sinan Divarci	0:4a2754e462db	1345	MAX31331_TIMER_CONFIG,
Sinan Divarci	0:4a2754e462db	1346	REG_NOT_AVAILABLE,
Sinan Divarci	0:4a2754e462db	1347	MAX31331_SECONDS_1_128,
Sinan Divarci	0:4a2754e462db	1348	MAX31331_SECONDS,
Sinan Divarci	0:4a2754e462db	1349	MAX31331_MINUTES,
Sinan Divarci	0:4a2754e462db	1350	MAX31331_HOURS,
Sinan Divarci	0:4a2754e462db	1351	MAX31331_DAY,
Sinan Divarci	0:4a2754e462db	1352	MAX31331_DATE,
Sinan Divarci	0:4a2754e462db	1353	MAX31331_MONTH,
Sinan Divarci	0:4a2754e462db	1354	MAX31331_YEAR,
Sinan Divarci	0:4a2754e462db	1355	MAX31331_ALM1_SEC,
Sinan Divarci	0:4a2754e462db	1356	MAX31331_ALM1_MIN,
Sinan Divarci	0:4a2754e462db	1357	MAX31331_ALM1_HRS,
Sinan Divarci	0:4a2754e462db	1358	MAX31331_ALM1_DAY_DATE,
Sinan Divarci	0:4a2754e462db	1359	MAX31331_ALM1_MON,
Sinan Divarci	0:4a2754e462db	1360	MAX31331_ALM1_YEAR,
Sinan Divarci	0:4a2754e462db	1361	MAX31331_ALM2_MIN,
Sinan Divarci	0:4a2754e462db	1362	MAX31331_ALM2_HRS,
Sinan Divarci	0:4a2754e462db	1363	MAX31331_ALM2_DAY_DATE,
Sinan Divarci	0:4a2754e462db	1364	MAX31331_TIMER_COUNT,
Sinan Divarci	0:4a2754e462db	1365	REG_NOT_AVAILABLE,
Sinan Divarci	0:4a2754e462db	1366	REG_NOT_AVAILABLE,
Sinan Divarci	0:4a2754e462db	1367	MAX31331_TIMER_INIT,
Sinan Divarci	0:4a2754e462db	1368	REG_NOT_AVAILABLE,
Sinan Divarci	0:4a2754e462db	1369	REG_NOT_AVAILABLE,
Sinan Divarci	0:4a2754e462db	1370	MAX31331_PWR_MGMT,
Sinan Divarci	0:4a2754e462db	1371	MAX31331_TRICKLE_REG,
Sinan Divarci	0:4a2754e462db	1372	MAX31331_OFFSET_HIGH,
Sinan Divarci	0:4a2754e462db	1373	MAX31331_OFFSET_LOW,
Sinan Divarci	0:4a2754e462db	1374	MAX31331_TS0_SEC_1_128,
Sinan Divarci	0:4a2754e462db	1375	MAX31331_TS0_SEC,
Sinan Divarci	0:4a2754e462db	1376	MAX31331_TS0_MIN,
Sinan Divarci	0:4a2754e462db	1377	MAX31331_TS0_HOUR,
Sinan Divarci	0:4a2754e462db	1378	MAX31331_TS0_DATE,
Sinan Divarci	0:4a2754e462db	1379	MAX31331_TS0_MONTH,
Sinan Divarci	0:4a2754e462db	1380	MAX31331_TS0_YEAR,
Sinan Divarci	0:4a2754e462db	1381	MAX31331_TS0_FLAGS,
Sinan Divarci	0:4a2754e462db	1382	MAX31331_TS1_SEC_1_128,
Sinan Divarci	0:4a2754e462db	1383	MAX31331_TS1_SEC,
Sinan Divarci	0:4a2754e462db	1384	MAX31331_TS1_MIN,
Sinan Divarci	0:4a2754e462db	1385	MAX31331_TS1_HOUR,
Sinan Divarci	0:4a2754e462db	1386	MAX31331_TS1_DATE,
Sinan Divarci	0:4a2754e462db	1387	MAX31331_TS1_MONTH,
Sinan Divarci	0:4a2754e462db	1388	MAX31331_TS1_YEAR,
Sinan Divarci	0:4a2754e462db	1389	MAX31331_TS1_FLAGS,
Sinan Divarci	0:4a2754e462db	1390	MAX31331_TS2_SEC_1_128,
Sinan Divarci	0:4a2754e462db	1391	MAX31331_TS2_SEC,
Sinan Divarci	0:4a2754e462db	1392	MAX31331_TS2_MIN,
Sinan Divarci	0:4a2754e462db	1393	MAX31331_TS2_HOUR,
Sinan Divarci	0:4a2754e462db	1394	MAX31331_TS2_DATE,
Sinan Divarci	0:4a2754e462db	1395	MAX31331_TS2_MONTH,
Sinan Divarci	0:4a2754e462db	1396	MAX31331_TS2_YEAR,
Sinan Divarci	0:4a2754e462db	1397	MAX31331_TS2_FLAGS,
Sinan Divarci	0:4a2754e462db	1398	MAX31331_TS3_SEC_1_128,
Sinan Divarci	0:4a2754e462db	1399	MAX31331_TS3_SEC,
Sinan Divarci	0:4a2754e462db	1400	MAX31331_TS3_MIN,
Sinan Divarci	0:4a2754e462db	1401	MAX31331_TS3_HOUR,
Sinan Divarci	0:4a2754e462db	1402	MAX31331_TS3_DATE,
Sinan Divarci	0:4a2754e462db	1403	MAX31331_TS3_MONTH,
Sinan Divarci	0:4a2754e462db	1404	MAX31331_TS3_YEAR,
Sinan Divarci	0:4a2754e462db	1405	MAX31331_TS3_FLAGS
Sinan Divarci	0:4a2754e462db	1406	};

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Type:	Library
Created:	02 Aug 2022
Imports:	1
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	110

max3133x.cpp@0:4a2754e462db, 22 months ago (annotated)

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