Maxim Integrated
MAX7032 Transceiver Mbed Driver
Max7032_regs.h@0:65766360f6b9, 2021-08-02 (annotated)
- Committer:
- Sinan Divarci
- Date:
- Mon Aug 02 16:42:52 2021 +0300
- Revision:
- 0:65766360f6b9
initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Sinan Divarci |
0:65766360f6b9 | 1 | /******************************************************************************* |
| Sinan Divarci |
0:65766360f6b9 | 2 | * Copyright(C) Maxim Integrated Products, Inc., All Rights Reserved. |
| Sinan Divarci |
0:65766360f6b9 | 3 | * |
| Sinan Divarci |
0:65766360f6b9 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Sinan Divarci |
0:65766360f6b9 | 5 | * copy of this software and associated documentation files(the "Software"), |
| Sinan Divarci |
0:65766360f6b9 | 6 | * to deal in the Software without restriction, including without limitation |
| Sinan Divarci |
0:65766360f6b9 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Sinan Divarci |
0:65766360f6b9 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Sinan Divarci |
0:65766360f6b9 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Sinan Divarci |
0:65766360f6b9 | 10 | * |
| Sinan Divarci |
0:65766360f6b9 | 11 | * The above copyright notice and this permission notice shall be included |
| Sinan Divarci |
0:65766360f6b9 | 12 | * in all copies or substantial portions of the Software. |
| Sinan Divarci |
0:65766360f6b9 | 13 | * |
| Sinan Divarci |
0:65766360f6b9 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Sinan Divarci |
0:65766360f6b9 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Sinan Divarci |
0:65766360f6b9 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Sinan Divarci |
0:65766360f6b9 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Sinan Divarci |
0:65766360f6b9 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Sinan Divarci |
0:65766360f6b9 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Sinan Divarci |
0:65766360f6b9 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Sinan Divarci |
0:65766360f6b9 | 21 | * |
| Sinan Divarci |
0:65766360f6b9 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Sinan Divarci |
0:65766360f6b9 | 23 | * Products, Inc.shall not be used except as stated in the Maxim Integrated |
| Sinan Divarci |
0:65766360f6b9 | 24 | * Products, Inc.Branding Policy. |
| Sinan Divarci |
0:65766360f6b9 | 25 | * |
| Sinan Divarci |
0:65766360f6b9 | 26 | * The mere transfer of this software does not imply any licenses |
| Sinan Divarci |
0:65766360f6b9 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Sinan Divarci |
0:65766360f6b9 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Sinan Divarci |
0:65766360f6b9 | 29 | * property whatsoever. Maxim Integrated Products, Inc.retains all |
| Sinan Divarci |
0:65766360f6b9 | 30 | * ownership rights. |
| Sinan Divarci |
0:65766360f6b9 | 31 | ******************************************************************************* |
| Sinan Divarci |
0:65766360f6b9 | 32 | */ |
| Sinan Divarci |
0:65766360f6b9 | 33 | |
| Sinan Divarci |
0:65766360f6b9 | 34 | #ifndef MAX7032_REGS_H_ |
| Sinan Divarci |
0:65766360f6b9 | 35 | #define MAX7032_REGS_H_ |
| Sinan Divarci |
0:65766360f6b9 | 36 | |
| Sinan Divarci |
0:65766360f6b9 | 37 | /** |
| Sinan Divarci |
0:65766360f6b9 | 38 | * @brief POWER Register |
| Sinan Divarci |
0:65766360f6b9 | 39 | * |
| Sinan Divarci |
0:65766360f6b9 | 40 | * Address : 0x00 |
| Sinan Divarci |
0:65766360f6b9 | 41 | */ |
| Sinan Divarci |
0:65766360f6b9 | 42 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 43 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 44 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 45 | unsigned char x : 1; /**< None Not used */ |
| Sinan Divarci |
0:65766360f6b9 | 46 | unsigned char rssio : 1; /**< RSSI amplifier enable 1 = Enable buffer 0 = Disable buffer */ |
| Sinan Divarci |
0:65766360f6b9 | 47 | unsigned char pa : 1; /**< Transmitter PA enable 1 = Enable PA 0 = Disable PA */ |
| Sinan Divarci |
0:65766360f6b9 | 48 | unsigned char pkdet : 1; /**< Peak-detector enable 1 = Enable peak detector 0 = Disable peak detector */ |
| Sinan Divarci |
0:65766360f6b9 | 49 | unsigned char baseb : 1; /**< Baseband enable 1 = Enable baseband 0 = Disable baseband */ |
| Sinan Divarci |
0:65766360f6b9 | 50 | unsigned char mixer : 1; /**< Mixer enable 1 = Enable mixer 0 = Disable mixer */ |
| Sinan Divarci |
0:65766360f6b9 | 51 | unsigned char agc : 1; /**< AGC enable 1 = Enable AGC 0 = Disable AGC */ |
| Sinan Divarci |
0:65766360f6b9 | 52 | unsigned char lna : 1; /**< LNA enable 1 = Enable LNA 0 = Disable LNA */ |
| Sinan Divarci |
0:65766360f6b9 | 53 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 54 | } max7032_power_t; |
| Sinan Divarci |
0:65766360f6b9 | 55 | |
| Sinan Divarci |
0:65766360f6b9 | 56 | /** |
| Sinan Divarci |
0:65766360f6b9 | 57 | * @brief CONTRL Register |
| Sinan Divarci |
0:65766360f6b9 | 58 | * |
| Sinan Divarci |
0:65766360f6b9 | 59 | * Address : 0x01 |
| Sinan Divarci |
0:65766360f6b9 | 60 | */ |
| Sinan Divarci |
0:65766360f6b9 | 61 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 62 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 63 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 64 | unsigned char sleep : 1; /**< Sleep mode 1 = Deep-sleep |
| Sinan Divarci |
0:65766360f6b9 | 65 | 0 = Normal operation */ |
| Sinan Divarci |
0:65766360f6b9 | 66 | unsigned char ckout : 1; /**< Crystal clock output enable 1 = Enable crystal clock output |
| Sinan Divarci |
0:65766360f6b9 | 67 | 0 = Disable crystal clock output */ |
| Sinan Divarci |
0:65766360f6b9 | 68 | unsigned char fcal : 1; /**< FSK calibration 1 = Perform FSK calibration Automatically */ |
| Sinan Divarci |
0:65766360f6b9 | 69 | unsigned char pcal : 1; /**< Polling timer calibration 1 = Perform polling timer calibration Automatically*/ |
| Sinan Divarci |
0:65766360f6b9 | 70 | unsigned char x : 1; /**< None Not used*/ |
| Sinan Divarci |
0:65766360f6b9 | 71 | unsigned char trk_en : 1; /**< Manual peak-detector tracking 1 = Force manual peak-detector tracking |
| Sinan Divarci |
0:65766360f6b9 | 72 | 0 = Release peak-detector tracking*/ |
| Sinan Divarci |
0:65766360f6b9 | 73 | unsigned char gain : 1; /**< Gain state 1 = Force manual high-gain state if MGAIN = 1 |
| Sinan Divarci |
0:65766360f6b9 | 74 | 0 = Force manual low-gain state if MGAIN = 1*/ |
| Sinan Divarci |
0:65766360f6b9 | 75 | unsigned char agclk : 1; /**< AGC locking feature 1 = Enable AGC lock |
| Sinan Divarci |
0:65766360f6b9 | 76 | 0 = Disable AGC lock*/ |
| Sinan Divarci |
0:65766360f6b9 | 77 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 78 | } max7032_contrl_t; |
| Sinan Divarci |
0:65766360f6b9 | 79 | |
| Sinan Divarci |
0:65766360f6b9 | 80 | /** |
| Sinan Divarci |
0:65766360f6b9 | 81 | * @brief CONF0 Register |
| Sinan Divarci |
0:65766360f6b9 | 82 | * |
| Sinan Divarci |
0:65766360f6b9 | 83 | * Address : 0x02 |
| Sinan Divarci |
0:65766360f6b9 | 84 | */ |
| Sinan Divarci |
0:65766360f6b9 | 85 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 86 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 87 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 88 | unsigned char onps : 2; /**< On-timer prescaler Sets the time base for the on timer */ |
| Sinan Divarci |
0:65766360f6b9 | 89 | unsigned char ofps : 2; /**< Off-timer prescaler Sets the time base for the off timer */ |
| Sinan Divarci |
0:65766360f6b9 | 90 | unsigned char drx : 1; /**< Discontinuous receive mode 1 = Enable DRX |
| Sinan Divarci |
0:65766360f6b9 | 91 | 0 = Disable DRX */ |
| Sinan Divarci |
0:65766360f6b9 | 92 | unsigned char mgain : 1; /**< Manual gain mode 1 = Enable manual-gain mode |
| Sinan Divarci |
0:65766360f6b9 | 93 | 0 = Disable manual-gain mode */ |
| Sinan Divarci |
0:65766360f6b9 | 94 | unsigned char t_r : 1; /**< Transmit or receive 1 = Enable transmit mode of the transceiver |
| Sinan Divarci |
0:65766360f6b9 | 95 | 0 = Enable receive mode of the transceiver */ |
| Sinan Divarci |
0:65766360f6b9 | 96 | unsigned char mode : 1; /**< FSK or ASK modulation 1 = Enable FSK for both receive and transmit |
| Sinan Divarci |
0:65766360f6b9 | 97 | 0 = Enable ASK for both receive and transmit */ |
| Sinan Divarci |
0:65766360f6b9 | 98 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 99 | } max7032_conf0_t; |
| Sinan Divarci |
0:65766360f6b9 | 100 | |
| Sinan Divarci |
0:65766360f6b9 | 101 | /** |
| Sinan Divarci |
0:65766360f6b9 | 102 | * @brief CONF1 Register |
| Sinan Divarci |
0:65766360f6b9 | 103 | * |
| Sinan Divarci |
0:65766360f6b9 | 104 | * Address : 0x03 |
| Sinan Divarci |
0:65766360f6b9 | 105 | */ |
| Sinan Divarci |
0:65766360f6b9 | 106 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 107 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 108 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 109 | unsigned char dt : 3; /**< AGC dwell timer AGC dwell timer */ |
| Sinan Divarci |
0:65766360f6b9 | 110 | unsigned char cdiv : 2; /**< Crystal divider CLKOUT crystal-divider */ |
| Sinan Divarci |
0:65766360f6b9 | 111 | unsigned char clkof : 1; /**< Continuous clock output 1 = Enable continuous clock output when CKOUT = 1 |
| Sinan Divarci |
0:65766360f6b9 | 112 | 0 = Continuous clock output */ |
| Sinan Divarci |
0:65766360f6b9 | 113 | unsigned char acal : 1; /**< Automatic FSK calibration 1 = Enable automatic FSK calibration |
| Sinan Divarci |
0:65766360f6b9 | 114 | 0 = Disable automatic FSK calibration*/ |
| Sinan Divarci |
0:65766360f6b9 | 115 | unsigned char x : 1; /**< None Not used*/ |
| Sinan Divarci |
0:65766360f6b9 | 116 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 117 | } max7032_conf1_t; |
| Sinan Divarci |
0:65766360f6b9 | 118 | |
| Sinan Divarci |
0:65766360f6b9 | 119 | /** |
| Sinan Divarci |
0:65766360f6b9 | 120 | * @brief OSC Register |
| Sinan Divarci |
0:65766360f6b9 | 121 | * |
| Sinan Divarci |
0:65766360f6b9 | 122 | * Address : 0x05 |
| Sinan Divarci |
0:65766360f6b9 | 123 | */ |
| Sinan Divarci |
0:65766360f6b9 | 124 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 125 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 126 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 127 | unsigned char osc; |
| Sinan Divarci |
0:65766360f6b9 | 128 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 129 | } max7032_osc_t; |
| Sinan Divarci |
0:65766360f6b9 | 130 | |
| Sinan Divarci |
0:65766360f6b9 | 131 | /** |
| Sinan Divarci |
0:65766360f6b9 | 132 | * @brief tOFF Register (Upper Byte) |
| Sinan Divarci |
0:65766360f6b9 | 133 | * |
| Sinan Divarci |
0:65766360f6b9 | 134 | * Address : 0x06 |
| Sinan Divarci |
0:65766360f6b9 | 135 | */ |
| Sinan Divarci |
0:65766360f6b9 | 136 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 137 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 138 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 139 | unsigned char toff_upper; |
| Sinan Divarci |
0:65766360f6b9 | 140 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 141 | } max7032_toff_upper_t; |
| Sinan Divarci |
0:65766360f6b9 | 142 | |
| Sinan Divarci |
0:65766360f6b9 | 143 | /** |
| Sinan Divarci |
0:65766360f6b9 | 144 | * @brief tOFF Register (Lower Byte) |
| Sinan Divarci |
0:65766360f6b9 | 145 | * |
| Sinan Divarci |
0:65766360f6b9 | 146 | * Address : 0x07 |
| Sinan Divarci |
0:65766360f6b9 | 147 | */ |
| Sinan Divarci |
0:65766360f6b9 | 148 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 149 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 150 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 151 | unsigned char toff_lower; |
| Sinan Divarci |
0:65766360f6b9 | 152 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 153 | } max7032_toff_lower_t; |
| Sinan Divarci |
0:65766360f6b9 | 154 | |
| Sinan Divarci |
0:65766360f6b9 | 155 | /** |
| Sinan Divarci |
0:65766360f6b9 | 156 | * @brief tCPU Register |
| Sinan Divarci |
0:65766360f6b9 | 157 | * |
| Sinan Divarci |
0:65766360f6b9 | 158 | * Address : 0x08 |
| Sinan Divarci |
0:65766360f6b9 | 159 | */ |
| Sinan Divarci |
0:65766360f6b9 | 160 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 161 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 162 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 163 | unsigned char tcpu; |
| Sinan Divarci |
0:65766360f6b9 | 164 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 165 | } max7032_tcpu_t; |
| Sinan Divarci |
0:65766360f6b9 | 166 | |
| Sinan Divarci |
0:65766360f6b9 | 167 | /** |
| Sinan Divarci |
0:65766360f6b9 | 168 | * @brief tRF Register (Upper Byte) |
| Sinan Divarci |
0:65766360f6b9 | 169 | * |
| Sinan Divarci |
0:65766360f6b9 | 170 | * Address : 0x09 |
| Sinan Divarci |
0:65766360f6b9 | 171 | */ |
| Sinan Divarci |
0:65766360f6b9 | 172 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 173 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 174 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 175 | unsigned char trf_upper; |
| Sinan Divarci |
0:65766360f6b9 | 176 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 177 | } max7032_trf_upper_t; |
| Sinan Divarci |
0:65766360f6b9 | 178 | |
| Sinan Divarci |
0:65766360f6b9 | 179 | /** |
| Sinan Divarci |
0:65766360f6b9 | 180 | * @brief tRF Register (Lower Byte) |
| Sinan Divarci |
0:65766360f6b9 | 181 | * |
| Sinan Divarci |
0:65766360f6b9 | 182 | * Address : 0x0A |
| Sinan Divarci |
0:65766360f6b9 | 183 | */ |
| Sinan Divarci |
0:65766360f6b9 | 184 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 185 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 186 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 187 | unsigned char trf_lower; |
| Sinan Divarci |
0:65766360f6b9 | 188 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 189 | } max7032_trf_lower_t; |
| Sinan Divarci |
0:65766360f6b9 | 190 | |
| Sinan Divarci |
0:65766360f6b9 | 191 | /** |
| Sinan Divarci |
0:65766360f6b9 | 192 | * @brief tON Register (Upper Byte) |
| Sinan Divarci |
0:65766360f6b9 | 193 | * |
| Sinan Divarci |
0:65766360f6b9 | 194 | * Address : 0x0B |
| Sinan Divarci |
0:65766360f6b9 | 195 | */ |
| Sinan Divarci |
0:65766360f6b9 | 196 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 197 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 198 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 199 | unsigned char ton_upper; |
| Sinan Divarci |
0:65766360f6b9 | 200 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 201 | } max7032_ton_upper_t; |
| Sinan Divarci |
0:65766360f6b9 | 202 | |
| Sinan Divarci |
0:65766360f6b9 | 203 | /** |
| Sinan Divarci |
0:65766360f6b9 | 204 | * @brief tON Register (Lower Byte) |
| Sinan Divarci |
0:65766360f6b9 | 205 | * |
| Sinan Divarci |
0:65766360f6b9 | 206 | * Address : 0x0C |
| Sinan Divarci |
0:65766360f6b9 | 207 | */ |
| Sinan Divarci |
0:65766360f6b9 | 208 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 209 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 210 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 211 | unsigned char ton_lower; |
| Sinan Divarci |
0:65766360f6b9 | 212 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 213 | } max7032_ton_lower_t; |
| Sinan Divarci |
0:65766360f6b9 | 214 | |
| Sinan Divarci |
0:65766360f6b9 | 215 | /** |
| Sinan Divarci |
0:65766360f6b9 | 216 | * @brief TxLOW Register (Upper Byte) |
| Sinan Divarci |
0:65766360f6b9 | 217 | * |
| Sinan Divarci |
0:65766360f6b9 | 218 | * Address : 0x0D |
| Sinan Divarci |
0:65766360f6b9 | 219 | */ |
| Sinan Divarci |
0:65766360f6b9 | 220 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 221 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 222 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 223 | unsigned char txlow_upper; |
| Sinan Divarci |
0:65766360f6b9 | 224 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 225 | } max7032_txlow_upper_t; |
| Sinan Divarci |
0:65766360f6b9 | 226 | |
| Sinan Divarci |
0:65766360f6b9 | 227 | /** |
| Sinan Divarci |
0:65766360f6b9 | 228 | * @brief TxLOW Register (Lower Byte) |
| Sinan Divarci |
0:65766360f6b9 | 229 | * |
| Sinan Divarci |
0:65766360f6b9 | 230 | * Address : 0x0E |
| Sinan Divarci |
0:65766360f6b9 | 231 | */ |
| Sinan Divarci |
0:65766360f6b9 | 232 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 233 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 234 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 235 | unsigned char txlow_lower; |
| Sinan Divarci |
0:65766360f6b9 | 236 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 237 | } max7032_txlow_lower_t; |
| Sinan Divarci |
0:65766360f6b9 | 238 | |
| Sinan Divarci |
0:65766360f6b9 | 239 | /** |
| Sinan Divarci |
0:65766360f6b9 | 240 | * @brief TxHIGH Register (Upper Byte) |
| Sinan Divarci |
0:65766360f6b9 | 241 | * |
| Sinan Divarci |
0:65766360f6b9 | 242 | * Address : 0x0F |
| Sinan Divarci |
0:65766360f6b9 | 243 | */ |
| Sinan Divarci |
0:65766360f6b9 | 244 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 245 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 246 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 247 | unsigned char txhigh_upper; |
| Sinan Divarci |
0:65766360f6b9 | 248 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 249 | } max7032_txhigh_upper_t; |
| Sinan Divarci |
0:65766360f6b9 | 250 | |
| Sinan Divarci |
0:65766360f6b9 | 251 | /** |
| Sinan Divarci |
0:65766360f6b9 | 252 | * @brief TxHIGH Register (Lower Byte) |
| Sinan Divarci |
0:65766360f6b9 | 253 | * |
| Sinan Divarci |
0:65766360f6b9 | 254 | * Address : 0x10 |
| Sinan Divarci |
0:65766360f6b9 | 255 | */ |
| Sinan Divarci |
0:65766360f6b9 | 256 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 257 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 258 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 259 | unsigned char txhigh_lower; |
| Sinan Divarci |
0:65766360f6b9 | 260 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 261 | } max7032_txhigh_lower_t; |
| Sinan Divarci |
0:65766360f6b9 | 262 | |
| Sinan Divarci |
0:65766360f6b9 | 263 | /** |
| Sinan Divarci |
0:65766360f6b9 | 264 | * @brief STATUS Register |
| Sinan Divarci |
0:65766360f6b9 | 265 | * |
| Sinan Divarci |
0:65766360f6b9 | 266 | * Address : 0x1A |
| Sinan Divarci |
0:65766360f6b9 | 267 | */ |
| Sinan Divarci |
0:65766360f6b9 | 268 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 269 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 270 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 271 | unsigned char fcald : 1; /**< FSK calibration done 1 = FSK calibration is completed |
| Sinan Divarci |
0:65766360f6b9 | 272 | 0 = FSK calibration is in progress or not completed*/ |
| Sinan Divarci |
0:65766360f6b9 | 273 | unsigned char pcald : 1; /**< Polling timer calibration done 1 = Polling timer calibration is completed |
| Sinan Divarci |
0:65766360f6b9 | 274 | 0 = Polling timer calibration is in progress or not completed*/ |
| Sinan Divarci |
0:65766360f6b9 | 275 | unsigned char x0 : 1; /**< None Zero*/ |
| Sinan Divarci |
0:65766360f6b9 | 276 | unsigned char x1 : 1; /**< None Zero*/ |
| Sinan Divarci |
0:65766360f6b9 | 277 | unsigned char x2 : 1; /**< None Zero*/ |
| Sinan Divarci |
0:65766360f6b9 | 278 | unsigned char clkon : 1; /**< Clock/crystal alive 1 = Valid clock at crystal inputs |
| Sinan Divarci |
0:65766360f6b9 | 279 | 0 = No valid clock signal seen at the crystal inputs*/ |
| Sinan Divarci |
0:65766360f6b9 | 280 | unsigned char gains : 1; /**< AGC gain state 1 = LNA in high-gain state |
| Sinan Divarci |
0:65766360f6b9 | 281 | 0 = LNA in low-gain state*/ |
| Sinan Divarci |
0:65766360f6b9 | 282 | unsigned char lckd : 1; /**< Lock detect 1 = Internal PLL is locked |
| Sinan Divarci |
0:65766360f6b9 | 283 | 0 = Internal PLL is not locked */ |
| Sinan Divarci |
0:65766360f6b9 | 284 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 285 | } max7032_status_t; |
| Sinan Divarci |
0:65766360f6b9 | 286 | |
| Sinan Divarci |
0:65766360f6b9 | 287 | /** |
| Sinan Divarci |
0:65766360f6b9 | 288 | * @brief DEMOD Register |
| Sinan Divarci |
0:65766360f6b9 | 289 | * |
| Sinan Divarci |
0:65766360f6b9 | 290 | * Address : 0x00 |
| Sinan Divarci |
0:65766360f6b9 | 291 | */ |
| Sinan Divarci |
0:65766360f6b9 | 292 | typedef union { |
| Sinan Divarci |
0:65766360f6b9 | 293 | unsigned char raw; |
| Sinan Divarci |
0:65766360f6b9 | 294 | struct { |
| Sinan Divarci |
0:65766360f6b9 | 295 | unsigned char dummy_byte; |
| Sinan Divarci |
0:65766360f6b9 | 296 | |
| Sinan Divarci |
0:65766360f6b9 | 297 | } bits; |
| Sinan Divarci |
0:65766360f6b9 | 298 | } max7032_dummy_t; |
| Sinan Divarci |
0:65766360f6b9 | 299 | |
| Sinan Divarci |
0:65766360f6b9 | 300 | /** |
| Sinan Divarci |
0:65766360f6b9 | 301 | * @brief Register Set |
| Sinan Divarci |
0:65766360f6b9 | 302 | * |
| Sinan Divarci |
0:65766360f6b9 | 303 | * |
| Sinan Divarci |
0:65766360f6b9 | 304 | */ |
| Sinan Divarci |
0:65766360f6b9 | 305 | typedef struct { |
| Sinan Divarci |
0:65766360f6b9 | 306 | max7032_power_t power; |
| Sinan Divarci |
0:65766360f6b9 | 307 | max7032_contrl_t contrl; |
| Sinan Divarci |
0:65766360f6b9 | 308 | max7032_conf0_t conf0; |
| Sinan Divarci |
0:65766360f6b9 | 309 | max7032_conf1_t conf1; |
| Sinan Divarci |
0:65766360f6b9 | 310 | max7032_osc_t osc; |
| Sinan Divarci |
0:65766360f6b9 | 311 | max7032_toff_upper_t toff_upper; |
| Sinan Divarci |
0:65766360f6b9 | 312 | max7032_toff_lower_t toff_lower; |
| Sinan Divarci |
0:65766360f6b9 | 313 | max7032_tcpu_t tcpu; |
| Sinan Divarci |
0:65766360f6b9 | 314 | max7032_trf_upper_t trf_upper; |
| Sinan Divarci |
0:65766360f6b9 | 315 | max7032_trf_lower_t trf_lower; |
| Sinan Divarci |
0:65766360f6b9 | 316 | max7032_ton_upper_t ton_upper; |
| Sinan Divarci |
0:65766360f6b9 | 317 | max7032_ton_lower_t ton_lower; |
| Sinan Divarci |
0:65766360f6b9 | 318 | max7032_txlow_upper_t txlow_upper; |
| Sinan Divarci |
0:65766360f6b9 | 319 | max7032_txlow_lower_t txlow_lower; |
| Sinan Divarci |
0:65766360f6b9 | 320 | max7032_txhigh_upper_t txhigh_upper; |
| Sinan Divarci |
0:65766360f6b9 | 321 | max7032_txhigh_lower_t txhigh_lower; |
| Sinan Divarci |
0:65766360f6b9 | 322 | max7032_status_t status; |
| Sinan Divarci |
0:65766360f6b9 | 323 | } max7032_reg_map_t; |
| Sinan Divarci |
0:65766360f6b9 | 324 | |
| Sinan Divarci |
0:65766360f6b9 | 325 | #endif /* MAX7032_REGS_H_ */ |