Interactive Device Design / Mbed 2 deprecated air_zuma

Control the wondrous spinning-frog game of Zuma's Revenge with a rotating chair and an Airzooka. Maps compass rotation, flex sensor and push button input to USB actions to control Zuma's Revenge (http://www.popcap.com/games/zumas-revenge/online)

Dependencies:   LSM303DLHC mbed

Note that content for USB HID and USB Device is actually from the USBDevice mbed library. However, we made a couple of small changes to this library (allowing USB clicks at a particular location) that required us to break it off from the main project if we wanted to publish without pushing upstream.

USBDevice/USBHAL_KL25Z.cpp@0:4df415dde990, 2014-09-29 (annotated)

Committer:
andrewhead
Date:
Mon Sep 29 01:12:20 2014 +0000
Revision:
0:4df415dde990
Initial Commit.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
andrewhead 0:4df415dde990 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
andrewhead 0:4df415dde990 2 *
andrewhead 0:4df415dde990 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
andrewhead 0:4df415dde990 4 * and associated documentation files (the "Software"), to deal in the Software without
andrewhead 0:4df415dde990 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
andrewhead 0:4df415dde990 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
andrewhead 0:4df415dde990 7 * Software is furnished to do so, subject to the following conditions:
andrewhead 0:4df415dde990 8 *
andrewhead 0:4df415dde990 9 * The above copyright notice and this permission notice shall be included in all copies or
andrewhead 0:4df415dde990 10 * substantial portions of the Software.
andrewhead 0:4df415dde990 11 *
andrewhead 0:4df415dde990 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
andrewhead 0:4df415dde990 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
andrewhead 0:4df415dde990 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
andrewhead 0:4df415dde990 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
andrewhead 0:4df415dde990 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
andrewhead 0:4df415dde990 17 */
andrewhead 0:4df415dde990 18
andrewhead 0:4df415dde990 19 #if defined(TARGET_KL25Z)
andrewhead 0:4df415dde990 20
andrewhead 0:4df415dde990 21 #include "USBHAL.h"
andrewhead 0:4df415dde990 22
andrewhead 0:4df415dde990 23 USBHAL * USBHAL::instance;
andrewhead 0:4df415dde990 24
andrewhead 0:4df415dde990 25 static volatile int epComplete = 0;
andrewhead 0:4df415dde990 26
andrewhead 0:4df415dde990 27 // Convert physical endpoint number to register bit
andrewhead 0:4df415dde990 28 #define EP(endpoint) (1<<(endpoint))
andrewhead 0:4df415dde990 29
andrewhead 0:4df415dde990 30 // Convert physical to logical
andrewhead 0:4df415dde990 31 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
andrewhead 0:4df415dde990 32
andrewhead 0:4df415dde990 33 // Get endpoint direction
andrewhead 0:4df415dde990 34 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
andrewhead 0:4df415dde990 35 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
andrewhead 0:4df415dde990 36
andrewhead 0:4df415dde990 37 #define BD_OWN_MASK (1<<7)
andrewhead 0:4df415dde990 38 #define BD_DATA01_MASK (1<<6)
andrewhead 0:4df415dde990 39 #define BD_KEEP_MASK (1<<5)
andrewhead 0:4df415dde990 40 #define BD_NINC_MASK (1<<4)
andrewhead 0:4df415dde990 41 #define BD_DTS_MASK (1<<3)
andrewhead 0:4df415dde990 42 #define BD_STALL_MASK (1<<2)
andrewhead 0:4df415dde990 43
andrewhead 0:4df415dde990 44 #define TX 1
andrewhead 0:4df415dde990 45 #define RX 0
andrewhead 0:4df415dde990 46 #define ODD 0
andrewhead 0:4df415dde990 47 #define EVEN 1
andrewhead 0:4df415dde990 48 // this macro waits a physical endpoint number
andrewhead 0:4df415dde990 49 #define EP_BDT_IDX(ep, dir, odd) (((ep * 4) + (2 * dir) + (1 * odd)))
andrewhead 0:4df415dde990 50
andrewhead 0:4df415dde990 51 #define SETUP_TOKEN 0x0D
andrewhead 0:4df415dde990 52 #define IN_TOKEN 0x09
andrewhead 0:4df415dde990 53 #define OUT_TOKEN 0x01
andrewhead 0:4df415dde990 54 #define TOK_PID(idx) ((bdt[idx].info >> 2) & 0x0F)
andrewhead 0:4df415dde990 55
andrewhead 0:4df415dde990 56 // for each endpt: 8 bytes
andrewhead 0:4df415dde990 57 typedef struct BDT {
andrewhead 0:4df415dde990 58 uint8_t info; // BD[0:7]
andrewhead 0:4df415dde990 59 uint8_t dummy; // RSVD: BD[8:15]
andrewhead 0:4df415dde990 60 uint16_t byte_count; // BD[16:32]
andrewhead 0:4df415dde990 61 uint32_t address; // Addr
andrewhead 0:4df415dde990 62 } BDT;
andrewhead 0:4df415dde990 63
andrewhead 0:4df415dde990 64
andrewhead 0:4df415dde990 65 // there are:
andrewhead 0:4df415dde990 66 // * 16 bidirectionnal endpt -> 32 physical endpt
andrewhead 0:4df415dde990 67 // * as there are ODD and EVEN buffer -> 32*2 bdt
andrewhead 0:4df415dde990 68 __attribute__((__aligned__(512))) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
andrewhead 0:4df415dde990 69 uint8_t endpoint_buffer[(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2][64];
andrewhead 0:4df415dde990 70 uint8_t endpoint_buffer_iso[2*2][1023];
andrewhead 0:4df415dde990 71
andrewhead 0:4df415dde990 72 static uint8_t set_addr = 0;
andrewhead 0:4df415dde990 73 static uint8_t addr = 0;
andrewhead 0:4df415dde990 74
andrewhead 0:4df415dde990 75 static uint32_t Data1 = 0x55555555;
andrewhead 0:4df415dde990 76
andrewhead 0:4df415dde990 77 static uint32_t frameNumber() {
andrewhead 0:4df415dde990 78 return((USB0->FRMNUML | (USB0->FRMNUMH << 8) & 0x07FF));
andrewhead 0:4df415dde990 79 }
andrewhead 0:4df415dde990 80
andrewhead 0:4df415dde990 81 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
andrewhead 0:4df415dde990 82 return 0;
andrewhead 0:4df415dde990 83 }
andrewhead 0:4df415dde990 84
andrewhead 0:4df415dde990 85 USBHAL::USBHAL(void) {
andrewhead 0:4df415dde990 86 // Disable IRQ
andrewhead 0:4df415dde990 87 NVIC_DisableIRQ(USB0_IRQn);
andrewhead 0:4df415dde990 88
andrewhead 0:4df415dde990 89 // fill in callback array
andrewhead 0:4df415dde990 90 epCallback[0] = &USBHAL::EP1_OUT_callback;
andrewhead 0:4df415dde990 91 epCallback[1] = &USBHAL::EP1_IN_callback;
andrewhead 0:4df415dde990 92 epCallback[2] = &USBHAL::EP2_OUT_callback;
andrewhead 0:4df415dde990 93 epCallback[3] = &USBHAL::EP2_IN_callback;
andrewhead 0:4df415dde990 94 epCallback[4] = &USBHAL::EP3_OUT_callback;
andrewhead 0:4df415dde990 95 epCallback[5] = &USBHAL::EP3_IN_callback;
andrewhead 0:4df415dde990 96 epCallback[6] = &USBHAL::EP4_OUT_callback;
andrewhead 0:4df415dde990 97 epCallback[7] = &USBHAL::EP4_IN_callback;
andrewhead 0:4df415dde990 98 epCallback[8] = &USBHAL::EP5_OUT_callback;
andrewhead 0:4df415dde990 99 epCallback[9] = &USBHAL::EP5_IN_callback;
andrewhead 0:4df415dde990 100 epCallback[10] = &USBHAL::EP6_OUT_callback;
andrewhead 0:4df415dde990 101 epCallback[11] = &USBHAL::EP6_IN_callback;
andrewhead 0:4df415dde990 102 epCallback[12] = &USBHAL::EP7_OUT_callback;
andrewhead 0:4df415dde990 103 epCallback[13] = &USBHAL::EP7_IN_callback;
andrewhead 0:4df415dde990 104 epCallback[14] = &USBHAL::EP8_OUT_callback;
andrewhead 0:4df415dde990 105 epCallback[15] = &USBHAL::EP8_IN_callback;
andrewhead 0:4df415dde990 106 epCallback[16] = &USBHAL::EP9_OUT_callback;
andrewhead 0:4df415dde990 107 epCallback[17] = &USBHAL::EP9_IN_callback;
andrewhead 0:4df415dde990 108 epCallback[18] = &USBHAL::EP10_OUT_callback;
andrewhead 0:4df415dde990 109 epCallback[19] = &USBHAL::EP10_IN_callback;
andrewhead 0:4df415dde990 110 epCallback[20] = &USBHAL::EP11_OUT_callback;
andrewhead 0:4df415dde990 111 epCallback[21] = &USBHAL::EP11_IN_callback;
andrewhead 0:4df415dde990 112 epCallback[22] = &USBHAL::EP12_OUT_callback;
andrewhead 0:4df415dde990 113 epCallback[23] = &USBHAL::EP12_IN_callback;
andrewhead 0:4df415dde990 114 epCallback[24] = &USBHAL::EP13_OUT_callback;
andrewhead 0:4df415dde990 115 epCallback[25] = &USBHAL::EP13_IN_callback;
andrewhead 0:4df415dde990 116 epCallback[26] = &USBHAL::EP14_OUT_callback;
andrewhead 0:4df415dde990 117 epCallback[27] = &USBHAL::EP14_IN_callback;
andrewhead 0:4df415dde990 118 epCallback[28] = &USBHAL::EP15_OUT_callback;
andrewhead 0:4df415dde990 119 epCallback[29] = &USBHAL::EP15_IN_callback;
andrewhead 0:4df415dde990 120
andrewhead 0:4df415dde990 121
andrewhead 0:4df415dde990 122 // choose usb src as PLL
andrewhead 0:4df415dde990 123 SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
andrewhead 0:4df415dde990 124
andrewhead 0:4df415dde990 125 // enable OTG clock
andrewhead 0:4df415dde990 126 SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
andrewhead 0:4df415dde990 127
andrewhead 0:4df415dde990 128 // Attach IRQ
andrewhead 0:4df415dde990 129 instance = this;
andrewhead 0:4df415dde990 130 NVIC_SetVector(USB0_IRQn, (uint32_t)&_usbisr);
andrewhead 0:4df415dde990 131 NVIC_EnableIRQ(USB0_IRQn);
andrewhead 0:4df415dde990 132
andrewhead 0:4df415dde990 133 // USB Module Configuration
andrewhead 0:4df415dde990 134 // Reset USB Module
andrewhead 0:4df415dde990 135 USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
andrewhead 0:4df415dde990 136 while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
andrewhead 0:4df415dde990 137
andrewhead 0:4df415dde990 138 // Set BDT Base Register
andrewhead 0:4df415dde990 139 USB0->BDTPAGE1=(uint8_t)((uint32_t)bdt>>8);
andrewhead 0:4df415dde990 140 USB0->BDTPAGE2=(uint8_t)((uint32_t)bdt>>16);
andrewhead 0:4df415dde990 141 USB0->BDTPAGE3=(uint8_t)((uint32_t)bdt>>24);
andrewhead 0:4df415dde990 142
andrewhead 0:4df415dde990 143 // Clear interrupt flag
andrewhead 0:4df415dde990 144 USB0->ISTAT = 0xff;
andrewhead 0:4df415dde990 145
andrewhead 0:4df415dde990 146 // USB Interrupt Enablers
andrewhead 0:4df415dde990 147 USB0->INTEN |= USB_INTEN_TOKDNEEN_MASK |
andrewhead 0:4df415dde990 148 USB_INTEN_SOFTOKEN_MASK |
andrewhead 0:4df415dde990 149 USB_INTEN_ERROREN_MASK |
andrewhead 0:4df415dde990 150 USB_INTEN_USBRSTEN_MASK;
andrewhead 0:4df415dde990 151
andrewhead 0:4df415dde990 152 // Disable weak pull downs
andrewhead 0:4df415dde990 153 USB0->USBCTRL &= ~(USB_USBCTRL_PDE_MASK | USB_USBCTRL_SUSP_MASK);
andrewhead 0:4df415dde990 154
andrewhead 0:4df415dde990 155 USB0->USBTRC0 |= 0x40;
andrewhead 0:4df415dde990 156 }
andrewhead 0:4df415dde990 157
andrewhead 0:4df415dde990 158 USBHAL::~USBHAL(void) { }
andrewhead 0:4df415dde990 159
andrewhead 0:4df415dde990 160 void USBHAL::connect(void) {
andrewhead 0:4df415dde990 161 // enable USB
andrewhead 0:4df415dde990 162 USB0->CTL |= USB_CTL_USBENSOFEN_MASK;
andrewhead 0:4df415dde990 163 // Pull up enable
andrewhead 0:4df415dde990 164 USB0->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
andrewhead 0:4df415dde990 165 }
andrewhead 0:4df415dde990 166
andrewhead 0:4df415dde990 167 void USBHAL::disconnect(void) {
andrewhead 0:4df415dde990 168 // disable USB
andrewhead 0:4df415dde990 169 USB0->CTL &= ~USB_CTL_USBENSOFEN_MASK;
andrewhead 0:4df415dde990 170 // Pull up disable
andrewhead 0:4df415dde990 171 USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
andrewhead 0:4df415dde990 172 }
andrewhead 0:4df415dde990 173
andrewhead 0:4df415dde990 174 void USBHAL::configureDevice(void) {
andrewhead 0:4df415dde990 175 // not needed
andrewhead 0:4df415dde990 176 }
andrewhead 0:4df415dde990 177
andrewhead 0:4df415dde990 178 void USBHAL::unconfigureDevice(void) {
andrewhead 0:4df415dde990 179 // not needed
andrewhead 0:4df415dde990 180 }
andrewhead 0:4df415dde990 181
andrewhead 0:4df415dde990 182 void USBHAL::setAddress(uint8_t address) {
andrewhead 0:4df415dde990 183 // we don't set the address now otherwise the usb controller does not ack
andrewhead 0:4df415dde990 184 // we set a flag instead
andrewhead 0:4df415dde990 185 // see usbisr when an IN token is received
andrewhead 0:4df415dde990 186 set_addr = 1;
andrewhead 0:4df415dde990 187 addr = address;
andrewhead 0:4df415dde990 188 }
andrewhead 0:4df415dde990 189
andrewhead 0:4df415dde990 190 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
andrewhead 0:4df415dde990 191 uint32_t handshake_flag = 0;
andrewhead 0:4df415dde990 192 uint8_t * buf;
andrewhead 0:4df415dde990 193
andrewhead 0:4df415dde990 194 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
andrewhead 0:4df415dde990 195 return false;
andrewhead 0:4df415dde990 196 }
andrewhead 0:4df415dde990 197
andrewhead 0:4df415dde990 198 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
andrewhead 0:4df415dde990 199
andrewhead 0:4df415dde990 200 if ((flags & ISOCHRONOUS) == 0) {
andrewhead 0:4df415dde990 201 handshake_flag = USB_ENDPT_EPHSHK_MASK;
andrewhead 0:4df415dde990 202 if (IN_EP(endpoint))
andrewhead 0:4df415dde990 203 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD )][0];
andrewhead 0:4df415dde990 204 else
andrewhead 0:4df415dde990 205 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD )][0];
andrewhead 0:4df415dde990 206 } else {
andrewhead 0:4df415dde990 207 if (IN_EP(endpoint))
andrewhead 0:4df415dde990 208 buf = &endpoint_buffer_iso[2][0];
andrewhead 0:4df415dde990 209 else
andrewhead 0:4df415dde990 210 buf = &endpoint_buffer_iso[0][0];
andrewhead 0:4df415dde990 211 }
andrewhead 0:4df415dde990 212
andrewhead 0:4df415dde990 213 // IN endpt -> device to host (TX)
andrewhead 0:4df415dde990 214 if (IN_EP(endpoint)) {
andrewhead 0:4df415dde990 215 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
andrewhead 0:4df415dde990 216 USB_ENDPT_EPTXEN_MASK; // en TX (IN) tran
andrewhead 0:4df415dde990 217 bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].address = (uint32_t) buf;
andrewhead 0:4df415dde990 218 bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].address = 0;
andrewhead 0:4df415dde990 219 }
andrewhead 0:4df415dde990 220 // OUT endpt -> host to device (RX)
andrewhead 0:4df415dde990 221 else {
andrewhead 0:4df415dde990 222 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
andrewhead 0:4df415dde990 223 USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran.
andrewhead 0:4df415dde990 224 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = maxPacket;
andrewhead 0:4df415dde990 225 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf;
andrewhead 0:4df415dde990 226 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_OWN_MASK | BD_DTS_MASK;
andrewhead 0:4df415dde990 227 bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0;
andrewhead 0:4df415dde990 228 }
andrewhead 0:4df415dde990 229
andrewhead 0:4df415dde990 230 Data1 |= (1 << endpoint);
andrewhead 0:4df415dde990 231
andrewhead 0:4df415dde990 232 return true;
andrewhead 0:4df415dde990 233 }
andrewhead 0:4df415dde990 234
andrewhead 0:4df415dde990 235 // read setup packet
andrewhead 0:4df415dde990 236 void USBHAL::EP0setup(uint8_t *buffer) {
andrewhead 0:4df415dde990 237 uint32_t sz;
andrewhead 0:4df415dde990 238 endpointReadResult(EP0OUT, buffer, &sz);
andrewhead 0:4df415dde990 239 }
andrewhead 0:4df415dde990 240
andrewhead 0:4df415dde990 241 void USBHAL::EP0readStage(void) {
andrewhead 0:4df415dde990 242 Data1 &= ~1UL; // set DATA0
andrewhead 0:4df415dde990 243 bdt[0].info = (BD_DTS_MASK | BD_OWN_MASK);
andrewhead 0:4df415dde990 244 }
andrewhead 0:4df415dde990 245
andrewhead 0:4df415dde990 246 void USBHAL::EP0read(void) {
andrewhead 0:4df415dde990 247 uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0);
andrewhead 0:4df415dde990 248 bdt[idx].byte_count = MAX_PACKET_SIZE_EP0;
andrewhead 0:4df415dde990 249 }
andrewhead 0:4df415dde990 250
andrewhead 0:4df415dde990 251 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
andrewhead 0:4df415dde990 252 uint32_t sz;
andrewhead 0:4df415dde990 253 endpointReadResult(EP0OUT, buffer, &sz);
andrewhead 0:4df415dde990 254 return sz;
andrewhead 0:4df415dde990 255 }
andrewhead 0:4df415dde990 256
andrewhead 0:4df415dde990 257 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
andrewhead 0:4df415dde990 258 endpointWrite(EP0IN, buffer, size);
andrewhead 0:4df415dde990 259 }
andrewhead 0:4df415dde990 260
andrewhead 0:4df415dde990 261 void USBHAL::EP0getWriteResult(void) {
andrewhead 0:4df415dde990 262 }
andrewhead 0:4df415dde990 263
andrewhead 0:4df415dde990 264 void USBHAL::EP0stall(void) {
andrewhead 0:4df415dde990 265 stallEndpoint(EP0OUT);
andrewhead 0:4df415dde990 266 }
andrewhead 0:4df415dde990 267
andrewhead 0:4df415dde990 268 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
andrewhead 0:4df415dde990 269 endpoint = PHY_TO_LOG(endpoint);
andrewhead 0:4df415dde990 270 uint32_t idx = EP_BDT_IDX(endpoint, RX, 0);
andrewhead 0:4df415dde990 271 bdt[idx].byte_count = maximumSize;
andrewhead 0:4df415dde990 272 return EP_PENDING;
andrewhead 0:4df415dde990 273 }
andrewhead 0:4df415dde990 274
andrewhead 0:4df415dde990 275 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
andrewhead 0:4df415dde990 276 uint32_t n, sz, idx, setup = 0;
andrewhead 0:4df415dde990 277 uint8_t not_iso;
andrewhead 0:4df415dde990 278 uint8_t * ep_buf;
andrewhead 0:4df415dde990 279
andrewhead 0:4df415dde990 280 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
andrewhead 0:4df415dde990 281
andrewhead 0:4df415dde990 282 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
andrewhead 0:4df415dde990 283 return EP_INVALID;
andrewhead 0:4df415dde990 284 }
andrewhead 0:4df415dde990 285
andrewhead 0:4df415dde990 286 // if read on a IN endpoint -> error
andrewhead 0:4df415dde990 287 if (IN_EP(endpoint)) {
andrewhead 0:4df415dde990 288 return EP_INVALID;
andrewhead 0:4df415dde990 289 }
andrewhead 0:4df415dde990 290
andrewhead 0:4df415dde990 291 idx = EP_BDT_IDX(log_endpoint, RX, 0);
andrewhead 0:4df415dde990 292 sz = bdt[idx].byte_count;
andrewhead 0:4df415dde990 293 not_iso = USB0->ENDPOINT[log_endpoint].ENDPT & USB_ENDPT_EPHSHK_MASK;
andrewhead 0:4df415dde990 294
andrewhead 0:4df415dde990 295 //for isochronous endpoint, we don't wait an interrupt
andrewhead 0:4df415dde990 296 if ((log_endpoint != 0) && not_iso && !(epComplete & EP(endpoint))) {
andrewhead 0:4df415dde990 297 return EP_PENDING;
andrewhead 0:4df415dde990 298 }
andrewhead 0:4df415dde990 299
andrewhead 0:4df415dde990 300 if ((log_endpoint == 0) && (TOK_PID(idx) == SETUP_TOKEN)) {
andrewhead 0:4df415dde990 301 setup = 1;
andrewhead 0:4df415dde990 302 }
andrewhead 0:4df415dde990 303
andrewhead 0:4df415dde990 304 // non iso endpoint
andrewhead 0:4df415dde990 305 if (not_iso) {
andrewhead 0:4df415dde990 306 ep_buf = endpoint_buffer[idx];
andrewhead 0:4df415dde990 307 } else {
andrewhead 0:4df415dde990 308 ep_buf = endpoint_buffer_iso[0];
andrewhead 0:4df415dde990 309 }
andrewhead 0:4df415dde990 310
andrewhead 0:4df415dde990 311 for (n = 0; n < sz; n++) {
andrewhead 0:4df415dde990 312 buffer[n] = ep_buf[n];
andrewhead 0:4df415dde990 313 }
andrewhead 0:4df415dde990 314
andrewhead 0:4df415dde990 315 if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) {
andrewhead 0:4df415dde990 316 if (setup && (buffer[6] == 0)) // if no setup data stage,
andrewhead 0:4df415dde990 317 Data1 &= ~1UL; // set DATA0
andrewhead 0:4df415dde990 318 else
andrewhead 0:4df415dde990 319 Data1 ^= (1 << endpoint);
andrewhead 0:4df415dde990 320 }
andrewhead 0:4df415dde990 321
andrewhead 0:4df415dde990 322 if (((Data1 >> endpoint) & 1)) {
andrewhead 0:4df415dde990 323 bdt[idx].info = BD_DTS_MASK | BD_DATA01_MASK | BD_OWN_MASK;
andrewhead 0:4df415dde990 324 }
andrewhead 0:4df415dde990 325 else {
andrewhead 0:4df415dde990 326 bdt[idx].info = BD_DTS_MASK | BD_OWN_MASK;
andrewhead 0:4df415dde990 327 }
andrewhead 0:4df415dde990 328
andrewhead 0:4df415dde990 329 USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
andrewhead 0:4df415dde990 330 *bytesRead = sz;
andrewhead 0:4df415dde990 331
andrewhead 0:4df415dde990 332 epComplete &= ~EP(endpoint);
andrewhead 0:4df415dde990 333 return EP_COMPLETED;
andrewhead 0:4df415dde990 334 }
andrewhead 0:4df415dde990 335
andrewhead 0:4df415dde990 336 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
andrewhead 0:4df415dde990 337 uint32_t idx, n;
andrewhead 0:4df415dde990 338 uint8_t * ep_buf;
andrewhead 0:4df415dde990 339
andrewhead 0:4df415dde990 340 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
andrewhead 0:4df415dde990 341 return EP_INVALID;
andrewhead 0:4df415dde990 342 }
andrewhead 0:4df415dde990 343
andrewhead 0:4df415dde990 344 // if write on a OUT endpoint -> error
andrewhead 0:4df415dde990 345 if (OUT_EP(endpoint)) {
andrewhead 0:4df415dde990 346 return EP_INVALID;
andrewhead 0:4df415dde990 347 }
andrewhead 0:4df415dde990 348
andrewhead 0:4df415dde990 349 idx = EP_BDT_IDX(PHY_TO_LOG(endpoint), TX, 0);
andrewhead 0:4df415dde990 350 bdt[idx].byte_count = size;
andrewhead 0:4df415dde990 351
andrewhead 0:4df415dde990 352
andrewhead 0:4df415dde990 353 // non iso endpoint
andrewhead 0:4df415dde990 354 if (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPHSHK_MASK) {
andrewhead 0:4df415dde990 355 ep_buf = endpoint_buffer[idx];
andrewhead 0:4df415dde990 356 } else {
andrewhead 0:4df415dde990 357 ep_buf = endpoint_buffer_iso[2];
andrewhead 0:4df415dde990 358 }
andrewhead 0:4df415dde990 359
andrewhead 0:4df415dde990 360 for (n = 0; n < size; n++) {
andrewhead 0:4df415dde990 361 ep_buf[n] = data[n];
andrewhead 0:4df415dde990 362 }
andrewhead 0:4df415dde990 363
andrewhead 0:4df415dde990 364 if ((Data1 >> endpoint) & 1) {
andrewhead 0:4df415dde990 365 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK;
andrewhead 0:4df415dde990 366 } else {
andrewhead 0:4df415dde990 367 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
andrewhead 0:4df415dde990 368 }
andrewhead 0:4df415dde990 369
andrewhead 0:4df415dde990 370 Data1 ^= (1 << endpoint);
andrewhead 0:4df415dde990 371
andrewhead 0:4df415dde990 372 return EP_PENDING;
andrewhead 0:4df415dde990 373 }
andrewhead 0:4df415dde990 374
andrewhead 0:4df415dde990 375 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
andrewhead 0:4df415dde990 376 if (epComplete & EP(endpoint)) {
andrewhead 0:4df415dde990 377 epComplete &= ~EP(endpoint);
andrewhead 0:4df415dde990 378 return EP_COMPLETED;
andrewhead 0:4df415dde990 379 }
andrewhead 0:4df415dde990 380
andrewhead 0:4df415dde990 381 return EP_PENDING;
andrewhead 0:4df415dde990 382 }
andrewhead 0:4df415dde990 383
andrewhead 0:4df415dde990 384 void USBHAL::stallEndpoint(uint8_t endpoint) {
andrewhead 0:4df415dde990 385 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT |= USB_ENDPT_EPSTALL_MASK;
andrewhead 0:4df415dde990 386 }
andrewhead 0:4df415dde990 387
andrewhead 0:4df415dde990 388 void USBHAL::unstallEndpoint(uint8_t endpoint) {
andrewhead 0:4df415dde990 389 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
andrewhead 0:4df415dde990 390 }
andrewhead 0:4df415dde990 391
andrewhead 0:4df415dde990 392 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
andrewhead 0:4df415dde990 393 uint8_t stall = (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPSTALL_MASK);
andrewhead 0:4df415dde990 394 return (stall) ? true : false;
andrewhead 0:4df415dde990 395 }
andrewhead 0:4df415dde990 396
andrewhead 0:4df415dde990 397 void USBHAL::remoteWakeup(void) {
andrewhead 0:4df415dde990 398 // [TODO]
andrewhead 0:4df415dde990 399 }
andrewhead 0:4df415dde990 400
andrewhead 0:4df415dde990 401
andrewhead 0:4df415dde990 402 void USBHAL::_usbisr(void) {
andrewhead 0:4df415dde990 403 instance->usbisr();
andrewhead 0:4df415dde990 404 }
andrewhead 0:4df415dde990 405
andrewhead 0:4df415dde990 406
andrewhead 0:4df415dde990 407 void USBHAL::usbisr(void) {
andrewhead 0:4df415dde990 408 uint8_t i;
andrewhead 0:4df415dde990 409 uint8_t istat = USB0->ISTAT;
andrewhead 0:4df415dde990 410
andrewhead 0:4df415dde990 411 // reset interrupt
andrewhead 0:4df415dde990 412 if (istat & USB_ISTAT_USBRST_MASK) {
andrewhead 0:4df415dde990 413 // disable all endpt
andrewhead 0:4df415dde990 414 for(i = 0; i < 16; i++) {
andrewhead 0:4df415dde990 415 USB0->ENDPOINT[i].ENDPT = 0x00;
andrewhead 0:4df415dde990 416 }
andrewhead 0:4df415dde990 417
andrewhead 0:4df415dde990 418 // enable control endpoint
andrewhead 0:4df415dde990 419 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
andrewhead 0:4df415dde990 420 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
andrewhead 0:4df415dde990 421
andrewhead 0:4df415dde990 422 Data1 = 0x55555555;
andrewhead 0:4df415dde990 423 USB0->CTL |= USB_CTL_ODDRST_MASK;
andrewhead 0:4df415dde990 424
andrewhead 0:4df415dde990 425 USB0->ISTAT = 0xFF; // clear all interrupt status flags
andrewhead 0:4df415dde990 426 USB0->ERRSTAT = 0xFF; // clear all error flags
andrewhead 0:4df415dde990 427 USB0->ERREN = 0xFF; // enable error interrupt sources
andrewhead 0:4df415dde990 428 USB0->ADDR = 0x00; // set default address
andrewhead 0:4df415dde990 429
andrewhead 0:4df415dde990 430 return;
andrewhead 0:4df415dde990 431 }
andrewhead 0:4df415dde990 432
andrewhead 0:4df415dde990 433 // resume interrupt
andrewhead 0:4df415dde990 434 if (istat & USB_ISTAT_RESUME_MASK) {
andrewhead 0:4df415dde990 435 USB0->ISTAT = USB_ISTAT_RESUME_MASK;
andrewhead 0:4df415dde990 436 }
andrewhead 0:4df415dde990 437
andrewhead 0:4df415dde990 438 // SOF interrupt
andrewhead 0:4df415dde990 439 if (istat & USB_ISTAT_SOFTOK_MASK) {
andrewhead 0:4df415dde990 440 USB0->ISTAT = USB_ISTAT_SOFTOK_MASK;
andrewhead 0:4df415dde990 441 // SOF event, read frame number
andrewhead 0:4df415dde990 442 SOF(frameNumber());
andrewhead 0:4df415dde990 443 }
andrewhead 0:4df415dde990 444
andrewhead 0:4df415dde990 445 // stall interrupt
andrewhead 0:4df415dde990 446 if (istat & 1<<7) {
andrewhead 0:4df415dde990 447 if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK)
andrewhead 0:4df415dde990 448 USB0->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
andrewhead 0:4df415dde990 449 USB0->ISTAT |= USB_ISTAT_STALL_MASK;
andrewhead 0:4df415dde990 450 }
andrewhead 0:4df415dde990 451
andrewhead 0:4df415dde990 452 // token interrupt
andrewhead 0:4df415dde990 453 if (istat & 1<<3) {
andrewhead 0:4df415dde990 454 uint32_t num = (USB0->STAT >> 4) & 0x0F;
andrewhead 0:4df415dde990 455 uint32_t dir = (USB0->STAT >> 3) & 0x01;
andrewhead 0:4df415dde990 456 uint32_t ev_odd = (USB0->STAT >> 2) & 0x01;
andrewhead 0:4df415dde990 457
andrewhead 0:4df415dde990 458 // setup packet
andrewhead 0:4df415dde990 459 if ((num == 0) && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == SETUP_TOKEN)) {
andrewhead 0:4df415dde990 460 Data1 &= ~0x02;
andrewhead 0:4df415dde990 461 bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK;
andrewhead 0:4df415dde990 462 bdt[EP_BDT_IDX(0, TX, ODD)].info &= ~BD_OWN_MASK;
andrewhead 0:4df415dde990 463
andrewhead 0:4df415dde990 464 // EP0 SETUP event (SETUP data received)
andrewhead 0:4df415dde990 465 EP0setupCallback();
andrewhead 0:4df415dde990 466
andrewhead 0:4df415dde990 467 } else {
andrewhead 0:4df415dde990 468 // OUT packet
andrewhead 0:4df415dde990 469 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == OUT_TOKEN) {
andrewhead 0:4df415dde990 470 if (num == 0)
andrewhead 0:4df415dde990 471 EP0out();
andrewhead 0:4df415dde990 472 else {
andrewhead 0:4df415dde990 473 epComplete |= (1 << EP(num));
andrewhead 0:4df415dde990 474 if ((instance->*(epCallback[EP(num) - 2]))()) {
andrewhead 0:4df415dde990 475 epComplete &= ~(1 << EP(num));
andrewhead 0:4df415dde990 476 }
andrewhead 0:4df415dde990 477 }
andrewhead 0:4df415dde990 478 }
andrewhead 0:4df415dde990 479
andrewhead 0:4df415dde990 480 // IN packet
andrewhead 0:4df415dde990 481 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == IN_TOKEN) {
andrewhead 0:4df415dde990 482 if (num == 0) {
andrewhead 0:4df415dde990 483 EP0in();
andrewhead 0:4df415dde990 484 if (set_addr == 1) {
andrewhead 0:4df415dde990 485 USB0->ADDR = addr & 0x7F;
andrewhead 0:4df415dde990 486 set_addr = 0;
andrewhead 0:4df415dde990 487 }
andrewhead 0:4df415dde990 488 }
andrewhead 0:4df415dde990 489 else {
andrewhead 0:4df415dde990 490 epComplete |= (1 << (EP(num) + 1));
andrewhead 0:4df415dde990 491 if ((instance->*(epCallback[EP(num) + 1 - 2]))()) {
andrewhead 0:4df415dde990 492 epComplete &= ~(1 << (EP(num) + 1));
andrewhead 0:4df415dde990 493 }
andrewhead 0:4df415dde990 494 }
andrewhead 0:4df415dde990 495 }
andrewhead 0:4df415dde990 496 }
andrewhead 0:4df415dde990 497
andrewhead 0:4df415dde990 498 USB0->ISTAT = USB_ISTAT_TOKDNE_MASK;
andrewhead 0:4df415dde990 499 }
andrewhead 0:4df415dde990 500
andrewhead 0:4df415dde990 501 // sleep interrupt
andrewhead 0:4df415dde990 502 if (istat & 1<<4) {
andrewhead 0:4df415dde990 503 USB0->ISTAT |= USB_ISTAT_SLEEP_MASK;
andrewhead 0:4df415dde990 504 }
andrewhead 0:4df415dde990 505
andrewhead 0:4df415dde990 506 // error interrupt
andrewhead 0:4df415dde990 507 if (istat & USB_ISTAT_ERROR_MASK) {
andrewhead 0:4df415dde990 508 USB0->ERRSTAT = 0xFF;
andrewhead 0:4df415dde990 509 USB0->ISTAT |= USB_ISTAT_ERROR_MASK;
andrewhead 0:4df415dde990 510 }
andrewhead 0:4df415dde990 511 }
andrewhead 0:4df415dde990 512
andrewhead 0:4df415dde990 513
andrewhead 0:4df415dde990 514 #endif