I have two questions about the SystemInit() function on the mbed 1768 device:

• Why is only PLL0 used? Is there a reason that PLL1 couldn't have been used to provide the 48 MHz clock for the USB subsystem and then PLL0 used to run the CPU at a full 100 MHz instead of 96 MHz?
• Why are the FLASHTIM bits in the Flash Accelerator Configuration Register set to 4'b0011 for 4 CPU clocks. The LPC17xx User Manual indicate that this should only be used for CPU clock rates up to 80 MHz? Seems like it should be set to 4'b0100 for 5 CPU clocks. I see that the CMSIS drivers from NXP also set it to 4'b0011 when setting the CPU clock rate at 100 MHz so maybe the user manual is incorrect.

Thanks so much for the help,

Adam

Hi Adam, they are both good questions. The short answer is that the current system configuration has been "inherited" from an early NXP recommendation and that this legacy configuration seems to support quite well the existing mbed codebase.

In the latest reference configuration USB is clocked from PLL1, the CPU clock is 100MHz and the Flash Access Time is 5 CPU clocks.

Until now, avoiding the risk of breaking user code that may rely on the old system configuration prevailed over the advantages that the new configuration would bring.

Personally, I would favour the new configuration. When we will have a slightly improved test coverage we will update it.

Cheers, Emilio

Emilio, thanks for the response. I appreciate it.

I was thinking of changing these parameters in a one-off project but I thought it first wise to find out why the mbed SDK configured it as it did :) Definitely appears to be worth me trying to make the changes to see what happens.

-Adam