Symptom: using a high SPI output rate such at 2 MHz at 5 bits per byte (that is, 5 bits per SPI 'byte'), the SPI output is not completely continuous. Gaps occur between strings of 5-bit bytes.
Bug: the transmit IRQ handlers in
- file stm32f3xx_hal_spi.c
- funtion SPI_TxISR_8BIT(), SPI_TxISR_16BIT(), amongst others,
all DO NOT check the TXE value going high to ensure the FIFO is filled up enough. They currently only write at most once to the DR register, whereas the reference manual describes that the FIFO can take several words of input to fill up the FIFO.
Code that works for my in my situation:
while (((hspi->Instance->SR) & 2) && (hspi->TxXferCount != 0))
{
*(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
hspi->TxXferCount--;
}
While still TXE and there's data available, write to DR the next data.
2 MHz at 8 bits per byte is fine, 1 MHz at 5 bits per byte is fine too, but speeds where bytes are completed faster such as 2 MHz at 5 bits per byte are not.
Hope to see this in mbed-src soon :)
RichColours
Symptom: using a high SPI output rate such at 2 MHz at 5 bits per byte (that is, 5 bits per SPI 'byte'), the SPI output is not completely continuous. Gaps occur between strings of 5-bit bytes.
Bug: the transmit IRQ handlers in
Code that works for my in my situation:
while (((hspi->Instance->SR) & 2) && (hspi->TxXferCount != 0)) { *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); hspi->TxXferCount--; }While still TXE and there's data available, write to DR the next data.
2 MHz at 8 bits per byte is fine, 1 MHz at 5 bits per byte is fine too, but speeds where bytes are completed faster such as 2 MHz at 5 bits per byte are not.
Hope to see this in mbed-src soon :)
RichColours