Przemek Dawid / Mbed 2 deprecated KL46Z-Lab2_szkolenie

akcelerometr i czujnik swiatla

Dependencies:   MAG3110 MMA8451Q SLCD- TSI USBDevice mbed

SLCD-/LCDconfig.h@0:9f7e045dcaa5, 2014-04-16 (annotated)

Committer:
zochmen
Date:
Wed Apr 16 12:20:13 2014 +0000
Revision:
0:9f7e045dcaa5
akcelerometr; czujnika swiatla;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
zochmen 0:9f7e045dcaa5 1 #include "FRDM-s401.h" // 4x7 segdisplay
zochmen 0:9f7e045dcaa5 2
zochmen 0:9f7e045dcaa5 3
zochmen 0:9f7e045dcaa5 4 #if 1 // VREF to VLL1
zochmen 0:9f7e045dcaa5 5 /* Following configuration is used for LCD default initialization */
zochmen 0:9f7e045dcaa5 6 #define _LCDRVEN (1) //
zochmen 0:9f7e045dcaa5 7 #define _LCDRVTRIM (8) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
zochmen 0:9f7e045dcaa5 8 #define _LCDCPSEL (1) // charge pump select 0 or 1
zochmen 0:9f7e045dcaa5 9 #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
zochmen 0:9f7e045dcaa5 10 #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
zochmen 0:9f7e045dcaa5 11 #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock
zochmen 0:9f7e045dcaa5 12
zochmen 0:9f7e045dcaa5 13 #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms
zochmen 0:9f7e045dcaa5 14 #define _LCDSUPPLY (1)
zochmen 0:9f7e045dcaa5 15 #define _LCDHREF (0) // 0 or 1
zochmen 0:9f7e045dcaa5 16 #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock
zochmen 0:9f7e045dcaa5 17 #define _LCDLCK (1) //Any number between 0 and 7
zochmen 0:9f7e045dcaa5 18 #define _LCDBLINKRATE (3) //Any number between 0 and 7
zochmen 0:9f7e045dcaa5 19
zochmen 0:9f7e045dcaa5 20
zochmen 0:9f7e045dcaa5 21 #else //VLL3 to VDD internally
zochmen 0:9f7e045dcaa5 22 /* Following configuration is used for LCD default initialization */
zochmen 0:9f7e045dcaa5 23 #define _LCDCLKSOURCE (1) // 0 -- External clock 1 -- Alternate clock
zochmen 0:9f7e045dcaa5 24 #define _LCDALRCLKSOURCE (0) // 0 -- External clock 1 -- Alternate clock
zochmen 0:9f7e045dcaa5 25 #define _LCDCLKPSL (0) // Clock divider to generate the LCD Waveforms
zochmen 0:9f7e045dcaa5 26 #define _LCDSUPPLY (0)
zochmen 0:9f7e045dcaa5 27 #define _LCDLOADADJUST (3) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
zochmen 0:9f7e045dcaa5 28 #define _LCDALTDIV (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
zochmen 0:9f7e045dcaa5 29 #define _LCDRVTRIM (0) // CPSEL = 1 0 -- 8000 pf 1 -- 6000 pf 2 -- 4000 pf 3 -- 2000 pf
zochmen 0:9f7e045dcaa5 30 #define _LCDHREF (0) // 0 or 1
zochmen 0:9f7e045dcaa5 31 #define _LCDCPSEL (1) // 0 or 1
zochmen 0:9f7e045dcaa5 32 #define _LCDRVEN (0) //
zochmen 0:9f7e045dcaa5 33 #define _LCDBLINKRATE (3) // Any number between 0 and 7
zochmen 0:9f7e045dcaa5 34 #define _LCDLCK (0) // Any number between 0 and 7
zochmen 0:9f7e045dcaa5 35
zochmen 0:9f7e045dcaa5 36 #endif
zochmen 0:9f7e045dcaa5 37
zochmen 0:9f7e045dcaa5 38
zochmen 0:9f7e045dcaa5 39
zochmen 0:9f7e045dcaa5 40
zochmen 0:9f7e045dcaa5 41 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 0 ~|~|~|~|~|~|~|~|~|~|~|~|~*/
zochmen 0:9f7e045dcaa5 42 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
zochmen 0:9f7e045dcaa5 43 #define _LCDINTENABLE (1)
zochmen 0:9f7e045dcaa5 44
zochmen 0:9f7e045dcaa5 45 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Control Register 1 ~|~|~|~|~|~|~|~|~|~|~|~|~|*/
zochmen 0:9f7e045dcaa5 46 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
zochmen 0:9f7e045dcaa5 47 #define _LCDFRAMEINTERRUPT (0) //0 Disable Frame Frequency Interrupt
zochmen 0:9f7e045dcaa5 48 //1 Enable an LCD interrupt that coincides with the LCD frame frequency
zochmen 0:9f7e045dcaa5 49 #define _LCDFULLCPLDIRIVE (0) // 0 GPIO shared with the LCD. Inputs levels and internal pullup reference to VDD
zochmen 0:9f7e045dcaa5 50 // 1 If VSUPPLY=11and RVEN=0. Inputs levels and internal pullup reference to VLL3
zochmen 0:9f7e045dcaa5 51 #define _LCDWAITMODE (0) // 0 Allows the LCD driver and charge pump to continue running during wait mode
zochmen 0:9f7e045dcaa5 52 // 1 Disable the LCD when the MCU goes into wait mode
zochmen 0:9f7e045dcaa5 53 #define _LCDSTOPMODE (0) // 0 Allows the LCD driver and charge pump to continue running during stop2 or stop3
zochmen 0:9f7e045dcaa5 54 // 1 Disable the LCD when and charge pump when the MCU goes into stop2 or stop3
zochmen 0:9f7e045dcaa5 55
zochmen 0:9f7e045dcaa5 56 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Voltage Supply Register ~|~|~|~|~|~|~|~|~|~|~|~*/
zochmen 0:9f7e045dcaa5 57 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
zochmen 0:9f7e045dcaa5 58 #define _LCDHIGHREF (0) //0 Divide input VIREG=1.0v
zochmen 0:9f7e045dcaa5 59 //1 Do not divide the input VIREG=1.67v
zochmen 0:9f7e045dcaa5 60 #define _LCDBBYPASS (0) //Determines whether the internal LCD op amp buffer is bypassed
zochmen 0:9f7e045dcaa5 61 //0 Buffered mode
zochmen 0:9f7e045dcaa5 62 //1 Unbuffered mode
zochmen 0:9f7e045dcaa5 63
zochmen 0:9f7e045dcaa5 64 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Regulated Voltage Control |~|~|~|~|~|~|~|~|~|~*/
zochmen 0:9f7e045dcaa5 65 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
zochmen 0:9f7e045dcaa5 66 #define _LCDCONTRAST (1) //Contrast by software 0 -- Disable 1-- Enable
zochmen 0:9f7e045dcaa5 67 #define _LVLCONTRAST (0) //Any number between 0 and 15, if the number is bigger the glass gets darker
zochmen 0:9f7e045dcaa5 68
zochmen 0:9f7e045dcaa5 69 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~ LCD Blink Control Register ~|~|~|~|~|~|~|~|~|~|~|~*/
zochmen 0:9f7e045dcaa5 70 /*~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|~|*/
zochmen 0:9f7e045dcaa5 71 #define _LCDBLINKCONTROL (1) //0 Disable blink mode
zochmen 0:9f7e045dcaa5 72 //1 Enable blink mode
zochmen 0:9f7e045dcaa5 73 #define _LCDALTMODE (0) //0 Normal display
zochmen 0:9f7e045dcaa5 74 //1 Alternate display for 4 backplanes or less the LCD backplane sequencer changes to otuput an alternate display
zochmen 0:9f7e045dcaa5 75 #define _LCDBLANKDISP (0) //0 Do not blank display
zochmen 0:9f7e045dcaa5 76 //1 Blank display if you put it in 0 the text before blank is manteined
zochmen 0:9f7e045dcaa5 77 #define _LCDBLINKMODE (0) //0 Display blank during the blink period
zochmen 0:9f7e045dcaa5 78 //1 Display alternate displat during blink period (Ignored if duty is 5 or greater)
zochmen 0:9f7e045dcaa5 79
zochmen 0:9f7e045dcaa5 80
zochmen 0:9f7e045dcaa5 81 //Calculated values
zochmen 0:9f7e045dcaa5 82 #define _LCDUSEDPINS (_LCDFRONTPLANES + _LCDBACKPLANES)
zochmen 0:9f7e045dcaa5 83 #define _LCDDUTY (_LCDBACKPLANES-1) //Any number between 0 and 7
zochmen 0:9f7e045dcaa5 84 #define LCD_WF_BASE LCD->WF8B[0]
zochmen 0:9f7e045dcaa5 85
zochmen 0:9f7e045dcaa5 86 // General definitions used by the LCD library
zochmen 0:9f7e045dcaa5 87 #define LCD_WF(x) *((uint8 *)&LCD_WF_BASE + x)
zochmen 0:9f7e045dcaa5 88
zochmen 0:9f7e045dcaa5 89 /*LCD Fault Detections Consts*/
zochmen 0:9f7e045dcaa5 90 #define FP_TYPE 0x00 // pin is a Front Plane
zochmen 0:9f7e045dcaa5 91 #define BP_TYPE 0x80 // pin is Back Plane
zochmen 0:9f7e045dcaa5 92
zochmen 0:9f7e045dcaa5 93 // Fault Detect Preescaler Options
zochmen 0:9f7e045dcaa5 94 #define FDPRS_1 0
zochmen 0:9f7e045dcaa5 95 #define FDPRS_2 1
zochmen 0:9f7e045dcaa5 96 #define FDPRS_4 2
zochmen 0:9f7e045dcaa5 97 #define FDPRS_8 3
zochmen 0:9f7e045dcaa5 98 #define FDPRS_16 4
zochmen 0:9f7e045dcaa5 99 #define FDPRS_32 5
zochmen 0:9f7e045dcaa5 100 #define FDPRS_64 6
zochmen 0:9f7e045dcaa5 101 #define FDPRS_128 7
zochmen 0:9f7e045dcaa5 102
zochmen 0:9f7e045dcaa5 103 // Fault Detect Sample Window Width Values
zochmen 0:9f7e045dcaa5 104 #define FDSWW_4 0
zochmen 0:9f7e045dcaa5 105 #define FDSWW_8 1
zochmen 0:9f7e045dcaa5 106 #define FDSWW_16 2
zochmen 0:9f7e045dcaa5 107 #define FDSWW_32 3
zochmen 0:9f7e045dcaa5 108 #define FDSWW_64 4
zochmen 0:9f7e045dcaa5 109 #define FDSWW_128 5
zochmen 0:9f7e045dcaa5 110 #define FDSWW_256 6
zochmen 0:9f7e045dcaa5 111 #define FDSWW_512 7
zochmen 0:9f7e045dcaa5 112
zochmen 0:9f7e045dcaa5 113 /*
zochmen 0:9f7e045dcaa5 114 Mask Bit definitions used f
zochmen 0:9f7e045dcaa5 115 */
zochmen 0:9f7e045dcaa5 116 #define mBIT0 1
zochmen 0:9f7e045dcaa5 117 #define mBIT1 2
zochmen 0:9f7e045dcaa5 118 #define mBIT2 4
zochmen 0:9f7e045dcaa5 119 #define mBIT3 8
zochmen 0:9f7e045dcaa5 120 #define mBIT4 16
zochmen 0:9f7e045dcaa5 121 #define mBIT5 32
zochmen 0:9f7e045dcaa5 122 #define mBIT6 64
zochmen 0:9f7e045dcaa5 123 #define mBIT7 128
zochmen 0:9f7e045dcaa5 124 #define mBIT8 256
zochmen 0:9f7e045dcaa5 125 #define mBIT9 512
zochmen 0:9f7e045dcaa5 126 #define mBIT10 1024
zochmen 0:9f7e045dcaa5 127 #define mBIT11 2048
zochmen 0:9f7e045dcaa5 128 #define mBIT12 4096
zochmen 0:9f7e045dcaa5 129 #define mBIT13 8192
zochmen 0:9f7e045dcaa5 130 #define mBIT14 16384
zochmen 0:9f7e045dcaa5 131 #define mBIT15 32768
zochmen 0:9f7e045dcaa5 132 #define mBIT16 65536
zochmen 0:9f7e045dcaa5 133 #define mBIT17 131072
zochmen 0:9f7e045dcaa5 134 #define mBIT18 262144
zochmen 0:9f7e045dcaa5 135 #define mBIT19 524288
zochmen 0:9f7e045dcaa5 136 #define mBIT20 1048576
zochmen 0:9f7e045dcaa5 137 #define mBIT21 2097152
zochmen 0:9f7e045dcaa5 138 #define mBIT22 4194304
zochmen 0:9f7e045dcaa5 139 #define mBIT23 8388608
zochmen 0:9f7e045dcaa5 140 #define mBIT24 16777216
zochmen 0:9f7e045dcaa5 141 #define mBIT25 33554432
zochmen 0:9f7e045dcaa5 142 #define mBIT26 67108864
zochmen 0:9f7e045dcaa5 143 #define mBIT27 134217728
zochmen 0:9f7e045dcaa5 144 #define mBIT28 268435456
zochmen 0:9f7e045dcaa5 145 #define mBIT29 536870912
zochmen 0:9f7e045dcaa5 146 #define mBIT30 1073741824
zochmen 0:9f7e045dcaa5 147 #define mBIT31 2147483648
zochmen 0:9f7e045dcaa5 148
zochmen 0:9f7e045dcaa5 149 #define mBIT32 1
zochmen 0:9f7e045dcaa5 150 #define mBIT33 2
zochmen 0:9f7e045dcaa5 151 #define mBIT34 4
zochmen 0:9f7e045dcaa5 152 #define mBIT35 8
zochmen 0:9f7e045dcaa5 153 #define mBIT36 16
zochmen 0:9f7e045dcaa5 154 #define mBIT37 32
zochmen 0:9f7e045dcaa5 155 #define mBIT38 64
zochmen 0:9f7e045dcaa5 156 #define mBIT39 128
zochmen 0:9f7e045dcaa5 157 #define mBIT40 256
zochmen 0:9f7e045dcaa5 158 #define mBIT41 512
zochmen 0:9f7e045dcaa5 159 #define mBIT42 1024
zochmen 0:9f7e045dcaa5 160 #define mBIT43 2048
zochmen 0:9f7e045dcaa5 161 #define mBIT44 4096
zochmen 0:9f7e045dcaa5 162 #define mBIT45 8192
zochmen 0:9f7e045dcaa5 163 #define mBIT46 16384
zochmen 0:9f7e045dcaa5 164 #define mBIT47 32768
zochmen 0:9f7e045dcaa5 165 #define mBIT48 65536
zochmen 0:9f7e045dcaa5 166 #define mBIT49 131072
zochmen 0:9f7e045dcaa5 167 #define mBIT50 262144
zochmen 0:9f7e045dcaa5 168 #define mBIT51 524288
zochmen 0:9f7e045dcaa5 169 #define mBIT52 1048576
zochmen 0:9f7e045dcaa5 170 #define mBIT53 2097152
zochmen 0:9f7e045dcaa5 171 #define mBIT54 4194304
zochmen 0:9f7e045dcaa5 172 #define mBIT55 8388608
zochmen 0:9f7e045dcaa5 173 #define mBIT56 16777216
zochmen 0:9f7e045dcaa5 174 #define mBIT57 33554432
zochmen 0:9f7e045dcaa5 175 #define mBIT58 67108864
zochmen 0:9f7e045dcaa5 176 #define mBIT59 134217728
zochmen 0:9f7e045dcaa5 177 #define mBIT60 268435456
zochmen 0:9f7e045dcaa5 178 #define mBIT61 536870912
zochmen 0:9f7e045dcaa5 179 #define mBIT62 1073741824
zochmen 0:9f7e045dcaa5 180 #define mBIT63 2147483648
zochmen 0:9f7e045dcaa5 181
zochmen 0:9f7e045dcaa5 182
zochmen 0:9f7e045dcaa5 183