雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

Fork of mbed by mbed official

TARGET_NUCLEO_F302R8/stm32f30x_rcc.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /**
bogdanm 82:6473597d706e 2 ******************************************************************************
bogdanm 82:6473597d706e 3 * @file stm32f30x_rcc.h
bogdanm 82:6473597d706e 4 * @author MCD Application Team
bogdanm 82:6473597d706e 5 * @version V1.1.0
bogdanm 82:6473597d706e 6 * @date 27-February-2014
bogdanm 82:6473597d706e 7 * @brief This file contains all the functions prototypes for the RCC
bogdanm 82:6473597d706e 8 * firmware library.
bogdanm 82:6473597d706e 9 ******************************************************************************
bogdanm 82:6473597d706e 10 * @attention
bogdanm 82:6473597d706e 11 *
bogdanm 82:6473597d706e 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 82:6473597d706e 13 *
bogdanm 82:6473597d706e 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 82:6473597d706e 15 * are permitted provided that the following conditions are met:
bogdanm 82:6473597d706e 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 82:6473597d706e 17 * this list of conditions and the following disclaimer.
bogdanm 82:6473597d706e 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 82:6473597d706e 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 82:6473597d706e 20 * and/or other materials provided with the distribution.
bogdanm 82:6473597d706e 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 82:6473597d706e 22 * may be used to endorse or promote products derived from this software
bogdanm 82:6473597d706e 23 * without specific prior written permission.
bogdanm 82:6473597d706e 24 *
bogdanm 82:6473597d706e 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 82:6473597d706e 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 82:6473597d706e 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 82:6473597d706e 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 82:6473597d706e 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 82:6473597d706e 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 82:6473597d706e 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 82:6473597d706e 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 82:6473597d706e 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 82:6473597d706e 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 82:6473597d706e 35 *
bogdanm 82:6473597d706e 36 ******************************************************************************
bogdanm 82:6473597d706e 37 */
bogdanm 82:6473597d706e 38
bogdanm 82:6473597d706e 39 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 82:6473597d706e 40 #ifndef __STM32F30x_RCC_H
bogdanm 82:6473597d706e 41 #define __STM32F30x_RCC_H
bogdanm 82:6473597d706e 42
bogdanm 82:6473597d706e 43 #ifdef __cplusplus
bogdanm 82:6473597d706e 44 extern "C" {
bogdanm 82:6473597d706e 45 #endif
bogdanm 82:6473597d706e 46
bogdanm 82:6473597d706e 47 /* Includes ------------------------------------------------------------------*/
bogdanm 82:6473597d706e 48 #include "stm32f30x.h"
bogdanm 82:6473597d706e 49
bogdanm 82:6473597d706e 50 /** @addtogroup STM32F30x_StdPeriph_Driver
bogdanm 82:6473597d706e 51 * @{
bogdanm 82:6473597d706e 52 */
bogdanm 82:6473597d706e 53
bogdanm 82:6473597d706e 54 /** @addtogroup RCC
bogdanm 82:6473597d706e 55 * @{
bogdanm 82:6473597d706e 56 */
bogdanm 82:6473597d706e 57
bogdanm 82:6473597d706e 58 /* Exported types ------------------------------------------------------------*/
bogdanm 82:6473597d706e 59
bogdanm 82:6473597d706e 60 typedef struct
bogdanm 82:6473597d706e 61 {
bogdanm 82:6473597d706e 62 uint32_t SYSCLK_Frequency;
bogdanm 82:6473597d706e 63 uint32_t HCLK_Frequency;
bogdanm 82:6473597d706e 64 uint32_t PCLK1_Frequency;
bogdanm 82:6473597d706e 65 uint32_t PCLK2_Frequency;
bogdanm 82:6473597d706e 66 uint32_t ADC12CLK_Frequency;
bogdanm 82:6473597d706e 67 uint32_t ADC34CLK_Frequency;
bogdanm 82:6473597d706e 68 uint32_t I2C1CLK_Frequency;
bogdanm 82:6473597d706e 69 uint32_t I2C2CLK_Frequency;
bogdanm 82:6473597d706e 70 uint32_t I2C3CLK_Frequency;
bogdanm 82:6473597d706e 71 uint32_t TIM1CLK_Frequency;
bogdanm 82:6473597d706e 72 uint32_t HRTIM1CLK_Frequency;
bogdanm 82:6473597d706e 73 uint32_t TIM8CLK_Frequency;
bogdanm 82:6473597d706e 74 uint32_t USART1CLK_Frequency;
bogdanm 82:6473597d706e 75 uint32_t USART2CLK_Frequency;
bogdanm 82:6473597d706e 76 uint32_t USART3CLK_Frequency;
bogdanm 82:6473597d706e 77 uint32_t UART4CLK_Frequency;
bogdanm 82:6473597d706e 78 uint32_t UART5CLK_Frequency;
bogdanm 82:6473597d706e 79 uint32_t TIM15CLK_Frequency;
bogdanm 82:6473597d706e 80 uint32_t TIM16CLK_Frequency;
bogdanm 82:6473597d706e 81 uint32_t TIM17CLK_Frequency;
bogdanm 82:6473597d706e 82 }RCC_ClocksTypeDef;
bogdanm 82:6473597d706e 83
bogdanm 82:6473597d706e 84 /* Exported constants --------------------------------------------------------*/
bogdanm 82:6473597d706e 85
bogdanm 82:6473597d706e 86 /** @defgroup RCC_Exported_Constants
bogdanm 82:6473597d706e 87 * @{
bogdanm 82:6473597d706e 88 */
bogdanm 82:6473597d706e 89
bogdanm 82:6473597d706e 90 /** @defgroup RCC_HSE_configuration
bogdanm 82:6473597d706e 91 * @{
bogdanm 82:6473597d706e 92 */
bogdanm 82:6473597d706e 93
bogdanm 82:6473597d706e 94 #define RCC_HSE_OFF ((uint8_t)0x00)
bogdanm 82:6473597d706e 95 #define RCC_HSE_ON ((uint8_t)0x01)
bogdanm 82:6473597d706e 96 #define RCC_HSE_Bypass ((uint8_t)0x05)
bogdanm 82:6473597d706e 97 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
bogdanm 82:6473597d706e 98 ((HSE) == RCC_HSE_Bypass))
bogdanm 82:6473597d706e 99
bogdanm 82:6473597d706e 100 /**
bogdanm 82:6473597d706e 101 * @}
bogdanm 82:6473597d706e 102 */
bogdanm 82:6473597d706e 103
bogdanm 82:6473597d706e 104 /** @defgroup RCC_PLL_Clock_Source
bogdanm 82:6473597d706e 105 * @{
bogdanm 82:6473597d706e 106 */
bogdanm 82:6473597d706e 107
bogdanm 82:6473597d706e 108 #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
bogdanm 82:6473597d706e 109 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
bogdanm 82:6473597d706e 110
bogdanm 82:6473597d706e 111 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
bogdanm 82:6473597d706e 112 ((SOURCE) == RCC_PLLSource_PREDIV1))
bogdanm 82:6473597d706e 113 /**
bogdanm 82:6473597d706e 114 * @}
bogdanm 82:6473597d706e 115 */
bogdanm 82:6473597d706e 116
bogdanm 82:6473597d706e 117 /** @defgroup RCC_PLL_Multiplication_Factor
bogdanm 82:6473597d706e 118 * @{
bogdanm 82:6473597d706e 119 */
bogdanm 82:6473597d706e 120
bogdanm 82:6473597d706e 121 #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
bogdanm 82:6473597d706e 122 #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
bogdanm 82:6473597d706e 123 #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
bogdanm 82:6473597d706e 124 #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
bogdanm 82:6473597d706e 125 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
bogdanm 82:6473597d706e 126 #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
bogdanm 82:6473597d706e 127 #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
bogdanm 82:6473597d706e 128 #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
bogdanm 82:6473597d706e 129 #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
bogdanm 82:6473597d706e 130 #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
bogdanm 82:6473597d706e 131 #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
bogdanm 82:6473597d706e 132 #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
bogdanm 82:6473597d706e 133 #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
bogdanm 82:6473597d706e 134 #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
bogdanm 82:6473597d706e 135 #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
bogdanm 82:6473597d706e 136 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
bogdanm 82:6473597d706e 137 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
bogdanm 82:6473597d706e 138 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
bogdanm 82:6473597d706e 139 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
bogdanm 82:6473597d706e 140 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
bogdanm 82:6473597d706e 141 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
bogdanm 82:6473597d706e 142 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
bogdanm 82:6473597d706e 143 ((MUL) == RCC_PLLMul_16))
bogdanm 82:6473597d706e 144 /**
bogdanm 82:6473597d706e 145 * @}
bogdanm 82:6473597d706e 146 */
bogdanm 82:6473597d706e 147
bogdanm 82:6473597d706e 148 /** @defgroup RCC_PREDIV1_division_factor
bogdanm 82:6473597d706e 149 * @{
bogdanm 82:6473597d706e 150 */
bogdanm 82:6473597d706e 151 #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
bogdanm 82:6473597d706e 152 #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
bogdanm 82:6473597d706e 153 #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
bogdanm 82:6473597d706e 154 #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
bogdanm 82:6473597d706e 155 #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
bogdanm 82:6473597d706e 156 #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
bogdanm 82:6473597d706e 157 #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
bogdanm 82:6473597d706e 158 #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
bogdanm 82:6473597d706e 159 #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
bogdanm 82:6473597d706e 160 #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
bogdanm 82:6473597d706e 161 #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
bogdanm 82:6473597d706e 162 #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
bogdanm 82:6473597d706e 163 #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
bogdanm 82:6473597d706e 164 #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
bogdanm 82:6473597d706e 165 #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
bogdanm 82:6473597d706e 166 #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
bogdanm 82:6473597d706e 167
bogdanm 82:6473597d706e 168 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
bogdanm 82:6473597d706e 169 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
bogdanm 82:6473597d706e 170 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
bogdanm 82:6473597d706e 171 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
bogdanm 82:6473597d706e 172 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
bogdanm 82:6473597d706e 173 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
bogdanm 82:6473597d706e 174 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
bogdanm 82:6473597d706e 175 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
bogdanm 82:6473597d706e 176 /**
bogdanm 82:6473597d706e 177 * @}
bogdanm 82:6473597d706e 178 */
bogdanm 82:6473597d706e 179
bogdanm 82:6473597d706e 180 /** @defgroup RCC_System_Clock_Source
bogdanm 82:6473597d706e 181 * @{
bogdanm 82:6473597d706e 182 */
bogdanm 82:6473597d706e 183
bogdanm 82:6473597d706e 184 #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
bogdanm 82:6473597d706e 185 #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
bogdanm 82:6473597d706e 186 #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
bogdanm 82:6473597d706e 187 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
bogdanm 82:6473597d706e 188 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
bogdanm 82:6473597d706e 189 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
bogdanm 82:6473597d706e 190 /**
bogdanm 82:6473597d706e 191 * @}
bogdanm 82:6473597d706e 192 */
bogdanm 82:6473597d706e 193
bogdanm 82:6473597d706e 194 /** @defgroup RCC_AHB_Clock_Source
bogdanm 82:6473597d706e 195 * @{
bogdanm 82:6473597d706e 196 */
bogdanm 82:6473597d706e 197
bogdanm 82:6473597d706e 198 #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
bogdanm 82:6473597d706e 199 #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
bogdanm 82:6473597d706e 200 #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
bogdanm 82:6473597d706e 201 #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
bogdanm 82:6473597d706e 202 #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
bogdanm 82:6473597d706e 203 #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
bogdanm 82:6473597d706e 204 #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
bogdanm 82:6473597d706e 205 #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
bogdanm 82:6473597d706e 206 #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
bogdanm 82:6473597d706e 207 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
bogdanm 82:6473597d706e 208 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
bogdanm 82:6473597d706e 209 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
bogdanm 82:6473597d706e 210 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
bogdanm 82:6473597d706e 211 ((HCLK) == RCC_SYSCLK_Div512))
bogdanm 82:6473597d706e 212 /**
bogdanm 82:6473597d706e 213 * @}
bogdanm 82:6473597d706e 214 */
bogdanm 82:6473597d706e 215
bogdanm 82:6473597d706e 216 /** @defgroup RCC_APB1_APB2_clock_source
bogdanm 82:6473597d706e 217 * @{
bogdanm 82:6473597d706e 218 */
bogdanm 82:6473597d706e 219
bogdanm 82:6473597d706e 220 #define RCC_HCLK_Div1 ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 221 #define RCC_HCLK_Div2 ((uint32_t)0x00000400)
bogdanm 82:6473597d706e 222 #define RCC_HCLK_Div4 ((uint32_t)0x00000500)
bogdanm 82:6473597d706e 223 #define RCC_HCLK_Div8 ((uint32_t)0x00000600)
bogdanm 82:6473597d706e 224 #define RCC_HCLK_Div16 ((uint32_t)0x00000700)
bogdanm 82:6473597d706e 225 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
bogdanm 82:6473597d706e 226 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
bogdanm 82:6473597d706e 227 ((PCLK) == RCC_HCLK_Div16))
bogdanm 82:6473597d706e 228 /**
bogdanm 82:6473597d706e 229 * @}
bogdanm 82:6473597d706e 230 */
bogdanm 82:6473597d706e 231
bogdanm 82:6473597d706e 232 /** @defgroup RCC_ADC_clock_source
bogdanm 82:6473597d706e 233 * @{
bogdanm 82:6473597d706e 234 */
bogdanm 82:6473597d706e 235
bogdanm 82:6473597d706e 236 /* ADC1 & ADC2 */
bogdanm 82:6473597d706e 237 #define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 238 #define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100)
bogdanm 82:6473597d706e 239 #define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110)
bogdanm 82:6473597d706e 240 #define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120)
bogdanm 82:6473597d706e 241 #define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130)
bogdanm 82:6473597d706e 242 #define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140)
bogdanm 82:6473597d706e 243 #define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150)
bogdanm 82:6473597d706e 244 #define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160)
bogdanm 82:6473597d706e 245 #define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170)
bogdanm 82:6473597d706e 246 #define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180)
bogdanm 82:6473597d706e 247 #define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190)
bogdanm 82:6473597d706e 248 #define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0)
bogdanm 82:6473597d706e 249 #define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0)
bogdanm 82:6473597d706e 250
bogdanm 82:6473597d706e 251 /* ADC3 & ADC4 */
bogdanm 82:6473597d706e 252 #define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000)
bogdanm 82:6473597d706e 253 #define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000)
bogdanm 82:6473597d706e 254 #define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200)
bogdanm 82:6473597d706e 255 #define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400)
bogdanm 82:6473597d706e 256 #define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600)
bogdanm 82:6473597d706e 257 #define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800)
bogdanm 82:6473597d706e 258 #define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00)
bogdanm 82:6473597d706e 259 #define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00)
bogdanm 82:6473597d706e 260 #define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00)
bogdanm 82:6473597d706e 261 #define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000)
bogdanm 82:6473597d706e 262 #define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200)
bogdanm 82:6473597d706e 263 #define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400)
bogdanm 82:6473597d706e 264 #define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600)
bogdanm 82:6473597d706e 265
bogdanm 82:6473597d706e 266 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \
bogdanm 82:6473597d706e 267 ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \
bogdanm 82:6473597d706e 268 ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \
bogdanm 82:6473597d706e 269 ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \
bogdanm 82:6473597d706e 270 ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \
bogdanm 82:6473597d706e 271 ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \
bogdanm 82:6473597d706e 272 ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \
bogdanm 82:6473597d706e 273 ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \
bogdanm 82:6473597d706e 274 ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \
bogdanm 82:6473597d706e 275 ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \
bogdanm 82:6473597d706e 276 ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \
bogdanm 82:6473597d706e 277 ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \
bogdanm 82:6473597d706e 278 ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256))
bogdanm 82:6473597d706e 279
bogdanm 82:6473597d706e 280 /**
bogdanm 82:6473597d706e 281 * @}
bogdanm 82:6473597d706e 282 */
bogdanm 82:6473597d706e 283
bogdanm 82:6473597d706e 284 /** @defgroup RCC_TIM_clock_source
bogdanm 82:6473597d706e 285 * @{
bogdanm 82:6473597d706e 286 */
bogdanm 82:6473597d706e 287
bogdanm 82:6473597d706e 288 #define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 289 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW
bogdanm 82:6473597d706e 290
bogdanm 82:6473597d706e 291 #define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000)
bogdanm 82:6473597d706e 292 #define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200)
bogdanm 82:6473597d706e 293
bogdanm 82:6473597d706e 294 #define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000)
bogdanm 82:6473597d706e 295 #define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400)
bogdanm 82:6473597d706e 296
bogdanm 82:6473597d706e 297 #define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000)
bogdanm 82:6473597d706e 298 #define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800)
bogdanm 82:6473597d706e 299
bogdanm 82:6473597d706e 300 #define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000)
bogdanm 82:6473597d706e 301 #define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000)
bogdanm 82:6473597d706e 302
bogdanm 82:6473597d706e 303 #define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \
bogdanm 82:6473597d706e 304 ((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \
bogdanm 82:6473597d706e 305 ((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \
bogdanm 82:6473597d706e 306 ((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \
bogdanm 82:6473597d706e 307 ((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK))
bogdanm 82:6473597d706e 308
bogdanm 82:6473597d706e 309 /**
bogdanm 82:6473597d706e 310 * @}
bogdanm 82:6473597d706e 311 */
bogdanm 82:6473597d706e 312
bogdanm 82:6473597d706e 313 /** @defgroup RCC_HRTIM_clock_source
bogdanm 82:6473597d706e 314 * @{
bogdanm 82:6473597d706e 315 */
bogdanm 82:6473597d706e 316
bogdanm 82:6473597d706e 317 #define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 318 #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW
bogdanm 82:6473597d706e 319
bogdanm 82:6473597d706e 320 #define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK))
bogdanm 82:6473597d706e 321
bogdanm 82:6473597d706e 322 /**
bogdanm 82:6473597d706e 323 * @}
bogdanm 82:6473597d706e 324 */
bogdanm 82:6473597d706e 325
bogdanm 82:6473597d706e 326 /** @defgroup RCC_I2C_clock_source
bogdanm 82:6473597d706e 327 * @{
bogdanm 82:6473597d706e 328 */
bogdanm 82:6473597d706e 329
bogdanm 82:6473597d706e 330 #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 331 #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
bogdanm 82:6473597d706e 332
bogdanm 82:6473597d706e 333 #define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
bogdanm 82:6473597d706e 334 #define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
bogdanm 82:6473597d706e 335
bogdanm 82:6473597d706e 336 #define RCC_I2C3CLK_HSI ((uint32_t)0x20000000)
bogdanm 82:6473597d706e 337 #define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040)
bogdanm 82:6473597d706e 338
bogdanm 82:6473597d706e 339 #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
bogdanm 82:6473597d706e 340 ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \
bogdanm 82:6473597d706e 341 ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK))
bogdanm 82:6473597d706e 342
bogdanm 82:6473597d706e 343 /**
bogdanm 82:6473597d706e 344 * @}
bogdanm 82:6473597d706e 345 */
bogdanm 82:6473597d706e 346
bogdanm 82:6473597d706e 347 /** @defgroup RCC_USART_clock_source
bogdanm 82:6473597d706e 348 * @{
bogdanm 82:6473597d706e 349 */
bogdanm 82:6473597d706e 350
bogdanm 82:6473597d706e 351 #define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
bogdanm 82:6473597d706e 352 #define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
bogdanm 82:6473597d706e 353 #define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
bogdanm 82:6473597d706e 354 #define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
bogdanm 82:6473597d706e 355
bogdanm 82:6473597d706e 356 #define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
bogdanm 82:6473597d706e 357 #define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
bogdanm 82:6473597d706e 358 #define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
bogdanm 82:6473597d706e 359 #define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
bogdanm 82:6473597d706e 360
bogdanm 82:6473597d706e 361 #define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
bogdanm 82:6473597d706e 362 #define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
bogdanm 82:6473597d706e 363 #define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
bogdanm 82:6473597d706e 364 #define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
bogdanm 82:6473597d706e 365
bogdanm 82:6473597d706e 366 #define RCC_UART4CLK_PCLK ((uint32_t)0x40000000)
bogdanm 82:6473597d706e 367 #define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000)
bogdanm 82:6473597d706e 368 #define RCC_UART4CLK_LSE ((uint32_t)0x40200000)
bogdanm 82:6473597d706e 369 #define RCC_UART4CLK_HSI ((uint32_t)0x40300000)
bogdanm 82:6473597d706e 370
bogdanm 82:6473597d706e 371 #define RCC_UART5CLK_PCLK ((uint32_t)0x50000000)
bogdanm 82:6473597d706e 372 #define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000)
bogdanm 82:6473597d706e 373 #define RCC_UART5CLK_LSE ((uint32_t)0x50800000)
bogdanm 82:6473597d706e 374 #define RCC_UART5CLK_HSI ((uint32_t)0x50C00000)
bogdanm 82:6473597d706e 375
bogdanm 82:6473597d706e 376 #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
bogdanm 82:6473597d706e 377 ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
bogdanm 82:6473597d706e 378 ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
bogdanm 82:6473597d706e 379 ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
bogdanm 82:6473597d706e 380 ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
bogdanm 82:6473597d706e 381 ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \
bogdanm 82:6473597d706e 382 ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \
bogdanm 82:6473597d706e 383 ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \
bogdanm 82:6473597d706e 384 ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \
bogdanm 82:6473597d706e 385 ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI))
bogdanm 82:6473597d706e 386
bogdanm 82:6473597d706e 387 /**
bogdanm 82:6473597d706e 388 * @}
bogdanm 82:6473597d706e 389 */
bogdanm 82:6473597d706e 390
bogdanm 82:6473597d706e 391 /** @defgroup RCC_Interrupt_Source
bogdanm 82:6473597d706e 392 * @{
bogdanm 82:6473597d706e 393 */
bogdanm 82:6473597d706e 394
bogdanm 82:6473597d706e 395 #define RCC_IT_LSIRDY ((uint8_t)0x01)
bogdanm 82:6473597d706e 396 #define RCC_IT_LSERDY ((uint8_t)0x02)
bogdanm 82:6473597d706e 397 #define RCC_IT_HSIRDY ((uint8_t)0x04)
bogdanm 82:6473597d706e 398 #define RCC_IT_HSERDY ((uint8_t)0x08)
bogdanm 82:6473597d706e 399 #define RCC_IT_PLLRDY ((uint8_t)0x10)
bogdanm 82:6473597d706e 400 #define RCC_IT_CSS ((uint8_t)0x80)
bogdanm 82:6473597d706e 401
bogdanm 82:6473597d706e 402 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
bogdanm 82:6473597d706e 403
bogdanm 82:6473597d706e 404 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
bogdanm 82:6473597d706e 405 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
bogdanm 82:6473597d706e 406 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
bogdanm 82:6473597d706e 407
bogdanm 82:6473597d706e 408
bogdanm 82:6473597d706e 409 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
bogdanm 82:6473597d706e 410
bogdanm 82:6473597d706e 411 /**
bogdanm 82:6473597d706e 412 * @}
bogdanm 82:6473597d706e 413 */
bogdanm 82:6473597d706e 414
bogdanm 82:6473597d706e 415 /** @defgroup RCC_LSE_configuration
bogdanm 82:6473597d706e 416 * @{
bogdanm 82:6473597d706e 417 */
bogdanm 82:6473597d706e 418
bogdanm 82:6473597d706e 419 #define RCC_LSE_OFF ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 420 #define RCC_LSE_ON RCC_BDCR_LSEON
bogdanm 82:6473597d706e 421 #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
bogdanm 82:6473597d706e 422 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
bogdanm 82:6473597d706e 423 ((LSE) == RCC_LSE_Bypass))
bogdanm 82:6473597d706e 424 /**
bogdanm 82:6473597d706e 425 * @}
bogdanm 82:6473597d706e 426 */
bogdanm 82:6473597d706e 427
bogdanm 82:6473597d706e 428 /** @defgroup RCC_RTC_Clock_Source
bogdanm 82:6473597d706e 429 * @{
bogdanm 82:6473597d706e 430 */
bogdanm 82:6473597d706e 431
bogdanm 82:6473597d706e 432 #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
bogdanm 82:6473597d706e 433 #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
bogdanm 82:6473597d706e 434 #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
bogdanm 82:6473597d706e 435
bogdanm 82:6473597d706e 436 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
bogdanm 82:6473597d706e 437 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
bogdanm 82:6473597d706e 438 ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
bogdanm 82:6473597d706e 439 /**
bogdanm 82:6473597d706e 440 * @}
bogdanm 82:6473597d706e 441 */
bogdanm 82:6473597d706e 442
bogdanm 82:6473597d706e 443 /** @defgroup RCC_I2S_Clock_Source
bogdanm 82:6473597d706e 444 * @{
bogdanm 82:6473597d706e 445 */
bogdanm 82:6473597d706e 446 #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
bogdanm 82:6473597d706e 447 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01)
bogdanm 82:6473597d706e 448
bogdanm 82:6473597d706e 449 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext))
bogdanm 82:6473597d706e 450
bogdanm 82:6473597d706e 451 /** @defgroup RCC_LSE_Drive_Configuration
bogdanm 82:6473597d706e 452 * @{
bogdanm 82:6473597d706e 453 */
bogdanm 82:6473597d706e 454
bogdanm 82:6473597d706e 455 #define RCC_LSEDrive_Low ((uint32_t)0x00000000)
bogdanm 82:6473597d706e 456 #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
bogdanm 82:6473597d706e 457 #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
bogdanm 82:6473597d706e 458 #define RCC_LSEDrive_High RCC_BDCR_LSEDRV
bogdanm 82:6473597d706e 459 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
bogdanm 82:6473597d706e 460 ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
bogdanm 82:6473597d706e 461 /**
bogdanm 82:6473597d706e 462 * @}
bogdanm 82:6473597d706e 463 */
bogdanm 82:6473597d706e 464
bogdanm 82:6473597d706e 465 /** @defgroup RCC_AHB_Peripherals
bogdanm 82:6473597d706e 466 * @{
bogdanm 82:6473597d706e 467 */
bogdanm 82:6473597d706e 468
bogdanm 82:6473597d706e 469 #define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN
bogdanm 82:6473597d706e 470 #define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN
bogdanm 82:6473597d706e 471 #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
bogdanm 82:6473597d706e 472 #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
bogdanm 82:6473597d706e 473 #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
bogdanm 82:6473597d706e 474 #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
bogdanm 82:6473597d706e 475 #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
bogdanm 82:6473597d706e 476 #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
bogdanm 82:6473597d706e 477 #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
bogdanm 82:6473597d706e 478 #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
bogdanm 82:6473597d706e 479 #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
bogdanm 82:6473597d706e 480 #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
bogdanm 82:6473597d706e 481 #define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
bogdanm 82:6473597d706e 482 #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
bogdanm 82:6473597d706e 483
bogdanm 82:6473597d706e 484 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00))
bogdanm 82:6473597d706e 485 #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00))
bogdanm 82:6473597d706e 486
bogdanm 82:6473597d706e 487 /**
bogdanm 82:6473597d706e 488 * @}
bogdanm 82:6473597d706e 489 */
bogdanm 82:6473597d706e 490
bogdanm 82:6473597d706e 491 /** @defgroup RCC_APB2_Peripherals
bogdanm 82:6473597d706e 492 * @{
bogdanm 82:6473597d706e 493 */
bogdanm 82:6473597d706e 494
bogdanm 82:6473597d706e 495 #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
bogdanm 82:6473597d706e 496 #define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
bogdanm 82:6473597d706e 497 #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
bogdanm 82:6473597d706e 498 #define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN
bogdanm 82:6473597d706e 499 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
bogdanm 82:6473597d706e 500 #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
bogdanm 82:6473597d706e 501 #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
bogdanm 82:6473597d706e 502 #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
bogdanm 82:6473597d706e 503 #define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1
bogdanm 82:6473597d706e 504
bogdanm 82:6473597d706e 505 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00))
bogdanm 82:6473597d706e 506
bogdanm 82:6473597d706e 507 /**
bogdanm 82:6473597d706e 508 * @}
bogdanm 82:6473597d706e 509 */
bogdanm 82:6473597d706e 510
bogdanm 82:6473597d706e 511 /** @defgroup RCC_APB1_Peripherals
bogdanm 82:6473597d706e 512 * @{
bogdanm 82:6473597d706e 513 */
bogdanm 82:6473597d706e 514 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
bogdanm 82:6473597d706e 515 #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
bogdanm 82:6473597d706e 516 #define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
bogdanm 82:6473597d706e 517 #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
bogdanm 82:6473597d706e 518 #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
bogdanm 82:6473597d706e 519 #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
bogdanm 82:6473597d706e 520 #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
bogdanm 82:6473597d706e 521 #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
bogdanm 82:6473597d706e 522 #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
bogdanm 82:6473597d706e 523 #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
bogdanm 82:6473597d706e 524 #define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
bogdanm 82:6473597d706e 525 #define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
bogdanm 82:6473597d706e 526 #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
bogdanm 82:6473597d706e 527 #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
bogdanm 82:6473597d706e 528 #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
bogdanm 82:6473597d706e 529 #define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
bogdanm 82:6473597d706e 530 #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
bogdanm 82:6473597d706e 531 #define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
bogdanm 82:6473597d706e 532 #define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN
bogdanm 82:6473597d706e 533 #define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
bogdanm 82:6473597d706e 534 #define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1
bogdanm 82:6473597d706e 535
bogdanm 82:6473597d706e 536
bogdanm 82:6473597d706e 537 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00))
bogdanm 82:6473597d706e 538 /**
bogdanm 82:6473597d706e 539 * @}
bogdanm 82:6473597d706e 540 */
bogdanm 82:6473597d706e 541
bogdanm 82:6473597d706e 542 /** @defgroup RCC_MCO_Clock_Source
bogdanm 82:6473597d706e 543 * @{
bogdanm 82:6473597d706e 544 */
bogdanm 82:6473597d706e 545
bogdanm 82:6473597d706e 546 #define RCC_MCOSource_NoClock ((uint8_t)0x00)
bogdanm 82:6473597d706e 547 #define RCC_MCOSource_LSI ((uint8_t)0x02)
bogdanm 82:6473597d706e 548 #define RCC_MCOSource_LSE ((uint8_t)0x03)
bogdanm 82:6473597d706e 549 #define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
bogdanm 82:6473597d706e 550 #define RCC_MCOSource_HSI ((uint8_t)0x05)
bogdanm 82:6473597d706e 551 #define RCC_MCOSource_HSE ((uint8_t)0x06)
bogdanm 82:6473597d706e 552 #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
bogdanm 82:6473597d706e 553
bogdanm 82:6473597d706e 554 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
bogdanm 82:6473597d706e 555 ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
bogdanm 82:6473597d706e 556 ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
bogdanm 82:6473597d706e 557 ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
bogdanm 82:6473597d706e 558 /**
bogdanm 82:6473597d706e 559 * @}
bogdanm 82:6473597d706e 560 */
bogdanm 82:6473597d706e 561
bogdanm 82:6473597d706e 562 /** @defgroup RCC_MCOPrescaler
bogdanm 82:6473597d706e 563 * @{
bogdanm 82:6473597d706e 564 */
bogdanm 82:6473597d706e 565
bogdanm 82:6473597d706e 566 #define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
bogdanm 82:6473597d706e 567 #define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
bogdanm 82:6473597d706e 568 #define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
bogdanm 82:6473597d706e 569 #define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
bogdanm 82:6473597d706e 570 #define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
bogdanm 82:6473597d706e 571 #define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
bogdanm 82:6473597d706e 572 #define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
bogdanm 82:6473597d706e 573 #define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
bogdanm 82:6473597d706e 574
bogdanm 82:6473597d706e 575 #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
bogdanm 82:6473597d706e 576 ((PRESCALER) == RCC_MCOPrescaler_2) || \
bogdanm 82:6473597d706e 577 ((PRESCALER) == RCC_MCOPrescaler_4) || \
bogdanm 82:6473597d706e 578 ((PRESCALER) == RCC_MCOPrescaler_8) || \
bogdanm 82:6473597d706e 579 ((PRESCALER) == RCC_MCOPrescaler_16) || \
bogdanm 82:6473597d706e 580 ((PRESCALER) == RCC_MCOPrescaler_32) || \
bogdanm 82:6473597d706e 581 ((PRESCALER) == RCC_MCOPrescaler_64) || \
bogdanm 82:6473597d706e 582 ((PRESCALER) == RCC_MCOPrescaler_128))
bogdanm 82:6473597d706e 583 /**
bogdanm 82:6473597d706e 584 * @}
bogdanm 82:6473597d706e 585 */
bogdanm 82:6473597d706e 586
bogdanm 82:6473597d706e 587 /** @defgroup RCC_USB_Device_clock_source
bogdanm 82:6473597d706e 588 * @{
bogdanm 82:6473597d706e 589 */
bogdanm 82:6473597d706e 590
bogdanm 82:6473597d706e 591 #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
bogdanm 82:6473597d706e 592 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
bogdanm 82:6473597d706e 593
bogdanm 82:6473597d706e 594 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
bogdanm 82:6473597d706e 595 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
bogdanm 82:6473597d706e 596 /**
bogdanm 82:6473597d706e 597 * @}
bogdanm 82:6473597d706e 598 */
bogdanm 82:6473597d706e 599
bogdanm 82:6473597d706e 600 /** @defgroup RCC_Flag
bogdanm 82:6473597d706e 601 * @{
bogdanm 82:6473597d706e 602 */
bogdanm 82:6473597d706e 603 #define RCC_FLAG_HSIRDY ((uint8_t)0x01)
bogdanm 82:6473597d706e 604 #define RCC_FLAG_HSERDY ((uint8_t)0x11)
bogdanm 82:6473597d706e 605 #define RCC_FLAG_PLLRDY ((uint8_t)0x19)
bogdanm 82:6473597d706e 606 #define RCC_FLAG_MCOF ((uint8_t)0x9C)
bogdanm 82:6473597d706e 607 #define RCC_FLAG_LSERDY ((uint8_t)0x21)
bogdanm 82:6473597d706e 608 #define RCC_FLAG_LSIRDY ((uint8_t)0x41)
bogdanm 82:6473597d706e 609 #define RCC_FLAG_OBLRST ((uint8_t)0x59)
bogdanm 82:6473597d706e 610 #define RCC_FLAG_PINRST ((uint8_t)0x5A)
bogdanm 82:6473597d706e 611 #define RCC_FLAG_PORRST ((uint8_t)0x5B)
bogdanm 82:6473597d706e 612 #define RCC_FLAG_SFTRST ((uint8_t)0x5C)
bogdanm 82:6473597d706e 613 #define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
bogdanm 82:6473597d706e 614 #define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
bogdanm 82:6473597d706e 615 #define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
bogdanm 82:6473597d706e 616
bogdanm 82:6473597d706e 617 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
bogdanm 82:6473597d706e 618 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
bogdanm 82:6473597d706e 619 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
bogdanm 82:6473597d706e 620 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
bogdanm 82:6473597d706e 621 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
bogdanm 82:6473597d706e 622 ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
bogdanm 82:6473597d706e 623 ((FLAG) == RCC_FLAG_MCOF))
bogdanm 82:6473597d706e 624
bogdanm 82:6473597d706e 625 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
bogdanm 82:6473597d706e 626
bogdanm 82:6473597d706e 627 /**
bogdanm 82:6473597d706e 628 * @}
bogdanm 82:6473597d706e 629 */
bogdanm 82:6473597d706e 630
bogdanm 82:6473597d706e 631 /**
bogdanm 82:6473597d706e 632 * @}
bogdanm 82:6473597d706e 633 */
bogdanm 82:6473597d706e 634
bogdanm 82:6473597d706e 635 /* Exported macro ------------------------------------------------------------*/
bogdanm 82:6473597d706e 636 /* Exported functions ------------------------------------------------------- */
bogdanm 82:6473597d706e 637
bogdanm 82:6473597d706e 638 /* Function used to set the RCC clock configuration to the default reset state */
bogdanm 82:6473597d706e 639 void RCC_DeInit(void);
bogdanm 82:6473597d706e 640
bogdanm 82:6473597d706e 641 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
bogdanm 82:6473597d706e 642 void RCC_HSEConfig(uint8_t RCC_HSE);
bogdanm 82:6473597d706e 643 ErrorStatus RCC_WaitForHSEStartUp(void);
bogdanm 82:6473597d706e 644 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
bogdanm 82:6473597d706e 645 void RCC_HSICmd(FunctionalState NewState);
bogdanm 82:6473597d706e 646 void RCC_LSEConfig(uint32_t RCC_LSE);
bogdanm 82:6473597d706e 647 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
bogdanm 82:6473597d706e 648 void RCC_LSICmd(FunctionalState NewState);
bogdanm 82:6473597d706e 649 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
bogdanm 82:6473597d706e 650 void RCC_PLLCmd(FunctionalState NewState);
bogdanm 82:6473597d706e 651 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
bogdanm 82:6473597d706e 652 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
bogdanm 82:6473597d706e 653 #ifdef STM32F303xC
bogdanm 82:6473597d706e 654 void RCC_MCOConfig(uint8_t RCC_MCOSource);
bogdanm 82:6473597d706e 655 #else
bogdanm 82:6473597d706e 656 void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
bogdanm 82:6473597d706e 657 #endif /* STM32F303xC */
bogdanm 82:6473597d706e 658
bogdanm 82:6473597d706e 659 /* System, AHB and APB busses clocks configuration functions ******************/
bogdanm 82:6473597d706e 660 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
bogdanm 82:6473597d706e 661 uint8_t RCC_GetSYSCLKSource(void);
bogdanm 82:6473597d706e 662 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
bogdanm 82:6473597d706e 663 void RCC_PCLK1Config(uint32_t RCC_HCLK);
bogdanm 82:6473597d706e 664 void RCC_PCLK2Config(uint32_t RCC_HCLK);
bogdanm 82:6473597d706e 665 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
bogdanm 82:6473597d706e 666
bogdanm 82:6473597d706e 667 /* Peripheral clocks configuration functions **********************************/
bogdanm 82:6473597d706e 668 void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK);
bogdanm 82:6473597d706e 669 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
bogdanm 82:6473597d706e 670 void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK);
bogdanm 82:6473597d706e 671 void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK);
bogdanm 82:6473597d706e 672 void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
bogdanm 82:6473597d706e 673 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
bogdanm 82:6473597d706e 674 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
bogdanm 82:6473597d706e 675
bogdanm 82:6473597d706e 676 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
bogdanm 82:6473597d706e 677 void RCC_RTCCLKCmd(FunctionalState NewState);
bogdanm 82:6473597d706e 678 void RCC_BackupResetCmd(FunctionalState NewState);
bogdanm 82:6473597d706e 679
bogdanm 82:6473597d706e 680 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
bogdanm 82:6473597d706e 681 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
bogdanm 82:6473597d706e 682 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
bogdanm 82:6473597d706e 683
bogdanm 82:6473597d706e 684 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
bogdanm 82:6473597d706e 685 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
bogdanm 82:6473597d706e 686 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
bogdanm 82:6473597d706e 687
bogdanm 82:6473597d706e 688 /* Interrupts and flags management functions **********************************/
bogdanm 82:6473597d706e 689 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
bogdanm 82:6473597d706e 690 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
bogdanm 82:6473597d706e 691 void RCC_ClearFlag(void);
bogdanm 82:6473597d706e 692 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
bogdanm 82:6473597d706e 693 void RCC_ClearITPendingBit(uint8_t RCC_IT);
bogdanm 82:6473597d706e 694
bogdanm 82:6473597d706e 695 #ifdef __cplusplus
bogdanm 82:6473597d706e 696 }
bogdanm 82:6473597d706e 697 #endif
bogdanm 82:6473597d706e 698
bogdanm 82:6473597d706e 699 #endif /* __STM32F30x_RCC_H */
bogdanm 82:6473597d706e 700
bogdanm 82:6473597d706e 701 /**
bogdanm 82:6473597d706e 702 * @}
bogdanm 82:6473597d706e 703 */
bogdanm 82:6473597d706e 704
bogdanm 82:6473597d706e 705 /**
bogdanm 82:6473597d706e 706 * @}
bogdanm 82:6473597d706e 707 */
bogdanm 82:6473597d706e 708
bogdanm 82:6473597d706e 709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/