雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

Fork of mbed by mbed official

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/edma/fsl_edma_features.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Child:
90:cb3d968589d8
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 82:6473597d706e 6 * are permitted provided that the following conditions are met:
bogdanm 82:6473597d706e 7 *
bogdanm 82:6473597d706e 8 * o Redistributions of source code must retain the above copyright notice, this list
bogdanm 82:6473597d706e 9 * of conditions and the following disclaimer.
bogdanm 82:6473597d706e 10 *
bogdanm 82:6473597d706e 11 * o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 82:6473597d706e 12 * list of conditions and the following disclaimer in the documentation and/or
bogdanm 82:6473597d706e 13 * other materials provided with the distribution.
bogdanm 82:6473597d706e 14 *
bogdanm 82:6473597d706e 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 82:6473597d706e 16 * contributors may be used to endorse or promote products derived from this
bogdanm 82:6473597d706e 17 * software without specific prior written permission.
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 82:6473597d706e 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 82:6473597d706e 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 82:6473597d706e 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 82:6473597d706e 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 82:6473597d706e 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 82:6473597d706e 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 82:6473597d706e 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 82:6473597d706e 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 82:6473597d706e 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 82:6473597d706e 29 */
bogdanm 82:6473597d706e 30 #if !defined(__FSL_DMA_FEATURES_H__)
bogdanm 82:6473597d706e 31 #define __FSL_DMA_FEATURES_H__
bogdanm 82:6473597d706e 32
bogdanm 82:6473597d706e 33 #if defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
bogdanm 82:6473597d706e 34 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
bogdanm 82:6473597d706e 35 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
bogdanm 82:6473597d706e 36 defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
bogdanm 82:6473597d706e 37 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) || defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || \
bogdanm 82:6473597d706e 38 defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || \
bogdanm 82:6473597d706e 39 defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || \
bogdanm 82:6473597d706e 40 defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)
bogdanm 82:6473597d706e 41 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 42 #define FSL_FEATURE_DMA_MODULE_CHANNEL (4)
bogdanm 82:6473597d706e 43 /* @brief Total number of DMA channels on all modules.*/
bogdanm 82:6473597d706e 44 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4)
bogdanm 82:6473597d706e 45 /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
bogdanm 82:6473597d706e 46 #define FSL_FEATURE_DMA_IS_EDMA (1)
bogdanm 82:6473597d706e 47 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 48 #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1)
bogdanm 82:6473597d706e 49 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 50 #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
bogdanm 82:6473597d706e 51 #elif defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
bogdanm 82:6473597d706e 52 defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F256VLH12) || \
bogdanm 82:6473597d706e 53 defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31FN512VLH12) || defined(CPU_MKV31F512VLL12)
bogdanm 82:6473597d706e 54 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 55 #define FSL_FEATURE_DMA_MODULE_CHANNEL (16)
bogdanm 82:6473597d706e 56 /* @brief Total number of DMA channels on all modules.*/
bogdanm 82:6473597d706e 57 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16)
bogdanm 82:6473597d706e 58 /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
bogdanm 82:6473597d706e 59 #define FSL_FEATURE_DMA_IS_EDMA (1)
bogdanm 82:6473597d706e 60 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 61 #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1)
bogdanm 82:6473597d706e 62 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 63 #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
bogdanm 82:6473597d706e 64 #elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || \
bogdanm 82:6473597d706e 65 defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FX512VLQ12) || \
bogdanm 82:6473597d706e 66 defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12)
bogdanm 82:6473597d706e 67 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 68 #define FSL_FEATURE_DMA_MODULE_CHANNEL (16)
bogdanm 82:6473597d706e 69 /* @brief Total number of DMA channels on all modules.*/
bogdanm 82:6473597d706e 70 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 16)
bogdanm 82:6473597d706e 71 /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
bogdanm 82:6473597d706e 72 #define FSL_FEATURE_DMA_IS_EDMA (1)
bogdanm 82:6473597d706e 73 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 74 #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (1)
bogdanm 82:6473597d706e 75 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 76 #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
bogdanm 82:6473597d706e 77 #elif defined(CPU_MK65FN2M0VMF18) || defined(CPU_MK65FX1M0VMF18) || defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18)
bogdanm 82:6473597d706e 78 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 79 #define FSL_FEATURE_DMA_MODULE_CHANNEL (32)
bogdanm 82:6473597d706e 80 /* @brief Total number of DMA channels on all modules.*/
bogdanm 82:6473597d706e 81 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32)
bogdanm 82:6473597d706e 82 /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
bogdanm 82:6473597d706e 83 #define FSL_FEATURE_DMA_IS_EDMA (1)
bogdanm 82:6473597d706e 84 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 85 #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (2)
bogdanm 82:6473597d706e 86 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 87 #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
bogdanm 82:6473597d706e 88 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
bogdanm 82:6473597d706e 89 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
bogdanm 82:6473597d706e 90 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 91 #define FSL_FEATURE_DMA_MODULE_CHANNEL (32)
bogdanm 82:6473597d706e 92 /* @brief Total number of DMA channels on all modules.*/
bogdanm 82:6473597d706e 93 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 32)
bogdanm 82:6473597d706e 94 /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
bogdanm 82:6473597d706e 95 #define FSL_FEATURE_DMA_IS_EDMA (1)
bogdanm 82:6473597d706e 96 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 97 #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (2)
bogdanm 82:6473597d706e 98 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 99 #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
bogdanm 82:6473597d706e 100 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
bogdanm 82:6473597d706e 101 defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
bogdanm 82:6473597d706e 102 defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL25Z32VFM4) || \
bogdanm 82:6473597d706e 103 defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || \
bogdanm 82:6473597d706e 104 defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || \
bogdanm 82:6473597d706e 105 defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || defined(CPU_MKL46Z128VLH4) || \
bogdanm 82:6473597d706e 106 defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || \
bogdanm 82:6473597d706e 107 defined(CPU_MKL46Z256VMC4)
bogdanm 82:6473597d706e 108 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 109 #define FSL_FEATURE_DMA_MODULE_CHANNEL (4)
bogdanm 82:6473597d706e 110 /* @brief Total number of DMA channels on all modules.*/
bogdanm 82:6473597d706e 111 #define FSL_FEATURE_DMA_DMAMUX_CHANNELS (HW_DMA_INSTANCE_COUNT * 4)
bogdanm 82:6473597d706e 112 /* @brief Enhanced Direct Memory Access Controller (registers CR, ES, ERQ, EEI, CEEI, SEEI, CERQ, SERQ, CDNE, SSRT, CERR, CINT, INT, ERR, HRS, DCHPRIn, TCDn if non-zero, otherwise SARn, DARn, DSR_BCRn, DCRn).*/
bogdanm 82:6473597d706e 113 #define FSL_FEATURE_DMA_IS_EDMA (0)
bogdanm 82:6473597d706e 114 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 115 #define FSL_FEATURE_DMA_CHANNEL_GROUP_COUNT (0)
bogdanm 82:6473597d706e 116 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.)*/
bogdanm 82:6473597d706e 117 #define FSL_FEATURE_DMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
bogdanm 82:6473597d706e 118 #else
bogdanm 82:6473597d706e 119 #error "No valid CPU defined!"
bogdanm 82:6473597d706e 120 #endif
bogdanm 82:6473597d706e 121
bogdanm 82:6473597d706e 122 #endif /* __FSL_DMA_FEATURES_H__*/
bogdanm 82:6473597d706e 123 /*******************************************************************************
bogdanm 82:6473597d706e 124 * EOF
bogdanm 82:6473597d706e 125 ******************************************************************************/
bogdanm 82:6473597d706e 126