mbed(SerialHalfDuplex入り)
Fork of mbed by
TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/dspi/fsl_dspi_features.h@82:6473597d706e, 2014-04-07 (annotated)
- Committer:
- bogdanm
- Date:
- Mon Apr 07 18:28:36 2014 +0100
- Revision:
- 82:6473597d706e
- Child:
- 90:cb3d968589d8
Release 82 of the mbed library
Main changes:
- support for K64F
- Revisited Nordic code structure
- Test infrastructure improvements
- various bug fixes
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 82:6473597d706e | 1 | /* |
bogdanm | 82:6473597d706e | 2 | * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. |
bogdanm | 82:6473597d706e | 3 | * All rights reserved. |
bogdanm | 82:6473597d706e | 4 | * |
bogdanm | 82:6473597d706e | 5 | * Redistribution and use in source and binary forms, with or without modification, |
bogdanm | 82:6473597d706e | 6 | * are permitted provided that the following conditions are met: |
bogdanm | 82:6473597d706e | 7 | * |
bogdanm | 82:6473597d706e | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
bogdanm | 82:6473597d706e | 9 | * of conditions and the following disclaimer. |
bogdanm | 82:6473597d706e | 10 | * |
bogdanm | 82:6473597d706e | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
bogdanm | 82:6473597d706e | 12 | * list of conditions and the following disclaimer in the documentation and/or |
bogdanm | 82:6473597d706e | 13 | * other materials provided with the distribution. |
bogdanm | 82:6473597d706e | 14 | * |
bogdanm | 82:6473597d706e | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
bogdanm | 82:6473597d706e | 16 | * contributors may be used to endorse or promote products derived from this |
bogdanm | 82:6473597d706e | 17 | * software without specific prior written permission. |
bogdanm | 82:6473597d706e | 18 | * |
bogdanm | 82:6473597d706e | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
bogdanm | 82:6473597d706e | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
bogdanm | 82:6473597d706e | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 82:6473597d706e | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
bogdanm | 82:6473597d706e | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
bogdanm | 82:6473597d706e | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
bogdanm | 82:6473597d706e | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
bogdanm | 82:6473597d706e | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
bogdanm | 82:6473597d706e | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
bogdanm | 82:6473597d706e | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 82:6473597d706e | 29 | */ |
bogdanm | 82:6473597d706e | 30 | #if !defined(__FSL_DSPI_FEATURES_H__) |
bogdanm | 82:6473597d706e | 31 | #define __FSL_DSPI_FEATURES_H__ |
bogdanm | 82:6473597d706e | 32 | |
bogdanm | 82:6473597d706e | 33 | #if defined(CPU_MK10DN512VLK10) || defined(CPU_MK10DN512VMB10) || defined(CPU_MK10DX128VMP5) || defined(CPU_MK10DN128VMP5) || \ |
bogdanm | 82:6473597d706e | 34 | defined(CPU_MK10DX64VMP5) || defined(CPU_MK10DN64VMP5) || defined(CPU_MK10DX32VMP5) || defined(CPU_MK10DN32VMP5) || \ |
bogdanm | 82:6473597d706e | 35 | defined(CPU_MK10DX128VLH5) || defined(CPU_MK10DN128VLH5) || defined(CPU_MK10DX64VLH5) || defined(CPU_MK10DN64VLH5) || \ |
bogdanm | 82:6473597d706e | 36 | defined(CPU_MK10DX32VLH5) || defined(CPU_MK10DN32VLH5) || defined(CPU_MK10DX128VFT5) || defined(CPU_MK10DN128VFT5) || \ |
bogdanm | 82:6473597d706e | 37 | defined(CPU_MK10DX64VFT5) || defined(CPU_MK10DN64VFT5) || defined(CPU_MK10DX32VFT5) || defined(CPU_MK10DN32VFT5) || \ |
bogdanm | 82:6473597d706e | 38 | defined(CPU_MK10DX128VLF5) || defined(CPU_MK10DN128VLF5) || defined(CPU_MK10DX64VLF5) || defined(CPU_MK10DN64VLF5) || \ |
bogdanm | 82:6473597d706e | 39 | defined(CPU_MK10DX32VLF5) || defined(CPU_MK10DN32VLF5) || defined(CPU_MK10DX64VLH7) || defined(CPU_MK10DX128VLH7) || \ |
bogdanm | 82:6473597d706e | 40 | defined(CPU_MK10DX256VLH7) || defined(CPU_MK10DX64VLK7) || defined(CPU_MK10DX128VLK7) || defined(CPU_MK10DX256VLK7) || \ |
bogdanm | 82:6473597d706e | 41 | defined(CPU_MK10DX64VMB7) || defined(CPU_MK10DX128VMB7) || defined(CPU_MK10DX256VMB7) || defined(CPU_MK10DN512ZVLK10) || \ |
bogdanm | 82:6473597d706e | 42 | defined(CPU_MK10DN512ZVMB10) || defined(CPU_MK20DN512VLK10) || defined(CPU_MK20DN512VMB10) || defined(CPU_MK20DX128VMP5) || \ |
bogdanm | 82:6473597d706e | 43 | defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || defined(CPU_MK20DX32VMP5) || \ |
bogdanm | 82:6473597d706e | 44 | defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || defined(CPU_MK20DX64VLH5) || \ |
bogdanm | 82:6473597d706e | 45 | defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || defined(CPU_MK20DX128VFT5) || \ |
bogdanm | 82:6473597d706e | 46 | defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || defined(CPU_MK20DX32VFT5) || \ |
bogdanm | 82:6473597d706e | 47 | defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || defined(CPU_MK20DX64VLF5) || \ |
bogdanm | 82:6473597d706e | 48 | defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5) || defined(CPU_MK20DX64VLH7) || \ |
bogdanm | 82:6473597d706e | 49 | defined(CPU_MK20DX128VLH7) || defined(CPU_MK20DX256VLH7) || defined(CPU_MK20DX64VLK7) || defined(CPU_MK20DX128VLK7) || \ |
bogdanm | 82:6473597d706e | 50 | defined(CPU_MK20DX256VLK7) || defined(CPU_MK20DX64VMB7) || defined(CPU_MK20DX128VMB7) || defined(CPU_MK20DX256VMB7) || \ |
bogdanm | 82:6473597d706e | 51 | defined(CPU_MK20DN512ZVLK10) || defined(CPU_MK20DX256ZVLK10) || defined(CPU_MK20DN512ZVMB10) || defined(CPU_MK20DX256ZVMB10) || \ |
bogdanm | 82:6473597d706e | 52 | defined(CPU_MK22FX512VLH12) || defined(CPU_MK22FN1M0VLH12) || defined(CPU_MK22FX512VLK12) || defined(CPU_MK22FN1M0VLK12) || \ |
bogdanm | 82:6473597d706e | 53 | defined(CPU_MK30DN512VLK10) || defined(CPU_MK30DN512VMB10) || defined(CPU_MK30DX64VLH7) || defined(CPU_MK30DX128VLH7) || \ |
bogdanm | 82:6473597d706e | 54 | defined(CPU_MK30DX256VLH7) || defined(CPU_MK30DX64VLK7) || defined(CPU_MK30DX128VLK7) || defined(CPU_MK30DX256VLK7) || \ |
bogdanm | 82:6473597d706e | 55 | defined(CPU_MK30DX64VMB7) || defined(CPU_MK30DX128VMB7) || defined(CPU_MK30DX256VMB7) || defined(CPU_MK30DN512ZVLK10) || \ |
bogdanm | 82:6473597d706e | 56 | defined(CPU_MK30DN512ZVMB10) || defined(CPU_MK40DN512VLK10) || defined(CPU_MK40DN512VMB10) || defined(CPU_MK40DX64VLH7) || \ |
bogdanm | 82:6473597d706e | 57 | defined(CPU_MK40DX128VLH7) || defined(CPU_MK40DX256VLH7) || defined(CPU_MK40DX64VLK7) || defined(CPU_MK40DX128VLK7) || \ |
bogdanm | 82:6473597d706e | 58 | defined(CPU_MK40DX256VLK7) || defined(CPU_MK40DX64VMB7) || defined(CPU_MK40DX128VMB7) || defined(CPU_MK40DX256VMB7) || \ |
bogdanm | 82:6473597d706e | 59 | defined(CPU_MK40DN512ZVLK10) || defined(CPU_MK40DN512ZVMB10) || defined(CPU_MK50DX128CLH7) || defined(CPU_MK50DX256CLK10) || \ |
bogdanm | 82:6473597d706e | 60 | defined(CPU_MK50DX128CLK7) || defined(CPU_MK50DX256CLK7) || defined(CPU_MK50DX256CMB10) || defined(CPU_MK50DX128CMB7) || \ |
bogdanm | 82:6473597d706e | 61 | defined(CPU_MK50DX256CMB7) || defined(CPU_MK50DX256ZCLK10) || defined(CPU_MK50DX256ZCMB10) || defined(CPU_MK51DX128CLH7) || \ |
bogdanm | 82:6473597d706e | 62 | defined(CPU_MK51DX256CLK10) || defined(CPU_MK51DX128CLK7) || defined(CPU_MK51DX256CLK7) || defined(CPU_MK51DX256CMB10) || \ |
bogdanm | 82:6473597d706e | 63 | defined(CPU_MK51DX128CMB7) || defined(CPU_MK51DX256CMB7) || defined(CPU_MK51DX256ZCLK10) || defined(CPU_MK51DX256ZCMB10) |
bogdanm | 82:6473597d706e | 64 | /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/ |
bogdanm | 82:6473597d706e | 65 | #define FSL_FEATURE_SPI_IS_DSPI (1) |
bogdanm | 82:6473597d706e | 66 | /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 67 | #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) |
bogdanm | 82:6473597d706e | 68 | /* @brief Receive/transmit FIFO size in number of items.*/ |
bogdanm | 82:6473597d706e | 69 | #define FSL_FEATURE_SPI_FIFO_SIZE (4) |
bogdanm | 82:6473597d706e | 70 | /* @brief Maximum transfer data width in bits.*/ |
bogdanm | 82:6473597d706e | 71 | #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) |
bogdanm | 82:6473597d706e | 72 | /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 73 | #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6) |
bogdanm | 82:6473597d706e | 74 | /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 75 | #define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \ |
bogdanm | 82:6473597d706e | 76 | ((x) == 0 ? (5) : \ |
bogdanm | 82:6473597d706e | 77 | ((x) == 1 ? (3) : (-1))) |
bogdanm | 82:6473597d706e | 78 | /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 79 | #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1) |
bogdanm | 82:6473597d706e | 80 | /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 81 | #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0) |
bogdanm | 82:6473597d706e | 82 | /* @brief Has 16-bit data transfer support.*/ |
bogdanm | 82:6473597d706e | 83 | #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1) |
bogdanm | 82:6473597d706e | 84 | #elif defined(CPU_MK10DN512VLL10) || defined(CPU_MK10DX128VLQ10) || defined(CPU_MK10DX256VLQ10) || defined(CPU_MK10DN512VLQ10) || \ |
bogdanm | 82:6473597d706e | 85 | defined(CPU_MK10DN512VMC10) || defined(CPU_MK10DX128VMD10) || defined(CPU_MK10DX256VMD10) || defined(CPU_MK10DN512VMD10) || \ |
bogdanm | 82:6473597d706e | 86 | defined(CPU_MK10DX128VLL7) || defined(CPU_MK10DX256VLL7) || defined(CPU_MK10DX128VML7) || defined(CPU_MK10DX256VML7) || \ |
bogdanm | 82:6473597d706e | 87 | defined(CPU_MK10FN1M0VLQ12) || defined(CPU_MK10FX512VLQ12) || defined(CPU_MK10FN1M0VMD12) || defined(CPU_MK10FX512VMD12) || \ |
bogdanm | 82:6473597d706e | 88 | defined(CPU_MK10DN512ZVLL10) || defined(CPU_MK10DN512ZVLQ10) || defined(CPU_MK10DX256ZVLQ10) || defined(CPU_MK10DX128ZVLQ10) || \ |
bogdanm | 82:6473597d706e | 89 | defined(CPU_MK10DN512ZVMC10) || defined(CPU_MK10DN512ZVMD10) || defined(CPU_MK10DX256ZVMD10) || defined(CPU_MK10DX128ZVMD10) || \ |
bogdanm | 82:6473597d706e | 90 | defined(CPU_MK20DN512VLL10) || defined(CPU_MK20DX128VLQ10) || defined(CPU_MK20DX256VLQ10) || defined(CPU_MK20DN512VLQ10) || \ |
bogdanm | 82:6473597d706e | 91 | defined(CPU_MK20DX256VMC10) || defined(CPU_MK20DN512VMC10) || defined(CPU_MK20DX128VMD10) || defined(CPU_MK20DX256VMD10) || \ |
bogdanm | 82:6473597d706e | 92 | defined(CPU_MK20DN512VMD10) || defined(CPU_MK20DX128VLL7) || defined(CPU_MK20DX256VLL7) || defined(CPU_MK20DX128VML7) || \ |
bogdanm | 82:6473597d706e | 93 | defined(CPU_MK20DX256VML7) || defined(CPU_MK20FN1M0VLQ12) || defined(CPU_MK20FX512VLQ12) || defined(CPU_MK20FN1M0VMD12) || \ |
bogdanm | 82:6473597d706e | 94 | defined(CPU_MK20FX512VMD12) || defined(CPU_MK20DN512ZVLL10) || defined(CPU_MK20DX256ZVLL10) || defined(CPU_MK20DN512ZVLQ10) || \ |
bogdanm | 82:6473597d706e | 95 | defined(CPU_MK20DX256ZVLQ10) || defined(CPU_MK20DX128ZVLQ10) || defined(CPU_MK20DN512ZVMC10) || defined(CPU_MK20DX256ZVMC10) || \ |
bogdanm | 82:6473597d706e | 96 | defined(CPU_MK20DN512ZVMD10) || defined(CPU_MK20DX256ZVMD10) || defined(CPU_MK20DX128ZVMD10) || defined(CPU_MK21FX512VLQ12) || \ |
bogdanm | 82:6473597d706e | 97 | defined(CPU_MK21FN1M0VLQ12) || defined(CPU_MK21FX512VLQ12WS) || defined(CPU_MK21FN1M0VLQ12WS) || defined(CPU_MK21FX512VMC12) || \ |
bogdanm | 82:6473597d706e | 98 | defined(CPU_MK21FN1M0VMC12) || defined(CPU_MK21FX512VMC12WS) || defined(CPU_MK21FN1M0VMC12WS) || defined(CPU_MK21FX512VMD12) || \ |
bogdanm | 82:6473597d706e | 99 | defined(CPU_MK21FN1M0VMD12) || defined(CPU_MK21FX512VMD12WS) || defined(CPU_MK21FN1M0VMD12WS) || defined(CPU_MK22FX512VLL12) || \ |
bogdanm | 82:6473597d706e | 100 | defined(CPU_MK22FN1M0VLL12) || defined(CPU_MK22FX512VLQ12) || defined(CPU_MK22FN1M0VLQ12) || defined(CPU_MK22FX512VMC12) || \ |
bogdanm | 82:6473597d706e | 101 | defined(CPU_MK22FN1M0VMC12) || defined(CPU_MK22FX512VMD12) || defined(CPU_MK22FN1M0VMD12) || defined(CPU_MK30DN512VLL10) || \ |
bogdanm | 82:6473597d706e | 102 | defined(CPU_MK30DX128VLQ10) || defined(CPU_MK30DX256VLQ10) || defined(CPU_MK30DN512VLQ10) || defined(CPU_MK30DN512VMC10) || \ |
bogdanm | 82:6473597d706e | 103 | defined(CPU_MK30DX128VMD10) || defined(CPU_MK30DX256VMD10) || defined(CPU_MK30DN512VMD10) || defined(CPU_MK30DX128VLL7) || \ |
bogdanm | 82:6473597d706e | 104 | defined(CPU_MK30DX256VLL7) || defined(CPU_MK30DX128VML7) || defined(CPU_MK30DX256VML7) || defined(CPU_MK30DN512ZVLL10) || \ |
bogdanm | 82:6473597d706e | 105 | defined(CPU_MK30DN512ZVLQ10) || defined(CPU_MK30DX256ZVLQ10) || defined(CPU_MK30DX128ZVLQ10) || defined(CPU_MK30DN512ZVMC10) || \ |
bogdanm | 82:6473597d706e | 106 | defined(CPU_MK30DN512ZVMD10) || defined(CPU_MK30DX256ZVMD10) || defined(CPU_MK30DX128ZVMD10) || defined(CPU_MK40DN512VLL10) || \ |
bogdanm | 82:6473597d706e | 107 | defined(CPU_MK40DX128VLQ10) || defined(CPU_MK40DX256VLQ10) || defined(CPU_MK40DN512VLQ10) || defined(CPU_MK40DN512VMC10) || \ |
bogdanm | 82:6473597d706e | 108 | defined(CPU_MK40DX128VMD10) || defined(CPU_MK40DX256VMD10) || defined(CPU_MK40DN512VMD10) || defined(CPU_MK40DX128VLL7) || \ |
bogdanm | 82:6473597d706e | 109 | defined(CPU_MK40DX256VLL7) || defined(CPU_MK40DX128VML7) || defined(CPU_MK40DX256VML7) || defined(CPU_MK40DN512ZVLL10) || \ |
bogdanm | 82:6473597d706e | 110 | defined(CPU_MK40DN512ZVLQ10) || defined(CPU_MK40DX256ZVLQ10) || defined(CPU_MK40DX128ZVLQ10) || defined(CPU_MK40DN512ZVMC10) || \ |
bogdanm | 82:6473597d706e | 111 | defined(CPU_MK40DN512ZVMD10) || defined(CPU_MK40DX256ZVMD10) || defined(CPU_MK40DX128ZVMD10) || defined(CPU_MK50DX256CLL10) || \ |
bogdanm | 82:6473597d706e | 112 | defined(CPU_MK50DN512CLL10) || defined(CPU_MK50DN512CLQ10) || defined(CPU_MK50DX256CMC10) || defined(CPU_MK50DN512CMC10) || \ |
bogdanm | 82:6473597d706e | 113 | defined(CPU_MK50DN512CMD10) || defined(CPU_MK50DX256CMD10) || defined(CPU_MK50DX256CLL7) || defined(CPU_MK50DX256CML7) || \ |
bogdanm | 82:6473597d706e | 114 | defined(CPU_MK50DN512ZCLL10) || defined(CPU_MK50DX256ZCLL10) || defined(CPU_MK50DN512ZCLQ10) || defined(CPU_MK50DN512ZCMC10) || \ |
bogdanm | 82:6473597d706e | 115 | defined(CPU_MK50DX256ZCMC10) || defined(CPU_MK50DN512ZCMD10) || defined(CPU_MK51DX256CLL10) || defined(CPU_MK51DN512CLL10) || \ |
bogdanm | 82:6473597d706e | 116 | defined(CPU_MK51DN256CLQ10) || defined(CPU_MK51DN512CLQ10) || defined(CPU_MK51DX256CMC10) || defined(CPU_MK51DN512CMC10) || \ |
bogdanm | 82:6473597d706e | 117 | defined(CPU_MK51DN256CMD10) || defined(CPU_MK51DN512CMD10) || defined(CPU_MK51DX256CLL7) || defined(CPU_MK51DX256CML7) || \ |
bogdanm | 82:6473597d706e | 118 | defined(CPU_MK51DN512ZCLL10) || defined(CPU_MK51DX256ZCLL10) || defined(CPU_MK51DN512ZCLQ10) || defined(CPU_MK51DN256ZCLQ10) || \ |
bogdanm | 82:6473597d706e | 119 | defined(CPU_MK51DN512ZCMC10) || defined(CPU_MK51DX256ZCMC10) || defined(CPU_MK51DN512ZCMD10) || defined(CPU_MK51DN256ZCMD10) || \ |
bogdanm | 82:6473597d706e | 120 | defined(CPU_MK52DN512CLQ10) || defined(CPU_MK52DN512CMD10) || defined(CPU_MK52DN512ZCLQ10) || defined(CPU_MK52DN512ZCMD10) || \ |
bogdanm | 82:6473597d706e | 121 | defined(CPU_MK53DN512CLQ10) || defined(CPU_MK53DX256CLQ10) || defined(CPU_MK53DN512CMD10) || defined(CPU_MK53DX256CMD10) || \ |
bogdanm | 82:6473597d706e | 122 | defined(CPU_MK53DN512ZCLQ10) || defined(CPU_MK53DX256ZCLQ10) || defined(CPU_MK53DN512ZCMD10) || defined(CPU_MK53DX256ZCMD10) || \ |
bogdanm | 82:6473597d706e | 123 | defined(CPU_MK60DN256VLL10) || defined(CPU_MK60DX256VLL10) || defined(CPU_MK60DN512VLL10) || defined(CPU_MK60DN256VLQ10) || \ |
bogdanm | 82:6473597d706e | 124 | defined(CPU_MK60DX256VLQ10) || defined(CPU_MK60DN512VLQ10) || defined(CPU_MK60DN256VMC10) || defined(CPU_MK60DX256VMC10) || \ |
bogdanm | 82:6473597d706e | 125 | defined(CPU_MK60DN512VMC10) || defined(CPU_MK60DN256VMD10) || defined(CPU_MK60DX256VMD10) || defined(CPU_MK60DN512VMD10) || \ |
bogdanm | 82:6473597d706e | 126 | defined(CPU_MK60FN1M0VLQ12) || defined(CPU_MK60FX512VLQ12) || defined(CPU_MK60FN1M0VLQ15) || defined(CPU_MK60FX512VLQ15) || \ |
bogdanm | 82:6473597d706e | 127 | defined(CPU_MK60FN1M0VMD12) || defined(CPU_MK60FX512VMD12) || defined(CPU_MK60FN1M0VMD15) || defined(CPU_MK60FX512VMD15) || \ |
bogdanm | 82:6473597d706e | 128 | defined(CPU_MK60DN512ZVLL10) || defined(CPU_MK60DX256ZVLL10) || defined(CPU_MK60DN256ZVLL10) || defined(CPU_MK60DN512ZVLQ10) || \ |
bogdanm | 82:6473597d706e | 129 | defined(CPU_MK60DX256ZVLQ10) || defined(CPU_MK60DN256ZVLQ10) || defined(CPU_MK60DN512ZVMC10) || defined(CPU_MK60DX256ZVMC10) || \ |
bogdanm | 82:6473597d706e | 130 | defined(CPU_MK60DN256ZVMC10) || defined(CPU_MK60DN512ZVMD10) || defined(CPU_MK60DX256ZVMD10) || defined(CPU_MK60DN256ZVMD10) || \ |
bogdanm | 82:6473597d706e | 131 | defined(CPU_MK61FN1M0VMD12) || defined(CPU_MK61FX512VMD12) || defined(CPU_MK61FN1M0VMD15) || defined(CPU_MK61FX512VMD15) || \ |
bogdanm | 82:6473597d706e | 132 | defined(CPU_MK61FN1M0VMD12WS) || defined(CPU_MK61FX512VMD12WS) || defined(CPU_MK61FN1M0VMD15WS) || defined(CPU_MK61FX512VMD15WS) || \ |
bogdanm | 82:6473597d706e | 133 | defined(CPU_MK61FN1M0VMF12) || defined(CPU_MK61FX512VMF12) || defined(CPU_MK61FN1M0VMF15) || defined(CPU_MK61FX512VMF15) || \ |
bogdanm | 82:6473597d706e | 134 | defined(CPU_MK61FN1M0VMJ12) || defined(CPU_MK61FX512VMJ12) || defined(CPU_MK61FN1M0VMJ15) || defined(CPU_MK61FX512VMJ15) || \ |
bogdanm | 82:6473597d706e | 135 | defined(CPU_MK61FN1M0VMJ12WS) || defined(CPU_MK61FX512VMJ12WS) || defined(CPU_MK61FN1M0VMJ15WS) || defined(CPU_MK61FX512VMJ15WS) || \ |
bogdanm | 82:6473597d706e | 136 | defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK63FN1M0VMD12WS) || defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) || \ |
bogdanm | 82:6473597d706e | 137 | defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \ |
bogdanm | 82:6473597d706e | 138 | defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15) || \ |
bogdanm | 82:6473597d706e | 139 | defined(CPU_MK70FN1M0VMJ12WS) || defined(CPU_MK70FX512VMJ12WS) || defined(CPU_MK70FN1M0VMJ15WS) || defined(CPU_MK70FX512VMJ15WS) |
bogdanm | 82:6473597d706e | 140 | /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/ |
bogdanm | 82:6473597d706e | 141 | #define FSL_FEATURE_SPI_IS_DSPI (1) |
bogdanm | 82:6473597d706e | 142 | /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 143 | #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) |
bogdanm | 82:6473597d706e | 144 | /* @brief Receive/transmit FIFO size in number of items.*/ |
bogdanm | 82:6473597d706e | 145 | #if defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) |
bogdanm | 82:6473597d706e | 146 | #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ |
bogdanm | 82:6473597d706e | 147 | ((x) == 0 ? (4) : \ |
bogdanm | 82:6473597d706e | 148 | ((x) == 1 ? (1) : \ |
bogdanm | 82:6473597d706e | 149 | ((x) == 2 ? (1) : (-1)))) |
bogdanm | 82:6473597d706e | 150 | #else |
bogdanm | 82:6473597d706e | 151 | #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ |
bogdanm | 82:6473597d706e | 152 | ((x) == 0 ? (4) : \ |
bogdanm | 82:6473597d706e | 153 | ((x) == 1 ? (4) : \ |
bogdanm | 82:6473597d706e | 154 | ((x) == 2 ? (4) : (-1)))) |
bogdanm | 82:6473597d706e | 155 | #endif |
bogdanm | 82:6473597d706e | 156 | /* @brief Maximum transfer data width in bits.*/ |
bogdanm | 82:6473597d706e | 157 | #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) |
bogdanm | 82:6473597d706e | 158 | /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 159 | #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6) |
bogdanm | 82:6473597d706e | 160 | /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 161 | #define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \ |
bogdanm | 82:6473597d706e | 162 | ((x) == 0 ? (6) : \ |
bogdanm | 82:6473597d706e | 163 | ((x) == 1 ? (4) : \ |
bogdanm | 82:6473597d706e | 164 | ((x) == 2 ? (1) : (-1)))) |
bogdanm | 82:6473597d706e | 165 | /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 166 | #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1) |
bogdanm | 82:6473597d706e | 167 | /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 168 | #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0) |
bogdanm | 82:6473597d706e | 169 | /* @brief Has 16-bit data transfer support.*/ |
bogdanm | 82:6473597d706e | 170 | #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1) |
bogdanm | 82:6473597d706e | 171 | #elif defined(CPU_MK10DX128VFM5) || defined(CPU_MK10DN128VFM5) || defined(CPU_MK10DX64VFM5) || defined(CPU_MK10DN64VFM5) || \ |
bogdanm | 82:6473597d706e | 172 | defined(CPU_MK10DX32VFM5) || defined(CPU_MK10DN32VFM5) || defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || \ |
bogdanm | 82:6473597d706e | 173 | defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5) |
bogdanm | 82:6473597d706e | 174 | /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/ |
bogdanm | 82:6473597d706e | 175 | #define FSL_FEATURE_SPI_IS_DSPI (1) |
bogdanm | 82:6473597d706e | 176 | /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 177 | #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) |
bogdanm | 82:6473597d706e | 178 | /* @brief Receive/transmit FIFO size in number of items.*/ |
bogdanm | 82:6473597d706e | 179 | #define FSL_FEATURE_SPI_FIFO_SIZE (4) |
bogdanm | 82:6473597d706e | 180 | /* @brief Maximum transfer data width in bits.*/ |
bogdanm | 82:6473597d706e | 181 | #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) |
bogdanm | 82:6473597d706e | 182 | /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 183 | #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6) |
bogdanm | 82:6473597d706e | 184 | /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 185 | #define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (4) |
bogdanm | 82:6473597d706e | 186 | /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 187 | #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1) |
bogdanm | 82:6473597d706e | 188 | /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 189 | #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0) |
bogdanm | 82:6473597d706e | 190 | /* @brief Has 16-bit data transfer support.*/ |
bogdanm | 82:6473597d706e | 191 | #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1) |
bogdanm | 82:6473597d706e | 192 | #elif defined(CPU_MK11DX128VLK5) || defined(CPU_MK11DX256VLK5) || defined(CPU_MK11DN512VLK5) || defined(CPU_MK11DX128VLK5WS) || \ |
bogdanm | 82:6473597d706e | 193 | defined(CPU_MK11DX256VLK5WS) || defined(CPU_MK11DN512VLK5WS) || defined(CPU_MK11DX128VMC5) || defined(CPU_MK11DX256VMC5) || \ |
bogdanm | 82:6473597d706e | 194 | defined(CPU_MK11DN512VMC5) || defined(CPU_MK11DX128VMC5WS) || defined(CPU_MK11DX256VMC5WS) || defined(CPU_MK11DN512VMC5WS) || \ |
bogdanm | 82:6473597d706e | 195 | defined(CPU_MK12DX128VLH5) || defined(CPU_MK12DX256VLH5) || defined(CPU_MK12DN512VLH5) || defined(CPU_MK12DX128VLK5) || \ |
bogdanm | 82:6473597d706e | 196 | defined(CPU_MK12DX256VLK5) || defined(CPU_MK12DN512VLK5) || defined(CPU_MK12DX128VMC5) || defined(CPU_MK12DX256VMC5) || \ |
bogdanm | 82:6473597d706e | 197 | defined(CPU_MK12DN512VMC5) || defined(CPU_MK12DX128VLF5) || defined(CPU_MK12DX256VLF5) || defined(CPU_MK21DX128VLK5) || \ |
bogdanm | 82:6473597d706e | 198 | defined(CPU_MK21DX256VLK5) || defined(CPU_MK21DN512VLK5) || defined(CPU_MK21DX128VLK5WS) || defined(CPU_MK21DX256VLK5WS) || \ |
bogdanm | 82:6473597d706e | 199 | defined(CPU_MK21DN512VLK5WS) || defined(CPU_MK21DX128VMC5) || defined(CPU_MK21DX256VMC5) || defined(CPU_MK21DN512VMC5) || \ |
bogdanm | 82:6473597d706e | 200 | defined(CPU_MK21DX128VMC5WS) || defined(CPU_MK21DX256VMC5WS) || defined(CPU_MK21DN512VMC5WS) || defined(CPU_MK22DX128VLH5) || \ |
bogdanm | 82:6473597d706e | 201 | defined(CPU_MK22DX256VLH5) || defined(CPU_MK22DN512VLH5) || defined(CPU_MK22DX128VLK5) || defined(CPU_MK22DX256VLK5) || \ |
bogdanm | 82:6473597d706e | 202 | defined(CPU_MK22DN512VLK5) || defined(CPU_MK22DX128VMC5) || defined(CPU_MK22DX256VMC5) || defined(CPU_MK22DN512VMC5) || \ |
bogdanm | 82:6473597d706e | 203 | defined(CPU_MK22DX128VLF5) || defined(CPU_MK22DX256VLF5) |
bogdanm | 82:6473597d706e | 204 | /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/ |
bogdanm | 82:6473597d706e | 205 | #define FSL_FEATURE_SPI_IS_DSPI (1) |
bogdanm | 82:6473597d706e | 206 | /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 207 | #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) |
bogdanm | 82:6473597d706e | 208 | /* @brief Receive/transmit FIFO size in number of items.*/ |
bogdanm | 82:6473597d706e | 209 | #define FSL_FEATURE_SPI_FIFO_SIZE (4) |
bogdanm | 82:6473597d706e | 210 | /* @brief Maximum transfer data width in bits.*/ |
bogdanm | 82:6473597d706e | 211 | #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) |
bogdanm | 82:6473597d706e | 212 | /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 213 | #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (5) |
bogdanm | 82:6473597d706e | 214 | /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 215 | #define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \ |
bogdanm | 82:6473597d706e | 216 | ((x) == 0 ? (5) : \ |
bogdanm | 82:6473597d706e | 217 | ((x) == 1 ? (3) : (-1))) |
bogdanm | 82:6473597d706e | 218 | /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 219 | #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0) |
bogdanm | 82:6473597d706e | 220 | /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 221 | #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0) |
bogdanm | 82:6473597d706e | 222 | /* @brief Has 16-bit data transfer support.*/ |
bogdanm | 82:6473597d706e | 223 | #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1) |
bogdanm | 82:6473597d706e | 224 | #elif defined(CPU_MK22FN512VDC12) |
bogdanm | 82:6473597d706e | 225 | /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/ |
bogdanm | 82:6473597d706e | 226 | #define FSL_FEATURE_SPI_IS_DSPI (1) |
bogdanm | 82:6473597d706e | 227 | /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 228 | #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) |
bogdanm | 82:6473597d706e | 229 | /* @brief Receive/transmit FIFO size in number of items.*/ |
bogdanm | 82:6473597d706e | 230 | #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ |
bogdanm | 82:6473597d706e | 231 | ((x) == 0 ? (4) : \ |
bogdanm | 82:6473597d706e | 232 | ((x) == 1 ? (1) : (-1))) |
bogdanm | 82:6473597d706e | 233 | /* @brief Maximum transfer data width in bits.*/ |
bogdanm | 82:6473597d706e | 234 | #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) |
bogdanm | 82:6473597d706e | 235 | /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 236 | #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6) |
bogdanm | 82:6473597d706e | 237 | /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 238 | #define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0) |
bogdanm | 82:6473597d706e | 239 | /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 240 | #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1) |
bogdanm | 82:6473597d706e | 241 | /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 242 | #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0) |
bogdanm | 82:6473597d706e | 243 | /* @brief Has 16-bit data transfer support.*/ |
bogdanm | 82:6473597d706e | 244 | #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1) |
bogdanm | 82:6473597d706e | 245 | #elif defined(CPU_MK22FN512VDC12) |
bogdanm | 82:6473597d706e | 246 | /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/ |
bogdanm | 82:6473597d706e | 247 | #define FSL_FEATURE_SPI_IS_DSPI (1) |
bogdanm | 82:6473597d706e | 248 | /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 249 | #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) |
bogdanm | 82:6473597d706e | 250 | /* @brief Receive/transmit FIFO size in number of items.*/ |
bogdanm | 82:6473597d706e | 251 | #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ |
bogdanm | 82:6473597d706e | 252 | ((x) == 0 ? (4) : \ |
bogdanm | 82:6473597d706e | 253 | ((x) == 1 ? (1) : (-1))) |
bogdanm | 82:6473597d706e | 254 | /* @brief Maximum transfer data width in bits.*/ |
bogdanm | 82:6473597d706e | 255 | #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) |
bogdanm | 82:6473597d706e | 256 | /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 257 | #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (6) |
bogdanm | 82:6473597d706e | 258 | /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 259 | #define FSL_FEATURE_SPI_CHIP_SELECT_COUNTn(x) \ |
bogdanm | 82:6473597d706e | 260 | ((x) == 0 ? (5) : \ |
bogdanm | 82:6473597d706e | 261 | ((x) == 1 ? (3) : (-1))) |
bogdanm | 82:6473597d706e | 262 | /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 263 | #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (1) |
bogdanm | 82:6473597d706e | 264 | /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 265 | #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (0) |
bogdanm | 82:6473597d706e | 266 | /* @brief Has 16-bit data transfer support.*/ |
bogdanm | 82:6473597d706e | 267 | #define FSL_FEATURE_SPI_FEATURE_16BIT_TRANSFERS (1) |
bogdanm | 82:6473597d706e | 268 | #elif defined(CPU_MKE02Z64VLC2) || defined(CPU_MKE02Z32VLC2) || defined(CPU_MKE02Z16VLC2) || defined(CPU_MKE02Z64VLD2) || \ |
bogdanm | 82:6473597d706e | 269 | defined(CPU_MKE02Z32VLD2) || defined(CPU_MKE02Z16VLD2) || defined(CPU_MKE02Z64VLH2) || defined(CPU_MKE02Z64VQH2) || \ |
bogdanm | 82:6473597d706e | 270 | defined(CPU_MKE02Z32VLH2) || defined(CPU_MKE02Z32VQH2) || defined(CPU_MKE04Z8VFK4) || defined(CPU_MKE04Z8VTG4) || \ |
bogdanm | 82:6473597d706e | 271 | defined(CPU_MKE04Z8VWJ4) || defined(CPU_MKL02Z32CAF4) || defined(CPU_MKL02Z8VFG4) || defined(CPU_MKL02Z16VFG4) || \ |
bogdanm | 82:6473597d706e | 272 | defined(CPU_MKL02Z32VFG4) || defined(CPU_MKL02Z16VFK4) || defined(CPU_MKL02Z32VFK4) || defined(CPU_MKL02Z16VFM4) || \ |
bogdanm | 82:6473597d706e | 273 | defined(CPU_MKL02Z32VFM4) |
bogdanm | 82:6473597d706e | 274 | /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/ |
bogdanm | 82:6473597d706e | 275 | #define FSL_FEATURE_SPI_IS_DSPI (0) |
bogdanm | 82:6473597d706e | 276 | /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 277 | #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (0) |
bogdanm | 82:6473597d706e | 278 | /* @brief Receive/transmit FIFO size in number of items.*/ |
bogdanm | 82:6473597d706e | 279 | #define FSL_FEATURE_SPI_FIFO_SIZE (1) |
bogdanm | 82:6473597d706e | 280 | /* @brief Maximum transfer data width in bits.*/ |
bogdanm | 82:6473597d706e | 281 | #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8) |
bogdanm | 82:6473597d706e | 282 | /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 283 | #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1) |
bogdanm | 82:6473597d706e | 284 | /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 285 | #define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0) |
bogdanm | 82:6473597d706e | 286 | /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 287 | #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0) |
bogdanm | 82:6473597d706e | 288 | /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 289 | #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) |
bogdanm | 82:6473597d706e | 290 | /* @brief Has 16-bit data transfer support.*/ |
bogdanm | 82:6473597d706e | 291 | #define FSL_FEATURE_SPI_16BIT_TRANSFERS (0) |
bogdanm | 82:6473597d706e | 292 | #elif defined(CPU_MKL04Z8VFK4) || defined(CPU_MKL04Z16VFK4) || defined(CPU_MKL04Z32VFK4) || defined(CPU_MKL04Z8VLC4) || \ |
bogdanm | 82:6473597d706e | 293 | defined(CPU_MKL04Z16VLC4) || defined(CPU_MKL04Z32VLC4) || defined(CPU_MKL04Z8VFM4) || defined(CPU_MKL04Z16VFM4) || \ |
bogdanm | 82:6473597d706e | 294 | defined(CPU_MKL04Z32VFM4) || defined(CPU_MKL04Z16VLF4) || defined(CPU_MKL04Z32VLF4) || defined(CPU_MKL05Z8VFK4) || \ |
bogdanm | 82:6473597d706e | 295 | defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || defined(CPU_MKL05Z16VLC4) || \ |
bogdanm | 82:6473597d706e | 296 | defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || defined(CPU_MKL05Z32VFM4) || \ |
bogdanm | 82:6473597d706e | 297 | defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4) || defined(CPU_MKL14Z32VFM4) || defined(CPU_MKL14Z64VFM4) || \ |
bogdanm | 82:6473597d706e | 298 | defined(CPU_MKL14Z32VFT4) || defined(CPU_MKL14Z64VFT4) || defined(CPU_MKL14Z32VLH4) || defined(CPU_MKL14Z64VLH4) || \ |
bogdanm | 82:6473597d706e | 299 | defined(CPU_MKL14Z32VLK4) || defined(CPU_MKL14Z64VLK4) || defined(CPU_MKL15Z32VFM4) || defined(CPU_MKL15Z64VFM4) || \ |
bogdanm | 82:6473597d706e | 300 | defined(CPU_MKL15Z128VFM4) || defined(CPU_MKL15Z32VFT4) || defined(CPU_MKL15Z64VFT4) || defined(CPU_MKL15Z128VFT4) || \ |
bogdanm | 82:6473597d706e | 301 | defined(CPU_MKL15Z32VLH4) || defined(CPU_MKL15Z64VLH4) || defined(CPU_MKL15Z128VLH4) || defined(CPU_MKL15Z32VLK4) || \ |
bogdanm | 82:6473597d706e | 302 | defined(CPU_MKL15Z64VLK4) || defined(CPU_MKL15Z128VLK4) || defined(CPU_MKL24Z32VFM4) || defined(CPU_MKL24Z64VFM4) || \ |
bogdanm | 82:6473597d706e | 303 | defined(CPU_MKL24Z32VFT4) || defined(CPU_MKL24Z64VFT4) || defined(CPU_MKL24Z32VLH4) || defined(CPU_MKL24Z64VLH4) || \ |
bogdanm | 82:6473597d706e | 304 | defined(CPU_MKL24Z32VLK4) || defined(CPU_MKL24Z64VLK4) || defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || \ |
bogdanm | 82:6473597d706e | 305 | defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || \ |
bogdanm | 82:6473597d706e | 306 | defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || \ |
bogdanm | 82:6473597d706e | 307 | defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) |
bogdanm | 82:6473597d706e | 308 | /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/ |
bogdanm | 82:6473597d706e | 309 | #define FSL_FEATURE_SPI_IS_DSPI (0) |
bogdanm | 82:6473597d706e | 310 | /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 311 | #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) |
bogdanm | 82:6473597d706e | 312 | /* @brief Receive/transmit FIFO size in number of items.*/ |
bogdanm | 82:6473597d706e | 313 | #define FSL_FEATURE_SPI_FIFO_SIZE (1) |
bogdanm | 82:6473597d706e | 314 | /* @brief Maximum transfer data width in bits.*/ |
bogdanm | 82:6473597d706e | 315 | #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (8) |
bogdanm | 82:6473597d706e | 316 | /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 317 | #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1) |
bogdanm | 82:6473597d706e | 318 | /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 319 | #define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0) |
bogdanm | 82:6473597d706e | 320 | /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 321 | #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0) |
bogdanm | 82:6473597d706e | 322 | /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 323 | #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) |
bogdanm | 82:6473597d706e | 324 | /* @brief Has 16-bit data transfer support.*/ |
bogdanm | 82:6473597d706e | 325 | #define FSL_FEATURE_SPI_16BIT_TRANSFERS (0) |
bogdanm | 82:6473597d706e | 326 | #elif defined(CPU_MKL16Z32VFM4) || defined(CPU_MKL16Z64VFM4) || defined(CPU_MKL16Z128VFM4) || defined(CPU_MKL16Z32VFT4) || \ |
bogdanm | 82:6473597d706e | 327 | defined(CPU_MKL16Z64VFT4) || defined(CPU_MKL16Z128VFT4) || defined(CPU_MKL16Z32VLH4) || defined(CPU_MKL16Z64VLH4) || \ |
bogdanm | 82:6473597d706e | 328 | defined(CPU_MKL16Z128VLH4) || defined(CPU_MKL16Z256VLH4) || defined(CPU_MKL16Z256VLK4) || defined(CPU_MKL26Z32VFM4) || \ |
bogdanm | 82:6473597d706e | 329 | defined(CPU_MKL26Z64VFM4) || defined(CPU_MKL26Z128VFM4) || defined(CPU_MKL26Z32VFT4) || defined(CPU_MKL26Z64VFT4) || \ |
bogdanm | 82:6473597d706e | 330 | defined(CPU_MKL26Z128VFT4) || defined(CPU_MKL26Z32VLH4) || defined(CPU_MKL26Z64VLH4) || defined(CPU_MKL26Z128VLH4) || \ |
bogdanm | 82:6473597d706e | 331 | defined(CPU_MKL26Z256VLH4) || defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || \ |
bogdanm | 82:6473597d706e | 332 | defined(CPU_MKL26Z128VMC4) || defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL34Z64VLH4) || defined(CPU_MKL34Z64VLL4) || \ |
bogdanm | 82:6473597d706e | 333 | defined(CPU_MKL36Z64VLH4) || defined(CPU_MKL36Z128VLH4) || defined(CPU_MKL36Z256VLH4) || defined(CPU_MKL36Z64VLL4) || \ |
bogdanm | 82:6473597d706e | 334 | defined(CPU_MKL36Z128VLL4) || defined(CPU_MKL36Z256VLL4) || defined(CPU_MKL36Z128VMC4) || defined(CPU_MKL36Z256VMC4) || \ |
bogdanm | 82:6473597d706e | 335 | defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || defined(CPU_MKL46Z256VLL4) || \ |
bogdanm | 82:6473597d706e | 336 | defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4) |
bogdanm | 82:6473597d706e | 337 | /* @brief Deserial serial peripheral interface (registers MCR, TCR, CTARn, CTARn_SLAVE, SR, RSER, PUSHR, PUSHR_SLAVE, POPR, TXFRn, RXFRn if non-zero, otherwise C1, S, C2, BR, D, M).*/ |
bogdanm | 82:6473597d706e | 338 | #define FSL_FEATURE_SPI_IS_DSPI (0) |
bogdanm | 82:6473597d706e | 339 | /* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 340 | #define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1) |
bogdanm | 82:6473597d706e | 341 | /* @brief Receive/transmit FIFO size in number of items.*/ |
bogdanm | 82:6473597d706e | 342 | #define FSL_FEATURE_SPI_FIFO_SIZEn(x) \ |
bogdanm | 82:6473597d706e | 343 | ((x) == 0 ? (1) : \ |
bogdanm | 82:6473597d706e | 344 | ((x) == 1 ? (8) : (-1))) |
bogdanm | 82:6473597d706e | 345 | /* @brief Maximum transfer data width in bits.*/ |
bogdanm | 82:6473597d706e | 346 | #define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16) |
bogdanm | 82:6473597d706e | 347 | /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS] on DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 348 | #define FSL_FEATURE_SPI_MAX_CHIP_SELECT_COUNT (1) |
bogdanm | 82:6473597d706e | 349 | /* @brief Number of chip select pins. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 350 | #define FSL_FEATURE_SPI_CHIP_SELECT_COUNT (0) |
bogdanm | 82:6473597d706e | 351 | /* @brief Has chip select strobe capability on the PCS5 pin. (Only valid for DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 352 | #define FSL_FEATURE_SPI_HAS_CHIP_SELECT_STROBE (0) |
bogdanm | 82:6473597d706e | 353 | /* @brief The data register name has postfix (L as low and H as high). (Only valid for non-DSPI modules.)*/ |
bogdanm | 82:6473597d706e | 354 | #define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1) |
bogdanm | 82:6473597d706e | 355 | /* @brief Has 16-bit data transfer support.*/ |
bogdanm | 82:6473597d706e | 356 | #define FSL_FEATURE_SPI_16BIT_TRANSFERS (1) |
bogdanm | 82:6473597d706e | 357 | #else |
bogdanm | 82:6473597d706e | 358 | #error "No valid CPU defined!" |
bogdanm | 82:6473597d706e | 359 | #endif |
bogdanm | 82:6473597d706e | 360 | |
bogdanm | 82:6473597d706e | 361 | #endif /* __FSL_DSPI_FEATURES_H__*/ |
bogdanm | 82:6473597d706e | 362 | /******************************************************************************* |
bogdanm | 82:6473597d706e | 363 | * EOF |
bogdanm | 82:6473597d706e | 364 | ******************************************************************************/ |
bogdanm | 82:6473597d706e | 365 |