雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_sim.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_SIM_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_SIM_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 SIM
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * System Integration Module
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_SIM_SOPT1 - System Options Register 1
bogdanm 82:6473597d706e 33 * - HW_SIM_SOPT1CFG - SOPT1 Configuration Register
bogdanm 82:6473597d706e 34 * - HW_SIM_SOPT2 - System Options Register 2
bogdanm 82:6473597d706e 35 * - HW_SIM_SOPT4 - System Options Register 4
bogdanm 82:6473597d706e 36 * - HW_SIM_SOPT5 - System Options Register 5
bogdanm 82:6473597d706e 37 * - HW_SIM_SOPT7 - System Options Register 7
bogdanm 82:6473597d706e 38 * - HW_SIM_SDID - System Device Identification Register
bogdanm 82:6473597d706e 39 * - HW_SIM_SCGC1 - System Clock Gating Control Register 1
bogdanm 82:6473597d706e 40 * - HW_SIM_SCGC2 - System Clock Gating Control Register 2
bogdanm 82:6473597d706e 41 * - HW_SIM_SCGC3 - System Clock Gating Control Register 3
bogdanm 82:6473597d706e 42 * - HW_SIM_SCGC4 - System Clock Gating Control Register 4
bogdanm 82:6473597d706e 43 * - HW_SIM_SCGC5 - System Clock Gating Control Register 5
bogdanm 82:6473597d706e 44 * - HW_SIM_SCGC6 - System Clock Gating Control Register 6
bogdanm 82:6473597d706e 45 * - HW_SIM_SCGC7 - System Clock Gating Control Register 7
bogdanm 82:6473597d706e 46 * - HW_SIM_CLKDIV1 - System Clock Divider Register 1
bogdanm 82:6473597d706e 47 * - HW_SIM_CLKDIV2 - System Clock Divider Register 2
bogdanm 82:6473597d706e 48 * - HW_SIM_FCFG1 - Flash Configuration Register 1
bogdanm 82:6473597d706e 49 * - HW_SIM_FCFG2 - Flash Configuration Register 2
bogdanm 82:6473597d706e 50 * - HW_SIM_UIDH - Unique Identification Register High
bogdanm 82:6473597d706e 51 * - HW_SIM_UIDMH - Unique Identification Register Mid-High
bogdanm 82:6473597d706e 52 * - HW_SIM_UIDML - Unique Identification Register Mid Low
bogdanm 82:6473597d706e 53 * - HW_SIM_UIDL - Unique Identification Register Low
bogdanm 82:6473597d706e 54 *
bogdanm 82:6473597d706e 55 * - hw_sim_t - Struct containing all module registers.
bogdanm 82:6473597d706e 56 */
bogdanm 82:6473597d706e 57
bogdanm 82:6473597d706e 58 //! @name Module base addresses
bogdanm 82:6473597d706e 59 //@{
bogdanm 82:6473597d706e 60 #ifndef REGS_SIM_BASE
bogdanm 82:6473597d706e 61 #define HW_SIM_INSTANCE_COUNT (1U) //!< Number of instances of the SIM module.
bogdanm 82:6473597d706e 62 #define REGS_SIM_BASE (0x40047000U) //!< Base address for SIM.
bogdanm 82:6473597d706e 63 #endif
bogdanm 82:6473597d706e 64 //@}
bogdanm 82:6473597d706e 65
bogdanm 82:6473597d706e 66 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 67 // HW_SIM_SOPT1 - System Options Register 1
bogdanm 82:6473597d706e 68 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 69
bogdanm 82:6473597d706e 70 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 71 /*!
bogdanm 82:6473597d706e 72 * @brief HW_SIM_SOPT1 - System Options Register 1 (RW)
bogdanm 82:6473597d706e 73 *
bogdanm 82:6473597d706e 74 * Reset value: 0x80000000U
bogdanm 82:6473597d706e 75 *
bogdanm 82:6473597d706e 76 * The SOPT1 register is only reset on POR or LVD.
bogdanm 82:6473597d706e 77 */
bogdanm 82:6473597d706e 78 typedef union _hw_sim_sopt1
bogdanm 82:6473597d706e 79 {
bogdanm 82:6473597d706e 80 uint32_t U;
bogdanm 82:6473597d706e 81 struct _hw_sim_sopt1_bitfields
bogdanm 82:6473597d706e 82 {
bogdanm 82:6473597d706e 83 uint32_t RESERVED0 : 12; //!< [11:0]
bogdanm 82:6473597d706e 84 uint32_t RAMSIZE : 4; //!< [15:12] RAM size
bogdanm 82:6473597d706e 85 uint32_t RESERVED1 : 2; //!< [17:16]
bogdanm 82:6473597d706e 86 uint32_t OSC32KSEL : 2; //!< [19:18] 32K oscillator clock select
bogdanm 82:6473597d706e 87 uint32_t RESERVED2 : 9; //!< [28:20]
bogdanm 82:6473597d706e 88 uint32_t USBVSTBY : 1; //!< [29] USB voltage regulator in standby
bogdanm 82:6473597d706e 89 //! mode during VLPR and VLPW modes
bogdanm 82:6473597d706e 90 uint32_t USBSSTBY : 1; //!< [30] USB voltage regulator in standby
bogdanm 82:6473597d706e 91 //! mode during Stop, VLPS, LLS and VLLS modes.
bogdanm 82:6473597d706e 92 uint32_t USBREGEN : 1; //!< [31] USB voltage regulator enable
bogdanm 82:6473597d706e 93 } B;
bogdanm 82:6473597d706e 94 } hw_sim_sopt1_t;
bogdanm 82:6473597d706e 95 #endif
bogdanm 82:6473597d706e 96
bogdanm 82:6473597d706e 97 /*!
bogdanm 82:6473597d706e 98 * @name Constants and macros for entire SIM_SOPT1 register
bogdanm 82:6473597d706e 99 */
bogdanm 82:6473597d706e 100 //@{
bogdanm 82:6473597d706e 101 #define HW_SIM_SOPT1_ADDR (REGS_SIM_BASE + 0x0U)
bogdanm 82:6473597d706e 102
bogdanm 82:6473597d706e 103 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 104 #define HW_SIM_SOPT1 (*(__IO hw_sim_sopt1_t *) HW_SIM_SOPT1_ADDR)
bogdanm 82:6473597d706e 105 #define HW_SIM_SOPT1_RD() (HW_SIM_SOPT1.U)
bogdanm 82:6473597d706e 106 #define HW_SIM_SOPT1_WR(v) (HW_SIM_SOPT1.U = (v))
bogdanm 82:6473597d706e 107 #define HW_SIM_SOPT1_SET(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() | (v)))
bogdanm 82:6473597d706e 108 #define HW_SIM_SOPT1_CLR(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() & ~(v)))
bogdanm 82:6473597d706e 109 #define HW_SIM_SOPT1_TOG(v) (HW_SIM_SOPT1_WR(HW_SIM_SOPT1_RD() ^ (v)))
bogdanm 82:6473597d706e 110 #endif
bogdanm 82:6473597d706e 111 //@}
bogdanm 82:6473597d706e 112
bogdanm 82:6473597d706e 113 /*
bogdanm 82:6473597d706e 114 * Constants & macros for individual SIM_SOPT1 bitfields
bogdanm 82:6473597d706e 115 */
bogdanm 82:6473597d706e 116
bogdanm 82:6473597d706e 117 /*!
bogdanm 82:6473597d706e 118 * @name Register SIM_SOPT1, field RAMSIZE[15:12] (RO)
bogdanm 82:6473597d706e 119 *
bogdanm 82:6473597d706e 120 * This field specifies the amount of system RAM available on the device.
bogdanm 82:6473597d706e 121 *
bogdanm 82:6473597d706e 122 * Values:
bogdanm 82:6473597d706e 123 * - 0001 - 8 KB
bogdanm 82:6473597d706e 124 * - 0011 - 16 KB
bogdanm 82:6473597d706e 125 * - 0100 - 24 KB
bogdanm 82:6473597d706e 126 * - 0101 - 32 KB
bogdanm 82:6473597d706e 127 * - 0110 - 48 KB
bogdanm 82:6473597d706e 128 * - 0111 - 64 KB
bogdanm 82:6473597d706e 129 * - 1000 - 96 KB
bogdanm 82:6473597d706e 130 * - 1001 - 128 KB
bogdanm 82:6473597d706e 131 * - 1011 - 256 KB
bogdanm 82:6473597d706e 132 */
bogdanm 82:6473597d706e 133 //@{
bogdanm 82:6473597d706e 134 #define BP_SIM_SOPT1_RAMSIZE (12U) //!< Bit position for SIM_SOPT1_RAMSIZE.
bogdanm 82:6473597d706e 135 #define BM_SIM_SOPT1_RAMSIZE (0x0000F000U) //!< Bit mask for SIM_SOPT1_RAMSIZE.
bogdanm 82:6473597d706e 136 #define BS_SIM_SOPT1_RAMSIZE (4U) //!< Bit field size in bits for SIM_SOPT1_RAMSIZE.
bogdanm 82:6473597d706e 137
bogdanm 82:6473597d706e 138 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 139 //! @brief Read current value of the SIM_SOPT1_RAMSIZE field.
bogdanm 82:6473597d706e 140 #define BR_SIM_SOPT1_RAMSIZE (HW_SIM_SOPT1.B.RAMSIZE)
bogdanm 82:6473597d706e 141 #endif
bogdanm 82:6473597d706e 142 //@}
bogdanm 82:6473597d706e 143
bogdanm 82:6473597d706e 144 /*!
bogdanm 82:6473597d706e 145 * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
bogdanm 82:6473597d706e 146 *
bogdanm 82:6473597d706e 147 * Selects the 32 kHz clock source (ERCLK32K) for LPTMR. This field is reset
bogdanm 82:6473597d706e 148 * only on POR/LVD.
bogdanm 82:6473597d706e 149 *
bogdanm 82:6473597d706e 150 * Values:
bogdanm 82:6473597d706e 151 * - 00 - System oscillator (OSC32KCLK)
bogdanm 82:6473597d706e 152 * - 01 - Reserved
bogdanm 82:6473597d706e 153 * - 10 - RTC 32.768kHz oscillator
bogdanm 82:6473597d706e 154 * - 11 - LPO 1 kHz
bogdanm 82:6473597d706e 155 */
bogdanm 82:6473597d706e 156 //@{
bogdanm 82:6473597d706e 157 #define BP_SIM_SOPT1_OSC32KSEL (18U) //!< Bit position for SIM_SOPT1_OSC32KSEL.
bogdanm 82:6473597d706e 158 #define BM_SIM_SOPT1_OSC32KSEL (0x000C0000U) //!< Bit mask for SIM_SOPT1_OSC32KSEL.
bogdanm 82:6473597d706e 159 #define BS_SIM_SOPT1_OSC32KSEL (2U) //!< Bit field size in bits for SIM_SOPT1_OSC32KSEL.
bogdanm 82:6473597d706e 160
bogdanm 82:6473597d706e 161 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 162 //! @brief Read current value of the SIM_SOPT1_OSC32KSEL field.
bogdanm 82:6473597d706e 163 #define BR_SIM_SOPT1_OSC32KSEL (HW_SIM_SOPT1.B.OSC32KSEL)
bogdanm 82:6473597d706e 164 #endif
bogdanm 82:6473597d706e 165
bogdanm 82:6473597d706e 166 //! @brief Format value for bitfield SIM_SOPT1_OSC32KSEL.
bogdanm 82:6473597d706e 167 #define BF_SIM_SOPT1_OSC32KSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_OSC32KSEL), uint32_t) & BM_SIM_SOPT1_OSC32KSEL)
bogdanm 82:6473597d706e 168
bogdanm 82:6473597d706e 169 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 170 //! @brief Set the OSC32KSEL field to a new value.
bogdanm 82:6473597d706e 171 #define BW_SIM_SOPT1_OSC32KSEL(v) (HW_SIM_SOPT1_WR((HW_SIM_SOPT1_RD() & ~BM_SIM_SOPT1_OSC32KSEL) | BF_SIM_SOPT1_OSC32KSEL(v)))
bogdanm 82:6473597d706e 172 #endif
bogdanm 82:6473597d706e 173 //@}
bogdanm 82:6473597d706e 174
bogdanm 82:6473597d706e 175 /*!
bogdanm 82:6473597d706e 176 * @name Register SIM_SOPT1, field USBVSTBY[29] (RW)
bogdanm 82:6473597d706e 177 *
bogdanm 82:6473597d706e 178 * Controls whether the USB voltage regulator is placed in standby mode during
bogdanm 82:6473597d706e 179 * VLPR and VLPW modes.
bogdanm 82:6473597d706e 180 *
bogdanm 82:6473597d706e 181 * Values:
bogdanm 82:6473597d706e 182 * - 0 - USB voltage regulator not in standby during VLPR and VLPW modes.
bogdanm 82:6473597d706e 183 * - 1 - USB voltage regulator in standby during VLPR and VLPW modes.
bogdanm 82:6473597d706e 184 */
bogdanm 82:6473597d706e 185 //@{
bogdanm 82:6473597d706e 186 #define BP_SIM_SOPT1_USBVSTBY (29U) //!< Bit position for SIM_SOPT1_USBVSTBY.
bogdanm 82:6473597d706e 187 #define BM_SIM_SOPT1_USBVSTBY (0x20000000U) //!< Bit mask for SIM_SOPT1_USBVSTBY.
bogdanm 82:6473597d706e 188 #define BS_SIM_SOPT1_USBVSTBY (1U) //!< Bit field size in bits for SIM_SOPT1_USBVSTBY.
bogdanm 82:6473597d706e 189
bogdanm 82:6473597d706e 190 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 191 //! @brief Read current value of the SIM_SOPT1_USBVSTBY field.
bogdanm 82:6473597d706e 192 #define BR_SIM_SOPT1_USBVSTBY (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBVSTBY))
bogdanm 82:6473597d706e 193 #endif
bogdanm 82:6473597d706e 194
bogdanm 82:6473597d706e 195 //! @brief Format value for bitfield SIM_SOPT1_USBVSTBY.
bogdanm 82:6473597d706e 196 #define BF_SIM_SOPT1_USBVSTBY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBVSTBY), uint32_t) & BM_SIM_SOPT1_USBVSTBY)
bogdanm 82:6473597d706e 197
bogdanm 82:6473597d706e 198 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 199 //! @brief Set the USBVSTBY field to a new value.
bogdanm 82:6473597d706e 200 #define BW_SIM_SOPT1_USBVSTBY(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBVSTBY) = (v))
bogdanm 82:6473597d706e 201 #endif
bogdanm 82:6473597d706e 202 //@}
bogdanm 82:6473597d706e 203
bogdanm 82:6473597d706e 204 /*!
bogdanm 82:6473597d706e 205 * @name Register SIM_SOPT1, field USBSSTBY[30] (RW)
bogdanm 82:6473597d706e 206 *
bogdanm 82:6473597d706e 207 * Controls whether the USB voltage regulator is placed in standby mode during
bogdanm 82:6473597d706e 208 * Stop, VLPS, LLS and VLLS modes.
bogdanm 82:6473597d706e 209 *
bogdanm 82:6473597d706e 210 * Values:
bogdanm 82:6473597d706e 211 * - 0 - USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS
bogdanm 82:6473597d706e 212 * modes.
bogdanm 82:6473597d706e 213 * - 1 - USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
bogdanm 82:6473597d706e 214 */
bogdanm 82:6473597d706e 215 //@{
bogdanm 82:6473597d706e 216 #define BP_SIM_SOPT1_USBSSTBY (30U) //!< Bit position for SIM_SOPT1_USBSSTBY.
bogdanm 82:6473597d706e 217 #define BM_SIM_SOPT1_USBSSTBY (0x40000000U) //!< Bit mask for SIM_SOPT1_USBSSTBY.
bogdanm 82:6473597d706e 218 #define BS_SIM_SOPT1_USBSSTBY (1U) //!< Bit field size in bits for SIM_SOPT1_USBSSTBY.
bogdanm 82:6473597d706e 219
bogdanm 82:6473597d706e 220 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 221 //! @brief Read current value of the SIM_SOPT1_USBSSTBY field.
bogdanm 82:6473597d706e 222 #define BR_SIM_SOPT1_USBSSTBY (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBSSTBY))
bogdanm 82:6473597d706e 223 #endif
bogdanm 82:6473597d706e 224
bogdanm 82:6473597d706e 225 //! @brief Format value for bitfield SIM_SOPT1_USBSSTBY.
bogdanm 82:6473597d706e 226 #define BF_SIM_SOPT1_USBSSTBY(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBSSTBY), uint32_t) & BM_SIM_SOPT1_USBSSTBY)
bogdanm 82:6473597d706e 227
bogdanm 82:6473597d706e 228 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 229 //! @brief Set the USBSSTBY field to a new value.
bogdanm 82:6473597d706e 230 #define BW_SIM_SOPT1_USBSSTBY(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBSSTBY) = (v))
bogdanm 82:6473597d706e 231 #endif
bogdanm 82:6473597d706e 232 //@}
bogdanm 82:6473597d706e 233
bogdanm 82:6473597d706e 234 /*!
bogdanm 82:6473597d706e 235 * @name Register SIM_SOPT1, field USBREGEN[31] (RW)
bogdanm 82:6473597d706e 236 *
bogdanm 82:6473597d706e 237 * Controls whether the USB voltage regulator is enabled.
bogdanm 82:6473597d706e 238 *
bogdanm 82:6473597d706e 239 * Values:
bogdanm 82:6473597d706e 240 * - 0 - USB voltage regulator is disabled.
bogdanm 82:6473597d706e 241 * - 1 - USB voltage regulator is enabled.
bogdanm 82:6473597d706e 242 */
bogdanm 82:6473597d706e 243 //@{
bogdanm 82:6473597d706e 244 #define BP_SIM_SOPT1_USBREGEN (31U) //!< Bit position for SIM_SOPT1_USBREGEN.
bogdanm 82:6473597d706e 245 #define BM_SIM_SOPT1_USBREGEN (0x80000000U) //!< Bit mask for SIM_SOPT1_USBREGEN.
bogdanm 82:6473597d706e 246 #define BS_SIM_SOPT1_USBREGEN (1U) //!< Bit field size in bits for SIM_SOPT1_USBREGEN.
bogdanm 82:6473597d706e 247
bogdanm 82:6473597d706e 248 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 249 //! @brief Read current value of the SIM_SOPT1_USBREGEN field.
bogdanm 82:6473597d706e 250 #define BR_SIM_SOPT1_USBREGEN (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBREGEN))
bogdanm 82:6473597d706e 251 #endif
bogdanm 82:6473597d706e 252
bogdanm 82:6473597d706e 253 //! @brief Format value for bitfield SIM_SOPT1_USBREGEN.
bogdanm 82:6473597d706e 254 #define BF_SIM_SOPT1_USBREGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1_USBREGEN), uint32_t) & BM_SIM_SOPT1_USBREGEN)
bogdanm 82:6473597d706e 255
bogdanm 82:6473597d706e 256 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 257 //! @brief Set the USBREGEN field to a new value.
bogdanm 82:6473597d706e 258 #define BW_SIM_SOPT1_USBREGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT1_ADDR, BP_SIM_SOPT1_USBREGEN) = (v))
bogdanm 82:6473597d706e 259 #endif
bogdanm 82:6473597d706e 260 //@}
bogdanm 82:6473597d706e 261
bogdanm 82:6473597d706e 262 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 263 // HW_SIM_SOPT1CFG - SOPT1 Configuration Register
bogdanm 82:6473597d706e 264 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 265
bogdanm 82:6473597d706e 266 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 267 /*!
bogdanm 82:6473597d706e 268 * @brief HW_SIM_SOPT1CFG - SOPT1 Configuration Register (RW)
bogdanm 82:6473597d706e 269 *
bogdanm 82:6473597d706e 270 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 271 *
bogdanm 82:6473597d706e 272 * The SOPT1CFG register is reset on System Reset not VLLS.
bogdanm 82:6473597d706e 273 */
bogdanm 82:6473597d706e 274 typedef union _hw_sim_sopt1cfg
bogdanm 82:6473597d706e 275 {
bogdanm 82:6473597d706e 276 uint32_t U;
bogdanm 82:6473597d706e 277 struct _hw_sim_sopt1cfg_bitfields
bogdanm 82:6473597d706e 278 {
bogdanm 82:6473597d706e 279 uint32_t RESERVED0 : 24; //!< [23:0]
bogdanm 82:6473597d706e 280 uint32_t URWE : 1; //!< [24] USB voltage regulator enable write enable
bogdanm 82:6473597d706e 281 uint32_t UVSWE : 1; //!< [25] USB voltage regulator VLP standby write
bogdanm 82:6473597d706e 282 //! enable
bogdanm 82:6473597d706e 283 uint32_t USSWE : 1; //!< [26] USB voltage regulator stop standby
bogdanm 82:6473597d706e 284 //! write enable
bogdanm 82:6473597d706e 285 uint32_t RESERVED1 : 5; //!< [31:27]
bogdanm 82:6473597d706e 286 } B;
bogdanm 82:6473597d706e 287 } hw_sim_sopt1cfg_t;
bogdanm 82:6473597d706e 288 #endif
bogdanm 82:6473597d706e 289
bogdanm 82:6473597d706e 290 /*!
bogdanm 82:6473597d706e 291 * @name Constants and macros for entire SIM_SOPT1CFG register
bogdanm 82:6473597d706e 292 */
bogdanm 82:6473597d706e 293 //@{
bogdanm 82:6473597d706e 294 #define HW_SIM_SOPT1CFG_ADDR (REGS_SIM_BASE + 0x4U)
bogdanm 82:6473597d706e 295
bogdanm 82:6473597d706e 296 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 297 #define HW_SIM_SOPT1CFG (*(__IO hw_sim_sopt1cfg_t *) HW_SIM_SOPT1CFG_ADDR)
bogdanm 82:6473597d706e 298 #define HW_SIM_SOPT1CFG_RD() (HW_SIM_SOPT1CFG.U)
bogdanm 82:6473597d706e 299 #define HW_SIM_SOPT1CFG_WR(v) (HW_SIM_SOPT1CFG.U = (v))
bogdanm 82:6473597d706e 300 #define HW_SIM_SOPT1CFG_SET(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() | (v)))
bogdanm 82:6473597d706e 301 #define HW_SIM_SOPT1CFG_CLR(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() & ~(v)))
bogdanm 82:6473597d706e 302 #define HW_SIM_SOPT1CFG_TOG(v) (HW_SIM_SOPT1CFG_WR(HW_SIM_SOPT1CFG_RD() ^ (v)))
bogdanm 82:6473597d706e 303 #endif
bogdanm 82:6473597d706e 304 //@}
bogdanm 82:6473597d706e 305
bogdanm 82:6473597d706e 306 /*
bogdanm 82:6473597d706e 307 * Constants & macros for individual SIM_SOPT1CFG bitfields
bogdanm 82:6473597d706e 308 */
bogdanm 82:6473597d706e 309
bogdanm 82:6473597d706e 310 /*!
bogdanm 82:6473597d706e 311 * @name Register SIM_SOPT1CFG, field URWE[24] (RW)
bogdanm 82:6473597d706e 312 *
bogdanm 82:6473597d706e 313 * Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This
bogdanm 82:6473597d706e 314 * register bit clears after a write to USBREGEN.
bogdanm 82:6473597d706e 315 *
bogdanm 82:6473597d706e 316 * Values:
bogdanm 82:6473597d706e 317 * - 0 - SOPT1 USBREGEN cannot be written.
bogdanm 82:6473597d706e 318 * - 1 - SOPT1 USBREGEN can be written.
bogdanm 82:6473597d706e 319 */
bogdanm 82:6473597d706e 320 //@{
bogdanm 82:6473597d706e 321 #define BP_SIM_SOPT1CFG_URWE (24U) //!< Bit position for SIM_SOPT1CFG_URWE.
bogdanm 82:6473597d706e 322 #define BM_SIM_SOPT1CFG_URWE (0x01000000U) //!< Bit mask for SIM_SOPT1CFG_URWE.
bogdanm 82:6473597d706e 323 #define BS_SIM_SOPT1CFG_URWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_URWE.
bogdanm 82:6473597d706e 324
bogdanm 82:6473597d706e 325 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 326 //! @brief Read current value of the SIM_SOPT1CFG_URWE field.
bogdanm 82:6473597d706e 327 #define BR_SIM_SOPT1CFG_URWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_URWE))
bogdanm 82:6473597d706e 328 #endif
bogdanm 82:6473597d706e 329
bogdanm 82:6473597d706e 330 //! @brief Format value for bitfield SIM_SOPT1CFG_URWE.
bogdanm 82:6473597d706e 331 #define BF_SIM_SOPT1CFG_URWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_URWE), uint32_t) & BM_SIM_SOPT1CFG_URWE)
bogdanm 82:6473597d706e 332
bogdanm 82:6473597d706e 333 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 334 //! @brief Set the URWE field to a new value.
bogdanm 82:6473597d706e 335 #define BW_SIM_SOPT1CFG_URWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_URWE) = (v))
bogdanm 82:6473597d706e 336 #endif
bogdanm 82:6473597d706e 337 //@}
bogdanm 82:6473597d706e 338
bogdanm 82:6473597d706e 339 /*!
bogdanm 82:6473597d706e 340 * @name Register SIM_SOPT1CFG, field UVSWE[25] (RW)
bogdanm 82:6473597d706e 341 *
bogdanm 82:6473597d706e 342 * Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written.
bogdanm 82:6473597d706e 343 * This register bit clears after a write to USBVSTBY.
bogdanm 82:6473597d706e 344 *
bogdanm 82:6473597d706e 345 * Values:
bogdanm 82:6473597d706e 346 * - 0 - SOPT1 USBVSTBY cannot be written.
bogdanm 82:6473597d706e 347 * - 1 - SOPT1 USBVSTBY can be written.
bogdanm 82:6473597d706e 348 */
bogdanm 82:6473597d706e 349 //@{
bogdanm 82:6473597d706e 350 #define BP_SIM_SOPT1CFG_UVSWE (25U) //!< Bit position for SIM_SOPT1CFG_UVSWE.
bogdanm 82:6473597d706e 351 #define BM_SIM_SOPT1CFG_UVSWE (0x02000000U) //!< Bit mask for SIM_SOPT1CFG_UVSWE.
bogdanm 82:6473597d706e 352 #define BS_SIM_SOPT1CFG_UVSWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_UVSWE.
bogdanm 82:6473597d706e 353
bogdanm 82:6473597d706e 354 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 355 //! @brief Read current value of the SIM_SOPT1CFG_UVSWE field.
bogdanm 82:6473597d706e 356 #define BR_SIM_SOPT1CFG_UVSWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_UVSWE))
bogdanm 82:6473597d706e 357 #endif
bogdanm 82:6473597d706e 358
bogdanm 82:6473597d706e 359 //! @brief Format value for bitfield SIM_SOPT1CFG_UVSWE.
bogdanm 82:6473597d706e 360 #define BF_SIM_SOPT1CFG_UVSWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_UVSWE), uint32_t) & BM_SIM_SOPT1CFG_UVSWE)
bogdanm 82:6473597d706e 361
bogdanm 82:6473597d706e 362 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 363 //! @brief Set the UVSWE field to a new value.
bogdanm 82:6473597d706e 364 #define BW_SIM_SOPT1CFG_UVSWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_UVSWE) = (v))
bogdanm 82:6473597d706e 365 #endif
bogdanm 82:6473597d706e 366 //@}
bogdanm 82:6473597d706e 367
bogdanm 82:6473597d706e 368 /*!
bogdanm 82:6473597d706e 369 * @name Register SIM_SOPT1CFG, field USSWE[26] (RW)
bogdanm 82:6473597d706e 370 *
bogdanm 82:6473597d706e 371 * Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written.
bogdanm 82:6473597d706e 372 * This register bit clears after a write to USBSSTBY.
bogdanm 82:6473597d706e 373 *
bogdanm 82:6473597d706e 374 * Values:
bogdanm 82:6473597d706e 375 * - 0 - SOPT1 USBSSTBY cannot be written.
bogdanm 82:6473597d706e 376 * - 1 - SOPT1 USBSSTBY can be written.
bogdanm 82:6473597d706e 377 */
bogdanm 82:6473597d706e 378 //@{
bogdanm 82:6473597d706e 379 #define BP_SIM_SOPT1CFG_USSWE (26U) //!< Bit position for SIM_SOPT1CFG_USSWE.
bogdanm 82:6473597d706e 380 #define BM_SIM_SOPT1CFG_USSWE (0x04000000U) //!< Bit mask for SIM_SOPT1CFG_USSWE.
bogdanm 82:6473597d706e 381 #define BS_SIM_SOPT1CFG_USSWE (1U) //!< Bit field size in bits for SIM_SOPT1CFG_USSWE.
bogdanm 82:6473597d706e 382
bogdanm 82:6473597d706e 383 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 384 //! @brief Read current value of the SIM_SOPT1CFG_USSWE field.
bogdanm 82:6473597d706e 385 #define BR_SIM_SOPT1CFG_USSWE (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_USSWE))
bogdanm 82:6473597d706e 386 #endif
bogdanm 82:6473597d706e 387
bogdanm 82:6473597d706e 388 //! @brief Format value for bitfield SIM_SOPT1CFG_USSWE.
bogdanm 82:6473597d706e 389 #define BF_SIM_SOPT1CFG_USSWE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT1CFG_USSWE), uint32_t) & BM_SIM_SOPT1CFG_USSWE)
bogdanm 82:6473597d706e 390
bogdanm 82:6473597d706e 391 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 392 //! @brief Set the USSWE field to a new value.
bogdanm 82:6473597d706e 393 #define BW_SIM_SOPT1CFG_USSWE(v) (BITBAND_ACCESS32(HW_SIM_SOPT1CFG_ADDR, BP_SIM_SOPT1CFG_USSWE) = (v))
bogdanm 82:6473597d706e 394 #endif
bogdanm 82:6473597d706e 395 //@}
bogdanm 82:6473597d706e 396
bogdanm 82:6473597d706e 397 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 398 // HW_SIM_SOPT2 - System Options Register 2
bogdanm 82:6473597d706e 399 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 400
bogdanm 82:6473597d706e 401 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 402 /*!
bogdanm 82:6473597d706e 403 * @brief HW_SIM_SOPT2 - System Options Register 2 (RW)
bogdanm 82:6473597d706e 404 *
bogdanm 82:6473597d706e 405 * Reset value: 0x00001000U
bogdanm 82:6473597d706e 406 *
bogdanm 82:6473597d706e 407 * SOPT2 contains the controls for selecting many of the module clock source
bogdanm 82:6473597d706e 408 * options on this device. See the Clock Distribution chapter for more information
bogdanm 82:6473597d706e 409 * including clocking diagrams and definitions of device clocks.
bogdanm 82:6473597d706e 410 */
bogdanm 82:6473597d706e 411 typedef union _hw_sim_sopt2
bogdanm 82:6473597d706e 412 {
bogdanm 82:6473597d706e 413 uint32_t U;
bogdanm 82:6473597d706e 414 struct _hw_sim_sopt2_bitfields
bogdanm 82:6473597d706e 415 {
bogdanm 82:6473597d706e 416 uint32_t RESERVED0 : 4; //!< [3:0]
bogdanm 82:6473597d706e 417 uint32_t RTCCLKOUTSEL : 1; //!< [4] RTC clock out select
bogdanm 82:6473597d706e 418 uint32_t CLKOUTSEL : 3; //!< [7:5] CLKOUT select
bogdanm 82:6473597d706e 419 uint32_t FBSL : 2; //!< [9:8] FlexBus security level
bogdanm 82:6473597d706e 420 uint32_t RESERVED1 : 1; //!< [10]
bogdanm 82:6473597d706e 421 uint32_t PTD7PAD : 1; //!< [11] PTD7 pad drive strength
bogdanm 82:6473597d706e 422 uint32_t TRACECLKSEL : 1; //!< [12] Debug trace clock select
bogdanm 82:6473597d706e 423 uint32_t RESERVED2 : 3; //!< [15:13]
bogdanm 82:6473597d706e 424 uint32_t PLLFLLSEL : 2; //!< [17:16] PLL/FLL clock select
bogdanm 82:6473597d706e 425 uint32_t USBSRC : 1; //!< [18] USB clock source select
bogdanm 82:6473597d706e 426 uint32_t RMIISRC : 1; //!< [19] RMII clock source select
bogdanm 82:6473597d706e 427 uint32_t TIMESRC : 2; //!< [21:20] IEEE 1588 timestamp clock source
bogdanm 82:6473597d706e 428 //! select
bogdanm 82:6473597d706e 429 uint32_t RESERVED3 : 6; //!< [27:22]
bogdanm 82:6473597d706e 430 uint32_t SDHCSRC : 2; //!< [29:28] SDHC clock source select
bogdanm 82:6473597d706e 431 uint32_t RESERVED4 : 2; //!< [31:30]
bogdanm 82:6473597d706e 432 } B;
bogdanm 82:6473597d706e 433 } hw_sim_sopt2_t;
bogdanm 82:6473597d706e 434 #endif
bogdanm 82:6473597d706e 435
bogdanm 82:6473597d706e 436 /*!
bogdanm 82:6473597d706e 437 * @name Constants and macros for entire SIM_SOPT2 register
bogdanm 82:6473597d706e 438 */
bogdanm 82:6473597d706e 439 //@{
bogdanm 82:6473597d706e 440 #define HW_SIM_SOPT2_ADDR (REGS_SIM_BASE + 0x1004U)
bogdanm 82:6473597d706e 441
bogdanm 82:6473597d706e 442 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 443 #define HW_SIM_SOPT2 (*(__IO hw_sim_sopt2_t *) HW_SIM_SOPT2_ADDR)
bogdanm 82:6473597d706e 444 #define HW_SIM_SOPT2_RD() (HW_SIM_SOPT2.U)
bogdanm 82:6473597d706e 445 #define HW_SIM_SOPT2_WR(v) (HW_SIM_SOPT2.U = (v))
bogdanm 82:6473597d706e 446 #define HW_SIM_SOPT2_SET(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() | (v)))
bogdanm 82:6473597d706e 447 #define HW_SIM_SOPT2_CLR(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() & ~(v)))
bogdanm 82:6473597d706e 448 #define HW_SIM_SOPT2_TOG(v) (HW_SIM_SOPT2_WR(HW_SIM_SOPT2_RD() ^ (v)))
bogdanm 82:6473597d706e 449 #endif
bogdanm 82:6473597d706e 450 //@}
bogdanm 82:6473597d706e 451
bogdanm 82:6473597d706e 452 /*
bogdanm 82:6473597d706e 453 * Constants & macros for individual SIM_SOPT2 bitfields
bogdanm 82:6473597d706e 454 */
bogdanm 82:6473597d706e 455
bogdanm 82:6473597d706e 456 /*!
bogdanm 82:6473597d706e 457 * @name Register SIM_SOPT2, field RTCCLKOUTSEL[4] (RW)
bogdanm 82:6473597d706e 458 *
bogdanm 82:6473597d706e 459 * Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the
bogdanm 82:6473597d706e 460 * RTC_CLKOUT pin.
bogdanm 82:6473597d706e 461 *
bogdanm 82:6473597d706e 462 * Values:
bogdanm 82:6473597d706e 463 * - 0 - RTC 1 Hz clock is output on the RTC_CLKOUT pin.
bogdanm 82:6473597d706e 464 * - 1 - RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
bogdanm 82:6473597d706e 465 */
bogdanm 82:6473597d706e 466 //@{
bogdanm 82:6473597d706e 467 #define BP_SIM_SOPT2_RTCCLKOUTSEL (4U) //!< Bit position for SIM_SOPT2_RTCCLKOUTSEL.
bogdanm 82:6473597d706e 468 #define BM_SIM_SOPT2_RTCCLKOUTSEL (0x00000010U) //!< Bit mask for SIM_SOPT2_RTCCLKOUTSEL.
bogdanm 82:6473597d706e 469 #define BS_SIM_SOPT2_RTCCLKOUTSEL (1U) //!< Bit field size in bits for SIM_SOPT2_RTCCLKOUTSEL.
bogdanm 82:6473597d706e 470
bogdanm 82:6473597d706e 471 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 472 //! @brief Read current value of the SIM_SOPT2_RTCCLKOUTSEL field.
bogdanm 82:6473597d706e 473 #define BR_SIM_SOPT2_RTCCLKOUTSEL (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RTCCLKOUTSEL))
bogdanm 82:6473597d706e 474 #endif
bogdanm 82:6473597d706e 475
bogdanm 82:6473597d706e 476 //! @brief Format value for bitfield SIM_SOPT2_RTCCLKOUTSEL.
bogdanm 82:6473597d706e 477 #define BF_SIM_SOPT2_RTCCLKOUTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_RTCCLKOUTSEL), uint32_t) & BM_SIM_SOPT2_RTCCLKOUTSEL)
bogdanm 82:6473597d706e 478
bogdanm 82:6473597d706e 479 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 480 //! @brief Set the RTCCLKOUTSEL field to a new value.
bogdanm 82:6473597d706e 481 #define BW_SIM_SOPT2_RTCCLKOUTSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RTCCLKOUTSEL) = (v))
bogdanm 82:6473597d706e 482 #endif
bogdanm 82:6473597d706e 483 //@}
bogdanm 82:6473597d706e 484
bogdanm 82:6473597d706e 485 /*!
bogdanm 82:6473597d706e 486 * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
bogdanm 82:6473597d706e 487 *
bogdanm 82:6473597d706e 488 * Selects the clock to output on the CLKOUT pin.
bogdanm 82:6473597d706e 489 *
bogdanm 82:6473597d706e 490 * Values:
bogdanm 82:6473597d706e 491 * - 000 - FlexBus CLKOUT
bogdanm 82:6473597d706e 492 * - 001 - Reserved
bogdanm 82:6473597d706e 493 * - 010 - Flash clock
bogdanm 82:6473597d706e 494 * - 011 - LPO clock (1 kHz)
bogdanm 82:6473597d706e 495 * - 100 - MCGIRCLK
bogdanm 82:6473597d706e 496 * - 101 - RTC 32.768kHz clock
bogdanm 82:6473597d706e 497 * - 110 - OSCERCLK0
bogdanm 82:6473597d706e 498 * - 111 - IRC 48 MHz clock
bogdanm 82:6473597d706e 499 */
bogdanm 82:6473597d706e 500 //@{
bogdanm 82:6473597d706e 501 #define BP_SIM_SOPT2_CLKOUTSEL (5U) //!< Bit position for SIM_SOPT2_CLKOUTSEL.
bogdanm 82:6473597d706e 502 #define BM_SIM_SOPT2_CLKOUTSEL (0x000000E0U) //!< Bit mask for SIM_SOPT2_CLKOUTSEL.
bogdanm 82:6473597d706e 503 #define BS_SIM_SOPT2_CLKOUTSEL (3U) //!< Bit field size in bits for SIM_SOPT2_CLKOUTSEL.
bogdanm 82:6473597d706e 504
bogdanm 82:6473597d706e 505 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 506 //! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field.
bogdanm 82:6473597d706e 507 #define BR_SIM_SOPT2_CLKOUTSEL (HW_SIM_SOPT2.B.CLKOUTSEL)
bogdanm 82:6473597d706e 508 #endif
bogdanm 82:6473597d706e 509
bogdanm 82:6473597d706e 510 //! @brief Format value for bitfield SIM_SOPT2_CLKOUTSEL.
bogdanm 82:6473597d706e 511 #define BF_SIM_SOPT2_CLKOUTSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_CLKOUTSEL), uint32_t) & BM_SIM_SOPT2_CLKOUTSEL)
bogdanm 82:6473597d706e 512
bogdanm 82:6473597d706e 513 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 514 //! @brief Set the CLKOUTSEL field to a new value.
bogdanm 82:6473597d706e 515 #define BW_SIM_SOPT2_CLKOUTSEL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_CLKOUTSEL) | BF_SIM_SOPT2_CLKOUTSEL(v)))
bogdanm 82:6473597d706e 516 #endif
bogdanm 82:6473597d706e 517 //@}
bogdanm 82:6473597d706e 518
bogdanm 82:6473597d706e 519 /*!
bogdanm 82:6473597d706e 520 * @name Register SIM_SOPT2, field FBSL[9:8] (RW)
bogdanm 82:6473597d706e 521 *
bogdanm 82:6473597d706e 522 * If flash security is enabled, then this field affects what CPU operations can
bogdanm 82:6473597d706e 523 * access off-chip via the FlexBus interface. This field has no effect if flash
bogdanm 82:6473597d706e 524 * security is not enabled.
bogdanm 82:6473597d706e 525 *
bogdanm 82:6473597d706e 526 * Values:
bogdanm 82:6473597d706e 527 * - 00 - All off-chip accesses (instruction and data) via the FlexBus are
bogdanm 82:6473597d706e 528 * disallowed.
bogdanm 82:6473597d706e 529 * - 01 - All off-chip accesses (instruction and data) via the FlexBus are
bogdanm 82:6473597d706e 530 * disallowed.
bogdanm 82:6473597d706e 531 * - 10 - Off-chip instruction accesses are disallowed. Data accesses are
bogdanm 82:6473597d706e 532 * allowed.
bogdanm 82:6473597d706e 533 * - 11 - Off-chip instruction accesses and data accesses are allowed.
bogdanm 82:6473597d706e 534 */
bogdanm 82:6473597d706e 535 //@{
bogdanm 82:6473597d706e 536 #define BP_SIM_SOPT2_FBSL (8U) //!< Bit position for SIM_SOPT2_FBSL.
bogdanm 82:6473597d706e 537 #define BM_SIM_SOPT2_FBSL (0x00000300U) //!< Bit mask for SIM_SOPT2_FBSL.
bogdanm 82:6473597d706e 538 #define BS_SIM_SOPT2_FBSL (2U) //!< Bit field size in bits for SIM_SOPT2_FBSL.
bogdanm 82:6473597d706e 539
bogdanm 82:6473597d706e 540 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 541 //! @brief Read current value of the SIM_SOPT2_FBSL field.
bogdanm 82:6473597d706e 542 #define BR_SIM_SOPT2_FBSL (HW_SIM_SOPT2.B.FBSL)
bogdanm 82:6473597d706e 543 #endif
bogdanm 82:6473597d706e 544
bogdanm 82:6473597d706e 545 //! @brief Format value for bitfield SIM_SOPT2_FBSL.
bogdanm 82:6473597d706e 546 #define BF_SIM_SOPT2_FBSL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_FBSL), uint32_t) & BM_SIM_SOPT2_FBSL)
bogdanm 82:6473597d706e 547
bogdanm 82:6473597d706e 548 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 549 //! @brief Set the FBSL field to a new value.
bogdanm 82:6473597d706e 550 #define BW_SIM_SOPT2_FBSL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_FBSL) | BF_SIM_SOPT2_FBSL(v)))
bogdanm 82:6473597d706e 551 #endif
bogdanm 82:6473597d706e 552 //@}
bogdanm 82:6473597d706e 553
bogdanm 82:6473597d706e 554 /*!
bogdanm 82:6473597d706e 555 * @name Register SIM_SOPT2, field PTD7PAD[11] (RW)
bogdanm 82:6473597d706e 556 *
bogdanm 82:6473597d706e 557 * Controls the output drive strength of the PTD7 pin by selecting either one or
bogdanm 82:6473597d706e 558 * two pads to drive it.
bogdanm 82:6473597d706e 559 *
bogdanm 82:6473597d706e 560 * Values:
bogdanm 82:6473597d706e 561 * - 0 - Single-pad drive strength for PTD7.
bogdanm 82:6473597d706e 562 * - 1 - Double pad drive strength for PTD7.
bogdanm 82:6473597d706e 563 */
bogdanm 82:6473597d706e 564 //@{
bogdanm 82:6473597d706e 565 #define BP_SIM_SOPT2_PTD7PAD (11U) //!< Bit position for SIM_SOPT2_PTD7PAD.
bogdanm 82:6473597d706e 566 #define BM_SIM_SOPT2_PTD7PAD (0x00000800U) //!< Bit mask for SIM_SOPT2_PTD7PAD.
bogdanm 82:6473597d706e 567 #define BS_SIM_SOPT2_PTD7PAD (1U) //!< Bit field size in bits for SIM_SOPT2_PTD7PAD.
bogdanm 82:6473597d706e 568
bogdanm 82:6473597d706e 569 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 570 //! @brief Read current value of the SIM_SOPT2_PTD7PAD field.
bogdanm 82:6473597d706e 571 #define BR_SIM_SOPT2_PTD7PAD (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_PTD7PAD))
bogdanm 82:6473597d706e 572 #endif
bogdanm 82:6473597d706e 573
bogdanm 82:6473597d706e 574 //! @brief Format value for bitfield SIM_SOPT2_PTD7PAD.
bogdanm 82:6473597d706e 575 #define BF_SIM_SOPT2_PTD7PAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_PTD7PAD), uint32_t) & BM_SIM_SOPT2_PTD7PAD)
bogdanm 82:6473597d706e 576
bogdanm 82:6473597d706e 577 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 578 //! @brief Set the PTD7PAD field to a new value.
bogdanm 82:6473597d706e 579 #define BW_SIM_SOPT2_PTD7PAD(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_PTD7PAD) = (v))
bogdanm 82:6473597d706e 580 #endif
bogdanm 82:6473597d706e 581 //@}
bogdanm 82:6473597d706e 582
bogdanm 82:6473597d706e 583 /*!
bogdanm 82:6473597d706e 584 * @name Register SIM_SOPT2, field TRACECLKSEL[12] (RW)
bogdanm 82:6473597d706e 585 *
bogdanm 82:6473597d706e 586 * Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace
bogdanm 82:6473597d706e 587 * clock source.
bogdanm 82:6473597d706e 588 *
bogdanm 82:6473597d706e 589 * Values:
bogdanm 82:6473597d706e 590 * - 0 - MCGOUTCLK
bogdanm 82:6473597d706e 591 * - 1 - Core/system clock
bogdanm 82:6473597d706e 592 */
bogdanm 82:6473597d706e 593 //@{
bogdanm 82:6473597d706e 594 #define BP_SIM_SOPT2_TRACECLKSEL (12U) //!< Bit position for SIM_SOPT2_TRACECLKSEL.
bogdanm 82:6473597d706e 595 #define BM_SIM_SOPT2_TRACECLKSEL (0x00001000U) //!< Bit mask for SIM_SOPT2_TRACECLKSEL.
bogdanm 82:6473597d706e 596 #define BS_SIM_SOPT2_TRACECLKSEL (1U) //!< Bit field size in bits for SIM_SOPT2_TRACECLKSEL.
bogdanm 82:6473597d706e 597
bogdanm 82:6473597d706e 598 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 599 //! @brief Read current value of the SIM_SOPT2_TRACECLKSEL field.
bogdanm 82:6473597d706e 600 #define BR_SIM_SOPT2_TRACECLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_TRACECLKSEL))
bogdanm 82:6473597d706e 601 #endif
bogdanm 82:6473597d706e 602
bogdanm 82:6473597d706e 603 //! @brief Format value for bitfield SIM_SOPT2_TRACECLKSEL.
bogdanm 82:6473597d706e 604 #define BF_SIM_SOPT2_TRACECLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_TRACECLKSEL), uint32_t) & BM_SIM_SOPT2_TRACECLKSEL)
bogdanm 82:6473597d706e 605
bogdanm 82:6473597d706e 606 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 607 //! @brief Set the TRACECLKSEL field to a new value.
bogdanm 82:6473597d706e 608 #define BW_SIM_SOPT2_TRACECLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_TRACECLKSEL) = (v))
bogdanm 82:6473597d706e 609 #endif
bogdanm 82:6473597d706e 610 //@}
bogdanm 82:6473597d706e 611
bogdanm 82:6473597d706e 612 /*!
bogdanm 82:6473597d706e 613 * @name Register SIM_SOPT2, field PLLFLLSEL[17:16] (RW)
bogdanm 82:6473597d706e 614 *
bogdanm 82:6473597d706e 615 * Selects the high frequency clock for various peripheral clocking options.
bogdanm 82:6473597d706e 616 *
bogdanm 82:6473597d706e 617 * Values:
bogdanm 82:6473597d706e 618 * - 00 - MCGFLLCLK clock
bogdanm 82:6473597d706e 619 * - 01 - MCGPLLCLK clock
bogdanm 82:6473597d706e 620 * - 10 - Reserved
bogdanm 82:6473597d706e 621 * - 11 - IRC48 MHz clock
bogdanm 82:6473597d706e 622 */
bogdanm 82:6473597d706e 623 //@{
bogdanm 82:6473597d706e 624 #define BP_SIM_SOPT2_PLLFLLSEL (16U) //!< Bit position for SIM_SOPT2_PLLFLLSEL.
bogdanm 82:6473597d706e 625 #define BM_SIM_SOPT2_PLLFLLSEL (0x00030000U) //!< Bit mask for SIM_SOPT2_PLLFLLSEL.
bogdanm 82:6473597d706e 626 #define BS_SIM_SOPT2_PLLFLLSEL (2U) //!< Bit field size in bits for SIM_SOPT2_PLLFLLSEL.
bogdanm 82:6473597d706e 627
bogdanm 82:6473597d706e 628 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 629 //! @brief Read current value of the SIM_SOPT2_PLLFLLSEL field.
bogdanm 82:6473597d706e 630 #define BR_SIM_SOPT2_PLLFLLSEL (HW_SIM_SOPT2.B.PLLFLLSEL)
bogdanm 82:6473597d706e 631 #endif
bogdanm 82:6473597d706e 632
bogdanm 82:6473597d706e 633 //! @brief Format value for bitfield SIM_SOPT2_PLLFLLSEL.
bogdanm 82:6473597d706e 634 #define BF_SIM_SOPT2_PLLFLLSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_PLLFLLSEL), uint32_t) & BM_SIM_SOPT2_PLLFLLSEL)
bogdanm 82:6473597d706e 635
bogdanm 82:6473597d706e 636 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 637 //! @brief Set the PLLFLLSEL field to a new value.
bogdanm 82:6473597d706e 638 #define BW_SIM_SOPT2_PLLFLLSEL(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_PLLFLLSEL) | BF_SIM_SOPT2_PLLFLLSEL(v)))
bogdanm 82:6473597d706e 639 #endif
bogdanm 82:6473597d706e 640 //@}
bogdanm 82:6473597d706e 641
bogdanm 82:6473597d706e 642 /*!
bogdanm 82:6473597d706e 643 * @name Register SIM_SOPT2, field USBSRC[18] (RW)
bogdanm 82:6473597d706e 644 *
bogdanm 82:6473597d706e 645 * Selects the clock source for the USB 48 MHz clock.
bogdanm 82:6473597d706e 646 *
bogdanm 82:6473597d706e 647 * Values:
bogdanm 82:6473597d706e 648 * - 0 - External bypass clock (USB_CLKIN).
bogdanm 82:6473597d706e 649 * - 1 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
bogdanm 82:6473597d706e 650 * SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by
bogdanm 82:6473597d706e 651 * SIM_CLKDIV2[USBFRAC, USBDIV].
bogdanm 82:6473597d706e 652 */
bogdanm 82:6473597d706e 653 //@{
bogdanm 82:6473597d706e 654 #define BP_SIM_SOPT2_USBSRC (18U) //!< Bit position for SIM_SOPT2_USBSRC.
bogdanm 82:6473597d706e 655 #define BM_SIM_SOPT2_USBSRC (0x00040000U) //!< Bit mask for SIM_SOPT2_USBSRC.
bogdanm 82:6473597d706e 656 #define BS_SIM_SOPT2_USBSRC (1U) //!< Bit field size in bits for SIM_SOPT2_USBSRC.
bogdanm 82:6473597d706e 657
bogdanm 82:6473597d706e 658 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 659 //! @brief Read current value of the SIM_SOPT2_USBSRC field.
bogdanm 82:6473597d706e 660 #define BR_SIM_SOPT2_USBSRC (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_USBSRC))
bogdanm 82:6473597d706e 661 #endif
bogdanm 82:6473597d706e 662
bogdanm 82:6473597d706e 663 //! @brief Format value for bitfield SIM_SOPT2_USBSRC.
bogdanm 82:6473597d706e 664 #define BF_SIM_SOPT2_USBSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_USBSRC), uint32_t) & BM_SIM_SOPT2_USBSRC)
bogdanm 82:6473597d706e 665
bogdanm 82:6473597d706e 666 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 667 //! @brief Set the USBSRC field to a new value.
bogdanm 82:6473597d706e 668 #define BW_SIM_SOPT2_USBSRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_USBSRC) = (v))
bogdanm 82:6473597d706e 669 #endif
bogdanm 82:6473597d706e 670 //@}
bogdanm 82:6473597d706e 671
bogdanm 82:6473597d706e 672 /*!
bogdanm 82:6473597d706e 673 * @name Register SIM_SOPT2, field RMIISRC[19] (RW)
bogdanm 82:6473597d706e 674 *
bogdanm 82:6473597d706e 675 * Selects the clock source for the Ethernet RMII interface
bogdanm 82:6473597d706e 676 *
bogdanm 82:6473597d706e 677 * Values:
bogdanm 82:6473597d706e 678 * - 0 - EXTAL clock
bogdanm 82:6473597d706e 679 * - 1 - External bypass clock (ENET_1588_CLKIN).
bogdanm 82:6473597d706e 680 */
bogdanm 82:6473597d706e 681 //@{
bogdanm 82:6473597d706e 682 #define BP_SIM_SOPT2_RMIISRC (19U) //!< Bit position for SIM_SOPT2_RMIISRC.
bogdanm 82:6473597d706e 683 #define BM_SIM_SOPT2_RMIISRC (0x00080000U) //!< Bit mask for SIM_SOPT2_RMIISRC.
bogdanm 82:6473597d706e 684 #define BS_SIM_SOPT2_RMIISRC (1U) //!< Bit field size in bits for SIM_SOPT2_RMIISRC.
bogdanm 82:6473597d706e 685
bogdanm 82:6473597d706e 686 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 687 //! @brief Read current value of the SIM_SOPT2_RMIISRC field.
bogdanm 82:6473597d706e 688 #define BR_SIM_SOPT2_RMIISRC (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RMIISRC))
bogdanm 82:6473597d706e 689 #endif
bogdanm 82:6473597d706e 690
bogdanm 82:6473597d706e 691 //! @brief Format value for bitfield SIM_SOPT2_RMIISRC.
bogdanm 82:6473597d706e 692 #define BF_SIM_SOPT2_RMIISRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_RMIISRC), uint32_t) & BM_SIM_SOPT2_RMIISRC)
bogdanm 82:6473597d706e 693
bogdanm 82:6473597d706e 694 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 695 //! @brief Set the RMIISRC field to a new value.
bogdanm 82:6473597d706e 696 #define BW_SIM_SOPT2_RMIISRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT2_ADDR, BP_SIM_SOPT2_RMIISRC) = (v))
bogdanm 82:6473597d706e 697 #endif
bogdanm 82:6473597d706e 698 //@}
bogdanm 82:6473597d706e 699
bogdanm 82:6473597d706e 700 /*!
bogdanm 82:6473597d706e 701 * @name Register SIM_SOPT2, field TIMESRC[21:20] (RW)
bogdanm 82:6473597d706e 702 *
bogdanm 82:6473597d706e 703 * Selects the clock source for the Ethernet timestamp clock.
bogdanm 82:6473597d706e 704 *
bogdanm 82:6473597d706e 705 * Values:
bogdanm 82:6473597d706e 706 * - 00 - Core/system clock.
bogdanm 82:6473597d706e 707 * - 01 - MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by
bogdanm 82:6473597d706e 708 * SOPT2[PLLFLLSEL].
bogdanm 82:6473597d706e 709 * - 10 - OSCERCLK clock
bogdanm 82:6473597d706e 710 * - 11 - External bypass clock (ENET_1588_CLKIN).
bogdanm 82:6473597d706e 711 */
bogdanm 82:6473597d706e 712 //@{
bogdanm 82:6473597d706e 713 #define BP_SIM_SOPT2_TIMESRC (20U) //!< Bit position for SIM_SOPT2_TIMESRC.
bogdanm 82:6473597d706e 714 #define BM_SIM_SOPT2_TIMESRC (0x00300000U) //!< Bit mask for SIM_SOPT2_TIMESRC.
bogdanm 82:6473597d706e 715 #define BS_SIM_SOPT2_TIMESRC (2U) //!< Bit field size in bits for SIM_SOPT2_TIMESRC.
bogdanm 82:6473597d706e 716
bogdanm 82:6473597d706e 717 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 718 //! @brief Read current value of the SIM_SOPT2_TIMESRC field.
bogdanm 82:6473597d706e 719 #define BR_SIM_SOPT2_TIMESRC (HW_SIM_SOPT2.B.TIMESRC)
bogdanm 82:6473597d706e 720 #endif
bogdanm 82:6473597d706e 721
bogdanm 82:6473597d706e 722 //! @brief Format value for bitfield SIM_SOPT2_TIMESRC.
bogdanm 82:6473597d706e 723 #define BF_SIM_SOPT2_TIMESRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_TIMESRC), uint32_t) & BM_SIM_SOPT2_TIMESRC)
bogdanm 82:6473597d706e 724
bogdanm 82:6473597d706e 725 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 726 //! @brief Set the TIMESRC field to a new value.
bogdanm 82:6473597d706e 727 #define BW_SIM_SOPT2_TIMESRC(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_TIMESRC) | BF_SIM_SOPT2_TIMESRC(v)))
bogdanm 82:6473597d706e 728 #endif
bogdanm 82:6473597d706e 729 //@}
bogdanm 82:6473597d706e 730
bogdanm 82:6473597d706e 731 /*!
bogdanm 82:6473597d706e 732 * @name Register SIM_SOPT2, field SDHCSRC[29:28] (RW)
bogdanm 82:6473597d706e 733 *
bogdanm 82:6473597d706e 734 * Selects the clock source for the SDHC clock .
bogdanm 82:6473597d706e 735 *
bogdanm 82:6473597d706e 736 * Values:
bogdanm 82:6473597d706e 737 * - 00 - Core/system clock.
bogdanm 82:6473597d706e 738 * - 01 - MCGFLLCLK, or MCGPLLCLK , or IRC48M clock as selected by
bogdanm 82:6473597d706e 739 * SOPT2[PLLFLLSEL].
bogdanm 82:6473597d706e 740 * - 10 - OSCERCLK clock
bogdanm 82:6473597d706e 741 * - 11 - External bypass clock (SDHC0_CLKIN)
bogdanm 82:6473597d706e 742 */
bogdanm 82:6473597d706e 743 //@{
bogdanm 82:6473597d706e 744 #define BP_SIM_SOPT2_SDHCSRC (28U) //!< Bit position for SIM_SOPT2_SDHCSRC.
bogdanm 82:6473597d706e 745 #define BM_SIM_SOPT2_SDHCSRC (0x30000000U) //!< Bit mask for SIM_SOPT2_SDHCSRC.
bogdanm 82:6473597d706e 746 #define BS_SIM_SOPT2_SDHCSRC (2U) //!< Bit field size in bits for SIM_SOPT2_SDHCSRC.
bogdanm 82:6473597d706e 747
bogdanm 82:6473597d706e 748 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 749 //! @brief Read current value of the SIM_SOPT2_SDHCSRC field.
bogdanm 82:6473597d706e 750 #define BR_SIM_SOPT2_SDHCSRC (HW_SIM_SOPT2.B.SDHCSRC)
bogdanm 82:6473597d706e 751 #endif
bogdanm 82:6473597d706e 752
bogdanm 82:6473597d706e 753 //! @brief Format value for bitfield SIM_SOPT2_SDHCSRC.
bogdanm 82:6473597d706e 754 #define BF_SIM_SOPT2_SDHCSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT2_SDHCSRC), uint32_t) & BM_SIM_SOPT2_SDHCSRC)
bogdanm 82:6473597d706e 755
bogdanm 82:6473597d706e 756 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 757 //! @brief Set the SDHCSRC field to a new value.
bogdanm 82:6473597d706e 758 #define BW_SIM_SOPT2_SDHCSRC(v) (HW_SIM_SOPT2_WR((HW_SIM_SOPT2_RD() & ~BM_SIM_SOPT2_SDHCSRC) | BF_SIM_SOPT2_SDHCSRC(v)))
bogdanm 82:6473597d706e 759 #endif
bogdanm 82:6473597d706e 760 //@}
bogdanm 82:6473597d706e 761
bogdanm 82:6473597d706e 762 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 763 // HW_SIM_SOPT4 - System Options Register 4
bogdanm 82:6473597d706e 764 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 765
bogdanm 82:6473597d706e 766 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 767 /*!
bogdanm 82:6473597d706e 768 * @brief HW_SIM_SOPT4 - System Options Register 4 (RW)
bogdanm 82:6473597d706e 769 *
bogdanm 82:6473597d706e 770 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 771 */
bogdanm 82:6473597d706e 772 typedef union _hw_sim_sopt4
bogdanm 82:6473597d706e 773 {
bogdanm 82:6473597d706e 774 uint32_t U;
bogdanm 82:6473597d706e 775 struct _hw_sim_sopt4_bitfields
bogdanm 82:6473597d706e 776 {
bogdanm 82:6473597d706e 777 uint32_t FTM0FLT0 : 1; //!< [0] FTM0 Fault 0 Select
bogdanm 82:6473597d706e 778 uint32_t FTM0FLT1 : 1; //!< [1] FTM0 Fault 1 Select
bogdanm 82:6473597d706e 779 uint32_t FTM0FLT2 : 1; //!< [2] FTM0 Fault 2 Select
bogdanm 82:6473597d706e 780 uint32_t RESERVED0 : 1; //!< [3]
bogdanm 82:6473597d706e 781 uint32_t FTM1FLT0 : 1; //!< [4] FTM1 Fault 0 Select
bogdanm 82:6473597d706e 782 uint32_t RESERVED1 : 3; //!< [7:5]
bogdanm 82:6473597d706e 783 uint32_t FTM2FLT0 : 1; //!< [8] FTM2 Fault 0 Select
bogdanm 82:6473597d706e 784 uint32_t RESERVED2 : 3; //!< [11:9]
bogdanm 82:6473597d706e 785 uint32_t FTM3FLT0 : 1; //!< [12] FTM3 Fault 0 Select
bogdanm 82:6473597d706e 786 uint32_t RESERVED3 : 5; //!< [17:13]
bogdanm 82:6473597d706e 787 uint32_t FTM1CH0SRC : 2; //!< [19:18] FTM1 channel 0 input capture
bogdanm 82:6473597d706e 788 //! source select
bogdanm 82:6473597d706e 789 uint32_t FTM2CH0SRC : 2; //!< [21:20] FTM2 channel 0 input capture
bogdanm 82:6473597d706e 790 //! source select
bogdanm 82:6473597d706e 791 uint32_t RESERVED4 : 2; //!< [23:22]
bogdanm 82:6473597d706e 792 uint32_t FTM0CLKSEL : 1; //!< [24] FlexTimer 0 External Clock Pin
bogdanm 82:6473597d706e 793 //! Select
bogdanm 82:6473597d706e 794 uint32_t FTM1CLKSEL : 1; //!< [25] FTM1 External Clock Pin Select
bogdanm 82:6473597d706e 795 uint32_t FTM2CLKSEL : 1; //!< [26] FlexTimer 2 External Clock Pin
bogdanm 82:6473597d706e 796 //! Select
bogdanm 82:6473597d706e 797 uint32_t FTM3CLKSEL : 1; //!< [27] FlexTimer 3 External Clock Pin
bogdanm 82:6473597d706e 798 //! Select
bogdanm 82:6473597d706e 799 uint32_t FTM0TRG0SRC : 1; //!< [28] FlexTimer 0 Hardware Trigger 0
bogdanm 82:6473597d706e 800 //! Source Select
bogdanm 82:6473597d706e 801 uint32_t FTM0TRG1SRC : 1; //!< [29] FlexTimer 0 Hardware Trigger 1
bogdanm 82:6473597d706e 802 //! Source Select
bogdanm 82:6473597d706e 803 uint32_t FTM3TRG0SRC : 1; //!< [30] FlexTimer 3 Hardware Trigger 0
bogdanm 82:6473597d706e 804 //! Source Select
bogdanm 82:6473597d706e 805 uint32_t FTM3TRG1SRC : 1; //!< [31] FlexTimer 3 Hardware Trigger 1
bogdanm 82:6473597d706e 806 //! Source Select
bogdanm 82:6473597d706e 807 } B;
bogdanm 82:6473597d706e 808 } hw_sim_sopt4_t;
bogdanm 82:6473597d706e 809 #endif
bogdanm 82:6473597d706e 810
bogdanm 82:6473597d706e 811 /*!
bogdanm 82:6473597d706e 812 * @name Constants and macros for entire SIM_SOPT4 register
bogdanm 82:6473597d706e 813 */
bogdanm 82:6473597d706e 814 //@{
bogdanm 82:6473597d706e 815 #define HW_SIM_SOPT4_ADDR (REGS_SIM_BASE + 0x100CU)
bogdanm 82:6473597d706e 816
bogdanm 82:6473597d706e 817 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 818 #define HW_SIM_SOPT4 (*(__IO hw_sim_sopt4_t *) HW_SIM_SOPT4_ADDR)
bogdanm 82:6473597d706e 819 #define HW_SIM_SOPT4_RD() (HW_SIM_SOPT4.U)
bogdanm 82:6473597d706e 820 #define HW_SIM_SOPT4_WR(v) (HW_SIM_SOPT4.U = (v))
bogdanm 82:6473597d706e 821 #define HW_SIM_SOPT4_SET(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() | (v)))
bogdanm 82:6473597d706e 822 #define HW_SIM_SOPT4_CLR(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() & ~(v)))
bogdanm 82:6473597d706e 823 #define HW_SIM_SOPT4_TOG(v) (HW_SIM_SOPT4_WR(HW_SIM_SOPT4_RD() ^ (v)))
bogdanm 82:6473597d706e 824 #endif
bogdanm 82:6473597d706e 825 //@}
bogdanm 82:6473597d706e 826
bogdanm 82:6473597d706e 827 /*
bogdanm 82:6473597d706e 828 * Constants & macros for individual SIM_SOPT4 bitfields
bogdanm 82:6473597d706e 829 */
bogdanm 82:6473597d706e 830
bogdanm 82:6473597d706e 831 /*!
bogdanm 82:6473597d706e 832 * @name Register SIM_SOPT4, field FTM0FLT0[0] (RW)
bogdanm 82:6473597d706e 833 *
bogdanm 82:6473597d706e 834 * Selects the source of FTM0 fault 0. The pin source for fault 0 must be
bogdanm 82:6473597d706e 835 * configured for the FTM module fault function through the appropriate pin control
bogdanm 82:6473597d706e 836 * register in the port control module.
bogdanm 82:6473597d706e 837 *
bogdanm 82:6473597d706e 838 * Values:
bogdanm 82:6473597d706e 839 * - 0 - FTM0_FLT0 pin
bogdanm 82:6473597d706e 840 * - 1 - CMP0 out
bogdanm 82:6473597d706e 841 */
bogdanm 82:6473597d706e 842 //@{
bogdanm 82:6473597d706e 843 #define BP_SIM_SOPT4_FTM0FLT0 (0U) //!< Bit position for SIM_SOPT4_FTM0FLT0.
bogdanm 82:6473597d706e 844 #define BM_SIM_SOPT4_FTM0FLT0 (0x00000001U) //!< Bit mask for SIM_SOPT4_FTM0FLT0.
bogdanm 82:6473597d706e 845 #define BS_SIM_SOPT4_FTM0FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT0.
bogdanm 82:6473597d706e 846
bogdanm 82:6473597d706e 847 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 848 //! @brief Read current value of the SIM_SOPT4_FTM0FLT0 field.
bogdanm 82:6473597d706e 849 #define BR_SIM_SOPT4_FTM0FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT0))
bogdanm 82:6473597d706e 850 #endif
bogdanm 82:6473597d706e 851
bogdanm 82:6473597d706e 852 //! @brief Format value for bitfield SIM_SOPT4_FTM0FLT0.
bogdanm 82:6473597d706e 853 #define BF_SIM_SOPT4_FTM0FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT0), uint32_t) & BM_SIM_SOPT4_FTM0FLT0)
bogdanm 82:6473597d706e 854
bogdanm 82:6473597d706e 855 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 856 //! @brief Set the FTM0FLT0 field to a new value.
bogdanm 82:6473597d706e 857 #define BW_SIM_SOPT4_FTM0FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT0) = (v))
bogdanm 82:6473597d706e 858 #endif
bogdanm 82:6473597d706e 859 //@}
bogdanm 82:6473597d706e 860
bogdanm 82:6473597d706e 861 /*!
bogdanm 82:6473597d706e 862 * @name Register SIM_SOPT4, field FTM0FLT1[1] (RW)
bogdanm 82:6473597d706e 863 *
bogdanm 82:6473597d706e 864 * Selects the source of FTM0 fault 1. The pin source for fault 1 must be
bogdanm 82:6473597d706e 865 * configured for the FTM module fault function through the appropriate pin control
bogdanm 82:6473597d706e 866 * register in the port control module.
bogdanm 82:6473597d706e 867 *
bogdanm 82:6473597d706e 868 * Values:
bogdanm 82:6473597d706e 869 * - 0 - FTM0_FLT1 pin
bogdanm 82:6473597d706e 870 * - 1 - CMP1 out
bogdanm 82:6473597d706e 871 */
bogdanm 82:6473597d706e 872 //@{
bogdanm 82:6473597d706e 873 #define BP_SIM_SOPT4_FTM0FLT1 (1U) //!< Bit position for SIM_SOPT4_FTM0FLT1.
bogdanm 82:6473597d706e 874 #define BM_SIM_SOPT4_FTM0FLT1 (0x00000002U) //!< Bit mask for SIM_SOPT4_FTM0FLT1.
bogdanm 82:6473597d706e 875 #define BS_SIM_SOPT4_FTM0FLT1 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT1.
bogdanm 82:6473597d706e 876
bogdanm 82:6473597d706e 877 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 878 //! @brief Read current value of the SIM_SOPT4_FTM0FLT1 field.
bogdanm 82:6473597d706e 879 #define BR_SIM_SOPT4_FTM0FLT1 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT1))
bogdanm 82:6473597d706e 880 #endif
bogdanm 82:6473597d706e 881
bogdanm 82:6473597d706e 882 //! @brief Format value for bitfield SIM_SOPT4_FTM0FLT1.
bogdanm 82:6473597d706e 883 #define BF_SIM_SOPT4_FTM0FLT1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT1), uint32_t) & BM_SIM_SOPT4_FTM0FLT1)
bogdanm 82:6473597d706e 884
bogdanm 82:6473597d706e 885 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 886 //! @brief Set the FTM0FLT1 field to a new value.
bogdanm 82:6473597d706e 887 #define BW_SIM_SOPT4_FTM0FLT1(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT1) = (v))
bogdanm 82:6473597d706e 888 #endif
bogdanm 82:6473597d706e 889 //@}
bogdanm 82:6473597d706e 890
bogdanm 82:6473597d706e 891 /*!
bogdanm 82:6473597d706e 892 * @name Register SIM_SOPT4, field FTM0FLT2[2] (RW)
bogdanm 82:6473597d706e 893 *
bogdanm 82:6473597d706e 894 * Selects the source of FTM0 fault 2. The pin source for fault 2 must be
bogdanm 82:6473597d706e 895 * configured for the FTM module fault function through the appropriate pin control
bogdanm 82:6473597d706e 896 * register in the port control module.
bogdanm 82:6473597d706e 897 *
bogdanm 82:6473597d706e 898 * Values:
bogdanm 82:6473597d706e 899 * - 0 - FTM0_FLT2 pin
bogdanm 82:6473597d706e 900 * - 1 - CMP2 out
bogdanm 82:6473597d706e 901 */
bogdanm 82:6473597d706e 902 //@{
bogdanm 82:6473597d706e 903 #define BP_SIM_SOPT4_FTM0FLT2 (2U) //!< Bit position for SIM_SOPT4_FTM0FLT2.
bogdanm 82:6473597d706e 904 #define BM_SIM_SOPT4_FTM0FLT2 (0x00000004U) //!< Bit mask for SIM_SOPT4_FTM0FLT2.
bogdanm 82:6473597d706e 905 #define BS_SIM_SOPT4_FTM0FLT2 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0FLT2.
bogdanm 82:6473597d706e 906
bogdanm 82:6473597d706e 907 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 908 //! @brief Read current value of the SIM_SOPT4_FTM0FLT2 field.
bogdanm 82:6473597d706e 909 #define BR_SIM_SOPT4_FTM0FLT2 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT2))
bogdanm 82:6473597d706e 910 #endif
bogdanm 82:6473597d706e 911
bogdanm 82:6473597d706e 912 //! @brief Format value for bitfield SIM_SOPT4_FTM0FLT2.
bogdanm 82:6473597d706e 913 #define BF_SIM_SOPT4_FTM0FLT2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0FLT2), uint32_t) & BM_SIM_SOPT4_FTM0FLT2)
bogdanm 82:6473597d706e 914
bogdanm 82:6473597d706e 915 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 916 //! @brief Set the FTM0FLT2 field to a new value.
bogdanm 82:6473597d706e 917 #define BW_SIM_SOPT4_FTM0FLT2(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0FLT2) = (v))
bogdanm 82:6473597d706e 918 #endif
bogdanm 82:6473597d706e 919 //@}
bogdanm 82:6473597d706e 920
bogdanm 82:6473597d706e 921 /*!
bogdanm 82:6473597d706e 922 * @name Register SIM_SOPT4, field FTM1FLT0[4] (RW)
bogdanm 82:6473597d706e 923 *
bogdanm 82:6473597d706e 924 * Selects the source of FTM1 fault 0. The pin source for fault 0 must be
bogdanm 82:6473597d706e 925 * configured for the FTM module fault function through the appropriate pin control
bogdanm 82:6473597d706e 926 * register in the port control module.
bogdanm 82:6473597d706e 927 *
bogdanm 82:6473597d706e 928 * Values:
bogdanm 82:6473597d706e 929 * - 0 - FTM1_FLT0 pin
bogdanm 82:6473597d706e 930 * - 1 - CMP0 out
bogdanm 82:6473597d706e 931 */
bogdanm 82:6473597d706e 932 //@{
bogdanm 82:6473597d706e 933 #define BP_SIM_SOPT4_FTM1FLT0 (4U) //!< Bit position for SIM_SOPT4_FTM1FLT0.
bogdanm 82:6473597d706e 934 #define BM_SIM_SOPT4_FTM1FLT0 (0x00000010U) //!< Bit mask for SIM_SOPT4_FTM1FLT0.
bogdanm 82:6473597d706e 935 #define BS_SIM_SOPT4_FTM1FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM1FLT0.
bogdanm 82:6473597d706e 936
bogdanm 82:6473597d706e 937 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 938 //! @brief Read current value of the SIM_SOPT4_FTM1FLT0 field.
bogdanm 82:6473597d706e 939 #define BR_SIM_SOPT4_FTM1FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1FLT0))
bogdanm 82:6473597d706e 940 #endif
bogdanm 82:6473597d706e 941
bogdanm 82:6473597d706e 942 //! @brief Format value for bitfield SIM_SOPT4_FTM1FLT0.
bogdanm 82:6473597d706e 943 #define BF_SIM_SOPT4_FTM1FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1FLT0), uint32_t) & BM_SIM_SOPT4_FTM1FLT0)
bogdanm 82:6473597d706e 944
bogdanm 82:6473597d706e 945 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 946 //! @brief Set the FTM1FLT0 field to a new value.
bogdanm 82:6473597d706e 947 #define BW_SIM_SOPT4_FTM1FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1FLT0) = (v))
bogdanm 82:6473597d706e 948 #endif
bogdanm 82:6473597d706e 949 //@}
bogdanm 82:6473597d706e 950
bogdanm 82:6473597d706e 951 /*!
bogdanm 82:6473597d706e 952 * @name Register SIM_SOPT4, field FTM2FLT0[8] (RW)
bogdanm 82:6473597d706e 953 *
bogdanm 82:6473597d706e 954 * Selects the source of FTM2 fault 0. The pin source for fault 0 must be
bogdanm 82:6473597d706e 955 * configured for the FTM module fault function through the appropriate PORTx pin
bogdanm 82:6473597d706e 956 * control register.
bogdanm 82:6473597d706e 957 *
bogdanm 82:6473597d706e 958 * Values:
bogdanm 82:6473597d706e 959 * - 0 - FTM2_FLT0 pin
bogdanm 82:6473597d706e 960 * - 1 - CMP0 out
bogdanm 82:6473597d706e 961 */
bogdanm 82:6473597d706e 962 //@{
bogdanm 82:6473597d706e 963 #define BP_SIM_SOPT4_FTM2FLT0 (8U) //!< Bit position for SIM_SOPT4_FTM2FLT0.
bogdanm 82:6473597d706e 964 #define BM_SIM_SOPT4_FTM2FLT0 (0x00000100U) //!< Bit mask for SIM_SOPT4_FTM2FLT0.
bogdanm 82:6473597d706e 965 #define BS_SIM_SOPT4_FTM2FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM2FLT0.
bogdanm 82:6473597d706e 966
bogdanm 82:6473597d706e 967 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 968 //! @brief Read current value of the SIM_SOPT4_FTM2FLT0 field.
bogdanm 82:6473597d706e 969 #define BR_SIM_SOPT4_FTM2FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2FLT0))
bogdanm 82:6473597d706e 970 #endif
bogdanm 82:6473597d706e 971
bogdanm 82:6473597d706e 972 //! @brief Format value for bitfield SIM_SOPT4_FTM2FLT0.
bogdanm 82:6473597d706e 973 #define BF_SIM_SOPT4_FTM2FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2FLT0), uint32_t) & BM_SIM_SOPT4_FTM2FLT0)
bogdanm 82:6473597d706e 974
bogdanm 82:6473597d706e 975 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 976 //! @brief Set the FTM2FLT0 field to a new value.
bogdanm 82:6473597d706e 977 #define BW_SIM_SOPT4_FTM2FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2FLT0) = (v))
bogdanm 82:6473597d706e 978 #endif
bogdanm 82:6473597d706e 979 //@}
bogdanm 82:6473597d706e 980
bogdanm 82:6473597d706e 981 /*!
bogdanm 82:6473597d706e 982 * @name Register SIM_SOPT4, field FTM3FLT0[12] (RW)
bogdanm 82:6473597d706e 983 *
bogdanm 82:6473597d706e 984 * Selects the source of FTM3 fault 0. The pin source for fault 0 must be
bogdanm 82:6473597d706e 985 * configured for the FTM module fault function through the appropriate PORTx pin
bogdanm 82:6473597d706e 986 * control register.
bogdanm 82:6473597d706e 987 *
bogdanm 82:6473597d706e 988 * Values:
bogdanm 82:6473597d706e 989 * - 0 - FTM3_FLT0 pin
bogdanm 82:6473597d706e 990 * - 1 - CMP0 out
bogdanm 82:6473597d706e 991 */
bogdanm 82:6473597d706e 992 //@{
bogdanm 82:6473597d706e 993 #define BP_SIM_SOPT4_FTM3FLT0 (12U) //!< Bit position for SIM_SOPT4_FTM3FLT0.
bogdanm 82:6473597d706e 994 #define BM_SIM_SOPT4_FTM3FLT0 (0x00001000U) //!< Bit mask for SIM_SOPT4_FTM3FLT0.
bogdanm 82:6473597d706e 995 #define BS_SIM_SOPT4_FTM3FLT0 (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3FLT0.
bogdanm 82:6473597d706e 996
bogdanm 82:6473597d706e 997 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 998 //! @brief Read current value of the SIM_SOPT4_FTM3FLT0 field.
bogdanm 82:6473597d706e 999 #define BR_SIM_SOPT4_FTM3FLT0 (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3FLT0))
bogdanm 82:6473597d706e 1000 #endif
bogdanm 82:6473597d706e 1001
bogdanm 82:6473597d706e 1002 //! @brief Format value for bitfield SIM_SOPT4_FTM3FLT0.
bogdanm 82:6473597d706e 1003 #define BF_SIM_SOPT4_FTM3FLT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3FLT0), uint32_t) & BM_SIM_SOPT4_FTM3FLT0)
bogdanm 82:6473597d706e 1004
bogdanm 82:6473597d706e 1005 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1006 //! @brief Set the FTM3FLT0 field to a new value.
bogdanm 82:6473597d706e 1007 #define BW_SIM_SOPT4_FTM3FLT0(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3FLT0) = (v))
bogdanm 82:6473597d706e 1008 #endif
bogdanm 82:6473597d706e 1009 //@}
bogdanm 82:6473597d706e 1010
bogdanm 82:6473597d706e 1011 /*!
bogdanm 82:6473597d706e 1012 * @name Register SIM_SOPT4, field FTM1CH0SRC[19:18] (RW)
bogdanm 82:6473597d706e 1013 *
bogdanm 82:6473597d706e 1014 * Selects the source for FTM1 channel 0 input capture. When the FTM is not in
bogdanm 82:6473597d706e 1015 * input capture mode, clear this field.
bogdanm 82:6473597d706e 1016 *
bogdanm 82:6473597d706e 1017 * Values:
bogdanm 82:6473597d706e 1018 * - 00 - FTM1_CH0 signal
bogdanm 82:6473597d706e 1019 * - 01 - CMP0 output
bogdanm 82:6473597d706e 1020 * - 10 - CMP1 output
bogdanm 82:6473597d706e 1021 * - 11 - USB start of frame pulse
bogdanm 82:6473597d706e 1022 */
bogdanm 82:6473597d706e 1023 //@{
bogdanm 82:6473597d706e 1024 #define BP_SIM_SOPT4_FTM1CH0SRC (18U) //!< Bit position for SIM_SOPT4_FTM1CH0SRC.
bogdanm 82:6473597d706e 1025 #define BM_SIM_SOPT4_FTM1CH0SRC (0x000C0000U) //!< Bit mask for SIM_SOPT4_FTM1CH0SRC.
bogdanm 82:6473597d706e 1026 #define BS_SIM_SOPT4_FTM1CH0SRC (2U) //!< Bit field size in bits for SIM_SOPT4_FTM1CH0SRC.
bogdanm 82:6473597d706e 1027
bogdanm 82:6473597d706e 1028 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1029 //! @brief Read current value of the SIM_SOPT4_FTM1CH0SRC field.
bogdanm 82:6473597d706e 1030 #define BR_SIM_SOPT4_FTM1CH0SRC (HW_SIM_SOPT4.B.FTM1CH0SRC)
bogdanm 82:6473597d706e 1031 #endif
bogdanm 82:6473597d706e 1032
bogdanm 82:6473597d706e 1033 //! @brief Format value for bitfield SIM_SOPT4_FTM1CH0SRC.
bogdanm 82:6473597d706e 1034 #define BF_SIM_SOPT4_FTM1CH0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1CH0SRC), uint32_t) & BM_SIM_SOPT4_FTM1CH0SRC)
bogdanm 82:6473597d706e 1035
bogdanm 82:6473597d706e 1036 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1037 //! @brief Set the FTM1CH0SRC field to a new value.
bogdanm 82:6473597d706e 1038 #define BW_SIM_SOPT4_FTM1CH0SRC(v) (HW_SIM_SOPT4_WR((HW_SIM_SOPT4_RD() & ~BM_SIM_SOPT4_FTM1CH0SRC) | BF_SIM_SOPT4_FTM1CH0SRC(v)))
bogdanm 82:6473597d706e 1039 #endif
bogdanm 82:6473597d706e 1040 //@}
bogdanm 82:6473597d706e 1041
bogdanm 82:6473597d706e 1042 /*!
bogdanm 82:6473597d706e 1043 * @name Register SIM_SOPT4, field FTM2CH0SRC[21:20] (RW)
bogdanm 82:6473597d706e 1044 *
bogdanm 82:6473597d706e 1045 * Selects the source for FTM2 channel 0 input capture. When the FTM is not in
bogdanm 82:6473597d706e 1046 * input capture mode, clear this field.
bogdanm 82:6473597d706e 1047 *
bogdanm 82:6473597d706e 1048 * Values:
bogdanm 82:6473597d706e 1049 * - 00 - FTM2_CH0 signal
bogdanm 82:6473597d706e 1050 * - 01 - CMP0 output
bogdanm 82:6473597d706e 1051 * - 10 - CMP1 output
bogdanm 82:6473597d706e 1052 * - 11 - Reserved
bogdanm 82:6473597d706e 1053 */
bogdanm 82:6473597d706e 1054 //@{
bogdanm 82:6473597d706e 1055 #define BP_SIM_SOPT4_FTM2CH0SRC (20U) //!< Bit position for SIM_SOPT4_FTM2CH0SRC.
bogdanm 82:6473597d706e 1056 #define BM_SIM_SOPT4_FTM2CH0SRC (0x00300000U) //!< Bit mask for SIM_SOPT4_FTM2CH0SRC.
bogdanm 82:6473597d706e 1057 #define BS_SIM_SOPT4_FTM2CH0SRC (2U) //!< Bit field size in bits for SIM_SOPT4_FTM2CH0SRC.
bogdanm 82:6473597d706e 1058
bogdanm 82:6473597d706e 1059 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1060 //! @brief Read current value of the SIM_SOPT4_FTM2CH0SRC field.
bogdanm 82:6473597d706e 1061 #define BR_SIM_SOPT4_FTM2CH0SRC (HW_SIM_SOPT4.B.FTM2CH0SRC)
bogdanm 82:6473597d706e 1062 #endif
bogdanm 82:6473597d706e 1063
bogdanm 82:6473597d706e 1064 //! @brief Format value for bitfield SIM_SOPT4_FTM2CH0SRC.
bogdanm 82:6473597d706e 1065 #define BF_SIM_SOPT4_FTM2CH0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2CH0SRC), uint32_t) & BM_SIM_SOPT4_FTM2CH0SRC)
bogdanm 82:6473597d706e 1066
bogdanm 82:6473597d706e 1067 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1068 //! @brief Set the FTM2CH0SRC field to a new value.
bogdanm 82:6473597d706e 1069 #define BW_SIM_SOPT4_FTM2CH0SRC(v) (HW_SIM_SOPT4_WR((HW_SIM_SOPT4_RD() & ~BM_SIM_SOPT4_FTM2CH0SRC) | BF_SIM_SOPT4_FTM2CH0SRC(v)))
bogdanm 82:6473597d706e 1070 #endif
bogdanm 82:6473597d706e 1071 //@}
bogdanm 82:6473597d706e 1072
bogdanm 82:6473597d706e 1073 /*!
bogdanm 82:6473597d706e 1074 * @name Register SIM_SOPT4, field FTM0CLKSEL[24] (RW)
bogdanm 82:6473597d706e 1075 *
bogdanm 82:6473597d706e 1076 * Selects the external pin used to drive the clock to the FTM0 module. The
bogdanm 82:6473597d706e 1077 * selected pin must also be configured for the FTM external clock function through
bogdanm 82:6473597d706e 1078 * the appropriate pin control register in the port control module.
bogdanm 82:6473597d706e 1079 *
bogdanm 82:6473597d706e 1080 * Values:
bogdanm 82:6473597d706e 1081 * - 0 - FTM_CLK0 pin
bogdanm 82:6473597d706e 1082 * - 1 - FTM_CLK1 pin
bogdanm 82:6473597d706e 1083 */
bogdanm 82:6473597d706e 1084 //@{
bogdanm 82:6473597d706e 1085 #define BP_SIM_SOPT4_FTM0CLKSEL (24U) //!< Bit position for SIM_SOPT4_FTM0CLKSEL.
bogdanm 82:6473597d706e 1086 #define BM_SIM_SOPT4_FTM0CLKSEL (0x01000000U) //!< Bit mask for SIM_SOPT4_FTM0CLKSEL.
bogdanm 82:6473597d706e 1087 #define BS_SIM_SOPT4_FTM0CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0CLKSEL.
bogdanm 82:6473597d706e 1088
bogdanm 82:6473597d706e 1089 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1090 //! @brief Read current value of the SIM_SOPT4_FTM0CLKSEL field.
bogdanm 82:6473597d706e 1091 #define BR_SIM_SOPT4_FTM0CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0CLKSEL))
bogdanm 82:6473597d706e 1092 #endif
bogdanm 82:6473597d706e 1093
bogdanm 82:6473597d706e 1094 //! @brief Format value for bitfield SIM_SOPT4_FTM0CLKSEL.
bogdanm 82:6473597d706e 1095 #define BF_SIM_SOPT4_FTM0CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM0CLKSEL)
bogdanm 82:6473597d706e 1096
bogdanm 82:6473597d706e 1097 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1098 //! @brief Set the FTM0CLKSEL field to a new value.
bogdanm 82:6473597d706e 1099 #define BW_SIM_SOPT4_FTM0CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0CLKSEL) = (v))
bogdanm 82:6473597d706e 1100 #endif
bogdanm 82:6473597d706e 1101 //@}
bogdanm 82:6473597d706e 1102
bogdanm 82:6473597d706e 1103 /*!
bogdanm 82:6473597d706e 1104 * @name Register SIM_SOPT4, field FTM1CLKSEL[25] (RW)
bogdanm 82:6473597d706e 1105 *
bogdanm 82:6473597d706e 1106 * Selects the external pin used to drive the clock to the FTM1 module. The
bogdanm 82:6473597d706e 1107 * selected pin must also be configured for the FTM external clock function through
bogdanm 82:6473597d706e 1108 * the appropriate pin control register in the port control module.
bogdanm 82:6473597d706e 1109 *
bogdanm 82:6473597d706e 1110 * Values:
bogdanm 82:6473597d706e 1111 * - 0 - FTM_CLK0 pin
bogdanm 82:6473597d706e 1112 * - 1 - FTM_CLK1 pin
bogdanm 82:6473597d706e 1113 */
bogdanm 82:6473597d706e 1114 //@{
bogdanm 82:6473597d706e 1115 #define BP_SIM_SOPT4_FTM1CLKSEL (25U) //!< Bit position for SIM_SOPT4_FTM1CLKSEL.
bogdanm 82:6473597d706e 1116 #define BM_SIM_SOPT4_FTM1CLKSEL (0x02000000U) //!< Bit mask for SIM_SOPT4_FTM1CLKSEL.
bogdanm 82:6473597d706e 1117 #define BS_SIM_SOPT4_FTM1CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM1CLKSEL.
bogdanm 82:6473597d706e 1118
bogdanm 82:6473597d706e 1119 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1120 //! @brief Read current value of the SIM_SOPT4_FTM1CLKSEL field.
bogdanm 82:6473597d706e 1121 #define BR_SIM_SOPT4_FTM1CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1CLKSEL))
bogdanm 82:6473597d706e 1122 #endif
bogdanm 82:6473597d706e 1123
bogdanm 82:6473597d706e 1124 //! @brief Format value for bitfield SIM_SOPT4_FTM1CLKSEL.
bogdanm 82:6473597d706e 1125 #define BF_SIM_SOPT4_FTM1CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM1CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM1CLKSEL)
bogdanm 82:6473597d706e 1126
bogdanm 82:6473597d706e 1127 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1128 //! @brief Set the FTM1CLKSEL field to a new value.
bogdanm 82:6473597d706e 1129 #define BW_SIM_SOPT4_FTM1CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM1CLKSEL) = (v))
bogdanm 82:6473597d706e 1130 #endif
bogdanm 82:6473597d706e 1131 //@}
bogdanm 82:6473597d706e 1132
bogdanm 82:6473597d706e 1133 /*!
bogdanm 82:6473597d706e 1134 * @name Register SIM_SOPT4, field FTM2CLKSEL[26] (RW)
bogdanm 82:6473597d706e 1135 *
bogdanm 82:6473597d706e 1136 * Selects the external pin used to drive the clock to the FTM2 module. The
bogdanm 82:6473597d706e 1137 * selected pin must also be configured for the FTM2 module external clock function
bogdanm 82:6473597d706e 1138 * through the appropriate pin control register in the port control module.
bogdanm 82:6473597d706e 1139 *
bogdanm 82:6473597d706e 1140 * Values:
bogdanm 82:6473597d706e 1141 * - 0 - FTM2 external clock driven by FTM_CLK0 pin.
bogdanm 82:6473597d706e 1142 * - 1 - FTM2 external clock driven by FTM_CLK1 pin.
bogdanm 82:6473597d706e 1143 */
bogdanm 82:6473597d706e 1144 //@{
bogdanm 82:6473597d706e 1145 #define BP_SIM_SOPT4_FTM2CLKSEL (26U) //!< Bit position for SIM_SOPT4_FTM2CLKSEL.
bogdanm 82:6473597d706e 1146 #define BM_SIM_SOPT4_FTM2CLKSEL (0x04000000U) //!< Bit mask for SIM_SOPT4_FTM2CLKSEL.
bogdanm 82:6473597d706e 1147 #define BS_SIM_SOPT4_FTM2CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM2CLKSEL.
bogdanm 82:6473597d706e 1148
bogdanm 82:6473597d706e 1149 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1150 //! @brief Read current value of the SIM_SOPT4_FTM2CLKSEL field.
bogdanm 82:6473597d706e 1151 #define BR_SIM_SOPT4_FTM2CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2CLKSEL))
bogdanm 82:6473597d706e 1152 #endif
bogdanm 82:6473597d706e 1153
bogdanm 82:6473597d706e 1154 //! @brief Format value for bitfield SIM_SOPT4_FTM2CLKSEL.
bogdanm 82:6473597d706e 1155 #define BF_SIM_SOPT4_FTM2CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM2CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM2CLKSEL)
bogdanm 82:6473597d706e 1156
bogdanm 82:6473597d706e 1157 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1158 //! @brief Set the FTM2CLKSEL field to a new value.
bogdanm 82:6473597d706e 1159 #define BW_SIM_SOPT4_FTM2CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM2CLKSEL) = (v))
bogdanm 82:6473597d706e 1160 #endif
bogdanm 82:6473597d706e 1161 //@}
bogdanm 82:6473597d706e 1162
bogdanm 82:6473597d706e 1163 /*!
bogdanm 82:6473597d706e 1164 * @name Register SIM_SOPT4, field FTM3CLKSEL[27] (RW)
bogdanm 82:6473597d706e 1165 *
bogdanm 82:6473597d706e 1166 * Selects the external pin used to drive the clock to the FTM3 module. The
bogdanm 82:6473597d706e 1167 * selected pin must also be configured for the FTM3 module external clock function
bogdanm 82:6473597d706e 1168 * through the appropriate pin control register in the port control module.
bogdanm 82:6473597d706e 1169 *
bogdanm 82:6473597d706e 1170 * Values:
bogdanm 82:6473597d706e 1171 * - 0 - FTM3 external clock driven by FTM_CLK0 pin.
bogdanm 82:6473597d706e 1172 * - 1 - FTM3 external clock driven by FTM_CLK1 pin.
bogdanm 82:6473597d706e 1173 */
bogdanm 82:6473597d706e 1174 //@{
bogdanm 82:6473597d706e 1175 #define BP_SIM_SOPT4_FTM3CLKSEL (27U) //!< Bit position for SIM_SOPT4_FTM3CLKSEL.
bogdanm 82:6473597d706e 1176 #define BM_SIM_SOPT4_FTM3CLKSEL (0x08000000U) //!< Bit mask for SIM_SOPT4_FTM3CLKSEL.
bogdanm 82:6473597d706e 1177 #define BS_SIM_SOPT4_FTM3CLKSEL (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3CLKSEL.
bogdanm 82:6473597d706e 1178
bogdanm 82:6473597d706e 1179 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1180 //! @brief Read current value of the SIM_SOPT4_FTM3CLKSEL field.
bogdanm 82:6473597d706e 1181 #define BR_SIM_SOPT4_FTM3CLKSEL (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3CLKSEL))
bogdanm 82:6473597d706e 1182 #endif
bogdanm 82:6473597d706e 1183
bogdanm 82:6473597d706e 1184 //! @brief Format value for bitfield SIM_SOPT4_FTM3CLKSEL.
bogdanm 82:6473597d706e 1185 #define BF_SIM_SOPT4_FTM3CLKSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3CLKSEL), uint32_t) & BM_SIM_SOPT4_FTM3CLKSEL)
bogdanm 82:6473597d706e 1186
bogdanm 82:6473597d706e 1187 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1188 //! @brief Set the FTM3CLKSEL field to a new value.
bogdanm 82:6473597d706e 1189 #define BW_SIM_SOPT4_FTM3CLKSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3CLKSEL) = (v))
bogdanm 82:6473597d706e 1190 #endif
bogdanm 82:6473597d706e 1191 //@}
bogdanm 82:6473597d706e 1192
bogdanm 82:6473597d706e 1193 /*!
bogdanm 82:6473597d706e 1194 * @name Register SIM_SOPT4, field FTM0TRG0SRC[28] (RW)
bogdanm 82:6473597d706e 1195 *
bogdanm 82:6473597d706e 1196 * Selects the source of FTM0 hardware trigger 0.
bogdanm 82:6473597d706e 1197 *
bogdanm 82:6473597d706e 1198 * Values:
bogdanm 82:6473597d706e 1199 * - 0 - HSCMP0 output drives FTM0 hardware trigger 0
bogdanm 82:6473597d706e 1200 * - 1 - FTM1 channel match drives FTM0 hardware trigger 0
bogdanm 82:6473597d706e 1201 */
bogdanm 82:6473597d706e 1202 //@{
bogdanm 82:6473597d706e 1203 #define BP_SIM_SOPT4_FTM0TRG0SRC (28U) //!< Bit position for SIM_SOPT4_FTM0TRG0SRC.
bogdanm 82:6473597d706e 1204 #define BM_SIM_SOPT4_FTM0TRG0SRC (0x10000000U) //!< Bit mask for SIM_SOPT4_FTM0TRG0SRC.
bogdanm 82:6473597d706e 1205 #define BS_SIM_SOPT4_FTM0TRG0SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0TRG0SRC.
bogdanm 82:6473597d706e 1206
bogdanm 82:6473597d706e 1207 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1208 //! @brief Read current value of the SIM_SOPT4_FTM0TRG0SRC field.
bogdanm 82:6473597d706e 1209 #define BR_SIM_SOPT4_FTM0TRG0SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG0SRC))
bogdanm 82:6473597d706e 1210 #endif
bogdanm 82:6473597d706e 1211
bogdanm 82:6473597d706e 1212 //! @brief Format value for bitfield SIM_SOPT4_FTM0TRG0SRC.
bogdanm 82:6473597d706e 1213 #define BF_SIM_SOPT4_FTM0TRG0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0TRG0SRC), uint32_t) & BM_SIM_SOPT4_FTM0TRG0SRC)
bogdanm 82:6473597d706e 1214
bogdanm 82:6473597d706e 1215 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1216 //! @brief Set the FTM0TRG0SRC field to a new value.
bogdanm 82:6473597d706e 1217 #define BW_SIM_SOPT4_FTM0TRG0SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG0SRC) = (v))
bogdanm 82:6473597d706e 1218 #endif
bogdanm 82:6473597d706e 1219 //@}
bogdanm 82:6473597d706e 1220
bogdanm 82:6473597d706e 1221 /*!
bogdanm 82:6473597d706e 1222 * @name Register SIM_SOPT4, field FTM0TRG1SRC[29] (RW)
bogdanm 82:6473597d706e 1223 *
bogdanm 82:6473597d706e 1224 * Selects the source of FTM0 hardware trigger 1.
bogdanm 82:6473597d706e 1225 *
bogdanm 82:6473597d706e 1226 * Values:
bogdanm 82:6473597d706e 1227 * - 0 - PDB output trigger 1 drives FTM0 hardware trigger 1
bogdanm 82:6473597d706e 1228 * - 1 - FTM2 channel match drives FTM0 hardware trigger 1
bogdanm 82:6473597d706e 1229 */
bogdanm 82:6473597d706e 1230 //@{
bogdanm 82:6473597d706e 1231 #define BP_SIM_SOPT4_FTM0TRG1SRC (29U) //!< Bit position for SIM_SOPT4_FTM0TRG1SRC.
bogdanm 82:6473597d706e 1232 #define BM_SIM_SOPT4_FTM0TRG1SRC (0x20000000U) //!< Bit mask for SIM_SOPT4_FTM0TRG1SRC.
bogdanm 82:6473597d706e 1233 #define BS_SIM_SOPT4_FTM0TRG1SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM0TRG1SRC.
bogdanm 82:6473597d706e 1234
bogdanm 82:6473597d706e 1235 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1236 //! @brief Read current value of the SIM_SOPT4_FTM0TRG1SRC field.
bogdanm 82:6473597d706e 1237 #define BR_SIM_SOPT4_FTM0TRG1SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG1SRC))
bogdanm 82:6473597d706e 1238 #endif
bogdanm 82:6473597d706e 1239
bogdanm 82:6473597d706e 1240 //! @brief Format value for bitfield SIM_SOPT4_FTM0TRG1SRC.
bogdanm 82:6473597d706e 1241 #define BF_SIM_SOPT4_FTM0TRG1SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM0TRG1SRC), uint32_t) & BM_SIM_SOPT4_FTM0TRG1SRC)
bogdanm 82:6473597d706e 1242
bogdanm 82:6473597d706e 1243 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1244 //! @brief Set the FTM0TRG1SRC field to a new value.
bogdanm 82:6473597d706e 1245 #define BW_SIM_SOPT4_FTM0TRG1SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM0TRG1SRC) = (v))
bogdanm 82:6473597d706e 1246 #endif
bogdanm 82:6473597d706e 1247 //@}
bogdanm 82:6473597d706e 1248
bogdanm 82:6473597d706e 1249 /*!
bogdanm 82:6473597d706e 1250 * @name Register SIM_SOPT4, field FTM3TRG0SRC[30] (RW)
bogdanm 82:6473597d706e 1251 *
bogdanm 82:6473597d706e 1252 * Selects the source of FTM3 hardware trigger 0.
bogdanm 82:6473597d706e 1253 *
bogdanm 82:6473597d706e 1254 * Values:
bogdanm 82:6473597d706e 1255 * - 0 - Reserved
bogdanm 82:6473597d706e 1256 * - 1 - FTM1 channel match drives FTM3 hardware trigger 0
bogdanm 82:6473597d706e 1257 */
bogdanm 82:6473597d706e 1258 //@{
bogdanm 82:6473597d706e 1259 #define BP_SIM_SOPT4_FTM3TRG0SRC (30U) //!< Bit position for SIM_SOPT4_FTM3TRG0SRC.
bogdanm 82:6473597d706e 1260 #define BM_SIM_SOPT4_FTM3TRG0SRC (0x40000000U) //!< Bit mask for SIM_SOPT4_FTM3TRG0SRC.
bogdanm 82:6473597d706e 1261 #define BS_SIM_SOPT4_FTM3TRG0SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3TRG0SRC.
bogdanm 82:6473597d706e 1262
bogdanm 82:6473597d706e 1263 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1264 //! @brief Read current value of the SIM_SOPT4_FTM3TRG0SRC field.
bogdanm 82:6473597d706e 1265 #define BR_SIM_SOPT4_FTM3TRG0SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG0SRC))
bogdanm 82:6473597d706e 1266 #endif
bogdanm 82:6473597d706e 1267
bogdanm 82:6473597d706e 1268 //! @brief Format value for bitfield SIM_SOPT4_FTM3TRG0SRC.
bogdanm 82:6473597d706e 1269 #define BF_SIM_SOPT4_FTM3TRG0SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3TRG0SRC), uint32_t) & BM_SIM_SOPT4_FTM3TRG0SRC)
bogdanm 82:6473597d706e 1270
bogdanm 82:6473597d706e 1271 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1272 //! @brief Set the FTM3TRG0SRC field to a new value.
bogdanm 82:6473597d706e 1273 #define BW_SIM_SOPT4_FTM3TRG0SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG0SRC) = (v))
bogdanm 82:6473597d706e 1274 #endif
bogdanm 82:6473597d706e 1275 //@}
bogdanm 82:6473597d706e 1276
bogdanm 82:6473597d706e 1277 /*!
bogdanm 82:6473597d706e 1278 * @name Register SIM_SOPT4, field FTM3TRG1SRC[31] (RW)
bogdanm 82:6473597d706e 1279 *
bogdanm 82:6473597d706e 1280 * Selects the source of FTM3 hardware trigger 1.
bogdanm 82:6473597d706e 1281 *
bogdanm 82:6473597d706e 1282 * Values:
bogdanm 82:6473597d706e 1283 * - 0 - Reserved
bogdanm 82:6473597d706e 1284 * - 1 - FTM2 channel match drives FTM3 hardware trigger 1
bogdanm 82:6473597d706e 1285 */
bogdanm 82:6473597d706e 1286 //@{
bogdanm 82:6473597d706e 1287 #define BP_SIM_SOPT4_FTM3TRG1SRC (31U) //!< Bit position for SIM_SOPT4_FTM3TRG1SRC.
bogdanm 82:6473597d706e 1288 #define BM_SIM_SOPT4_FTM3TRG1SRC (0x80000000U) //!< Bit mask for SIM_SOPT4_FTM3TRG1SRC.
bogdanm 82:6473597d706e 1289 #define BS_SIM_SOPT4_FTM3TRG1SRC (1U) //!< Bit field size in bits for SIM_SOPT4_FTM3TRG1SRC.
bogdanm 82:6473597d706e 1290
bogdanm 82:6473597d706e 1291 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1292 //! @brief Read current value of the SIM_SOPT4_FTM3TRG1SRC field.
bogdanm 82:6473597d706e 1293 #define BR_SIM_SOPT4_FTM3TRG1SRC (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG1SRC))
bogdanm 82:6473597d706e 1294 #endif
bogdanm 82:6473597d706e 1295
bogdanm 82:6473597d706e 1296 //! @brief Format value for bitfield SIM_SOPT4_FTM3TRG1SRC.
bogdanm 82:6473597d706e 1297 #define BF_SIM_SOPT4_FTM3TRG1SRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT4_FTM3TRG1SRC), uint32_t) & BM_SIM_SOPT4_FTM3TRG1SRC)
bogdanm 82:6473597d706e 1298
bogdanm 82:6473597d706e 1299 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1300 //! @brief Set the FTM3TRG1SRC field to a new value.
bogdanm 82:6473597d706e 1301 #define BW_SIM_SOPT4_FTM3TRG1SRC(v) (BITBAND_ACCESS32(HW_SIM_SOPT4_ADDR, BP_SIM_SOPT4_FTM3TRG1SRC) = (v))
bogdanm 82:6473597d706e 1302 #endif
bogdanm 82:6473597d706e 1303 //@}
bogdanm 82:6473597d706e 1304
bogdanm 82:6473597d706e 1305 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1306 // HW_SIM_SOPT5 - System Options Register 5
bogdanm 82:6473597d706e 1307 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1308
bogdanm 82:6473597d706e 1309 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1310 /*!
bogdanm 82:6473597d706e 1311 * @brief HW_SIM_SOPT5 - System Options Register 5 (RW)
bogdanm 82:6473597d706e 1312 *
bogdanm 82:6473597d706e 1313 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 1314 */
bogdanm 82:6473597d706e 1315 typedef union _hw_sim_sopt5
bogdanm 82:6473597d706e 1316 {
bogdanm 82:6473597d706e 1317 uint32_t U;
bogdanm 82:6473597d706e 1318 struct _hw_sim_sopt5_bitfields
bogdanm 82:6473597d706e 1319 {
bogdanm 82:6473597d706e 1320 uint32_t UART0TXSRC : 2; //!< [1:0] UART 0 transmit data source select
bogdanm 82:6473597d706e 1321 uint32_t UART0RXSRC : 2; //!< [3:2] UART 0 receive data source select
bogdanm 82:6473597d706e 1322 uint32_t UART1TXSRC : 2; //!< [5:4] UART 1 transmit data source select
bogdanm 82:6473597d706e 1323 uint32_t UART1RXSRC : 2; //!< [7:6] UART 1 receive data source select
bogdanm 82:6473597d706e 1324 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 1325 } B;
bogdanm 82:6473597d706e 1326 } hw_sim_sopt5_t;
bogdanm 82:6473597d706e 1327 #endif
bogdanm 82:6473597d706e 1328
bogdanm 82:6473597d706e 1329 /*!
bogdanm 82:6473597d706e 1330 * @name Constants and macros for entire SIM_SOPT5 register
bogdanm 82:6473597d706e 1331 */
bogdanm 82:6473597d706e 1332 //@{
bogdanm 82:6473597d706e 1333 #define HW_SIM_SOPT5_ADDR (REGS_SIM_BASE + 0x1010U)
bogdanm 82:6473597d706e 1334
bogdanm 82:6473597d706e 1335 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1336 #define HW_SIM_SOPT5 (*(__IO hw_sim_sopt5_t *) HW_SIM_SOPT5_ADDR)
bogdanm 82:6473597d706e 1337 #define HW_SIM_SOPT5_RD() (HW_SIM_SOPT5.U)
bogdanm 82:6473597d706e 1338 #define HW_SIM_SOPT5_WR(v) (HW_SIM_SOPT5.U = (v))
bogdanm 82:6473597d706e 1339 #define HW_SIM_SOPT5_SET(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() | (v)))
bogdanm 82:6473597d706e 1340 #define HW_SIM_SOPT5_CLR(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() & ~(v)))
bogdanm 82:6473597d706e 1341 #define HW_SIM_SOPT5_TOG(v) (HW_SIM_SOPT5_WR(HW_SIM_SOPT5_RD() ^ (v)))
bogdanm 82:6473597d706e 1342 #endif
bogdanm 82:6473597d706e 1343 //@}
bogdanm 82:6473597d706e 1344
bogdanm 82:6473597d706e 1345 /*
bogdanm 82:6473597d706e 1346 * Constants & macros for individual SIM_SOPT5 bitfields
bogdanm 82:6473597d706e 1347 */
bogdanm 82:6473597d706e 1348
bogdanm 82:6473597d706e 1349 /*!
bogdanm 82:6473597d706e 1350 * @name Register SIM_SOPT5, field UART0TXSRC[1:0] (RW)
bogdanm 82:6473597d706e 1351 *
bogdanm 82:6473597d706e 1352 * Selects the source for the UART 0 transmit data.
bogdanm 82:6473597d706e 1353 *
bogdanm 82:6473597d706e 1354 * Values:
bogdanm 82:6473597d706e 1355 * - 00 - UART0_TX pin
bogdanm 82:6473597d706e 1356 * - 01 - UART0_TX pin modulated with FTM1 channel 0 output
bogdanm 82:6473597d706e 1357 * - 10 - UART0_TX pin modulated with FTM2 channel 0 output
bogdanm 82:6473597d706e 1358 * - 11 - Reserved
bogdanm 82:6473597d706e 1359 */
bogdanm 82:6473597d706e 1360 //@{
bogdanm 82:6473597d706e 1361 #define BP_SIM_SOPT5_UART0TXSRC (0U) //!< Bit position for SIM_SOPT5_UART0TXSRC.
bogdanm 82:6473597d706e 1362 #define BM_SIM_SOPT5_UART0TXSRC (0x00000003U) //!< Bit mask for SIM_SOPT5_UART0TXSRC.
bogdanm 82:6473597d706e 1363 #define BS_SIM_SOPT5_UART0TXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART0TXSRC.
bogdanm 82:6473597d706e 1364
bogdanm 82:6473597d706e 1365 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1366 //! @brief Read current value of the SIM_SOPT5_UART0TXSRC field.
bogdanm 82:6473597d706e 1367 #define BR_SIM_SOPT5_UART0TXSRC (HW_SIM_SOPT5.B.UART0TXSRC)
bogdanm 82:6473597d706e 1368 #endif
bogdanm 82:6473597d706e 1369
bogdanm 82:6473597d706e 1370 //! @brief Format value for bitfield SIM_SOPT5_UART0TXSRC.
bogdanm 82:6473597d706e 1371 #define BF_SIM_SOPT5_UART0TXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART0TXSRC), uint32_t) & BM_SIM_SOPT5_UART0TXSRC)
bogdanm 82:6473597d706e 1372
bogdanm 82:6473597d706e 1373 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1374 //! @brief Set the UART0TXSRC field to a new value.
bogdanm 82:6473597d706e 1375 #define BW_SIM_SOPT5_UART0TXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART0TXSRC) | BF_SIM_SOPT5_UART0TXSRC(v)))
bogdanm 82:6473597d706e 1376 #endif
bogdanm 82:6473597d706e 1377 //@}
bogdanm 82:6473597d706e 1378
bogdanm 82:6473597d706e 1379 /*!
bogdanm 82:6473597d706e 1380 * @name Register SIM_SOPT5, field UART0RXSRC[3:2] (RW)
bogdanm 82:6473597d706e 1381 *
bogdanm 82:6473597d706e 1382 * Selects the source for the UART 0 receive data.
bogdanm 82:6473597d706e 1383 *
bogdanm 82:6473597d706e 1384 * Values:
bogdanm 82:6473597d706e 1385 * - 00 - UART0_RX pin
bogdanm 82:6473597d706e 1386 * - 01 - CMP0
bogdanm 82:6473597d706e 1387 * - 10 - CMP1
bogdanm 82:6473597d706e 1388 * - 11 - Reserved
bogdanm 82:6473597d706e 1389 */
bogdanm 82:6473597d706e 1390 //@{
bogdanm 82:6473597d706e 1391 #define BP_SIM_SOPT5_UART0RXSRC (2U) //!< Bit position for SIM_SOPT5_UART0RXSRC.
bogdanm 82:6473597d706e 1392 #define BM_SIM_SOPT5_UART0RXSRC (0x0000000CU) //!< Bit mask for SIM_SOPT5_UART0RXSRC.
bogdanm 82:6473597d706e 1393 #define BS_SIM_SOPT5_UART0RXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART0RXSRC.
bogdanm 82:6473597d706e 1394
bogdanm 82:6473597d706e 1395 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1396 //! @brief Read current value of the SIM_SOPT5_UART0RXSRC field.
bogdanm 82:6473597d706e 1397 #define BR_SIM_SOPT5_UART0RXSRC (HW_SIM_SOPT5.B.UART0RXSRC)
bogdanm 82:6473597d706e 1398 #endif
bogdanm 82:6473597d706e 1399
bogdanm 82:6473597d706e 1400 //! @brief Format value for bitfield SIM_SOPT5_UART0RXSRC.
bogdanm 82:6473597d706e 1401 #define BF_SIM_SOPT5_UART0RXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART0RXSRC), uint32_t) & BM_SIM_SOPT5_UART0RXSRC)
bogdanm 82:6473597d706e 1402
bogdanm 82:6473597d706e 1403 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1404 //! @brief Set the UART0RXSRC field to a new value.
bogdanm 82:6473597d706e 1405 #define BW_SIM_SOPT5_UART0RXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART0RXSRC) | BF_SIM_SOPT5_UART0RXSRC(v)))
bogdanm 82:6473597d706e 1406 #endif
bogdanm 82:6473597d706e 1407 //@}
bogdanm 82:6473597d706e 1408
bogdanm 82:6473597d706e 1409 /*!
bogdanm 82:6473597d706e 1410 * @name Register SIM_SOPT5, field UART1TXSRC[5:4] (RW)
bogdanm 82:6473597d706e 1411 *
bogdanm 82:6473597d706e 1412 * Selects the source for the UART 1 transmit data.
bogdanm 82:6473597d706e 1413 *
bogdanm 82:6473597d706e 1414 * Values:
bogdanm 82:6473597d706e 1415 * - 00 - UART1_TX pin
bogdanm 82:6473597d706e 1416 * - 01 - UART1_TX pin modulated with FTM1 channel 0 output
bogdanm 82:6473597d706e 1417 * - 10 - UART1_TX pin modulated with FTM2 channel 0 output
bogdanm 82:6473597d706e 1418 * - 11 - Reserved
bogdanm 82:6473597d706e 1419 */
bogdanm 82:6473597d706e 1420 //@{
bogdanm 82:6473597d706e 1421 #define BP_SIM_SOPT5_UART1TXSRC (4U) //!< Bit position for SIM_SOPT5_UART1TXSRC.
bogdanm 82:6473597d706e 1422 #define BM_SIM_SOPT5_UART1TXSRC (0x00000030U) //!< Bit mask for SIM_SOPT5_UART1TXSRC.
bogdanm 82:6473597d706e 1423 #define BS_SIM_SOPT5_UART1TXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART1TXSRC.
bogdanm 82:6473597d706e 1424
bogdanm 82:6473597d706e 1425 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1426 //! @brief Read current value of the SIM_SOPT5_UART1TXSRC field.
bogdanm 82:6473597d706e 1427 #define BR_SIM_SOPT5_UART1TXSRC (HW_SIM_SOPT5.B.UART1TXSRC)
bogdanm 82:6473597d706e 1428 #endif
bogdanm 82:6473597d706e 1429
bogdanm 82:6473597d706e 1430 //! @brief Format value for bitfield SIM_SOPT5_UART1TXSRC.
bogdanm 82:6473597d706e 1431 #define BF_SIM_SOPT5_UART1TXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART1TXSRC), uint32_t) & BM_SIM_SOPT5_UART1TXSRC)
bogdanm 82:6473597d706e 1432
bogdanm 82:6473597d706e 1433 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1434 //! @brief Set the UART1TXSRC field to a new value.
bogdanm 82:6473597d706e 1435 #define BW_SIM_SOPT5_UART1TXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART1TXSRC) | BF_SIM_SOPT5_UART1TXSRC(v)))
bogdanm 82:6473597d706e 1436 #endif
bogdanm 82:6473597d706e 1437 //@}
bogdanm 82:6473597d706e 1438
bogdanm 82:6473597d706e 1439 /*!
bogdanm 82:6473597d706e 1440 * @name Register SIM_SOPT5, field UART1RXSRC[7:6] (RW)
bogdanm 82:6473597d706e 1441 *
bogdanm 82:6473597d706e 1442 * Selects the source for the UART 1 receive data.
bogdanm 82:6473597d706e 1443 *
bogdanm 82:6473597d706e 1444 * Values:
bogdanm 82:6473597d706e 1445 * - 00 - UART1_RX pin
bogdanm 82:6473597d706e 1446 * - 01 - CMP0
bogdanm 82:6473597d706e 1447 * - 10 - CMP1
bogdanm 82:6473597d706e 1448 * - 11 - Reserved
bogdanm 82:6473597d706e 1449 */
bogdanm 82:6473597d706e 1450 //@{
bogdanm 82:6473597d706e 1451 #define BP_SIM_SOPT5_UART1RXSRC (6U) //!< Bit position for SIM_SOPT5_UART1RXSRC.
bogdanm 82:6473597d706e 1452 #define BM_SIM_SOPT5_UART1RXSRC (0x000000C0U) //!< Bit mask for SIM_SOPT5_UART1RXSRC.
bogdanm 82:6473597d706e 1453 #define BS_SIM_SOPT5_UART1RXSRC (2U) //!< Bit field size in bits for SIM_SOPT5_UART1RXSRC.
bogdanm 82:6473597d706e 1454
bogdanm 82:6473597d706e 1455 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1456 //! @brief Read current value of the SIM_SOPT5_UART1RXSRC field.
bogdanm 82:6473597d706e 1457 #define BR_SIM_SOPT5_UART1RXSRC (HW_SIM_SOPT5.B.UART1RXSRC)
bogdanm 82:6473597d706e 1458 #endif
bogdanm 82:6473597d706e 1459
bogdanm 82:6473597d706e 1460 //! @brief Format value for bitfield SIM_SOPT5_UART1RXSRC.
bogdanm 82:6473597d706e 1461 #define BF_SIM_SOPT5_UART1RXSRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT5_UART1RXSRC), uint32_t) & BM_SIM_SOPT5_UART1RXSRC)
bogdanm 82:6473597d706e 1462
bogdanm 82:6473597d706e 1463 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1464 //! @brief Set the UART1RXSRC field to a new value.
bogdanm 82:6473597d706e 1465 #define BW_SIM_SOPT5_UART1RXSRC(v) (HW_SIM_SOPT5_WR((HW_SIM_SOPT5_RD() & ~BM_SIM_SOPT5_UART1RXSRC) | BF_SIM_SOPT5_UART1RXSRC(v)))
bogdanm 82:6473597d706e 1466 #endif
bogdanm 82:6473597d706e 1467 //@}
bogdanm 82:6473597d706e 1468
bogdanm 82:6473597d706e 1469 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1470 // HW_SIM_SOPT7 - System Options Register 7
bogdanm 82:6473597d706e 1471 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1472
bogdanm 82:6473597d706e 1473 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1474 /*!
bogdanm 82:6473597d706e 1475 * @brief HW_SIM_SOPT7 - System Options Register 7 (RW)
bogdanm 82:6473597d706e 1476 *
bogdanm 82:6473597d706e 1477 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 1478 */
bogdanm 82:6473597d706e 1479 typedef union _hw_sim_sopt7
bogdanm 82:6473597d706e 1480 {
bogdanm 82:6473597d706e 1481 uint32_t U;
bogdanm 82:6473597d706e 1482 struct _hw_sim_sopt7_bitfields
bogdanm 82:6473597d706e 1483 {
bogdanm 82:6473597d706e 1484 uint32_t ADC0TRGSEL : 4; //!< [3:0] ADC0 trigger select
bogdanm 82:6473597d706e 1485 uint32_t ADC0PRETRGSEL : 1; //!< [4] ADC0 pretrigger select
bogdanm 82:6473597d706e 1486 uint32_t RESERVED0 : 2; //!< [6:5]
bogdanm 82:6473597d706e 1487 uint32_t ADC0ALTTRGEN : 1; //!< [7] ADC0 alternate trigger enable
bogdanm 82:6473597d706e 1488 uint32_t ADC1TRGSEL : 4; //!< [11:8] ADC1 trigger select
bogdanm 82:6473597d706e 1489 uint32_t ADC1PRETRGSEL : 1; //!< [12] ADC1 pre-trigger select
bogdanm 82:6473597d706e 1490 uint32_t RESERVED1 : 2; //!< [14:13]
bogdanm 82:6473597d706e 1491 uint32_t ADC1ALTTRGEN : 1; //!< [15] ADC1 alternate trigger enable
bogdanm 82:6473597d706e 1492 uint32_t RESERVED2 : 16; //!< [31:16]
bogdanm 82:6473597d706e 1493 } B;
bogdanm 82:6473597d706e 1494 } hw_sim_sopt7_t;
bogdanm 82:6473597d706e 1495 #endif
bogdanm 82:6473597d706e 1496
bogdanm 82:6473597d706e 1497 /*!
bogdanm 82:6473597d706e 1498 * @name Constants and macros for entire SIM_SOPT7 register
bogdanm 82:6473597d706e 1499 */
bogdanm 82:6473597d706e 1500 //@{
bogdanm 82:6473597d706e 1501 #define HW_SIM_SOPT7_ADDR (REGS_SIM_BASE + 0x1018U)
bogdanm 82:6473597d706e 1502
bogdanm 82:6473597d706e 1503 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1504 #define HW_SIM_SOPT7 (*(__IO hw_sim_sopt7_t *) HW_SIM_SOPT7_ADDR)
bogdanm 82:6473597d706e 1505 #define HW_SIM_SOPT7_RD() (HW_SIM_SOPT7.U)
bogdanm 82:6473597d706e 1506 #define HW_SIM_SOPT7_WR(v) (HW_SIM_SOPT7.U = (v))
bogdanm 82:6473597d706e 1507 #define HW_SIM_SOPT7_SET(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() | (v)))
bogdanm 82:6473597d706e 1508 #define HW_SIM_SOPT7_CLR(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() & ~(v)))
bogdanm 82:6473597d706e 1509 #define HW_SIM_SOPT7_TOG(v) (HW_SIM_SOPT7_WR(HW_SIM_SOPT7_RD() ^ (v)))
bogdanm 82:6473597d706e 1510 #endif
bogdanm 82:6473597d706e 1511 //@}
bogdanm 82:6473597d706e 1512
bogdanm 82:6473597d706e 1513 /*
bogdanm 82:6473597d706e 1514 * Constants & macros for individual SIM_SOPT7 bitfields
bogdanm 82:6473597d706e 1515 */
bogdanm 82:6473597d706e 1516
bogdanm 82:6473597d706e 1517 /*!
bogdanm 82:6473597d706e 1518 * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
bogdanm 82:6473597d706e 1519 *
bogdanm 82:6473597d706e 1520 * Selects the ADC0 trigger source when alternative triggers are functional in
bogdanm 82:6473597d706e 1521 * stop and VLPS modes. .
bogdanm 82:6473597d706e 1522 *
bogdanm 82:6473597d706e 1523 * Values:
bogdanm 82:6473597d706e 1524 * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
bogdanm 82:6473597d706e 1525 * - 0001 - High speed comparator 0 output
bogdanm 82:6473597d706e 1526 * - 0010 - High speed comparator 1 output
bogdanm 82:6473597d706e 1527 * - 0011 - High speed comparator 2 output
bogdanm 82:6473597d706e 1528 * - 0100 - PIT trigger 0
bogdanm 82:6473597d706e 1529 * - 0101 - PIT trigger 1
bogdanm 82:6473597d706e 1530 * - 0110 - PIT trigger 2
bogdanm 82:6473597d706e 1531 * - 0111 - PIT trigger 3
bogdanm 82:6473597d706e 1532 * - 1000 - FTM0 trigger
bogdanm 82:6473597d706e 1533 * - 1001 - FTM1 trigger
bogdanm 82:6473597d706e 1534 * - 1010 - FTM2 trigger
bogdanm 82:6473597d706e 1535 * - 1011 - FTM3 trigger
bogdanm 82:6473597d706e 1536 * - 1100 - RTC alarm
bogdanm 82:6473597d706e 1537 * - 1101 - RTC seconds
bogdanm 82:6473597d706e 1538 * - 1110 - Low-power timer (LPTMR) trigger
bogdanm 82:6473597d706e 1539 * - 1111 - Reserved
bogdanm 82:6473597d706e 1540 */
bogdanm 82:6473597d706e 1541 //@{
bogdanm 82:6473597d706e 1542 #define BP_SIM_SOPT7_ADC0TRGSEL (0U) //!< Bit position for SIM_SOPT7_ADC0TRGSEL.
bogdanm 82:6473597d706e 1543 #define BM_SIM_SOPT7_ADC0TRGSEL (0x0000000FU) //!< Bit mask for SIM_SOPT7_ADC0TRGSEL.
bogdanm 82:6473597d706e 1544 #define BS_SIM_SOPT7_ADC0TRGSEL (4U) //!< Bit field size in bits for SIM_SOPT7_ADC0TRGSEL.
bogdanm 82:6473597d706e 1545
bogdanm 82:6473597d706e 1546 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1547 //! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field.
bogdanm 82:6473597d706e 1548 #define BR_SIM_SOPT7_ADC0TRGSEL (HW_SIM_SOPT7.B.ADC0TRGSEL)
bogdanm 82:6473597d706e 1549 #endif
bogdanm 82:6473597d706e 1550
bogdanm 82:6473597d706e 1551 //! @brief Format value for bitfield SIM_SOPT7_ADC0TRGSEL.
bogdanm 82:6473597d706e 1552 #define BF_SIM_SOPT7_ADC0TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0TRGSEL), uint32_t) & BM_SIM_SOPT7_ADC0TRGSEL)
bogdanm 82:6473597d706e 1553
bogdanm 82:6473597d706e 1554 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1555 //! @brief Set the ADC0TRGSEL field to a new value.
bogdanm 82:6473597d706e 1556 #define BW_SIM_SOPT7_ADC0TRGSEL(v) (HW_SIM_SOPT7_WR((HW_SIM_SOPT7_RD() & ~BM_SIM_SOPT7_ADC0TRGSEL) | BF_SIM_SOPT7_ADC0TRGSEL(v)))
bogdanm 82:6473597d706e 1557 #endif
bogdanm 82:6473597d706e 1558 //@}
bogdanm 82:6473597d706e 1559
bogdanm 82:6473597d706e 1560 /*!
bogdanm 82:6473597d706e 1561 * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
bogdanm 82:6473597d706e 1562 *
bogdanm 82:6473597d706e 1563 * Selects the ADC0 pre-trigger source when alternative triggers are enabled
bogdanm 82:6473597d706e 1564 * through ADC0ALTTRGEN.
bogdanm 82:6473597d706e 1565 *
bogdanm 82:6473597d706e 1566 * Values:
bogdanm 82:6473597d706e 1567 * - 0 - Pre-trigger A
bogdanm 82:6473597d706e 1568 * - 1 - Pre-trigger B
bogdanm 82:6473597d706e 1569 */
bogdanm 82:6473597d706e 1570 //@{
bogdanm 82:6473597d706e 1571 #define BP_SIM_SOPT7_ADC0PRETRGSEL (4U) //!< Bit position for SIM_SOPT7_ADC0PRETRGSEL.
bogdanm 82:6473597d706e 1572 #define BM_SIM_SOPT7_ADC0PRETRGSEL (0x00000010U) //!< Bit mask for SIM_SOPT7_ADC0PRETRGSEL.
bogdanm 82:6473597d706e 1573 #define BS_SIM_SOPT7_ADC0PRETRGSEL (1U) //!< Bit field size in bits for SIM_SOPT7_ADC0PRETRGSEL.
bogdanm 82:6473597d706e 1574
bogdanm 82:6473597d706e 1575 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1576 //! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field.
bogdanm 82:6473597d706e 1577 #define BR_SIM_SOPT7_ADC0PRETRGSEL (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0PRETRGSEL))
bogdanm 82:6473597d706e 1578 #endif
bogdanm 82:6473597d706e 1579
bogdanm 82:6473597d706e 1580 //! @brief Format value for bitfield SIM_SOPT7_ADC0PRETRGSEL.
bogdanm 82:6473597d706e 1581 #define BF_SIM_SOPT7_ADC0PRETRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0PRETRGSEL), uint32_t) & BM_SIM_SOPT7_ADC0PRETRGSEL)
bogdanm 82:6473597d706e 1582
bogdanm 82:6473597d706e 1583 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1584 //! @brief Set the ADC0PRETRGSEL field to a new value.
bogdanm 82:6473597d706e 1585 #define BW_SIM_SOPT7_ADC0PRETRGSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0PRETRGSEL) = (v))
bogdanm 82:6473597d706e 1586 #endif
bogdanm 82:6473597d706e 1587 //@}
bogdanm 82:6473597d706e 1588
bogdanm 82:6473597d706e 1589 /*!
bogdanm 82:6473597d706e 1590 * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
bogdanm 82:6473597d706e 1591 *
bogdanm 82:6473597d706e 1592 * Enable alternative conversion triggers for ADC0.
bogdanm 82:6473597d706e 1593 *
bogdanm 82:6473597d706e 1594 * Values:
bogdanm 82:6473597d706e 1595 * - 0 - PDB trigger selected for ADC0.
bogdanm 82:6473597d706e 1596 * - 1 - Alternate trigger selected for ADC0.
bogdanm 82:6473597d706e 1597 */
bogdanm 82:6473597d706e 1598 //@{
bogdanm 82:6473597d706e 1599 #define BP_SIM_SOPT7_ADC0ALTTRGEN (7U) //!< Bit position for SIM_SOPT7_ADC0ALTTRGEN.
bogdanm 82:6473597d706e 1600 #define BM_SIM_SOPT7_ADC0ALTTRGEN (0x00000080U) //!< Bit mask for SIM_SOPT7_ADC0ALTTRGEN.
bogdanm 82:6473597d706e 1601 #define BS_SIM_SOPT7_ADC0ALTTRGEN (1U) //!< Bit field size in bits for SIM_SOPT7_ADC0ALTTRGEN.
bogdanm 82:6473597d706e 1602
bogdanm 82:6473597d706e 1603 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1604 //! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field.
bogdanm 82:6473597d706e 1605 #define BR_SIM_SOPT7_ADC0ALTTRGEN (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0ALTTRGEN))
bogdanm 82:6473597d706e 1606 #endif
bogdanm 82:6473597d706e 1607
bogdanm 82:6473597d706e 1608 //! @brief Format value for bitfield SIM_SOPT7_ADC0ALTTRGEN.
bogdanm 82:6473597d706e 1609 #define BF_SIM_SOPT7_ADC0ALTTRGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC0ALTTRGEN), uint32_t) & BM_SIM_SOPT7_ADC0ALTTRGEN)
bogdanm 82:6473597d706e 1610
bogdanm 82:6473597d706e 1611 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1612 //! @brief Set the ADC0ALTTRGEN field to a new value.
bogdanm 82:6473597d706e 1613 #define BW_SIM_SOPT7_ADC0ALTTRGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC0ALTTRGEN) = (v))
bogdanm 82:6473597d706e 1614 #endif
bogdanm 82:6473597d706e 1615 //@}
bogdanm 82:6473597d706e 1616
bogdanm 82:6473597d706e 1617 /*!
bogdanm 82:6473597d706e 1618 * @name Register SIM_SOPT7, field ADC1TRGSEL[11:8] (RW)
bogdanm 82:6473597d706e 1619 *
bogdanm 82:6473597d706e 1620 * Selects the ADC1 trigger source when alternative triggers are functional in
bogdanm 82:6473597d706e 1621 * stop and VLPS modes.
bogdanm 82:6473597d706e 1622 *
bogdanm 82:6473597d706e 1623 * Values:
bogdanm 82:6473597d706e 1624 * - 0000 - PDB external trigger pin input (PDB0_EXTRG)
bogdanm 82:6473597d706e 1625 * - 0001 - High speed comparator 0 output
bogdanm 82:6473597d706e 1626 * - 0010 - High speed comparator 1 output
bogdanm 82:6473597d706e 1627 * - 0011 - High speed comparator 2 output
bogdanm 82:6473597d706e 1628 * - 0100 - PIT trigger 0
bogdanm 82:6473597d706e 1629 * - 0101 - PIT trigger 1
bogdanm 82:6473597d706e 1630 * - 0110 - PIT trigger 2
bogdanm 82:6473597d706e 1631 * - 0111 - PIT trigger 3
bogdanm 82:6473597d706e 1632 * - 1000 - FTM0 trigger
bogdanm 82:6473597d706e 1633 * - 1001 - FTM1 trigger
bogdanm 82:6473597d706e 1634 * - 1010 - FTM2 trigger
bogdanm 82:6473597d706e 1635 * - 1011 - FTM3 trigger
bogdanm 82:6473597d706e 1636 * - 1100 - RTC alarm
bogdanm 82:6473597d706e 1637 * - 1101 - RTC seconds
bogdanm 82:6473597d706e 1638 * - 1110 - Low-power timer (LPTMR) trigger
bogdanm 82:6473597d706e 1639 * - 1111 - Reserved
bogdanm 82:6473597d706e 1640 */
bogdanm 82:6473597d706e 1641 //@{
bogdanm 82:6473597d706e 1642 #define BP_SIM_SOPT7_ADC1TRGSEL (8U) //!< Bit position for SIM_SOPT7_ADC1TRGSEL.
bogdanm 82:6473597d706e 1643 #define BM_SIM_SOPT7_ADC1TRGSEL (0x00000F00U) //!< Bit mask for SIM_SOPT7_ADC1TRGSEL.
bogdanm 82:6473597d706e 1644 #define BS_SIM_SOPT7_ADC1TRGSEL (4U) //!< Bit field size in bits for SIM_SOPT7_ADC1TRGSEL.
bogdanm 82:6473597d706e 1645
bogdanm 82:6473597d706e 1646 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1647 //! @brief Read current value of the SIM_SOPT7_ADC1TRGSEL field.
bogdanm 82:6473597d706e 1648 #define BR_SIM_SOPT7_ADC1TRGSEL (HW_SIM_SOPT7.B.ADC1TRGSEL)
bogdanm 82:6473597d706e 1649 #endif
bogdanm 82:6473597d706e 1650
bogdanm 82:6473597d706e 1651 //! @brief Format value for bitfield SIM_SOPT7_ADC1TRGSEL.
bogdanm 82:6473597d706e 1652 #define BF_SIM_SOPT7_ADC1TRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1TRGSEL), uint32_t) & BM_SIM_SOPT7_ADC1TRGSEL)
bogdanm 82:6473597d706e 1653
bogdanm 82:6473597d706e 1654 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1655 //! @brief Set the ADC1TRGSEL field to a new value.
bogdanm 82:6473597d706e 1656 #define BW_SIM_SOPT7_ADC1TRGSEL(v) (HW_SIM_SOPT7_WR((HW_SIM_SOPT7_RD() & ~BM_SIM_SOPT7_ADC1TRGSEL) | BF_SIM_SOPT7_ADC1TRGSEL(v)))
bogdanm 82:6473597d706e 1657 #endif
bogdanm 82:6473597d706e 1658 //@}
bogdanm 82:6473597d706e 1659
bogdanm 82:6473597d706e 1660 /*!
bogdanm 82:6473597d706e 1661 * @name Register SIM_SOPT7, field ADC1PRETRGSEL[12] (RW)
bogdanm 82:6473597d706e 1662 *
bogdanm 82:6473597d706e 1663 * Selects the ADC1 pre-trigger source when alternative triggers are enabled
bogdanm 82:6473597d706e 1664 * through ADC1ALTTRGEN.
bogdanm 82:6473597d706e 1665 *
bogdanm 82:6473597d706e 1666 * Values:
bogdanm 82:6473597d706e 1667 * - 0 - Pre-trigger A selected for ADC1.
bogdanm 82:6473597d706e 1668 * - 1 - Pre-trigger B selected for ADC1.
bogdanm 82:6473597d706e 1669 */
bogdanm 82:6473597d706e 1670 //@{
bogdanm 82:6473597d706e 1671 #define BP_SIM_SOPT7_ADC1PRETRGSEL (12U) //!< Bit position for SIM_SOPT7_ADC1PRETRGSEL.
bogdanm 82:6473597d706e 1672 #define BM_SIM_SOPT7_ADC1PRETRGSEL (0x00001000U) //!< Bit mask for SIM_SOPT7_ADC1PRETRGSEL.
bogdanm 82:6473597d706e 1673 #define BS_SIM_SOPT7_ADC1PRETRGSEL (1U) //!< Bit field size in bits for SIM_SOPT7_ADC1PRETRGSEL.
bogdanm 82:6473597d706e 1674
bogdanm 82:6473597d706e 1675 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1676 //! @brief Read current value of the SIM_SOPT7_ADC1PRETRGSEL field.
bogdanm 82:6473597d706e 1677 #define BR_SIM_SOPT7_ADC1PRETRGSEL (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1PRETRGSEL))
bogdanm 82:6473597d706e 1678 #endif
bogdanm 82:6473597d706e 1679
bogdanm 82:6473597d706e 1680 //! @brief Format value for bitfield SIM_SOPT7_ADC1PRETRGSEL.
bogdanm 82:6473597d706e 1681 #define BF_SIM_SOPT7_ADC1PRETRGSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1PRETRGSEL), uint32_t) & BM_SIM_SOPT7_ADC1PRETRGSEL)
bogdanm 82:6473597d706e 1682
bogdanm 82:6473597d706e 1683 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1684 //! @brief Set the ADC1PRETRGSEL field to a new value.
bogdanm 82:6473597d706e 1685 #define BW_SIM_SOPT7_ADC1PRETRGSEL(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1PRETRGSEL) = (v))
bogdanm 82:6473597d706e 1686 #endif
bogdanm 82:6473597d706e 1687 //@}
bogdanm 82:6473597d706e 1688
bogdanm 82:6473597d706e 1689 /*!
bogdanm 82:6473597d706e 1690 * @name Register SIM_SOPT7, field ADC1ALTTRGEN[15] (RW)
bogdanm 82:6473597d706e 1691 *
bogdanm 82:6473597d706e 1692 * Enable alternative conversion triggers for ADC1.
bogdanm 82:6473597d706e 1693 *
bogdanm 82:6473597d706e 1694 * Values:
bogdanm 82:6473597d706e 1695 * - 0 - PDB trigger selected for ADC1
bogdanm 82:6473597d706e 1696 * - 1 - Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
bogdanm 82:6473597d706e 1697 */
bogdanm 82:6473597d706e 1698 //@{
bogdanm 82:6473597d706e 1699 #define BP_SIM_SOPT7_ADC1ALTTRGEN (15U) //!< Bit position for SIM_SOPT7_ADC1ALTTRGEN.
bogdanm 82:6473597d706e 1700 #define BM_SIM_SOPT7_ADC1ALTTRGEN (0x00008000U) //!< Bit mask for SIM_SOPT7_ADC1ALTTRGEN.
bogdanm 82:6473597d706e 1701 #define BS_SIM_SOPT7_ADC1ALTTRGEN (1U) //!< Bit field size in bits for SIM_SOPT7_ADC1ALTTRGEN.
bogdanm 82:6473597d706e 1702
bogdanm 82:6473597d706e 1703 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1704 //! @brief Read current value of the SIM_SOPT7_ADC1ALTTRGEN field.
bogdanm 82:6473597d706e 1705 #define BR_SIM_SOPT7_ADC1ALTTRGEN (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1ALTTRGEN))
bogdanm 82:6473597d706e 1706 #endif
bogdanm 82:6473597d706e 1707
bogdanm 82:6473597d706e 1708 //! @brief Format value for bitfield SIM_SOPT7_ADC1ALTTRGEN.
bogdanm 82:6473597d706e 1709 #define BF_SIM_SOPT7_ADC1ALTTRGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SOPT7_ADC1ALTTRGEN), uint32_t) & BM_SIM_SOPT7_ADC1ALTTRGEN)
bogdanm 82:6473597d706e 1710
bogdanm 82:6473597d706e 1711 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1712 //! @brief Set the ADC1ALTTRGEN field to a new value.
bogdanm 82:6473597d706e 1713 #define BW_SIM_SOPT7_ADC1ALTTRGEN(v) (BITBAND_ACCESS32(HW_SIM_SOPT7_ADDR, BP_SIM_SOPT7_ADC1ALTTRGEN) = (v))
bogdanm 82:6473597d706e 1714 #endif
bogdanm 82:6473597d706e 1715 //@}
bogdanm 82:6473597d706e 1716
bogdanm 82:6473597d706e 1717 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1718 // HW_SIM_SDID - System Device Identification Register
bogdanm 82:6473597d706e 1719 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1720
bogdanm 82:6473597d706e 1721 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1722 /*!
bogdanm 82:6473597d706e 1723 * @brief HW_SIM_SDID - System Device Identification Register (RO)
bogdanm 82:6473597d706e 1724 *
bogdanm 82:6473597d706e 1725 * Reset value: 0x00000380U
bogdanm 82:6473597d706e 1726 */
bogdanm 82:6473597d706e 1727 typedef union _hw_sim_sdid
bogdanm 82:6473597d706e 1728 {
bogdanm 82:6473597d706e 1729 uint32_t U;
bogdanm 82:6473597d706e 1730 struct _hw_sim_sdid_bitfields
bogdanm 82:6473597d706e 1731 {
bogdanm 82:6473597d706e 1732 uint32_t PINID : 4; //!< [3:0] Pincount identification
bogdanm 82:6473597d706e 1733 uint32_t FAMID : 3; //!< [6:4] Kinetis family identification
bogdanm 82:6473597d706e 1734 uint32_t DIEID : 5; //!< [11:7] Device Die ID
bogdanm 82:6473597d706e 1735 uint32_t REVID : 4; //!< [15:12] Device revision number
bogdanm 82:6473597d706e 1736 uint32_t RESERVED0 : 4; //!< [19:16]
bogdanm 82:6473597d706e 1737 uint32_t SERIESID : 4; //!< [23:20] Kinetis Series ID
bogdanm 82:6473597d706e 1738 uint32_t SUBFAMID : 4; //!< [27:24] Kinetis Sub-Family ID
bogdanm 82:6473597d706e 1739 uint32_t FAMILYID : 4; //!< [31:28] Kinetis Family ID
bogdanm 82:6473597d706e 1740 } B;
bogdanm 82:6473597d706e 1741 } hw_sim_sdid_t;
bogdanm 82:6473597d706e 1742 #endif
bogdanm 82:6473597d706e 1743
bogdanm 82:6473597d706e 1744 /*!
bogdanm 82:6473597d706e 1745 * @name Constants and macros for entire SIM_SDID register
bogdanm 82:6473597d706e 1746 */
bogdanm 82:6473597d706e 1747 //@{
bogdanm 82:6473597d706e 1748 #define HW_SIM_SDID_ADDR (REGS_SIM_BASE + 0x1024U)
bogdanm 82:6473597d706e 1749
bogdanm 82:6473597d706e 1750 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1751 #define HW_SIM_SDID (*(__I hw_sim_sdid_t *) HW_SIM_SDID_ADDR)
bogdanm 82:6473597d706e 1752 #define HW_SIM_SDID_RD() (HW_SIM_SDID.U)
bogdanm 82:6473597d706e 1753 #endif
bogdanm 82:6473597d706e 1754 //@}
bogdanm 82:6473597d706e 1755
bogdanm 82:6473597d706e 1756 /*
bogdanm 82:6473597d706e 1757 * Constants & macros for individual SIM_SDID bitfields
bogdanm 82:6473597d706e 1758 */
bogdanm 82:6473597d706e 1759
bogdanm 82:6473597d706e 1760 /*!
bogdanm 82:6473597d706e 1761 * @name Register SIM_SDID, field PINID[3:0] (RO)
bogdanm 82:6473597d706e 1762 *
bogdanm 82:6473597d706e 1763 * Specifies the pincount of the device.
bogdanm 82:6473597d706e 1764 *
bogdanm 82:6473597d706e 1765 * Values:
bogdanm 82:6473597d706e 1766 * - 0000 - Reserved
bogdanm 82:6473597d706e 1767 * - 0001 - Reserved
bogdanm 82:6473597d706e 1768 * - 0010 - 32-pin
bogdanm 82:6473597d706e 1769 * - 0011 - Reserved
bogdanm 82:6473597d706e 1770 * - 0100 - 48-pin
bogdanm 82:6473597d706e 1771 * - 0101 - 64-pin
bogdanm 82:6473597d706e 1772 * - 0110 - 80-pin
bogdanm 82:6473597d706e 1773 * - 0111 - 81-pin or 121-pin
bogdanm 82:6473597d706e 1774 * - 1000 - 100-pin
bogdanm 82:6473597d706e 1775 * - 1001 - 121-pin
bogdanm 82:6473597d706e 1776 * - 1010 - 144-pin
bogdanm 82:6473597d706e 1777 * - 1011 - Custom pinout (WLCSP)
bogdanm 82:6473597d706e 1778 * - 1100 - 169-pin
bogdanm 82:6473597d706e 1779 * - 1101 - Reserved
bogdanm 82:6473597d706e 1780 * - 1110 - 256-pin
bogdanm 82:6473597d706e 1781 * - 1111 - Reserved
bogdanm 82:6473597d706e 1782 */
bogdanm 82:6473597d706e 1783 //@{
bogdanm 82:6473597d706e 1784 #define BP_SIM_SDID_PINID (0U) //!< Bit position for SIM_SDID_PINID.
bogdanm 82:6473597d706e 1785 #define BM_SIM_SDID_PINID (0x0000000FU) //!< Bit mask for SIM_SDID_PINID.
bogdanm 82:6473597d706e 1786 #define BS_SIM_SDID_PINID (4U) //!< Bit field size in bits for SIM_SDID_PINID.
bogdanm 82:6473597d706e 1787
bogdanm 82:6473597d706e 1788 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1789 //! @brief Read current value of the SIM_SDID_PINID field.
bogdanm 82:6473597d706e 1790 #define BR_SIM_SDID_PINID (HW_SIM_SDID.B.PINID)
bogdanm 82:6473597d706e 1791 #endif
bogdanm 82:6473597d706e 1792 //@}
bogdanm 82:6473597d706e 1793
bogdanm 82:6473597d706e 1794 /*!
bogdanm 82:6473597d706e 1795 * @name Register SIM_SDID, field FAMID[6:4] (RO)
bogdanm 82:6473597d706e 1796 *
bogdanm 82:6473597d706e 1797 * This field is maintained for compatibility only, but has been superceded by
bogdanm 82:6473597d706e 1798 * the SERIESID, FAMILYID and SUBFAMID fields in this register.
bogdanm 82:6473597d706e 1799 *
bogdanm 82:6473597d706e 1800 * Values:
bogdanm 82:6473597d706e 1801 * - 000 - K1x Family (without tamper)
bogdanm 82:6473597d706e 1802 * - 001 - K2x Family (without tamper)
bogdanm 82:6473597d706e 1803 * - 010 - K3x Family or K1x/K6x Family (with tamper)
bogdanm 82:6473597d706e 1804 * - 011 - K4x Family or K2x Family (with tamper)
bogdanm 82:6473597d706e 1805 * - 100 - K6x Family (without tamper)
bogdanm 82:6473597d706e 1806 * - 101 - K7x Family
bogdanm 82:6473597d706e 1807 * - 110 - Reserved
bogdanm 82:6473597d706e 1808 * - 111 - Reserved
bogdanm 82:6473597d706e 1809 */
bogdanm 82:6473597d706e 1810 //@{
bogdanm 82:6473597d706e 1811 #define BP_SIM_SDID_FAMID (4U) //!< Bit position for SIM_SDID_FAMID.
bogdanm 82:6473597d706e 1812 #define BM_SIM_SDID_FAMID (0x00000070U) //!< Bit mask for SIM_SDID_FAMID.
bogdanm 82:6473597d706e 1813 #define BS_SIM_SDID_FAMID (3U) //!< Bit field size in bits for SIM_SDID_FAMID.
bogdanm 82:6473597d706e 1814
bogdanm 82:6473597d706e 1815 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1816 //! @brief Read current value of the SIM_SDID_FAMID field.
bogdanm 82:6473597d706e 1817 #define BR_SIM_SDID_FAMID (HW_SIM_SDID.B.FAMID)
bogdanm 82:6473597d706e 1818 #endif
bogdanm 82:6473597d706e 1819 //@}
bogdanm 82:6473597d706e 1820
bogdanm 82:6473597d706e 1821 /*!
bogdanm 82:6473597d706e 1822 * @name Register SIM_SDID, field DIEID[11:7] (RO)
bogdanm 82:6473597d706e 1823 *
bogdanm 82:6473597d706e 1824 * Specifies the silicon feature set identication number for the device.
bogdanm 82:6473597d706e 1825 */
bogdanm 82:6473597d706e 1826 //@{
bogdanm 82:6473597d706e 1827 #define BP_SIM_SDID_DIEID (7U) //!< Bit position for SIM_SDID_DIEID.
bogdanm 82:6473597d706e 1828 #define BM_SIM_SDID_DIEID (0x00000F80U) //!< Bit mask for SIM_SDID_DIEID.
bogdanm 82:6473597d706e 1829 #define BS_SIM_SDID_DIEID (5U) //!< Bit field size in bits for SIM_SDID_DIEID.
bogdanm 82:6473597d706e 1830
bogdanm 82:6473597d706e 1831 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1832 //! @brief Read current value of the SIM_SDID_DIEID field.
bogdanm 82:6473597d706e 1833 #define BR_SIM_SDID_DIEID (HW_SIM_SDID.B.DIEID)
bogdanm 82:6473597d706e 1834 #endif
bogdanm 82:6473597d706e 1835 //@}
bogdanm 82:6473597d706e 1836
bogdanm 82:6473597d706e 1837 /*!
bogdanm 82:6473597d706e 1838 * @name Register SIM_SDID, field REVID[15:12] (RO)
bogdanm 82:6473597d706e 1839 *
bogdanm 82:6473597d706e 1840 * Specifies the silicon implementation number for the device.
bogdanm 82:6473597d706e 1841 */
bogdanm 82:6473597d706e 1842 //@{
bogdanm 82:6473597d706e 1843 #define BP_SIM_SDID_REVID (12U) //!< Bit position for SIM_SDID_REVID.
bogdanm 82:6473597d706e 1844 #define BM_SIM_SDID_REVID (0x0000F000U) //!< Bit mask for SIM_SDID_REVID.
bogdanm 82:6473597d706e 1845 #define BS_SIM_SDID_REVID (4U) //!< Bit field size in bits for SIM_SDID_REVID.
bogdanm 82:6473597d706e 1846
bogdanm 82:6473597d706e 1847 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1848 //! @brief Read current value of the SIM_SDID_REVID field.
bogdanm 82:6473597d706e 1849 #define BR_SIM_SDID_REVID (HW_SIM_SDID.B.REVID)
bogdanm 82:6473597d706e 1850 #endif
bogdanm 82:6473597d706e 1851 //@}
bogdanm 82:6473597d706e 1852
bogdanm 82:6473597d706e 1853 /*!
bogdanm 82:6473597d706e 1854 * @name Register SIM_SDID, field SERIESID[23:20] (RO)
bogdanm 82:6473597d706e 1855 *
bogdanm 82:6473597d706e 1856 * Specifies the Kinetis series of the device.
bogdanm 82:6473597d706e 1857 *
bogdanm 82:6473597d706e 1858 * Values:
bogdanm 82:6473597d706e 1859 * - 0000 - Kinetis K series
bogdanm 82:6473597d706e 1860 * - 0001 - Kinetis L series
bogdanm 82:6473597d706e 1861 * - 0101 - Kinetis W series
bogdanm 82:6473597d706e 1862 * - 0110 - Kinetis V series
bogdanm 82:6473597d706e 1863 */
bogdanm 82:6473597d706e 1864 //@{
bogdanm 82:6473597d706e 1865 #define BP_SIM_SDID_SERIESID (20U) //!< Bit position for SIM_SDID_SERIESID.
bogdanm 82:6473597d706e 1866 #define BM_SIM_SDID_SERIESID (0x00F00000U) //!< Bit mask for SIM_SDID_SERIESID.
bogdanm 82:6473597d706e 1867 #define BS_SIM_SDID_SERIESID (4U) //!< Bit field size in bits for SIM_SDID_SERIESID.
bogdanm 82:6473597d706e 1868
bogdanm 82:6473597d706e 1869 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1870 //! @brief Read current value of the SIM_SDID_SERIESID field.
bogdanm 82:6473597d706e 1871 #define BR_SIM_SDID_SERIESID (HW_SIM_SDID.B.SERIESID)
bogdanm 82:6473597d706e 1872 #endif
bogdanm 82:6473597d706e 1873 //@}
bogdanm 82:6473597d706e 1874
bogdanm 82:6473597d706e 1875 /*!
bogdanm 82:6473597d706e 1876 * @name Register SIM_SDID, field SUBFAMID[27:24] (RO)
bogdanm 82:6473597d706e 1877 *
bogdanm 82:6473597d706e 1878 * Specifies the Kinetis sub-family of the device.
bogdanm 82:6473597d706e 1879 *
bogdanm 82:6473597d706e 1880 * Values:
bogdanm 82:6473597d706e 1881 * - 0000 - Kx0 Subfamily
bogdanm 82:6473597d706e 1882 * - 0001 - Kx1 Subfamily (tamper detect)
bogdanm 82:6473597d706e 1883 * - 0010 - Kx2 Subfamily
bogdanm 82:6473597d706e 1884 * - 0011 - Kx3 Subfamily (tamper detect)
bogdanm 82:6473597d706e 1885 * - 0100 - Kx4 Subfamily
bogdanm 82:6473597d706e 1886 * - 0101 - Kx5 Subfamily (tamper detect)
bogdanm 82:6473597d706e 1887 * - 0110 - Kx6 Subfamily
bogdanm 82:6473597d706e 1888 */
bogdanm 82:6473597d706e 1889 //@{
bogdanm 82:6473597d706e 1890 #define BP_SIM_SDID_SUBFAMID (24U) //!< Bit position for SIM_SDID_SUBFAMID.
bogdanm 82:6473597d706e 1891 #define BM_SIM_SDID_SUBFAMID (0x0F000000U) //!< Bit mask for SIM_SDID_SUBFAMID.
bogdanm 82:6473597d706e 1892 #define BS_SIM_SDID_SUBFAMID (4U) //!< Bit field size in bits for SIM_SDID_SUBFAMID.
bogdanm 82:6473597d706e 1893
bogdanm 82:6473597d706e 1894 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1895 //! @brief Read current value of the SIM_SDID_SUBFAMID field.
bogdanm 82:6473597d706e 1896 #define BR_SIM_SDID_SUBFAMID (HW_SIM_SDID.B.SUBFAMID)
bogdanm 82:6473597d706e 1897 #endif
bogdanm 82:6473597d706e 1898 //@}
bogdanm 82:6473597d706e 1899
bogdanm 82:6473597d706e 1900 /*!
bogdanm 82:6473597d706e 1901 * @name Register SIM_SDID, field FAMILYID[31:28] (RO)
bogdanm 82:6473597d706e 1902 *
bogdanm 82:6473597d706e 1903 * Specifies the Kinetis family of the device.
bogdanm 82:6473597d706e 1904 *
bogdanm 82:6473597d706e 1905 * Values:
bogdanm 82:6473597d706e 1906 * - 0001 - K1x Family
bogdanm 82:6473597d706e 1907 * - 0010 - K2x Family
bogdanm 82:6473597d706e 1908 * - 0011 - K3x Family
bogdanm 82:6473597d706e 1909 * - 0100 - K4x Family
bogdanm 82:6473597d706e 1910 * - 0110 - K6x Family
bogdanm 82:6473597d706e 1911 * - 0111 - K7x Family
bogdanm 82:6473597d706e 1912 */
bogdanm 82:6473597d706e 1913 //@{
bogdanm 82:6473597d706e 1914 #define BP_SIM_SDID_FAMILYID (28U) //!< Bit position for SIM_SDID_FAMILYID.
bogdanm 82:6473597d706e 1915 #define BM_SIM_SDID_FAMILYID (0xF0000000U) //!< Bit mask for SIM_SDID_FAMILYID.
bogdanm 82:6473597d706e 1916 #define BS_SIM_SDID_FAMILYID (4U) //!< Bit field size in bits for SIM_SDID_FAMILYID.
bogdanm 82:6473597d706e 1917
bogdanm 82:6473597d706e 1918 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1919 //! @brief Read current value of the SIM_SDID_FAMILYID field.
bogdanm 82:6473597d706e 1920 #define BR_SIM_SDID_FAMILYID (HW_SIM_SDID.B.FAMILYID)
bogdanm 82:6473597d706e 1921 #endif
bogdanm 82:6473597d706e 1922 //@}
bogdanm 82:6473597d706e 1923
bogdanm 82:6473597d706e 1924 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1925 // HW_SIM_SCGC1 - System Clock Gating Control Register 1
bogdanm 82:6473597d706e 1926 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1927
bogdanm 82:6473597d706e 1928 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1929 /*!
bogdanm 82:6473597d706e 1930 * @brief HW_SIM_SCGC1 - System Clock Gating Control Register 1 (RW)
bogdanm 82:6473597d706e 1931 *
bogdanm 82:6473597d706e 1932 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 1933 */
bogdanm 82:6473597d706e 1934 typedef union _hw_sim_scgc1
bogdanm 82:6473597d706e 1935 {
bogdanm 82:6473597d706e 1936 uint32_t U;
bogdanm 82:6473597d706e 1937 struct _hw_sim_scgc1_bitfields
bogdanm 82:6473597d706e 1938 {
bogdanm 82:6473597d706e 1939 uint32_t RESERVED0 : 6; //!< [5:0]
bogdanm 82:6473597d706e 1940 uint32_t I2C2b : 1; //!< [6] I2C2 Clock Gate Control
bogdanm 82:6473597d706e 1941 uint32_t RESERVED1 : 3; //!< [9:7]
bogdanm 82:6473597d706e 1942 uint32_t UART4b : 1; //!< [10] UART4 Clock Gate Control
bogdanm 82:6473597d706e 1943 uint32_t UART5b : 1; //!< [11] UART5 Clock Gate Control
bogdanm 82:6473597d706e 1944 uint32_t RESERVED2 : 20; //!< [31:12]
bogdanm 82:6473597d706e 1945 } B;
bogdanm 82:6473597d706e 1946 } hw_sim_scgc1_t;
bogdanm 82:6473597d706e 1947 #endif
bogdanm 82:6473597d706e 1948
bogdanm 82:6473597d706e 1949 /*!
bogdanm 82:6473597d706e 1950 * @name Constants and macros for entire SIM_SCGC1 register
bogdanm 82:6473597d706e 1951 */
bogdanm 82:6473597d706e 1952 //@{
bogdanm 82:6473597d706e 1953 #define HW_SIM_SCGC1_ADDR (REGS_SIM_BASE + 0x1028U)
bogdanm 82:6473597d706e 1954
bogdanm 82:6473597d706e 1955 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1956 #define HW_SIM_SCGC1 (*(__IO hw_sim_scgc1_t *) HW_SIM_SCGC1_ADDR)
bogdanm 82:6473597d706e 1957 #define HW_SIM_SCGC1_RD() (HW_SIM_SCGC1.U)
bogdanm 82:6473597d706e 1958 #define HW_SIM_SCGC1_WR(v) (HW_SIM_SCGC1.U = (v))
bogdanm 82:6473597d706e 1959 #define HW_SIM_SCGC1_SET(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() | (v)))
bogdanm 82:6473597d706e 1960 #define HW_SIM_SCGC1_CLR(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() & ~(v)))
bogdanm 82:6473597d706e 1961 #define HW_SIM_SCGC1_TOG(v) (HW_SIM_SCGC1_WR(HW_SIM_SCGC1_RD() ^ (v)))
bogdanm 82:6473597d706e 1962 #endif
bogdanm 82:6473597d706e 1963 //@}
bogdanm 82:6473597d706e 1964
bogdanm 82:6473597d706e 1965 /*
bogdanm 82:6473597d706e 1966 * Constants & macros for individual SIM_SCGC1 bitfields
bogdanm 82:6473597d706e 1967 */
bogdanm 82:6473597d706e 1968
bogdanm 82:6473597d706e 1969 /*!
bogdanm 82:6473597d706e 1970 * @name Register SIM_SCGC1, field I2C2[6] (RW)
bogdanm 82:6473597d706e 1971 *
bogdanm 82:6473597d706e 1972 * This bit controls the clock gate to the I2C2 module.
bogdanm 82:6473597d706e 1973 *
bogdanm 82:6473597d706e 1974 * Values:
bogdanm 82:6473597d706e 1975 * - 0 - Clock disabled
bogdanm 82:6473597d706e 1976 * - 1 - Clock enabled
bogdanm 82:6473597d706e 1977 */
bogdanm 82:6473597d706e 1978 //@{
bogdanm 82:6473597d706e 1979 #define BP_SIM_SCGC1_I2C2 (6U) //!< Bit position for SIM_SCGC1_I2C2.
bogdanm 82:6473597d706e 1980 #define BM_SIM_SCGC1_I2C2 (0x00000040U) //!< Bit mask for SIM_SCGC1_I2C2.
bogdanm 82:6473597d706e 1981 #define BS_SIM_SCGC1_I2C2 (1U) //!< Bit field size in bits for SIM_SCGC1_I2C2.
bogdanm 82:6473597d706e 1982
bogdanm 82:6473597d706e 1983 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1984 //! @brief Read current value of the SIM_SCGC1_I2C2 field.
bogdanm 82:6473597d706e 1985 #define BR_SIM_SCGC1_I2C2 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_I2C2))
bogdanm 82:6473597d706e 1986 #endif
bogdanm 82:6473597d706e 1987
bogdanm 82:6473597d706e 1988 //! @brief Format value for bitfield SIM_SCGC1_I2C2.
bogdanm 82:6473597d706e 1989 #define BF_SIM_SCGC1_I2C2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_I2C2), uint32_t) & BM_SIM_SCGC1_I2C2)
bogdanm 82:6473597d706e 1990
bogdanm 82:6473597d706e 1991 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1992 //! @brief Set the I2C2 field to a new value.
bogdanm 82:6473597d706e 1993 #define BW_SIM_SCGC1_I2C2(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_I2C2) = (v))
bogdanm 82:6473597d706e 1994 #endif
bogdanm 82:6473597d706e 1995 //@}
bogdanm 82:6473597d706e 1996
bogdanm 82:6473597d706e 1997 /*!
bogdanm 82:6473597d706e 1998 * @name Register SIM_SCGC1, field UART4[10] (RW)
bogdanm 82:6473597d706e 1999 *
bogdanm 82:6473597d706e 2000 * This bit controls the clock gate to the UART4 module.
bogdanm 82:6473597d706e 2001 *
bogdanm 82:6473597d706e 2002 * Values:
bogdanm 82:6473597d706e 2003 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2004 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2005 */
bogdanm 82:6473597d706e 2006 //@{
bogdanm 82:6473597d706e 2007 #define BP_SIM_SCGC1_UART4 (10U) //!< Bit position for SIM_SCGC1_UART4.
bogdanm 82:6473597d706e 2008 #define BM_SIM_SCGC1_UART4 (0x00000400U) //!< Bit mask for SIM_SCGC1_UART4.
bogdanm 82:6473597d706e 2009 #define BS_SIM_SCGC1_UART4 (1U) //!< Bit field size in bits for SIM_SCGC1_UART4.
bogdanm 82:6473597d706e 2010
bogdanm 82:6473597d706e 2011 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2012 //! @brief Read current value of the SIM_SCGC1_UART4 field.
bogdanm 82:6473597d706e 2013 #define BR_SIM_SCGC1_UART4 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART4))
bogdanm 82:6473597d706e 2014 #endif
bogdanm 82:6473597d706e 2015
bogdanm 82:6473597d706e 2016 //! @brief Format value for bitfield SIM_SCGC1_UART4.
bogdanm 82:6473597d706e 2017 #define BF_SIM_SCGC1_UART4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_UART4), uint32_t) & BM_SIM_SCGC1_UART4)
bogdanm 82:6473597d706e 2018
bogdanm 82:6473597d706e 2019 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2020 //! @brief Set the UART4 field to a new value.
bogdanm 82:6473597d706e 2021 #define BW_SIM_SCGC1_UART4(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART4) = (v))
bogdanm 82:6473597d706e 2022 #endif
bogdanm 82:6473597d706e 2023 //@}
bogdanm 82:6473597d706e 2024
bogdanm 82:6473597d706e 2025 /*!
bogdanm 82:6473597d706e 2026 * @name Register SIM_SCGC1, field UART5[11] (RW)
bogdanm 82:6473597d706e 2027 *
bogdanm 82:6473597d706e 2028 * This bit controls the clock gate to the UART5 module.
bogdanm 82:6473597d706e 2029 *
bogdanm 82:6473597d706e 2030 * Values:
bogdanm 82:6473597d706e 2031 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2032 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2033 */
bogdanm 82:6473597d706e 2034 //@{
bogdanm 82:6473597d706e 2035 #define BP_SIM_SCGC1_UART5 (11U) //!< Bit position for SIM_SCGC1_UART5.
bogdanm 82:6473597d706e 2036 #define BM_SIM_SCGC1_UART5 (0x00000800U) //!< Bit mask for SIM_SCGC1_UART5.
bogdanm 82:6473597d706e 2037 #define BS_SIM_SCGC1_UART5 (1U) //!< Bit field size in bits for SIM_SCGC1_UART5.
bogdanm 82:6473597d706e 2038
bogdanm 82:6473597d706e 2039 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2040 //! @brief Read current value of the SIM_SCGC1_UART5 field.
bogdanm 82:6473597d706e 2041 #define BR_SIM_SCGC1_UART5 (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART5))
bogdanm 82:6473597d706e 2042 #endif
bogdanm 82:6473597d706e 2043
bogdanm 82:6473597d706e 2044 //! @brief Format value for bitfield SIM_SCGC1_UART5.
bogdanm 82:6473597d706e 2045 #define BF_SIM_SCGC1_UART5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC1_UART5), uint32_t) & BM_SIM_SCGC1_UART5)
bogdanm 82:6473597d706e 2046
bogdanm 82:6473597d706e 2047 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2048 //! @brief Set the UART5 field to a new value.
bogdanm 82:6473597d706e 2049 #define BW_SIM_SCGC1_UART5(v) (BITBAND_ACCESS32(HW_SIM_SCGC1_ADDR, BP_SIM_SCGC1_UART5) = (v))
bogdanm 82:6473597d706e 2050 #endif
bogdanm 82:6473597d706e 2051 //@}
bogdanm 82:6473597d706e 2052
bogdanm 82:6473597d706e 2053 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2054 // HW_SIM_SCGC2 - System Clock Gating Control Register 2
bogdanm 82:6473597d706e 2055 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2056
bogdanm 82:6473597d706e 2057 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2058 /*!
bogdanm 82:6473597d706e 2059 * @brief HW_SIM_SCGC2 - System Clock Gating Control Register 2 (RW)
bogdanm 82:6473597d706e 2060 *
bogdanm 82:6473597d706e 2061 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 2062 *
bogdanm 82:6473597d706e 2063 * DAC0 can be accessed through both AIPS0 and AIPS1. When accessing through
bogdanm 82:6473597d706e 2064 * AIPS1, define the clock gate control bits in the SCGC2. When accessing through
bogdanm 82:6473597d706e 2065 * AIPS0, define the clock gate control bits in SCGC6.
bogdanm 82:6473597d706e 2066 */
bogdanm 82:6473597d706e 2067 typedef union _hw_sim_scgc2
bogdanm 82:6473597d706e 2068 {
bogdanm 82:6473597d706e 2069 uint32_t U;
bogdanm 82:6473597d706e 2070 struct _hw_sim_scgc2_bitfields
bogdanm 82:6473597d706e 2071 {
bogdanm 82:6473597d706e 2072 uint32_t ENETb : 1; //!< [0] ENET Clock Gate Control
bogdanm 82:6473597d706e 2073 uint32_t RESERVED0 : 11; //!< [11:1]
bogdanm 82:6473597d706e 2074 uint32_t DAC0b : 1; //!< [12] DAC0 Clock Gate Control
bogdanm 82:6473597d706e 2075 uint32_t DAC1b : 1; //!< [13] DAC1 Clock Gate Control
bogdanm 82:6473597d706e 2076 uint32_t RESERVED1 : 18; //!< [31:14]
bogdanm 82:6473597d706e 2077 } B;
bogdanm 82:6473597d706e 2078 } hw_sim_scgc2_t;
bogdanm 82:6473597d706e 2079 #endif
bogdanm 82:6473597d706e 2080
bogdanm 82:6473597d706e 2081 /*!
bogdanm 82:6473597d706e 2082 * @name Constants and macros for entire SIM_SCGC2 register
bogdanm 82:6473597d706e 2083 */
bogdanm 82:6473597d706e 2084 //@{
bogdanm 82:6473597d706e 2085 #define HW_SIM_SCGC2_ADDR (REGS_SIM_BASE + 0x102CU)
bogdanm 82:6473597d706e 2086
bogdanm 82:6473597d706e 2087 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2088 #define HW_SIM_SCGC2 (*(__IO hw_sim_scgc2_t *) HW_SIM_SCGC2_ADDR)
bogdanm 82:6473597d706e 2089 #define HW_SIM_SCGC2_RD() (HW_SIM_SCGC2.U)
bogdanm 82:6473597d706e 2090 #define HW_SIM_SCGC2_WR(v) (HW_SIM_SCGC2.U = (v))
bogdanm 82:6473597d706e 2091 #define HW_SIM_SCGC2_SET(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() | (v)))
bogdanm 82:6473597d706e 2092 #define HW_SIM_SCGC2_CLR(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() & ~(v)))
bogdanm 82:6473597d706e 2093 #define HW_SIM_SCGC2_TOG(v) (HW_SIM_SCGC2_WR(HW_SIM_SCGC2_RD() ^ (v)))
bogdanm 82:6473597d706e 2094 #endif
bogdanm 82:6473597d706e 2095 //@}
bogdanm 82:6473597d706e 2096
bogdanm 82:6473597d706e 2097 /*
bogdanm 82:6473597d706e 2098 * Constants & macros for individual SIM_SCGC2 bitfields
bogdanm 82:6473597d706e 2099 */
bogdanm 82:6473597d706e 2100
bogdanm 82:6473597d706e 2101 /*!
bogdanm 82:6473597d706e 2102 * @name Register SIM_SCGC2, field ENET[0] (RW)
bogdanm 82:6473597d706e 2103 *
bogdanm 82:6473597d706e 2104 * This bit controls the clock gate to the ENET module.
bogdanm 82:6473597d706e 2105 *
bogdanm 82:6473597d706e 2106 * Values:
bogdanm 82:6473597d706e 2107 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2108 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2109 */
bogdanm 82:6473597d706e 2110 //@{
bogdanm 82:6473597d706e 2111 #define BP_SIM_SCGC2_ENET (0U) //!< Bit position for SIM_SCGC2_ENET.
bogdanm 82:6473597d706e 2112 #define BM_SIM_SCGC2_ENET (0x00000001U) //!< Bit mask for SIM_SCGC2_ENET.
bogdanm 82:6473597d706e 2113 #define BS_SIM_SCGC2_ENET (1U) //!< Bit field size in bits for SIM_SCGC2_ENET.
bogdanm 82:6473597d706e 2114
bogdanm 82:6473597d706e 2115 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2116 //! @brief Read current value of the SIM_SCGC2_ENET field.
bogdanm 82:6473597d706e 2117 #define BR_SIM_SCGC2_ENET (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_ENET))
bogdanm 82:6473597d706e 2118 #endif
bogdanm 82:6473597d706e 2119
bogdanm 82:6473597d706e 2120 //! @brief Format value for bitfield SIM_SCGC2_ENET.
bogdanm 82:6473597d706e 2121 #define BF_SIM_SCGC2_ENET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_ENET), uint32_t) & BM_SIM_SCGC2_ENET)
bogdanm 82:6473597d706e 2122
bogdanm 82:6473597d706e 2123 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2124 //! @brief Set the ENET field to a new value.
bogdanm 82:6473597d706e 2125 #define BW_SIM_SCGC2_ENET(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_ENET) = (v))
bogdanm 82:6473597d706e 2126 #endif
bogdanm 82:6473597d706e 2127 //@}
bogdanm 82:6473597d706e 2128
bogdanm 82:6473597d706e 2129 /*!
bogdanm 82:6473597d706e 2130 * @name Register SIM_SCGC2, field DAC0[12] (RW)
bogdanm 82:6473597d706e 2131 *
bogdanm 82:6473597d706e 2132 * This bit controls the clock gate to the DAC0 module.
bogdanm 82:6473597d706e 2133 *
bogdanm 82:6473597d706e 2134 * Values:
bogdanm 82:6473597d706e 2135 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2136 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2137 */
bogdanm 82:6473597d706e 2138 //@{
bogdanm 82:6473597d706e 2139 #define BP_SIM_SCGC2_DAC0 (12U) //!< Bit position for SIM_SCGC2_DAC0.
bogdanm 82:6473597d706e 2140 #define BM_SIM_SCGC2_DAC0 (0x00001000U) //!< Bit mask for SIM_SCGC2_DAC0.
bogdanm 82:6473597d706e 2141 #define BS_SIM_SCGC2_DAC0 (1U) //!< Bit field size in bits for SIM_SCGC2_DAC0.
bogdanm 82:6473597d706e 2142
bogdanm 82:6473597d706e 2143 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2144 //! @brief Read current value of the SIM_SCGC2_DAC0 field.
bogdanm 82:6473597d706e 2145 #define BR_SIM_SCGC2_DAC0 (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC0))
bogdanm 82:6473597d706e 2146 #endif
bogdanm 82:6473597d706e 2147
bogdanm 82:6473597d706e 2148 //! @brief Format value for bitfield SIM_SCGC2_DAC0.
bogdanm 82:6473597d706e 2149 #define BF_SIM_SCGC2_DAC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_DAC0), uint32_t) & BM_SIM_SCGC2_DAC0)
bogdanm 82:6473597d706e 2150
bogdanm 82:6473597d706e 2151 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2152 //! @brief Set the DAC0 field to a new value.
bogdanm 82:6473597d706e 2153 #define BW_SIM_SCGC2_DAC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC0) = (v))
bogdanm 82:6473597d706e 2154 #endif
bogdanm 82:6473597d706e 2155 //@}
bogdanm 82:6473597d706e 2156
bogdanm 82:6473597d706e 2157 /*!
bogdanm 82:6473597d706e 2158 * @name Register SIM_SCGC2, field DAC1[13] (RW)
bogdanm 82:6473597d706e 2159 *
bogdanm 82:6473597d706e 2160 * This bit controls the clock gate to the DAC1 module.
bogdanm 82:6473597d706e 2161 *
bogdanm 82:6473597d706e 2162 * Values:
bogdanm 82:6473597d706e 2163 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2164 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2165 */
bogdanm 82:6473597d706e 2166 //@{
bogdanm 82:6473597d706e 2167 #define BP_SIM_SCGC2_DAC1 (13U) //!< Bit position for SIM_SCGC2_DAC1.
bogdanm 82:6473597d706e 2168 #define BM_SIM_SCGC2_DAC1 (0x00002000U) //!< Bit mask for SIM_SCGC2_DAC1.
bogdanm 82:6473597d706e 2169 #define BS_SIM_SCGC2_DAC1 (1U) //!< Bit field size in bits for SIM_SCGC2_DAC1.
bogdanm 82:6473597d706e 2170
bogdanm 82:6473597d706e 2171 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2172 //! @brief Read current value of the SIM_SCGC2_DAC1 field.
bogdanm 82:6473597d706e 2173 #define BR_SIM_SCGC2_DAC1 (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC1))
bogdanm 82:6473597d706e 2174 #endif
bogdanm 82:6473597d706e 2175
bogdanm 82:6473597d706e 2176 //! @brief Format value for bitfield SIM_SCGC2_DAC1.
bogdanm 82:6473597d706e 2177 #define BF_SIM_SCGC2_DAC1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC2_DAC1), uint32_t) & BM_SIM_SCGC2_DAC1)
bogdanm 82:6473597d706e 2178
bogdanm 82:6473597d706e 2179 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2180 //! @brief Set the DAC1 field to a new value.
bogdanm 82:6473597d706e 2181 #define BW_SIM_SCGC2_DAC1(v) (BITBAND_ACCESS32(HW_SIM_SCGC2_ADDR, BP_SIM_SCGC2_DAC1) = (v))
bogdanm 82:6473597d706e 2182 #endif
bogdanm 82:6473597d706e 2183 //@}
bogdanm 82:6473597d706e 2184
bogdanm 82:6473597d706e 2185 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2186 // HW_SIM_SCGC3 - System Clock Gating Control Register 3
bogdanm 82:6473597d706e 2187 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2188
bogdanm 82:6473597d706e 2189 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2190 /*!
bogdanm 82:6473597d706e 2191 * @brief HW_SIM_SCGC3 - System Clock Gating Control Register 3 (RW)
bogdanm 82:6473597d706e 2192 *
bogdanm 82:6473597d706e 2193 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 2194 *
bogdanm 82:6473597d706e 2195 * FTM2 and RNGA can be accessed through both AIPS0 and AIPS1. When accessing
bogdanm 82:6473597d706e 2196 * through AIPS1, define the clock gate control bits in the SCGC3. When accessing
bogdanm 82:6473597d706e 2197 * through AIPS0, define the clock gate control bits in SCGC6.
bogdanm 82:6473597d706e 2198 */
bogdanm 82:6473597d706e 2199 typedef union _hw_sim_scgc3
bogdanm 82:6473597d706e 2200 {
bogdanm 82:6473597d706e 2201 uint32_t U;
bogdanm 82:6473597d706e 2202 struct _hw_sim_scgc3_bitfields
bogdanm 82:6473597d706e 2203 {
bogdanm 82:6473597d706e 2204 uint32_t RNGA : 1; //!< [0] RNGA Clock Gate Control
bogdanm 82:6473597d706e 2205 uint32_t RESERVED0 : 11; //!< [11:1]
bogdanm 82:6473597d706e 2206 uint32_t SPI2b : 1; //!< [12] SPI2 Clock Gate Control
bogdanm 82:6473597d706e 2207 uint32_t RESERVED1 : 4; //!< [16:13]
bogdanm 82:6473597d706e 2208 uint32_t SDHCb : 1; //!< [17] SDHC Clock Gate Control
bogdanm 82:6473597d706e 2209 uint32_t RESERVED2 : 6; //!< [23:18]
bogdanm 82:6473597d706e 2210 uint32_t FTM2b : 1; //!< [24] FTM2 Clock Gate Control
bogdanm 82:6473597d706e 2211 uint32_t FTM3b : 1; //!< [25] FTM3 Clock Gate Control
bogdanm 82:6473597d706e 2212 uint32_t RESERVED3 : 1; //!< [26]
bogdanm 82:6473597d706e 2213 uint32_t ADC1b : 1; //!< [27] ADC1 Clock Gate Control
bogdanm 82:6473597d706e 2214 uint32_t RESERVED4 : 4; //!< [31:28]
bogdanm 82:6473597d706e 2215 } B;
bogdanm 82:6473597d706e 2216 } hw_sim_scgc3_t;
bogdanm 82:6473597d706e 2217 #endif
bogdanm 82:6473597d706e 2218
bogdanm 82:6473597d706e 2219 /*!
bogdanm 82:6473597d706e 2220 * @name Constants and macros for entire SIM_SCGC3 register
bogdanm 82:6473597d706e 2221 */
bogdanm 82:6473597d706e 2222 //@{
bogdanm 82:6473597d706e 2223 #define HW_SIM_SCGC3_ADDR (REGS_SIM_BASE + 0x1030U)
bogdanm 82:6473597d706e 2224
bogdanm 82:6473597d706e 2225 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2226 #define HW_SIM_SCGC3 (*(__IO hw_sim_scgc3_t *) HW_SIM_SCGC3_ADDR)
bogdanm 82:6473597d706e 2227 #define HW_SIM_SCGC3_RD() (HW_SIM_SCGC3.U)
bogdanm 82:6473597d706e 2228 #define HW_SIM_SCGC3_WR(v) (HW_SIM_SCGC3.U = (v))
bogdanm 82:6473597d706e 2229 #define HW_SIM_SCGC3_SET(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() | (v)))
bogdanm 82:6473597d706e 2230 #define HW_SIM_SCGC3_CLR(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() & ~(v)))
bogdanm 82:6473597d706e 2231 #define HW_SIM_SCGC3_TOG(v) (HW_SIM_SCGC3_WR(HW_SIM_SCGC3_RD() ^ (v)))
bogdanm 82:6473597d706e 2232 #endif
bogdanm 82:6473597d706e 2233 //@}
bogdanm 82:6473597d706e 2234
bogdanm 82:6473597d706e 2235 /*
bogdanm 82:6473597d706e 2236 * Constants & macros for individual SIM_SCGC3 bitfields
bogdanm 82:6473597d706e 2237 */
bogdanm 82:6473597d706e 2238
bogdanm 82:6473597d706e 2239 /*!
bogdanm 82:6473597d706e 2240 * @name Register SIM_SCGC3, field RNGA[0] (RW)
bogdanm 82:6473597d706e 2241 *
bogdanm 82:6473597d706e 2242 * This bit controls the clock gate to the RNGA module.
bogdanm 82:6473597d706e 2243 *
bogdanm 82:6473597d706e 2244 * Values:
bogdanm 82:6473597d706e 2245 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2246 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2247 */
bogdanm 82:6473597d706e 2248 //@{
bogdanm 82:6473597d706e 2249 #define BP_SIM_SCGC3_RNGA (0U) //!< Bit position for SIM_SCGC3_RNGA.
bogdanm 82:6473597d706e 2250 #define BM_SIM_SCGC3_RNGA (0x00000001U) //!< Bit mask for SIM_SCGC3_RNGA.
bogdanm 82:6473597d706e 2251 #define BS_SIM_SCGC3_RNGA (1U) //!< Bit field size in bits for SIM_SCGC3_RNGA.
bogdanm 82:6473597d706e 2252
bogdanm 82:6473597d706e 2253 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2254 //! @brief Read current value of the SIM_SCGC3_RNGA field.
bogdanm 82:6473597d706e 2255 #define BR_SIM_SCGC3_RNGA (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_RNGA))
bogdanm 82:6473597d706e 2256 #endif
bogdanm 82:6473597d706e 2257
bogdanm 82:6473597d706e 2258 //! @brief Format value for bitfield SIM_SCGC3_RNGA.
bogdanm 82:6473597d706e 2259 #define BF_SIM_SCGC3_RNGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_RNGA), uint32_t) & BM_SIM_SCGC3_RNGA)
bogdanm 82:6473597d706e 2260
bogdanm 82:6473597d706e 2261 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2262 //! @brief Set the RNGA field to a new value.
bogdanm 82:6473597d706e 2263 #define BW_SIM_SCGC3_RNGA(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_RNGA) = (v))
bogdanm 82:6473597d706e 2264 #endif
bogdanm 82:6473597d706e 2265 //@}
bogdanm 82:6473597d706e 2266
bogdanm 82:6473597d706e 2267 /*!
bogdanm 82:6473597d706e 2268 * @name Register SIM_SCGC3, field SPI2[12] (RW)
bogdanm 82:6473597d706e 2269 *
bogdanm 82:6473597d706e 2270 * This bit controls the clock gate to the SPI2 module.
bogdanm 82:6473597d706e 2271 *
bogdanm 82:6473597d706e 2272 * Values:
bogdanm 82:6473597d706e 2273 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2274 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2275 */
bogdanm 82:6473597d706e 2276 //@{
bogdanm 82:6473597d706e 2277 #define BP_SIM_SCGC3_SPI2 (12U) //!< Bit position for SIM_SCGC3_SPI2.
bogdanm 82:6473597d706e 2278 #define BM_SIM_SCGC3_SPI2 (0x00001000U) //!< Bit mask for SIM_SCGC3_SPI2.
bogdanm 82:6473597d706e 2279 #define BS_SIM_SCGC3_SPI2 (1U) //!< Bit field size in bits for SIM_SCGC3_SPI2.
bogdanm 82:6473597d706e 2280
bogdanm 82:6473597d706e 2281 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2282 //! @brief Read current value of the SIM_SCGC3_SPI2 field.
bogdanm 82:6473597d706e 2283 #define BR_SIM_SCGC3_SPI2 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SPI2))
bogdanm 82:6473597d706e 2284 #endif
bogdanm 82:6473597d706e 2285
bogdanm 82:6473597d706e 2286 //! @brief Format value for bitfield SIM_SCGC3_SPI2.
bogdanm 82:6473597d706e 2287 #define BF_SIM_SCGC3_SPI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_SPI2), uint32_t) & BM_SIM_SCGC3_SPI2)
bogdanm 82:6473597d706e 2288
bogdanm 82:6473597d706e 2289 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2290 //! @brief Set the SPI2 field to a new value.
bogdanm 82:6473597d706e 2291 #define BW_SIM_SCGC3_SPI2(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SPI2) = (v))
bogdanm 82:6473597d706e 2292 #endif
bogdanm 82:6473597d706e 2293 //@}
bogdanm 82:6473597d706e 2294
bogdanm 82:6473597d706e 2295 /*!
bogdanm 82:6473597d706e 2296 * @name Register SIM_SCGC3, field SDHC[17] (RW)
bogdanm 82:6473597d706e 2297 *
bogdanm 82:6473597d706e 2298 * This bit controls the clock gate to the SDHC module.
bogdanm 82:6473597d706e 2299 *
bogdanm 82:6473597d706e 2300 * Values:
bogdanm 82:6473597d706e 2301 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2302 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2303 */
bogdanm 82:6473597d706e 2304 //@{
bogdanm 82:6473597d706e 2305 #define BP_SIM_SCGC3_SDHC (17U) //!< Bit position for SIM_SCGC3_SDHC.
bogdanm 82:6473597d706e 2306 #define BM_SIM_SCGC3_SDHC (0x00020000U) //!< Bit mask for SIM_SCGC3_SDHC.
bogdanm 82:6473597d706e 2307 #define BS_SIM_SCGC3_SDHC (1U) //!< Bit field size in bits for SIM_SCGC3_SDHC.
bogdanm 82:6473597d706e 2308
bogdanm 82:6473597d706e 2309 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2310 //! @brief Read current value of the SIM_SCGC3_SDHC field.
bogdanm 82:6473597d706e 2311 #define BR_SIM_SCGC3_SDHC (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SDHC))
bogdanm 82:6473597d706e 2312 #endif
bogdanm 82:6473597d706e 2313
bogdanm 82:6473597d706e 2314 //! @brief Format value for bitfield SIM_SCGC3_SDHC.
bogdanm 82:6473597d706e 2315 #define BF_SIM_SCGC3_SDHC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_SDHC), uint32_t) & BM_SIM_SCGC3_SDHC)
bogdanm 82:6473597d706e 2316
bogdanm 82:6473597d706e 2317 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2318 //! @brief Set the SDHC field to a new value.
bogdanm 82:6473597d706e 2319 #define BW_SIM_SCGC3_SDHC(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_SDHC) = (v))
bogdanm 82:6473597d706e 2320 #endif
bogdanm 82:6473597d706e 2321 //@}
bogdanm 82:6473597d706e 2322
bogdanm 82:6473597d706e 2323 /*!
bogdanm 82:6473597d706e 2324 * @name Register SIM_SCGC3, field FTM2[24] (RW)
bogdanm 82:6473597d706e 2325 *
bogdanm 82:6473597d706e 2326 * This bit controls the clock gate to the FTM2 module.
bogdanm 82:6473597d706e 2327 *
bogdanm 82:6473597d706e 2328 * Values:
bogdanm 82:6473597d706e 2329 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2330 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2331 */
bogdanm 82:6473597d706e 2332 //@{
bogdanm 82:6473597d706e 2333 #define BP_SIM_SCGC3_FTM2 (24U) //!< Bit position for SIM_SCGC3_FTM2.
bogdanm 82:6473597d706e 2334 #define BM_SIM_SCGC3_FTM2 (0x01000000U) //!< Bit mask for SIM_SCGC3_FTM2.
bogdanm 82:6473597d706e 2335 #define BS_SIM_SCGC3_FTM2 (1U) //!< Bit field size in bits for SIM_SCGC3_FTM2.
bogdanm 82:6473597d706e 2336
bogdanm 82:6473597d706e 2337 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2338 //! @brief Read current value of the SIM_SCGC3_FTM2 field.
bogdanm 82:6473597d706e 2339 #define BR_SIM_SCGC3_FTM2 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM2))
bogdanm 82:6473597d706e 2340 #endif
bogdanm 82:6473597d706e 2341
bogdanm 82:6473597d706e 2342 //! @brief Format value for bitfield SIM_SCGC3_FTM2.
bogdanm 82:6473597d706e 2343 #define BF_SIM_SCGC3_FTM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_FTM2), uint32_t) & BM_SIM_SCGC3_FTM2)
bogdanm 82:6473597d706e 2344
bogdanm 82:6473597d706e 2345 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2346 //! @brief Set the FTM2 field to a new value.
bogdanm 82:6473597d706e 2347 #define BW_SIM_SCGC3_FTM2(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM2) = (v))
bogdanm 82:6473597d706e 2348 #endif
bogdanm 82:6473597d706e 2349 //@}
bogdanm 82:6473597d706e 2350
bogdanm 82:6473597d706e 2351 /*!
bogdanm 82:6473597d706e 2352 * @name Register SIM_SCGC3, field FTM3[25] (RW)
bogdanm 82:6473597d706e 2353 *
bogdanm 82:6473597d706e 2354 * This bit controls the clock gate to the FTM3 module.
bogdanm 82:6473597d706e 2355 *
bogdanm 82:6473597d706e 2356 * Values:
bogdanm 82:6473597d706e 2357 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2358 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2359 */
bogdanm 82:6473597d706e 2360 //@{
bogdanm 82:6473597d706e 2361 #define BP_SIM_SCGC3_FTM3 (25U) //!< Bit position for SIM_SCGC3_FTM3.
bogdanm 82:6473597d706e 2362 #define BM_SIM_SCGC3_FTM3 (0x02000000U) //!< Bit mask for SIM_SCGC3_FTM3.
bogdanm 82:6473597d706e 2363 #define BS_SIM_SCGC3_FTM3 (1U) //!< Bit field size in bits for SIM_SCGC3_FTM3.
bogdanm 82:6473597d706e 2364
bogdanm 82:6473597d706e 2365 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2366 //! @brief Read current value of the SIM_SCGC3_FTM3 field.
bogdanm 82:6473597d706e 2367 #define BR_SIM_SCGC3_FTM3 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM3))
bogdanm 82:6473597d706e 2368 #endif
bogdanm 82:6473597d706e 2369
bogdanm 82:6473597d706e 2370 //! @brief Format value for bitfield SIM_SCGC3_FTM3.
bogdanm 82:6473597d706e 2371 #define BF_SIM_SCGC3_FTM3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_FTM3), uint32_t) & BM_SIM_SCGC3_FTM3)
bogdanm 82:6473597d706e 2372
bogdanm 82:6473597d706e 2373 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2374 //! @brief Set the FTM3 field to a new value.
bogdanm 82:6473597d706e 2375 #define BW_SIM_SCGC3_FTM3(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_FTM3) = (v))
bogdanm 82:6473597d706e 2376 #endif
bogdanm 82:6473597d706e 2377 //@}
bogdanm 82:6473597d706e 2378
bogdanm 82:6473597d706e 2379 /*!
bogdanm 82:6473597d706e 2380 * @name Register SIM_SCGC3, field ADC1[27] (RW)
bogdanm 82:6473597d706e 2381 *
bogdanm 82:6473597d706e 2382 * This bit controls the clock gate to the ADC1 module.
bogdanm 82:6473597d706e 2383 *
bogdanm 82:6473597d706e 2384 * Values:
bogdanm 82:6473597d706e 2385 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2386 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2387 */
bogdanm 82:6473597d706e 2388 //@{
bogdanm 82:6473597d706e 2389 #define BP_SIM_SCGC3_ADC1 (27U) //!< Bit position for SIM_SCGC3_ADC1.
bogdanm 82:6473597d706e 2390 #define BM_SIM_SCGC3_ADC1 (0x08000000U) //!< Bit mask for SIM_SCGC3_ADC1.
bogdanm 82:6473597d706e 2391 #define BS_SIM_SCGC3_ADC1 (1U) //!< Bit field size in bits for SIM_SCGC3_ADC1.
bogdanm 82:6473597d706e 2392
bogdanm 82:6473597d706e 2393 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2394 //! @brief Read current value of the SIM_SCGC3_ADC1 field.
bogdanm 82:6473597d706e 2395 #define BR_SIM_SCGC3_ADC1 (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_ADC1))
bogdanm 82:6473597d706e 2396 #endif
bogdanm 82:6473597d706e 2397
bogdanm 82:6473597d706e 2398 //! @brief Format value for bitfield SIM_SCGC3_ADC1.
bogdanm 82:6473597d706e 2399 #define BF_SIM_SCGC3_ADC1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC3_ADC1), uint32_t) & BM_SIM_SCGC3_ADC1)
bogdanm 82:6473597d706e 2400
bogdanm 82:6473597d706e 2401 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2402 //! @brief Set the ADC1 field to a new value.
bogdanm 82:6473597d706e 2403 #define BW_SIM_SCGC3_ADC1(v) (BITBAND_ACCESS32(HW_SIM_SCGC3_ADDR, BP_SIM_SCGC3_ADC1) = (v))
bogdanm 82:6473597d706e 2404 #endif
bogdanm 82:6473597d706e 2405 //@}
bogdanm 82:6473597d706e 2406
bogdanm 82:6473597d706e 2407 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2408 // HW_SIM_SCGC4 - System Clock Gating Control Register 4
bogdanm 82:6473597d706e 2409 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2410
bogdanm 82:6473597d706e 2411 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2412 /*!
bogdanm 82:6473597d706e 2413 * @brief HW_SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
bogdanm 82:6473597d706e 2414 *
bogdanm 82:6473597d706e 2415 * Reset value: 0xF0100030U
bogdanm 82:6473597d706e 2416 */
bogdanm 82:6473597d706e 2417 typedef union _hw_sim_scgc4
bogdanm 82:6473597d706e 2418 {
bogdanm 82:6473597d706e 2419 uint32_t U;
bogdanm 82:6473597d706e 2420 struct _hw_sim_scgc4_bitfields
bogdanm 82:6473597d706e 2421 {
bogdanm 82:6473597d706e 2422 uint32_t RESERVED0 : 1; //!< [0]
bogdanm 82:6473597d706e 2423 uint32_t EWMb : 1; //!< [1] EWM Clock Gate Control
bogdanm 82:6473597d706e 2424 uint32_t CMTb : 1; //!< [2] CMT Clock Gate Control
bogdanm 82:6473597d706e 2425 uint32_t RESERVED1 : 3; //!< [5:3]
bogdanm 82:6473597d706e 2426 uint32_t I2C0b : 1; //!< [6] I2C0 Clock Gate Control
bogdanm 82:6473597d706e 2427 uint32_t I2C1b : 1; //!< [7] I2C1 Clock Gate Control
bogdanm 82:6473597d706e 2428 uint32_t RESERVED2 : 2; //!< [9:8]
bogdanm 82:6473597d706e 2429 uint32_t UART0b : 1; //!< [10] UART0 Clock Gate Control
bogdanm 82:6473597d706e 2430 uint32_t UART1b : 1; //!< [11] UART1 Clock Gate Control
bogdanm 82:6473597d706e 2431 uint32_t UART2b : 1; //!< [12] UART2 Clock Gate Control
bogdanm 82:6473597d706e 2432 uint32_t UART3b : 1; //!< [13] UART3 Clock Gate Control
bogdanm 82:6473597d706e 2433 uint32_t RESERVED3 : 4; //!< [17:14]
bogdanm 82:6473597d706e 2434 uint32_t USBOTG : 1; //!< [18] USB Clock Gate Control
bogdanm 82:6473597d706e 2435 uint32_t CMP : 1; //!< [19] Comparator Clock Gate Control
bogdanm 82:6473597d706e 2436 uint32_t VREFb : 1; //!< [20] VREF Clock Gate Control
bogdanm 82:6473597d706e 2437 uint32_t RESERVED4 : 11; //!< [31:21]
bogdanm 82:6473597d706e 2438 } B;
bogdanm 82:6473597d706e 2439 } hw_sim_scgc4_t;
bogdanm 82:6473597d706e 2440 #endif
bogdanm 82:6473597d706e 2441
bogdanm 82:6473597d706e 2442 /*!
bogdanm 82:6473597d706e 2443 * @name Constants and macros for entire SIM_SCGC4 register
bogdanm 82:6473597d706e 2444 */
bogdanm 82:6473597d706e 2445 //@{
bogdanm 82:6473597d706e 2446 #define HW_SIM_SCGC4_ADDR (REGS_SIM_BASE + 0x1034U)
bogdanm 82:6473597d706e 2447
bogdanm 82:6473597d706e 2448 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2449 #define HW_SIM_SCGC4 (*(__IO hw_sim_scgc4_t *) HW_SIM_SCGC4_ADDR)
bogdanm 82:6473597d706e 2450 #define HW_SIM_SCGC4_RD() (HW_SIM_SCGC4.U)
bogdanm 82:6473597d706e 2451 #define HW_SIM_SCGC4_WR(v) (HW_SIM_SCGC4.U = (v))
bogdanm 82:6473597d706e 2452 #define HW_SIM_SCGC4_SET(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() | (v)))
bogdanm 82:6473597d706e 2453 #define HW_SIM_SCGC4_CLR(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() & ~(v)))
bogdanm 82:6473597d706e 2454 #define HW_SIM_SCGC4_TOG(v) (HW_SIM_SCGC4_WR(HW_SIM_SCGC4_RD() ^ (v)))
bogdanm 82:6473597d706e 2455 #endif
bogdanm 82:6473597d706e 2456 //@}
bogdanm 82:6473597d706e 2457
bogdanm 82:6473597d706e 2458 /*
bogdanm 82:6473597d706e 2459 * Constants & macros for individual SIM_SCGC4 bitfields
bogdanm 82:6473597d706e 2460 */
bogdanm 82:6473597d706e 2461
bogdanm 82:6473597d706e 2462 /*!
bogdanm 82:6473597d706e 2463 * @name Register SIM_SCGC4, field EWM[1] (RW)
bogdanm 82:6473597d706e 2464 *
bogdanm 82:6473597d706e 2465 * This bit controls the clock gate to the EWM module.
bogdanm 82:6473597d706e 2466 *
bogdanm 82:6473597d706e 2467 * Values:
bogdanm 82:6473597d706e 2468 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2469 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2470 */
bogdanm 82:6473597d706e 2471 //@{
bogdanm 82:6473597d706e 2472 #define BP_SIM_SCGC4_EWM (1U) //!< Bit position for SIM_SCGC4_EWM.
bogdanm 82:6473597d706e 2473 #define BM_SIM_SCGC4_EWM (0x00000002U) //!< Bit mask for SIM_SCGC4_EWM.
bogdanm 82:6473597d706e 2474 #define BS_SIM_SCGC4_EWM (1U) //!< Bit field size in bits for SIM_SCGC4_EWM.
bogdanm 82:6473597d706e 2475
bogdanm 82:6473597d706e 2476 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2477 //! @brief Read current value of the SIM_SCGC4_EWM field.
bogdanm 82:6473597d706e 2478 #define BR_SIM_SCGC4_EWM (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_EWM))
bogdanm 82:6473597d706e 2479 #endif
bogdanm 82:6473597d706e 2480
bogdanm 82:6473597d706e 2481 //! @brief Format value for bitfield SIM_SCGC4_EWM.
bogdanm 82:6473597d706e 2482 #define BF_SIM_SCGC4_EWM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_EWM), uint32_t) & BM_SIM_SCGC4_EWM)
bogdanm 82:6473597d706e 2483
bogdanm 82:6473597d706e 2484 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2485 //! @brief Set the EWM field to a new value.
bogdanm 82:6473597d706e 2486 #define BW_SIM_SCGC4_EWM(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_EWM) = (v))
bogdanm 82:6473597d706e 2487 #endif
bogdanm 82:6473597d706e 2488 //@}
bogdanm 82:6473597d706e 2489
bogdanm 82:6473597d706e 2490 /*!
bogdanm 82:6473597d706e 2491 * @name Register SIM_SCGC4, field CMT[2] (RW)
bogdanm 82:6473597d706e 2492 *
bogdanm 82:6473597d706e 2493 * This bit controls the clock gate to the CMT module.
bogdanm 82:6473597d706e 2494 *
bogdanm 82:6473597d706e 2495 * Values:
bogdanm 82:6473597d706e 2496 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2497 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2498 */
bogdanm 82:6473597d706e 2499 //@{
bogdanm 82:6473597d706e 2500 #define BP_SIM_SCGC4_CMT (2U) //!< Bit position for SIM_SCGC4_CMT.
bogdanm 82:6473597d706e 2501 #define BM_SIM_SCGC4_CMT (0x00000004U) //!< Bit mask for SIM_SCGC4_CMT.
bogdanm 82:6473597d706e 2502 #define BS_SIM_SCGC4_CMT (1U) //!< Bit field size in bits for SIM_SCGC4_CMT.
bogdanm 82:6473597d706e 2503
bogdanm 82:6473597d706e 2504 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2505 //! @brief Read current value of the SIM_SCGC4_CMT field.
bogdanm 82:6473597d706e 2506 #define BR_SIM_SCGC4_CMT (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMT))
bogdanm 82:6473597d706e 2507 #endif
bogdanm 82:6473597d706e 2508
bogdanm 82:6473597d706e 2509 //! @brief Format value for bitfield SIM_SCGC4_CMT.
bogdanm 82:6473597d706e 2510 #define BF_SIM_SCGC4_CMT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_CMT), uint32_t) & BM_SIM_SCGC4_CMT)
bogdanm 82:6473597d706e 2511
bogdanm 82:6473597d706e 2512 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2513 //! @brief Set the CMT field to a new value.
bogdanm 82:6473597d706e 2514 #define BW_SIM_SCGC4_CMT(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMT) = (v))
bogdanm 82:6473597d706e 2515 #endif
bogdanm 82:6473597d706e 2516 //@}
bogdanm 82:6473597d706e 2517
bogdanm 82:6473597d706e 2518 /*!
bogdanm 82:6473597d706e 2519 * @name Register SIM_SCGC4, field I2C0[6] (RW)
bogdanm 82:6473597d706e 2520 *
bogdanm 82:6473597d706e 2521 * This bit controls the clock gate to the I 2 C0 module.
bogdanm 82:6473597d706e 2522 *
bogdanm 82:6473597d706e 2523 * Values:
bogdanm 82:6473597d706e 2524 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2525 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2526 */
bogdanm 82:6473597d706e 2527 //@{
bogdanm 82:6473597d706e 2528 #define BP_SIM_SCGC4_I2C0 (6U) //!< Bit position for SIM_SCGC4_I2C0.
bogdanm 82:6473597d706e 2529 #define BM_SIM_SCGC4_I2C0 (0x00000040U) //!< Bit mask for SIM_SCGC4_I2C0.
bogdanm 82:6473597d706e 2530 #define BS_SIM_SCGC4_I2C0 (1U) //!< Bit field size in bits for SIM_SCGC4_I2C0.
bogdanm 82:6473597d706e 2531
bogdanm 82:6473597d706e 2532 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2533 //! @brief Read current value of the SIM_SCGC4_I2C0 field.
bogdanm 82:6473597d706e 2534 #define BR_SIM_SCGC4_I2C0 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C0))
bogdanm 82:6473597d706e 2535 #endif
bogdanm 82:6473597d706e 2536
bogdanm 82:6473597d706e 2537 //! @brief Format value for bitfield SIM_SCGC4_I2C0.
bogdanm 82:6473597d706e 2538 #define BF_SIM_SCGC4_I2C0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_I2C0), uint32_t) & BM_SIM_SCGC4_I2C0)
bogdanm 82:6473597d706e 2539
bogdanm 82:6473597d706e 2540 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2541 //! @brief Set the I2C0 field to a new value.
bogdanm 82:6473597d706e 2542 #define BW_SIM_SCGC4_I2C0(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C0) = (v))
bogdanm 82:6473597d706e 2543 #endif
bogdanm 82:6473597d706e 2544 //@}
bogdanm 82:6473597d706e 2545
bogdanm 82:6473597d706e 2546 /*!
bogdanm 82:6473597d706e 2547 * @name Register SIM_SCGC4, field I2C1[7] (RW)
bogdanm 82:6473597d706e 2548 *
bogdanm 82:6473597d706e 2549 * This bit controls the clock gate to the I 2 C1 module.
bogdanm 82:6473597d706e 2550 *
bogdanm 82:6473597d706e 2551 * Values:
bogdanm 82:6473597d706e 2552 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2553 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2554 */
bogdanm 82:6473597d706e 2555 //@{
bogdanm 82:6473597d706e 2556 #define BP_SIM_SCGC4_I2C1 (7U) //!< Bit position for SIM_SCGC4_I2C1.
bogdanm 82:6473597d706e 2557 #define BM_SIM_SCGC4_I2C1 (0x00000080U) //!< Bit mask for SIM_SCGC4_I2C1.
bogdanm 82:6473597d706e 2558 #define BS_SIM_SCGC4_I2C1 (1U) //!< Bit field size in bits for SIM_SCGC4_I2C1.
bogdanm 82:6473597d706e 2559
bogdanm 82:6473597d706e 2560 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2561 //! @brief Read current value of the SIM_SCGC4_I2C1 field.
bogdanm 82:6473597d706e 2562 #define BR_SIM_SCGC4_I2C1 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C1))
bogdanm 82:6473597d706e 2563 #endif
bogdanm 82:6473597d706e 2564
bogdanm 82:6473597d706e 2565 //! @brief Format value for bitfield SIM_SCGC4_I2C1.
bogdanm 82:6473597d706e 2566 #define BF_SIM_SCGC4_I2C1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_I2C1), uint32_t) & BM_SIM_SCGC4_I2C1)
bogdanm 82:6473597d706e 2567
bogdanm 82:6473597d706e 2568 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2569 //! @brief Set the I2C1 field to a new value.
bogdanm 82:6473597d706e 2570 #define BW_SIM_SCGC4_I2C1(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_I2C1) = (v))
bogdanm 82:6473597d706e 2571 #endif
bogdanm 82:6473597d706e 2572 //@}
bogdanm 82:6473597d706e 2573
bogdanm 82:6473597d706e 2574 /*!
bogdanm 82:6473597d706e 2575 * @name Register SIM_SCGC4, field UART0[10] (RW)
bogdanm 82:6473597d706e 2576 *
bogdanm 82:6473597d706e 2577 * This bit controls the clock gate to the UART0 module.
bogdanm 82:6473597d706e 2578 *
bogdanm 82:6473597d706e 2579 * Values:
bogdanm 82:6473597d706e 2580 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2581 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2582 */
bogdanm 82:6473597d706e 2583 //@{
bogdanm 82:6473597d706e 2584 #define BP_SIM_SCGC4_UART0 (10U) //!< Bit position for SIM_SCGC4_UART0.
bogdanm 82:6473597d706e 2585 #define BM_SIM_SCGC4_UART0 (0x00000400U) //!< Bit mask for SIM_SCGC4_UART0.
bogdanm 82:6473597d706e 2586 #define BS_SIM_SCGC4_UART0 (1U) //!< Bit field size in bits for SIM_SCGC4_UART0.
bogdanm 82:6473597d706e 2587
bogdanm 82:6473597d706e 2588 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2589 //! @brief Read current value of the SIM_SCGC4_UART0 field.
bogdanm 82:6473597d706e 2590 #define BR_SIM_SCGC4_UART0 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART0))
bogdanm 82:6473597d706e 2591 #endif
bogdanm 82:6473597d706e 2592
bogdanm 82:6473597d706e 2593 //! @brief Format value for bitfield SIM_SCGC4_UART0.
bogdanm 82:6473597d706e 2594 #define BF_SIM_SCGC4_UART0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART0), uint32_t) & BM_SIM_SCGC4_UART0)
bogdanm 82:6473597d706e 2595
bogdanm 82:6473597d706e 2596 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2597 //! @brief Set the UART0 field to a new value.
bogdanm 82:6473597d706e 2598 #define BW_SIM_SCGC4_UART0(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART0) = (v))
bogdanm 82:6473597d706e 2599 #endif
bogdanm 82:6473597d706e 2600 //@}
bogdanm 82:6473597d706e 2601
bogdanm 82:6473597d706e 2602 /*!
bogdanm 82:6473597d706e 2603 * @name Register SIM_SCGC4, field UART1[11] (RW)
bogdanm 82:6473597d706e 2604 *
bogdanm 82:6473597d706e 2605 * This bit controls the clock gate to the UART1 module.
bogdanm 82:6473597d706e 2606 *
bogdanm 82:6473597d706e 2607 * Values:
bogdanm 82:6473597d706e 2608 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2609 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2610 */
bogdanm 82:6473597d706e 2611 //@{
bogdanm 82:6473597d706e 2612 #define BP_SIM_SCGC4_UART1 (11U) //!< Bit position for SIM_SCGC4_UART1.
bogdanm 82:6473597d706e 2613 #define BM_SIM_SCGC4_UART1 (0x00000800U) //!< Bit mask for SIM_SCGC4_UART1.
bogdanm 82:6473597d706e 2614 #define BS_SIM_SCGC4_UART1 (1U) //!< Bit field size in bits for SIM_SCGC4_UART1.
bogdanm 82:6473597d706e 2615
bogdanm 82:6473597d706e 2616 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2617 //! @brief Read current value of the SIM_SCGC4_UART1 field.
bogdanm 82:6473597d706e 2618 #define BR_SIM_SCGC4_UART1 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART1))
bogdanm 82:6473597d706e 2619 #endif
bogdanm 82:6473597d706e 2620
bogdanm 82:6473597d706e 2621 //! @brief Format value for bitfield SIM_SCGC4_UART1.
bogdanm 82:6473597d706e 2622 #define BF_SIM_SCGC4_UART1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART1), uint32_t) & BM_SIM_SCGC4_UART1)
bogdanm 82:6473597d706e 2623
bogdanm 82:6473597d706e 2624 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2625 //! @brief Set the UART1 field to a new value.
bogdanm 82:6473597d706e 2626 #define BW_SIM_SCGC4_UART1(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART1) = (v))
bogdanm 82:6473597d706e 2627 #endif
bogdanm 82:6473597d706e 2628 //@}
bogdanm 82:6473597d706e 2629
bogdanm 82:6473597d706e 2630 /*!
bogdanm 82:6473597d706e 2631 * @name Register SIM_SCGC4, field UART2[12] (RW)
bogdanm 82:6473597d706e 2632 *
bogdanm 82:6473597d706e 2633 * This bit controls the clock gate to the UART2 module.
bogdanm 82:6473597d706e 2634 *
bogdanm 82:6473597d706e 2635 * Values:
bogdanm 82:6473597d706e 2636 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2637 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2638 */
bogdanm 82:6473597d706e 2639 //@{
bogdanm 82:6473597d706e 2640 #define BP_SIM_SCGC4_UART2 (12U) //!< Bit position for SIM_SCGC4_UART2.
bogdanm 82:6473597d706e 2641 #define BM_SIM_SCGC4_UART2 (0x00001000U) //!< Bit mask for SIM_SCGC4_UART2.
bogdanm 82:6473597d706e 2642 #define BS_SIM_SCGC4_UART2 (1U) //!< Bit field size in bits for SIM_SCGC4_UART2.
bogdanm 82:6473597d706e 2643
bogdanm 82:6473597d706e 2644 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2645 //! @brief Read current value of the SIM_SCGC4_UART2 field.
bogdanm 82:6473597d706e 2646 #define BR_SIM_SCGC4_UART2 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART2))
bogdanm 82:6473597d706e 2647 #endif
bogdanm 82:6473597d706e 2648
bogdanm 82:6473597d706e 2649 //! @brief Format value for bitfield SIM_SCGC4_UART2.
bogdanm 82:6473597d706e 2650 #define BF_SIM_SCGC4_UART2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART2), uint32_t) & BM_SIM_SCGC4_UART2)
bogdanm 82:6473597d706e 2651
bogdanm 82:6473597d706e 2652 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2653 //! @brief Set the UART2 field to a new value.
bogdanm 82:6473597d706e 2654 #define BW_SIM_SCGC4_UART2(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART2) = (v))
bogdanm 82:6473597d706e 2655 #endif
bogdanm 82:6473597d706e 2656 //@}
bogdanm 82:6473597d706e 2657
bogdanm 82:6473597d706e 2658 /*!
bogdanm 82:6473597d706e 2659 * @name Register SIM_SCGC4, field UART3[13] (RW)
bogdanm 82:6473597d706e 2660 *
bogdanm 82:6473597d706e 2661 * This bit controls the clock gate to the UART3 module.
bogdanm 82:6473597d706e 2662 *
bogdanm 82:6473597d706e 2663 * Values:
bogdanm 82:6473597d706e 2664 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2665 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2666 */
bogdanm 82:6473597d706e 2667 //@{
bogdanm 82:6473597d706e 2668 #define BP_SIM_SCGC4_UART3 (13U) //!< Bit position for SIM_SCGC4_UART3.
bogdanm 82:6473597d706e 2669 #define BM_SIM_SCGC4_UART3 (0x00002000U) //!< Bit mask for SIM_SCGC4_UART3.
bogdanm 82:6473597d706e 2670 #define BS_SIM_SCGC4_UART3 (1U) //!< Bit field size in bits for SIM_SCGC4_UART3.
bogdanm 82:6473597d706e 2671
bogdanm 82:6473597d706e 2672 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2673 //! @brief Read current value of the SIM_SCGC4_UART3 field.
bogdanm 82:6473597d706e 2674 #define BR_SIM_SCGC4_UART3 (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART3))
bogdanm 82:6473597d706e 2675 #endif
bogdanm 82:6473597d706e 2676
bogdanm 82:6473597d706e 2677 //! @brief Format value for bitfield SIM_SCGC4_UART3.
bogdanm 82:6473597d706e 2678 #define BF_SIM_SCGC4_UART3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_UART3), uint32_t) & BM_SIM_SCGC4_UART3)
bogdanm 82:6473597d706e 2679
bogdanm 82:6473597d706e 2680 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2681 //! @brief Set the UART3 field to a new value.
bogdanm 82:6473597d706e 2682 #define BW_SIM_SCGC4_UART3(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_UART3) = (v))
bogdanm 82:6473597d706e 2683 #endif
bogdanm 82:6473597d706e 2684 //@}
bogdanm 82:6473597d706e 2685
bogdanm 82:6473597d706e 2686 /*!
bogdanm 82:6473597d706e 2687 * @name Register SIM_SCGC4, field USBOTG[18] (RW)
bogdanm 82:6473597d706e 2688 *
bogdanm 82:6473597d706e 2689 * This bit controls the clock gate to the USB module.
bogdanm 82:6473597d706e 2690 *
bogdanm 82:6473597d706e 2691 * Values:
bogdanm 82:6473597d706e 2692 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2693 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2694 */
bogdanm 82:6473597d706e 2695 //@{
bogdanm 82:6473597d706e 2696 #define BP_SIM_SCGC4_USBOTG (18U) //!< Bit position for SIM_SCGC4_USBOTG.
bogdanm 82:6473597d706e 2697 #define BM_SIM_SCGC4_USBOTG (0x00040000U) //!< Bit mask for SIM_SCGC4_USBOTG.
bogdanm 82:6473597d706e 2698 #define BS_SIM_SCGC4_USBOTG (1U) //!< Bit field size in bits for SIM_SCGC4_USBOTG.
bogdanm 82:6473597d706e 2699
bogdanm 82:6473597d706e 2700 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2701 //! @brief Read current value of the SIM_SCGC4_USBOTG field.
bogdanm 82:6473597d706e 2702 #define BR_SIM_SCGC4_USBOTG (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_USBOTG))
bogdanm 82:6473597d706e 2703 #endif
bogdanm 82:6473597d706e 2704
bogdanm 82:6473597d706e 2705 //! @brief Format value for bitfield SIM_SCGC4_USBOTG.
bogdanm 82:6473597d706e 2706 #define BF_SIM_SCGC4_USBOTG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_USBOTG), uint32_t) & BM_SIM_SCGC4_USBOTG)
bogdanm 82:6473597d706e 2707
bogdanm 82:6473597d706e 2708 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2709 //! @brief Set the USBOTG field to a new value.
bogdanm 82:6473597d706e 2710 #define BW_SIM_SCGC4_USBOTG(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_USBOTG) = (v))
bogdanm 82:6473597d706e 2711 #endif
bogdanm 82:6473597d706e 2712 //@}
bogdanm 82:6473597d706e 2713
bogdanm 82:6473597d706e 2714 /*!
bogdanm 82:6473597d706e 2715 * @name Register SIM_SCGC4, field CMP[19] (RW)
bogdanm 82:6473597d706e 2716 *
bogdanm 82:6473597d706e 2717 * This bit controls the clock gate to the comparator module.
bogdanm 82:6473597d706e 2718 *
bogdanm 82:6473597d706e 2719 * Values:
bogdanm 82:6473597d706e 2720 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2721 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2722 */
bogdanm 82:6473597d706e 2723 //@{
bogdanm 82:6473597d706e 2724 #define BP_SIM_SCGC4_CMP (19U) //!< Bit position for SIM_SCGC4_CMP.
bogdanm 82:6473597d706e 2725 #define BM_SIM_SCGC4_CMP (0x00080000U) //!< Bit mask for SIM_SCGC4_CMP.
bogdanm 82:6473597d706e 2726 #define BS_SIM_SCGC4_CMP (1U) //!< Bit field size in bits for SIM_SCGC4_CMP.
bogdanm 82:6473597d706e 2727
bogdanm 82:6473597d706e 2728 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2729 //! @brief Read current value of the SIM_SCGC4_CMP field.
bogdanm 82:6473597d706e 2730 #define BR_SIM_SCGC4_CMP (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMP))
bogdanm 82:6473597d706e 2731 #endif
bogdanm 82:6473597d706e 2732
bogdanm 82:6473597d706e 2733 //! @brief Format value for bitfield SIM_SCGC4_CMP.
bogdanm 82:6473597d706e 2734 #define BF_SIM_SCGC4_CMP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_CMP), uint32_t) & BM_SIM_SCGC4_CMP)
bogdanm 82:6473597d706e 2735
bogdanm 82:6473597d706e 2736 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2737 //! @brief Set the CMP field to a new value.
bogdanm 82:6473597d706e 2738 #define BW_SIM_SCGC4_CMP(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_CMP) = (v))
bogdanm 82:6473597d706e 2739 #endif
bogdanm 82:6473597d706e 2740 //@}
bogdanm 82:6473597d706e 2741
bogdanm 82:6473597d706e 2742 /*!
bogdanm 82:6473597d706e 2743 * @name Register SIM_SCGC4, field VREF[20] (RW)
bogdanm 82:6473597d706e 2744 *
bogdanm 82:6473597d706e 2745 * This bit controls the clock gate to the VREF module.
bogdanm 82:6473597d706e 2746 *
bogdanm 82:6473597d706e 2747 * Values:
bogdanm 82:6473597d706e 2748 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2749 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2750 */
bogdanm 82:6473597d706e 2751 //@{
bogdanm 82:6473597d706e 2752 #define BP_SIM_SCGC4_VREF (20U) //!< Bit position for SIM_SCGC4_VREF.
bogdanm 82:6473597d706e 2753 #define BM_SIM_SCGC4_VREF (0x00100000U) //!< Bit mask for SIM_SCGC4_VREF.
bogdanm 82:6473597d706e 2754 #define BS_SIM_SCGC4_VREF (1U) //!< Bit field size in bits for SIM_SCGC4_VREF.
bogdanm 82:6473597d706e 2755
bogdanm 82:6473597d706e 2756 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2757 //! @brief Read current value of the SIM_SCGC4_VREF field.
bogdanm 82:6473597d706e 2758 #define BR_SIM_SCGC4_VREF (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_VREF))
bogdanm 82:6473597d706e 2759 #endif
bogdanm 82:6473597d706e 2760
bogdanm 82:6473597d706e 2761 //! @brief Format value for bitfield SIM_SCGC4_VREF.
bogdanm 82:6473597d706e 2762 #define BF_SIM_SCGC4_VREF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC4_VREF), uint32_t) & BM_SIM_SCGC4_VREF)
bogdanm 82:6473597d706e 2763
bogdanm 82:6473597d706e 2764 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2765 //! @brief Set the VREF field to a new value.
bogdanm 82:6473597d706e 2766 #define BW_SIM_SCGC4_VREF(v) (BITBAND_ACCESS32(HW_SIM_SCGC4_ADDR, BP_SIM_SCGC4_VREF) = (v))
bogdanm 82:6473597d706e 2767 #endif
bogdanm 82:6473597d706e 2768 //@}
bogdanm 82:6473597d706e 2769
bogdanm 82:6473597d706e 2770 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2771 // HW_SIM_SCGC5 - System Clock Gating Control Register 5
bogdanm 82:6473597d706e 2772 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2773
bogdanm 82:6473597d706e 2774 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2775 /*!
bogdanm 82:6473597d706e 2776 * @brief HW_SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
bogdanm 82:6473597d706e 2777 *
bogdanm 82:6473597d706e 2778 * Reset value: 0x00040182U
bogdanm 82:6473597d706e 2779 */
bogdanm 82:6473597d706e 2780 typedef union _hw_sim_scgc5
bogdanm 82:6473597d706e 2781 {
bogdanm 82:6473597d706e 2782 uint32_t U;
bogdanm 82:6473597d706e 2783 struct _hw_sim_scgc5_bitfields
bogdanm 82:6473597d706e 2784 {
bogdanm 82:6473597d706e 2785 uint32_t LPTMR : 1; //!< [0] Low Power Timer Access Control
bogdanm 82:6473597d706e 2786 uint32_t RESERVED0 : 8; //!< [8:1]
bogdanm 82:6473597d706e 2787 uint32_t PORTAb : 1; //!< [9] Port A Clock Gate Control
bogdanm 82:6473597d706e 2788 uint32_t PORTBb : 1; //!< [10] Port B Clock Gate Control
bogdanm 82:6473597d706e 2789 uint32_t PORTCb : 1; //!< [11] Port C Clock Gate Control
bogdanm 82:6473597d706e 2790 uint32_t PORTDb : 1; //!< [12] Port D Clock Gate Control
bogdanm 82:6473597d706e 2791 uint32_t PORTEb : 1; //!< [13] Port E Clock Gate Control
bogdanm 82:6473597d706e 2792 uint32_t RESERVED1 : 18; //!< [31:14]
bogdanm 82:6473597d706e 2793 } B;
bogdanm 82:6473597d706e 2794 } hw_sim_scgc5_t;
bogdanm 82:6473597d706e 2795 #endif
bogdanm 82:6473597d706e 2796
bogdanm 82:6473597d706e 2797 /*!
bogdanm 82:6473597d706e 2798 * @name Constants and macros for entire SIM_SCGC5 register
bogdanm 82:6473597d706e 2799 */
bogdanm 82:6473597d706e 2800 //@{
bogdanm 82:6473597d706e 2801 #define HW_SIM_SCGC5_ADDR (REGS_SIM_BASE + 0x1038U)
bogdanm 82:6473597d706e 2802
bogdanm 82:6473597d706e 2803 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2804 #define HW_SIM_SCGC5 (*(__IO hw_sim_scgc5_t *) HW_SIM_SCGC5_ADDR)
bogdanm 82:6473597d706e 2805 #define HW_SIM_SCGC5_RD() (HW_SIM_SCGC5.U)
bogdanm 82:6473597d706e 2806 #define HW_SIM_SCGC5_WR(v) (HW_SIM_SCGC5.U = (v))
bogdanm 82:6473597d706e 2807 #define HW_SIM_SCGC5_SET(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() | (v)))
bogdanm 82:6473597d706e 2808 #define HW_SIM_SCGC5_CLR(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() & ~(v)))
bogdanm 82:6473597d706e 2809 #define HW_SIM_SCGC5_TOG(v) (HW_SIM_SCGC5_WR(HW_SIM_SCGC5_RD() ^ (v)))
bogdanm 82:6473597d706e 2810 #endif
bogdanm 82:6473597d706e 2811 //@}
bogdanm 82:6473597d706e 2812
bogdanm 82:6473597d706e 2813 /*
bogdanm 82:6473597d706e 2814 * Constants & macros for individual SIM_SCGC5 bitfields
bogdanm 82:6473597d706e 2815 */
bogdanm 82:6473597d706e 2816
bogdanm 82:6473597d706e 2817 /*!
bogdanm 82:6473597d706e 2818 * @name Register SIM_SCGC5, field LPTMR[0] (RW)
bogdanm 82:6473597d706e 2819 *
bogdanm 82:6473597d706e 2820 * This bit controls software access to the Low Power Timer module.
bogdanm 82:6473597d706e 2821 *
bogdanm 82:6473597d706e 2822 * Values:
bogdanm 82:6473597d706e 2823 * - 0 - Access disabled
bogdanm 82:6473597d706e 2824 * - 1 - Access enabled
bogdanm 82:6473597d706e 2825 */
bogdanm 82:6473597d706e 2826 //@{
bogdanm 82:6473597d706e 2827 #define BP_SIM_SCGC5_LPTMR (0U) //!< Bit position for SIM_SCGC5_LPTMR.
bogdanm 82:6473597d706e 2828 #define BM_SIM_SCGC5_LPTMR (0x00000001U) //!< Bit mask for SIM_SCGC5_LPTMR.
bogdanm 82:6473597d706e 2829 #define BS_SIM_SCGC5_LPTMR (1U) //!< Bit field size in bits for SIM_SCGC5_LPTMR.
bogdanm 82:6473597d706e 2830
bogdanm 82:6473597d706e 2831 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2832 //! @brief Read current value of the SIM_SCGC5_LPTMR field.
bogdanm 82:6473597d706e 2833 #define BR_SIM_SCGC5_LPTMR (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_LPTMR))
bogdanm 82:6473597d706e 2834 #endif
bogdanm 82:6473597d706e 2835
bogdanm 82:6473597d706e 2836 //! @brief Format value for bitfield SIM_SCGC5_LPTMR.
bogdanm 82:6473597d706e 2837 #define BF_SIM_SCGC5_LPTMR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_LPTMR), uint32_t) & BM_SIM_SCGC5_LPTMR)
bogdanm 82:6473597d706e 2838
bogdanm 82:6473597d706e 2839 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2840 //! @brief Set the LPTMR field to a new value.
bogdanm 82:6473597d706e 2841 #define BW_SIM_SCGC5_LPTMR(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_LPTMR) = (v))
bogdanm 82:6473597d706e 2842 #endif
bogdanm 82:6473597d706e 2843 //@}
bogdanm 82:6473597d706e 2844
bogdanm 82:6473597d706e 2845 /*!
bogdanm 82:6473597d706e 2846 * @name Register SIM_SCGC5, field PORTA[9] (RW)
bogdanm 82:6473597d706e 2847 *
bogdanm 82:6473597d706e 2848 * This bit controls the clock gate to the Port A module.
bogdanm 82:6473597d706e 2849 *
bogdanm 82:6473597d706e 2850 * Values:
bogdanm 82:6473597d706e 2851 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2852 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2853 */
bogdanm 82:6473597d706e 2854 //@{
bogdanm 82:6473597d706e 2855 #define BP_SIM_SCGC5_PORTA (9U) //!< Bit position for SIM_SCGC5_PORTA.
bogdanm 82:6473597d706e 2856 #define BM_SIM_SCGC5_PORTA (0x00000200U) //!< Bit mask for SIM_SCGC5_PORTA.
bogdanm 82:6473597d706e 2857 #define BS_SIM_SCGC5_PORTA (1U) //!< Bit field size in bits for SIM_SCGC5_PORTA.
bogdanm 82:6473597d706e 2858
bogdanm 82:6473597d706e 2859 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2860 //! @brief Read current value of the SIM_SCGC5_PORTA field.
bogdanm 82:6473597d706e 2861 #define BR_SIM_SCGC5_PORTA (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTA))
bogdanm 82:6473597d706e 2862 #endif
bogdanm 82:6473597d706e 2863
bogdanm 82:6473597d706e 2864 //! @brief Format value for bitfield SIM_SCGC5_PORTA.
bogdanm 82:6473597d706e 2865 #define BF_SIM_SCGC5_PORTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTA), uint32_t) & BM_SIM_SCGC5_PORTA)
bogdanm 82:6473597d706e 2866
bogdanm 82:6473597d706e 2867 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2868 //! @brief Set the PORTA field to a new value.
bogdanm 82:6473597d706e 2869 #define BW_SIM_SCGC5_PORTA(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTA) = (v))
bogdanm 82:6473597d706e 2870 #endif
bogdanm 82:6473597d706e 2871 //@}
bogdanm 82:6473597d706e 2872
bogdanm 82:6473597d706e 2873 /*!
bogdanm 82:6473597d706e 2874 * @name Register SIM_SCGC5, field PORTB[10] (RW)
bogdanm 82:6473597d706e 2875 *
bogdanm 82:6473597d706e 2876 * This bit controls the clock gate to the Port B module.
bogdanm 82:6473597d706e 2877 *
bogdanm 82:6473597d706e 2878 * Values:
bogdanm 82:6473597d706e 2879 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2880 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2881 */
bogdanm 82:6473597d706e 2882 //@{
bogdanm 82:6473597d706e 2883 #define BP_SIM_SCGC5_PORTB (10U) //!< Bit position for SIM_SCGC5_PORTB.
bogdanm 82:6473597d706e 2884 #define BM_SIM_SCGC5_PORTB (0x00000400U) //!< Bit mask for SIM_SCGC5_PORTB.
bogdanm 82:6473597d706e 2885 #define BS_SIM_SCGC5_PORTB (1U) //!< Bit field size in bits for SIM_SCGC5_PORTB.
bogdanm 82:6473597d706e 2886
bogdanm 82:6473597d706e 2887 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2888 //! @brief Read current value of the SIM_SCGC5_PORTB field.
bogdanm 82:6473597d706e 2889 #define BR_SIM_SCGC5_PORTB (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTB))
bogdanm 82:6473597d706e 2890 #endif
bogdanm 82:6473597d706e 2891
bogdanm 82:6473597d706e 2892 //! @brief Format value for bitfield SIM_SCGC5_PORTB.
bogdanm 82:6473597d706e 2893 #define BF_SIM_SCGC5_PORTB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTB), uint32_t) & BM_SIM_SCGC5_PORTB)
bogdanm 82:6473597d706e 2894
bogdanm 82:6473597d706e 2895 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2896 //! @brief Set the PORTB field to a new value.
bogdanm 82:6473597d706e 2897 #define BW_SIM_SCGC5_PORTB(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTB) = (v))
bogdanm 82:6473597d706e 2898 #endif
bogdanm 82:6473597d706e 2899 //@}
bogdanm 82:6473597d706e 2900
bogdanm 82:6473597d706e 2901 /*!
bogdanm 82:6473597d706e 2902 * @name Register SIM_SCGC5, field PORTC[11] (RW)
bogdanm 82:6473597d706e 2903 *
bogdanm 82:6473597d706e 2904 * This bit controls the clock gate to the Port C module.
bogdanm 82:6473597d706e 2905 *
bogdanm 82:6473597d706e 2906 * Values:
bogdanm 82:6473597d706e 2907 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2908 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2909 */
bogdanm 82:6473597d706e 2910 //@{
bogdanm 82:6473597d706e 2911 #define BP_SIM_SCGC5_PORTC (11U) //!< Bit position for SIM_SCGC5_PORTC.
bogdanm 82:6473597d706e 2912 #define BM_SIM_SCGC5_PORTC (0x00000800U) //!< Bit mask for SIM_SCGC5_PORTC.
bogdanm 82:6473597d706e 2913 #define BS_SIM_SCGC5_PORTC (1U) //!< Bit field size in bits for SIM_SCGC5_PORTC.
bogdanm 82:6473597d706e 2914
bogdanm 82:6473597d706e 2915 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2916 //! @brief Read current value of the SIM_SCGC5_PORTC field.
bogdanm 82:6473597d706e 2917 #define BR_SIM_SCGC5_PORTC (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTC))
bogdanm 82:6473597d706e 2918 #endif
bogdanm 82:6473597d706e 2919
bogdanm 82:6473597d706e 2920 //! @brief Format value for bitfield SIM_SCGC5_PORTC.
bogdanm 82:6473597d706e 2921 #define BF_SIM_SCGC5_PORTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTC), uint32_t) & BM_SIM_SCGC5_PORTC)
bogdanm 82:6473597d706e 2922
bogdanm 82:6473597d706e 2923 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2924 //! @brief Set the PORTC field to a new value.
bogdanm 82:6473597d706e 2925 #define BW_SIM_SCGC5_PORTC(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTC) = (v))
bogdanm 82:6473597d706e 2926 #endif
bogdanm 82:6473597d706e 2927 //@}
bogdanm 82:6473597d706e 2928
bogdanm 82:6473597d706e 2929 /*!
bogdanm 82:6473597d706e 2930 * @name Register SIM_SCGC5, field PORTD[12] (RW)
bogdanm 82:6473597d706e 2931 *
bogdanm 82:6473597d706e 2932 * This bit controls the clock gate to the Port D module.
bogdanm 82:6473597d706e 2933 *
bogdanm 82:6473597d706e 2934 * Values:
bogdanm 82:6473597d706e 2935 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2936 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2937 */
bogdanm 82:6473597d706e 2938 //@{
bogdanm 82:6473597d706e 2939 #define BP_SIM_SCGC5_PORTD (12U) //!< Bit position for SIM_SCGC5_PORTD.
bogdanm 82:6473597d706e 2940 #define BM_SIM_SCGC5_PORTD (0x00001000U) //!< Bit mask for SIM_SCGC5_PORTD.
bogdanm 82:6473597d706e 2941 #define BS_SIM_SCGC5_PORTD (1U) //!< Bit field size in bits for SIM_SCGC5_PORTD.
bogdanm 82:6473597d706e 2942
bogdanm 82:6473597d706e 2943 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2944 //! @brief Read current value of the SIM_SCGC5_PORTD field.
bogdanm 82:6473597d706e 2945 #define BR_SIM_SCGC5_PORTD (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTD))
bogdanm 82:6473597d706e 2946 #endif
bogdanm 82:6473597d706e 2947
bogdanm 82:6473597d706e 2948 //! @brief Format value for bitfield SIM_SCGC5_PORTD.
bogdanm 82:6473597d706e 2949 #define BF_SIM_SCGC5_PORTD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTD), uint32_t) & BM_SIM_SCGC5_PORTD)
bogdanm 82:6473597d706e 2950
bogdanm 82:6473597d706e 2951 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2952 //! @brief Set the PORTD field to a new value.
bogdanm 82:6473597d706e 2953 #define BW_SIM_SCGC5_PORTD(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTD) = (v))
bogdanm 82:6473597d706e 2954 #endif
bogdanm 82:6473597d706e 2955 //@}
bogdanm 82:6473597d706e 2956
bogdanm 82:6473597d706e 2957 /*!
bogdanm 82:6473597d706e 2958 * @name Register SIM_SCGC5, field PORTE[13] (RW)
bogdanm 82:6473597d706e 2959 *
bogdanm 82:6473597d706e 2960 * This bit controls the clock gate to the Port E module.
bogdanm 82:6473597d706e 2961 *
bogdanm 82:6473597d706e 2962 * Values:
bogdanm 82:6473597d706e 2963 * - 0 - Clock disabled
bogdanm 82:6473597d706e 2964 * - 1 - Clock enabled
bogdanm 82:6473597d706e 2965 */
bogdanm 82:6473597d706e 2966 //@{
bogdanm 82:6473597d706e 2967 #define BP_SIM_SCGC5_PORTE (13U) //!< Bit position for SIM_SCGC5_PORTE.
bogdanm 82:6473597d706e 2968 #define BM_SIM_SCGC5_PORTE (0x00002000U) //!< Bit mask for SIM_SCGC5_PORTE.
bogdanm 82:6473597d706e 2969 #define BS_SIM_SCGC5_PORTE (1U) //!< Bit field size in bits for SIM_SCGC5_PORTE.
bogdanm 82:6473597d706e 2970
bogdanm 82:6473597d706e 2971 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2972 //! @brief Read current value of the SIM_SCGC5_PORTE field.
bogdanm 82:6473597d706e 2973 #define BR_SIM_SCGC5_PORTE (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTE))
bogdanm 82:6473597d706e 2974 #endif
bogdanm 82:6473597d706e 2975
bogdanm 82:6473597d706e 2976 //! @brief Format value for bitfield SIM_SCGC5_PORTE.
bogdanm 82:6473597d706e 2977 #define BF_SIM_SCGC5_PORTE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC5_PORTE), uint32_t) & BM_SIM_SCGC5_PORTE)
bogdanm 82:6473597d706e 2978
bogdanm 82:6473597d706e 2979 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2980 //! @brief Set the PORTE field to a new value.
bogdanm 82:6473597d706e 2981 #define BW_SIM_SCGC5_PORTE(v) (BITBAND_ACCESS32(HW_SIM_SCGC5_ADDR, BP_SIM_SCGC5_PORTE) = (v))
bogdanm 82:6473597d706e 2982 #endif
bogdanm 82:6473597d706e 2983 //@}
bogdanm 82:6473597d706e 2984
bogdanm 82:6473597d706e 2985 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2986 // HW_SIM_SCGC6 - System Clock Gating Control Register 6
bogdanm 82:6473597d706e 2987 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2988
bogdanm 82:6473597d706e 2989 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2990 /*!
bogdanm 82:6473597d706e 2991 * @brief HW_SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
bogdanm 82:6473597d706e 2992 *
bogdanm 82:6473597d706e 2993 * Reset value: 0x40000001U
bogdanm 82:6473597d706e 2994 *
bogdanm 82:6473597d706e 2995 * DAC0, FTM2, and RNGA can be accessed through both AIPS0 and AIPS1. When
bogdanm 82:6473597d706e 2996 * accessing through AIPS1, define the clock gate control bits in the SCGC2 and SCGC3.
bogdanm 82:6473597d706e 2997 * When accessing through AIPS0, define the clock gate control bits in SCGC6.
bogdanm 82:6473597d706e 2998 */
bogdanm 82:6473597d706e 2999 typedef union _hw_sim_scgc6
bogdanm 82:6473597d706e 3000 {
bogdanm 82:6473597d706e 3001 uint32_t U;
bogdanm 82:6473597d706e 3002 struct _hw_sim_scgc6_bitfields
bogdanm 82:6473597d706e 3003 {
bogdanm 82:6473597d706e 3004 uint32_t FTF : 1; //!< [0] Flash Memory Clock Gate Control
bogdanm 82:6473597d706e 3005 uint32_t DMAMUXb : 1; //!< [1] DMA Mux Clock Gate Control
bogdanm 82:6473597d706e 3006 uint32_t RESERVED0 : 2; //!< [3:2]
bogdanm 82:6473597d706e 3007 uint32_t FLEXCAN0 : 1; //!< [4] FlexCAN0 Clock Gate Control
bogdanm 82:6473597d706e 3008 uint32_t RESERVED1 : 4; //!< [8:5]
bogdanm 82:6473597d706e 3009 uint32_t RNGA : 1; //!< [9] RNGA Clock Gate Control
bogdanm 82:6473597d706e 3010 uint32_t RESERVED2 : 2; //!< [11:10]
bogdanm 82:6473597d706e 3011 uint32_t SPI0b : 1; //!< [12] SPI0 Clock Gate Control
bogdanm 82:6473597d706e 3012 uint32_t SPI1b : 1; //!< [13] SPI1 Clock Gate Control
bogdanm 82:6473597d706e 3013 uint32_t RESERVED3 : 1; //!< [14]
bogdanm 82:6473597d706e 3014 uint32_t I2S : 1; //!< [15] I2S Clock Gate Control
bogdanm 82:6473597d706e 3015 uint32_t RESERVED4 : 2; //!< [17:16]
bogdanm 82:6473597d706e 3016 uint32_t CRCb : 1; //!< [18] CRC Clock Gate Control
bogdanm 82:6473597d706e 3017 uint32_t RESERVED5 : 2; //!< [20:19]
bogdanm 82:6473597d706e 3018 uint32_t USBDCDb : 1; //!< [21] USB DCD Clock Gate Control
bogdanm 82:6473597d706e 3019 uint32_t PDB : 1; //!< [22] PDB Clock Gate Control
bogdanm 82:6473597d706e 3020 uint32_t PITb : 1; //!< [23] PIT Clock Gate Control
bogdanm 82:6473597d706e 3021 uint32_t FTM0b : 1; //!< [24] FTM0 Clock Gate Control
bogdanm 82:6473597d706e 3022 uint32_t FTM1b : 1; //!< [25] FTM1 Clock Gate Control
bogdanm 82:6473597d706e 3023 uint32_t FTM2b : 1; //!< [26] FTM2 Clock Gate Control
bogdanm 82:6473597d706e 3024 uint32_t ADC0b : 1; //!< [27] ADC0 Clock Gate Control
bogdanm 82:6473597d706e 3025 uint32_t RESERVED6 : 1; //!< [28]
bogdanm 82:6473597d706e 3026 uint32_t RTCb : 1; //!< [29] RTC Access Control
bogdanm 82:6473597d706e 3027 uint32_t RESERVED7 : 1; //!< [30]
bogdanm 82:6473597d706e 3028 uint32_t DAC0b : 1; //!< [31] DAC0 Clock Gate Control
bogdanm 82:6473597d706e 3029 } B;
bogdanm 82:6473597d706e 3030 } hw_sim_scgc6_t;
bogdanm 82:6473597d706e 3031 #endif
bogdanm 82:6473597d706e 3032
bogdanm 82:6473597d706e 3033 /*!
bogdanm 82:6473597d706e 3034 * @name Constants and macros for entire SIM_SCGC6 register
bogdanm 82:6473597d706e 3035 */
bogdanm 82:6473597d706e 3036 //@{
bogdanm 82:6473597d706e 3037 #define HW_SIM_SCGC6_ADDR (REGS_SIM_BASE + 0x103CU)
bogdanm 82:6473597d706e 3038
bogdanm 82:6473597d706e 3039 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3040 #define HW_SIM_SCGC6 (*(__IO hw_sim_scgc6_t *) HW_SIM_SCGC6_ADDR)
bogdanm 82:6473597d706e 3041 #define HW_SIM_SCGC6_RD() (HW_SIM_SCGC6.U)
bogdanm 82:6473597d706e 3042 #define HW_SIM_SCGC6_WR(v) (HW_SIM_SCGC6.U = (v))
bogdanm 82:6473597d706e 3043 #define HW_SIM_SCGC6_SET(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() | (v)))
bogdanm 82:6473597d706e 3044 #define HW_SIM_SCGC6_CLR(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() & ~(v)))
bogdanm 82:6473597d706e 3045 #define HW_SIM_SCGC6_TOG(v) (HW_SIM_SCGC6_WR(HW_SIM_SCGC6_RD() ^ (v)))
bogdanm 82:6473597d706e 3046 #endif
bogdanm 82:6473597d706e 3047 //@}
bogdanm 82:6473597d706e 3048
bogdanm 82:6473597d706e 3049 /*
bogdanm 82:6473597d706e 3050 * Constants & macros for individual SIM_SCGC6 bitfields
bogdanm 82:6473597d706e 3051 */
bogdanm 82:6473597d706e 3052
bogdanm 82:6473597d706e 3053 /*!
bogdanm 82:6473597d706e 3054 * @name Register SIM_SCGC6, field FTF[0] (RW)
bogdanm 82:6473597d706e 3055 *
bogdanm 82:6473597d706e 3056 * This bit controls the clock gate to the flash memory. Flash reads are still
bogdanm 82:6473597d706e 3057 * supported while the flash memory is clock gated, but entry into low power modes
bogdanm 82:6473597d706e 3058 * is blocked.
bogdanm 82:6473597d706e 3059 *
bogdanm 82:6473597d706e 3060 * Values:
bogdanm 82:6473597d706e 3061 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3062 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3063 */
bogdanm 82:6473597d706e 3064 //@{
bogdanm 82:6473597d706e 3065 #define BP_SIM_SCGC6_FTF (0U) //!< Bit position for SIM_SCGC6_FTF.
bogdanm 82:6473597d706e 3066 #define BM_SIM_SCGC6_FTF (0x00000001U) //!< Bit mask for SIM_SCGC6_FTF.
bogdanm 82:6473597d706e 3067 #define BS_SIM_SCGC6_FTF (1U) //!< Bit field size in bits for SIM_SCGC6_FTF.
bogdanm 82:6473597d706e 3068
bogdanm 82:6473597d706e 3069 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3070 //! @brief Read current value of the SIM_SCGC6_FTF field.
bogdanm 82:6473597d706e 3071 #define BR_SIM_SCGC6_FTF (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTF))
bogdanm 82:6473597d706e 3072 #endif
bogdanm 82:6473597d706e 3073
bogdanm 82:6473597d706e 3074 //! @brief Format value for bitfield SIM_SCGC6_FTF.
bogdanm 82:6473597d706e 3075 #define BF_SIM_SCGC6_FTF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTF), uint32_t) & BM_SIM_SCGC6_FTF)
bogdanm 82:6473597d706e 3076
bogdanm 82:6473597d706e 3077 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3078 //! @brief Set the FTF field to a new value.
bogdanm 82:6473597d706e 3079 #define BW_SIM_SCGC6_FTF(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTF) = (v))
bogdanm 82:6473597d706e 3080 #endif
bogdanm 82:6473597d706e 3081 //@}
bogdanm 82:6473597d706e 3082
bogdanm 82:6473597d706e 3083 /*!
bogdanm 82:6473597d706e 3084 * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
bogdanm 82:6473597d706e 3085 *
bogdanm 82:6473597d706e 3086 * This bit controls the clock gate to the DMA Mux module.
bogdanm 82:6473597d706e 3087 *
bogdanm 82:6473597d706e 3088 * Values:
bogdanm 82:6473597d706e 3089 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3090 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3091 */
bogdanm 82:6473597d706e 3092 //@{
bogdanm 82:6473597d706e 3093 #define BP_SIM_SCGC6_DMAMUX (1U) //!< Bit position for SIM_SCGC6_DMAMUX.
bogdanm 82:6473597d706e 3094 #define BM_SIM_SCGC6_DMAMUX (0x00000002U) //!< Bit mask for SIM_SCGC6_DMAMUX.
bogdanm 82:6473597d706e 3095 #define BS_SIM_SCGC6_DMAMUX (1U) //!< Bit field size in bits for SIM_SCGC6_DMAMUX.
bogdanm 82:6473597d706e 3096
bogdanm 82:6473597d706e 3097 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3098 //! @brief Read current value of the SIM_SCGC6_DMAMUX field.
bogdanm 82:6473597d706e 3099 #define BR_SIM_SCGC6_DMAMUX (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DMAMUX))
bogdanm 82:6473597d706e 3100 #endif
bogdanm 82:6473597d706e 3101
bogdanm 82:6473597d706e 3102 //! @brief Format value for bitfield SIM_SCGC6_DMAMUX.
bogdanm 82:6473597d706e 3103 #define BF_SIM_SCGC6_DMAMUX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_DMAMUX), uint32_t) & BM_SIM_SCGC6_DMAMUX)
bogdanm 82:6473597d706e 3104
bogdanm 82:6473597d706e 3105 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3106 //! @brief Set the DMAMUX field to a new value.
bogdanm 82:6473597d706e 3107 #define BW_SIM_SCGC6_DMAMUX(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DMAMUX) = (v))
bogdanm 82:6473597d706e 3108 #endif
bogdanm 82:6473597d706e 3109 //@}
bogdanm 82:6473597d706e 3110
bogdanm 82:6473597d706e 3111 /*!
bogdanm 82:6473597d706e 3112 * @name Register SIM_SCGC6, field FLEXCAN0[4] (RW)
bogdanm 82:6473597d706e 3113 *
bogdanm 82:6473597d706e 3114 * This bit controls the clock gate to the FlexCAN0 module.
bogdanm 82:6473597d706e 3115 *
bogdanm 82:6473597d706e 3116 * Values:
bogdanm 82:6473597d706e 3117 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3118 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3119 */
bogdanm 82:6473597d706e 3120 //@{
bogdanm 82:6473597d706e 3121 #define BP_SIM_SCGC6_FLEXCAN0 (4U) //!< Bit position for SIM_SCGC6_FLEXCAN0.
bogdanm 82:6473597d706e 3122 #define BM_SIM_SCGC6_FLEXCAN0 (0x00000010U) //!< Bit mask for SIM_SCGC6_FLEXCAN0.
bogdanm 82:6473597d706e 3123 #define BS_SIM_SCGC6_FLEXCAN0 (1U) //!< Bit field size in bits for SIM_SCGC6_FLEXCAN0.
bogdanm 82:6473597d706e 3124
bogdanm 82:6473597d706e 3125 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3126 //! @brief Read current value of the SIM_SCGC6_FLEXCAN0 field.
bogdanm 82:6473597d706e 3127 #define BR_SIM_SCGC6_FLEXCAN0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FLEXCAN0))
bogdanm 82:6473597d706e 3128 #endif
bogdanm 82:6473597d706e 3129
bogdanm 82:6473597d706e 3130 //! @brief Format value for bitfield SIM_SCGC6_FLEXCAN0.
bogdanm 82:6473597d706e 3131 #define BF_SIM_SCGC6_FLEXCAN0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FLEXCAN0), uint32_t) & BM_SIM_SCGC6_FLEXCAN0)
bogdanm 82:6473597d706e 3132
bogdanm 82:6473597d706e 3133 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3134 //! @brief Set the FLEXCAN0 field to a new value.
bogdanm 82:6473597d706e 3135 #define BW_SIM_SCGC6_FLEXCAN0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FLEXCAN0) = (v))
bogdanm 82:6473597d706e 3136 #endif
bogdanm 82:6473597d706e 3137 //@}
bogdanm 82:6473597d706e 3138
bogdanm 82:6473597d706e 3139 /*!
bogdanm 82:6473597d706e 3140 * @name Register SIM_SCGC6, field RNGA[9] (RW)
bogdanm 82:6473597d706e 3141 *
bogdanm 82:6473597d706e 3142 * This bit controls the clock gate to the RNGA module.
bogdanm 82:6473597d706e 3143 */
bogdanm 82:6473597d706e 3144 //@{
bogdanm 82:6473597d706e 3145 #define BP_SIM_SCGC6_RNGA (9U) //!< Bit position for SIM_SCGC6_RNGA.
bogdanm 82:6473597d706e 3146 #define BM_SIM_SCGC6_RNGA (0x00000200U) //!< Bit mask for SIM_SCGC6_RNGA.
bogdanm 82:6473597d706e 3147 #define BS_SIM_SCGC6_RNGA (1U) //!< Bit field size in bits for SIM_SCGC6_RNGA.
bogdanm 82:6473597d706e 3148
bogdanm 82:6473597d706e 3149 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3150 //! @brief Read current value of the SIM_SCGC6_RNGA field.
bogdanm 82:6473597d706e 3151 #define BR_SIM_SCGC6_RNGA (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RNGA))
bogdanm 82:6473597d706e 3152 #endif
bogdanm 82:6473597d706e 3153
bogdanm 82:6473597d706e 3154 //! @brief Format value for bitfield SIM_SCGC6_RNGA.
bogdanm 82:6473597d706e 3155 #define BF_SIM_SCGC6_RNGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_RNGA), uint32_t) & BM_SIM_SCGC6_RNGA)
bogdanm 82:6473597d706e 3156
bogdanm 82:6473597d706e 3157 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3158 //! @brief Set the RNGA field to a new value.
bogdanm 82:6473597d706e 3159 #define BW_SIM_SCGC6_RNGA(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RNGA) = (v))
bogdanm 82:6473597d706e 3160 #endif
bogdanm 82:6473597d706e 3161 //@}
bogdanm 82:6473597d706e 3162
bogdanm 82:6473597d706e 3163 /*!
bogdanm 82:6473597d706e 3164 * @name Register SIM_SCGC6, field SPI0[12] (RW)
bogdanm 82:6473597d706e 3165 *
bogdanm 82:6473597d706e 3166 * This bit controls the clock gate to the SPI0 module.
bogdanm 82:6473597d706e 3167 *
bogdanm 82:6473597d706e 3168 * Values:
bogdanm 82:6473597d706e 3169 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3170 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3171 */
bogdanm 82:6473597d706e 3172 //@{
bogdanm 82:6473597d706e 3173 #define BP_SIM_SCGC6_SPI0 (12U) //!< Bit position for SIM_SCGC6_SPI0.
bogdanm 82:6473597d706e 3174 #define BM_SIM_SCGC6_SPI0 (0x00001000U) //!< Bit mask for SIM_SCGC6_SPI0.
bogdanm 82:6473597d706e 3175 #define BS_SIM_SCGC6_SPI0 (1U) //!< Bit field size in bits for SIM_SCGC6_SPI0.
bogdanm 82:6473597d706e 3176
bogdanm 82:6473597d706e 3177 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3178 //! @brief Read current value of the SIM_SCGC6_SPI0 field.
bogdanm 82:6473597d706e 3179 #define BR_SIM_SCGC6_SPI0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI0))
bogdanm 82:6473597d706e 3180 #endif
bogdanm 82:6473597d706e 3181
bogdanm 82:6473597d706e 3182 //! @brief Format value for bitfield SIM_SCGC6_SPI0.
bogdanm 82:6473597d706e 3183 #define BF_SIM_SCGC6_SPI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_SPI0), uint32_t) & BM_SIM_SCGC6_SPI0)
bogdanm 82:6473597d706e 3184
bogdanm 82:6473597d706e 3185 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3186 //! @brief Set the SPI0 field to a new value.
bogdanm 82:6473597d706e 3187 #define BW_SIM_SCGC6_SPI0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI0) = (v))
bogdanm 82:6473597d706e 3188 #endif
bogdanm 82:6473597d706e 3189 //@}
bogdanm 82:6473597d706e 3190
bogdanm 82:6473597d706e 3191 /*!
bogdanm 82:6473597d706e 3192 * @name Register SIM_SCGC6, field SPI1[13] (RW)
bogdanm 82:6473597d706e 3193 *
bogdanm 82:6473597d706e 3194 * This bit controls the clock gate to the SPI1 module.
bogdanm 82:6473597d706e 3195 *
bogdanm 82:6473597d706e 3196 * Values:
bogdanm 82:6473597d706e 3197 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3198 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3199 */
bogdanm 82:6473597d706e 3200 //@{
bogdanm 82:6473597d706e 3201 #define BP_SIM_SCGC6_SPI1 (13U) //!< Bit position for SIM_SCGC6_SPI1.
bogdanm 82:6473597d706e 3202 #define BM_SIM_SCGC6_SPI1 (0x00002000U) //!< Bit mask for SIM_SCGC6_SPI1.
bogdanm 82:6473597d706e 3203 #define BS_SIM_SCGC6_SPI1 (1U) //!< Bit field size in bits for SIM_SCGC6_SPI1.
bogdanm 82:6473597d706e 3204
bogdanm 82:6473597d706e 3205 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3206 //! @brief Read current value of the SIM_SCGC6_SPI1 field.
bogdanm 82:6473597d706e 3207 #define BR_SIM_SCGC6_SPI1 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI1))
bogdanm 82:6473597d706e 3208 #endif
bogdanm 82:6473597d706e 3209
bogdanm 82:6473597d706e 3210 //! @brief Format value for bitfield SIM_SCGC6_SPI1.
bogdanm 82:6473597d706e 3211 #define BF_SIM_SCGC6_SPI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_SPI1), uint32_t) & BM_SIM_SCGC6_SPI1)
bogdanm 82:6473597d706e 3212
bogdanm 82:6473597d706e 3213 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3214 //! @brief Set the SPI1 field to a new value.
bogdanm 82:6473597d706e 3215 #define BW_SIM_SCGC6_SPI1(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_SPI1) = (v))
bogdanm 82:6473597d706e 3216 #endif
bogdanm 82:6473597d706e 3217 //@}
bogdanm 82:6473597d706e 3218
bogdanm 82:6473597d706e 3219 /*!
bogdanm 82:6473597d706e 3220 * @name Register SIM_SCGC6, field I2S[15] (RW)
bogdanm 82:6473597d706e 3221 *
bogdanm 82:6473597d706e 3222 * This bit controls the clock gate to the I 2 S module.
bogdanm 82:6473597d706e 3223 *
bogdanm 82:6473597d706e 3224 * Values:
bogdanm 82:6473597d706e 3225 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3226 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3227 */
bogdanm 82:6473597d706e 3228 //@{
bogdanm 82:6473597d706e 3229 #define BP_SIM_SCGC6_I2S (15U) //!< Bit position for SIM_SCGC6_I2S.
bogdanm 82:6473597d706e 3230 #define BM_SIM_SCGC6_I2S (0x00008000U) //!< Bit mask for SIM_SCGC6_I2S.
bogdanm 82:6473597d706e 3231 #define BS_SIM_SCGC6_I2S (1U) //!< Bit field size in bits for SIM_SCGC6_I2S.
bogdanm 82:6473597d706e 3232
bogdanm 82:6473597d706e 3233 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3234 //! @brief Read current value of the SIM_SCGC6_I2S field.
bogdanm 82:6473597d706e 3235 #define BR_SIM_SCGC6_I2S (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_I2S))
bogdanm 82:6473597d706e 3236 #endif
bogdanm 82:6473597d706e 3237
bogdanm 82:6473597d706e 3238 //! @brief Format value for bitfield SIM_SCGC6_I2S.
bogdanm 82:6473597d706e 3239 #define BF_SIM_SCGC6_I2S(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_I2S), uint32_t) & BM_SIM_SCGC6_I2S)
bogdanm 82:6473597d706e 3240
bogdanm 82:6473597d706e 3241 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3242 //! @brief Set the I2S field to a new value.
bogdanm 82:6473597d706e 3243 #define BW_SIM_SCGC6_I2S(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_I2S) = (v))
bogdanm 82:6473597d706e 3244 #endif
bogdanm 82:6473597d706e 3245 //@}
bogdanm 82:6473597d706e 3246
bogdanm 82:6473597d706e 3247 /*!
bogdanm 82:6473597d706e 3248 * @name Register SIM_SCGC6, field CRC[18] (RW)
bogdanm 82:6473597d706e 3249 *
bogdanm 82:6473597d706e 3250 * This bit controls the clock gate to the CRC module.
bogdanm 82:6473597d706e 3251 *
bogdanm 82:6473597d706e 3252 * Values:
bogdanm 82:6473597d706e 3253 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3254 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3255 */
bogdanm 82:6473597d706e 3256 //@{
bogdanm 82:6473597d706e 3257 #define BP_SIM_SCGC6_CRC (18U) //!< Bit position for SIM_SCGC6_CRC.
bogdanm 82:6473597d706e 3258 #define BM_SIM_SCGC6_CRC (0x00040000U) //!< Bit mask for SIM_SCGC6_CRC.
bogdanm 82:6473597d706e 3259 #define BS_SIM_SCGC6_CRC (1U) //!< Bit field size in bits for SIM_SCGC6_CRC.
bogdanm 82:6473597d706e 3260
bogdanm 82:6473597d706e 3261 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3262 //! @brief Read current value of the SIM_SCGC6_CRC field.
bogdanm 82:6473597d706e 3263 #define BR_SIM_SCGC6_CRC (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_CRC))
bogdanm 82:6473597d706e 3264 #endif
bogdanm 82:6473597d706e 3265
bogdanm 82:6473597d706e 3266 //! @brief Format value for bitfield SIM_SCGC6_CRC.
bogdanm 82:6473597d706e 3267 #define BF_SIM_SCGC6_CRC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_CRC), uint32_t) & BM_SIM_SCGC6_CRC)
bogdanm 82:6473597d706e 3268
bogdanm 82:6473597d706e 3269 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3270 //! @brief Set the CRC field to a new value.
bogdanm 82:6473597d706e 3271 #define BW_SIM_SCGC6_CRC(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_CRC) = (v))
bogdanm 82:6473597d706e 3272 #endif
bogdanm 82:6473597d706e 3273 //@}
bogdanm 82:6473597d706e 3274
bogdanm 82:6473597d706e 3275 /*!
bogdanm 82:6473597d706e 3276 * @name Register SIM_SCGC6, field USBDCD[21] (RW)
bogdanm 82:6473597d706e 3277 *
bogdanm 82:6473597d706e 3278 * This bit controls the clock gate to the USB DCD module.
bogdanm 82:6473597d706e 3279 *
bogdanm 82:6473597d706e 3280 * Values:
bogdanm 82:6473597d706e 3281 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3282 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3283 */
bogdanm 82:6473597d706e 3284 //@{
bogdanm 82:6473597d706e 3285 #define BP_SIM_SCGC6_USBDCD (21U) //!< Bit position for SIM_SCGC6_USBDCD.
bogdanm 82:6473597d706e 3286 #define BM_SIM_SCGC6_USBDCD (0x00200000U) //!< Bit mask for SIM_SCGC6_USBDCD.
bogdanm 82:6473597d706e 3287 #define BS_SIM_SCGC6_USBDCD (1U) //!< Bit field size in bits for SIM_SCGC6_USBDCD.
bogdanm 82:6473597d706e 3288
bogdanm 82:6473597d706e 3289 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3290 //! @brief Read current value of the SIM_SCGC6_USBDCD field.
bogdanm 82:6473597d706e 3291 #define BR_SIM_SCGC6_USBDCD (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_USBDCD))
bogdanm 82:6473597d706e 3292 #endif
bogdanm 82:6473597d706e 3293
bogdanm 82:6473597d706e 3294 //! @brief Format value for bitfield SIM_SCGC6_USBDCD.
bogdanm 82:6473597d706e 3295 #define BF_SIM_SCGC6_USBDCD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_USBDCD), uint32_t) & BM_SIM_SCGC6_USBDCD)
bogdanm 82:6473597d706e 3296
bogdanm 82:6473597d706e 3297 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3298 //! @brief Set the USBDCD field to a new value.
bogdanm 82:6473597d706e 3299 #define BW_SIM_SCGC6_USBDCD(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_USBDCD) = (v))
bogdanm 82:6473597d706e 3300 #endif
bogdanm 82:6473597d706e 3301 //@}
bogdanm 82:6473597d706e 3302
bogdanm 82:6473597d706e 3303 /*!
bogdanm 82:6473597d706e 3304 * @name Register SIM_SCGC6, field PDB[22] (RW)
bogdanm 82:6473597d706e 3305 *
bogdanm 82:6473597d706e 3306 * This bit controls the clock gate to the PDB module.
bogdanm 82:6473597d706e 3307 *
bogdanm 82:6473597d706e 3308 * Values:
bogdanm 82:6473597d706e 3309 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3310 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3311 */
bogdanm 82:6473597d706e 3312 //@{
bogdanm 82:6473597d706e 3313 #define BP_SIM_SCGC6_PDB (22U) //!< Bit position for SIM_SCGC6_PDB.
bogdanm 82:6473597d706e 3314 #define BM_SIM_SCGC6_PDB (0x00400000U) //!< Bit mask for SIM_SCGC6_PDB.
bogdanm 82:6473597d706e 3315 #define BS_SIM_SCGC6_PDB (1U) //!< Bit field size in bits for SIM_SCGC6_PDB.
bogdanm 82:6473597d706e 3316
bogdanm 82:6473597d706e 3317 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3318 //! @brief Read current value of the SIM_SCGC6_PDB field.
bogdanm 82:6473597d706e 3319 #define BR_SIM_SCGC6_PDB (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PDB))
bogdanm 82:6473597d706e 3320 #endif
bogdanm 82:6473597d706e 3321
bogdanm 82:6473597d706e 3322 //! @brief Format value for bitfield SIM_SCGC6_PDB.
bogdanm 82:6473597d706e 3323 #define BF_SIM_SCGC6_PDB(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_PDB), uint32_t) & BM_SIM_SCGC6_PDB)
bogdanm 82:6473597d706e 3324
bogdanm 82:6473597d706e 3325 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3326 //! @brief Set the PDB field to a new value.
bogdanm 82:6473597d706e 3327 #define BW_SIM_SCGC6_PDB(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PDB) = (v))
bogdanm 82:6473597d706e 3328 #endif
bogdanm 82:6473597d706e 3329 //@}
bogdanm 82:6473597d706e 3330
bogdanm 82:6473597d706e 3331 /*!
bogdanm 82:6473597d706e 3332 * @name Register SIM_SCGC6, field PIT[23] (RW)
bogdanm 82:6473597d706e 3333 *
bogdanm 82:6473597d706e 3334 * This bit controls the clock gate to the PIT module.
bogdanm 82:6473597d706e 3335 *
bogdanm 82:6473597d706e 3336 * Values:
bogdanm 82:6473597d706e 3337 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3338 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3339 */
bogdanm 82:6473597d706e 3340 //@{
bogdanm 82:6473597d706e 3341 #define BP_SIM_SCGC6_PIT (23U) //!< Bit position for SIM_SCGC6_PIT.
bogdanm 82:6473597d706e 3342 #define BM_SIM_SCGC6_PIT (0x00800000U) //!< Bit mask for SIM_SCGC6_PIT.
bogdanm 82:6473597d706e 3343 #define BS_SIM_SCGC6_PIT (1U) //!< Bit field size in bits for SIM_SCGC6_PIT.
bogdanm 82:6473597d706e 3344
bogdanm 82:6473597d706e 3345 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3346 //! @brief Read current value of the SIM_SCGC6_PIT field.
bogdanm 82:6473597d706e 3347 #define BR_SIM_SCGC6_PIT (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PIT))
bogdanm 82:6473597d706e 3348 #endif
bogdanm 82:6473597d706e 3349
bogdanm 82:6473597d706e 3350 //! @brief Format value for bitfield SIM_SCGC6_PIT.
bogdanm 82:6473597d706e 3351 #define BF_SIM_SCGC6_PIT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_PIT), uint32_t) & BM_SIM_SCGC6_PIT)
bogdanm 82:6473597d706e 3352
bogdanm 82:6473597d706e 3353 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3354 //! @brief Set the PIT field to a new value.
bogdanm 82:6473597d706e 3355 #define BW_SIM_SCGC6_PIT(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_PIT) = (v))
bogdanm 82:6473597d706e 3356 #endif
bogdanm 82:6473597d706e 3357 //@}
bogdanm 82:6473597d706e 3358
bogdanm 82:6473597d706e 3359 /*!
bogdanm 82:6473597d706e 3360 * @name Register SIM_SCGC6, field FTM0[24] (RW)
bogdanm 82:6473597d706e 3361 *
bogdanm 82:6473597d706e 3362 * This bit controls the clock gate to the FTM0 module.
bogdanm 82:6473597d706e 3363 *
bogdanm 82:6473597d706e 3364 * Values:
bogdanm 82:6473597d706e 3365 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3366 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3367 */
bogdanm 82:6473597d706e 3368 //@{
bogdanm 82:6473597d706e 3369 #define BP_SIM_SCGC6_FTM0 (24U) //!< Bit position for SIM_SCGC6_FTM0.
bogdanm 82:6473597d706e 3370 #define BM_SIM_SCGC6_FTM0 (0x01000000U) //!< Bit mask for SIM_SCGC6_FTM0.
bogdanm 82:6473597d706e 3371 #define BS_SIM_SCGC6_FTM0 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM0.
bogdanm 82:6473597d706e 3372
bogdanm 82:6473597d706e 3373 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3374 //! @brief Read current value of the SIM_SCGC6_FTM0 field.
bogdanm 82:6473597d706e 3375 #define BR_SIM_SCGC6_FTM0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM0))
bogdanm 82:6473597d706e 3376 #endif
bogdanm 82:6473597d706e 3377
bogdanm 82:6473597d706e 3378 //! @brief Format value for bitfield SIM_SCGC6_FTM0.
bogdanm 82:6473597d706e 3379 #define BF_SIM_SCGC6_FTM0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM0), uint32_t) & BM_SIM_SCGC6_FTM0)
bogdanm 82:6473597d706e 3380
bogdanm 82:6473597d706e 3381 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3382 //! @brief Set the FTM0 field to a new value.
bogdanm 82:6473597d706e 3383 #define BW_SIM_SCGC6_FTM0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM0) = (v))
bogdanm 82:6473597d706e 3384 #endif
bogdanm 82:6473597d706e 3385 //@}
bogdanm 82:6473597d706e 3386
bogdanm 82:6473597d706e 3387 /*!
bogdanm 82:6473597d706e 3388 * @name Register SIM_SCGC6, field FTM1[25] (RW)
bogdanm 82:6473597d706e 3389 *
bogdanm 82:6473597d706e 3390 * This bit controls the clock gate to the FTM1 module.
bogdanm 82:6473597d706e 3391 *
bogdanm 82:6473597d706e 3392 * Values:
bogdanm 82:6473597d706e 3393 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3394 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3395 */
bogdanm 82:6473597d706e 3396 //@{
bogdanm 82:6473597d706e 3397 #define BP_SIM_SCGC6_FTM1 (25U) //!< Bit position for SIM_SCGC6_FTM1.
bogdanm 82:6473597d706e 3398 #define BM_SIM_SCGC6_FTM1 (0x02000000U) //!< Bit mask for SIM_SCGC6_FTM1.
bogdanm 82:6473597d706e 3399 #define BS_SIM_SCGC6_FTM1 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM1.
bogdanm 82:6473597d706e 3400
bogdanm 82:6473597d706e 3401 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3402 //! @brief Read current value of the SIM_SCGC6_FTM1 field.
bogdanm 82:6473597d706e 3403 #define BR_SIM_SCGC6_FTM1 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM1))
bogdanm 82:6473597d706e 3404 #endif
bogdanm 82:6473597d706e 3405
bogdanm 82:6473597d706e 3406 //! @brief Format value for bitfield SIM_SCGC6_FTM1.
bogdanm 82:6473597d706e 3407 #define BF_SIM_SCGC6_FTM1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM1), uint32_t) & BM_SIM_SCGC6_FTM1)
bogdanm 82:6473597d706e 3408
bogdanm 82:6473597d706e 3409 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3410 //! @brief Set the FTM1 field to a new value.
bogdanm 82:6473597d706e 3411 #define BW_SIM_SCGC6_FTM1(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM1) = (v))
bogdanm 82:6473597d706e 3412 #endif
bogdanm 82:6473597d706e 3413 //@}
bogdanm 82:6473597d706e 3414
bogdanm 82:6473597d706e 3415 /*!
bogdanm 82:6473597d706e 3416 * @name Register SIM_SCGC6, field FTM2[26] (RW)
bogdanm 82:6473597d706e 3417 *
bogdanm 82:6473597d706e 3418 * This bit controls the clock gate to the FTM2 module.
bogdanm 82:6473597d706e 3419 *
bogdanm 82:6473597d706e 3420 * Values:
bogdanm 82:6473597d706e 3421 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3422 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3423 */
bogdanm 82:6473597d706e 3424 //@{
bogdanm 82:6473597d706e 3425 #define BP_SIM_SCGC6_FTM2 (26U) //!< Bit position for SIM_SCGC6_FTM2.
bogdanm 82:6473597d706e 3426 #define BM_SIM_SCGC6_FTM2 (0x04000000U) //!< Bit mask for SIM_SCGC6_FTM2.
bogdanm 82:6473597d706e 3427 #define BS_SIM_SCGC6_FTM2 (1U) //!< Bit field size in bits for SIM_SCGC6_FTM2.
bogdanm 82:6473597d706e 3428
bogdanm 82:6473597d706e 3429 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3430 //! @brief Read current value of the SIM_SCGC6_FTM2 field.
bogdanm 82:6473597d706e 3431 #define BR_SIM_SCGC6_FTM2 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM2))
bogdanm 82:6473597d706e 3432 #endif
bogdanm 82:6473597d706e 3433
bogdanm 82:6473597d706e 3434 //! @brief Format value for bitfield SIM_SCGC6_FTM2.
bogdanm 82:6473597d706e 3435 #define BF_SIM_SCGC6_FTM2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_FTM2), uint32_t) & BM_SIM_SCGC6_FTM2)
bogdanm 82:6473597d706e 3436
bogdanm 82:6473597d706e 3437 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3438 //! @brief Set the FTM2 field to a new value.
bogdanm 82:6473597d706e 3439 #define BW_SIM_SCGC6_FTM2(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_FTM2) = (v))
bogdanm 82:6473597d706e 3440 #endif
bogdanm 82:6473597d706e 3441 //@}
bogdanm 82:6473597d706e 3442
bogdanm 82:6473597d706e 3443 /*!
bogdanm 82:6473597d706e 3444 * @name Register SIM_SCGC6, field ADC0[27] (RW)
bogdanm 82:6473597d706e 3445 *
bogdanm 82:6473597d706e 3446 * This bit controls the clock gate to the ADC0 module.
bogdanm 82:6473597d706e 3447 *
bogdanm 82:6473597d706e 3448 * Values:
bogdanm 82:6473597d706e 3449 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3450 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3451 */
bogdanm 82:6473597d706e 3452 //@{
bogdanm 82:6473597d706e 3453 #define BP_SIM_SCGC6_ADC0 (27U) //!< Bit position for SIM_SCGC6_ADC0.
bogdanm 82:6473597d706e 3454 #define BM_SIM_SCGC6_ADC0 (0x08000000U) //!< Bit mask for SIM_SCGC6_ADC0.
bogdanm 82:6473597d706e 3455 #define BS_SIM_SCGC6_ADC0 (1U) //!< Bit field size in bits for SIM_SCGC6_ADC0.
bogdanm 82:6473597d706e 3456
bogdanm 82:6473597d706e 3457 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3458 //! @brief Read current value of the SIM_SCGC6_ADC0 field.
bogdanm 82:6473597d706e 3459 #define BR_SIM_SCGC6_ADC0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_ADC0))
bogdanm 82:6473597d706e 3460 #endif
bogdanm 82:6473597d706e 3461
bogdanm 82:6473597d706e 3462 //! @brief Format value for bitfield SIM_SCGC6_ADC0.
bogdanm 82:6473597d706e 3463 #define BF_SIM_SCGC6_ADC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_ADC0), uint32_t) & BM_SIM_SCGC6_ADC0)
bogdanm 82:6473597d706e 3464
bogdanm 82:6473597d706e 3465 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3466 //! @brief Set the ADC0 field to a new value.
bogdanm 82:6473597d706e 3467 #define BW_SIM_SCGC6_ADC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_ADC0) = (v))
bogdanm 82:6473597d706e 3468 #endif
bogdanm 82:6473597d706e 3469 //@}
bogdanm 82:6473597d706e 3470
bogdanm 82:6473597d706e 3471 /*!
bogdanm 82:6473597d706e 3472 * @name Register SIM_SCGC6, field RTC[29] (RW)
bogdanm 82:6473597d706e 3473 *
bogdanm 82:6473597d706e 3474 * This bit controls software access and interrupts to the RTC module.
bogdanm 82:6473597d706e 3475 *
bogdanm 82:6473597d706e 3476 * Values:
bogdanm 82:6473597d706e 3477 * - 0 - Access and interrupts disabled
bogdanm 82:6473597d706e 3478 * - 1 - Access and interrupts enabled
bogdanm 82:6473597d706e 3479 */
bogdanm 82:6473597d706e 3480 //@{
bogdanm 82:6473597d706e 3481 #define BP_SIM_SCGC6_RTC (29U) //!< Bit position for SIM_SCGC6_RTC.
bogdanm 82:6473597d706e 3482 #define BM_SIM_SCGC6_RTC (0x20000000U) //!< Bit mask for SIM_SCGC6_RTC.
bogdanm 82:6473597d706e 3483 #define BS_SIM_SCGC6_RTC (1U) //!< Bit field size in bits for SIM_SCGC6_RTC.
bogdanm 82:6473597d706e 3484
bogdanm 82:6473597d706e 3485 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3486 //! @brief Read current value of the SIM_SCGC6_RTC field.
bogdanm 82:6473597d706e 3487 #define BR_SIM_SCGC6_RTC (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RTC))
bogdanm 82:6473597d706e 3488 #endif
bogdanm 82:6473597d706e 3489
bogdanm 82:6473597d706e 3490 //! @brief Format value for bitfield SIM_SCGC6_RTC.
bogdanm 82:6473597d706e 3491 #define BF_SIM_SCGC6_RTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_RTC), uint32_t) & BM_SIM_SCGC6_RTC)
bogdanm 82:6473597d706e 3492
bogdanm 82:6473597d706e 3493 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3494 //! @brief Set the RTC field to a new value.
bogdanm 82:6473597d706e 3495 #define BW_SIM_SCGC6_RTC(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_RTC) = (v))
bogdanm 82:6473597d706e 3496 #endif
bogdanm 82:6473597d706e 3497 //@}
bogdanm 82:6473597d706e 3498
bogdanm 82:6473597d706e 3499 /*!
bogdanm 82:6473597d706e 3500 * @name Register SIM_SCGC6, field DAC0[31] (RW)
bogdanm 82:6473597d706e 3501 *
bogdanm 82:6473597d706e 3502 * This bit controls the clock gate to the DAC0 module.
bogdanm 82:6473597d706e 3503 *
bogdanm 82:6473597d706e 3504 * Values:
bogdanm 82:6473597d706e 3505 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3506 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3507 */
bogdanm 82:6473597d706e 3508 //@{
bogdanm 82:6473597d706e 3509 #define BP_SIM_SCGC6_DAC0 (31U) //!< Bit position for SIM_SCGC6_DAC0.
bogdanm 82:6473597d706e 3510 #define BM_SIM_SCGC6_DAC0 (0x80000000U) //!< Bit mask for SIM_SCGC6_DAC0.
bogdanm 82:6473597d706e 3511 #define BS_SIM_SCGC6_DAC0 (1U) //!< Bit field size in bits for SIM_SCGC6_DAC0.
bogdanm 82:6473597d706e 3512
bogdanm 82:6473597d706e 3513 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3514 //! @brief Read current value of the SIM_SCGC6_DAC0 field.
bogdanm 82:6473597d706e 3515 #define BR_SIM_SCGC6_DAC0 (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DAC0))
bogdanm 82:6473597d706e 3516 #endif
bogdanm 82:6473597d706e 3517
bogdanm 82:6473597d706e 3518 //! @brief Format value for bitfield SIM_SCGC6_DAC0.
bogdanm 82:6473597d706e 3519 #define BF_SIM_SCGC6_DAC0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC6_DAC0), uint32_t) & BM_SIM_SCGC6_DAC0)
bogdanm 82:6473597d706e 3520
bogdanm 82:6473597d706e 3521 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3522 //! @brief Set the DAC0 field to a new value.
bogdanm 82:6473597d706e 3523 #define BW_SIM_SCGC6_DAC0(v) (BITBAND_ACCESS32(HW_SIM_SCGC6_ADDR, BP_SIM_SCGC6_DAC0) = (v))
bogdanm 82:6473597d706e 3524 #endif
bogdanm 82:6473597d706e 3525 //@}
bogdanm 82:6473597d706e 3526
bogdanm 82:6473597d706e 3527 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3528 // HW_SIM_SCGC7 - System Clock Gating Control Register 7
bogdanm 82:6473597d706e 3529 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3530
bogdanm 82:6473597d706e 3531 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3532 /*!
bogdanm 82:6473597d706e 3533 * @brief HW_SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
bogdanm 82:6473597d706e 3534 *
bogdanm 82:6473597d706e 3535 * Reset value: 0x00000006U
bogdanm 82:6473597d706e 3536 */
bogdanm 82:6473597d706e 3537 typedef union _hw_sim_scgc7
bogdanm 82:6473597d706e 3538 {
bogdanm 82:6473597d706e 3539 uint32_t U;
bogdanm 82:6473597d706e 3540 struct _hw_sim_scgc7_bitfields
bogdanm 82:6473597d706e 3541 {
bogdanm 82:6473597d706e 3542 uint32_t FLEXBUS : 1; //!< [0] FlexBus Clock Gate Control
bogdanm 82:6473597d706e 3543 uint32_t DMAb : 1; //!< [1] DMA Clock Gate Control
bogdanm 82:6473597d706e 3544 uint32_t MPUb : 1; //!< [2] MPU Clock Gate Control
bogdanm 82:6473597d706e 3545 uint32_t RESERVED0 : 29; //!< [31:3]
bogdanm 82:6473597d706e 3546 } B;
bogdanm 82:6473597d706e 3547 } hw_sim_scgc7_t;
bogdanm 82:6473597d706e 3548 #endif
bogdanm 82:6473597d706e 3549
bogdanm 82:6473597d706e 3550 /*!
bogdanm 82:6473597d706e 3551 * @name Constants and macros for entire SIM_SCGC7 register
bogdanm 82:6473597d706e 3552 */
bogdanm 82:6473597d706e 3553 //@{
bogdanm 82:6473597d706e 3554 #define HW_SIM_SCGC7_ADDR (REGS_SIM_BASE + 0x1040U)
bogdanm 82:6473597d706e 3555
bogdanm 82:6473597d706e 3556 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3557 #define HW_SIM_SCGC7 (*(__IO hw_sim_scgc7_t *) HW_SIM_SCGC7_ADDR)
bogdanm 82:6473597d706e 3558 #define HW_SIM_SCGC7_RD() (HW_SIM_SCGC7.U)
bogdanm 82:6473597d706e 3559 #define HW_SIM_SCGC7_WR(v) (HW_SIM_SCGC7.U = (v))
bogdanm 82:6473597d706e 3560 #define HW_SIM_SCGC7_SET(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() | (v)))
bogdanm 82:6473597d706e 3561 #define HW_SIM_SCGC7_CLR(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() & ~(v)))
bogdanm 82:6473597d706e 3562 #define HW_SIM_SCGC7_TOG(v) (HW_SIM_SCGC7_WR(HW_SIM_SCGC7_RD() ^ (v)))
bogdanm 82:6473597d706e 3563 #endif
bogdanm 82:6473597d706e 3564 //@}
bogdanm 82:6473597d706e 3565
bogdanm 82:6473597d706e 3566 /*
bogdanm 82:6473597d706e 3567 * Constants & macros for individual SIM_SCGC7 bitfields
bogdanm 82:6473597d706e 3568 */
bogdanm 82:6473597d706e 3569
bogdanm 82:6473597d706e 3570 /*!
bogdanm 82:6473597d706e 3571 * @name Register SIM_SCGC7, field FLEXBUS[0] (RW)
bogdanm 82:6473597d706e 3572 *
bogdanm 82:6473597d706e 3573 * This bit controls the clock gate to the FlexBus module.
bogdanm 82:6473597d706e 3574 *
bogdanm 82:6473597d706e 3575 * Values:
bogdanm 82:6473597d706e 3576 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3577 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3578 */
bogdanm 82:6473597d706e 3579 //@{
bogdanm 82:6473597d706e 3580 #define BP_SIM_SCGC7_FLEXBUS (0U) //!< Bit position for SIM_SCGC7_FLEXBUS.
bogdanm 82:6473597d706e 3581 #define BM_SIM_SCGC7_FLEXBUS (0x00000001U) //!< Bit mask for SIM_SCGC7_FLEXBUS.
bogdanm 82:6473597d706e 3582 #define BS_SIM_SCGC7_FLEXBUS (1U) //!< Bit field size in bits for SIM_SCGC7_FLEXBUS.
bogdanm 82:6473597d706e 3583
bogdanm 82:6473597d706e 3584 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3585 //! @brief Read current value of the SIM_SCGC7_FLEXBUS field.
bogdanm 82:6473597d706e 3586 #define BR_SIM_SCGC7_FLEXBUS (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_FLEXBUS))
bogdanm 82:6473597d706e 3587 #endif
bogdanm 82:6473597d706e 3588
bogdanm 82:6473597d706e 3589 //! @brief Format value for bitfield SIM_SCGC7_FLEXBUS.
bogdanm 82:6473597d706e 3590 #define BF_SIM_SCGC7_FLEXBUS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_FLEXBUS), uint32_t) & BM_SIM_SCGC7_FLEXBUS)
bogdanm 82:6473597d706e 3591
bogdanm 82:6473597d706e 3592 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3593 //! @brief Set the FLEXBUS field to a new value.
bogdanm 82:6473597d706e 3594 #define BW_SIM_SCGC7_FLEXBUS(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_FLEXBUS) = (v))
bogdanm 82:6473597d706e 3595 #endif
bogdanm 82:6473597d706e 3596 //@}
bogdanm 82:6473597d706e 3597
bogdanm 82:6473597d706e 3598 /*!
bogdanm 82:6473597d706e 3599 * @name Register SIM_SCGC7, field DMA[1] (RW)
bogdanm 82:6473597d706e 3600 *
bogdanm 82:6473597d706e 3601 * This bit controls the clock gate to the DMA module.
bogdanm 82:6473597d706e 3602 *
bogdanm 82:6473597d706e 3603 * Values:
bogdanm 82:6473597d706e 3604 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3605 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3606 */
bogdanm 82:6473597d706e 3607 //@{
bogdanm 82:6473597d706e 3608 #define BP_SIM_SCGC7_DMA (1U) //!< Bit position for SIM_SCGC7_DMA.
bogdanm 82:6473597d706e 3609 #define BM_SIM_SCGC7_DMA (0x00000002U) //!< Bit mask for SIM_SCGC7_DMA.
bogdanm 82:6473597d706e 3610 #define BS_SIM_SCGC7_DMA (1U) //!< Bit field size in bits for SIM_SCGC7_DMA.
bogdanm 82:6473597d706e 3611
bogdanm 82:6473597d706e 3612 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3613 //! @brief Read current value of the SIM_SCGC7_DMA field.
bogdanm 82:6473597d706e 3614 #define BR_SIM_SCGC7_DMA (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_DMA))
bogdanm 82:6473597d706e 3615 #endif
bogdanm 82:6473597d706e 3616
bogdanm 82:6473597d706e 3617 //! @brief Format value for bitfield SIM_SCGC7_DMA.
bogdanm 82:6473597d706e 3618 #define BF_SIM_SCGC7_DMA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_DMA), uint32_t) & BM_SIM_SCGC7_DMA)
bogdanm 82:6473597d706e 3619
bogdanm 82:6473597d706e 3620 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3621 //! @brief Set the DMA field to a new value.
bogdanm 82:6473597d706e 3622 #define BW_SIM_SCGC7_DMA(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_DMA) = (v))
bogdanm 82:6473597d706e 3623 #endif
bogdanm 82:6473597d706e 3624 //@}
bogdanm 82:6473597d706e 3625
bogdanm 82:6473597d706e 3626 /*!
bogdanm 82:6473597d706e 3627 * @name Register SIM_SCGC7, field MPU[2] (RW)
bogdanm 82:6473597d706e 3628 *
bogdanm 82:6473597d706e 3629 * This bit controls the clock gate to the MPU module.
bogdanm 82:6473597d706e 3630 *
bogdanm 82:6473597d706e 3631 * Values:
bogdanm 82:6473597d706e 3632 * - 0 - Clock disabled
bogdanm 82:6473597d706e 3633 * - 1 - Clock enabled
bogdanm 82:6473597d706e 3634 */
bogdanm 82:6473597d706e 3635 //@{
bogdanm 82:6473597d706e 3636 #define BP_SIM_SCGC7_MPU (2U) //!< Bit position for SIM_SCGC7_MPU.
bogdanm 82:6473597d706e 3637 #define BM_SIM_SCGC7_MPU (0x00000004U) //!< Bit mask for SIM_SCGC7_MPU.
bogdanm 82:6473597d706e 3638 #define BS_SIM_SCGC7_MPU (1U) //!< Bit field size in bits for SIM_SCGC7_MPU.
bogdanm 82:6473597d706e 3639
bogdanm 82:6473597d706e 3640 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3641 //! @brief Read current value of the SIM_SCGC7_MPU field.
bogdanm 82:6473597d706e 3642 #define BR_SIM_SCGC7_MPU (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_MPU))
bogdanm 82:6473597d706e 3643 #endif
bogdanm 82:6473597d706e 3644
bogdanm 82:6473597d706e 3645 //! @brief Format value for bitfield SIM_SCGC7_MPU.
bogdanm 82:6473597d706e 3646 #define BF_SIM_SCGC7_MPU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_SCGC7_MPU), uint32_t) & BM_SIM_SCGC7_MPU)
bogdanm 82:6473597d706e 3647
bogdanm 82:6473597d706e 3648 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3649 //! @brief Set the MPU field to a new value.
bogdanm 82:6473597d706e 3650 #define BW_SIM_SCGC7_MPU(v) (BITBAND_ACCESS32(HW_SIM_SCGC7_ADDR, BP_SIM_SCGC7_MPU) = (v))
bogdanm 82:6473597d706e 3651 #endif
bogdanm 82:6473597d706e 3652 //@}
bogdanm 82:6473597d706e 3653
bogdanm 82:6473597d706e 3654 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3655 // HW_SIM_CLKDIV1 - System Clock Divider Register 1
bogdanm 82:6473597d706e 3656 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3657
bogdanm 82:6473597d706e 3658 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3659 /*!
bogdanm 82:6473597d706e 3660 * @brief HW_SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
bogdanm 82:6473597d706e 3661 *
bogdanm 82:6473597d706e 3662 * Reset value: 0x00010000U
bogdanm 82:6473597d706e 3663 *
bogdanm 82:6473597d706e 3664 * When updating CLKDIV1, update all fields using the one write command.
bogdanm 82:6473597d706e 3665 * Attempting to write an invalid clock ratio to the CLKDIV1 register will cause the
bogdanm 82:6473597d706e 3666 * write to be ignored. The maximum divide ratio that can be programmed between
bogdanm 82:6473597d706e 3667 * core/system clock and the other divided clocks is divide by 8. When OUTDIV1 equals
bogdanm 82:6473597d706e 3668 * 0000 (divide by 1), the other dividers cannot be set higher than 0111 (divide
bogdanm 82:6473597d706e 3669 * by 8). The CLKDIV1 register cannot be written to when the device is in VLPR
bogdanm 82:6473597d706e 3670 * mode.
bogdanm 82:6473597d706e 3671 */
bogdanm 82:6473597d706e 3672 typedef union _hw_sim_clkdiv1
bogdanm 82:6473597d706e 3673 {
bogdanm 82:6473597d706e 3674 uint32_t U;
bogdanm 82:6473597d706e 3675 struct _hw_sim_clkdiv1_bitfields
bogdanm 82:6473597d706e 3676 {
bogdanm 82:6473597d706e 3677 uint32_t RESERVED0 : 16; //!< [15:0]
bogdanm 82:6473597d706e 3678 uint32_t OUTDIV4 : 4; //!< [19:16] Clock 4 output divider value
bogdanm 82:6473597d706e 3679 uint32_t OUTDIV3 : 4; //!< [23:20] Clock 3 output divider value
bogdanm 82:6473597d706e 3680 uint32_t OUTDIV2 : 4; //!< [27:24] Clock 2 output divider value
bogdanm 82:6473597d706e 3681 uint32_t OUTDIV1 : 4; //!< [31:28] Clock 1 output divider value
bogdanm 82:6473597d706e 3682 } B;
bogdanm 82:6473597d706e 3683 } hw_sim_clkdiv1_t;
bogdanm 82:6473597d706e 3684 #endif
bogdanm 82:6473597d706e 3685
bogdanm 82:6473597d706e 3686 /*!
bogdanm 82:6473597d706e 3687 * @name Constants and macros for entire SIM_CLKDIV1 register
bogdanm 82:6473597d706e 3688 */
bogdanm 82:6473597d706e 3689 //@{
bogdanm 82:6473597d706e 3690 #define HW_SIM_CLKDIV1_ADDR (REGS_SIM_BASE + 0x1044U)
bogdanm 82:6473597d706e 3691
bogdanm 82:6473597d706e 3692 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3693 #define HW_SIM_CLKDIV1 (*(__IO hw_sim_clkdiv1_t *) HW_SIM_CLKDIV1_ADDR)
bogdanm 82:6473597d706e 3694 #define HW_SIM_CLKDIV1_RD() (HW_SIM_CLKDIV1.U)
bogdanm 82:6473597d706e 3695 #define HW_SIM_CLKDIV1_WR(v) (HW_SIM_CLKDIV1.U = (v))
bogdanm 82:6473597d706e 3696 #define HW_SIM_CLKDIV1_SET(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() | (v)))
bogdanm 82:6473597d706e 3697 #define HW_SIM_CLKDIV1_CLR(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() & ~(v)))
bogdanm 82:6473597d706e 3698 #define HW_SIM_CLKDIV1_TOG(v) (HW_SIM_CLKDIV1_WR(HW_SIM_CLKDIV1_RD() ^ (v)))
bogdanm 82:6473597d706e 3699 #endif
bogdanm 82:6473597d706e 3700 //@}
bogdanm 82:6473597d706e 3701
bogdanm 82:6473597d706e 3702 /*
bogdanm 82:6473597d706e 3703 * Constants & macros for individual SIM_CLKDIV1 bitfields
bogdanm 82:6473597d706e 3704 */
bogdanm 82:6473597d706e 3705
bogdanm 82:6473597d706e 3706 /*!
bogdanm 82:6473597d706e 3707 * @name Register SIM_CLKDIV1, field OUTDIV4[19:16] (RW)
bogdanm 82:6473597d706e 3708 *
bogdanm 82:6473597d706e 3709 * This field sets the divide value for the flash clock from MCGOUTCLK. At the
bogdanm 82:6473597d706e 3710 * end of reset, it is loaded with either 0001 or 1111 depending on
bogdanm 82:6473597d706e 3711 * FTF_FOPT[LPBOOT]. The flash clock frequency must be an integer divide of the system clock
bogdanm 82:6473597d706e 3712 * frequency.
bogdanm 82:6473597d706e 3713 *
bogdanm 82:6473597d706e 3714 * Values:
bogdanm 82:6473597d706e 3715 * - 0000 - Divide-by-1.
bogdanm 82:6473597d706e 3716 * - 0001 - Divide-by-2.
bogdanm 82:6473597d706e 3717 * - 0010 - Divide-by-3.
bogdanm 82:6473597d706e 3718 * - 0011 - Divide-by-4.
bogdanm 82:6473597d706e 3719 * - 0100 - Divide-by-5.
bogdanm 82:6473597d706e 3720 * - 0101 - Divide-by-6.
bogdanm 82:6473597d706e 3721 * - 0110 - Divide-by-7.
bogdanm 82:6473597d706e 3722 * - 0111 - Divide-by-8.
bogdanm 82:6473597d706e 3723 * - 1000 - Divide-by-9.
bogdanm 82:6473597d706e 3724 * - 1001 - Divide-by-10.
bogdanm 82:6473597d706e 3725 * - 1010 - Divide-by-11.
bogdanm 82:6473597d706e 3726 * - 1011 - Divide-by-12.
bogdanm 82:6473597d706e 3727 * - 1100 - Divide-by-13.
bogdanm 82:6473597d706e 3728 * - 1101 - Divide-by-14.
bogdanm 82:6473597d706e 3729 * - 1110 - Divide-by-15.
bogdanm 82:6473597d706e 3730 * - 1111 - Divide-by-16.
bogdanm 82:6473597d706e 3731 */
bogdanm 82:6473597d706e 3732 //@{
bogdanm 82:6473597d706e 3733 #define BP_SIM_CLKDIV1_OUTDIV4 (16U) //!< Bit position for SIM_CLKDIV1_OUTDIV4.
bogdanm 82:6473597d706e 3734 #define BM_SIM_CLKDIV1_OUTDIV4 (0x000F0000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV4.
bogdanm 82:6473597d706e 3735 #define BS_SIM_CLKDIV1_OUTDIV4 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV4.
bogdanm 82:6473597d706e 3736
bogdanm 82:6473597d706e 3737 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3738 //! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field.
bogdanm 82:6473597d706e 3739 #define BR_SIM_CLKDIV1_OUTDIV4 (HW_SIM_CLKDIV1.B.OUTDIV4)
bogdanm 82:6473597d706e 3740 #endif
bogdanm 82:6473597d706e 3741
bogdanm 82:6473597d706e 3742 //! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV4.
bogdanm 82:6473597d706e 3743 #define BF_SIM_CLKDIV1_OUTDIV4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV4), uint32_t) & BM_SIM_CLKDIV1_OUTDIV4)
bogdanm 82:6473597d706e 3744
bogdanm 82:6473597d706e 3745 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3746 //! @brief Set the OUTDIV4 field to a new value.
bogdanm 82:6473597d706e 3747 #define BW_SIM_CLKDIV1_OUTDIV4(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV4) | BF_SIM_CLKDIV1_OUTDIV4(v)))
bogdanm 82:6473597d706e 3748 #endif
bogdanm 82:6473597d706e 3749 //@}
bogdanm 82:6473597d706e 3750
bogdanm 82:6473597d706e 3751 /*!
bogdanm 82:6473597d706e 3752 * @name Register SIM_CLKDIV1, field OUTDIV3[23:20] (RW)
bogdanm 82:6473597d706e 3753 *
bogdanm 82:6473597d706e 3754 * This field sets the divide value for the FlexBus clock (external pin FB_CLK)
bogdanm 82:6473597d706e 3755 * from MCGOUTCLK. At the end of reset, it is loaded with either 0001 or 1111
bogdanm 82:6473597d706e 3756 * depending on FTF_FOPT[LPBOOT]. The FlexBus clock frequency must be an integer
bogdanm 82:6473597d706e 3757 * divide of the system clock frequency.
bogdanm 82:6473597d706e 3758 *
bogdanm 82:6473597d706e 3759 * Values:
bogdanm 82:6473597d706e 3760 * - 0000 - Divide-by-1.
bogdanm 82:6473597d706e 3761 * - 0001 - Divide-by-2.
bogdanm 82:6473597d706e 3762 * - 0010 - Divide-by-3.
bogdanm 82:6473597d706e 3763 * - 0011 - Divide-by-4.
bogdanm 82:6473597d706e 3764 * - 0100 - Divide-by-5.
bogdanm 82:6473597d706e 3765 * - 0101 - Divide-by-6.
bogdanm 82:6473597d706e 3766 * - 0110 - Divide-by-7.
bogdanm 82:6473597d706e 3767 * - 0111 - Divide-by-8.
bogdanm 82:6473597d706e 3768 * - 1000 - Divide-by-9.
bogdanm 82:6473597d706e 3769 * - 1001 - Divide-by-10.
bogdanm 82:6473597d706e 3770 * - 1010 - Divide-by-11.
bogdanm 82:6473597d706e 3771 * - 1011 - Divide-by-12.
bogdanm 82:6473597d706e 3772 * - 1100 - Divide-by-13.
bogdanm 82:6473597d706e 3773 * - 1101 - Divide-by-14.
bogdanm 82:6473597d706e 3774 * - 1110 - Divide-by-15.
bogdanm 82:6473597d706e 3775 * - 1111 - Divide-by-16.
bogdanm 82:6473597d706e 3776 */
bogdanm 82:6473597d706e 3777 //@{
bogdanm 82:6473597d706e 3778 #define BP_SIM_CLKDIV1_OUTDIV3 (20U) //!< Bit position for SIM_CLKDIV1_OUTDIV3.
bogdanm 82:6473597d706e 3779 #define BM_SIM_CLKDIV1_OUTDIV3 (0x00F00000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV3.
bogdanm 82:6473597d706e 3780 #define BS_SIM_CLKDIV1_OUTDIV3 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV3.
bogdanm 82:6473597d706e 3781
bogdanm 82:6473597d706e 3782 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3783 //! @brief Read current value of the SIM_CLKDIV1_OUTDIV3 field.
bogdanm 82:6473597d706e 3784 #define BR_SIM_CLKDIV1_OUTDIV3 (HW_SIM_CLKDIV1.B.OUTDIV3)
bogdanm 82:6473597d706e 3785 #endif
bogdanm 82:6473597d706e 3786
bogdanm 82:6473597d706e 3787 //! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV3.
bogdanm 82:6473597d706e 3788 #define BF_SIM_CLKDIV1_OUTDIV3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV3), uint32_t) & BM_SIM_CLKDIV1_OUTDIV3)
bogdanm 82:6473597d706e 3789
bogdanm 82:6473597d706e 3790 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3791 //! @brief Set the OUTDIV3 field to a new value.
bogdanm 82:6473597d706e 3792 #define BW_SIM_CLKDIV1_OUTDIV3(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV3) | BF_SIM_CLKDIV1_OUTDIV3(v)))
bogdanm 82:6473597d706e 3793 #endif
bogdanm 82:6473597d706e 3794 //@}
bogdanm 82:6473597d706e 3795
bogdanm 82:6473597d706e 3796 /*!
bogdanm 82:6473597d706e 3797 * @name Register SIM_CLKDIV1, field OUTDIV2[27:24] (RW)
bogdanm 82:6473597d706e 3798 *
bogdanm 82:6473597d706e 3799 * This field sets the divide value for the bus clock from MCGOUTCLK. At the end
bogdanm 82:6473597d706e 3800 * of reset, it is loaded with either 0000 or 0111 depending on
bogdanm 82:6473597d706e 3801 * FTF_FOPT[LPBOOT]. The bus clock frequency must be an integer divide of the core/system clock
bogdanm 82:6473597d706e 3802 * frequency.
bogdanm 82:6473597d706e 3803 *
bogdanm 82:6473597d706e 3804 * Values:
bogdanm 82:6473597d706e 3805 * - 0000 - Divide-by-1.
bogdanm 82:6473597d706e 3806 * - 0001 - Divide-by-2.
bogdanm 82:6473597d706e 3807 * - 0010 - Divide-by-3.
bogdanm 82:6473597d706e 3808 * - 0011 - Divide-by-4.
bogdanm 82:6473597d706e 3809 * - 0100 - Divide-by-5.
bogdanm 82:6473597d706e 3810 * - 0101 - Divide-by-6.
bogdanm 82:6473597d706e 3811 * - 0110 - Divide-by-7.
bogdanm 82:6473597d706e 3812 * - 0111 - Divide-by-8.
bogdanm 82:6473597d706e 3813 * - 1000 - Divide-by-9.
bogdanm 82:6473597d706e 3814 * - 1001 - Divide-by-10.
bogdanm 82:6473597d706e 3815 * - 1010 - Divide-by-11.
bogdanm 82:6473597d706e 3816 * - 1011 - Divide-by-12.
bogdanm 82:6473597d706e 3817 * - 1100 - Divide-by-13.
bogdanm 82:6473597d706e 3818 * - 1101 - Divide-by-14.
bogdanm 82:6473597d706e 3819 * - 1110 - Divide-by-15.
bogdanm 82:6473597d706e 3820 * - 1111 - Divide-by-16.
bogdanm 82:6473597d706e 3821 */
bogdanm 82:6473597d706e 3822 //@{
bogdanm 82:6473597d706e 3823 #define BP_SIM_CLKDIV1_OUTDIV2 (24U) //!< Bit position for SIM_CLKDIV1_OUTDIV2.
bogdanm 82:6473597d706e 3824 #define BM_SIM_CLKDIV1_OUTDIV2 (0x0F000000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV2.
bogdanm 82:6473597d706e 3825 #define BS_SIM_CLKDIV1_OUTDIV2 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV2.
bogdanm 82:6473597d706e 3826
bogdanm 82:6473597d706e 3827 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3828 //! @brief Read current value of the SIM_CLKDIV1_OUTDIV2 field.
bogdanm 82:6473597d706e 3829 #define BR_SIM_CLKDIV1_OUTDIV2 (HW_SIM_CLKDIV1.B.OUTDIV2)
bogdanm 82:6473597d706e 3830 #endif
bogdanm 82:6473597d706e 3831
bogdanm 82:6473597d706e 3832 //! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV2.
bogdanm 82:6473597d706e 3833 #define BF_SIM_CLKDIV1_OUTDIV2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV2), uint32_t) & BM_SIM_CLKDIV1_OUTDIV2)
bogdanm 82:6473597d706e 3834
bogdanm 82:6473597d706e 3835 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3836 //! @brief Set the OUTDIV2 field to a new value.
bogdanm 82:6473597d706e 3837 #define BW_SIM_CLKDIV1_OUTDIV2(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV2) | BF_SIM_CLKDIV1_OUTDIV2(v)))
bogdanm 82:6473597d706e 3838 #endif
bogdanm 82:6473597d706e 3839 //@}
bogdanm 82:6473597d706e 3840
bogdanm 82:6473597d706e 3841 /*!
bogdanm 82:6473597d706e 3842 * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
bogdanm 82:6473597d706e 3843 *
bogdanm 82:6473597d706e 3844 * This field sets the divide value for the core/system clock from MCGOUTCLK. At
bogdanm 82:6473597d706e 3845 * the end of reset, it is loaded with either 0000 or 0111 depending on
bogdanm 82:6473597d706e 3846 * FTF_FOPT[LPBOOT].
bogdanm 82:6473597d706e 3847 *
bogdanm 82:6473597d706e 3848 * Values:
bogdanm 82:6473597d706e 3849 * - 0000 - Divide-by-1.
bogdanm 82:6473597d706e 3850 * - 0001 - Divide-by-2.
bogdanm 82:6473597d706e 3851 * - 0010 - Divide-by-3.
bogdanm 82:6473597d706e 3852 * - 0011 - Divide-by-4.
bogdanm 82:6473597d706e 3853 * - 0100 - Divide-by-5.
bogdanm 82:6473597d706e 3854 * - 0101 - Divide-by-6.
bogdanm 82:6473597d706e 3855 * - 0110 - Divide-by-7.
bogdanm 82:6473597d706e 3856 * - 0111 - Divide-by-8.
bogdanm 82:6473597d706e 3857 * - 1000 - Divide-by-9.
bogdanm 82:6473597d706e 3858 * - 1001 - Divide-by-10.
bogdanm 82:6473597d706e 3859 * - 1010 - Divide-by-11.
bogdanm 82:6473597d706e 3860 * - 1011 - Divide-by-12.
bogdanm 82:6473597d706e 3861 * - 1100 - Divide-by-13.
bogdanm 82:6473597d706e 3862 * - 1101 - Divide-by-14.
bogdanm 82:6473597d706e 3863 * - 1110 - Divide-by-15.
bogdanm 82:6473597d706e 3864 * - 1111 - Divide-by-16.
bogdanm 82:6473597d706e 3865 */
bogdanm 82:6473597d706e 3866 //@{
bogdanm 82:6473597d706e 3867 #define BP_SIM_CLKDIV1_OUTDIV1 (28U) //!< Bit position for SIM_CLKDIV1_OUTDIV1.
bogdanm 82:6473597d706e 3868 #define BM_SIM_CLKDIV1_OUTDIV1 (0xF0000000U) //!< Bit mask for SIM_CLKDIV1_OUTDIV1.
bogdanm 82:6473597d706e 3869 #define BS_SIM_CLKDIV1_OUTDIV1 (4U) //!< Bit field size in bits for SIM_CLKDIV1_OUTDIV1.
bogdanm 82:6473597d706e 3870
bogdanm 82:6473597d706e 3871 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3872 //! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field.
bogdanm 82:6473597d706e 3873 #define BR_SIM_CLKDIV1_OUTDIV1 (HW_SIM_CLKDIV1.B.OUTDIV1)
bogdanm 82:6473597d706e 3874 #endif
bogdanm 82:6473597d706e 3875
bogdanm 82:6473597d706e 3876 //! @brief Format value for bitfield SIM_CLKDIV1_OUTDIV1.
bogdanm 82:6473597d706e 3877 #define BF_SIM_CLKDIV1_OUTDIV1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV1_OUTDIV1), uint32_t) & BM_SIM_CLKDIV1_OUTDIV1)
bogdanm 82:6473597d706e 3878
bogdanm 82:6473597d706e 3879 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3880 //! @brief Set the OUTDIV1 field to a new value.
bogdanm 82:6473597d706e 3881 #define BW_SIM_CLKDIV1_OUTDIV1(v) (HW_SIM_CLKDIV1_WR((HW_SIM_CLKDIV1_RD() & ~BM_SIM_CLKDIV1_OUTDIV1) | BF_SIM_CLKDIV1_OUTDIV1(v)))
bogdanm 82:6473597d706e 3882 #endif
bogdanm 82:6473597d706e 3883 //@}
bogdanm 82:6473597d706e 3884
bogdanm 82:6473597d706e 3885 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3886 // HW_SIM_CLKDIV2 - System Clock Divider Register 2
bogdanm 82:6473597d706e 3887 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3888
bogdanm 82:6473597d706e 3889 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3890 /*!
bogdanm 82:6473597d706e 3891 * @brief HW_SIM_CLKDIV2 - System Clock Divider Register 2 (RW)
bogdanm 82:6473597d706e 3892 *
bogdanm 82:6473597d706e 3893 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 3894 */
bogdanm 82:6473597d706e 3895 typedef union _hw_sim_clkdiv2
bogdanm 82:6473597d706e 3896 {
bogdanm 82:6473597d706e 3897 uint32_t U;
bogdanm 82:6473597d706e 3898 struct _hw_sim_clkdiv2_bitfields
bogdanm 82:6473597d706e 3899 {
bogdanm 82:6473597d706e 3900 uint32_t USBFRAC : 1; //!< [0] USB clock divider fraction
bogdanm 82:6473597d706e 3901 uint32_t USBDIV : 3; //!< [3:1] USB clock divider divisor
bogdanm 82:6473597d706e 3902 uint32_t RESERVED0 : 28; //!< [31:4]
bogdanm 82:6473597d706e 3903 } B;
bogdanm 82:6473597d706e 3904 } hw_sim_clkdiv2_t;
bogdanm 82:6473597d706e 3905 #endif
bogdanm 82:6473597d706e 3906
bogdanm 82:6473597d706e 3907 /*!
bogdanm 82:6473597d706e 3908 * @name Constants and macros for entire SIM_CLKDIV2 register
bogdanm 82:6473597d706e 3909 */
bogdanm 82:6473597d706e 3910 //@{
bogdanm 82:6473597d706e 3911 #define HW_SIM_CLKDIV2_ADDR (REGS_SIM_BASE + 0x1048U)
bogdanm 82:6473597d706e 3912
bogdanm 82:6473597d706e 3913 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3914 #define HW_SIM_CLKDIV2 (*(__IO hw_sim_clkdiv2_t *) HW_SIM_CLKDIV2_ADDR)
bogdanm 82:6473597d706e 3915 #define HW_SIM_CLKDIV2_RD() (HW_SIM_CLKDIV2.U)
bogdanm 82:6473597d706e 3916 #define HW_SIM_CLKDIV2_WR(v) (HW_SIM_CLKDIV2.U = (v))
bogdanm 82:6473597d706e 3917 #define HW_SIM_CLKDIV2_SET(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() | (v)))
bogdanm 82:6473597d706e 3918 #define HW_SIM_CLKDIV2_CLR(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() & ~(v)))
bogdanm 82:6473597d706e 3919 #define HW_SIM_CLKDIV2_TOG(v) (HW_SIM_CLKDIV2_WR(HW_SIM_CLKDIV2_RD() ^ (v)))
bogdanm 82:6473597d706e 3920 #endif
bogdanm 82:6473597d706e 3921 //@}
bogdanm 82:6473597d706e 3922
bogdanm 82:6473597d706e 3923 /*
bogdanm 82:6473597d706e 3924 * Constants & macros for individual SIM_CLKDIV2 bitfields
bogdanm 82:6473597d706e 3925 */
bogdanm 82:6473597d706e 3926
bogdanm 82:6473597d706e 3927 /*!
bogdanm 82:6473597d706e 3928 * @name Register SIM_CLKDIV2, field USBFRAC[0] (RW)
bogdanm 82:6473597d706e 3929 *
bogdanm 82:6473597d706e 3930 * This field sets the fraction multiply value for the fractional clock divider
bogdanm 82:6473597d706e 3931 * when the MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] =
bogdanm 82:6473597d706e 3932 * 1). Divider output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
bogdanm 82:6473597d706e 3933 */
bogdanm 82:6473597d706e 3934 //@{
bogdanm 82:6473597d706e 3935 #define BP_SIM_CLKDIV2_USBFRAC (0U) //!< Bit position for SIM_CLKDIV2_USBFRAC.
bogdanm 82:6473597d706e 3936 #define BM_SIM_CLKDIV2_USBFRAC (0x00000001U) //!< Bit mask for SIM_CLKDIV2_USBFRAC.
bogdanm 82:6473597d706e 3937 #define BS_SIM_CLKDIV2_USBFRAC (1U) //!< Bit field size in bits for SIM_CLKDIV2_USBFRAC.
bogdanm 82:6473597d706e 3938
bogdanm 82:6473597d706e 3939 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3940 //! @brief Read current value of the SIM_CLKDIV2_USBFRAC field.
bogdanm 82:6473597d706e 3941 #define BR_SIM_CLKDIV2_USBFRAC (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR, BP_SIM_CLKDIV2_USBFRAC))
bogdanm 82:6473597d706e 3942 #endif
bogdanm 82:6473597d706e 3943
bogdanm 82:6473597d706e 3944 //! @brief Format value for bitfield SIM_CLKDIV2_USBFRAC.
bogdanm 82:6473597d706e 3945 #define BF_SIM_CLKDIV2_USBFRAC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV2_USBFRAC), uint32_t) & BM_SIM_CLKDIV2_USBFRAC)
bogdanm 82:6473597d706e 3946
bogdanm 82:6473597d706e 3947 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3948 //! @brief Set the USBFRAC field to a new value.
bogdanm 82:6473597d706e 3949 #define BW_SIM_CLKDIV2_USBFRAC(v) (BITBAND_ACCESS32(HW_SIM_CLKDIV2_ADDR, BP_SIM_CLKDIV2_USBFRAC) = (v))
bogdanm 82:6473597d706e 3950 #endif
bogdanm 82:6473597d706e 3951 //@}
bogdanm 82:6473597d706e 3952
bogdanm 82:6473597d706e 3953 /*!
bogdanm 82:6473597d706e 3954 * @name Register SIM_CLKDIV2, field USBDIV[3:1] (RW)
bogdanm 82:6473597d706e 3955 *
bogdanm 82:6473597d706e 3956 * This field sets the divide value for the fractional clock divider when the
bogdanm 82:6473597d706e 3957 * MCGFLLCLK/MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). Divider
bogdanm 82:6473597d706e 3958 * output clock = Divider input clock * [ (USBFRAC+1) / (USBDIV+1) ]
bogdanm 82:6473597d706e 3959 */
bogdanm 82:6473597d706e 3960 //@{
bogdanm 82:6473597d706e 3961 #define BP_SIM_CLKDIV2_USBDIV (1U) //!< Bit position for SIM_CLKDIV2_USBDIV.
bogdanm 82:6473597d706e 3962 #define BM_SIM_CLKDIV2_USBDIV (0x0000000EU) //!< Bit mask for SIM_CLKDIV2_USBDIV.
bogdanm 82:6473597d706e 3963 #define BS_SIM_CLKDIV2_USBDIV (3U) //!< Bit field size in bits for SIM_CLKDIV2_USBDIV.
bogdanm 82:6473597d706e 3964
bogdanm 82:6473597d706e 3965 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3966 //! @brief Read current value of the SIM_CLKDIV2_USBDIV field.
bogdanm 82:6473597d706e 3967 #define BR_SIM_CLKDIV2_USBDIV (HW_SIM_CLKDIV2.B.USBDIV)
bogdanm 82:6473597d706e 3968 #endif
bogdanm 82:6473597d706e 3969
bogdanm 82:6473597d706e 3970 //! @brief Format value for bitfield SIM_CLKDIV2_USBDIV.
bogdanm 82:6473597d706e 3971 #define BF_SIM_CLKDIV2_USBDIV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_CLKDIV2_USBDIV), uint32_t) & BM_SIM_CLKDIV2_USBDIV)
bogdanm 82:6473597d706e 3972
bogdanm 82:6473597d706e 3973 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3974 //! @brief Set the USBDIV field to a new value.
bogdanm 82:6473597d706e 3975 #define BW_SIM_CLKDIV2_USBDIV(v) (HW_SIM_CLKDIV2_WR((HW_SIM_CLKDIV2_RD() & ~BM_SIM_CLKDIV2_USBDIV) | BF_SIM_CLKDIV2_USBDIV(v)))
bogdanm 82:6473597d706e 3976 #endif
bogdanm 82:6473597d706e 3977 //@}
bogdanm 82:6473597d706e 3978
bogdanm 82:6473597d706e 3979 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3980 // HW_SIM_FCFG1 - Flash Configuration Register 1
bogdanm 82:6473597d706e 3981 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3982
bogdanm 82:6473597d706e 3983 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3984 /*!
bogdanm 82:6473597d706e 3985 * @brief HW_SIM_FCFG1 - Flash Configuration Register 1 (RW)
bogdanm 82:6473597d706e 3986 *
bogdanm 82:6473597d706e 3987 * Reset value: 0xFF0F0F00U
bogdanm 82:6473597d706e 3988 *
bogdanm 82:6473597d706e 3989 * For devices with FlexNVM: The reset value of EESIZE and DEPART are based on
bogdanm 82:6473597d706e 3990 * user programming in user IFR via the PGMPART flash command. For devices with
bogdanm 82:6473597d706e 3991 * program flash only:
bogdanm 82:6473597d706e 3992 */
bogdanm 82:6473597d706e 3993 typedef union _hw_sim_fcfg1
bogdanm 82:6473597d706e 3994 {
bogdanm 82:6473597d706e 3995 uint32_t U;
bogdanm 82:6473597d706e 3996 struct _hw_sim_fcfg1_bitfields
bogdanm 82:6473597d706e 3997 {
bogdanm 82:6473597d706e 3998 uint32_t FLASHDIS : 1; //!< [0] Flash Disable
bogdanm 82:6473597d706e 3999 uint32_t FLASHDOZE : 1; //!< [1] Flash Doze
bogdanm 82:6473597d706e 4000 uint32_t RESERVED0 : 6; //!< [7:2]
bogdanm 82:6473597d706e 4001 uint32_t DEPART : 4; //!< [11:8] FlexNVM partition
bogdanm 82:6473597d706e 4002 uint32_t RESERVED1 : 4; //!< [15:12]
bogdanm 82:6473597d706e 4003 uint32_t EESIZE : 4; //!< [19:16] EEPROM size
bogdanm 82:6473597d706e 4004 uint32_t RESERVED2 : 4; //!< [23:20]
bogdanm 82:6473597d706e 4005 uint32_t PFSIZE : 4; //!< [27:24] Program flash size
bogdanm 82:6473597d706e 4006 uint32_t NVMSIZE : 4; //!< [31:28] FlexNVM size
bogdanm 82:6473597d706e 4007 } B;
bogdanm 82:6473597d706e 4008 } hw_sim_fcfg1_t;
bogdanm 82:6473597d706e 4009 #endif
bogdanm 82:6473597d706e 4010
bogdanm 82:6473597d706e 4011 /*!
bogdanm 82:6473597d706e 4012 * @name Constants and macros for entire SIM_FCFG1 register
bogdanm 82:6473597d706e 4013 */
bogdanm 82:6473597d706e 4014 //@{
bogdanm 82:6473597d706e 4015 #define HW_SIM_FCFG1_ADDR (REGS_SIM_BASE + 0x104CU)
bogdanm 82:6473597d706e 4016
bogdanm 82:6473597d706e 4017 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4018 #define HW_SIM_FCFG1 (*(__IO hw_sim_fcfg1_t *) HW_SIM_FCFG1_ADDR)
bogdanm 82:6473597d706e 4019 #define HW_SIM_FCFG1_RD() (HW_SIM_FCFG1.U)
bogdanm 82:6473597d706e 4020 #define HW_SIM_FCFG1_WR(v) (HW_SIM_FCFG1.U = (v))
bogdanm 82:6473597d706e 4021 #define HW_SIM_FCFG1_SET(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() | (v)))
bogdanm 82:6473597d706e 4022 #define HW_SIM_FCFG1_CLR(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() & ~(v)))
bogdanm 82:6473597d706e 4023 #define HW_SIM_FCFG1_TOG(v) (HW_SIM_FCFG1_WR(HW_SIM_FCFG1_RD() ^ (v)))
bogdanm 82:6473597d706e 4024 #endif
bogdanm 82:6473597d706e 4025 //@}
bogdanm 82:6473597d706e 4026
bogdanm 82:6473597d706e 4027 /*
bogdanm 82:6473597d706e 4028 * Constants & macros for individual SIM_FCFG1 bitfields
bogdanm 82:6473597d706e 4029 */
bogdanm 82:6473597d706e 4030
bogdanm 82:6473597d706e 4031 /*!
bogdanm 82:6473597d706e 4032 * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
bogdanm 82:6473597d706e 4033 *
bogdanm 82:6473597d706e 4034 * Flash accesses are disabled (and generate a bus error) and the Flash memory
bogdanm 82:6473597d706e 4035 * is placed in a low power state. This bit should not be changed during VLP
bogdanm 82:6473597d706e 4036 * modes. Relocate the interrupt vectors out of Flash memory before disabling the
bogdanm 82:6473597d706e 4037 * Flash.
bogdanm 82:6473597d706e 4038 *
bogdanm 82:6473597d706e 4039 * Values:
bogdanm 82:6473597d706e 4040 * - 0 - Flash is enabled
bogdanm 82:6473597d706e 4041 * - 1 - Flash is disabled
bogdanm 82:6473597d706e 4042 */
bogdanm 82:6473597d706e 4043 //@{
bogdanm 82:6473597d706e 4044 #define BP_SIM_FCFG1_FLASHDIS (0U) //!< Bit position for SIM_FCFG1_FLASHDIS.
bogdanm 82:6473597d706e 4045 #define BM_SIM_FCFG1_FLASHDIS (0x00000001U) //!< Bit mask for SIM_FCFG1_FLASHDIS.
bogdanm 82:6473597d706e 4046 #define BS_SIM_FCFG1_FLASHDIS (1U) //!< Bit field size in bits for SIM_FCFG1_FLASHDIS.
bogdanm 82:6473597d706e 4047
bogdanm 82:6473597d706e 4048 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4049 //! @brief Read current value of the SIM_FCFG1_FLASHDIS field.
bogdanm 82:6473597d706e 4050 #define BR_SIM_FCFG1_FLASHDIS (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDIS))
bogdanm 82:6473597d706e 4051 #endif
bogdanm 82:6473597d706e 4052
bogdanm 82:6473597d706e 4053 //! @brief Format value for bitfield SIM_FCFG1_FLASHDIS.
bogdanm 82:6473597d706e 4054 #define BF_SIM_FCFG1_FLASHDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_FCFG1_FLASHDIS), uint32_t) & BM_SIM_FCFG1_FLASHDIS)
bogdanm 82:6473597d706e 4055
bogdanm 82:6473597d706e 4056 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4057 //! @brief Set the FLASHDIS field to a new value.
bogdanm 82:6473597d706e 4058 #define BW_SIM_FCFG1_FLASHDIS(v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDIS) = (v))
bogdanm 82:6473597d706e 4059 #endif
bogdanm 82:6473597d706e 4060 //@}
bogdanm 82:6473597d706e 4061
bogdanm 82:6473597d706e 4062 /*!
bogdanm 82:6473597d706e 4063 * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
bogdanm 82:6473597d706e 4064 *
bogdanm 82:6473597d706e 4065 * When set, Flash memory is disabled for the duration of Wait mode. An attempt
bogdanm 82:6473597d706e 4066 * by the DMA or other bus master to access the Flash when the Flash is disabled
bogdanm 82:6473597d706e 4067 * will result in a bus error. This bit should be clear during VLP modes. The
bogdanm 82:6473597d706e 4068 * Flash will be automatically enabled again at the end of Wait mode so interrupt
bogdanm 82:6473597d706e 4069 * vectors do not need to be relocated out of Flash memory. The wakeup time from
bogdanm 82:6473597d706e 4070 * Wait mode is extended when this bit is set.
bogdanm 82:6473597d706e 4071 *
bogdanm 82:6473597d706e 4072 * Values:
bogdanm 82:6473597d706e 4073 * - 0 - Flash remains enabled during Wait mode
bogdanm 82:6473597d706e 4074 * - 1 - Flash is disabled for the duration of Wait mode
bogdanm 82:6473597d706e 4075 */
bogdanm 82:6473597d706e 4076 //@{
bogdanm 82:6473597d706e 4077 #define BP_SIM_FCFG1_FLASHDOZE (1U) //!< Bit position for SIM_FCFG1_FLASHDOZE.
bogdanm 82:6473597d706e 4078 #define BM_SIM_FCFG1_FLASHDOZE (0x00000002U) //!< Bit mask for SIM_FCFG1_FLASHDOZE.
bogdanm 82:6473597d706e 4079 #define BS_SIM_FCFG1_FLASHDOZE (1U) //!< Bit field size in bits for SIM_FCFG1_FLASHDOZE.
bogdanm 82:6473597d706e 4080
bogdanm 82:6473597d706e 4081 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4082 //! @brief Read current value of the SIM_FCFG1_FLASHDOZE field.
bogdanm 82:6473597d706e 4083 #define BR_SIM_FCFG1_FLASHDOZE (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDOZE))
bogdanm 82:6473597d706e 4084 #endif
bogdanm 82:6473597d706e 4085
bogdanm 82:6473597d706e 4086 //! @brief Format value for bitfield SIM_FCFG1_FLASHDOZE.
bogdanm 82:6473597d706e 4087 #define BF_SIM_FCFG1_FLASHDOZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SIM_FCFG1_FLASHDOZE), uint32_t) & BM_SIM_FCFG1_FLASHDOZE)
bogdanm 82:6473597d706e 4088
bogdanm 82:6473597d706e 4089 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4090 //! @brief Set the FLASHDOZE field to a new value.
bogdanm 82:6473597d706e 4091 #define BW_SIM_FCFG1_FLASHDOZE(v) (BITBAND_ACCESS32(HW_SIM_FCFG1_ADDR, BP_SIM_FCFG1_FLASHDOZE) = (v))
bogdanm 82:6473597d706e 4092 #endif
bogdanm 82:6473597d706e 4093 //@}
bogdanm 82:6473597d706e 4094
bogdanm 82:6473597d706e 4095 /*!
bogdanm 82:6473597d706e 4096 * @name Register SIM_FCFG1, field DEPART[11:8] (RO)
bogdanm 82:6473597d706e 4097 *
bogdanm 82:6473597d706e 4098 * For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit
bogdanm 82:6473597d706e 4099 * description in FTFE chapter. For devices without FlexNVM: Reserved
bogdanm 82:6473597d706e 4100 */
bogdanm 82:6473597d706e 4101 //@{
bogdanm 82:6473597d706e 4102 #define BP_SIM_FCFG1_DEPART (8U) //!< Bit position for SIM_FCFG1_DEPART.
bogdanm 82:6473597d706e 4103 #define BM_SIM_FCFG1_DEPART (0x00000F00U) //!< Bit mask for SIM_FCFG1_DEPART.
bogdanm 82:6473597d706e 4104 #define BS_SIM_FCFG1_DEPART (4U) //!< Bit field size in bits for SIM_FCFG1_DEPART.
bogdanm 82:6473597d706e 4105
bogdanm 82:6473597d706e 4106 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4107 //! @brief Read current value of the SIM_FCFG1_DEPART field.
bogdanm 82:6473597d706e 4108 #define BR_SIM_FCFG1_DEPART (HW_SIM_FCFG1.B.DEPART)
bogdanm 82:6473597d706e 4109 #endif
bogdanm 82:6473597d706e 4110 //@}
bogdanm 82:6473597d706e 4111
bogdanm 82:6473597d706e 4112 /*!
bogdanm 82:6473597d706e 4113 * @name Register SIM_FCFG1, field EESIZE[19:16] (RO)
bogdanm 82:6473597d706e 4114 *
bogdanm 82:6473597d706e 4115 * EEPROM data size .
bogdanm 82:6473597d706e 4116 *
bogdanm 82:6473597d706e 4117 * Values:
bogdanm 82:6473597d706e 4118 * - 0000 - 16 KB
bogdanm 82:6473597d706e 4119 * - 0001 - 8 KB
bogdanm 82:6473597d706e 4120 * - 0010 - 4 KB
bogdanm 82:6473597d706e 4121 * - 0011 - 2 KB
bogdanm 82:6473597d706e 4122 * - 0100 - 1 KB
bogdanm 82:6473597d706e 4123 * - 0101 - 512 Bytes
bogdanm 82:6473597d706e 4124 * - 0110 - 256 Bytes
bogdanm 82:6473597d706e 4125 * - 0111 - 128 Bytes
bogdanm 82:6473597d706e 4126 * - 1000 - 64 Bytes
bogdanm 82:6473597d706e 4127 * - 1001 - 32 Bytes
bogdanm 82:6473597d706e 4128 * - 1111 - 0 Bytes
bogdanm 82:6473597d706e 4129 */
bogdanm 82:6473597d706e 4130 //@{
bogdanm 82:6473597d706e 4131 #define BP_SIM_FCFG1_EESIZE (16U) //!< Bit position for SIM_FCFG1_EESIZE.
bogdanm 82:6473597d706e 4132 #define BM_SIM_FCFG1_EESIZE (0x000F0000U) //!< Bit mask for SIM_FCFG1_EESIZE.
bogdanm 82:6473597d706e 4133 #define BS_SIM_FCFG1_EESIZE (4U) //!< Bit field size in bits for SIM_FCFG1_EESIZE.
bogdanm 82:6473597d706e 4134
bogdanm 82:6473597d706e 4135 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4136 //! @brief Read current value of the SIM_FCFG1_EESIZE field.
bogdanm 82:6473597d706e 4137 #define BR_SIM_FCFG1_EESIZE (HW_SIM_FCFG1.B.EESIZE)
bogdanm 82:6473597d706e 4138 #endif
bogdanm 82:6473597d706e 4139 //@}
bogdanm 82:6473597d706e 4140
bogdanm 82:6473597d706e 4141 /*!
bogdanm 82:6473597d706e 4142 * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
bogdanm 82:6473597d706e 4143 *
bogdanm 82:6473597d706e 4144 * This field specifies the amount of program flash memory available on the
bogdanm 82:6473597d706e 4145 * device . Undefined values are reserved.
bogdanm 82:6473597d706e 4146 *
bogdanm 82:6473597d706e 4147 * Values:
bogdanm 82:6473597d706e 4148 * - 0011 - 32 KB of program flash memory
bogdanm 82:6473597d706e 4149 * - 0101 - 64 KB of program flash memory
bogdanm 82:6473597d706e 4150 * - 0111 - 128 KB of program flash memory
bogdanm 82:6473597d706e 4151 * - 1001 - 256 KB of program flash memory
bogdanm 82:6473597d706e 4152 * - 1011 - 512 KB of program flash memory
bogdanm 82:6473597d706e 4153 * - 1101 - 1024 KB of program flash memory
bogdanm 82:6473597d706e 4154 * - 1111 - 1024 KB of program flash memory
bogdanm 82:6473597d706e 4155 */
bogdanm 82:6473597d706e 4156 //@{
bogdanm 82:6473597d706e 4157 #define BP_SIM_FCFG1_PFSIZE (24U) //!< Bit position for SIM_FCFG1_PFSIZE.
bogdanm 82:6473597d706e 4158 #define BM_SIM_FCFG1_PFSIZE (0x0F000000U) //!< Bit mask for SIM_FCFG1_PFSIZE.
bogdanm 82:6473597d706e 4159 #define BS_SIM_FCFG1_PFSIZE (4U) //!< Bit field size in bits for SIM_FCFG1_PFSIZE.
bogdanm 82:6473597d706e 4160
bogdanm 82:6473597d706e 4161 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4162 //! @brief Read current value of the SIM_FCFG1_PFSIZE field.
bogdanm 82:6473597d706e 4163 #define BR_SIM_FCFG1_PFSIZE (HW_SIM_FCFG1.B.PFSIZE)
bogdanm 82:6473597d706e 4164 #endif
bogdanm 82:6473597d706e 4165 //@}
bogdanm 82:6473597d706e 4166
bogdanm 82:6473597d706e 4167 /*!
bogdanm 82:6473597d706e 4168 * @name Register SIM_FCFG1, field NVMSIZE[31:28] (RO)
bogdanm 82:6473597d706e 4169 *
bogdanm 82:6473597d706e 4170 * This field specifies the amount of FlexNVM memory available on the device .
bogdanm 82:6473597d706e 4171 * Undefined values are reserved.
bogdanm 82:6473597d706e 4172 *
bogdanm 82:6473597d706e 4173 * Values:
bogdanm 82:6473597d706e 4174 * - 0000 - 0 KB of FlexNVM
bogdanm 82:6473597d706e 4175 * - 0011 - 32 KB of FlexNVM
bogdanm 82:6473597d706e 4176 * - 0101 - 64 KB of FlexNVM
bogdanm 82:6473597d706e 4177 * - 0111 - 128 KB of FlexNVM
bogdanm 82:6473597d706e 4178 * - 1001 - 256 KB of FlexNVM
bogdanm 82:6473597d706e 4179 * - 1011 - 512 KB of FlexNVM
bogdanm 82:6473597d706e 4180 * - 1111 - 512 KB of FlexNVM
bogdanm 82:6473597d706e 4181 */
bogdanm 82:6473597d706e 4182 //@{
bogdanm 82:6473597d706e 4183 #define BP_SIM_FCFG1_NVMSIZE (28U) //!< Bit position for SIM_FCFG1_NVMSIZE.
bogdanm 82:6473597d706e 4184 #define BM_SIM_FCFG1_NVMSIZE (0xF0000000U) //!< Bit mask for SIM_FCFG1_NVMSIZE.
bogdanm 82:6473597d706e 4185 #define BS_SIM_FCFG1_NVMSIZE (4U) //!< Bit field size in bits for SIM_FCFG1_NVMSIZE.
bogdanm 82:6473597d706e 4186
bogdanm 82:6473597d706e 4187 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4188 //! @brief Read current value of the SIM_FCFG1_NVMSIZE field.
bogdanm 82:6473597d706e 4189 #define BR_SIM_FCFG1_NVMSIZE (HW_SIM_FCFG1.B.NVMSIZE)
bogdanm 82:6473597d706e 4190 #endif
bogdanm 82:6473597d706e 4191 //@}
bogdanm 82:6473597d706e 4192
bogdanm 82:6473597d706e 4193 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4194 // HW_SIM_FCFG2 - Flash Configuration Register 2
bogdanm 82:6473597d706e 4195 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4196
bogdanm 82:6473597d706e 4197 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4198 /*!
bogdanm 82:6473597d706e 4199 * @brief HW_SIM_FCFG2 - Flash Configuration Register 2 (RO)
bogdanm 82:6473597d706e 4200 *
bogdanm 82:6473597d706e 4201 * Reset value: 0x7F7F0000U
bogdanm 82:6473597d706e 4202 */
bogdanm 82:6473597d706e 4203 typedef union _hw_sim_fcfg2
bogdanm 82:6473597d706e 4204 {
bogdanm 82:6473597d706e 4205 uint32_t U;
bogdanm 82:6473597d706e 4206 struct _hw_sim_fcfg2_bitfields
bogdanm 82:6473597d706e 4207 {
bogdanm 82:6473597d706e 4208 uint32_t RESERVED0 : 16; //!< [15:0]
bogdanm 82:6473597d706e 4209 uint32_t MAXADDR1 : 7; //!< [22:16] Max address block 1
bogdanm 82:6473597d706e 4210 uint32_t PFLSH : 1; //!< [23] Program flash only
bogdanm 82:6473597d706e 4211 uint32_t MAXADDR0 : 7; //!< [30:24] Max address block 0
bogdanm 82:6473597d706e 4212 uint32_t RESERVED1 : 1; //!< [31]
bogdanm 82:6473597d706e 4213 } B;
bogdanm 82:6473597d706e 4214 } hw_sim_fcfg2_t;
bogdanm 82:6473597d706e 4215 #endif
bogdanm 82:6473597d706e 4216
bogdanm 82:6473597d706e 4217 /*!
bogdanm 82:6473597d706e 4218 * @name Constants and macros for entire SIM_FCFG2 register
bogdanm 82:6473597d706e 4219 */
bogdanm 82:6473597d706e 4220 //@{
bogdanm 82:6473597d706e 4221 #define HW_SIM_FCFG2_ADDR (REGS_SIM_BASE + 0x1050U)
bogdanm 82:6473597d706e 4222
bogdanm 82:6473597d706e 4223 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4224 #define HW_SIM_FCFG2 (*(__I hw_sim_fcfg2_t *) HW_SIM_FCFG2_ADDR)
bogdanm 82:6473597d706e 4225 #define HW_SIM_FCFG2_RD() (HW_SIM_FCFG2.U)
bogdanm 82:6473597d706e 4226 #endif
bogdanm 82:6473597d706e 4227 //@}
bogdanm 82:6473597d706e 4228
bogdanm 82:6473597d706e 4229 /*
bogdanm 82:6473597d706e 4230 * Constants & macros for individual SIM_FCFG2 bitfields
bogdanm 82:6473597d706e 4231 */
bogdanm 82:6473597d706e 4232
bogdanm 82:6473597d706e 4233 /*!
bogdanm 82:6473597d706e 4234 * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
bogdanm 82:6473597d706e 4235 *
bogdanm 82:6473597d706e 4236 * For devices with FlexNVM: This field concatenated with 13 trailing zeros plus
bogdanm 82:6473597d706e 4237 * the FlexNVM base address indicates the first invalid address of the FlexNVM
bogdanm 82:6473597d706e 4238 * flash block. For example, if MAXADDR1 = 0x20 the first invalid address of
bogdanm 82:6473597d706e 4239 * FlexNVM flash block is 0x4_0000 + 0x1000_0000 . This would be the MAXADDR1 value
bogdanm 82:6473597d706e 4240 * for a device with 256 KB FlexNVM. For devices with program flash only: This
bogdanm 82:6473597d706e 4241 * field equals zero if there is only one program flash block, otherwise it equals
bogdanm 82:6473597d706e 4242 * the value of the MAXADDR0 field. For example, with MAXADDR0 = MAXADDR1 = 0x20
bogdanm 82:6473597d706e 4243 * the first invalid address of flash block 1 is 0x4_0000 + 0x4_0000. This would be
bogdanm 82:6473597d706e 4244 * the MAXADDR1 value for a device with 512 KB program flash memory across two
bogdanm 82:6473597d706e 4245 * flash blocks and no FlexNVM.
bogdanm 82:6473597d706e 4246 */
bogdanm 82:6473597d706e 4247 //@{
bogdanm 82:6473597d706e 4248 #define BP_SIM_FCFG2_MAXADDR1 (16U) //!< Bit position for SIM_FCFG2_MAXADDR1.
bogdanm 82:6473597d706e 4249 #define BM_SIM_FCFG2_MAXADDR1 (0x007F0000U) //!< Bit mask for SIM_FCFG2_MAXADDR1.
bogdanm 82:6473597d706e 4250 #define BS_SIM_FCFG2_MAXADDR1 (7U) //!< Bit field size in bits for SIM_FCFG2_MAXADDR1.
bogdanm 82:6473597d706e 4251
bogdanm 82:6473597d706e 4252 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4253 //! @brief Read current value of the SIM_FCFG2_MAXADDR1 field.
bogdanm 82:6473597d706e 4254 #define BR_SIM_FCFG2_MAXADDR1 (HW_SIM_FCFG2.B.MAXADDR1)
bogdanm 82:6473597d706e 4255 #endif
bogdanm 82:6473597d706e 4256 //@}
bogdanm 82:6473597d706e 4257
bogdanm 82:6473597d706e 4258 /*!
bogdanm 82:6473597d706e 4259 * @name Register SIM_FCFG2, field PFLSH[23] (RO)
bogdanm 82:6473597d706e 4260 *
bogdanm 82:6473597d706e 4261 * For devices with FlexNVM, this bit is always clear. For devices without
bogdanm 82:6473597d706e 4262 * FlexNVM, this bit is always set.
bogdanm 82:6473597d706e 4263 *
bogdanm 82:6473597d706e 4264 * Values:
bogdanm 82:6473597d706e 4265 * - 0 - Device supports FlexNVM
bogdanm 82:6473597d706e 4266 * - 1 - Program Flash only, device does not support FlexNVM
bogdanm 82:6473597d706e 4267 */
bogdanm 82:6473597d706e 4268 //@{
bogdanm 82:6473597d706e 4269 #define BP_SIM_FCFG2_PFLSH (23U) //!< Bit position for SIM_FCFG2_PFLSH.
bogdanm 82:6473597d706e 4270 #define BM_SIM_FCFG2_PFLSH (0x00800000U) //!< Bit mask for SIM_FCFG2_PFLSH.
bogdanm 82:6473597d706e 4271 #define BS_SIM_FCFG2_PFLSH (1U) //!< Bit field size in bits for SIM_FCFG2_PFLSH.
bogdanm 82:6473597d706e 4272
bogdanm 82:6473597d706e 4273 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4274 //! @brief Read current value of the SIM_FCFG2_PFLSH field.
bogdanm 82:6473597d706e 4275 #define BR_SIM_FCFG2_PFLSH (BITBAND_ACCESS32(HW_SIM_FCFG2_ADDR, BP_SIM_FCFG2_PFLSH))
bogdanm 82:6473597d706e 4276 #endif
bogdanm 82:6473597d706e 4277 //@}
bogdanm 82:6473597d706e 4278
bogdanm 82:6473597d706e 4279 /*!
bogdanm 82:6473597d706e 4280 * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
bogdanm 82:6473597d706e 4281 *
bogdanm 82:6473597d706e 4282 * This field concatenated with 13 trailing zeros indicates the first invalid
bogdanm 82:6473597d706e 4283 * address of each program flash block. For example, if MAXADDR0 = 0x20 the first
bogdanm 82:6473597d706e 4284 * invalid address of flash block 0 is 0x0004_0000. This would be the MAXADDR0
bogdanm 82:6473597d706e 4285 * value for a device with 256 KB program flash in flash block 0.
bogdanm 82:6473597d706e 4286 */
bogdanm 82:6473597d706e 4287 //@{
bogdanm 82:6473597d706e 4288 #define BP_SIM_FCFG2_MAXADDR0 (24U) //!< Bit position for SIM_FCFG2_MAXADDR0.
bogdanm 82:6473597d706e 4289 #define BM_SIM_FCFG2_MAXADDR0 (0x7F000000U) //!< Bit mask for SIM_FCFG2_MAXADDR0.
bogdanm 82:6473597d706e 4290 #define BS_SIM_FCFG2_MAXADDR0 (7U) //!< Bit field size in bits for SIM_FCFG2_MAXADDR0.
bogdanm 82:6473597d706e 4291
bogdanm 82:6473597d706e 4292 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4293 //! @brief Read current value of the SIM_FCFG2_MAXADDR0 field.
bogdanm 82:6473597d706e 4294 #define BR_SIM_FCFG2_MAXADDR0 (HW_SIM_FCFG2.B.MAXADDR0)
bogdanm 82:6473597d706e 4295 #endif
bogdanm 82:6473597d706e 4296 //@}
bogdanm 82:6473597d706e 4297
bogdanm 82:6473597d706e 4298 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4299 // HW_SIM_UIDH - Unique Identification Register High
bogdanm 82:6473597d706e 4300 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4301
bogdanm 82:6473597d706e 4302 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4303 /*!
bogdanm 82:6473597d706e 4304 * @brief HW_SIM_UIDH - Unique Identification Register High (RO)
bogdanm 82:6473597d706e 4305 *
bogdanm 82:6473597d706e 4306 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4307 */
bogdanm 82:6473597d706e 4308 typedef union _hw_sim_uidh
bogdanm 82:6473597d706e 4309 {
bogdanm 82:6473597d706e 4310 uint32_t U;
bogdanm 82:6473597d706e 4311 struct _hw_sim_uidh_bitfields
bogdanm 82:6473597d706e 4312 {
bogdanm 82:6473597d706e 4313 uint32_t UID : 32; //!< [31:0] Unique Identification
bogdanm 82:6473597d706e 4314 } B;
bogdanm 82:6473597d706e 4315 } hw_sim_uidh_t;
bogdanm 82:6473597d706e 4316 #endif
bogdanm 82:6473597d706e 4317
bogdanm 82:6473597d706e 4318 /*!
bogdanm 82:6473597d706e 4319 * @name Constants and macros for entire SIM_UIDH register
bogdanm 82:6473597d706e 4320 */
bogdanm 82:6473597d706e 4321 //@{
bogdanm 82:6473597d706e 4322 #define HW_SIM_UIDH_ADDR (REGS_SIM_BASE + 0x1054U)
bogdanm 82:6473597d706e 4323
bogdanm 82:6473597d706e 4324 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4325 #define HW_SIM_UIDH (*(__I hw_sim_uidh_t *) HW_SIM_UIDH_ADDR)
bogdanm 82:6473597d706e 4326 #define HW_SIM_UIDH_RD() (HW_SIM_UIDH.U)
bogdanm 82:6473597d706e 4327 #endif
bogdanm 82:6473597d706e 4328 //@}
bogdanm 82:6473597d706e 4329
bogdanm 82:6473597d706e 4330 /*
bogdanm 82:6473597d706e 4331 * Constants & macros for individual SIM_UIDH bitfields
bogdanm 82:6473597d706e 4332 */
bogdanm 82:6473597d706e 4333
bogdanm 82:6473597d706e 4334 /*!
bogdanm 82:6473597d706e 4335 * @name Register SIM_UIDH, field UID[31:0] (RO)
bogdanm 82:6473597d706e 4336 *
bogdanm 82:6473597d706e 4337 * Unique identification for the device.
bogdanm 82:6473597d706e 4338 */
bogdanm 82:6473597d706e 4339 //@{
bogdanm 82:6473597d706e 4340 #define BP_SIM_UIDH_UID (0U) //!< Bit position for SIM_UIDH_UID.
bogdanm 82:6473597d706e 4341 #define BM_SIM_UIDH_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDH_UID.
bogdanm 82:6473597d706e 4342 #define BS_SIM_UIDH_UID (32U) //!< Bit field size in bits for SIM_UIDH_UID.
bogdanm 82:6473597d706e 4343
bogdanm 82:6473597d706e 4344 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4345 //! @brief Read current value of the SIM_UIDH_UID field.
bogdanm 82:6473597d706e 4346 #define BR_SIM_UIDH_UID (HW_SIM_UIDH.U)
bogdanm 82:6473597d706e 4347 #endif
bogdanm 82:6473597d706e 4348 //@}
bogdanm 82:6473597d706e 4349
bogdanm 82:6473597d706e 4350 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4351 // HW_SIM_UIDMH - Unique Identification Register Mid-High
bogdanm 82:6473597d706e 4352 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4353
bogdanm 82:6473597d706e 4354 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4355 /*!
bogdanm 82:6473597d706e 4356 * @brief HW_SIM_UIDMH - Unique Identification Register Mid-High (RO)
bogdanm 82:6473597d706e 4357 *
bogdanm 82:6473597d706e 4358 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4359 */
bogdanm 82:6473597d706e 4360 typedef union _hw_sim_uidmh
bogdanm 82:6473597d706e 4361 {
bogdanm 82:6473597d706e 4362 uint32_t U;
bogdanm 82:6473597d706e 4363 struct _hw_sim_uidmh_bitfields
bogdanm 82:6473597d706e 4364 {
bogdanm 82:6473597d706e 4365 uint32_t UID : 32; //!< [31:0] Unique Identification
bogdanm 82:6473597d706e 4366 } B;
bogdanm 82:6473597d706e 4367 } hw_sim_uidmh_t;
bogdanm 82:6473597d706e 4368 #endif
bogdanm 82:6473597d706e 4369
bogdanm 82:6473597d706e 4370 /*!
bogdanm 82:6473597d706e 4371 * @name Constants and macros for entire SIM_UIDMH register
bogdanm 82:6473597d706e 4372 */
bogdanm 82:6473597d706e 4373 //@{
bogdanm 82:6473597d706e 4374 #define HW_SIM_UIDMH_ADDR (REGS_SIM_BASE + 0x1058U)
bogdanm 82:6473597d706e 4375
bogdanm 82:6473597d706e 4376 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4377 #define HW_SIM_UIDMH (*(__I hw_sim_uidmh_t *) HW_SIM_UIDMH_ADDR)
bogdanm 82:6473597d706e 4378 #define HW_SIM_UIDMH_RD() (HW_SIM_UIDMH.U)
bogdanm 82:6473597d706e 4379 #endif
bogdanm 82:6473597d706e 4380 //@}
bogdanm 82:6473597d706e 4381
bogdanm 82:6473597d706e 4382 /*
bogdanm 82:6473597d706e 4383 * Constants & macros for individual SIM_UIDMH bitfields
bogdanm 82:6473597d706e 4384 */
bogdanm 82:6473597d706e 4385
bogdanm 82:6473597d706e 4386 /*!
bogdanm 82:6473597d706e 4387 * @name Register SIM_UIDMH, field UID[31:0] (RO)
bogdanm 82:6473597d706e 4388 *
bogdanm 82:6473597d706e 4389 * Unique identification for the device.
bogdanm 82:6473597d706e 4390 */
bogdanm 82:6473597d706e 4391 //@{
bogdanm 82:6473597d706e 4392 #define BP_SIM_UIDMH_UID (0U) //!< Bit position for SIM_UIDMH_UID.
bogdanm 82:6473597d706e 4393 #define BM_SIM_UIDMH_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDMH_UID.
bogdanm 82:6473597d706e 4394 #define BS_SIM_UIDMH_UID (32U) //!< Bit field size in bits for SIM_UIDMH_UID.
bogdanm 82:6473597d706e 4395
bogdanm 82:6473597d706e 4396 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4397 //! @brief Read current value of the SIM_UIDMH_UID field.
bogdanm 82:6473597d706e 4398 #define BR_SIM_UIDMH_UID (HW_SIM_UIDMH.U)
bogdanm 82:6473597d706e 4399 #endif
bogdanm 82:6473597d706e 4400 //@}
bogdanm 82:6473597d706e 4401
bogdanm 82:6473597d706e 4402 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4403 // HW_SIM_UIDML - Unique Identification Register Mid Low
bogdanm 82:6473597d706e 4404 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4405
bogdanm 82:6473597d706e 4406 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4407 /*!
bogdanm 82:6473597d706e 4408 * @brief HW_SIM_UIDML - Unique Identification Register Mid Low (RO)
bogdanm 82:6473597d706e 4409 *
bogdanm 82:6473597d706e 4410 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4411 */
bogdanm 82:6473597d706e 4412 typedef union _hw_sim_uidml
bogdanm 82:6473597d706e 4413 {
bogdanm 82:6473597d706e 4414 uint32_t U;
bogdanm 82:6473597d706e 4415 struct _hw_sim_uidml_bitfields
bogdanm 82:6473597d706e 4416 {
bogdanm 82:6473597d706e 4417 uint32_t UID : 32; //!< [31:0] Unique Identification
bogdanm 82:6473597d706e 4418 } B;
bogdanm 82:6473597d706e 4419 } hw_sim_uidml_t;
bogdanm 82:6473597d706e 4420 #endif
bogdanm 82:6473597d706e 4421
bogdanm 82:6473597d706e 4422 /*!
bogdanm 82:6473597d706e 4423 * @name Constants and macros for entire SIM_UIDML register
bogdanm 82:6473597d706e 4424 */
bogdanm 82:6473597d706e 4425 //@{
bogdanm 82:6473597d706e 4426 #define HW_SIM_UIDML_ADDR (REGS_SIM_BASE + 0x105CU)
bogdanm 82:6473597d706e 4427
bogdanm 82:6473597d706e 4428 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4429 #define HW_SIM_UIDML (*(__I hw_sim_uidml_t *) HW_SIM_UIDML_ADDR)
bogdanm 82:6473597d706e 4430 #define HW_SIM_UIDML_RD() (HW_SIM_UIDML.U)
bogdanm 82:6473597d706e 4431 #endif
bogdanm 82:6473597d706e 4432 //@}
bogdanm 82:6473597d706e 4433
bogdanm 82:6473597d706e 4434 /*
bogdanm 82:6473597d706e 4435 * Constants & macros for individual SIM_UIDML bitfields
bogdanm 82:6473597d706e 4436 */
bogdanm 82:6473597d706e 4437
bogdanm 82:6473597d706e 4438 /*!
bogdanm 82:6473597d706e 4439 * @name Register SIM_UIDML, field UID[31:0] (RO)
bogdanm 82:6473597d706e 4440 *
bogdanm 82:6473597d706e 4441 * Unique identification for the device.
bogdanm 82:6473597d706e 4442 */
bogdanm 82:6473597d706e 4443 //@{
bogdanm 82:6473597d706e 4444 #define BP_SIM_UIDML_UID (0U) //!< Bit position for SIM_UIDML_UID.
bogdanm 82:6473597d706e 4445 #define BM_SIM_UIDML_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDML_UID.
bogdanm 82:6473597d706e 4446 #define BS_SIM_UIDML_UID (32U) //!< Bit field size in bits for SIM_UIDML_UID.
bogdanm 82:6473597d706e 4447
bogdanm 82:6473597d706e 4448 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4449 //! @brief Read current value of the SIM_UIDML_UID field.
bogdanm 82:6473597d706e 4450 #define BR_SIM_UIDML_UID (HW_SIM_UIDML.U)
bogdanm 82:6473597d706e 4451 #endif
bogdanm 82:6473597d706e 4452 //@}
bogdanm 82:6473597d706e 4453
bogdanm 82:6473597d706e 4454 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4455 // HW_SIM_UIDL - Unique Identification Register Low
bogdanm 82:6473597d706e 4456 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4457
bogdanm 82:6473597d706e 4458 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4459 /*!
bogdanm 82:6473597d706e 4460 * @brief HW_SIM_UIDL - Unique Identification Register Low (RO)
bogdanm 82:6473597d706e 4461 *
bogdanm 82:6473597d706e 4462 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4463 */
bogdanm 82:6473597d706e 4464 typedef union _hw_sim_uidl
bogdanm 82:6473597d706e 4465 {
bogdanm 82:6473597d706e 4466 uint32_t U;
bogdanm 82:6473597d706e 4467 struct _hw_sim_uidl_bitfields
bogdanm 82:6473597d706e 4468 {
bogdanm 82:6473597d706e 4469 uint32_t UID : 32; //!< [31:0] Unique Identification
bogdanm 82:6473597d706e 4470 } B;
bogdanm 82:6473597d706e 4471 } hw_sim_uidl_t;
bogdanm 82:6473597d706e 4472 #endif
bogdanm 82:6473597d706e 4473
bogdanm 82:6473597d706e 4474 /*!
bogdanm 82:6473597d706e 4475 * @name Constants and macros for entire SIM_UIDL register
bogdanm 82:6473597d706e 4476 */
bogdanm 82:6473597d706e 4477 //@{
bogdanm 82:6473597d706e 4478 #define HW_SIM_UIDL_ADDR (REGS_SIM_BASE + 0x1060U)
bogdanm 82:6473597d706e 4479
bogdanm 82:6473597d706e 4480 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4481 #define HW_SIM_UIDL (*(__I hw_sim_uidl_t *) HW_SIM_UIDL_ADDR)
bogdanm 82:6473597d706e 4482 #define HW_SIM_UIDL_RD() (HW_SIM_UIDL.U)
bogdanm 82:6473597d706e 4483 #endif
bogdanm 82:6473597d706e 4484 //@}
bogdanm 82:6473597d706e 4485
bogdanm 82:6473597d706e 4486 /*
bogdanm 82:6473597d706e 4487 * Constants & macros for individual SIM_UIDL bitfields
bogdanm 82:6473597d706e 4488 */
bogdanm 82:6473597d706e 4489
bogdanm 82:6473597d706e 4490 /*!
bogdanm 82:6473597d706e 4491 * @name Register SIM_UIDL, field UID[31:0] (RO)
bogdanm 82:6473597d706e 4492 *
bogdanm 82:6473597d706e 4493 * Unique identification for the device.
bogdanm 82:6473597d706e 4494 */
bogdanm 82:6473597d706e 4495 //@{
bogdanm 82:6473597d706e 4496 #define BP_SIM_UIDL_UID (0U) //!< Bit position for SIM_UIDL_UID.
bogdanm 82:6473597d706e 4497 #define BM_SIM_UIDL_UID (0xFFFFFFFFU) //!< Bit mask for SIM_UIDL_UID.
bogdanm 82:6473597d706e 4498 #define BS_SIM_UIDL_UID (32U) //!< Bit field size in bits for SIM_UIDL_UID.
bogdanm 82:6473597d706e 4499
bogdanm 82:6473597d706e 4500 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4501 //! @brief Read current value of the SIM_UIDL_UID field.
bogdanm 82:6473597d706e 4502 #define BR_SIM_UIDL_UID (HW_SIM_UIDL.U)
bogdanm 82:6473597d706e 4503 #endif
bogdanm 82:6473597d706e 4504 //@}
bogdanm 82:6473597d706e 4505
bogdanm 82:6473597d706e 4506 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4507 // hw_sim_t - module struct
bogdanm 82:6473597d706e 4508 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4509 /*!
bogdanm 82:6473597d706e 4510 * @brief All SIM module registers.
bogdanm 82:6473597d706e 4511 */
bogdanm 82:6473597d706e 4512 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4513 #pragma pack(1)
bogdanm 82:6473597d706e 4514 typedef struct _hw_sim
bogdanm 82:6473597d706e 4515 {
bogdanm 82:6473597d706e 4516 __IO hw_sim_sopt1_t SOPT1; //!< [0x0] System Options Register 1
bogdanm 82:6473597d706e 4517 __IO hw_sim_sopt1cfg_t SOPT1CFG; //!< [0x4] SOPT1 Configuration Register
bogdanm 82:6473597d706e 4518 uint8_t _reserved0[4092];
bogdanm 82:6473597d706e 4519 __IO hw_sim_sopt2_t SOPT2; //!< [0x1004] System Options Register 2
bogdanm 82:6473597d706e 4520 uint8_t _reserved1[4];
bogdanm 82:6473597d706e 4521 __IO hw_sim_sopt4_t SOPT4; //!< [0x100C] System Options Register 4
bogdanm 82:6473597d706e 4522 __IO hw_sim_sopt5_t SOPT5; //!< [0x1010] System Options Register 5
bogdanm 82:6473597d706e 4523 uint8_t _reserved2[4];
bogdanm 82:6473597d706e 4524 __IO hw_sim_sopt7_t SOPT7; //!< [0x1018] System Options Register 7
bogdanm 82:6473597d706e 4525 uint8_t _reserved3[8];
bogdanm 82:6473597d706e 4526 __I hw_sim_sdid_t SDID; //!< [0x1024] System Device Identification Register
bogdanm 82:6473597d706e 4527 __IO hw_sim_scgc1_t SCGC1; //!< [0x1028] System Clock Gating Control Register 1
bogdanm 82:6473597d706e 4528 __IO hw_sim_scgc2_t SCGC2; //!< [0x102C] System Clock Gating Control Register 2
bogdanm 82:6473597d706e 4529 __IO hw_sim_scgc3_t SCGC3; //!< [0x1030] System Clock Gating Control Register 3
bogdanm 82:6473597d706e 4530 __IO hw_sim_scgc4_t SCGC4; //!< [0x1034] System Clock Gating Control Register 4
bogdanm 82:6473597d706e 4531 __IO hw_sim_scgc5_t SCGC5; //!< [0x1038] System Clock Gating Control Register 5
bogdanm 82:6473597d706e 4532 __IO hw_sim_scgc6_t SCGC6; //!< [0x103C] System Clock Gating Control Register 6
bogdanm 82:6473597d706e 4533 __IO hw_sim_scgc7_t SCGC7; //!< [0x1040] System Clock Gating Control Register 7
bogdanm 82:6473597d706e 4534 __IO hw_sim_clkdiv1_t CLKDIV1; //!< [0x1044] System Clock Divider Register 1
bogdanm 82:6473597d706e 4535 __IO hw_sim_clkdiv2_t CLKDIV2; //!< [0x1048] System Clock Divider Register 2
bogdanm 82:6473597d706e 4536 __IO hw_sim_fcfg1_t FCFG1; //!< [0x104C] Flash Configuration Register 1
bogdanm 82:6473597d706e 4537 __I hw_sim_fcfg2_t FCFG2; //!< [0x1050] Flash Configuration Register 2
bogdanm 82:6473597d706e 4538 __I hw_sim_uidh_t UIDH; //!< [0x1054] Unique Identification Register High
bogdanm 82:6473597d706e 4539 __I hw_sim_uidmh_t UIDMH; //!< [0x1058] Unique Identification Register Mid-High
bogdanm 82:6473597d706e 4540 __I hw_sim_uidml_t UIDML; //!< [0x105C] Unique Identification Register Mid Low
bogdanm 82:6473597d706e 4541 __I hw_sim_uidl_t UIDL; //!< [0x1060] Unique Identification Register Low
bogdanm 82:6473597d706e 4542 } hw_sim_t;
bogdanm 82:6473597d706e 4543 #pragma pack()
bogdanm 82:6473597d706e 4544
bogdanm 82:6473597d706e 4545 //! @brief Macro to access all SIM registers.
bogdanm 82:6473597d706e 4546 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 4547 //! use the '&' operator, like <code>&HW_SIM</code>.
bogdanm 82:6473597d706e 4548 #define HW_SIM (*(hw_sim_t *) REGS_SIM_BASE)
bogdanm 82:6473597d706e 4549 #endif
bogdanm 82:6473597d706e 4550
bogdanm 82:6473597d706e 4551 #endif // __HW_SIM_REGISTERS_H__
bogdanm 82:6473597d706e 4552 // v22/130726/0.9
bogdanm 82:6473597d706e 4553 // EOF