雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

Fork of mbed by mbed official

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_sdhc.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_SDHC_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_SDHC_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 SDHC
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * Secured Digital Host Controller
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_SDHC_DSADDR - DMA System Address register
bogdanm 82:6473597d706e 33 * - HW_SDHC_BLKATTR - Block Attributes register
bogdanm 82:6473597d706e 34 * - HW_SDHC_CMDARG - Command Argument register
bogdanm 82:6473597d706e 35 * - HW_SDHC_XFERTYP - Transfer Type register
bogdanm 82:6473597d706e 36 * - HW_SDHC_CMDRSP0 - Command Response 0
bogdanm 82:6473597d706e 37 * - HW_SDHC_CMDRSP1 - Command Response 1
bogdanm 82:6473597d706e 38 * - HW_SDHC_CMDRSP2 - Command Response 2
bogdanm 82:6473597d706e 39 * - HW_SDHC_CMDRSP3 - Command Response 3
bogdanm 82:6473597d706e 40 * - HW_SDHC_DATPORT - Buffer Data Port register
bogdanm 82:6473597d706e 41 * - HW_SDHC_PRSSTAT - Present State register
bogdanm 82:6473597d706e 42 * - HW_SDHC_PROCTL - Protocol Control register
bogdanm 82:6473597d706e 43 * - HW_SDHC_SYSCTL - System Control register
bogdanm 82:6473597d706e 44 * - HW_SDHC_IRQSTAT - Interrupt Status register
bogdanm 82:6473597d706e 45 * - HW_SDHC_IRQSTATEN - Interrupt Status Enable register
bogdanm 82:6473597d706e 46 * - HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
bogdanm 82:6473597d706e 47 * - HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
bogdanm 82:6473597d706e 48 * - HW_SDHC_HTCAPBLT - Host Controller Capabilities
bogdanm 82:6473597d706e 49 * - HW_SDHC_WML - Watermark Level Register
bogdanm 82:6473597d706e 50 * - HW_SDHC_FEVT - Force Event register
bogdanm 82:6473597d706e 51 * - HW_SDHC_ADMAES - ADMA Error Status register
bogdanm 82:6473597d706e 52 * - HW_SDHC_ADSADDR - ADMA System Addressregister
bogdanm 82:6473597d706e 53 * - HW_SDHC_VENDOR - Vendor Specific register
bogdanm 82:6473597d706e 54 * - HW_SDHC_MMCBOOT - MMC Boot register
bogdanm 82:6473597d706e 55 * - HW_SDHC_HOSTVER - Host Controller Version
bogdanm 82:6473597d706e 56 *
bogdanm 82:6473597d706e 57 * - hw_sdhc_t - Struct containing all module registers.
bogdanm 82:6473597d706e 58 */
bogdanm 82:6473597d706e 59
bogdanm 82:6473597d706e 60 //! @name Module base addresses
bogdanm 82:6473597d706e 61 //@{
bogdanm 82:6473597d706e 62 #ifndef REGS_SDHC_BASE
bogdanm 82:6473597d706e 63 #define HW_SDHC_INSTANCE_COUNT (1U) //!< Number of instances of the SDHC module.
bogdanm 82:6473597d706e 64 #define REGS_SDHC_BASE (0x400B1000U) //!< Base address for SDHC.
bogdanm 82:6473597d706e 65 #endif
bogdanm 82:6473597d706e 66 //@}
bogdanm 82:6473597d706e 67
bogdanm 82:6473597d706e 68 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 69 // HW_SDHC_DSADDR - DMA System Address register
bogdanm 82:6473597d706e 70 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 71
bogdanm 82:6473597d706e 72 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 73 /*!
bogdanm 82:6473597d706e 74 * @brief HW_SDHC_DSADDR - DMA System Address register (RW)
bogdanm 82:6473597d706e 75 *
bogdanm 82:6473597d706e 76 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 77 *
bogdanm 82:6473597d706e 78 * This register contains the physical system memory address used for DMA
bogdanm 82:6473597d706e 79 * transfers.
bogdanm 82:6473597d706e 80 */
bogdanm 82:6473597d706e 81 typedef union _hw_sdhc_dsaddr
bogdanm 82:6473597d706e 82 {
bogdanm 82:6473597d706e 83 uint32_t U;
bogdanm 82:6473597d706e 84 struct _hw_sdhc_dsaddr_bitfields
bogdanm 82:6473597d706e 85 {
bogdanm 82:6473597d706e 86 uint32_t RESERVED0 : 2; //!< [1:0]
bogdanm 82:6473597d706e 87 uint32_t DSADDR : 30; //!< [31:2] DMA System Address
bogdanm 82:6473597d706e 88 } B;
bogdanm 82:6473597d706e 89 } hw_sdhc_dsaddr_t;
bogdanm 82:6473597d706e 90 #endif
bogdanm 82:6473597d706e 91
bogdanm 82:6473597d706e 92 /*!
bogdanm 82:6473597d706e 93 * @name Constants and macros for entire SDHC_DSADDR register
bogdanm 82:6473597d706e 94 */
bogdanm 82:6473597d706e 95 //@{
bogdanm 82:6473597d706e 96 #define HW_SDHC_DSADDR_ADDR (REGS_SDHC_BASE + 0x0U)
bogdanm 82:6473597d706e 97
bogdanm 82:6473597d706e 98 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 99 #define HW_SDHC_DSADDR (*(__IO hw_sdhc_dsaddr_t *) HW_SDHC_DSADDR_ADDR)
bogdanm 82:6473597d706e 100 #define HW_SDHC_DSADDR_RD() (HW_SDHC_DSADDR.U)
bogdanm 82:6473597d706e 101 #define HW_SDHC_DSADDR_WR(v) (HW_SDHC_DSADDR.U = (v))
bogdanm 82:6473597d706e 102 #define HW_SDHC_DSADDR_SET(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() | (v)))
bogdanm 82:6473597d706e 103 #define HW_SDHC_DSADDR_CLR(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() & ~(v)))
bogdanm 82:6473597d706e 104 #define HW_SDHC_DSADDR_TOG(v) (HW_SDHC_DSADDR_WR(HW_SDHC_DSADDR_RD() ^ (v)))
bogdanm 82:6473597d706e 105 #endif
bogdanm 82:6473597d706e 106 //@}
bogdanm 82:6473597d706e 107
bogdanm 82:6473597d706e 108 /*
bogdanm 82:6473597d706e 109 * Constants & macros for individual SDHC_DSADDR bitfields
bogdanm 82:6473597d706e 110 */
bogdanm 82:6473597d706e 111
bogdanm 82:6473597d706e 112 /*!
bogdanm 82:6473597d706e 113 * @name Register SDHC_DSADDR, field DSADDR[31:2] (RW)
bogdanm 82:6473597d706e 114 *
bogdanm 82:6473597d706e 115 * Contains the 32-bit system memory address for a DMA transfer. Because the
bogdanm 82:6473597d706e 116 * address must be word (4 bytes) align, the least 2 bits are reserved, always 0.
bogdanm 82:6473597d706e 117 * When the SDHC stops a DMA transfer, this register points to the system address
bogdanm 82:6473597d706e 118 * of the next contiguous data position. It can be accessed only when no
bogdanm 82:6473597d706e 119 * transaction is executing, that is, after a transaction has stopped. Read operation
bogdanm 82:6473597d706e 120 * during transfers may return an invalid value. The host driver shall initialize
bogdanm 82:6473597d706e 121 * this register before starting a DMA transaction. After DMA has stopped, the
bogdanm 82:6473597d706e 122 * system address of the next contiguous data position can be read from this register.
bogdanm 82:6473597d706e 123 * This register is protected during a data transfer. When data lines are
bogdanm 82:6473597d706e 124 * active, write to this register is ignored. The host driver shall wait, until
bogdanm 82:6473597d706e 125 * PRSSTAT[DLA] is cleared, before writing to this register. The SDHC internal DMA does
bogdanm 82:6473597d706e 126 * not support a virtual memory system. It supports only continuous physical
bogdanm 82:6473597d706e 127 * memory access. And due to AHB burst limitations, if the burst must cross the 1 KB
bogdanm 82:6473597d706e 128 * boundary, SDHC will automatically change SEQ burst type to NSEQ. Because this
bogdanm 82:6473597d706e 129 * register supports dynamic address reflecting, when IRQSTAT[TC] bit is set, it
bogdanm 82:6473597d706e 130 * automatically alters the value of internal address counter, so SW cannot
bogdanm 82:6473597d706e 131 * change this register when IRQSTAT[TC] is set.
bogdanm 82:6473597d706e 132 */
bogdanm 82:6473597d706e 133 //@{
bogdanm 82:6473597d706e 134 #define BP_SDHC_DSADDR_DSADDR (2U) //!< Bit position for SDHC_DSADDR_DSADDR.
bogdanm 82:6473597d706e 135 #define BM_SDHC_DSADDR_DSADDR (0xFFFFFFFCU) //!< Bit mask for SDHC_DSADDR_DSADDR.
bogdanm 82:6473597d706e 136 #define BS_SDHC_DSADDR_DSADDR (30U) //!< Bit field size in bits for SDHC_DSADDR_DSADDR.
bogdanm 82:6473597d706e 137
bogdanm 82:6473597d706e 138 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 139 //! @brief Read current value of the SDHC_DSADDR_DSADDR field.
bogdanm 82:6473597d706e 140 #define BR_SDHC_DSADDR_DSADDR (HW_SDHC_DSADDR.B.DSADDR)
bogdanm 82:6473597d706e 141 #endif
bogdanm 82:6473597d706e 142
bogdanm 82:6473597d706e 143 //! @brief Format value for bitfield SDHC_DSADDR_DSADDR.
bogdanm 82:6473597d706e 144 #define BF_SDHC_DSADDR_DSADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_DSADDR_DSADDR), uint32_t) & BM_SDHC_DSADDR_DSADDR)
bogdanm 82:6473597d706e 145
bogdanm 82:6473597d706e 146 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 147 //! @brief Set the DSADDR field to a new value.
bogdanm 82:6473597d706e 148 #define BW_SDHC_DSADDR_DSADDR(v) (HW_SDHC_DSADDR_WR((HW_SDHC_DSADDR_RD() & ~BM_SDHC_DSADDR_DSADDR) | BF_SDHC_DSADDR_DSADDR(v)))
bogdanm 82:6473597d706e 149 #endif
bogdanm 82:6473597d706e 150 //@}
bogdanm 82:6473597d706e 151
bogdanm 82:6473597d706e 152 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 153 // HW_SDHC_BLKATTR - Block Attributes register
bogdanm 82:6473597d706e 154 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 155
bogdanm 82:6473597d706e 156 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 157 /*!
bogdanm 82:6473597d706e 158 * @brief HW_SDHC_BLKATTR - Block Attributes register (RW)
bogdanm 82:6473597d706e 159 *
bogdanm 82:6473597d706e 160 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 161 *
bogdanm 82:6473597d706e 162 * This register is used to configure the number of data blocks and the number
bogdanm 82:6473597d706e 163 * of bytes in each block.
bogdanm 82:6473597d706e 164 */
bogdanm 82:6473597d706e 165 typedef union _hw_sdhc_blkattr
bogdanm 82:6473597d706e 166 {
bogdanm 82:6473597d706e 167 uint32_t U;
bogdanm 82:6473597d706e 168 struct _hw_sdhc_blkattr_bitfields
bogdanm 82:6473597d706e 169 {
bogdanm 82:6473597d706e 170 uint32_t BLKSIZE : 13; //!< [12:0] Transfer Block Size
bogdanm 82:6473597d706e 171 uint32_t RESERVED0 : 3; //!< [15:13]
bogdanm 82:6473597d706e 172 uint32_t BLKCNT : 16; //!< [31:16] Blocks Count For Current Transfer
bogdanm 82:6473597d706e 173 } B;
bogdanm 82:6473597d706e 174 } hw_sdhc_blkattr_t;
bogdanm 82:6473597d706e 175 #endif
bogdanm 82:6473597d706e 176
bogdanm 82:6473597d706e 177 /*!
bogdanm 82:6473597d706e 178 * @name Constants and macros for entire SDHC_BLKATTR register
bogdanm 82:6473597d706e 179 */
bogdanm 82:6473597d706e 180 //@{
bogdanm 82:6473597d706e 181 #define HW_SDHC_BLKATTR_ADDR (REGS_SDHC_BASE + 0x4U)
bogdanm 82:6473597d706e 182
bogdanm 82:6473597d706e 183 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 184 #define HW_SDHC_BLKATTR (*(__IO hw_sdhc_blkattr_t *) HW_SDHC_BLKATTR_ADDR)
bogdanm 82:6473597d706e 185 #define HW_SDHC_BLKATTR_RD() (HW_SDHC_BLKATTR.U)
bogdanm 82:6473597d706e 186 #define HW_SDHC_BLKATTR_WR(v) (HW_SDHC_BLKATTR.U = (v))
bogdanm 82:6473597d706e 187 #define HW_SDHC_BLKATTR_SET(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() | (v)))
bogdanm 82:6473597d706e 188 #define HW_SDHC_BLKATTR_CLR(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() & ~(v)))
bogdanm 82:6473597d706e 189 #define HW_SDHC_BLKATTR_TOG(v) (HW_SDHC_BLKATTR_WR(HW_SDHC_BLKATTR_RD() ^ (v)))
bogdanm 82:6473597d706e 190 #endif
bogdanm 82:6473597d706e 191 //@}
bogdanm 82:6473597d706e 192
bogdanm 82:6473597d706e 193 /*
bogdanm 82:6473597d706e 194 * Constants & macros for individual SDHC_BLKATTR bitfields
bogdanm 82:6473597d706e 195 */
bogdanm 82:6473597d706e 196
bogdanm 82:6473597d706e 197 /*!
bogdanm 82:6473597d706e 198 * @name Register SDHC_BLKATTR, field BLKSIZE[12:0] (RW)
bogdanm 82:6473597d706e 199 *
bogdanm 82:6473597d706e 200 * Specifies the block size for block data transfers. Values ranging from 1 byte
bogdanm 82:6473597d706e 201 * up to the maximum buffer size can be set. It can be accessed only when no
bogdanm 82:6473597d706e 202 * transaction is executing, that is, after a transaction has stopped. Read
bogdanm 82:6473597d706e 203 * operations during transfers may return an invalid value, and write operations will be
bogdanm 82:6473597d706e 204 * ignored.
bogdanm 82:6473597d706e 205 *
bogdanm 82:6473597d706e 206 * Values:
bogdanm 82:6473597d706e 207 * - 0 - No data transfer.
bogdanm 82:6473597d706e 208 * - 1 - 1 Byte
bogdanm 82:6473597d706e 209 * - 10 - 2 Bytes
bogdanm 82:6473597d706e 210 * - 11 - 3 Bytes
bogdanm 82:6473597d706e 211 * - 100 - 4 Bytes
bogdanm 82:6473597d706e 212 * - 111111111 - 511 Bytes
bogdanm 82:6473597d706e 213 * - 1000000000 - 512 Bytes
bogdanm 82:6473597d706e 214 * - 100000000000 - 2048 Bytes
bogdanm 82:6473597d706e 215 * - 1000000000000 - 4096 Bytes
bogdanm 82:6473597d706e 216 */
bogdanm 82:6473597d706e 217 //@{
bogdanm 82:6473597d706e 218 #define BP_SDHC_BLKATTR_BLKSIZE (0U) //!< Bit position for SDHC_BLKATTR_BLKSIZE.
bogdanm 82:6473597d706e 219 #define BM_SDHC_BLKATTR_BLKSIZE (0x00001FFFU) //!< Bit mask for SDHC_BLKATTR_BLKSIZE.
bogdanm 82:6473597d706e 220 #define BS_SDHC_BLKATTR_BLKSIZE (13U) //!< Bit field size in bits for SDHC_BLKATTR_BLKSIZE.
bogdanm 82:6473597d706e 221
bogdanm 82:6473597d706e 222 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 223 //! @brief Read current value of the SDHC_BLKATTR_BLKSIZE field.
bogdanm 82:6473597d706e 224 #define BR_SDHC_BLKATTR_BLKSIZE (HW_SDHC_BLKATTR.B.BLKSIZE)
bogdanm 82:6473597d706e 225 #endif
bogdanm 82:6473597d706e 226
bogdanm 82:6473597d706e 227 //! @brief Format value for bitfield SDHC_BLKATTR_BLKSIZE.
bogdanm 82:6473597d706e 228 #define BF_SDHC_BLKATTR_BLKSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_BLKATTR_BLKSIZE), uint32_t) & BM_SDHC_BLKATTR_BLKSIZE)
bogdanm 82:6473597d706e 229
bogdanm 82:6473597d706e 230 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 231 //! @brief Set the BLKSIZE field to a new value.
bogdanm 82:6473597d706e 232 #define BW_SDHC_BLKATTR_BLKSIZE(v) (HW_SDHC_BLKATTR_WR((HW_SDHC_BLKATTR_RD() & ~BM_SDHC_BLKATTR_BLKSIZE) | BF_SDHC_BLKATTR_BLKSIZE(v)))
bogdanm 82:6473597d706e 233 #endif
bogdanm 82:6473597d706e 234 //@}
bogdanm 82:6473597d706e 235
bogdanm 82:6473597d706e 236 /*!
bogdanm 82:6473597d706e 237 * @name Register SDHC_BLKATTR, field BLKCNT[31:16] (RW)
bogdanm 82:6473597d706e 238 *
bogdanm 82:6473597d706e 239 * This register is enabled when XFERTYP[BCEN] is set to 1 and is valid only for
bogdanm 82:6473597d706e 240 * multiple block transfers. For single block transfer, this register will
bogdanm 82:6473597d706e 241 * always read as 1. The host driver shall set this register to a value between 1 and
bogdanm 82:6473597d706e 242 * the maximum block count. The SDHC decrements the block count after each block
bogdanm 82:6473597d706e 243 * transfer and stops when the count reaches zero. Setting the block count to 0
bogdanm 82:6473597d706e 244 * results in no data blocks being transferred. This register must be accessed
bogdanm 82:6473597d706e 245 * only when no transaction is executing, that is, after transactions are stopped.
bogdanm 82:6473597d706e 246 * During data transfer, read operations on this register may return an invalid
bogdanm 82:6473597d706e 247 * value and write operations are ignored. When saving transfer content as a result
bogdanm 82:6473597d706e 248 * of a suspend command, the number of blocks yet to be transferred can be
bogdanm 82:6473597d706e 249 * determined by reading this register. The reading of this register must be applied
bogdanm 82:6473597d706e 250 * after transfer is paused by stop at block gap operation and before sending the
bogdanm 82:6473597d706e 251 * command marked as suspend. This is because when suspend command is sent out,
bogdanm 82:6473597d706e 252 * SDHC will regard the current transfer as aborted and change BLKCNT back to its
bogdanm 82:6473597d706e 253 * original value instead of keeping the dynamical indicator of remained block
bogdanm 82:6473597d706e 254 * count. When restoring transfer content prior to issuing a resume command, the
bogdanm 82:6473597d706e 255 * host driver shall restore the previously saved block count. Although the BLKCNT
bogdanm 82:6473597d706e 256 * field is 0 after reset, the read of reset value is 0x1. This is because when
bogdanm 82:6473597d706e 257 * XFERTYP[MSBSEL] is 0, indicating a single block transfer, the read value of
bogdanm 82:6473597d706e 258 * BLKCNT is always 1.
bogdanm 82:6473597d706e 259 *
bogdanm 82:6473597d706e 260 * Values:
bogdanm 82:6473597d706e 261 * - 0 - Stop count.
bogdanm 82:6473597d706e 262 * - 1 - 1 block
bogdanm 82:6473597d706e 263 * - 10 - 2 blocks
bogdanm 82:6473597d706e 264 * - 1111111111111111 - 65535 blocks
bogdanm 82:6473597d706e 265 */
bogdanm 82:6473597d706e 266 //@{
bogdanm 82:6473597d706e 267 #define BP_SDHC_BLKATTR_BLKCNT (16U) //!< Bit position for SDHC_BLKATTR_BLKCNT.
bogdanm 82:6473597d706e 268 #define BM_SDHC_BLKATTR_BLKCNT (0xFFFF0000U) //!< Bit mask for SDHC_BLKATTR_BLKCNT.
bogdanm 82:6473597d706e 269 #define BS_SDHC_BLKATTR_BLKCNT (16U) //!< Bit field size in bits for SDHC_BLKATTR_BLKCNT.
bogdanm 82:6473597d706e 270
bogdanm 82:6473597d706e 271 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 272 //! @brief Read current value of the SDHC_BLKATTR_BLKCNT field.
bogdanm 82:6473597d706e 273 #define BR_SDHC_BLKATTR_BLKCNT (HW_SDHC_BLKATTR.B.BLKCNT)
bogdanm 82:6473597d706e 274 #endif
bogdanm 82:6473597d706e 275
bogdanm 82:6473597d706e 276 //! @brief Format value for bitfield SDHC_BLKATTR_BLKCNT.
bogdanm 82:6473597d706e 277 #define BF_SDHC_BLKATTR_BLKCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_BLKATTR_BLKCNT), uint32_t) & BM_SDHC_BLKATTR_BLKCNT)
bogdanm 82:6473597d706e 278
bogdanm 82:6473597d706e 279 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 280 //! @brief Set the BLKCNT field to a new value.
bogdanm 82:6473597d706e 281 #define BW_SDHC_BLKATTR_BLKCNT(v) (HW_SDHC_BLKATTR_WR((HW_SDHC_BLKATTR_RD() & ~BM_SDHC_BLKATTR_BLKCNT) | BF_SDHC_BLKATTR_BLKCNT(v)))
bogdanm 82:6473597d706e 282 #endif
bogdanm 82:6473597d706e 283 //@}
bogdanm 82:6473597d706e 284
bogdanm 82:6473597d706e 285 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 286 // HW_SDHC_CMDARG - Command Argument register
bogdanm 82:6473597d706e 287 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 288
bogdanm 82:6473597d706e 289 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 290 /*!
bogdanm 82:6473597d706e 291 * @brief HW_SDHC_CMDARG - Command Argument register (RW)
bogdanm 82:6473597d706e 292 *
bogdanm 82:6473597d706e 293 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 294 *
bogdanm 82:6473597d706e 295 * This register contains the SD/MMC command argument.
bogdanm 82:6473597d706e 296 */
bogdanm 82:6473597d706e 297 typedef union _hw_sdhc_cmdarg
bogdanm 82:6473597d706e 298 {
bogdanm 82:6473597d706e 299 uint32_t U;
bogdanm 82:6473597d706e 300 struct _hw_sdhc_cmdarg_bitfields
bogdanm 82:6473597d706e 301 {
bogdanm 82:6473597d706e 302 uint32_t CMDARG : 32; //!< [31:0] Command Argument
bogdanm 82:6473597d706e 303 } B;
bogdanm 82:6473597d706e 304 } hw_sdhc_cmdarg_t;
bogdanm 82:6473597d706e 305 #endif
bogdanm 82:6473597d706e 306
bogdanm 82:6473597d706e 307 /*!
bogdanm 82:6473597d706e 308 * @name Constants and macros for entire SDHC_CMDARG register
bogdanm 82:6473597d706e 309 */
bogdanm 82:6473597d706e 310 //@{
bogdanm 82:6473597d706e 311 #define HW_SDHC_CMDARG_ADDR (REGS_SDHC_BASE + 0x8U)
bogdanm 82:6473597d706e 312
bogdanm 82:6473597d706e 313 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 314 #define HW_SDHC_CMDARG (*(__IO hw_sdhc_cmdarg_t *) HW_SDHC_CMDARG_ADDR)
bogdanm 82:6473597d706e 315 #define HW_SDHC_CMDARG_RD() (HW_SDHC_CMDARG.U)
bogdanm 82:6473597d706e 316 #define HW_SDHC_CMDARG_WR(v) (HW_SDHC_CMDARG.U = (v))
bogdanm 82:6473597d706e 317 #define HW_SDHC_CMDARG_SET(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() | (v)))
bogdanm 82:6473597d706e 318 #define HW_SDHC_CMDARG_CLR(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() & ~(v)))
bogdanm 82:6473597d706e 319 #define HW_SDHC_CMDARG_TOG(v) (HW_SDHC_CMDARG_WR(HW_SDHC_CMDARG_RD() ^ (v)))
bogdanm 82:6473597d706e 320 #endif
bogdanm 82:6473597d706e 321 //@}
bogdanm 82:6473597d706e 322
bogdanm 82:6473597d706e 323 /*
bogdanm 82:6473597d706e 324 * Constants & macros for individual SDHC_CMDARG bitfields
bogdanm 82:6473597d706e 325 */
bogdanm 82:6473597d706e 326
bogdanm 82:6473597d706e 327 /*!
bogdanm 82:6473597d706e 328 * @name Register SDHC_CMDARG, field CMDARG[31:0] (RW)
bogdanm 82:6473597d706e 329 *
bogdanm 82:6473597d706e 330 * The SD/MMC command argument is specified as bits 39-8 of the command format
bogdanm 82:6473597d706e 331 * in the SD or MMC specification. This register is write protected when
bogdanm 82:6473597d706e 332 * PRSSTAT[CDIHB0] is set.
bogdanm 82:6473597d706e 333 */
bogdanm 82:6473597d706e 334 //@{
bogdanm 82:6473597d706e 335 #define BP_SDHC_CMDARG_CMDARG (0U) //!< Bit position for SDHC_CMDARG_CMDARG.
bogdanm 82:6473597d706e 336 #define BM_SDHC_CMDARG_CMDARG (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDARG_CMDARG.
bogdanm 82:6473597d706e 337 #define BS_SDHC_CMDARG_CMDARG (32U) //!< Bit field size in bits for SDHC_CMDARG_CMDARG.
bogdanm 82:6473597d706e 338
bogdanm 82:6473597d706e 339 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 340 //! @brief Read current value of the SDHC_CMDARG_CMDARG field.
bogdanm 82:6473597d706e 341 #define BR_SDHC_CMDARG_CMDARG (HW_SDHC_CMDARG.U)
bogdanm 82:6473597d706e 342 #endif
bogdanm 82:6473597d706e 343
bogdanm 82:6473597d706e 344 //! @brief Format value for bitfield SDHC_CMDARG_CMDARG.
bogdanm 82:6473597d706e 345 #define BF_SDHC_CMDARG_CMDARG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_CMDARG_CMDARG), uint32_t) & BM_SDHC_CMDARG_CMDARG)
bogdanm 82:6473597d706e 346
bogdanm 82:6473597d706e 347 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 348 //! @brief Set the CMDARG field to a new value.
bogdanm 82:6473597d706e 349 #define BW_SDHC_CMDARG_CMDARG(v) (HW_SDHC_CMDARG_WR(v))
bogdanm 82:6473597d706e 350 #endif
bogdanm 82:6473597d706e 351 //@}
bogdanm 82:6473597d706e 352
bogdanm 82:6473597d706e 353 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 354 // HW_SDHC_XFERTYP - Transfer Type register
bogdanm 82:6473597d706e 355 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 356
bogdanm 82:6473597d706e 357 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 358 /*!
bogdanm 82:6473597d706e 359 * @brief HW_SDHC_XFERTYP - Transfer Type register (RW)
bogdanm 82:6473597d706e 360 *
bogdanm 82:6473597d706e 361 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 362 *
bogdanm 82:6473597d706e 363 * This register is used to control the operation of data transfers. The host
bogdanm 82:6473597d706e 364 * driver shall set this register before issuing a command followed by a data
bogdanm 82:6473597d706e 365 * transfer, or before issuing a resume command. To prevent data loss, the SDHC
bogdanm 82:6473597d706e 366 * prevents writing to the bits that are involved in the data transfer of this
bogdanm 82:6473597d706e 367 * register, when data transfer is active. These bits are DPSEL, MBSEL, DTDSEL, AC12EN,
bogdanm 82:6473597d706e 368 * BCEN, and DMAEN. The host driver shall check PRSSTAT[CDIHB] and PRSSTAT[CIHB]
bogdanm 82:6473597d706e 369 * before writing to this register. When PRSSTAT[CDIHB] is set, any attempt to
bogdanm 82:6473597d706e 370 * send a command with data by writing to this register is ignored; when
bogdanm 82:6473597d706e 371 * PRSSTAT[CIHB] bit is set, any write to this register is ignored. On sending commands with
bogdanm 82:6473597d706e 372 * data transfer involved, it is mandatory that the block size is nonzero.
bogdanm 82:6473597d706e 373 * Besides, block count must also be nonzero, or indicated as single block transfer
bogdanm 82:6473597d706e 374 * (bit 5 of this register is 0 when written), or block count is disabled (bit 1 of
bogdanm 82:6473597d706e 375 * this register is 0 when written), otherwise SDHC will ignore the sending of
bogdanm 82:6473597d706e 376 * this command and do nothing. For write command, with all above restrictions, it
bogdanm 82:6473597d706e 377 * is also mandatory that the write protect switch is not active (WPSPL bit of
bogdanm 82:6473597d706e 378 * Present State Register is 1), otherwise SDHC will also ignore the command. If
bogdanm 82:6473597d706e 379 * the commands with data transfer does not receive the response in 64 clock
bogdanm 82:6473597d706e 380 * cycles, that is, response time-out, SDHC will regard the external device does not
bogdanm 82:6473597d706e 381 * accept the command and abort the data transfer. In this scenario, the driver
bogdanm 82:6473597d706e 382 * must issue the command again to retry the transfer. It is also possible that,
bogdanm 82:6473597d706e 383 * for some reason, the card responds to the command but SDHC does not receive the
bogdanm 82:6473597d706e 384 * response, and if it is internal DMA (either simple DMA or ADMA) read
bogdanm 82:6473597d706e 385 * operation, the external system memory is over-written by the internal DMA with data
bogdanm 82:6473597d706e 386 * sent back from the card. The following table shows the summary of how register
bogdanm 82:6473597d706e 387 * settings determine the type of data transfer. Transfer Type register setting for
bogdanm 82:6473597d706e 388 * various transfer types Multi/Single block select Block count enable Block
bogdanm 82:6473597d706e 389 * count Function 0 Don't care Don't care Single transfer 1 0 Don't care Infinite
bogdanm 82:6473597d706e 390 * transfer 1 1 Positive number Multiple transfer 1 1 Zero No data transfer The
bogdanm 82:6473597d706e 391 * following table shows the relationship between XFERTYP[CICEN] and XFERTYP[CCCEN],
bogdanm 82:6473597d706e 392 * in regards to XFERTYP[RSPTYP] as well as the name of the response type.
bogdanm 82:6473597d706e 393 * Relationship between parameters and the name of the response type Response type
bogdanm 82:6473597d706e 394 * (RSPTYP) Index check enable (CICEN) CRC check enable (CCCEN) Name of response
bogdanm 82:6473597d706e 395 * type 00 0 0 No Response 01 0 1 IR2 10 0 0 R3,R4 10 1 1 R1,R5,R6 11 1 1 R1b,R5b In
bogdanm 82:6473597d706e 396 * the SDIO specification, response type notation for R5b is not defined. R5
bogdanm 82:6473597d706e 397 * includes R5b in the SDIO specification. But R5b is defined in this specification
bogdanm 82:6473597d706e 398 * to specify that the SDHC will check the busy status after receiving a
bogdanm 82:6473597d706e 399 * response. For example, usually CMD52 is used with R5, but the I/O abort command shall
bogdanm 82:6473597d706e 400 * be used with R5b. The CRC field for R3 and R4 is expected to be all 1 bits.
bogdanm 82:6473597d706e 401 * The CRC check shall be disabled for these response types.
bogdanm 82:6473597d706e 402 */
bogdanm 82:6473597d706e 403 typedef union _hw_sdhc_xfertyp
bogdanm 82:6473597d706e 404 {
bogdanm 82:6473597d706e 405 uint32_t U;
bogdanm 82:6473597d706e 406 struct _hw_sdhc_xfertyp_bitfields
bogdanm 82:6473597d706e 407 {
bogdanm 82:6473597d706e 408 uint32_t DMAEN : 1; //!< [0] DMA Enable
bogdanm 82:6473597d706e 409 uint32_t BCEN : 1; //!< [1] Block Count Enable
bogdanm 82:6473597d706e 410 uint32_t AC12EN : 1; //!< [2] Auto CMD12 Enable
bogdanm 82:6473597d706e 411 uint32_t RESERVED0 : 1; //!< [3]
bogdanm 82:6473597d706e 412 uint32_t DTDSEL : 1; //!< [4] Data Transfer Direction Select
bogdanm 82:6473597d706e 413 uint32_t MSBSEL : 1; //!< [5] Multi/Single Block Select
bogdanm 82:6473597d706e 414 uint32_t RESERVED1 : 10; //!< [15:6]
bogdanm 82:6473597d706e 415 uint32_t RSPTYP : 2; //!< [17:16] Response Type Select
bogdanm 82:6473597d706e 416 uint32_t RESERVED2 : 1; //!< [18]
bogdanm 82:6473597d706e 417 uint32_t CCCEN : 1; //!< [19] Command CRC Check Enable
bogdanm 82:6473597d706e 418 uint32_t CICEN : 1; //!< [20] Command Index Check Enable
bogdanm 82:6473597d706e 419 uint32_t DPSEL : 1; //!< [21] Data Present Select
bogdanm 82:6473597d706e 420 uint32_t CMDTYP : 2; //!< [23:22] Command Type
bogdanm 82:6473597d706e 421 uint32_t CMDINX : 6; //!< [29:24] Command Index
bogdanm 82:6473597d706e 422 uint32_t RESERVED3 : 2; //!< [31:30]
bogdanm 82:6473597d706e 423 } B;
bogdanm 82:6473597d706e 424 } hw_sdhc_xfertyp_t;
bogdanm 82:6473597d706e 425 #endif
bogdanm 82:6473597d706e 426
bogdanm 82:6473597d706e 427 /*!
bogdanm 82:6473597d706e 428 * @name Constants and macros for entire SDHC_XFERTYP register
bogdanm 82:6473597d706e 429 */
bogdanm 82:6473597d706e 430 //@{
bogdanm 82:6473597d706e 431 #define HW_SDHC_XFERTYP_ADDR (REGS_SDHC_BASE + 0xCU)
bogdanm 82:6473597d706e 432
bogdanm 82:6473597d706e 433 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 434 #define HW_SDHC_XFERTYP (*(__IO hw_sdhc_xfertyp_t *) HW_SDHC_XFERTYP_ADDR)
bogdanm 82:6473597d706e 435 #define HW_SDHC_XFERTYP_RD() (HW_SDHC_XFERTYP.U)
bogdanm 82:6473597d706e 436 #define HW_SDHC_XFERTYP_WR(v) (HW_SDHC_XFERTYP.U = (v))
bogdanm 82:6473597d706e 437 #define HW_SDHC_XFERTYP_SET(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() | (v)))
bogdanm 82:6473597d706e 438 #define HW_SDHC_XFERTYP_CLR(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() & ~(v)))
bogdanm 82:6473597d706e 439 #define HW_SDHC_XFERTYP_TOG(v) (HW_SDHC_XFERTYP_WR(HW_SDHC_XFERTYP_RD() ^ (v)))
bogdanm 82:6473597d706e 440 #endif
bogdanm 82:6473597d706e 441 //@}
bogdanm 82:6473597d706e 442
bogdanm 82:6473597d706e 443 /*
bogdanm 82:6473597d706e 444 * Constants & macros for individual SDHC_XFERTYP bitfields
bogdanm 82:6473597d706e 445 */
bogdanm 82:6473597d706e 446
bogdanm 82:6473597d706e 447 /*!
bogdanm 82:6473597d706e 448 * @name Register SDHC_XFERTYP, field DMAEN[0] (RW)
bogdanm 82:6473597d706e 449 *
bogdanm 82:6473597d706e 450 * Enables DMA functionality. If this bit is set to 1, a DMA operation shall
bogdanm 82:6473597d706e 451 * begin when the host driver sets the DPSEL bit of this register. Whether the
bogdanm 82:6473597d706e 452 * simple DMA, or the advanced DMA, is active depends on PROCTL[DMAS].
bogdanm 82:6473597d706e 453 *
bogdanm 82:6473597d706e 454 * Values:
bogdanm 82:6473597d706e 455 * - 0 - Disable
bogdanm 82:6473597d706e 456 * - 1 - Enable
bogdanm 82:6473597d706e 457 */
bogdanm 82:6473597d706e 458 //@{
bogdanm 82:6473597d706e 459 #define BP_SDHC_XFERTYP_DMAEN (0U) //!< Bit position for SDHC_XFERTYP_DMAEN.
bogdanm 82:6473597d706e 460 #define BM_SDHC_XFERTYP_DMAEN (0x00000001U) //!< Bit mask for SDHC_XFERTYP_DMAEN.
bogdanm 82:6473597d706e 461 #define BS_SDHC_XFERTYP_DMAEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_DMAEN.
bogdanm 82:6473597d706e 462
bogdanm 82:6473597d706e 463 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 464 //! @brief Read current value of the SDHC_XFERTYP_DMAEN field.
bogdanm 82:6473597d706e 465 #define BR_SDHC_XFERTYP_DMAEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DMAEN))
bogdanm 82:6473597d706e 466 #endif
bogdanm 82:6473597d706e 467
bogdanm 82:6473597d706e 468 //! @brief Format value for bitfield SDHC_XFERTYP_DMAEN.
bogdanm 82:6473597d706e 469 #define BF_SDHC_XFERTYP_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DMAEN), uint32_t) & BM_SDHC_XFERTYP_DMAEN)
bogdanm 82:6473597d706e 470
bogdanm 82:6473597d706e 471 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 472 //! @brief Set the DMAEN field to a new value.
bogdanm 82:6473597d706e 473 #define BW_SDHC_XFERTYP_DMAEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DMAEN) = (v))
bogdanm 82:6473597d706e 474 #endif
bogdanm 82:6473597d706e 475 //@}
bogdanm 82:6473597d706e 476
bogdanm 82:6473597d706e 477 /*!
bogdanm 82:6473597d706e 478 * @name Register SDHC_XFERTYP, field BCEN[1] (RW)
bogdanm 82:6473597d706e 479 *
bogdanm 82:6473597d706e 480 * Used to enable the Block Count register, which is only relevant for multiple
bogdanm 82:6473597d706e 481 * block transfers. When this bit is 0, the internal counter for block is
bogdanm 82:6473597d706e 482 * disabled, which is useful in executing an infinite transfer.
bogdanm 82:6473597d706e 483 *
bogdanm 82:6473597d706e 484 * Values:
bogdanm 82:6473597d706e 485 * - 0 - Disable
bogdanm 82:6473597d706e 486 * - 1 - Enable
bogdanm 82:6473597d706e 487 */
bogdanm 82:6473597d706e 488 //@{
bogdanm 82:6473597d706e 489 #define BP_SDHC_XFERTYP_BCEN (1U) //!< Bit position for SDHC_XFERTYP_BCEN.
bogdanm 82:6473597d706e 490 #define BM_SDHC_XFERTYP_BCEN (0x00000002U) //!< Bit mask for SDHC_XFERTYP_BCEN.
bogdanm 82:6473597d706e 491 #define BS_SDHC_XFERTYP_BCEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_BCEN.
bogdanm 82:6473597d706e 492
bogdanm 82:6473597d706e 493 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 494 //! @brief Read current value of the SDHC_XFERTYP_BCEN field.
bogdanm 82:6473597d706e 495 #define BR_SDHC_XFERTYP_BCEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_BCEN))
bogdanm 82:6473597d706e 496 #endif
bogdanm 82:6473597d706e 497
bogdanm 82:6473597d706e 498 //! @brief Format value for bitfield SDHC_XFERTYP_BCEN.
bogdanm 82:6473597d706e 499 #define BF_SDHC_XFERTYP_BCEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_BCEN), uint32_t) & BM_SDHC_XFERTYP_BCEN)
bogdanm 82:6473597d706e 500
bogdanm 82:6473597d706e 501 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 502 //! @brief Set the BCEN field to a new value.
bogdanm 82:6473597d706e 503 #define BW_SDHC_XFERTYP_BCEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_BCEN) = (v))
bogdanm 82:6473597d706e 504 #endif
bogdanm 82:6473597d706e 505 //@}
bogdanm 82:6473597d706e 506
bogdanm 82:6473597d706e 507 /*!
bogdanm 82:6473597d706e 508 * @name Register SDHC_XFERTYP, field AC12EN[2] (RW)
bogdanm 82:6473597d706e 509 *
bogdanm 82:6473597d706e 510 * Multiple block transfers for memory require a CMD12 to stop the transaction.
bogdanm 82:6473597d706e 511 * When this bit is set to 1, the SDHC will issue a CMD12 automatically when the
bogdanm 82:6473597d706e 512 * last block transfer has completed. The host driver shall not set this bit to
bogdanm 82:6473597d706e 513 * issue commands that do not require CMD12 to stop a multiple block data
bogdanm 82:6473597d706e 514 * transfer. In particular, secure commands defined in File Security Specification (see
bogdanm 82:6473597d706e 515 * reference list) do not require CMD12. In single block transfer, the SDHC will
bogdanm 82:6473597d706e 516 * ignore this bit whether it is set or not.
bogdanm 82:6473597d706e 517 *
bogdanm 82:6473597d706e 518 * Values:
bogdanm 82:6473597d706e 519 * - 0 - Disable
bogdanm 82:6473597d706e 520 * - 1 - Enable
bogdanm 82:6473597d706e 521 */
bogdanm 82:6473597d706e 522 //@{
bogdanm 82:6473597d706e 523 #define BP_SDHC_XFERTYP_AC12EN (2U) //!< Bit position for SDHC_XFERTYP_AC12EN.
bogdanm 82:6473597d706e 524 #define BM_SDHC_XFERTYP_AC12EN (0x00000004U) //!< Bit mask for SDHC_XFERTYP_AC12EN.
bogdanm 82:6473597d706e 525 #define BS_SDHC_XFERTYP_AC12EN (1U) //!< Bit field size in bits for SDHC_XFERTYP_AC12EN.
bogdanm 82:6473597d706e 526
bogdanm 82:6473597d706e 527 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 528 //! @brief Read current value of the SDHC_XFERTYP_AC12EN field.
bogdanm 82:6473597d706e 529 #define BR_SDHC_XFERTYP_AC12EN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_AC12EN))
bogdanm 82:6473597d706e 530 #endif
bogdanm 82:6473597d706e 531
bogdanm 82:6473597d706e 532 //! @brief Format value for bitfield SDHC_XFERTYP_AC12EN.
bogdanm 82:6473597d706e 533 #define BF_SDHC_XFERTYP_AC12EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_AC12EN), uint32_t) & BM_SDHC_XFERTYP_AC12EN)
bogdanm 82:6473597d706e 534
bogdanm 82:6473597d706e 535 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 536 //! @brief Set the AC12EN field to a new value.
bogdanm 82:6473597d706e 537 #define BW_SDHC_XFERTYP_AC12EN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_AC12EN) = (v))
bogdanm 82:6473597d706e 538 #endif
bogdanm 82:6473597d706e 539 //@}
bogdanm 82:6473597d706e 540
bogdanm 82:6473597d706e 541 /*!
bogdanm 82:6473597d706e 542 * @name Register SDHC_XFERTYP, field DTDSEL[4] (RW)
bogdanm 82:6473597d706e 543 *
bogdanm 82:6473597d706e 544 * Defines the direction of DAT line data transfers. The bit is set to 1 by the
bogdanm 82:6473597d706e 545 * host driver to transfer data from the SD card to the SDHC and is set to 0 for
bogdanm 82:6473597d706e 546 * all other commands.
bogdanm 82:6473597d706e 547 *
bogdanm 82:6473597d706e 548 * Values:
bogdanm 82:6473597d706e 549 * - 0 - Write host to card.
bogdanm 82:6473597d706e 550 * - 1 - Read card to host.
bogdanm 82:6473597d706e 551 */
bogdanm 82:6473597d706e 552 //@{
bogdanm 82:6473597d706e 553 #define BP_SDHC_XFERTYP_DTDSEL (4U) //!< Bit position for SDHC_XFERTYP_DTDSEL.
bogdanm 82:6473597d706e 554 #define BM_SDHC_XFERTYP_DTDSEL (0x00000010U) //!< Bit mask for SDHC_XFERTYP_DTDSEL.
bogdanm 82:6473597d706e 555 #define BS_SDHC_XFERTYP_DTDSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_DTDSEL.
bogdanm 82:6473597d706e 556
bogdanm 82:6473597d706e 557 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 558 //! @brief Read current value of the SDHC_XFERTYP_DTDSEL field.
bogdanm 82:6473597d706e 559 #define BR_SDHC_XFERTYP_DTDSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DTDSEL))
bogdanm 82:6473597d706e 560 #endif
bogdanm 82:6473597d706e 561
bogdanm 82:6473597d706e 562 //! @brief Format value for bitfield SDHC_XFERTYP_DTDSEL.
bogdanm 82:6473597d706e 563 #define BF_SDHC_XFERTYP_DTDSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DTDSEL), uint32_t) & BM_SDHC_XFERTYP_DTDSEL)
bogdanm 82:6473597d706e 564
bogdanm 82:6473597d706e 565 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 566 //! @brief Set the DTDSEL field to a new value.
bogdanm 82:6473597d706e 567 #define BW_SDHC_XFERTYP_DTDSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DTDSEL) = (v))
bogdanm 82:6473597d706e 568 #endif
bogdanm 82:6473597d706e 569 //@}
bogdanm 82:6473597d706e 570
bogdanm 82:6473597d706e 571 /*!
bogdanm 82:6473597d706e 572 * @name Register SDHC_XFERTYP, field MSBSEL[5] (RW)
bogdanm 82:6473597d706e 573 *
bogdanm 82:6473597d706e 574 * Enables multiple block DAT line data transfers. For any other commands, this
bogdanm 82:6473597d706e 575 * bit shall be set to 0. If this bit is 0, it is not necessary to set the block
bogdanm 82:6473597d706e 576 * count register.
bogdanm 82:6473597d706e 577 *
bogdanm 82:6473597d706e 578 * Values:
bogdanm 82:6473597d706e 579 * - 0 - Single block.
bogdanm 82:6473597d706e 580 * - 1 - Multiple blocks.
bogdanm 82:6473597d706e 581 */
bogdanm 82:6473597d706e 582 //@{
bogdanm 82:6473597d706e 583 #define BP_SDHC_XFERTYP_MSBSEL (5U) //!< Bit position for SDHC_XFERTYP_MSBSEL.
bogdanm 82:6473597d706e 584 #define BM_SDHC_XFERTYP_MSBSEL (0x00000020U) //!< Bit mask for SDHC_XFERTYP_MSBSEL.
bogdanm 82:6473597d706e 585 #define BS_SDHC_XFERTYP_MSBSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_MSBSEL.
bogdanm 82:6473597d706e 586
bogdanm 82:6473597d706e 587 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 588 //! @brief Read current value of the SDHC_XFERTYP_MSBSEL field.
bogdanm 82:6473597d706e 589 #define BR_SDHC_XFERTYP_MSBSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_MSBSEL))
bogdanm 82:6473597d706e 590 #endif
bogdanm 82:6473597d706e 591
bogdanm 82:6473597d706e 592 //! @brief Format value for bitfield SDHC_XFERTYP_MSBSEL.
bogdanm 82:6473597d706e 593 #define BF_SDHC_XFERTYP_MSBSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_MSBSEL), uint32_t) & BM_SDHC_XFERTYP_MSBSEL)
bogdanm 82:6473597d706e 594
bogdanm 82:6473597d706e 595 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 596 //! @brief Set the MSBSEL field to a new value.
bogdanm 82:6473597d706e 597 #define BW_SDHC_XFERTYP_MSBSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_MSBSEL) = (v))
bogdanm 82:6473597d706e 598 #endif
bogdanm 82:6473597d706e 599 //@}
bogdanm 82:6473597d706e 600
bogdanm 82:6473597d706e 601 /*!
bogdanm 82:6473597d706e 602 * @name Register SDHC_XFERTYP, field RSPTYP[17:16] (RW)
bogdanm 82:6473597d706e 603 *
bogdanm 82:6473597d706e 604 * Values:
bogdanm 82:6473597d706e 605 * - 00 - No response.
bogdanm 82:6473597d706e 606 * - 01 - Response length 136.
bogdanm 82:6473597d706e 607 * - 10 - Response length 48.
bogdanm 82:6473597d706e 608 * - 11 - Response length 48, check busy after response.
bogdanm 82:6473597d706e 609 */
bogdanm 82:6473597d706e 610 //@{
bogdanm 82:6473597d706e 611 #define BP_SDHC_XFERTYP_RSPTYP (16U) //!< Bit position for SDHC_XFERTYP_RSPTYP.
bogdanm 82:6473597d706e 612 #define BM_SDHC_XFERTYP_RSPTYP (0x00030000U) //!< Bit mask for SDHC_XFERTYP_RSPTYP.
bogdanm 82:6473597d706e 613 #define BS_SDHC_XFERTYP_RSPTYP (2U) //!< Bit field size in bits for SDHC_XFERTYP_RSPTYP.
bogdanm 82:6473597d706e 614
bogdanm 82:6473597d706e 615 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 616 //! @brief Read current value of the SDHC_XFERTYP_RSPTYP field.
bogdanm 82:6473597d706e 617 #define BR_SDHC_XFERTYP_RSPTYP (HW_SDHC_XFERTYP.B.RSPTYP)
bogdanm 82:6473597d706e 618 #endif
bogdanm 82:6473597d706e 619
bogdanm 82:6473597d706e 620 //! @brief Format value for bitfield SDHC_XFERTYP_RSPTYP.
bogdanm 82:6473597d706e 621 #define BF_SDHC_XFERTYP_RSPTYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_RSPTYP), uint32_t) & BM_SDHC_XFERTYP_RSPTYP)
bogdanm 82:6473597d706e 622
bogdanm 82:6473597d706e 623 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 624 //! @brief Set the RSPTYP field to a new value.
bogdanm 82:6473597d706e 625 #define BW_SDHC_XFERTYP_RSPTYP(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_RSPTYP) | BF_SDHC_XFERTYP_RSPTYP(v)))
bogdanm 82:6473597d706e 626 #endif
bogdanm 82:6473597d706e 627 //@}
bogdanm 82:6473597d706e 628
bogdanm 82:6473597d706e 629 /*!
bogdanm 82:6473597d706e 630 * @name Register SDHC_XFERTYP, field CCCEN[19] (RW)
bogdanm 82:6473597d706e 631 *
bogdanm 82:6473597d706e 632 * If this bit is set to 1, the SDHC shall check the CRC field in the response.
bogdanm 82:6473597d706e 633 * If an error is detected, it is reported as a Command CRC Error. If this bit is
bogdanm 82:6473597d706e 634 * set to 0, the CRC field is not checked. The number of bits checked by the CRC
bogdanm 82:6473597d706e 635 * field value changes according to the length of the response.
bogdanm 82:6473597d706e 636 *
bogdanm 82:6473597d706e 637 * Values:
bogdanm 82:6473597d706e 638 * - 0 - Disable
bogdanm 82:6473597d706e 639 * - 1 - Enable
bogdanm 82:6473597d706e 640 */
bogdanm 82:6473597d706e 641 //@{
bogdanm 82:6473597d706e 642 #define BP_SDHC_XFERTYP_CCCEN (19U) //!< Bit position for SDHC_XFERTYP_CCCEN.
bogdanm 82:6473597d706e 643 #define BM_SDHC_XFERTYP_CCCEN (0x00080000U) //!< Bit mask for SDHC_XFERTYP_CCCEN.
bogdanm 82:6473597d706e 644 #define BS_SDHC_XFERTYP_CCCEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_CCCEN.
bogdanm 82:6473597d706e 645
bogdanm 82:6473597d706e 646 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 647 //! @brief Read current value of the SDHC_XFERTYP_CCCEN field.
bogdanm 82:6473597d706e 648 #define BR_SDHC_XFERTYP_CCCEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CCCEN))
bogdanm 82:6473597d706e 649 #endif
bogdanm 82:6473597d706e 650
bogdanm 82:6473597d706e 651 //! @brief Format value for bitfield SDHC_XFERTYP_CCCEN.
bogdanm 82:6473597d706e 652 #define BF_SDHC_XFERTYP_CCCEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CCCEN), uint32_t) & BM_SDHC_XFERTYP_CCCEN)
bogdanm 82:6473597d706e 653
bogdanm 82:6473597d706e 654 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 655 //! @brief Set the CCCEN field to a new value.
bogdanm 82:6473597d706e 656 #define BW_SDHC_XFERTYP_CCCEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CCCEN) = (v))
bogdanm 82:6473597d706e 657 #endif
bogdanm 82:6473597d706e 658 //@}
bogdanm 82:6473597d706e 659
bogdanm 82:6473597d706e 660 /*!
bogdanm 82:6473597d706e 661 * @name Register SDHC_XFERTYP, field CICEN[20] (RW)
bogdanm 82:6473597d706e 662 *
bogdanm 82:6473597d706e 663 * If this bit is set to 1, the SDHC will check the index field in the response
bogdanm 82:6473597d706e 664 * to see if it has the same value as the command index. If it is not, it is
bogdanm 82:6473597d706e 665 * reported as a command index error. If this bit is set to 0, the index field is not
bogdanm 82:6473597d706e 666 * checked.
bogdanm 82:6473597d706e 667 *
bogdanm 82:6473597d706e 668 * Values:
bogdanm 82:6473597d706e 669 * - 0 - Disable
bogdanm 82:6473597d706e 670 * - 1 - Enable
bogdanm 82:6473597d706e 671 */
bogdanm 82:6473597d706e 672 //@{
bogdanm 82:6473597d706e 673 #define BP_SDHC_XFERTYP_CICEN (20U) //!< Bit position for SDHC_XFERTYP_CICEN.
bogdanm 82:6473597d706e 674 #define BM_SDHC_XFERTYP_CICEN (0x00100000U) //!< Bit mask for SDHC_XFERTYP_CICEN.
bogdanm 82:6473597d706e 675 #define BS_SDHC_XFERTYP_CICEN (1U) //!< Bit field size in bits for SDHC_XFERTYP_CICEN.
bogdanm 82:6473597d706e 676
bogdanm 82:6473597d706e 677 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 678 //! @brief Read current value of the SDHC_XFERTYP_CICEN field.
bogdanm 82:6473597d706e 679 #define BR_SDHC_XFERTYP_CICEN (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CICEN))
bogdanm 82:6473597d706e 680 #endif
bogdanm 82:6473597d706e 681
bogdanm 82:6473597d706e 682 //! @brief Format value for bitfield SDHC_XFERTYP_CICEN.
bogdanm 82:6473597d706e 683 #define BF_SDHC_XFERTYP_CICEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CICEN), uint32_t) & BM_SDHC_XFERTYP_CICEN)
bogdanm 82:6473597d706e 684
bogdanm 82:6473597d706e 685 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 686 //! @brief Set the CICEN field to a new value.
bogdanm 82:6473597d706e 687 #define BW_SDHC_XFERTYP_CICEN(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_CICEN) = (v))
bogdanm 82:6473597d706e 688 #endif
bogdanm 82:6473597d706e 689 //@}
bogdanm 82:6473597d706e 690
bogdanm 82:6473597d706e 691 /*!
bogdanm 82:6473597d706e 692 * @name Register SDHC_XFERTYP, field DPSEL[21] (RW)
bogdanm 82:6473597d706e 693 *
bogdanm 82:6473597d706e 694 * This bit is set to 1 to indicate that data is present and shall be
bogdanm 82:6473597d706e 695 * transferred using the DAT line. It is set to 0 for the following: Commands using only
bogdanm 82:6473597d706e 696 * the CMD line, for example: CMD52. Commands with no data transfer, but using the
bogdanm 82:6473597d706e 697 * busy signal on DAT[0] line, R1b or R5b, for example: CMD38. In resume command,
bogdanm 82:6473597d706e 698 * this bit shall be set, and other bits in this register shall be set the same
bogdanm 82:6473597d706e 699 * as when the transfer was initially launched. When the Write Protect switch is
bogdanm 82:6473597d706e 700 * on, that is, the WPSPL bit is active as 0, any command with a write operation
bogdanm 82:6473597d706e 701 * will be ignored. That is to say, when this bit is set, while the DTDSEL bit is
bogdanm 82:6473597d706e 702 * 0, writes to the register Transfer Type are ignored.
bogdanm 82:6473597d706e 703 *
bogdanm 82:6473597d706e 704 * Values:
bogdanm 82:6473597d706e 705 * - 0 - No data present.
bogdanm 82:6473597d706e 706 * - 1 - Data present.
bogdanm 82:6473597d706e 707 */
bogdanm 82:6473597d706e 708 //@{
bogdanm 82:6473597d706e 709 #define BP_SDHC_XFERTYP_DPSEL (21U) //!< Bit position for SDHC_XFERTYP_DPSEL.
bogdanm 82:6473597d706e 710 #define BM_SDHC_XFERTYP_DPSEL (0x00200000U) //!< Bit mask for SDHC_XFERTYP_DPSEL.
bogdanm 82:6473597d706e 711 #define BS_SDHC_XFERTYP_DPSEL (1U) //!< Bit field size in bits for SDHC_XFERTYP_DPSEL.
bogdanm 82:6473597d706e 712
bogdanm 82:6473597d706e 713 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 714 //! @brief Read current value of the SDHC_XFERTYP_DPSEL field.
bogdanm 82:6473597d706e 715 #define BR_SDHC_XFERTYP_DPSEL (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DPSEL))
bogdanm 82:6473597d706e 716 #endif
bogdanm 82:6473597d706e 717
bogdanm 82:6473597d706e 718 //! @brief Format value for bitfield SDHC_XFERTYP_DPSEL.
bogdanm 82:6473597d706e 719 #define BF_SDHC_XFERTYP_DPSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_DPSEL), uint32_t) & BM_SDHC_XFERTYP_DPSEL)
bogdanm 82:6473597d706e 720
bogdanm 82:6473597d706e 721 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 722 //! @brief Set the DPSEL field to a new value.
bogdanm 82:6473597d706e 723 #define BW_SDHC_XFERTYP_DPSEL(v) (BITBAND_ACCESS32(HW_SDHC_XFERTYP_ADDR, BP_SDHC_XFERTYP_DPSEL) = (v))
bogdanm 82:6473597d706e 724 #endif
bogdanm 82:6473597d706e 725 //@}
bogdanm 82:6473597d706e 726
bogdanm 82:6473597d706e 727 /*!
bogdanm 82:6473597d706e 728 * @name Register SDHC_XFERTYP, field CMDTYP[23:22] (RW)
bogdanm 82:6473597d706e 729 *
bogdanm 82:6473597d706e 730 * There are three types of special commands: suspend, resume, and abort. These
bogdanm 82:6473597d706e 731 * bits shall be set to 00b for all other commands. Suspend command: If the
bogdanm 82:6473597d706e 732 * suspend command succeeds, the SDHC shall assume that the card bus has been released
bogdanm 82:6473597d706e 733 * and that it is possible to issue the next command which uses the DAT line.
bogdanm 82:6473597d706e 734 * Because the SDHC does not monitor the content of command response, it does not
bogdanm 82:6473597d706e 735 * know if the suspend command succeeded or not. It is the host driver's
bogdanm 82:6473597d706e 736 * responsibility to check the status of the suspend command and send another command
bogdanm 82:6473597d706e 737 * marked as suspend to inform the SDHC that a suspend command was successfully
bogdanm 82:6473597d706e 738 * issued. After the end bit of command is sent, the SDHC deasserts read wait for read
bogdanm 82:6473597d706e 739 * transactions and stops checking busy for write transactions. In 4-bit mode,
bogdanm 82:6473597d706e 740 * the interrupt cycle starts. If the suspend command fails, the SDHC will
bogdanm 82:6473597d706e 741 * maintain its current state, and the host driver shall restart the transfer by setting
bogdanm 82:6473597d706e 742 * PROCTL[CREQ]. Resume command: The host driver restarts the data transfer by
bogdanm 82:6473597d706e 743 * restoring the registers saved before sending the suspend command and then sends
bogdanm 82:6473597d706e 744 * the resume command. The SDHC will check for a pending busy state before
bogdanm 82:6473597d706e 745 * starting write transfers. Abort command: If this command is set when executing a
bogdanm 82:6473597d706e 746 * read transfer, the SDHC will stop reads to the buffer. If this command is set
bogdanm 82:6473597d706e 747 * when executing a write transfer, the SDHC will stop driving the DAT line. After
bogdanm 82:6473597d706e 748 * issuing the abort command, the host driver must issue a software reset (abort
bogdanm 82:6473597d706e 749 * transaction).
bogdanm 82:6473597d706e 750 *
bogdanm 82:6473597d706e 751 * Values:
bogdanm 82:6473597d706e 752 * - 00 - Normal other commands.
bogdanm 82:6473597d706e 753 * - 01 - Suspend CMD52 for writing bus suspend in CCCR.
bogdanm 82:6473597d706e 754 * - 10 - Resume CMD52 for writing function select in CCCR.
bogdanm 82:6473597d706e 755 * - 11 - Abort CMD12, CMD52 for writing I/O abort in CCCR.
bogdanm 82:6473597d706e 756 */
bogdanm 82:6473597d706e 757 //@{
bogdanm 82:6473597d706e 758 #define BP_SDHC_XFERTYP_CMDTYP (22U) //!< Bit position for SDHC_XFERTYP_CMDTYP.
bogdanm 82:6473597d706e 759 #define BM_SDHC_XFERTYP_CMDTYP (0x00C00000U) //!< Bit mask for SDHC_XFERTYP_CMDTYP.
bogdanm 82:6473597d706e 760 #define BS_SDHC_XFERTYP_CMDTYP (2U) //!< Bit field size in bits for SDHC_XFERTYP_CMDTYP.
bogdanm 82:6473597d706e 761
bogdanm 82:6473597d706e 762 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 763 //! @brief Read current value of the SDHC_XFERTYP_CMDTYP field.
bogdanm 82:6473597d706e 764 #define BR_SDHC_XFERTYP_CMDTYP (HW_SDHC_XFERTYP.B.CMDTYP)
bogdanm 82:6473597d706e 765 #endif
bogdanm 82:6473597d706e 766
bogdanm 82:6473597d706e 767 //! @brief Format value for bitfield SDHC_XFERTYP_CMDTYP.
bogdanm 82:6473597d706e 768 #define BF_SDHC_XFERTYP_CMDTYP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CMDTYP), uint32_t) & BM_SDHC_XFERTYP_CMDTYP)
bogdanm 82:6473597d706e 769
bogdanm 82:6473597d706e 770 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 771 //! @brief Set the CMDTYP field to a new value.
bogdanm 82:6473597d706e 772 #define BW_SDHC_XFERTYP_CMDTYP(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_CMDTYP) | BF_SDHC_XFERTYP_CMDTYP(v)))
bogdanm 82:6473597d706e 773 #endif
bogdanm 82:6473597d706e 774 //@}
bogdanm 82:6473597d706e 775
bogdanm 82:6473597d706e 776 /*!
bogdanm 82:6473597d706e 777 * @name Register SDHC_XFERTYP, field CMDINX[29:24] (RW)
bogdanm 82:6473597d706e 778 *
bogdanm 82:6473597d706e 779 * These bits shall be set to the command number that is specified in bits 45-40
bogdanm 82:6473597d706e 780 * of the command-format in the SD Memory Card Physical Layer Specification and
bogdanm 82:6473597d706e 781 * SDIO Card Specification.
bogdanm 82:6473597d706e 782 */
bogdanm 82:6473597d706e 783 //@{
bogdanm 82:6473597d706e 784 #define BP_SDHC_XFERTYP_CMDINX (24U) //!< Bit position for SDHC_XFERTYP_CMDINX.
bogdanm 82:6473597d706e 785 #define BM_SDHC_XFERTYP_CMDINX (0x3F000000U) //!< Bit mask for SDHC_XFERTYP_CMDINX.
bogdanm 82:6473597d706e 786 #define BS_SDHC_XFERTYP_CMDINX (6U) //!< Bit field size in bits for SDHC_XFERTYP_CMDINX.
bogdanm 82:6473597d706e 787
bogdanm 82:6473597d706e 788 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 789 //! @brief Read current value of the SDHC_XFERTYP_CMDINX field.
bogdanm 82:6473597d706e 790 #define BR_SDHC_XFERTYP_CMDINX (HW_SDHC_XFERTYP.B.CMDINX)
bogdanm 82:6473597d706e 791 #endif
bogdanm 82:6473597d706e 792
bogdanm 82:6473597d706e 793 //! @brief Format value for bitfield SDHC_XFERTYP_CMDINX.
bogdanm 82:6473597d706e 794 #define BF_SDHC_XFERTYP_CMDINX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_XFERTYP_CMDINX), uint32_t) & BM_SDHC_XFERTYP_CMDINX)
bogdanm 82:6473597d706e 795
bogdanm 82:6473597d706e 796 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 797 //! @brief Set the CMDINX field to a new value.
bogdanm 82:6473597d706e 798 #define BW_SDHC_XFERTYP_CMDINX(v) (HW_SDHC_XFERTYP_WR((HW_SDHC_XFERTYP_RD() & ~BM_SDHC_XFERTYP_CMDINX) | BF_SDHC_XFERTYP_CMDINX(v)))
bogdanm 82:6473597d706e 799 #endif
bogdanm 82:6473597d706e 800 //@}
bogdanm 82:6473597d706e 801
bogdanm 82:6473597d706e 802 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 803 // HW_SDHC_CMDRSP0 - Command Response 0
bogdanm 82:6473597d706e 804 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 805
bogdanm 82:6473597d706e 806 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 807 /*!
bogdanm 82:6473597d706e 808 * @brief HW_SDHC_CMDRSP0 - Command Response 0 (RO)
bogdanm 82:6473597d706e 809 *
bogdanm 82:6473597d706e 810 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 811 *
bogdanm 82:6473597d706e 812 * This register is used to store part 0 of the response bits from the card.
bogdanm 82:6473597d706e 813 */
bogdanm 82:6473597d706e 814 typedef union _hw_sdhc_cmdrsp0
bogdanm 82:6473597d706e 815 {
bogdanm 82:6473597d706e 816 uint32_t U;
bogdanm 82:6473597d706e 817 struct _hw_sdhc_cmdrsp0_bitfields
bogdanm 82:6473597d706e 818 {
bogdanm 82:6473597d706e 819 uint32_t CMDRSP0 : 32; //!< [31:0] Command Response 0
bogdanm 82:6473597d706e 820 } B;
bogdanm 82:6473597d706e 821 } hw_sdhc_cmdrsp0_t;
bogdanm 82:6473597d706e 822 #endif
bogdanm 82:6473597d706e 823
bogdanm 82:6473597d706e 824 /*!
bogdanm 82:6473597d706e 825 * @name Constants and macros for entire SDHC_CMDRSP0 register
bogdanm 82:6473597d706e 826 */
bogdanm 82:6473597d706e 827 //@{
bogdanm 82:6473597d706e 828 #define HW_SDHC_CMDRSP0_ADDR (REGS_SDHC_BASE + 0x10U)
bogdanm 82:6473597d706e 829
bogdanm 82:6473597d706e 830 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 831 #define HW_SDHC_CMDRSP0 (*(__I hw_sdhc_cmdrsp0_t *) HW_SDHC_CMDRSP0_ADDR)
bogdanm 82:6473597d706e 832 #define HW_SDHC_CMDRSP0_RD() (HW_SDHC_CMDRSP0.U)
bogdanm 82:6473597d706e 833 #endif
bogdanm 82:6473597d706e 834 //@}
bogdanm 82:6473597d706e 835
bogdanm 82:6473597d706e 836 /*
bogdanm 82:6473597d706e 837 * Constants & macros for individual SDHC_CMDRSP0 bitfields
bogdanm 82:6473597d706e 838 */
bogdanm 82:6473597d706e 839
bogdanm 82:6473597d706e 840 /*!
bogdanm 82:6473597d706e 841 * @name Register SDHC_CMDRSP0, field CMDRSP0[31:0] (RO)
bogdanm 82:6473597d706e 842 */
bogdanm 82:6473597d706e 843 //@{
bogdanm 82:6473597d706e 844 #define BP_SDHC_CMDRSP0_CMDRSP0 (0U) //!< Bit position for SDHC_CMDRSP0_CMDRSP0.
bogdanm 82:6473597d706e 845 #define BM_SDHC_CMDRSP0_CMDRSP0 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP0_CMDRSP0.
bogdanm 82:6473597d706e 846 #define BS_SDHC_CMDRSP0_CMDRSP0 (32U) //!< Bit field size in bits for SDHC_CMDRSP0_CMDRSP0.
bogdanm 82:6473597d706e 847
bogdanm 82:6473597d706e 848 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 849 //! @brief Read current value of the SDHC_CMDRSP0_CMDRSP0 field.
bogdanm 82:6473597d706e 850 #define BR_SDHC_CMDRSP0_CMDRSP0 (HW_SDHC_CMDRSP0.U)
bogdanm 82:6473597d706e 851 #endif
bogdanm 82:6473597d706e 852 //@}
bogdanm 82:6473597d706e 853
bogdanm 82:6473597d706e 854 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 855 // HW_SDHC_CMDRSP1 - Command Response 1
bogdanm 82:6473597d706e 856 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 857
bogdanm 82:6473597d706e 858 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 859 /*!
bogdanm 82:6473597d706e 860 * @brief HW_SDHC_CMDRSP1 - Command Response 1 (RO)
bogdanm 82:6473597d706e 861 *
bogdanm 82:6473597d706e 862 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 863 *
bogdanm 82:6473597d706e 864 * This register is used to store part 1 of the response bits from the card.
bogdanm 82:6473597d706e 865 */
bogdanm 82:6473597d706e 866 typedef union _hw_sdhc_cmdrsp1
bogdanm 82:6473597d706e 867 {
bogdanm 82:6473597d706e 868 uint32_t U;
bogdanm 82:6473597d706e 869 struct _hw_sdhc_cmdrsp1_bitfields
bogdanm 82:6473597d706e 870 {
bogdanm 82:6473597d706e 871 uint32_t CMDRSP1 : 32; //!< [31:0] Command Response 1
bogdanm 82:6473597d706e 872 } B;
bogdanm 82:6473597d706e 873 } hw_sdhc_cmdrsp1_t;
bogdanm 82:6473597d706e 874 #endif
bogdanm 82:6473597d706e 875
bogdanm 82:6473597d706e 876 /*!
bogdanm 82:6473597d706e 877 * @name Constants and macros for entire SDHC_CMDRSP1 register
bogdanm 82:6473597d706e 878 */
bogdanm 82:6473597d706e 879 //@{
bogdanm 82:6473597d706e 880 #define HW_SDHC_CMDRSP1_ADDR (REGS_SDHC_BASE + 0x14U)
bogdanm 82:6473597d706e 881
bogdanm 82:6473597d706e 882 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 883 #define HW_SDHC_CMDRSP1 (*(__I hw_sdhc_cmdrsp1_t *) HW_SDHC_CMDRSP1_ADDR)
bogdanm 82:6473597d706e 884 #define HW_SDHC_CMDRSP1_RD() (HW_SDHC_CMDRSP1.U)
bogdanm 82:6473597d706e 885 #endif
bogdanm 82:6473597d706e 886 //@}
bogdanm 82:6473597d706e 887
bogdanm 82:6473597d706e 888 /*
bogdanm 82:6473597d706e 889 * Constants & macros for individual SDHC_CMDRSP1 bitfields
bogdanm 82:6473597d706e 890 */
bogdanm 82:6473597d706e 891
bogdanm 82:6473597d706e 892 /*!
bogdanm 82:6473597d706e 893 * @name Register SDHC_CMDRSP1, field CMDRSP1[31:0] (RO)
bogdanm 82:6473597d706e 894 */
bogdanm 82:6473597d706e 895 //@{
bogdanm 82:6473597d706e 896 #define BP_SDHC_CMDRSP1_CMDRSP1 (0U) //!< Bit position for SDHC_CMDRSP1_CMDRSP1.
bogdanm 82:6473597d706e 897 #define BM_SDHC_CMDRSP1_CMDRSP1 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP1_CMDRSP1.
bogdanm 82:6473597d706e 898 #define BS_SDHC_CMDRSP1_CMDRSP1 (32U) //!< Bit field size in bits for SDHC_CMDRSP1_CMDRSP1.
bogdanm 82:6473597d706e 899
bogdanm 82:6473597d706e 900 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 901 //! @brief Read current value of the SDHC_CMDRSP1_CMDRSP1 field.
bogdanm 82:6473597d706e 902 #define BR_SDHC_CMDRSP1_CMDRSP1 (HW_SDHC_CMDRSP1.U)
bogdanm 82:6473597d706e 903 #endif
bogdanm 82:6473597d706e 904 //@}
bogdanm 82:6473597d706e 905
bogdanm 82:6473597d706e 906 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 907 // HW_SDHC_CMDRSP2 - Command Response 2
bogdanm 82:6473597d706e 908 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 909
bogdanm 82:6473597d706e 910 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 911 /*!
bogdanm 82:6473597d706e 912 * @brief HW_SDHC_CMDRSP2 - Command Response 2 (RO)
bogdanm 82:6473597d706e 913 *
bogdanm 82:6473597d706e 914 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 915 *
bogdanm 82:6473597d706e 916 * This register is used to store part 2 of the response bits from the card.
bogdanm 82:6473597d706e 917 */
bogdanm 82:6473597d706e 918 typedef union _hw_sdhc_cmdrsp2
bogdanm 82:6473597d706e 919 {
bogdanm 82:6473597d706e 920 uint32_t U;
bogdanm 82:6473597d706e 921 struct _hw_sdhc_cmdrsp2_bitfields
bogdanm 82:6473597d706e 922 {
bogdanm 82:6473597d706e 923 uint32_t CMDRSP2 : 32; //!< [31:0] Command Response 2
bogdanm 82:6473597d706e 924 } B;
bogdanm 82:6473597d706e 925 } hw_sdhc_cmdrsp2_t;
bogdanm 82:6473597d706e 926 #endif
bogdanm 82:6473597d706e 927
bogdanm 82:6473597d706e 928 /*!
bogdanm 82:6473597d706e 929 * @name Constants and macros for entire SDHC_CMDRSP2 register
bogdanm 82:6473597d706e 930 */
bogdanm 82:6473597d706e 931 //@{
bogdanm 82:6473597d706e 932 #define HW_SDHC_CMDRSP2_ADDR (REGS_SDHC_BASE + 0x18U)
bogdanm 82:6473597d706e 933
bogdanm 82:6473597d706e 934 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 935 #define HW_SDHC_CMDRSP2 (*(__I hw_sdhc_cmdrsp2_t *) HW_SDHC_CMDRSP2_ADDR)
bogdanm 82:6473597d706e 936 #define HW_SDHC_CMDRSP2_RD() (HW_SDHC_CMDRSP2.U)
bogdanm 82:6473597d706e 937 #endif
bogdanm 82:6473597d706e 938 //@}
bogdanm 82:6473597d706e 939
bogdanm 82:6473597d706e 940 /*
bogdanm 82:6473597d706e 941 * Constants & macros for individual SDHC_CMDRSP2 bitfields
bogdanm 82:6473597d706e 942 */
bogdanm 82:6473597d706e 943
bogdanm 82:6473597d706e 944 /*!
bogdanm 82:6473597d706e 945 * @name Register SDHC_CMDRSP2, field CMDRSP2[31:0] (RO)
bogdanm 82:6473597d706e 946 */
bogdanm 82:6473597d706e 947 //@{
bogdanm 82:6473597d706e 948 #define BP_SDHC_CMDRSP2_CMDRSP2 (0U) //!< Bit position for SDHC_CMDRSP2_CMDRSP2.
bogdanm 82:6473597d706e 949 #define BM_SDHC_CMDRSP2_CMDRSP2 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP2_CMDRSP2.
bogdanm 82:6473597d706e 950 #define BS_SDHC_CMDRSP2_CMDRSP2 (32U) //!< Bit field size in bits for SDHC_CMDRSP2_CMDRSP2.
bogdanm 82:6473597d706e 951
bogdanm 82:6473597d706e 952 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 953 //! @brief Read current value of the SDHC_CMDRSP2_CMDRSP2 field.
bogdanm 82:6473597d706e 954 #define BR_SDHC_CMDRSP2_CMDRSP2 (HW_SDHC_CMDRSP2.U)
bogdanm 82:6473597d706e 955 #endif
bogdanm 82:6473597d706e 956 //@}
bogdanm 82:6473597d706e 957
bogdanm 82:6473597d706e 958 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 959 // HW_SDHC_CMDRSP3 - Command Response 3
bogdanm 82:6473597d706e 960 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 961
bogdanm 82:6473597d706e 962 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 963 /*!
bogdanm 82:6473597d706e 964 * @brief HW_SDHC_CMDRSP3 - Command Response 3 (RO)
bogdanm 82:6473597d706e 965 *
bogdanm 82:6473597d706e 966 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 967 *
bogdanm 82:6473597d706e 968 * This register is used to store part 3 of the response bits from the card. The
bogdanm 82:6473597d706e 969 * following table describes the mapping of command responses from the SD bus to
bogdanm 82:6473597d706e 970 * command response registers for each response type. In the table, R[ ] refers
bogdanm 82:6473597d706e 971 * to a bit range within the response data as transmitted on the SD bus. Response
bogdanm 82:6473597d706e 972 * bit definition for each response type Response type Meaning of response
bogdanm 82:6473597d706e 973 * Response field Response register R1,R1b (normal response) Card status R[39:8]
bogdanm 82:6473597d706e 974 * CMDRSP0 R1b (Auto CMD12 response) Card status for auto CMD12 R[39:8] CMDRSP3 R2
bogdanm 82:6473597d706e 975 * (CID, CSD register) CID/CSD register [127:8] R[127:8] {CMDRSP3[23:0], CMDRSP2,
bogdanm 82:6473597d706e 976 * CMDRSP1, CMDRSP0} R3 (OCR register) OCR register for memory R[39:8] CMDRSP0 R4
bogdanm 82:6473597d706e 977 * (OCR register) OCR register for I/O etc. R[39:8] CMDRSP0 R5, R5b SDIO response
bogdanm 82:6473597d706e 978 * R[39:8] CMDRSP0 R6 (Publish RCA) New published RCA[31:16] and card
bogdanm 82:6473597d706e 979 * status[15:0] R[39:9] CMDRSP0 This table shows that most responses with a length of 48
bogdanm 82:6473597d706e 980 * (R[47:0]) have 32-bit of the response data (R[39:8]) stored in the CMDRSP0
bogdanm 82:6473597d706e 981 * register. Responses of type R1b (auto CMD12 responses) have response data bits
bogdanm 82:6473597d706e 982 * (R[39:8]) stored in the CMDRSP3 register. Responses with length 136 (R[135:0]) have
bogdanm 82:6473597d706e 983 * 120-bit of the response data (R[127:8]) stored in the CMDRSP0, 1, 2, and 3
bogdanm 82:6473597d706e 984 * registers. To be able to read the response status efficiently, the SDHC stores
bogdanm 82:6473597d706e 985 * only a part of the response data in the command response registers. This
bogdanm 82:6473597d706e 986 * enables the host driver to efficiently read 32-bit of response data in one read
bogdanm 82:6473597d706e 987 * cycle on a 32-bit bus system. Parts of the response, the index field and the CRC,
bogdanm 82:6473597d706e 988 * are checked by the SDHC, as specified by XFERTYP[CICEN] and XFERTYP[CCCEN],
bogdanm 82:6473597d706e 989 * and generate an error interrupt if any error is detected. The bit range for the
bogdanm 82:6473597d706e 990 * CRC check depends on the response length. If the response length is 48, the
bogdanm 82:6473597d706e 991 * SDHC will check R[47:1], and if the response length is 136 the SDHC will check
bogdanm 82:6473597d706e 992 * R[119:1]. Because the SDHC may have a multiple block data transfer executing
bogdanm 82:6473597d706e 993 * concurrently with a CMD_wo_DAT command, the SDHC stores the auto CMD12 response
bogdanm 82:6473597d706e 994 * in the CMDRSP3 register. The CMD_wo_DAT response is stored in CMDRSP0. This
bogdanm 82:6473597d706e 995 * allows the SDHC to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT
bogdanm 82:6473597d706e 996 * and vice versa. When the SDHC modifies part of the command response
bogdanm 82:6473597d706e 997 * registers, as shown in the table above, it preserves the unmodified bits.
bogdanm 82:6473597d706e 998 */
bogdanm 82:6473597d706e 999 typedef union _hw_sdhc_cmdrsp3
bogdanm 82:6473597d706e 1000 {
bogdanm 82:6473597d706e 1001 uint32_t U;
bogdanm 82:6473597d706e 1002 struct _hw_sdhc_cmdrsp3_bitfields
bogdanm 82:6473597d706e 1003 {
bogdanm 82:6473597d706e 1004 uint32_t CMDRSP3 : 32; //!< [31:0] Command Response 3
bogdanm 82:6473597d706e 1005 } B;
bogdanm 82:6473597d706e 1006 } hw_sdhc_cmdrsp3_t;
bogdanm 82:6473597d706e 1007 #endif
bogdanm 82:6473597d706e 1008
bogdanm 82:6473597d706e 1009 /*!
bogdanm 82:6473597d706e 1010 * @name Constants and macros for entire SDHC_CMDRSP3 register
bogdanm 82:6473597d706e 1011 */
bogdanm 82:6473597d706e 1012 //@{
bogdanm 82:6473597d706e 1013 #define HW_SDHC_CMDRSP3_ADDR (REGS_SDHC_BASE + 0x1CU)
bogdanm 82:6473597d706e 1014
bogdanm 82:6473597d706e 1015 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1016 #define HW_SDHC_CMDRSP3 (*(__I hw_sdhc_cmdrsp3_t *) HW_SDHC_CMDRSP3_ADDR)
bogdanm 82:6473597d706e 1017 #define HW_SDHC_CMDRSP3_RD() (HW_SDHC_CMDRSP3.U)
bogdanm 82:6473597d706e 1018 #endif
bogdanm 82:6473597d706e 1019 //@}
bogdanm 82:6473597d706e 1020
bogdanm 82:6473597d706e 1021 /*
bogdanm 82:6473597d706e 1022 * Constants & macros for individual SDHC_CMDRSP3 bitfields
bogdanm 82:6473597d706e 1023 */
bogdanm 82:6473597d706e 1024
bogdanm 82:6473597d706e 1025 /*!
bogdanm 82:6473597d706e 1026 * @name Register SDHC_CMDRSP3, field CMDRSP3[31:0] (RO)
bogdanm 82:6473597d706e 1027 */
bogdanm 82:6473597d706e 1028 //@{
bogdanm 82:6473597d706e 1029 #define BP_SDHC_CMDRSP3_CMDRSP3 (0U) //!< Bit position for SDHC_CMDRSP3_CMDRSP3.
bogdanm 82:6473597d706e 1030 #define BM_SDHC_CMDRSP3_CMDRSP3 (0xFFFFFFFFU) //!< Bit mask for SDHC_CMDRSP3_CMDRSP3.
bogdanm 82:6473597d706e 1031 #define BS_SDHC_CMDRSP3_CMDRSP3 (32U) //!< Bit field size in bits for SDHC_CMDRSP3_CMDRSP3.
bogdanm 82:6473597d706e 1032
bogdanm 82:6473597d706e 1033 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1034 //! @brief Read current value of the SDHC_CMDRSP3_CMDRSP3 field.
bogdanm 82:6473597d706e 1035 #define BR_SDHC_CMDRSP3_CMDRSP3 (HW_SDHC_CMDRSP3.U)
bogdanm 82:6473597d706e 1036 #endif
bogdanm 82:6473597d706e 1037 //@}
bogdanm 82:6473597d706e 1038
bogdanm 82:6473597d706e 1039 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1040 // HW_SDHC_DATPORT - Buffer Data Port register
bogdanm 82:6473597d706e 1041 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1042
bogdanm 82:6473597d706e 1043 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1044 /*!
bogdanm 82:6473597d706e 1045 * @brief HW_SDHC_DATPORT - Buffer Data Port register (RW)
bogdanm 82:6473597d706e 1046 *
bogdanm 82:6473597d706e 1047 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 1048 *
bogdanm 82:6473597d706e 1049 * This is a 32-bit data port register used to access the internal buffer and it
bogdanm 82:6473597d706e 1050 * cannot be updated in Idle mode.
bogdanm 82:6473597d706e 1051 */
bogdanm 82:6473597d706e 1052 typedef union _hw_sdhc_datport
bogdanm 82:6473597d706e 1053 {
bogdanm 82:6473597d706e 1054 uint32_t U;
bogdanm 82:6473597d706e 1055 struct _hw_sdhc_datport_bitfields
bogdanm 82:6473597d706e 1056 {
bogdanm 82:6473597d706e 1057 uint32_t DATCONT : 32; //!< [31:0] Data Content
bogdanm 82:6473597d706e 1058 } B;
bogdanm 82:6473597d706e 1059 } hw_sdhc_datport_t;
bogdanm 82:6473597d706e 1060 #endif
bogdanm 82:6473597d706e 1061
bogdanm 82:6473597d706e 1062 /*!
bogdanm 82:6473597d706e 1063 * @name Constants and macros for entire SDHC_DATPORT register
bogdanm 82:6473597d706e 1064 */
bogdanm 82:6473597d706e 1065 //@{
bogdanm 82:6473597d706e 1066 #define HW_SDHC_DATPORT_ADDR (REGS_SDHC_BASE + 0x20U)
bogdanm 82:6473597d706e 1067
bogdanm 82:6473597d706e 1068 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1069 #define HW_SDHC_DATPORT (*(__IO hw_sdhc_datport_t *) HW_SDHC_DATPORT_ADDR)
bogdanm 82:6473597d706e 1070 #define HW_SDHC_DATPORT_RD() (HW_SDHC_DATPORT.U)
bogdanm 82:6473597d706e 1071 #define HW_SDHC_DATPORT_WR(v) (HW_SDHC_DATPORT.U = (v))
bogdanm 82:6473597d706e 1072 #define HW_SDHC_DATPORT_SET(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() | (v)))
bogdanm 82:6473597d706e 1073 #define HW_SDHC_DATPORT_CLR(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() & ~(v)))
bogdanm 82:6473597d706e 1074 #define HW_SDHC_DATPORT_TOG(v) (HW_SDHC_DATPORT_WR(HW_SDHC_DATPORT_RD() ^ (v)))
bogdanm 82:6473597d706e 1075 #endif
bogdanm 82:6473597d706e 1076 //@}
bogdanm 82:6473597d706e 1077
bogdanm 82:6473597d706e 1078 /*
bogdanm 82:6473597d706e 1079 * Constants & macros for individual SDHC_DATPORT bitfields
bogdanm 82:6473597d706e 1080 */
bogdanm 82:6473597d706e 1081
bogdanm 82:6473597d706e 1082 /*!
bogdanm 82:6473597d706e 1083 * @name Register SDHC_DATPORT, field DATCONT[31:0] (RW)
bogdanm 82:6473597d706e 1084 *
bogdanm 82:6473597d706e 1085 * The Buffer Data Port register is for 32-bit data access by the CPU or the
bogdanm 82:6473597d706e 1086 * external DMA. When the internal DMA is enabled, any write to this register is
bogdanm 82:6473597d706e 1087 * ignored, and any read from this register will always yield 0s.
bogdanm 82:6473597d706e 1088 */
bogdanm 82:6473597d706e 1089 //@{
bogdanm 82:6473597d706e 1090 #define BP_SDHC_DATPORT_DATCONT (0U) //!< Bit position for SDHC_DATPORT_DATCONT.
bogdanm 82:6473597d706e 1091 #define BM_SDHC_DATPORT_DATCONT (0xFFFFFFFFU) //!< Bit mask for SDHC_DATPORT_DATCONT.
bogdanm 82:6473597d706e 1092 #define BS_SDHC_DATPORT_DATCONT (32U) //!< Bit field size in bits for SDHC_DATPORT_DATCONT.
bogdanm 82:6473597d706e 1093
bogdanm 82:6473597d706e 1094 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1095 //! @brief Read current value of the SDHC_DATPORT_DATCONT field.
bogdanm 82:6473597d706e 1096 #define BR_SDHC_DATPORT_DATCONT (HW_SDHC_DATPORT.U)
bogdanm 82:6473597d706e 1097 #endif
bogdanm 82:6473597d706e 1098
bogdanm 82:6473597d706e 1099 //! @brief Format value for bitfield SDHC_DATPORT_DATCONT.
bogdanm 82:6473597d706e 1100 #define BF_SDHC_DATPORT_DATCONT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_DATPORT_DATCONT), uint32_t) & BM_SDHC_DATPORT_DATCONT)
bogdanm 82:6473597d706e 1101
bogdanm 82:6473597d706e 1102 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1103 //! @brief Set the DATCONT field to a new value.
bogdanm 82:6473597d706e 1104 #define BW_SDHC_DATPORT_DATCONT(v) (HW_SDHC_DATPORT_WR(v))
bogdanm 82:6473597d706e 1105 #endif
bogdanm 82:6473597d706e 1106 //@}
bogdanm 82:6473597d706e 1107
bogdanm 82:6473597d706e 1108 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1109 // HW_SDHC_PRSSTAT - Present State register
bogdanm 82:6473597d706e 1110 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1111
bogdanm 82:6473597d706e 1112 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1113 /*!
bogdanm 82:6473597d706e 1114 * @brief HW_SDHC_PRSSTAT - Present State register (RO)
bogdanm 82:6473597d706e 1115 *
bogdanm 82:6473597d706e 1116 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 1117 *
bogdanm 82:6473597d706e 1118 * The host driver can get status of the SDHC from this 32-bit read-only
bogdanm 82:6473597d706e 1119 * register. The host driver can issue CMD0, CMD12, CMD13 (for memory) and CMD52 (for
bogdanm 82:6473597d706e 1120 * SDIO) when the DAT lines are busy during a data transfer. These commands can be
bogdanm 82:6473597d706e 1121 * issued when Command Inhibit (CIHB) is set to zero. Other commands shall be
bogdanm 82:6473597d706e 1122 * issued when Command Inhibit (CDIHB) is set to zero. Possible changes to the SD
bogdanm 82:6473597d706e 1123 * Physical Specification may add other commands to this list in the future.
bogdanm 82:6473597d706e 1124 */
bogdanm 82:6473597d706e 1125 typedef union _hw_sdhc_prsstat
bogdanm 82:6473597d706e 1126 {
bogdanm 82:6473597d706e 1127 uint32_t U;
bogdanm 82:6473597d706e 1128 struct _hw_sdhc_prsstat_bitfields
bogdanm 82:6473597d706e 1129 {
bogdanm 82:6473597d706e 1130 uint32_t CIHB : 1; //!< [0] Command Inhibit (CMD)
bogdanm 82:6473597d706e 1131 uint32_t CDIHB : 1; //!< [1] Command Inhibit (DAT)
bogdanm 82:6473597d706e 1132 uint32_t DLA : 1; //!< [2] Data Line Active
bogdanm 82:6473597d706e 1133 uint32_t SDSTB : 1; //!< [3] SD Clock Stable
bogdanm 82:6473597d706e 1134 uint32_t IPGOFF : 1; //!< [4] Bus Clock Gated Off Internally
bogdanm 82:6473597d706e 1135 uint32_t HCKOFF : 1; //!< [5] System Clock Gated Off Internally
bogdanm 82:6473597d706e 1136 uint32_t PEROFF : 1; //!< [6] SDHC clock Gated Off Internally
bogdanm 82:6473597d706e 1137 uint32_t SDOFF : 1; //!< [7] SD Clock Gated Off Internally
bogdanm 82:6473597d706e 1138 uint32_t WTA : 1; //!< [8] Write Transfer Active
bogdanm 82:6473597d706e 1139 uint32_t RTA : 1; //!< [9] Read Transfer Active
bogdanm 82:6473597d706e 1140 uint32_t BWEN : 1; //!< [10] Buffer Write Enable
bogdanm 82:6473597d706e 1141 uint32_t BREN : 1; //!< [11] Buffer Read Enable
bogdanm 82:6473597d706e 1142 uint32_t RESERVED0 : 4; //!< [15:12]
bogdanm 82:6473597d706e 1143 uint32_t CINS : 1; //!< [16] Card Inserted
bogdanm 82:6473597d706e 1144 uint32_t RESERVED1 : 6; //!< [22:17]
bogdanm 82:6473597d706e 1145 uint32_t CLSL : 1; //!< [23] CMD Line Signal Level
bogdanm 82:6473597d706e 1146 uint32_t DLSL : 8; //!< [31:24] DAT Line Signal Level
bogdanm 82:6473597d706e 1147 } B;
bogdanm 82:6473597d706e 1148 } hw_sdhc_prsstat_t;
bogdanm 82:6473597d706e 1149 #endif
bogdanm 82:6473597d706e 1150
bogdanm 82:6473597d706e 1151 /*!
bogdanm 82:6473597d706e 1152 * @name Constants and macros for entire SDHC_PRSSTAT register
bogdanm 82:6473597d706e 1153 */
bogdanm 82:6473597d706e 1154 //@{
bogdanm 82:6473597d706e 1155 #define HW_SDHC_PRSSTAT_ADDR (REGS_SDHC_BASE + 0x24U)
bogdanm 82:6473597d706e 1156
bogdanm 82:6473597d706e 1157 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1158 #define HW_SDHC_PRSSTAT (*(__I hw_sdhc_prsstat_t *) HW_SDHC_PRSSTAT_ADDR)
bogdanm 82:6473597d706e 1159 #define HW_SDHC_PRSSTAT_RD() (HW_SDHC_PRSSTAT.U)
bogdanm 82:6473597d706e 1160 #endif
bogdanm 82:6473597d706e 1161 //@}
bogdanm 82:6473597d706e 1162
bogdanm 82:6473597d706e 1163 /*
bogdanm 82:6473597d706e 1164 * Constants & macros for individual SDHC_PRSSTAT bitfields
bogdanm 82:6473597d706e 1165 */
bogdanm 82:6473597d706e 1166
bogdanm 82:6473597d706e 1167 /*!
bogdanm 82:6473597d706e 1168 * @name Register SDHC_PRSSTAT, field CIHB[0] (RO)
bogdanm 82:6473597d706e 1169 *
bogdanm 82:6473597d706e 1170 * If this status bit is 0, it indicates that the CMD line is not in use and the
bogdanm 82:6473597d706e 1171 * SDHC can issue a SD/MMC Command using the CMD line. This bit is set also
bogdanm 82:6473597d706e 1172 * immediately after the Transfer Type register is written. This bit is cleared when
bogdanm 82:6473597d706e 1173 * the command response is received. Even if the CDIHB bit is set to 1, Commands
bogdanm 82:6473597d706e 1174 * using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
bogdanm 82:6473597d706e 1175 * generates a command complete interrupt in the interrupt status register. If the
bogdanm 82:6473597d706e 1176 * SDHC cannot issue the command because of a command conflict error (see
bogdanm 82:6473597d706e 1177 * command CRC error) or because of a command not issued by auto CMD12 error, this bit
bogdanm 82:6473597d706e 1178 * will remain 1 and the command complete is not set. The status of issuing an
bogdanm 82:6473597d706e 1179 * auto CMD12 does not show on this bit.
bogdanm 82:6473597d706e 1180 *
bogdanm 82:6473597d706e 1181 * Values:
bogdanm 82:6473597d706e 1182 * - 0 - Can issue command using only CMD line.
bogdanm 82:6473597d706e 1183 * - 1 - Cannot issue command.
bogdanm 82:6473597d706e 1184 */
bogdanm 82:6473597d706e 1185 //@{
bogdanm 82:6473597d706e 1186 #define BP_SDHC_PRSSTAT_CIHB (0U) //!< Bit position for SDHC_PRSSTAT_CIHB.
bogdanm 82:6473597d706e 1187 #define BM_SDHC_PRSSTAT_CIHB (0x00000001U) //!< Bit mask for SDHC_PRSSTAT_CIHB.
bogdanm 82:6473597d706e 1188 #define BS_SDHC_PRSSTAT_CIHB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CIHB.
bogdanm 82:6473597d706e 1189
bogdanm 82:6473597d706e 1190 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1191 //! @brief Read current value of the SDHC_PRSSTAT_CIHB field.
bogdanm 82:6473597d706e 1192 #define BR_SDHC_PRSSTAT_CIHB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CIHB))
bogdanm 82:6473597d706e 1193 #endif
bogdanm 82:6473597d706e 1194 //@}
bogdanm 82:6473597d706e 1195
bogdanm 82:6473597d706e 1196 /*!
bogdanm 82:6473597d706e 1197 * @name Register SDHC_PRSSTAT, field CDIHB[1] (RO)
bogdanm 82:6473597d706e 1198 *
bogdanm 82:6473597d706e 1199 * This status bit is generated if either the DLA or the RTA is set to 1. If
bogdanm 82:6473597d706e 1200 * this bit is 0, it indicates that the SDHC can issue the next SD/MMC Command.
bogdanm 82:6473597d706e 1201 * Commands with a busy signal belong to CDIHB, for example, R1b, R5b type. Except in
bogdanm 82:6473597d706e 1202 * the case when the command busy is finished, changing from 1 to 0 generates a
bogdanm 82:6473597d706e 1203 * transfer complete interrupt in the Interrupt Status register. The SD host
bogdanm 82:6473597d706e 1204 * driver can save registers for a suspend transaction after this bit has changed
bogdanm 82:6473597d706e 1205 * from 1 to 0.
bogdanm 82:6473597d706e 1206 *
bogdanm 82:6473597d706e 1207 * Values:
bogdanm 82:6473597d706e 1208 * - 0 - Can issue command which uses the DAT line.
bogdanm 82:6473597d706e 1209 * - 1 - Cannot issue command which uses the DAT line.
bogdanm 82:6473597d706e 1210 */
bogdanm 82:6473597d706e 1211 //@{
bogdanm 82:6473597d706e 1212 #define BP_SDHC_PRSSTAT_CDIHB (1U) //!< Bit position for SDHC_PRSSTAT_CDIHB.
bogdanm 82:6473597d706e 1213 #define BM_SDHC_PRSSTAT_CDIHB (0x00000002U) //!< Bit mask for SDHC_PRSSTAT_CDIHB.
bogdanm 82:6473597d706e 1214 #define BS_SDHC_PRSSTAT_CDIHB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CDIHB.
bogdanm 82:6473597d706e 1215
bogdanm 82:6473597d706e 1216 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1217 //! @brief Read current value of the SDHC_PRSSTAT_CDIHB field.
bogdanm 82:6473597d706e 1218 #define BR_SDHC_PRSSTAT_CDIHB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CDIHB))
bogdanm 82:6473597d706e 1219 #endif
bogdanm 82:6473597d706e 1220 //@}
bogdanm 82:6473597d706e 1221
bogdanm 82:6473597d706e 1222 /*!
bogdanm 82:6473597d706e 1223 * @name Register SDHC_PRSSTAT, field DLA[2] (RO)
bogdanm 82:6473597d706e 1224 *
bogdanm 82:6473597d706e 1225 * Indicates whether one of the DAT lines on the SD bus is in use. In the case
bogdanm 82:6473597d706e 1226 * of read transactions: This status indicates whether a read transfer is
bogdanm 82:6473597d706e 1227 * executing on the SD bus. Changes in this value from 1 to 0, between data blocks,
bogdanm 82:6473597d706e 1228 * generates a block gap event interrupt in the Interrupt Status register. This bit
bogdanm 82:6473597d706e 1229 * will be set in either of the following cases: After the end bit of the read
bogdanm 82:6473597d706e 1230 * command. When writing a 1 to PROCTL[CREQ] to restart a read transfer. This bit
bogdanm 82:6473597d706e 1231 * will be cleared in either of the following cases: When the end bit of the last
bogdanm 82:6473597d706e 1232 * data block is sent from the SD bus to the SDHC. When the read wait state is
bogdanm 82:6473597d706e 1233 * stopped by a suspend command and the DAT2 line is released. The SDHC will wait at
bogdanm 82:6473597d706e 1234 * the next block gap by driving read wait at the start of the interrupt cycle.
bogdanm 82:6473597d706e 1235 * If the read wait signal is already driven (data buffer cannot receive data),
bogdanm 82:6473597d706e 1236 * the SDHC can wait for a current block gap by continuing to drive the read wait
bogdanm 82:6473597d706e 1237 * signal. It is necessary to support read wait to use the suspend / resume
bogdanm 82:6473597d706e 1238 * function. This bit will remain 1 during read wait. In the case of write
bogdanm 82:6473597d706e 1239 * transactions: This status indicates that a write transfer is executing on the SD bus.
bogdanm 82:6473597d706e 1240 * Changes in this value from 1 to 0 generate a transfer complete interrupt in the
bogdanm 82:6473597d706e 1241 * interrupt status register. This bit will be set in either of the following
bogdanm 82:6473597d706e 1242 * cases: After the end bit of the write command. When writing to 1 to PROCTL[CREQ] to
bogdanm 82:6473597d706e 1243 * continue a write transfer. This bit will be cleared in either of the
bogdanm 82:6473597d706e 1244 * following cases: When the SD card releases write busy of the last data block, the SDHC
bogdanm 82:6473597d706e 1245 * will also detect if the output is not busy. If the SD card does not drive the
bogdanm 82:6473597d706e 1246 * busy signal after the CRC status is received, the SDHC shall assume the card
bogdanm 82:6473597d706e 1247 * drive "Not busy". When the SD card releases write busy, prior to waiting for
bogdanm 82:6473597d706e 1248 * write transfer, and as a result of a stop at block gap request. In the case of
bogdanm 82:6473597d706e 1249 * command with busy pending: This status indicates that a busy state follows the
bogdanm 82:6473597d706e 1250 * command and the data line is in use. This bit will be cleared when the DAT0
bogdanm 82:6473597d706e 1251 * line is released.
bogdanm 82:6473597d706e 1252 *
bogdanm 82:6473597d706e 1253 * Values:
bogdanm 82:6473597d706e 1254 * - 0 - DAT line inactive.
bogdanm 82:6473597d706e 1255 * - 1 - DAT line active.
bogdanm 82:6473597d706e 1256 */
bogdanm 82:6473597d706e 1257 //@{
bogdanm 82:6473597d706e 1258 #define BP_SDHC_PRSSTAT_DLA (2U) //!< Bit position for SDHC_PRSSTAT_DLA.
bogdanm 82:6473597d706e 1259 #define BM_SDHC_PRSSTAT_DLA (0x00000004U) //!< Bit mask for SDHC_PRSSTAT_DLA.
bogdanm 82:6473597d706e 1260 #define BS_SDHC_PRSSTAT_DLA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_DLA.
bogdanm 82:6473597d706e 1261
bogdanm 82:6473597d706e 1262 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1263 //! @brief Read current value of the SDHC_PRSSTAT_DLA field.
bogdanm 82:6473597d706e 1264 #define BR_SDHC_PRSSTAT_DLA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_DLA))
bogdanm 82:6473597d706e 1265 #endif
bogdanm 82:6473597d706e 1266 //@}
bogdanm 82:6473597d706e 1267
bogdanm 82:6473597d706e 1268 /*!
bogdanm 82:6473597d706e 1269 * @name Register SDHC_PRSSTAT, field SDSTB[3] (RO)
bogdanm 82:6473597d706e 1270 *
bogdanm 82:6473597d706e 1271 * Indicates that the internal card clock is stable. This bit is for the host
bogdanm 82:6473597d706e 1272 * driver to poll clock status when changing the clock frequency. It is recommended
bogdanm 82:6473597d706e 1273 * to clear SYSCTL[SDCLKEN] to remove glitch on the card clock when the
bogdanm 82:6473597d706e 1274 * frequency is changing.
bogdanm 82:6473597d706e 1275 *
bogdanm 82:6473597d706e 1276 * Values:
bogdanm 82:6473597d706e 1277 * - 0 - Clock is changing frequency and not stable.
bogdanm 82:6473597d706e 1278 * - 1 - Clock is stable.
bogdanm 82:6473597d706e 1279 */
bogdanm 82:6473597d706e 1280 //@{
bogdanm 82:6473597d706e 1281 #define BP_SDHC_PRSSTAT_SDSTB (3U) //!< Bit position for SDHC_PRSSTAT_SDSTB.
bogdanm 82:6473597d706e 1282 #define BM_SDHC_PRSSTAT_SDSTB (0x00000008U) //!< Bit mask for SDHC_PRSSTAT_SDSTB.
bogdanm 82:6473597d706e 1283 #define BS_SDHC_PRSSTAT_SDSTB (1U) //!< Bit field size in bits for SDHC_PRSSTAT_SDSTB.
bogdanm 82:6473597d706e 1284
bogdanm 82:6473597d706e 1285 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1286 //! @brief Read current value of the SDHC_PRSSTAT_SDSTB field.
bogdanm 82:6473597d706e 1287 #define BR_SDHC_PRSSTAT_SDSTB (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_SDSTB))
bogdanm 82:6473597d706e 1288 #endif
bogdanm 82:6473597d706e 1289 //@}
bogdanm 82:6473597d706e 1290
bogdanm 82:6473597d706e 1291 /*!
bogdanm 82:6473597d706e 1292 * @name Register SDHC_PRSSTAT, field IPGOFF[4] (RO)
bogdanm 82:6473597d706e 1293 *
bogdanm 82:6473597d706e 1294 * Indicates that the bus clock is internally gated off. This bit is for the
bogdanm 82:6473597d706e 1295 * host driver to debug.
bogdanm 82:6473597d706e 1296 *
bogdanm 82:6473597d706e 1297 * Values:
bogdanm 82:6473597d706e 1298 * - 0 - Bus clock is active.
bogdanm 82:6473597d706e 1299 * - 1 - Bus clock is gated off.
bogdanm 82:6473597d706e 1300 */
bogdanm 82:6473597d706e 1301 //@{
bogdanm 82:6473597d706e 1302 #define BP_SDHC_PRSSTAT_IPGOFF (4U) //!< Bit position for SDHC_PRSSTAT_IPGOFF.
bogdanm 82:6473597d706e 1303 #define BM_SDHC_PRSSTAT_IPGOFF (0x00000010U) //!< Bit mask for SDHC_PRSSTAT_IPGOFF.
bogdanm 82:6473597d706e 1304 #define BS_SDHC_PRSSTAT_IPGOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_IPGOFF.
bogdanm 82:6473597d706e 1305
bogdanm 82:6473597d706e 1306 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1307 //! @brief Read current value of the SDHC_PRSSTAT_IPGOFF field.
bogdanm 82:6473597d706e 1308 #define BR_SDHC_PRSSTAT_IPGOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_IPGOFF))
bogdanm 82:6473597d706e 1309 #endif
bogdanm 82:6473597d706e 1310 //@}
bogdanm 82:6473597d706e 1311
bogdanm 82:6473597d706e 1312 /*!
bogdanm 82:6473597d706e 1313 * @name Register SDHC_PRSSTAT, field HCKOFF[5] (RO)
bogdanm 82:6473597d706e 1314 *
bogdanm 82:6473597d706e 1315 * Indicates that the system clock is internally gated off. This bit is for the
bogdanm 82:6473597d706e 1316 * host driver to debug during a data transfer.
bogdanm 82:6473597d706e 1317 *
bogdanm 82:6473597d706e 1318 * Values:
bogdanm 82:6473597d706e 1319 * - 0 - System clock is active.
bogdanm 82:6473597d706e 1320 * - 1 - System clock is gated off.
bogdanm 82:6473597d706e 1321 */
bogdanm 82:6473597d706e 1322 //@{
bogdanm 82:6473597d706e 1323 #define BP_SDHC_PRSSTAT_HCKOFF (5U) //!< Bit position for SDHC_PRSSTAT_HCKOFF.
bogdanm 82:6473597d706e 1324 #define BM_SDHC_PRSSTAT_HCKOFF (0x00000020U) //!< Bit mask for SDHC_PRSSTAT_HCKOFF.
bogdanm 82:6473597d706e 1325 #define BS_SDHC_PRSSTAT_HCKOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_HCKOFF.
bogdanm 82:6473597d706e 1326
bogdanm 82:6473597d706e 1327 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1328 //! @brief Read current value of the SDHC_PRSSTAT_HCKOFF field.
bogdanm 82:6473597d706e 1329 #define BR_SDHC_PRSSTAT_HCKOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_HCKOFF))
bogdanm 82:6473597d706e 1330 #endif
bogdanm 82:6473597d706e 1331 //@}
bogdanm 82:6473597d706e 1332
bogdanm 82:6473597d706e 1333 /*!
bogdanm 82:6473597d706e 1334 * @name Register SDHC_PRSSTAT, field PEROFF[6] (RO)
bogdanm 82:6473597d706e 1335 *
bogdanm 82:6473597d706e 1336 * Indicates that the is internally gated off. This bit is for the host driver
bogdanm 82:6473597d706e 1337 * to debug transaction on the SD bus. When INITA bit is set, SDHC sending 80
bogdanm 82:6473597d706e 1338 * clock cycles to the card, SDCLKEN must be 1 to enable the output card clock,
bogdanm 82:6473597d706e 1339 * otherwise the will never be gate off, so and will be always active. SDHC clock SDHC
bogdanm 82:6473597d706e 1340 * clock SDHC clock bus clock
bogdanm 82:6473597d706e 1341 *
bogdanm 82:6473597d706e 1342 * Values:
bogdanm 82:6473597d706e 1343 * - 0 - SDHC clock is active.
bogdanm 82:6473597d706e 1344 * - 1 - SDHC clock is gated off.
bogdanm 82:6473597d706e 1345 */
bogdanm 82:6473597d706e 1346 //@{
bogdanm 82:6473597d706e 1347 #define BP_SDHC_PRSSTAT_PEROFF (6U) //!< Bit position for SDHC_PRSSTAT_PEROFF.
bogdanm 82:6473597d706e 1348 #define BM_SDHC_PRSSTAT_PEROFF (0x00000040U) //!< Bit mask for SDHC_PRSSTAT_PEROFF.
bogdanm 82:6473597d706e 1349 #define BS_SDHC_PRSSTAT_PEROFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_PEROFF.
bogdanm 82:6473597d706e 1350
bogdanm 82:6473597d706e 1351 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1352 //! @brief Read current value of the SDHC_PRSSTAT_PEROFF field.
bogdanm 82:6473597d706e 1353 #define BR_SDHC_PRSSTAT_PEROFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_PEROFF))
bogdanm 82:6473597d706e 1354 #endif
bogdanm 82:6473597d706e 1355 //@}
bogdanm 82:6473597d706e 1356
bogdanm 82:6473597d706e 1357 /*!
bogdanm 82:6473597d706e 1358 * @name Register SDHC_PRSSTAT, field SDOFF[7] (RO)
bogdanm 82:6473597d706e 1359 *
bogdanm 82:6473597d706e 1360 * Indicates that the SD clock is internally gated off, because of buffer
bogdanm 82:6473597d706e 1361 * over/under-run or read pause without read wait assertion, or the driver has cleared
bogdanm 82:6473597d706e 1362 * SYSCTL[SDCLKEN] to stop the SD clock. This bit is for the host driver to debug
bogdanm 82:6473597d706e 1363 * data transaction on the SD bus.
bogdanm 82:6473597d706e 1364 *
bogdanm 82:6473597d706e 1365 * Values:
bogdanm 82:6473597d706e 1366 * - 0 - SD clock is active.
bogdanm 82:6473597d706e 1367 * - 1 - SD clock is gated off.
bogdanm 82:6473597d706e 1368 */
bogdanm 82:6473597d706e 1369 //@{
bogdanm 82:6473597d706e 1370 #define BP_SDHC_PRSSTAT_SDOFF (7U) //!< Bit position for SDHC_PRSSTAT_SDOFF.
bogdanm 82:6473597d706e 1371 #define BM_SDHC_PRSSTAT_SDOFF (0x00000080U) //!< Bit mask for SDHC_PRSSTAT_SDOFF.
bogdanm 82:6473597d706e 1372 #define BS_SDHC_PRSSTAT_SDOFF (1U) //!< Bit field size in bits for SDHC_PRSSTAT_SDOFF.
bogdanm 82:6473597d706e 1373
bogdanm 82:6473597d706e 1374 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1375 //! @brief Read current value of the SDHC_PRSSTAT_SDOFF field.
bogdanm 82:6473597d706e 1376 #define BR_SDHC_PRSSTAT_SDOFF (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_SDOFF))
bogdanm 82:6473597d706e 1377 #endif
bogdanm 82:6473597d706e 1378 //@}
bogdanm 82:6473597d706e 1379
bogdanm 82:6473597d706e 1380 /*!
bogdanm 82:6473597d706e 1381 * @name Register SDHC_PRSSTAT, field WTA[8] (RO)
bogdanm 82:6473597d706e 1382 *
bogdanm 82:6473597d706e 1383 * Indicates that a write transfer is active. If this bit is 0, it means no
bogdanm 82:6473597d706e 1384 * valid write data exists in the SDHC. This bit is set in either of the following
bogdanm 82:6473597d706e 1385 * cases: After the end bit of the write command. When writing 1 to PROCTL[CREQ] to
bogdanm 82:6473597d706e 1386 * restart a write transfer. This bit is cleared in either of the following
bogdanm 82:6473597d706e 1387 * cases: After getting the CRC status of the last data block as specified by the
bogdanm 82:6473597d706e 1388 * transfer count (single and multiple). After getting the CRC status of any block
bogdanm 82:6473597d706e 1389 * where data transmission is about to be stopped by a stop at block gap request.
bogdanm 82:6473597d706e 1390 * During a write transaction, a block gap event interrupt is generated when this
bogdanm 82:6473597d706e 1391 * bit is changed to 0, as result of the stop at block gap request being set.
bogdanm 82:6473597d706e 1392 * This status is useful for the host driver in determining when to issue commands
bogdanm 82:6473597d706e 1393 * during write busy state.
bogdanm 82:6473597d706e 1394 *
bogdanm 82:6473597d706e 1395 * Values:
bogdanm 82:6473597d706e 1396 * - 0 - No valid data.
bogdanm 82:6473597d706e 1397 * - 1 - Transferring data.
bogdanm 82:6473597d706e 1398 */
bogdanm 82:6473597d706e 1399 //@{
bogdanm 82:6473597d706e 1400 #define BP_SDHC_PRSSTAT_WTA (8U) //!< Bit position for SDHC_PRSSTAT_WTA.
bogdanm 82:6473597d706e 1401 #define BM_SDHC_PRSSTAT_WTA (0x00000100U) //!< Bit mask for SDHC_PRSSTAT_WTA.
bogdanm 82:6473597d706e 1402 #define BS_SDHC_PRSSTAT_WTA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_WTA.
bogdanm 82:6473597d706e 1403
bogdanm 82:6473597d706e 1404 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1405 //! @brief Read current value of the SDHC_PRSSTAT_WTA field.
bogdanm 82:6473597d706e 1406 #define BR_SDHC_PRSSTAT_WTA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_WTA))
bogdanm 82:6473597d706e 1407 #endif
bogdanm 82:6473597d706e 1408 //@}
bogdanm 82:6473597d706e 1409
bogdanm 82:6473597d706e 1410 /*!
bogdanm 82:6473597d706e 1411 * @name Register SDHC_PRSSTAT, field RTA[9] (RO)
bogdanm 82:6473597d706e 1412 *
bogdanm 82:6473597d706e 1413 * Used for detecting completion of a read transfer. This bit is set for either
bogdanm 82:6473597d706e 1414 * of the following conditions: After the end bit of the read command. When
bogdanm 82:6473597d706e 1415 * writing a 1 to PROCTL[CREQ] to restart a read transfer. A transfer complete
bogdanm 82:6473597d706e 1416 * interrupt is generated when this bit changes to 0. This bit is cleared for either of
bogdanm 82:6473597d706e 1417 * the following conditions: When the last data block as specified by block
bogdanm 82:6473597d706e 1418 * length is transferred to the system, that is, all data are read away from SDHC
bogdanm 82:6473597d706e 1419 * internal buffer. When all valid data blocks have been transferred from SDHC
bogdanm 82:6473597d706e 1420 * internal buffer to the system and no current block transfers are being sent as a
bogdanm 82:6473597d706e 1421 * result of the stop at block gap request being set to 1.
bogdanm 82:6473597d706e 1422 *
bogdanm 82:6473597d706e 1423 * Values:
bogdanm 82:6473597d706e 1424 * - 0 - No valid data.
bogdanm 82:6473597d706e 1425 * - 1 - Transferring data.
bogdanm 82:6473597d706e 1426 */
bogdanm 82:6473597d706e 1427 //@{
bogdanm 82:6473597d706e 1428 #define BP_SDHC_PRSSTAT_RTA (9U) //!< Bit position for SDHC_PRSSTAT_RTA.
bogdanm 82:6473597d706e 1429 #define BM_SDHC_PRSSTAT_RTA (0x00000200U) //!< Bit mask for SDHC_PRSSTAT_RTA.
bogdanm 82:6473597d706e 1430 #define BS_SDHC_PRSSTAT_RTA (1U) //!< Bit field size in bits for SDHC_PRSSTAT_RTA.
bogdanm 82:6473597d706e 1431
bogdanm 82:6473597d706e 1432 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1433 //! @brief Read current value of the SDHC_PRSSTAT_RTA field.
bogdanm 82:6473597d706e 1434 #define BR_SDHC_PRSSTAT_RTA (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_RTA))
bogdanm 82:6473597d706e 1435 #endif
bogdanm 82:6473597d706e 1436 //@}
bogdanm 82:6473597d706e 1437
bogdanm 82:6473597d706e 1438 /*!
bogdanm 82:6473597d706e 1439 * @name Register SDHC_PRSSTAT, field BWEN[10] (RO)
bogdanm 82:6473597d706e 1440 *
bogdanm 82:6473597d706e 1441 * Used for non-DMA write transfers. The SDHC can implement multiple buffers to
bogdanm 82:6473597d706e 1442 * transfer data efficiently. This read-only flag indicates whether space is
bogdanm 82:6473597d706e 1443 * available for write data. If this bit is 1, valid data greater than the watermark
bogdanm 82:6473597d706e 1444 * level can be written to the buffer. This read-only flag indicates whether
bogdanm 82:6473597d706e 1445 * space is available for write data.
bogdanm 82:6473597d706e 1446 *
bogdanm 82:6473597d706e 1447 * Values:
bogdanm 82:6473597d706e 1448 * - 0 - Write disable, the buffer can hold valid data less than the write
bogdanm 82:6473597d706e 1449 * watermark level.
bogdanm 82:6473597d706e 1450 * - 1 - Write enable, the buffer can hold valid data greater than the write
bogdanm 82:6473597d706e 1451 * watermark level.
bogdanm 82:6473597d706e 1452 */
bogdanm 82:6473597d706e 1453 //@{
bogdanm 82:6473597d706e 1454 #define BP_SDHC_PRSSTAT_BWEN (10U) //!< Bit position for SDHC_PRSSTAT_BWEN.
bogdanm 82:6473597d706e 1455 #define BM_SDHC_PRSSTAT_BWEN (0x00000400U) //!< Bit mask for SDHC_PRSSTAT_BWEN.
bogdanm 82:6473597d706e 1456 #define BS_SDHC_PRSSTAT_BWEN (1U) //!< Bit field size in bits for SDHC_PRSSTAT_BWEN.
bogdanm 82:6473597d706e 1457
bogdanm 82:6473597d706e 1458 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1459 //! @brief Read current value of the SDHC_PRSSTAT_BWEN field.
bogdanm 82:6473597d706e 1460 #define BR_SDHC_PRSSTAT_BWEN (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_BWEN))
bogdanm 82:6473597d706e 1461 #endif
bogdanm 82:6473597d706e 1462 //@}
bogdanm 82:6473597d706e 1463
bogdanm 82:6473597d706e 1464 /*!
bogdanm 82:6473597d706e 1465 * @name Register SDHC_PRSSTAT, field BREN[11] (RO)
bogdanm 82:6473597d706e 1466 *
bogdanm 82:6473597d706e 1467 * Used for non-DMA read transfers. The SDHC may implement multiple buffers to
bogdanm 82:6473597d706e 1468 * transfer data efficiently. This read-only flag indicates that valid data exists
bogdanm 82:6473597d706e 1469 * in the host side buffer. If this bit is high, valid data greater than the
bogdanm 82:6473597d706e 1470 * watermark level exist in the buffer. This read-only flag indicates that valid
bogdanm 82:6473597d706e 1471 * data exists in the host side buffer.
bogdanm 82:6473597d706e 1472 *
bogdanm 82:6473597d706e 1473 * Values:
bogdanm 82:6473597d706e 1474 * - 0 - Read disable, valid data less than the watermark level exist in the
bogdanm 82:6473597d706e 1475 * buffer.
bogdanm 82:6473597d706e 1476 * - 1 - Read enable, valid data greater than the watermark level exist in the
bogdanm 82:6473597d706e 1477 * buffer.
bogdanm 82:6473597d706e 1478 */
bogdanm 82:6473597d706e 1479 //@{
bogdanm 82:6473597d706e 1480 #define BP_SDHC_PRSSTAT_BREN (11U) //!< Bit position for SDHC_PRSSTAT_BREN.
bogdanm 82:6473597d706e 1481 #define BM_SDHC_PRSSTAT_BREN (0x00000800U) //!< Bit mask for SDHC_PRSSTAT_BREN.
bogdanm 82:6473597d706e 1482 #define BS_SDHC_PRSSTAT_BREN (1U) //!< Bit field size in bits for SDHC_PRSSTAT_BREN.
bogdanm 82:6473597d706e 1483
bogdanm 82:6473597d706e 1484 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1485 //! @brief Read current value of the SDHC_PRSSTAT_BREN field.
bogdanm 82:6473597d706e 1486 #define BR_SDHC_PRSSTAT_BREN (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_BREN))
bogdanm 82:6473597d706e 1487 #endif
bogdanm 82:6473597d706e 1488 //@}
bogdanm 82:6473597d706e 1489
bogdanm 82:6473597d706e 1490 /*!
bogdanm 82:6473597d706e 1491 * @name Register SDHC_PRSSTAT, field CINS[16] (RO)
bogdanm 82:6473597d706e 1492 *
bogdanm 82:6473597d706e 1493 * Indicates whether a card has been inserted. The SDHC debounces this signal so
bogdanm 82:6473597d706e 1494 * that the host driver will not need to wait for it to stabilize. Changing from
bogdanm 82:6473597d706e 1495 * a 0 to 1 generates a card insertion interrupt in the Interrupt Status
bogdanm 82:6473597d706e 1496 * register. Changing from a 1 to 0 generates a card removal interrupt in the Interrupt
bogdanm 82:6473597d706e 1497 * Status register. A write to the force event register does not effect this bit.
bogdanm 82:6473597d706e 1498 * SYSCTL[RSTA] does not effect this bit. A software reset does not effect this
bogdanm 82:6473597d706e 1499 * bit.
bogdanm 82:6473597d706e 1500 *
bogdanm 82:6473597d706e 1501 * Values:
bogdanm 82:6473597d706e 1502 * - 0 - Power on reset or no card.
bogdanm 82:6473597d706e 1503 * - 1 - Card inserted.
bogdanm 82:6473597d706e 1504 */
bogdanm 82:6473597d706e 1505 //@{
bogdanm 82:6473597d706e 1506 #define BP_SDHC_PRSSTAT_CINS (16U) //!< Bit position for SDHC_PRSSTAT_CINS.
bogdanm 82:6473597d706e 1507 #define BM_SDHC_PRSSTAT_CINS (0x00010000U) //!< Bit mask for SDHC_PRSSTAT_CINS.
bogdanm 82:6473597d706e 1508 #define BS_SDHC_PRSSTAT_CINS (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CINS.
bogdanm 82:6473597d706e 1509
bogdanm 82:6473597d706e 1510 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1511 //! @brief Read current value of the SDHC_PRSSTAT_CINS field.
bogdanm 82:6473597d706e 1512 #define BR_SDHC_PRSSTAT_CINS (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CINS))
bogdanm 82:6473597d706e 1513 #endif
bogdanm 82:6473597d706e 1514 //@}
bogdanm 82:6473597d706e 1515
bogdanm 82:6473597d706e 1516 /*!
bogdanm 82:6473597d706e 1517 * @name Register SDHC_PRSSTAT, field CLSL[23] (RO)
bogdanm 82:6473597d706e 1518 *
bogdanm 82:6473597d706e 1519 * Used to check the CMD line level to recover from errors, and for debugging.
bogdanm 82:6473597d706e 1520 * The reset value is effected by the external pullup/pulldown resistor, by
bogdanm 82:6473597d706e 1521 * default, the read value of this bit after reset is 1b, when the command line is
bogdanm 82:6473597d706e 1522 * pulled up.
bogdanm 82:6473597d706e 1523 */
bogdanm 82:6473597d706e 1524 //@{
bogdanm 82:6473597d706e 1525 #define BP_SDHC_PRSSTAT_CLSL (23U) //!< Bit position for SDHC_PRSSTAT_CLSL.
bogdanm 82:6473597d706e 1526 #define BM_SDHC_PRSSTAT_CLSL (0x00800000U) //!< Bit mask for SDHC_PRSSTAT_CLSL.
bogdanm 82:6473597d706e 1527 #define BS_SDHC_PRSSTAT_CLSL (1U) //!< Bit field size in bits for SDHC_PRSSTAT_CLSL.
bogdanm 82:6473597d706e 1528
bogdanm 82:6473597d706e 1529 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1530 //! @brief Read current value of the SDHC_PRSSTAT_CLSL field.
bogdanm 82:6473597d706e 1531 #define BR_SDHC_PRSSTAT_CLSL (BITBAND_ACCESS32(HW_SDHC_PRSSTAT_ADDR, BP_SDHC_PRSSTAT_CLSL))
bogdanm 82:6473597d706e 1532 #endif
bogdanm 82:6473597d706e 1533 //@}
bogdanm 82:6473597d706e 1534
bogdanm 82:6473597d706e 1535 /*!
bogdanm 82:6473597d706e 1536 * @name Register SDHC_PRSSTAT, field DLSL[31:24] (RO)
bogdanm 82:6473597d706e 1537 *
bogdanm 82:6473597d706e 1538 * Used to check the DAT line level to recover from errors, and for debugging.
bogdanm 82:6473597d706e 1539 * This is especially useful in detecting the busy signal level from DAT[0]. The
bogdanm 82:6473597d706e 1540 * reset value is effected by the external pullup/pulldown resistors. By default,
bogdanm 82:6473597d706e 1541 * the read value of this field after reset is 8'b11110111, when DAT[3] is pulled
bogdanm 82:6473597d706e 1542 * down and the other lines are pulled up.
bogdanm 82:6473597d706e 1543 */
bogdanm 82:6473597d706e 1544 //@{
bogdanm 82:6473597d706e 1545 #define BP_SDHC_PRSSTAT_DLSL (24U) //!< Bit position for SDHC_PRSSTAT_DLSL.
bogdanm 82:6473597d706e 1546 #define BM_SDHC_PRSSTAT_DLSL (0xFF000000U) //!< Bit mask for SDHC_PRSSTAT_DLSL.
bogdanm 82:6473597d706e 1547 #define BS_SDHC_PRSSTAT_DLSL (8U) //!< Bit field size in bits for SDHC_PRSSTAT_DLSL.
bogdanm 82:6473597d706e 1548
bogdanm 82:6473597d706e 1549 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1550 //! @brief Read current value of the SDHC_PRSSTAT_DLSL field.
bogdanm 82:6473597d706e 1551 #define BR_SDHC_PRSSTAT_DLSL (HW_SDHC_PRSSTAT.B.DLSL)
bogdanm 82:6473597d706e 1552 #endif
bogdanm 82:6473597d706e 1553 //@}
bogdanm 82:6473597d706e 1554
bogdanm 82:6473597d706e 1555 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1556 // HW_SDHC_PROCTL - Protocol Control register
bogdanm 82:6473597d706e 1557 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1558
bogdanm 82:6473597d706e 1559 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1560 /*!
bogdanm 82:6473597d706e 1561 * @brief HW_SDHC_PROCTL - Protocol Control register (RW)
bogdanm 82:6473597d706e 1562 *
bogdanm 82:6473597d706e 1563 * Reset value: 0x00000020U
bogdanm 82:6473597d706e 1564 *
bogdanm 82:6473597d706e 1565 * There are three cases to restart the transfer after stop at the block gap.
bogdanm 82:6473597d706e 1566 * Which case is appropriate depends on whether the SDHC issues a suspend command
bogdanm 82:6473597d706e 1567 * or the SD card accepts the suspend command: If the host driver does not issue a
bogdanm 82:6473597d706e 1568 * suspend command, the continue request shall be used to restart the transfer.
bogdanm 82:6473597d706e 1569 * If the host driver issues a suspend command and the SD card accepts it, a
bogdanm 82:6473597d706e 1570 * resume command shall be used to restart the transfer. If the host driver issues a
bogdanm 82:6473597d706e 1571 * suspend command and the SD card does not accept it, the continue request shall
bogdanm 82:6473597d706e 1572 * be used to restart the transfer. Any time stop at block gap request stops the
bogdanm 82:6473597d706e 1573 * data transfer, the host driver shall wait for a transfer complete (in the
bogdanm 82:6473597d706e 1574 * interrupt status register), before attempting to restart the transfer. When
bogdanm 82:6473597d706e 1575 * restarting the data transfer by continue request, the host driver shall clear the
bogdanm 82:6473597d706e 1576 * stop at block gap request before or simultaneously.
bogdanm 82:6473597d706e 1577 */
bogdanm 82:6473597d706e 1578 typedef union _hw_sdhc_proctl
bogdanm 82:6473597d706e 1579 {
bogdanm 82:6473597d706e 1580 uint32_t U;
bogdanm 82:6473597d706e 1581 struct _hw_sdhc_proctl_bitfields
bogdanm 82:6473597d706e 1582 {
bogdanm 82:6473597d706e 1583 uint32_t LCTL : 1; //!< [0] LED Control
bogdanm 82:6473597d706e 1584 uint32_t DTW : 2; //!< [2:1] Data Transfer Width
bogdanm 82:6473597d706e 1585 uint32_t D3CD : 1; //!< [3] DAT3 As Card Detection Pin
bogdanm 82:6473597d706e 1586 uint32_t EMODE : 2; //!< [5:4] Endian Mode
bogdanm 82:6473597d706e 1587 uint32_t CDTL : 1; //!< [6] Card Detect Test Level
bogdanm 82:6473597d706e 1588 uint32_t CDSS : 1; //!< [7] Card Detect Signal Selection
bogdanm 82:6473597d706e 1589 uint32_t DMAS : 2; //!< [9:8] DMA Select
bogdanm 82:6473597d706e 1590 uint32_t RESERVED0 : 6; //!< [15:10]
bogdanm 82:6473597d706e 1591 uint32_t SABGREQ : 1; //!< [16] Stop At Block Gap Request
bogdanm 82:6473597d706e 1592 uint32_t CREQ : 1; //!< [17] Continue Request
bogdanm 82:6473597d706e 1593 uint32_t RWCTL : 1; //!< [18] Read Wait Control
bogdanm 82:6473597d706e 1594 uint32_t IABG : 1; //!< [19] Interrupt At Block Gap
bogdanm 82:6473597d706e 1595 uint32_t RESERVED1 : 4; //!< [23:20]
bogdanm 82:6473597d706e 1596 uint32_t WECINT : 1; //!< [24] Wakeup Event Enable On Card Interrupt
bogdanm 82:6473597d706e 1597 uint32_t WECINS : 1; //!< [25] Wakeup Event Enable On SD Card
bogdanm 82:6473597d706e 1598 //! Insertion
bogdanm 82:6473597d706e 1599 uint32_t WECRM : 1; //!< [26] Wakeup Event Enable On SD Card Removal
bogdanm 82:6473597d706e 1600 uint32_t RESERVED2 : 5; //!< [31:27]
bogdanm 82:6473597d706e 1601 } B;
bogdanm 82:6473597d706e 1602 } hw_sdhc_proctl_t;
bogdanm 82:6473597d706e 1603 #endif
bogdanm 82:6473597d706e 1604
bogdanm 82:6473597d706e 1605 /*!
bogdanm 82:6473597d706e 1606 * @name Constants and macros for entire SDHC_PROCTL register
bogdanm 82:6473597d706e 1607 */
bogdanm 82:6473597d706e 1608 //@{
bogdanm 82:6473597d706e 1609 #define HW_SDHC_PROCTL_ADDR (REGS_SDHC_BASE + 0x28U)
bogdanm 82:6473597d706e 1610
bogdanm 82:6473597d706e 1611 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1612 #define HW_SDHC_PROCTL (*(__IO hw_sdhc_proctl_t *) HW_SDHC_PROCTL_ADDR)
bogdanm 82:6473597d706e 1613 #define HW_SDHC_PROCTL_RD() (HW_SDHC_PROCTL.U)
bogdanm 82:6473597d706e 1614 #define HW_SDHC_PROCTL_WR(v) (HW_SDHC_PROCTL.U = (v))
bogdanm 82:6473597d706e 1615 #define HW_SDHC_PROCTL_SET(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() | (v)))
bogdanm 82:6473597d706e 1616 #define HW_SDHC_PROCTL_CLR(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() & ~(v)))
bogdanm 82:6473597d706e 1617 #define HW_SDHC_PROCTL_TOG(v) (HW_SDHC_PROCTL_WR(HW_SDHC_PROCTL_RD() ^ (v)))
bogdanm 82:6473597d706e 1618 #endif
bogdanm 82:6473597d706e 1619 //@}
bogdanm 82:6473597d706e 1620
bogdanm 82:6473597d706e 1621 /*
bogdanm 82:6473597d706e 1622 * Constants & macros for individual SDHC_PROCTL bitfields
bogdanm 82:6473597d706e 1623 */
bogdanm 82:6473597d706e 1624
bogdanm 82:6473597d706e 1625 /*!
bogdanm 82:6473597d706e 1626 * @name Register SDHC_PROCTL, field LCTL[0] (RW)
bogdanm 82:6473597d706e 1627 *
bogdanm 82:6473597d706e 1628 * This bit, fully controlled by the host driver, is used to caution the user
bogdanm 82:6473597d706e 1629 * not to remove the card while the card is being accessed. If the software is
bogdanm 82:6473597d706e 1630 * going to issue multiple SD commands, this bit can be set during all these
bogdanm 82:6473597d706e 1631 * transactions. It is not necessary to change for each transaction. When the software
bogdanm 82:6473597d706e 1632 * issues multiple SD commands, setting the bit once before the first command is
bogdanm 82:6473597d706e 1633 * sufficient: it is not necessary to reset the bit between commands.
bogdanm 82:6473597d706e 1634 *
bogdanm 82:6473597d706e 1635 * Values:
bogdanm 82:6473597d706e 1636 * - 0 - LED off.
bogdanm 82:6473597d706e 1637 * - 1 - LED on.
bogdanm 82:6473597d706e 1638 */
bogdanm 82:6473597d706e 1639 //@{
bogdanm 82:6473597d706e 1640 #define BP_SDHC_PROCTL_LCTL (0U) //!< Bit position for SDHC_PROCTL_LCTL.
bogdanm 82:6473597d706e 1641 #define BM_SDHC_PROCTL_LCTL (0x00000001U) //!< Bit mask for SDHC_PROCTL_LCTL.
bogdanm 82:6473597d706e 1642 #define BS_SDHC_PROCTL_LCTL (1U) //!< Bit field size in bits for SDHC_PROCTL_LCTL.
bogdanm 82:6473597d706e 1643
bogdanm 82:6473597d706e 1644 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1645 //! @brief Read current value of the SDHC_PROCTL_LCTL field.
bogdanm 82:6473597d706e 1646 #define BR_SDHC_PROCTL_LCTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_LCTL))
bogdanm 82:6473597d706e 1647 #endif
bogdanm 82:6473597d706e 1648
bogdanm 82:6473597d706e 1649 //! @brief Format value for bitfield SDHC_PROCTL_LCTL.
bogdanm 82:6473597d706e 1650 #define BF_SDHC_PROCTL_LCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_LCTL), uint32_t) & BM_SDHC_PROCTL_LCTL)
bogdanm 82:6473597d706e 1651
bogdanm 82:6473597d706e 1652 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1653 //! @brief Set the LCTL field to a new value.
bogdanm 82:6473597d706e 1654 #define BW_SDHC_PROCTL_LCTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_LCTL) = (v))
bogdanm 82:6473597d706e 1655 #endif
bogdanm 82:6473597d706e 1656 //@}
bogdanm 82:6473597d706e 1657
bogdanm 82:6473597d706e 1658 /*!
bogdanm 82:6473597d706e 1659 * @name Register SDHC_PROCTL, field DTW[2:1] (RW)
bogdanm 82:6473597d706e 1660 *
bogdanm 82:6473597d706e 1661 * Selects the data width of the SD bus for a data transfer. The host driver
bogdanm 82:6473597d706e 1662 * shall set it to match the data width of the card. Possible data transfer width is
bogdanm 82:6473597d706e 1663 * 1-bit, 4-bits or 8-bits.
bogdanm 82:6473597d706e 1664 *
bogdanm 82:6473597d706e 1665 * Values:
bogdanm 82:6473597d706e 1666 * - 00 - 1-bit mode
bogdanm 82:6473597d706e 1667 * - 01 - 4-bit mode
bogdanm 82:6473597d706e 1668 * - 10 - 8-bit mode
bogdanm 82:6473597d706e 1669 * - 11 - Reserved
bogdanm 82:6473597d706e 1670 */
bogdanm 82:6473597d706e 1671 //@{
bogdanm 82:6473597d706e 1672 #define BP_SDHC_PROCTL_DTW (1U) //!< Bit position for SDHC_PROCTL_DTW.
bogdanm 82:6473597d706e 1673 #define BM_SDHC_PROCTL_DTW (0x00000006U) //!< Bit mask for SDHC_PROCTL_DTW.
bogdanm 82:6473597d706e 1674 #define BS_SDHC_PROCTL_DTW (2U) //!< Bit field size in bits for SDHC_PROCTL_DTW.
bogdanm 82:6473597d706e 1675
bogdanm 82:6473597d706e 1676 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1677 //! @brief Read current value of the SDHC_PROCTL_DTW field.
bogdanm 82:6473597d706e 1678 #define BR_SDHC_PROCTL_DTW (HW_SDHC_PROCTL.B.DTW)
bogdanm 82:6473597d706e 1679 #endif
bogdanm 82:6473597d706e 1680
bogdanm 82:6473597d706e 1681 //! @brief Format value for bitfield SDHC_PROCTL_DTW.
bogdanm 82:6473597d706e 1682 #define BF_SDHC_PROCTL_DTW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_DTW), uint32_t) & BM_SDHC_PROCTL_DTW)
bogdanm 82:6473597d706e 1683
bogdanm 82:6473597d706e 1684 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1685 //! @brief Set the DTW field to a new value.
bogdanm 82:6473597d706e 1686 #define BW_SDHC_PROCTL_DTW(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_DTW) | BF_SDHC_PROCTL_DTW(v)))
bogdanm 82:6473597d706e 1687 #endif
bogdanm 82:6473597d706e 1688 //@}
bogdanm 82:6473597d706e 1689
bogdanm 82:6473597d706e 1690 /*!
bogdanm 82:6473597d706e 1691 * @name Register SDHC_PROCTL, field D3CD[3] (RW)
bogdanm 82:6473597d706e 1692 *
bogdanm 82:6473597d706e 1693 * If this bit is set, DAT3 should be pulled down to act as a card detection
bogdanm 82:6473597d706e 1694 * pin. Be cautious when using this feature, because DAT3 is also a chip-select for
bogdanm 82:6473597d706e 1695 * the SPI mode. A pulldown on this pin and CMD0 may set the card into the SPI
bogdanm 82:6473597d706e 1696 * mode, which the SDHC does not support. Note: Keep this bit set if SDIO interrupt
bogdanm 82:6473597d706e 1697 * is used.
bogdanm 82:6473597d706e 1698 *
bogdanm 82:6473597d706e 1699 * Values:
bogdanm 82:6473597d706e 1700 * - 0 - DAT3 does not monitor card Insertion.
bogdanm 82:6473597d706e 1701 * - 1 - DAT3 as card detection pin.
bogdanm 82:6473597d706e 1702 */
bogdanm 82:6473597d706e 1703 //@{
bogdanm 82:6473597d706e 1704 #define BP_SDHC_PROCTL_D3CD (3U) //!< Bit position for SDHC_PROCTL_D3CD.
bogdanm 82:6473597d706e 1705 #define BM_SDHC_PROCTL_D3CD (0x00000008U) //!< Bit mask for SDHC_PROCTL_D3CD.
bogdanm 82:6473597d706e 1706 #define BS_SDHC_PROCTL_D3CD (1U) //!< Bit field size in bits for SDHC_PROCTL_D3CD.
bogdanm 82:6473597d706e 1707
bogdanm 82:6473597d706e 1708 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1709 //! @brief Read current value of the SDHC_PROCTL_D3CD field.
bogdanm 82:6473597d706e 1710 #define BR_SDHC_PROCTL_D3CD (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_D3CD))
bogdanm 82:6473597d706e 1711 #endif
bogdanm 82:6473597d706e 1712
bogdanm 82:6473597d706e 1713 //! @brief Format value for bitfield SDHC_PROCTL_D3CD.
bogdanm 82:6473597d706e 1714 #define BF_SDHC_PROCTL_D3CD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_D3CD), uint32_t) & BM_SDHC_PROCTL_D3CD)
bogdanm 82:6473597d706e 1715
bogdanm 82:6473597d706e 1716 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1717 //! @brief Set the D3CD field to a new value.
bogdanm 82:6473597d706e 1718 #define BW_SDHC_PROCTL_D3CD(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_D3CD) = (v))
bogdanm 82:6473597d706e 1719 #endif
bogdanm 82:6473597d706e 1720 //@}
bogdanm 82:6473597d706e 1721
bogdanm 82:6473597d706e 1722 /*!
bogdanm 82:6473597d706e 1723 * @name Register SDHC_PROCTL, field EMODE[5:4] (RW)
bogdanm 82:6473597d706e 1724 *
bogdanm 82:6473597d706e 1725 * The SDHC supports all four endian modes in data transfer.
bogdanm 82:6473597d706e 1726 *
bogdanm 82:6473597d706e 1727 * Values:
bogdanm 82:6473597d706e 1728 * - 00 - Big endian mode
bogdanm 82:6473597d706e 1729 * - 01 - Half word big endian mode
bogdanm 82:6473597d706e 1730 * - 10 - Little endian mode
bogdanm 82:6473597d706e 1731 * - 11 - Reserved
bogdanm 82:6473597d706e 1732 */
bogdanm 82:6473597d706e 1733 //@{
bogdanm 82:6473597d706e 1734 #define BP_SDHC_PROCTL_EMODE (4U) //!< Bit position for SDHC_PROCTL_EMODE.
bogdanm 82:6473597d706e 1735 #define BM_SDHC_PROCTL_EMODE (0x00000030U) //!< Bit mask for SDHC_PROCTL_EMODE.
bogdanm 82:6473597d706e 1736 #define BS_SDHC_PROCTL_EMODE (2U) //!< Bit field size in bits for SDHC_PROCTL_EMODE.
bogdanm 82:6473597d706e 1737
bogdanm 82:6473597d706e 1738 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1739 //! @brief Read current value of the SDHC_PROCTL_EMODE field.
bogdanm 82:6473597d706e 1740 #define BR_SDHC_PROCTL_EMODE (HW_SDHC_PROCTL.B.EMODE)
bogdanm 82:6473597d706e 1741 #endif
bogdanm 82:6473597d706e 1742
bogdanm 82:6473597d706e 1743 //! @brief Format value for bitfield SDHC_PROCTL_EMODE.
bogdanm 82:6473597d706e 1744 #define BF_SDHC_PROCTL_EMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_EMODE), uint32_t) & BM_SDHC_PROCTL_EMODE)
bogdanm 82:6473597d706e 1745
bogdanm 82:6473597d706e 1746 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1747 //! @brief Set the EMODE field to a new value.
bogdanm 82:6473597d706e 1748 #define BW_SDHC_PROCTL_EMODE(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_EMODE) | BF_SDHC_PROCTL_EMODE(v)))
bogdanm 82:6473597d706e 1749 #endif
bogdanm 82:6473597d706e 1750 //@}
bogdanm 82:6473597d706e 1751
bogdanm 82:6473597d706e 1752 /*!
bogdanm 82:6473597d706e 1753 * @name Register SDHC_PROCTL, field CDTL[6] (RW)
bogdanm 82:6473597d706e 1754 *
bogdanm 82:6473597d706e 1755 * Enabled while the CDSS is set to 1 and it indicates card insertion.
bogdanm 82:6473597d706e 1756 *
bogdanm 82:6473597d706e 1757 * Values:
bogdanm 82:6473597d706e 1758 * - 0 - Card detect test level is 0, no card inserted.
bogdanm 82:6473597d706e 1759 * - 1 - Card detect test level is 1, card inserted.
bogdanm 82:6473597d706e 1760 */
bogdanm 82:6473597d706e 1761 //@{
bogdanm 82:6473597d706e 1762 #define BP_SDHC_PROCTL_CDTL (6U) //!< Bit position for SDHC_PROCTL_CDTL.
bogdanm 82:6473597d706e 1763 #define BM_SDHC_PROCTL_CDTL (0x00000040U) //!< Bit mask for SDHC_PROCTL_CDTL.
bogdanm 82:6473597d706e 1764 #define BS_SDHC_PROCTL_CDTL (1U) //!< Bit field size in bits for SDHC_PROCTL_CDTL.
bogdanm 82:6473597d706e 1765
bogdanm 82:6473597d706e 1766 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1767 //! @brief Read current value of the SDHC_PROCTL_CDTL field.
bogdanm 82:6473597d706e 1768 #define BR_SDHC_PROCTL_CDTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDTL))
bogdanm 82:6473597d706e 1769 #endif
bogdanm 82:6473597d706e 1770
bogdanm 82:6473597d706e 1771 //! @brief Format value for bitfield SDHC_PROCTL_CDTL.
bogdanm 82:6473597d706e 1772 #define BF_SDHC_PROCTL_CDTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CDTL), uint32_t) & BM_SDHC_PROCTL_CDTL)
bogdanm 82:6473597d706e 1773
bogdanm 82:6473597d706e 1774 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1775 //! @brief Set the CDTL field to a new value.
bogdanm 82:6473597d706e 1776 #define BW_SDHC_PROCTL_CDTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDTL) = (v))
bogdanm 82:6473597d706e 1777 #endif
bogdanm 82:6473597d706e 1778 //@}
bogdanm 82:6473597d706e 1779
bogdanm 82:6473597d706e 1780 /*!
bogdanm 82:6473597d706e 1781 * @name Register SDHC_PROCTL, field CDSS[7] (RW)
bogdanm 82:6473597d706e 1782 *
bogdanm 82:6473597d706e 1783 * Selects the source for the card detection.
bogdanm 82:6473597d706e 1784 *
bogdanm 82:6473597d706e 1785 * Values:
bogdanm 82:6473597d706e 1786 * - 0 - Card detection level is selected for normal purpose.
bogdanm 82:6473597d706e 1787 * - 1 - Card detection test level is selected for test purpose.
bogdanm 82:6473597d706e 1788 */
bogdanm 82:6473597d706e 1789 //@{
bogdanm 82:6473597d706e 1790 #define BP_SDHC_PROCTL_CDSS (7U) //!< Bit position for SDHC_PROCTL_CDSS.
bogdanm 82:6473597d706e 1791 #define BM_SDHC_PROCTL_CDSS (0x00000080U) //!< Bit mask for SDHC_PROCTL_CDSS.
bogdanm 82:6473597d706e 1792 #define BS_SDHC_PROCTL_CDSS (1U) //!< Bit field size in bits for SDHC_PROCTL_CDSS.
bogdanm 82:6473597d706e 1793
bogdanm 82:6473597d706e 1794 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1795 //! @brief Read current value of the SDHC_PROCTL_CDSS field.
bogdanm 82:6473597d706e 1796 #define BR_SDHC_PROCTL_CDSS (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDSS))
bogdanm 82:6473597d706e 1797 #endif
bogdanm 82:6473597d706e 1798
bogdanm 82:6473597d706e 1799 //! @brief Format value for bitfield SDHC_PROCTL_CDSS.
bogdanm 82:6473597d706e 1800 #define BF_SDHC_PROCTL_CDSS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CDSS), uint32_t) & BM_SDHC_PROCTL_CDSS)
bogdanm 82:6473597d706e 1801
bogdanm 82:6473597d706e 1802 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1803 //! @brief Set the CDSS field to a new value.
bogdanm 82:6473597d706e 1804 #define BW_SDHC_PROCTL_CDSS(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CDSS) = (v))
bogdanm 82:6473597d706e 1805 #endif
bogdanm 82:6473597d706e 1806 //@}
bogdanm 82:6473597d706e 1807
bogdanm 82:6473597d706e 1808 /*!
bogdanm 82:6473597d706e 1809 * @name Register SDHC_PROCTL, field DMAS[9:8] (RW)
bogdanm 82:6473597d706e 1810 *
bogdanm 82:6473597d706e 1811 * This field is valid while DMA (SDMA or ADMA) is enabled and selects the DMA
bogdanm 82:6473597d706e 1812 * operation.
bogdanm 82:6473597d706e 1813 *
bogdanm 82:6473597d706e 1814 * Values:
bogdanm 82:6473597d706e 1815 * - 00 - No DMA or simple DMA is selected.
bogdanm 82:6473597d706e 1816 * - 01 - ADMA1 is selected.
bogdanm 82:6473597d706e 1817 * - 10 - ADMA2 is selected.
bogdanm 82:6473597d706e 1818 * - 11 - Reserved
bogdanm 82:6473597d706e 1819 */
bogdanm 82:6473597d706e 1820 //@{
bogdanm 82:6473597d706e 1821 #define BP_SDHC_PROCTL_DMAS (8U) //!< Bit position for SDHC_PROCTL_DMAS.
bogdanm 82:6473597d706e 1822 #define BM_SDHC_PROCTL_DMAS (0x00000300U) //!< Bit mask for SDHC_PROCTL_DMAS.
bogdanm 82:6473597d706e 1823 #define BS_SDHC_PROCTL_DMAS (2U) //!< Bit field size in bits for SDHC_PROCTL_DMAS.
bogdanm 82:6473597d706e 1824
bogdanm 82:6473597d706e 1825 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1826 //! @brief Read current value of the SDHC_PROCTL_DMAS field.
bogdanm 82:6473597d706e 1827 #define BR_SDHC_PROCTL_DMAS (HW_SDHC_PROCTL.B.DMAS)
bogdanm 82:6473597d706e 1828 #endif
bogdanm 82:6473597d706e 1829
bogdanm 82:6473597d706e 1830 //! @brief Format value for bitfield SDHC_PROCTL_DMAS.
bogdanm 82:6473597d706e 1831 #define BF_SDHC_PROCTL_DMAS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_DMAS), uint32_t) & BM_SDHC_PROCTL_DMAS)
bogdanm 82:6473597d706e 1832
bogdanm 82:6473597d706e 1833 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1834 //! @brief Set the DMAS field to a new value.
bogdanm 82:6473597d706e 1835 #define BW_SDHC_PROCTL_DMAS(v) (HW_SDHC_PROCTL_WR((HW_SDHC_PROCTL_RD() & ~BM_SDHC_PROCTL_DMAS) | BF_SDHC_PROCTL_DMAS(v)))
bogdanm 82:6473597d706e 1836 #endif
bogdanm 82:6473597d706e 1837 //@}
bogdanm 82:6473597d706e 1838
bogdanm 82:6473597d706e 1839 /*!
bogdanm 82:6473597d706e 1840 * @name Register SDHC_PROCTL, field SABGREQ[16] (RW)
bogdanm 82:6473597d706e 1841 *
bogdanm 82:6473597d706e 1842 * Used to stop executing a transaction at the next block gap for both DMA and
bogdanm 82:6473597d706e 1843 * non-DMA transfers. Until the IRQSTATEN[TCSEN] is set to 1, indicating a
bogdanm 82:6473597d706e 1844 * transfer completion, the host driver shall leave this bit set to 1. Clearing both
bogdanm 82:6473597d706e 1845 * PROCTL[SABGREQ] and PROCTL[CREQ] does not cause the transaction to restart. Read
bogdanm 82:6473597d706e 1846 * Wait is used to stop the read transaction at the block gap. The SDHC will
bogdanm 82:6473597d706e 1847 * honor the PROCTL[SABGREQ] for write transfers, but for read transfers it requires
bogdanm 82:6473597d706e 1848 * that SDIO card support read wait. Therefore, the host driver shall not set
bogdanm 82:6473597d706e 1849 * this bit during read transfers unless the SDIO card supports read wait and has
bogdanm 82:6473597d706e 1850 * set PROCTL[RWCTL] to 1, otherwise the SDHC will stop the SD bus clock to pause
bogdanm 82:6473597d706e 1851 * the read operation during block gap. In the case of write transfers in which
bogdanm 82:6473597d706e 1852 * the host driver writes data to the data port register, the host driver shall set
bogdanm 82:6473597d706e 1853 * this bit after all block data is written. If this bit is set to 1, the host
bogdanm 82:6473597d706e 1854 * driver shall not write data to the Data Port register after a block is sent.
bogdanm 82:6473597d706e 1855 * Once this bit is set, the host driver shall not clear this bit before
bogdanm 82:6473597d706e 1856 * IRQSTATEN[TCSEN] is set, otherwise the SDHC's behavior is undefined. This bit effects
bogdanm 82:6473597d706e 1857 * PRSSTAT[RTA], PRSSTAT[WTA], and PRSSTAT[CDIHB].
bogdanm 82:6473597d706e 1858 *
bogdanm 82:6473597d706e 1859 * Values:
bogdanm 82:6473597d706e 1860 * - 0 - Transfer
bogdanm 82:6473597d706e 1861 * - 1 - Stop
bogdanm 82:6473597d706e 1862 */
bogdanm 82:6473597d706e 1863 //@{
bogdanm 82:6473597d706e 1864 #define BP_SDHC_PROCTL_SABGREQ (16U) //!< Bit position for SDHC_PROCTL_SABGREQ.
bogdanm 82:6473597d706e 1865 #define BM_SDHC_PROCTL_SABGREQ (0x00010000U) //!< Bit mask for SDHC_PROCTL_SABGREQ.
bogdanm 82:6473597d706e 1866 #define BS_SDHC_PROCTL_SABGREQ (1U) //!< Bit field size in bits for SDHC_PROCTL_SABGREQ.
bogdanm 82:6473597d706e 1867
bogdanm 82:6473597d706e 1868 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1869 //! @brief Read current value of the SDHC_PROCTL_SABGREQ field.
bogdanm 82:6473597d706e 1870 #define BR_SDHC_PROCTL_SABGREQ (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_SABGREQ))
bogdanm 82:6473597d706e 1871 #endif
bogdanm 82:6473597d706e 1872
bogdanm 82:6473597d706e 1873 //! @brief Format value for bitfield SDHC_PROCTL_SABGREQ.
bogdanm 82:6473597d706e 1874 #define BF_SDHC_PROCTL_SABGREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_SABGREQ), uint32_t) & BM_SDHC_PROCTL_SABGREQ)
bogdanm 82:6473597d706e 1875
bogdanm 82:6473597d706e 1876 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1877 //! @brief Set the SABGREQ field to a new value.
bogdanm 82:6473597d706e 1878 #define BW_SDHC_PROCTL_SABGREQ(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_SABGREQ) = (v))
bogdanm 82:6473597d706e 1879 #endif
bogdanm 82:6473597d706e 1880 //@}
bogdanm 82:6473597d706e 1881
bogdanm 82:6473597d706e 1882 /*!
bogdanm 82:6473597d706e 1883 * @name Register SDHC_PROCTL, field CREQ[17] (RW)
bogdanm 82:6473597d706e 1884 *
bogdanm 82:6473597d706e 1885 * Used to restart a transaction which was stopped using the PROCTL[SABGREQ].
bogdanm 82:6473597d706e 1886 * When a suspend operation is not accepted by the card, it is also by setting this
bogdanm 82:6473597d706e 1887 * bit to restart the paused transfer. To cancel stop at the block gap, set
bogdanm 82:6473597d706e 1888 * PROCTL[SABGREQ] to 0 and set this bit to 1 to restart the transfer. The SDHC
bogdanm 82:6473597d706e 1889 * automatically clears this bit, therefore it is not necessary for the host driver to
bogdanm 82:6473597d706e 1890 * set this bit to 0. If both PROCTL[SABGREQ] and this bit are 1, the continue
bogdanm 82:6473597d706e 1891 * request is ignored.
bogdanm 82:6473597d706e 1892 *
bogdanm 82:6473597d706e 1893 * Values:
bogdanm 82:6473597d706e 1894 * - 0 - No effect.
bogdanm 82:6473597d706e 1895 * - 1 - Restart
bogdanm 82:6473597d706e 1896 */
bogdanm 82:6473597d706e 1897 //@{
bogdanm 82:6473597d706e 1898 #define BP_SDHC_PROCTL_CREQ (17U) //!< Bit position for SDHC_PROCTL_CREQ.
bogdanm 82:6473597d706e 1899 #define BM_SDHC_PROCTL_CREQ (0x00020000U) //!< Bit mask for SDHC_PROCTL_CREQ.
bogdanm 82:6473597d706e 1900 #define BS_SDHC_PROCTL_CREQ (1U) //!< Bit field size in bits for SDHC_PROCTL_CREQ.
bogdanm 82:6473597d706e 1901
bogdanm 82:6473597d706e 1902 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1903 //! @brief Read current value of the SDHC_PROCTL_CREQ field.
bogdanm 82:6473597d706e 1904 #define BR_SDHC_PROCTL_CREQ (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CREQ))
bogdanm 82:6473597d706e 1905 #endif
bogdanm 82:6473597d706e 1906
bogdanm 82:6473597d706e 1907 //! @brief Format value for bitfield SDHC_PROCTL_CREQ.
bogdanm 82:6473597d706e 1908 #define BF_SDHC_PROCTL_CREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_CREQ), uint32_t) & BM_SDHC_PROCTL_CREQ)
bogdanm 82:6473597d706e 1909
bogdanm 82:6473597d706e 1910 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1911 //! @brief Set the CREQ field to a new value.
bogdanm 82:6473597d706e 1912 #define BW_SDHC_PROCTL_CREQ(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_CREQ) = (v))
bogdanm 82:6473597d706e 1913 #endif
bogdanm 82:6473597d706e 1914 //@}
bogdanm 82:6473597d706e 1915
bogdanm 82:6473597d706e 1916 /*!
bogdanm 82:6473597d706e 1917 * @name Register SDHC_PROCTL, field RWCTL[18] (RW)
bogdanm 82:6473597d706e 1918 *
bogdanm 82:6473597d706e 1919 * The read wait function is optional for SDIO cards. If the card supports read
bogdanm 82:6473597d706e 1920 * wait, set this bit to enable use of the read wait protocol to stop read data
bogdanm 82:6473597d706e 1921 * using the DAT[2] line. Otherwise, the SDHC has to stop the SD Clock to hold
bogdanm 82:6473597d706e 1922 * read data, which restricts commands generation. When the host driver detects an
bogdanm 82:6473597d706e 1923 * SDIO card insertion, it shall set this bit according to the CCCR of the card.
bogdanm 82:6473597d706e 1924 * If the card does not support read wait, this bit shall never be set to 1,
bogdanm 82:6473597d706e 1925 * otherwise DAT line conflicts may occur. If this bit is set to 0, stop at block gap
bogdanm 82:6473597d706e 1926 * during read operation is also supported, but the SDHC will stop the SD Clock
bogdanm 82:6473597d706e 1927 * to pause reading operation.
bogdanm 82:6473597d706e 1928 *
bogdanm 82:6473597d706e 1929 * Values:
bogdanm 82:6473597d706e 1930 * - 0 - Disable read wait control, and stop SD clock at block gap when SABGREQ
bogdanm 82:6473597d706e 1931 * is set.
bogdanm 82:6473597d706e 1932 * - 1 - Enable read wait control, and assert read wait without stopping SD
bogdanm 82:6473597d706e 1933 * clock at block gap when SABGREQ bit is set.
bogdanm 82:6473597d706e 1934 */
bogdanm 82:6473597d706e 1935 //@{
bogdanm 82:6473597d706e 1936 #define BP_SDHC_PROCTL_RWCTL (18U) //!< Bit position for SDHC_PROCTL_RWCTL.
bogdanm 82:6473597d706e 1937 #define BM_SDHC_PROCTL_RWCTL (0x00040000U) //!< Bit mask for SDHC_PROCTL_RWCTL.
bogdanm 82:6473597d706e 1938 #define BS_SDHC_PROCTL_RWCTL (1U) //!< Bit field size in bits for SDHC_PROCTL_RWCTL.
bogdanm 82:6473597d706e 1939
bogdanm 82:6473597d706e 1940 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1941 //! @brief Read current value of the SDHC_PROCTL_RWCTL field.
bogdanm 82:6473597d706e 1942 #define BR_SDHC_PROCTL_RWCTL (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_RWCTL))
bogdanm 82:6473597d706e 1943 #endif
bogdanm 82:6473597d706e 1944
bogdanm 82:6473597d706e 1945 //! @brief Format value for bitfield SDHC_PROCTL_RWCTL.
bogdanm 82:6473597d706e 1946 #define BF_SDHC_PROCTL_RWCTL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_RWCTL), uint32_t) & BM_SDHC_PROCTL_RWCTL)
bogdanm 82:6473597d706e 1947
bogdanm 82:6473597d706e 1948 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1949 //! @brief Set the RWCTL field to a new value.
bogdanm 82:6473597d706e 1950 #define BW_SDHC_PROCTL_RWCTL(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_RWCTL) = (v))
bogdanm 82:6473597d706e 1951 #endif
bogdanm 82:6473597d706e 1952 //@}
bogdanm 82:6473597d706e 1953
bogdanm 82:6473597d706e 1954 /*!
bogdanm 82:6473597d706e 1955 * @name Register SDHC_PROCTL, field IABG[19] (RW)
bogdanm 82:6473597d706e 1956 *
bogdanm 82:6473597d706e 1957 * Valid only in 4-bit mode, of the SDIO card, and selects a sample point in the
bogdanm 82:6473597d706e 1958 * interrupt cycle. Setting to 1 enables interrupt detection at the block gap
bogdanm 82:6473597d706e 1959 * for a multiple block transfer. Setting to 0 disables interrupt detection during
bogdanm 82:6473597d706e 1960 * a multiple block transfer. If the SDIO card can't signal an interrupt during a
bogdanm 82:6473597d706e 1961 * multiple block transfer, this bit must be set to 0 to avoid an inadvertent
bogdanm 82:6473597d706e 1962 * interrupt. When the host driver detects an SDIO card insertion, it shall set
bogdanm 82:6473597d706e 1963 * this bit according to the CCCR of the card.
bogdanm 82:6473597d706e 1964 *
bogdanm 82:6473597d706e 1965 * Values:
bogdanm 82:6473597d706e 1966 * - 0 - Disabled
bogdanm 82:6473597d706e 1967 * - 1 - Enabled
bogdanm 82:6473597d706e 1968 */
bogdanm 82:6473597d706e 1969 //@{
bogdanm 82:6473597d706e 1970 #define BP_SDHC_PROCTL_IABG (19U) //!< Bit position for SDHC_PROCTL_IABG.
bogdanm 82:6473597d706e 1971 #define BM_SDHC_PROCTL_IABG (0x00080000U) //!< Bit mask for SDHC_PROCTL_IABG.
bogdanm 82:6473597d706e 1972 #define BS_SDHC_PROCTL_IABG (1U) //!< Bit field size in bits for SDHC_PROCTL_IABG.
bogdanm 82:6473597d706e 1973
bogdanm 82:6473597d706e 1974 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1975 //! @brief Read current value of the SDHC_PROCTL_IABG field.
bogdanm 82:6473597d706e 1976 #define BR_SDHC_PROCTL_IABG (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_IABG))
bogdanm 82:6473597d706e 1977 #endif
bogdanm 82:6473597d706e 1978
bogdanm 82:6473597d706e 1979 //! @brief Format value for bitfield SDHC_PROCTL_IABG.
bogdanm 82:6473597d706e 1980 #define BF_SDHC_PROCTL_IABG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_IABG), uint32_t) & BM_SDHC_PROCTL_IABG)
bogdanm 82:6473597d706e 1981
bogdanm 82:6473597d706e 1982 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1983 //! @brief Set the IABG field to a new value.
bogdanm 82:6473597d706e 1984 #define BW_SDHC_PROCTL_IABG(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_IABG) = (v))
bogdanm 82:6473597d706e 1985 #endif
bogdanm 82:6473597d706e 1986 //@}
bogdanm 82:6473597d706e 1987
bogdanm 82:6473597d706e 1988 /*!
bogdanm 82:6473597d706e 1989 * @name Register SDHC_PROCTL, field WECINT[24] (RW)
bogdanm 82:6473597d706e 1990 *
bogdanm 82:6473597d706e 1991 * Enables a wakeup event, via IRQSTAT[CINT]. This bit can be set to 1 if FN_WUS
bogdanm 82:6473597d706e 1992 * (Wake Up Support) in CIS is set to 1. When this bit is set, the card
bogdanm 82:6473597d706e 1993 * interrupt status and the SDHC interrupt can be asserted without SD_CLK toggling. When
bogdanm 82:6473597d706e 1994 * the wakeup feature is not enabled, the SD_CLK must be active to assert the
bogdanm 82:6473597d706e 1995 * card interrupt status and the SDHC interrupt.
bogdanm 82:6473597d706e 1996 *
bogdanm 82:6473597d706e 1997 * Values:
bogdanm 82:6473597d706e 1998 * - 0 - Disabled
bogdanm 82:6473597d706e 1999 * - 1 - Enabled
bogdanm 82:6473597d706e 2000 */
bogdanm 82:6473597d706e 2001 //@{
bogdanm 82:6473597d706e 2002 #define BP_SDHC_PROCTL_WECINT (24U) //!< Bit position for SDHC_PROCTL_WECINT.
bogdanm 82:6473597d706e 2003 #define BM_SDHC_PROCTL_WECINT (0x01000000U) //!< Bit mask for SDHC_PROCTL_WECINT.
bogdanm 82:6473597d706e 2004 #define BS_SDHC_PROCTL_WECINT (1U) //!< Bit field size in bits for SDHC_PROCTL_WECINT.
bogdanm 82:6473597d706e 2005
bogdanm 82:6473597d706e 2006 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2007 //! @brief Read current value of the SDHC_PROCTL_WECINT field.
bogdanm 82:6473597d706e 2008 #define BR_SDHC_PROCTL_WECINT (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINT))
bogdanm 82:6473597d706e 2009 #endif
bogdanm 82:6473597d706e 2010
bogdanm 82:6473597d706e 2011 //! @brief Format value for bitfield SDHC_PROCTL_WECINT.
bogdanm 82:6473597d706e 2012 #define BF_SDHC_PROCTL_WECINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECINT), uint32_t) & BM_SDHC_PROCTL_WECINT)
bogdanm 82:6473597d706e 2013
bogdanm 82:6473597d706e 2014 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2015 //! @brief Set the WECINT field to a new value.
bogdanm 82:6473597d706e 2016 #define BW_SDHC_PROCTL_WECINT(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINT) = (v))
bogdanm 82:6473597d706e 2017 #endif
bogdanm 82:6473597d706e 2018 //@}
bogdanm 82:6473597d706e 2019
bogdanm 82:6473597d706e 2020 /*!
bogdanm 82:6473597d706e 2021 * @name Register SDHC_PROCTL, field WECINS[25] (RW)
bogdanm 82:6473597d706e 2022 *
bogdanm 82:6473597d706e 2023 * Enables a wakeup event, via IRQSTAT[CINS]. FN_WUS (Wake Up Support) in CIS
bogdanm 82:6473597d706e 2024 * does not effect this bit. When this bit is set, IRQSTATEN[CINSEN] and the SDHC
bogdanm 82:6473597d706e 2025 * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is
bogdanm 82:6473597d706e 2026 * not enabled, the SD_CLK must be active to assert IRQSTATEN[CINSEN] and the SDHC
bogdanm 82:6473597d706e 2027 * interrupt.
bogdanm 82:6473597d706e 2028 *
bogdanm 82:6473597d706e 2029 * Values:
bogdanm 82:6473597d706e 2030 * - 0 - Disabled
bogdanm 82:6473597d706e 2031 * - 1 - Enabled
bogdanm 82:6473597d706e 2032 */
bogdanm 82:6473597d706e 2033 //@{
bogdanm 82:6473597d706e 2034 #define BP_SDHC_PROCTL_WECINS (25U) //!< Bit position for SDHC_PROCTL_WECINS.
bogdanm 82:6473597d706e 2035 #define BM_SDHC_PROCTL_WECINS (0x02000000U) //!< Bit mask for SDHC_PROCTL_WECINS.
bogdanm 82:6473597d706e 2036 #define BS_SDHC_PROCTL_WECINS (1U) //!< Bit field size in bits for SDHC_PROCTL_WECINS.
bogdanm 82:6473597d706e 2037
bogdanm 82:6473597d706e 2038 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2039 //! @brief Read current value of the SDHC_PROCTL_WECINS field.
bogdanm 82:6473597d706e 2040 #define BR_SDHC_PROCTL_WECINS (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINS))
bogdanm 82:6473597d706e 2041 #endif
bogdanm 82:6473597d706e 2042
bogdanm 82:6473597d706e 2043 //! @brief Format value for bitfield SDHC_PROCTL_WECINS.
bogdanm 82:6473597d706e 2044 #define BF_SDHC_PROCTL_WECINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECINS), uint32_t) & BM_SDHC_PROCTL_WECINS)
bogdanm 82:6473597d706e 2045
bogdanm 82:6473597d706e 2046 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2047 //! @brief Set the WECINS field to a new value.
bogdanm 82:6473597d706e 2048 #define BW_SDHC_PROCTL_WECINS(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECINS) = (v))
bogdanm 82:6473597d706e 2049 #endif
bogdanm 82:6473597d706e 2050 //@}
bogdanm 82:6473597d706e 2051
bogdanm 82:6473597d706e 2052 /*!
bogdanm 82:6473597d706e 2053 * @name Register SDHC_PROCTL, field WECRM[26] (RW)
bogdanm 82:6473597d706e 2054 *
bogdanm 82:6473597d706e 2055 * Enables a wakeup event, via IRQSTAT[CRM]. FN_WUS (Wake Up Support) in CIS
bogdanm 82:6473597d706e 2056 * does not effect this bit. When this bit is set, IRQSTAT[CRM] and the SDHC
bogdanm 82:6473597d706e 2057 * interrupt can be asserted without SD_CLK toggling. When the wakeup feature is not
bogdanm 82:6473597d706e 2058 * enabled, the SD_CLK must be active to assert IRQSTAT[CRM] and the SDHC interrupt.
bogdanm 82:6473597d706e 2059 *
bogdanm 82:6473597d706e 2060 * Values:
bogdanm 82:6473597d706e 2061 * - 0 - Disabled
bogdanm 82:6473597d706e 2062 * - 1 - Enabled
bogdanm 82:6473597d706e 2063 */
bogdanm 82:6473597d706e 2064 //@{
bogdanm 82:6473597d706e 2065 #define BP_SDHC_PROCTL_WECRM (26U) //!< Bit position for SDHC_PROCTL_WECRM.
bogdanm 82:6473597d706e 2066 #define BM_SDHC_PROCTL_WECRM (0x04000000U) //!< Bit mask for SDHC_PROCTL_WECRM.
bogdanm 82:6473597d706e 2067 #define BS_SDHC_PROCTL_WECRM (1U) //!< Bit field size in bits for SDHC_PROCTL_WECRM.
bogdanm 82:6473597d706e 2068
bogdanm 82:6473597d706e 2069 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2070 //! @brief Read current value of the SDHC_PROCTL_WECRM field.
bogdanm 82:6473597d706e 2071 #define BR_SDHC_PROCTL_WECRM (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECRM))
bogdanm 82:6473597d706e 2072 #endif
bogdanm 82:6473597d706e 2073
bogdanm 82:6473597d706e 2074 //! @brief Format value for bitfield SDHC_PROCTL_WECRM.
bogdanm 82:6473597d706e 2075 #define BF_SDHC_PROCTL_WECRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_PROCTL_WECRM), uint32_t) & BM_SDHC_PROCTL_WECRM)
bogdanm 82:6473597d706e 2076
bogdanm 82:6473597d706e 2077 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2078 //! @brief Set the WECRM field to a new value.
bogdanm 82:6473597d706e 2079 #define BW_SDHC_PROCTL_WECRM(v) (BITBAND_ACCESS32(HW_SDHC_PROCTL_ADDR, BP_SDHC_PROCTL_WECRM) = (v))
bogdanm 82:6473597d706e 2080 #endif
bogdanm 82:6473597d706e 2081 //@}
bogdanm 82:6473597d706e 2082
bogdanm 82:6473597d706e 2083 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2084 // HW_SDHC_SYSCTL - System Control register
bogdanm 82:6473597d706e 2085 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2086
bogdanm 82:6473597d706e 2087 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2088 /*!
bogdanm 82:6473597d706e 2089 * @brief HW_SDHC_SYSCTL - System Control register (RW)
bogdanm 82:6473597d706e 2090 *
bogdanm 82:6473597d706e 2091 * Reset value: 0x00008008U
bogdanm 82:6473597d706e 2092 */
bogdanm 82:6473597d706e 2093 typedef union _hw_sdhc_sysctl
bogdanm 82:6473597d706e 2094 {
bogdanm 82:6473597d706e 2095 uint32_t U;
bogdanm 82:6473597d706e 2096 struct _hw_sdhc_sysctl_bitfields
bogdanm 82:6473597d706e 2097 {
bogdanm 82:6473597d706e 2098 uint32_t IPGEN : 1; //!< [0] IPG Clock Enable
bogdanm 82:6473597d706e 2099 uint32_t HCKEN : 1; //!< [1] System Clock Enable
bogdanm 82:6473597d706e 2100 uint32_t PEREN : 1; //!< [2] Peripheral Clock Enable
bogdanm 82:6473597d706e 2101 uint32_t SDCLKEN : 1; //!< [3] SD Clock Enable
bogdanm 82:6473597d706e 2102 uint32_t DVS : 4; //!< [7:4] Divisor
bogdanm 82:6473597d706e 2103 uint32_t SDCLKFS : 8; //!< [15:8] SDCLK Frequency Select
bogdanm 82:6473597d706e 2104 uint32_t DTOCV : 4; //!< [19:16] Data Timeout Counter Value
bogdanm 82:6473597d706e 2105 uint32_t RESERVED0 : 4; //!< [23:20]
bogdanm 82:6473597d706e 2106 uint32_t RSTA : 1; //!< [24] Software Reset For ALL
bogdanm 82:6473597d706e 2107 uint32_t RSTC : 1; //!< [25] Software Reset For CMD Line
bogdanm 82:6473597d706e 2108 uint32_t RSTD : 1; //!< [26] Software Reset For DAT Line
bogdanm 82:6473597d706e 2109 uint32_t INITA : 1; //!< [27] Initialization Active
bogdanm 82:6473597d706e 2110 uint32_t RESERVED1 : 4; //!< [31:28]
bogdanm 82:6473597d706e 2111 } B;
bogdanm 82:6473597d706e 2112 } hw_sdhc_sysctl_t;
bogdanm 82:6473597d706e 2113 #endif
bogdanm 82:6473597d706e 2114
bogdanm 82:6473597d706e 2115 /*!
bogdanm 82:6473597d706e 2116 * @name Constants and macros for entire SDHC_SYSCTL register
bogdanm 82:6473597d706e 2117 */
bogdanm 82:6473597d706e 2118 //@{
bogdanm 82:6473597d706e 2119 #define HW_SDHC_SYSCTL_ADDR (REGS_SDHC_BASE + 0x2CU)
bogdanm 82:6473597d706e 2120
bogdanm 82:6473597d706e 2121 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2122 #define HW_SDHC_SYSCTL (*(__IO hw_sdhc_sysctl_t *) HW_SDHC_SYSCTL_ADDR)
bogdanm 82:6473597d706e 2123 #define HW_SDHC_SYSCTL_RD() (HW_SDHC_SYSCTL.U)
bogdanm 82:6473597d706e 2124 #define HW_SDHC_SYSCTL_WR(v) (HW_SDHC_SYSCTL.U = (v))
bogdanm 82:6473597d706e 2125 #define HW_SDHC_SYSCTL_SET(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() | (v)))
bogdanm 82:6473597d706e 2126 #define HW_SDHC_SYSCTL_CLR(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() & ~(v)))
bogdanm 82:6473597d706e 2127 #define HW_SDHC_SYSCTL_TOG(v) (HW_SDHC_SYSCTL_WR(HW_SDHC_SYSCTL_RD() ^ (v)))
bogdanm 82:6473597d706e 2128 #endif
bogdanm 82:6473597d706e 2129 //@}
bogdanm 82:6473597d706e 2130
bogdanm 82:6473597d706e 2131 /*
bogdanm 82:6473597d706e 2132 * Constants & macros for individual SDHC_SYSCTL bitfields
bogdanm 82:6473597d706e 2133 */
bogdanm 82:6473597d706e 2134
bogdanm 82:6473597d706e 2135 /*!
bogdanm 82:6473597d706e 2136 * @name Register SDHC_SYSCTL, field IPGEN[0] (RW)
bogdanm 82:6473597d706e 2137 *
bogdanm 82:6473597d706e 2138 * If this bit is set, bus clock will always be active and no automatic gating
bogdanm 82:6473597d706e 2139 * is applied. The bus clock will be internally gated off, if none of the
bogdanm 82:6473597d706e 2140 * following factors are met: The cmd part is reset, or Data part is reset, or Soft
bogdanm 82:6473597d706e 2141 * reset, or The cmd is about to send, or Clock divisor is just updated, or Continue
bogdanm 82:6473597d706e 2142 * request is just set, or This bit is set, or Card insertion is detected, or Card
bogdanm 82:6473597d706e 2143 * removal is detected, or Card external interrupt is detected, or The SDHC
bogdanm 82:6473597d706e 2144 * clock is not gated off The bus clock will not be auto gated off if the SDHC clock
bogdanm 82:6473597d706e 2145 * is not gated off. So clearing only this bit has no effect unless the PEREN bit
bogdanm 82:6473597d706e 2146 * is also cleared.
bogdanm 82:6473597d706e 2147 *
bogdanm 82:6473597d706e 2148 * Values:
bogdanm 82:6473597d706e 2149 * - 0 - Bus clock will be internally gated off.
bogdanm 82:6473597d706e 2150 * - 1 - Bus clock will not be automatically gated off.
bogdanm 82:6473597d706e 2151 */
bogdanm 82:6473597d706e 2152 //@{
bogdanm 82:6473597d706e 2153 #define BP_SDHC_SYSCTL_IPGEN (0U) //!< Bit position for SDHC_SYSCTL_IPGEN.
bogdanm 82:6473597d706e 2154 #define BM_SDHC_SYSCTL_IPGEN (0x00000001U) //!< Bit mask for SDHC_SYSCTL_IPGEN.
bogdanm 82:6473597d706e 2155 #define BS_SDHC_SYSCTL_IPGEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_IPGEN.
bogdanm 82:6473597d706e 2156
bogdanm 82:6473597d706e 2157 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2158 //! @brief Read current value of the SDHC_SYSCTL_IPGEN field.
bogdanm 82:6473597d706e 2159 #define BR_SDHC_SYSCTL_IPGEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_IPGEN))
bogdanm 82:6473597d706e 2160 #endif
bogdanm 82:6473597d706e 2161
bogdanm 82:6473597d706e 2162 //! @brief Format value for bitfield SDHC_SYSCTL_IPGEN.
bogdanm 82:6473597d706e 2163 #define BF_SDHC_SYSCTL_IPGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_IPGEN), uint32_t) & BM_SDHC_SYSCTL_IPGEN)
bogdanm 82:6473597d706e 2164
bogdanm 82:6473597d706e 2165 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2166 //! @brief Set the IPGEN field to a new value.
bogdanm 82:6473597d706e 2167 #define BW_SDHC_SYSCTL_IPGEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_IPGEN) = (v))
bogdanm 82:6473597d706e 2168 #endif
bogdanm 82:6473597d706e 2169 //@}
bogdanm 82:6473597d706e 2170
bogdanm 82:6473597d706e 2171 /*!
bogdanm 82:6473597d706e 2172 * @name Register SDHC_SYSCTL, field HCKEN[1] (RW)
bogdanm 82:6473597d706e 2173 *
bogdanm 82:6473597d706e 2174 * If this bit is set, system clock will always be active and no automatic
bogdanm 82:6473597d706e 2175 * gating is applied. When this bit is cleared, system clock will be automatically off
bogdanm 82:6473597d706e 2176 * when no data transfer is on the SD bus.
bogdanm 82:6473597d706e 2177 *
bogdanm 82:6473597d706e 2178 * Values:
bogdanm 82:6473597d706e 2179 * - 0 - System clock will be internally gated off.
bogdanm 82:6473597d706e 2180 * - 1 - System clock will not be automatically gated off.
bogdanm 82:6473597d706e 2181 */
bogdanm 82:6473597d706e 2182 //@{
bogdanm 82:6473597d706e 2183 #define BP_SDHC_SYSCTL_HCKEN (1U) //!< Bit position for SDHC_SYSCTL_HCKEN.
bogdanm 82:6473597d706e 2184 #define BM_SDHC_SYSCTL_HCKEN (0x00000002U) //!< Bit mask for SDHC_SYSCTL_HCKEN.
bogdanm 82:6473597d706e 2185 #define BS_SDHC_SYSCTL_HCKEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_HCKEN.
bogdanm 82:6473597d706e 2186
bogdanm 82:6473597d706e 2187 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2188 //! @brief Read current value of the SDHC_SYSCTL_HCKEN field.
bogdanm 82:6473597d706e 2189 #define BR_SDHC_SYSCTL_HCKEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_HCKEN))
bogdanm 82:6473597d706e 2190 #endif
bogdanm 82:6473597d706e 2191
bogdanm 82:6473597d706e 2192 //! @brief Format value for bitfield SDHC_SYSCTL_HCKEN.
bogdanm 82:6473597d706e 2193 #define BF_SDHC_SYSCTL_HCKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_HCKEN), uint32_t) & BM_SDHC_SYSCTL_HCKEN)
bogdanm 82:6473597d706e 2194
bogdanm 82:6473597d706e 2195 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2196 //! @brief Set the HCKEN field to a new value.
bogdanm 82:6473597d706e 2197 #define BW_SDHC_SYSCTL_HCKEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_HCKEN) = (v))
bogdanm 82:6473597d706e 2198 #endif
bogdanm 82:6473597d706e 2199 //@}
bogdanm 82:6473597d706e 2200
bogdanm 82:6473597d706e 2201 /*!
bogdanm 82:6473597d706e 2202 * @name Register SDHC_SYSCTL, field PEREN[2] (RW)
bogdanm 82:6473597d706e 2203 *
bogdanm 82:6473597d706e 2204 * If this bit is set, SDHC clock will always be active and no automatic gating
bogdanm 82:6473597d706e 2205 * is applied. Thus the SDCLK is active except for when auto gating-off during
bogdanm 82:6473597d706e 2206 * buffer danger (buffer about to over-run or under-run). When this bit is cleared,
bogdanm 82:6473597d706e 2207 * the SDHC clock will be automatically off whenever there is no transaction on
bogdanm 82:6473597d706e 2208 * the SD bus. Because this bit is only a feature enabling bit, clearing this bit
bogdanm 82:6473597d706e 2209 * does not stop SDCLK immediately. The SDHC clock will be internally gated off,
bogdanm 82:6473597d706e 2210 * if none of the following factors are met: The cmd part is reset, or Data part
bogdanm 82:6473597d706e 2211 * is reset, or A soft reset, or The cmd is about to send, or Clock divisor is
bogdanm 82:6473597d706e 2212 * just updated, or Continue request is just set, or This bit is set, or Card
bogdanm 82:6473597d706e 2213 * insertion is detected, or Card removal is detected, or Card external interrupt is
bogdanm 82:6473597d706e 2214 * detected, or 80 clocks for initialization phase is ongoing
bogdanm 82:6473597d706e 2215 *
bogdanm 82:6473597d706e 2216 * Values:
bogdanm 82:6473597d706e 2217 * - 0 - SDHC clock will be internally gated off.
bogdanm 82:6473597d706e 2218 * - 1 - SDHC clock will not be automatically gated off.
bogdanm 82:6473597d706e 2219 */
bogdanm 82:6473597d706e 2220 //@{
bogdanm 82:6473597d706e 2221 #define BP_SDHC_SYSCTL_PEREN (2U) //!< Bit position for SDHC_SYSCTL_PEREN.
bogdanm 82:6473597d706e 2222 #define BM_SDHC_SYSCTL_PEREN (0x00000004U) //!< Bit mask for SDHC_SYSCTL_PEREN.
bogdanm 82:6473597d706e 2223 #define BS_SDHC_SYSCTL_PEREN (1U) //!< Bit field size in bits for SDHC_SYSCTL_PEREN.
bogdanm 82:6473597d706e 2224
bogdanm 82:6473597d706e 2225 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2226 //! @brief Read current value of the SDHC_SYSCTL_PEREN field.
bogdanm 82:6473597d706e 2227 #define BR_SDHC_SYSCTL_PEREN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_PEREN))
bogdanm 82:6473597d706e 2228 #endif
bogdanm 82:6473597d706e 2229
bogdanm 82:6473597d706e 2230 //! @brief Format value for bitfield SDHC_SYSCTL_PEREN.
bogdanm 82:6473597d706e 2231 #define BF_SDHC_SYSCTL_PEREN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_PEREN), uint32_t) & BM_SDHC_SYSCTL_PEREN)
bogdanm 82:6473597d706e 2232
bogdanm 82:6473597d706e 2233 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2234 //! @brief Set the PEREN field to a new value.
bogdanm 82:6473597d706e 2235 #define BW_SDHC_SYSCTL_PEREN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_PEREN) = (v))
bogdanm 82:6473597d706e 2236 #endif
bogdanm 82:6473597d706e 2237 //@}
bogdanm 82:6473597d706e 2238
bogdanm 82:6473597d706e 2239 /*!
bogdanm 82:6473597d706e 2240 * @name Register SDHC_SYSCTL, field SDCLKEN[3] (RW)
bogdanm 82:6473597d706e 2241 *
bogdanm 82:6473597d706e 2242 * The host controller shall stop SDCLK when writing this bit to 0. SDCLK
bogdanm 82:6473597d706e 2243 * frequency can be changed when this bit is 0. Then, the host controller shall
bogdanm 82:6473597d706e 2244 * maintain the same clock frequency until SDCLK is stopped (stop at SDCLK = 0). If the
bogdanm 82:6473597d706e 2245 * IRQSTAT[CINS] is cleared, this bit must be cleared by the host driver to save
bogdanm 82:6473597d706e 2246 * power.
bogdanm 82:6473597d706e 2247 */
bogdanm 82:6473597d706e 2248 //@{
bogdanm 82:6473597d706e 2249 #define BP_SDHC_SYSCTL_SDCLKEN (3U) //!< Bit position for SDHC_SYSCTL_SDCLKEN.
bogdanm 82:6473597d706e 2250 #define BM_SDHC_SYSCTL_SDCLKEN (0x00000008U) //!< Bit mask for SDHC_SYSCTL_SDCLKEN.
bogdanm 82:6473597d706e 2251 #define BS_SDHC_SYSCTL_SDCLKEN (1U) //!< Bit field size in bits for SDHC_SYSCTL_SDCLKEN.
bogdanm 82:6473597d706e 2252
bogdanm 82:6473597d706e 2253 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2254 //! @brief Read current value of the SDHC_SYSCTL_SDCLKEN field.
bogdanm 82:6473597d706e 2255 #define BR_SDHC_SYSCTL_SDCLKEN (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_SDCLKEN))
bogdanm 82:6473597d706e 2256 #endif
bogdanm 82:6473597d706e 2257
bogdanm 82:6473597d706e 2258 //! @brief Format value for bitfield SDHC_SYSCTL_SDCLKEN.
bogdanm 82:6473597d706e 2259 #define BF_SDHC_SYSCTL_SDCLKEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_SDCLKEN), uint32_t) & BM_SDHC_SYSCTL_SDCLKEN)
bogdanm 82:6473597d706e 2260
bogdanm 82:6473597d706e 2261 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2262 //! @brief Set the SDCLKEN field to a new value.
bogdanm 82:6473597d706e 2263 #define BW_SDHC_SYSCTL_SDCLKEN(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_SDCLKEN) = (v))
bogdanm 82:6473597d706e 2264 #endif
bogdanm 82:6473597d706e 2265 //@}
bogdanm 82:6473597d706e 2266
bogdanm 82:6473597d706e 2267 /*!
bogdanm 82:6473597d706e 2268 * @name Register SDHC_SYSCTL, field DVS[7:4] (RW)
bogdanm 82:6473597d706e 2269 *
bogdanm 82:6473597d706e 2270 * Used to provide a more exact divisor to generate the desired SD clock
bogdanm 82:6473597d706e 2271 * frequency. Note the divider can even support odd divisor without deterioration of
bogdanm 82:6473597d706e 2272 * duty cycle. The setting are as following:
bogdanm 82:6473597d706e 2273 *
bogdanm 82:6473597d706e 2274 * Values:
bogdanm 82:6473597d706e 2275 * - 0 - Divisor by 1.
bogdanm 82:6473597d706e 2276 * - 1 - Divisor by 2.
bogdanm 82:6473597d706e 2277 * - 1110 - Divisor by 15.
bogdanm 82:6473597d706e 2278 * - 1111 - Divisor by 16.
bogdanm 82:6473597d706e 2279 */
bogdanm 82:6473597d706e 2280 //@{
bogdanm 82:6473597d706e 2281 #define BP_SDHC_SYSCTL_DVS (4U) //!< Bit position for SDHC_SYSCTL_DVS.
bogdanm 82:6473597d706e 2282 #define BM_SDHC_SYSCTL_DVS (0x000000F0U) //!< Bit mask for SDHC_SYSCTL_DVS.
bogdanm 82:6473597d706e 2283 #define BS_SDHC_SYSCTL_DVS (4U) //!< Bit field size in bits for SDHC_SYSCTL_DVS.
bogdanm 82:6473597d706e 2284
bogdanm 82:6473597d706e 2285 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2286 //! @brief Read current value of the SDHC_SYSCTL_DVS field.
bogdanm 82:6473597d706e 2287 #define BR_SDHC_SYSCTL_DVS (HW_SDHC_SYSCTL.B.DVS)
bogdanm 82:6473597d706e 2288 #endif
bogdanm 82:6473597d706e 2289
bogdanm 82:6473597d706e 2290 //! @brief Format value for bitfield SDHC_SYSCTL_DVS.
bogdanm 82:6473597d706e 2291 #define BF_SDHC_SYSCTL_DVS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_DVS), uint32_t) & BM_SDHC_SYSCTL_DVS)
bogdanm 82:6473597d706e 2292
bogdanm 82:6473597d706e 2293 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2294 //! @brief Set the DVS field to a new value.
bogdanm 82:6473597d706e 2295 #define BW_SDHC_SYSCTL_DVS(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_DVS) | BF_SDHC_SYSCTL_DVS(v)))
bogdanm 82:6473597d706e 2296 #endif
bogdanm 82:6473597d706e 2297 //@}
bogdanm 82:6473597d706e 2298
bogdanm 82:6473597d706e 2299 /*!
bogdanm 82:6473597d706e 2300 * @name Register SDHC_SYSCTL, field SDCLKFS[15:8] (RW)
bogdanm 82:6473597d706e 2301 *
bogdanm 82:6473597d706e 2302 * Used to select the frequency of the SDCLK pin. The frequency is not
bogdanm 82:6473597d706e 2303 * programmed directly. Rather this register holds the prescaler (this register) and
bogdanm 82:6473597d706e 2304 * divisor (next register) of the base clock frequency register. Setting 00h bypasses
bogdanm 82:6473597d706e 2305 * the frequency prescaler of the SD Clock. Multiple bits must not be set, or the
bogdanm 82:6473597d706e 2306 * behavior of this prescaler is undefined. The two default divider values can
bogdanm 82:6473597d706e 2307 * be calculated by the frequency of SDHC clock and the following divisor bits.
bogdanm 82:6473597d706e 2308 * The frequency of SDCLK is set by the following formula: Clock frequency = (Base
bogdanm 82:6473597d706e 2309 * clock) / (prescaler x divisor) For example, if the base clock frequency is 96
bogdanm 82:6473597d706e 2310 * MHz, and the target frequency is 25 MHz, then choosing the prescaler value of
bogdanm 82:6473597d706e 2311 * 01h and divisor value of 1h will yield 24 MHz, which is the nearest frequency
bogdanm 82:6473597d706e 2312 * less than or equal to the target. Similarly, to approach a clock value of 400
bogdanm 82:6473597d706e 2313 * kHz, the prescaler value of 08h and divisor value of eh yields the exact clock
bogdanm 82:6473597d706e 2314 * value of 400 kHz. The reset value of this field is 80h, so if the input base
bogdanm 82:6473597d706e 2315 * clock ( SDHC clock ) is about 96 MHz, the default SD clock after reset is 375
bogdanm 82:6473597d706e 2316 * kHz. According to the SD Physical Specification Version 1.1 and the SDIO Card
bogdanm 82:6473597d706e 2317 * Specification Version 1.2, the maximum SD clock frequency is 50 MHz and shall
bogdanm 82:6473597d706e 2318 * never exceed this limit. Only the following settings are allowed:
bogdanm 82:6473597d706e 2319 *
bogdanm 82:6473597d706e 2320 * Values:
bogdanm 82:6473597d706e 2321 * - 1 - Base clock divided by 2.
bogdanm 82:6473597d706e 2322 * - 10 - Base clock divided by 4.
bogdanm 82:6473597d706e 2323 * - 100 - Base clock divided by 8.
bogdanm 82:6473597d706e 2324 * - 1000 - Base clock divided by 16.
bogdanm 82:6473597d706e 2325 * - 10000 - Base clock divided by 32.
bogdanm 82:6473597d706e 2326 * - 100000 - Base clock divided by 64.
bogdanm 82:6473597d706e 2327 * - 1000000 - Base clock divided by 128.
bogdanm 82:6473597d706e 2328 * - 10000000 - Base clock divided by 256.
bogdanm 82:6473597d706e 2329 */
bogdanm 82:6473597d706e 2330 //@{
bogdanm 82:6473597d706e 2331 #define BP_SDHC_SYSCTL_SDCLKFS (8U) //!< Bit position for SDHC_SYSCTL_SDCLKFS.
bogdanm 82:6473597d706e 2332 #define BM_SDHC_SYSCTL_SDCLKFS (0x0000FF00U) //!< Bit mask for SDHC_SYSCTL_SDCLKFS.
bogdanm 82:6473597d706e 2333 #define BS_SDHC_SYSCTL_SDCLKFS (8U) //!< Bit field size in bits for SDHC_SYSCTL_SDCLKFS.
bogdanm 82:6473597d706e 2334
bogdanm 82:6473597d706e 2335 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2336 //! @brief Read current value of the SDHC_SYSCTL_SDCLKFS field.
bogdanm 82:6473597d706e 2337 #define BR_SDHC_SYSCTL_SDCLKFS (HW_SDHC_SYSCTL.B.SDCLKFS)
bogdanm 82:6473597d706e 2338 #endif
bogdanm 82:6473597d706e 2339
bogdanm 82:6473597d706e 2340 //! @brief Format value for bitfield SDHC_SYSCTL_SDCLKFS.
bogdanm 82:6473597d706e 2341 #define BF_SDHC_SYSCTL_SDCLKFS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_SDCLKFS), uint32_t) & BM_SDHC_SYSCTL_SDCLKFS)
bogdanm 82:6473597d706e 2342
bogdanm 82:6473597d706e 2343 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2344 //! @brief Set the SDCLKFS field to a new value.
bogdanm 82:6473597d706e 2345 #define BW_SDHC_SYSCTL_SDCLKFS(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_SDCLKFS) | BF_SDHC_SYSCTL_SDCLKFS(v)))
bogdanm 82:6473597d706e 2346 #endif
bogdanm 82:6473597d706e 2347 //@}
bogdanm 82:6473597d706e 2348
bogdanm 82:6473597d706e 2349 /*!
bogdanm 82:6473597d706e 2350 * @name Register SDHC_SYSCTL, field DTOCV[19:16] (RW)
bogdanm 82:6473597d706e 2351 *
bogdanm 82:6473597d706e 2352 * Determines the interval by which DAT line timeouts are detected. See
bogdanm 82:6473597d706e 2353 * IRQSTAT[DTOE] for information on factors that dictate time-out generation. Time-out
bogdanm 82:6473597d706e 2354 * clock frequency will be generated by dividing the base clock SDCLK value by this
bogdanm 82:6473597d706e 2355 * value. The host driver can clear IRQSTATEN[DTOESEN] to prevent inadvertent
bogdanm 82:6473597d706e 2356 * time-out events.
bogdanm 82:6473597d706e 2357 *
bogdanm 82:6473597d706e 2358 * Values:
bogdanm 82:6473597d706e 2359 * - 0000 - SDCLK x 2 13
bogdanm 82:6473597d706e 2360 * - 0001 - SDCLK x 2 14
bogdanm 82:6473597d706e 2361 * - 1110 - SDCLK x 2 27
bogdanm 82:6473597d706e 2362 * - 1111 - Reserved
bogdanm 82:6473597d706e 2363 */
bogdanm 82:6473597d706e 2364 //@{
bogdanm 82:6473597d706e 2365 #define BP_SDHC_SYSCTL_DTOCV (16U) //!< Bit position for SDHC_SYSCTL_DTOCV.
bogdanm 82:6473597d706e 2366 #define BM_SDHC_SYSCTL_DTOCV (0x000F0000U) //!< Bit mask for SDHC_SYSCTL_DTOCV.
bogdanm 82:6473597d706e 2367 #define BS_SDHC_SYSCTL_DTOCV (4U) //!< Bit field size in bits for SDHC_SYSCTL_DTOCV.
bogdanm 82:6473597d706e 2368
bogdanm 82:6473597d706e 2369 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2370 //! @brief Read current value of the SDHC_SYSCTL_DTOCV field.
bogdanm 82:6473597d706e 2371 #define BR_SDHC_SYSCTL_DTOCV (HW_SDHC_SYSCTL.B.DTOCV)
bogdanm 82:6473597d706e 2372 #endif
bogdanm 82:6473597d706e 2373
bogdanm 82:6473597d706e 2374 //! @brief Format value for bitfield SDHC_SYSCTL_DTOCV.
bogdanm 82:6473597d706e 2375 #define BF_SDHC_SYSCTL_DTOCV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_DTOCV), uint32_t) & BM_SDHC_SYSCTL_DTOCV)
bogdanm 82:6473597d706e 2376
bogdanm 82:6473597d706e 2377 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2378 //! @brief Set the DTOCV field to a new value.
bogdanm 82:6473597d706e 2379 #define BW_SDHC_SYSCTL_DTOCV(v) (HW_SDHC_SYSCTL_WR((HW_SDHC_SYSCTL_RD() & ~BM_SDHC_SYSCTL_DTOCV) | BF_SDHC_SYSCTL_DTOCV(v)))
bogdanm 82:6473597d706e 2380 #endif
bogdanm 82:6473597d706e 2381 //@}
bogdanm 82:6473597d706e 2382
bogdanm 82:6473597d706e 2383 /*!
bogdanm 82:6473597d706e 2384 * @name Register SDHC_SYSCTL, field RSTA[24] (WORZ)
bogdanm 82:6473597d706e 2385 *
bogdanm 82:6473597d706e 2386 * Effects the entire host controller except for the card detection circuit.
bogdanm 82:6473597d706e 2387 * Register bits of type ROC, RW, RW1C, RWAC are cleared. During its initialization,
bogdanm 82:6473597d706e 2388 * the host driver shall set this bit to 1 to reset the SDHC. The SDHC shall
bogdanm 82:6473597d706e 2389 * reset this bit to 0 when the capabilities registers are valid and the host driver
bogdanm 82:6473597d706e 2390 * can read them. Additional use of software reset for all does not affect the
bogdanm 82:6473597d706e 2391 * value of the capabilities registers. After this bit is set, it is recommended
bogdanm 82:6473597d706e 2392 * that the host driver reset the external card and reinitialize it.
bogdanm 82:6473597d706e 2393 *
bogdanm 82:6473597d706e 2394 * Values:
bogdanm 82:6473597d706e 2395 * - 0 - No reset.
bogdanm 82:6473597d706e 2396 * - 1 - Reset.
bogdanm 82:6473597d706e 2397 */
bogdanm 82:6473597d706e 2398 //@{
bogdanm 82:6473597d706e 2399 #define BP_SDHC_SYSCTL_RSTA (24U) //!< Bit position for SDHC_SYSCTL_RSTA.
bogdanm 82:6473597d706e 2400 #define BM_SDHC_SYSCTL_RSTA (0x01000000U) //!< Bit mask for SDHC_SYSCTL_RSTA.
bogdanm 82:6473597d706e 2401 #define BS_SDHC_SYSCTL_RSTA (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTA.
bogdanm 82:6473597d706e 2402
bogdanm 82:6473597d706e 2403 //! @brief Format value for bitfield SDHC_SYSCTL_RSTA.
bogdanm 82:6473597d706e 2404 #define BF_SDHC_SYSCTL_RSTA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTA), uint32_t) & BM_SDHC_SYSCTL_RSTA)
bogdanm 82:6473597d706e 2405
bogdanm 82:6473597d706e 2406 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2407 //! @brief Set the RSTA field to a new value.
bogdanm 82:6473597d706e 2408 #define BW_SDHC_SYSCTL_RSTA(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTA) = (v))
bogdanm 82:6473597d706e 2409 #endif
bogdanm 82:6473597d706e 2410 //@}
bogdanm 82:6473597d706e 2411
bogdanm 82:6473597d706e 2412 /*!
bogdanm 82:6473597d706e 2413 * @name Register SDHC_SYSCTL, field RSTC[25] (WORZ)
bogdanm 82:6473597d706e 2414 *
bogdanm 82:6473597d706e 2415 * Only part of the command circuit is reset. The following registers and bits
bogdanm 82:6473597d706e 2416 * are cleared by this bit: PRSSTAT[CIHB] IRQSTAT[CC]
bogdanm 82:6473597d706e 2417 *
bogdanm 82:6473597d706e 2418 * Values:
bogdanm 82:6473597d706e 2419 * - 0 - No reset.
bogdanm 82:6473597d706e 2420 * - 1 - Reset.
bogdanm 82:6473597d706e 2421 */
bogdanm 82:6473597d706e 2422 //@{
bogdanm 82:6473597d706e 2423 #define BP_SDHC_SYSCTL_RSTC (25U) //!< Bit position for SDHC_SYSCTL_RSTC.
bogdanm 82:6473597d706e 2424 #define BM_SDHC_SYSCTL_RSTC (0x02000000U) //!< Bit mask for SDHC_SYSCTL_RSTC.
bogdanm 82:6473597d706e 2425 #define BS_SDHC_SYSCTL_RSTC (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTC.
bogdanm 82:6473597d706e 2426
bogdanm 82:6473597d706e 2427 //! @brief Format value for bitfield SDHC_SYSCTL_RSTC.
bogdanm 82:6473597d706e 2428 #define BF_SDHC_SYSCTL_RSTC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTC), uint32_t) & BM_SDHC_SYSCTL_RSTC)
bogdanm 82:6473597d706e 2429
bogdanm 82:6473597d706e 2430 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2431 //! @brief Set the RSTC field to a new value.
bogdanm 82:6473597d706e 2432 #define BW_SDHC_SYSCTL_RSTC(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTC) = (v))
bogdanm 82:6473597d706e 2433 #endif
bogdanm 82:6473597d706e 2434 //@}
bogdanm 82:6473597d706e 2435
bogdanm 82:6473597d706e 2436 /*!
bogdanm 82:6473597d706e 2437 * @name Register SDHC_SYSCTL, field RSTD[26] (WORZ)
bogdanm 82:6473597d706e 2438 *
bogdanm 82:6473597d706e 2439 * Only part of the data circuit is reset. DMA circuit is also reset. The
bogdanm 82:6473597d706e 2440 * following registers and bits are cleared by this bit: Data Port register Buffer Is
bogdanm 82:6473597d706e 2441 * Cleared And Initialized.Present State register Buffer Read Enable Buffer Write
bogdanm 82:6473597d706e 2442 * Enable Read Transfer Active Write Transfer Active DAT Line Active Command
bogdanm 82:6473597d706e 2443 * Inhibit (DAT) Protocol Control register Continue Request Stop At Block Gap Request
bogdanm 82:6473597d706e 2444 * Interrupt Status register Buffer Read Ready Buffer Write Ready DMA Interrupt
bogdanm 82:6473597d706e 2445 * Block Gap Event Transfer Complete
bogdanm 82:6473597d706e 2446 *
bogdanm 82:6473597d706e 2447 * Values:
bogdanm 82:6473597d706e 2448 * - 0 - No reset.
bogdanm 82:6473597d706e 2449 * - 1 - Reset.
bogdanm 82:6473597d706e 2450 */
bogdanm 82:6473597d706e 2451 //@{
bogdanm 82:6473597d706e 2452 #define BP_SDHC_SYSCTL_RSTD (26U) //!< Bit position for SDHC_SYSCTL_RSTD.
bogdanm 82:6473597d706e 2453 #define BM_SDHC_SYSCTL_RSTD (0x04000000U) //!< Bit mask for SDHC_SYSCTL_RSTD.
bogdanm 82:6473597d706e 2454 #define BS_SDHC_SYSCTL_RSTD (1U) //!< Bit field size in bits for SDHC_SYSCTL_RSTD.
bogdanm 82:6473597d706e 2455
bogdanm 82:6473597d706e 2456 //! @brief Format value for bitfield SDHC_SYSCTL_RSTD.
bogdanm 82:6473597d706e 2457 #define BF_SDHC_SYSCTL_RSTD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_RSTD), uint32_t) & BM_SDHC_SYSCTL_RSTD)
bogdanm 82:6473597d706e 2458
bogdanm 82:6473597d706e 2459 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2460 //! @brief Set the RSTD field to a new value.
bogdanm 82:6473597d706e 2461 #define BW_SDHC_SYSCTL_RSTD(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_RSTD) = (v))
bogdanm 82:6473597d706e 2462 #endif
bogdanm 82:6473597d706e 2463 //@}
bogdanm 82:6473597d706e 2464
bogdanm 82:6473597d706e 2465 /*!
bogdanm 82:6473597d706e 2466 * @name Register SDHC_SYSCTL, field INITA[27] (RW)
bogdanm 82:6473597d706e 2467 *
bogdanm 82:6473597d706e 2468 * When this bit is set, 80 SD-clocks are sent to the card. After the 80 clocks
bogdanm 82:6473597d706e 2469 * are sent, this bit is self-cleared. This bit is very useful during the card
bogdanm 82:6473597d706e 2470 * power-up period when 74 SD-clocks are needed and the clock auto gating feature
bogdanm 82:6473597d706e 2471 * is enabled. Writing 1 to this bit when this bit is already 1 has no effect.
bogdanm 82:6473597d706e 2472 * Writing 0 to this bit at any time has no effect. When either of the PRSSTAT[CIHB]
bogdanm 82:6473597d706e 2473 * and PRSSTAT[CDIHB] bits are set, writing 1 to this bit is ignored, that is,
bogdanm 82:6473597d706e 2474 * when command line or data lines are active, write to this bit is not allowed.
bogdanm 82:6473597d706e 2475 * On the otherhand, when this bit is set, that is, during intialization active
bogdanm 82:6473597d706e 2476 * period, it is allowed to issue command, and the command bit stream will appear
bogdanm 82:6473597d706e 2477 * on the CMD pad after all 80 clock cycles are done. So when this command ends,
bogdanm 82:6473597d706e 2478 * the driver can make sure the 80 clock cycles are sent out. This is very useful
bogdanm 82:6473597d706e 2479 * when the driver needs send 80 cycles to the card and does not want to wait
bogdanm 82:6473597d706e 2480 * till this bit is self-cleared.
bogdanm 82:6473597d706e 2481 */
bogdanm 82:6473597d706e 2482 //@{
bogdanm 82:6473597d706e 2483 #define BP_SDHC_SYSCTL_INITA (27U) //!< Bit position for SDHC_SYSCTL_INITA.
bogdanm 82:6473597d706e 2484 #define BM_SDHC_SYSCTL_INITA (0x08000000U) //!< Bit mask for SDHC_SYSCTL_INITA.
bogdanm 82:6473597d706e 2485 #define BS_SDHC_SYSCTL_INITA (1U) //!< Bit field size in bits for SDHC_SYSCTL_INITA.
bogdanm 82:6473597d706e 2486
bogdanm 82:6473597d706e 2487 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2488 //! @brief Read current value of the SDHC_SYSCTL_INITA field.
bogdanm 82:6473597d706e 2489 #define BR_SDHC_SYSCTL_INITA (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_INITA))
bogdanm 82:6473597d706e 2490 #endif
bogdanm 82:6473597d706e 2491
bogdanm 82:6473597d706e 2492 //! @brief Format value for bitfield SDHC_SYSCTL_INITA.
bogdanm 82:6473597d706e 2493 #define BF_SDHC_SYSCTL_INITA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_SYSCTL_INITA), uint32_t) & BM_SDHC_SYSCTL_INITA)
bogdanm 82:6473597d706e 2494
bogdanm 82:6473597d706e 2495 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2496 //! @brief Set the INITA field to a new value.
bogdanm 82:6473597d706e 2497 #define BW_SDHC_SYSCTL_INITA(v) (BITBAND_ACCESS32(HW_SDHC_SYSCTL_ADDR, BP_SDHC_SYSCTL_INITA) = (v))
bogdanm 82:6473597d706e 2498 #endif
bogdanm 82:6473597d706e 2499 //@}
bogdanm 82:6473597d706e 2500
bogdanm 82:6473597d706e 2501 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2502 // HW_SDHC_IRQSTAT - Interrupt Status register
bogdanm 82:6473597d706e 2503 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 2504
bogdanm 82:6473597d706e 2505 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2506 /*!
bogdanm 82:6473597d706e 2507 * @brief HW_SDHC_IRQSTAT - Interrupt Status register (RW)
bogdanm 82:6473597d706e 2508 *
bogdanm 82:6473597d706e 2509 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 2510 *
bogdanm 82:6473597d706e 2511 * An interrupt is generated when the Normal Interrupt Signal Enable is enabled
bogdanm 82:6473597d706e 2512 * and at least one of the status bits is set to 1. For all bits, writing 1 to a
bogdanm 82:6473597d706e 2513 * bit clears it; writing to 0 keeps the bit unchanged. More than one status can
bogdanm 82:6473597d706e 2514 * be cleared with a single register write. For Card Interrupt, before writing 1
bogdanm 82:6473597d706e 2515 * to clear, it is required that the card stops asserting the interrupt, meaning
bogdanm 82:6473597d706e 2516 * that when the Card Driver services the interrupt condition, otherwise the CINT
bogdanm 82:6473597d706e 2517 * bit will be asserted again. The table below shows the relationship between
bogdanm 82:6473597d706e 2518 * the CTOE and the CC bits. SDHC status for CTOE/CC bit combinations Command
bogdanm 82:6473597d706e 2519 * complete Command timeout error Meaning of the status 0 0 X X 1 Response not
bogdanm 82:6473597d706e 2520 * received within 64 SDCLK cycles 1 0 Response received The table below shows the
bogdanm 82:6473597d706e 2521 * relationship between the Transfer Complete and the Data Timeout Error. SDHC status
bogdanm 82:6473597d706e 2522 * for data timeout error/transfer complete bit combinations Transfer complete
bogdanm 82:6473597d706e 2523 * Data timeout error Meaning of the status 0 0 X 0 1 Timeout occurred during
bogdanm 82:6473597d706e 2524 * transfer 1 X Data transfer complete The table below shows the relationship between
bogdanm 82:6473597d706e 2525 * the command CRC Error (CCE) and Command Timeout Error (CTOE). SDHC status for
bogdanm 82:6473597d706e 2526 * CCE/CTOE Bit Combinations Command complete Command timeout error Meaning of
bogdanm 82:6473597d706e 2527 * the status 0 0 No error 0 1 Response timeout error 1 0 Response CRC error 1 1
bogdanm 82:6473597d706e 2528 * CMD line conflict
bogdanm 82:6473597d706e 2529 */
bogdanm 82:6473597d706e 2530 typedef union _hw_sdhc_irqstat
bogdanm 82:6473597d706e 2531 {
bogdanm 82:6473597d706e 2532 uint32_t U;
bogdanm 82:6473597d706e 2533 struct _hw_sdhc_irqstat_bitfields
bogdanm 82:6473597d706e 2534 {
bogdanm 82:6473597d706e 2535 uint32_t CC : 1; //!< [0] Command Complete
bogdanm 82:6473597d706e 2536 uint32_t TC : 1; //!< [1] Transfer Complete
bogdanm 82:6473597d706e 2537 uint32_t BGE : 1; //!< [2] Block Gap Event
bogdanm 82:6473597d706e 2538 uint32_t DINT : 1; //!< [3] DMA Interrupt
bogdanm 82:6473597d706e 2539 uint32_t BWR : 1; //!< [4] Buffer Write Ready
bogdanm 82:6473597d706e 2540 uint32_t BRR : 1; //!< [5] Buffer Read Ready
bogdanm 82:6473597d706e 2541 uint32_t CINS : 1; //!< [6] Card Insertion
bogdanm 82:6473597d706e 2542 uint32_t CRM : 1; //!< [7] Card Removal
bogdanm 82:6473597d706e 2543 uint32_t CINT : 1; //!< [8] Card Interrupt
bogdanm 82:6473597d706e 2544 uint32_t RESERVED0 : 7; //!< [15:9]
bogdanm 82:6473597d706e 2545 uint32_t CTOE : 1; //!< [16] Command Timeout Error
bogdanm 82:6473597d706e 2546 uint32_t CCE : 1; //!< [17] Command CRC Error
bogdanm 82:6473597d706e 2547 uint32_t CEBE : 1; //!< [18] Command End Bit Error
bogdanm 82:6473597d706e 2548 uint32_t CIE : 1; //!< [19] Command Index Error
bogdanm 82:6473597d706e 2549 uint32_t DTOE : 1; //!< [20] Data Timeout Error
bogdanm 82:6473597d706e 2550 uint32_t DCE : 1; //!< [21] Data CRC Error
bogdanm 82:6473597d706e 2551 uint32_t DEBE : 1; //!< [22] Data End Bit Error
bogdanm 82:6473597d706e 2552 uint32_t RESERVED1 : 1; //!< [23]
bogdanm 82:6473597d706e 2553 uint32_t AC12E : 1; //!< [24] Auto CMD12 Error
bogdanm 82:6473597d706e 2554 uint32_t RESERVED2 : 3; //!< [27:25]
bogdanm 82:6473597d706e 2555 uint32_t DMAE : 1; //!< [28] DMA Error
bogdanm 82:6473597d706e 2556 uint32_t RESERVED3 : 3; //!< [31:29]
bogdanm 82:6473597d706e 2557 } B;
bogdanm 82:6473597d706e 2558 } hw_sdhc_irqstat_t;
bogdanm 82:6473597d706e 2559 #endif
bogdanm 82:6473597d706e 2560
bogdanm 82:6473597d706e 2561 /*!
bogdanm 82:6473597d706e 2562 * @name Constants and macros for entire SDHC_IRQSTAT register
bogdanm 82:6473597d706e 2563 */
bogdanm 82:6473597d706e 2564 //@{
bogdanm 82:6473597d706e 2565 #define HW_SDHC_IRQSTAT_ADDR (REGS_SDHC_BASE + 0x30U)
bogdanm 82:6473597d706e 2566
bogdanm 82:6473597d706e 2567 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2568 #define HW_SDHC_IRQSTAT (*(__IO hw_sdhc_irqstat_t *) HW_SDHC_IRQSTAT_ADDR)
bogdanm 82:6473597d706e 2569 #define HW_SDHC_IRQSTAT_RD() (HW_SDHC_IRQSTAT.U)
bogdanm 82:6473597d706e 2570 #define HW_SDHC_IRQSTAT_WR(v) (HW_SDHC_IRQSTAT.U = (v))
bogdanm 82:6473597d706e 2571 #define HW_SDHC_IRQSTAT_SET(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() | (v)))
bogdanm 82:6473597d706e 2572 #define HW_SDHC_IRQSTAT_CLR(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() & ~(v)))
bogdanm 82:6473597d706e 2573 #define HW_SDHC_IRQSTAT_TOG(v) (HW_SDHC_IRQSTAT_WR(HW_SDHC_IRQSTAT_RD() ^ (v)))
bogdanm 82:6473597d706e 2574 #endif
bogdanm 82:6473597d706e 2575 //@}
bogdanm 82:6473597d706e 2576
bogdanm 82:6473597d706e 2577 /*
bogdanm 82:6473597d706e 2578 * Constants & macros for individual SDHC_IRQSTAT bitfields
bogdanm 82:6473597d706e 2579 */
bogdanm 82:6473597d706e 2580
bogdanm 82:6473597d706e 2581 /*!
bogdanm 82:6473597d706e 2582 * @name Register SDHC_IRQSTAT, field CC[0] (W1C)
bogdanm 82:6473597d706e 2583 *
bogdanm 82:6473597d706e 2584 * This bit is set when you receive the end bit of the command response, except
bogdanm 82:6473597d706e 2585 * Auto CMD12. See PRSSTAT[CIHB].
bogdanm 82:6473597d706e 2586 *
bogdanm 82:6473597d706e 2587 * Values:
bogdanm 82:6473597d706e 2588 * - 0 - Command not complete.
bogdanm 82:6473597d706e 2589 * - 1 - Command complete.
bogdanm 82:6473597d706e 2590 */
bogdanm 82:6473597d706e 2591 //@{
bogdanm 82:6473597d706e 2592 #define BP_SDHC_IRQSTAT_CC (0U) //!< Bit position for SDHC_IRQSTAT_CC.
bogdanm 82:6473597d706e 2593 #define BM_SDHC_IRQSTAT_CC (0x00000001U) //!< Bit mask for SDHC_IRQSTAT_CC.
bogdanm 82:6473597d706e 2594 #define BS_SDHC_IRQSTAT_CC (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CC.
bogdanm 82:6473597d706e 2595
bogdanm 82:6473597d706e 2596 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2597 //! @brief Read current value of the SDHC_IRQSTAT_CC field.
bogdanm 82:6473597d706e 2598 #define BR_SDHC_IRQSTAT_CC (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CC))
bogdanm 82:6473597d706e 2599 #endif
bogdanm 82:6473597d706e 2600
bogdanm 82:6473597d706e 2601 //! @brief Format value for bitfield SDHC_IRQSTAT_CC.
bogdanm 82:6473597d706e 2602 #define BF_SDHC_IRQSTAT_CC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CC), uint32_t) & BM_SDHC_IRQSTAT_CC)
bogdanm 82:6473597d706e 2603
bogdanm 82:6473597d706e 2604 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2605 //! @brief Set the CC field to a new value.
bogdanm 82:6473597d706e 2606 #define BW_SDHC_IRQSTAT_CC(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CC) = (v))
bogdanm 82:6473597d706e 2607 #endif
bogdanm 82:6473597d706e 2608 //@}
bogdanm 82:6473597d706e 2609
bogdanm 82:6473597d706e 2610 /*!
bogdanm 82:6473597d706e 2611 * @name Register SDHC_IRQSTAT, field TC[1] (W1C)
bogdanm 82:6473597d706e 2612 *
bogdanm 82:6473597d706e 2613 * This bit is set when a read or write transfer is completed. In the case of a
bogdanm 82:6473597d706e 2614 * read transaction: This bit is set at the falling edge of the read transfer
bogdanm 82:6473597d706e 2615 * active status. There are two cases in which this interrupt is generated. The
bogdanm 82:6473597d706e 2616 * first is when a data transfer is completed as specified by the data length, after
bogdanm 82:6473597d706e 2617 * the last data has been read to the host system. The second is when data has
bogdanm 82:6473597d706e 2618 * stopped at the block gap and completed the data transfer by setting
bogdanm 82:6473597d706e 2619 * PROCTL[SABGREQ], after valid data has been read to the host system. In the case of a write
bogdanm 82:6473597d706e 2620 * transaction: This bit is set at the falling edge of the DAT line active
bogdanm 82:6473597d706e 2621 * status. There are two cases in which this interrupt is generated. The first is when
bogdanm 82:6473597d706e 2622 * the last data is written to the SD card as specified by the data length and
bogdanm 82:6473597d706e 2623 * the busy signal is released. The second is when data transfers are stopped at
bogdanm 82:6473597d706e 2624 * the block gap, by setting PROCTL[SABGREQ], and the data transfers are
bogdanm 82:6473597d706e 2625 * completed,after valid data is written to the SD card and the busy signal released.
bogdanm 82:6473597d706e 2626 *
bogdanm 82:6473597d706e 2627 * Values:
bogdanm 82:6473597d706e 2628 * - 0 - Transfer not complete.
bogdanm 82:6473597d706e 2629 * - 1 - Transfer complete.
bogdanm 82:6473597d706e 2630 */
bogdanm 82:6473597d706e 2631 //@{
bogdanm 82:6473597d706e 2632 #define BP_SDHC_IRQSTAT_TC (1U) //!< Bit position for SDHC_IRQSTAT_TC.
bogdanm 82:6473597d706e 2633 #define BM_SDHC_IRQSTAT_TC (0x00000002U) //!< Bit mask for SDHC_IRQSTAT_TC.
bogdanm 82:6473597d706e 2634 #define BS_SDHC_IRQSTAT_TC (1U) //!< Bit field size in bits for SDHC_IRQSTAT_TC.
bogdanm 82:6473597d706e 2635
bogdanm 82:6473597d706e 2636 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2637 //! @brief Read current value of the SDHC_IRQSTAT_TC field.
bogdanm 82:6473597d706e 2638 #define BR_SDHC_IRQSTAT_TC (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_TC))
bogdanm 82:6473597d706e 2639 #endif
bogdanm 82:6473597d706e 2640
bogdanm 82:6473597d706e 2641 //! @brief Format value for bitfield SDHC_IRQSTAT_TC.
bogdanm 82:6473597d706e 2642 #define BF_SDHC_IRQSTAT_TC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_TC), uint32_t) & BM_SDHC_IRQSTAT_TC)
bogdanm 82:6473597d706e 2643
bogdanm 82:6473597d706e 2644 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2645 //! @brief Set the TC field to a new value.
bogdanm 82:6473597d706e 2646 #define BW_SDHC_IRQSTAT_TC(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_TC) = (v))
bogdanm 82:6473597d706e 2647 #endif
bogdanm 82:6473597d706e 2648 //@}
bogdanm 82:6473597d706e 2649
bogdanm 82:6473597d706e 2650 /*!
bogdanm 82:6473597d706e 2651 * @name Register SDHC_IRQSTAT, field BGE[2] (W1C)
bogdanm 82:6473597d706e 2652 *
bogdanm 82:6473597d706e 2653 * If PROCTL[SABGREQ] is set, this bit is set when a read or write transaction
bogdanm 82:6473597d706e 2654 * is stopped at a block gap. If PROCTL[SABGREQ] is not set to 1, this bit is not
bogdanm 82:6473597d706e 2655 * set to 1. In the case of a read transaction: This bit is set at the falling
bogdanm 82:6473597d706e 2656 * edge of the DAT line active status, when the transaction is stopped at SD Bus
bogdanm 82:6473597d706e 2657 * timing. The read wait must be supported in order to use this function. In the
bogdanm 82:6473597d706e 2658 * case of write transaction: This bit is set at the falling edge of write transfer
bogdanm 82:6473597d706e 2659 * active status, after getting CRC status at SD bus timing.
bogdanm 82:6473597d706e 2660 *
bogdanm 82:6473597d706e 2661 * Values:
bogdanm 82:6473597d706e 2662 * - 0 - No block gap event.
bogdanm 82:6473597d706e 2663 * - 1 - Transaction stopped at block gap.
bogdanm 82:6473597d706e 2664 */
bogdanm 82:6473597d706e 2665 //@{
bogdanm 82:6473597d706e 2666 #define BP_SDHC_IRQSTAT_BGE (2U) //!< Bit position for SDHC_IRQSTAT_BGE.
bogdanm 82:6473597d706e 2667 #define BM_SDHC_IRQSTAT_BGE (0x00000004U) //!< Bit mask for SDHC_IRQSTAT_BGE.
bogdanm 82:6473597d706e 2668 #define BS_SDHC_IRQSTAT_BGE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BGE.
bogdanm 82:6473597d706e 2669
bogdanm 82:6473597d706e 2670 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2671 //! @brief Read current value of the SDHC_IRQSTAT_BGE field.
bogdanm 82:6473597d706e 2672 #define BR_SDHC_IRQSTAT_BGE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BGE))
bogdanm 82:6473597d706e 2673 #endif
bogdanm 82:6473597d706e 2674
bogdanm 82:6473597d706e 2675 //! @brief Format value for bitfield SDHC_IRQSTAT_BGE.
bogdanm 82:6473597d706e 2676 #define BF_SDHC_IRQSTAT_BGE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BGE), uint32_t) & BM_SDHC_IRQSTAT_BGE)
bogdanm 82:6473597d706e 2677
bogdanm 82:6473597d706e 2678 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2679 //! @brief Set the BGE field to a new value.
bogdanm 82:6473597d706e 2680 #define BW_SDHC_IRQSTAT_BGE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BGE) = (v))
bogdanm 82:6473597d706e 2681 #endif
bogdanm 82:6473597d706e 2682 //@}
bogdanm 82:6473597d706e 2683
bogdanm 82:6473597d706e 2684 /*!
bogdanm 82:6473597d706e 2685 * @name Register SDHC_IRQSTAT, field DINT[3] (W1C)
bogdanm 82:6473597d706e 2686 *
bogdanm 82:6473597d706e 2687 * Occurs only when the internal DMA finishes the data transfer successfully.
bogdanm 82:6473597d706e 2688 * Whenever errors occur during data transfer, this bit will not be set. Instead,
bogdanm 82:6473597d706e 2689 * the DMAE bit will be set. Either Simple DMA or ADMA finishes data transferring,
bogdanm 82:6473597d706e 2690 * this bit will be set.
bogdanm 82:6473597d706e 2691 *
bogdanm 82:6473597d706e 2692 * Values:
bogdanm 82:6473597d706e 2693 * - 0 - No DMA Interrupt.
bogdanm 82:6473597d706e 2694 * - 1 - DMA Interrupt is generated.
bogdanm 82:6473597d706e 2695 */
bogdanm 82:6473597d706e 2696 //@{
bogdanm 82:6473597d706e 2697 #define BP_SDHC_IRQSTAT_DINT (3U) //!< Bit position for SDHC_IRQSTAT_DINT.
bogdanm 82:6473597d706e 2698 #define BM_SDHC_IRQSTAT_DINT (0x00000008U) //!< Bit mask for SDHC_IRQSTAT_DINT.
bogdanm 82:6473597d706e 2699 #define BS_SDHC_IRQSTAT_DINT (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DINT.
bogdanm 82:6473597d706e 2700
bogdanm 82:6473597d706e 2701 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2702 //! @brief Read current value of the SDHC_IRQSTAT_DINT field.
bogdanm 82:6473597d706e 2703 #define BR_SDHC_IRQSTAT_DINT (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DINT))
bogdanm 82:6473597d706e 2704 #endif
bogdanm 82:6473597d706e 2705
bogdanm 82:6473597d706e 2706 //! @brief Format value for bitfield SDHC_IRQSTAT_DINT.
bogdanm 82:6473597d706e 2707 #define BF_SDHC_IRQSTAT_DINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DINT), uint32_t) & BM_SDHC_IRQSTAT_DINT)
bogdanm 82:6473597d706e 2708
bogdanm 82:6473597d706e 2709 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2710 //! @brief Set the DINT field to a new value.
bogdanm 82:6473597d706e 2711 #define BW_SDHC_IRQSTAT_DINT(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DINT) = (v))
bogdanm 82:6473597d706e 2712 #endif
bogdanm 82:6473597d706e 2713 //@}
bogdanm 82:6473597d706e 2714
bogdanm 82:6473597d706e 2715 /*!
bogdanm 82:6473597d706e 2716 * @name Register SDHC_IRQSTAT, field BWR[4] (W1C)
bogdanm 82:6473597d706e 2717 *
bogdanm 82:6473597d706e 2718 * This status bit is set if the Buffer Write Enable bit, in the Present State
bogdanm 82:6473597d706e 2719 * register, changes from 0 to 1. See the Buffer Write Enable bit in the Present
bogdanm 82:6473597d706e 2720 * State register for additional information.
bogdanm 82:6473597d706e 2721 *
bogdanm 82:6473597d706e 2722 * Values:
bogdanm 82:6473597d706e 2723 * - 0 - Not ready to write buffer.
bogdanm 82:6473597d706e 2724 * - 1 - Ready to write buffer.
bogdanm 82:6473597d706e 2725 */
bogdanm 82:6473597d706e 2726 //@{
bogdanm 82:6473597d706e 2727 #define BP_SDHC_IRQSTAT_BWR (4U) //!< Bit position for SDHC_IRQSTAT_BWR.
bogdanm 82:6473597d706e 2728 #define BM_SDHC_IRQSTAT_BWR (0x00000010U) //!< Bit mask for SDHC_IRQSTAT_BWR.
bogdanm 82:6473597d706e 2729 #define BS_SDHC_IRQSTAT_BWR (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BWR.
bogdanm 82:6473597d706e 2730
bogdanm 82:6473597d706e 2731 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2732 //! @brief Read current value of the SDHC_IRQSTAT_BWR field.
bogdanm 82:6473597d706e 2733 #define BR_SDHC_IRQSTAT_BWR (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BWR))
bogdanm 82:6473597d706e 2734 #endif
bogdanm 82:6473597d706e 2735
bogdanm 82:6473597d706e 2736 //! @brief Format value for bitfield SDHC_IRQSTAT_BWR.
bogdanm 82:6473597d706e 2737 #define BF_SDHC_IRQSTAT_BWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BWR), uint32_t) & BM_SDHC_IRQSTAT_BWR)
bogdanm 82:6473597d706e 2738
bogdanm 82:6473597d706e 2739 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2740 //! @brief Set the BWR field to a new value.
bogdanm 82:6473597d706e 2741 #define BW_SDHC_IRQSTAT_BWR(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BWR) = (v))
bogdanm 82:6473597d706e 2742 #endif
bogdanm 82:6473597d706e 2743 //@}
bogdanm 82:6473597d706e 2744
bogdanm 82:6473597d706e 2745 /*!
bogdanm 82:6473597d706e 2746 * @name Register SDHC_IRQSTAT, field BRR[5] (W1C)
bogdanm 82:6473597d706e 2747 *
bogdanm 82:6473597d706e 2748 * This status bit is set if the Buffer Read Enable bit, in the Present State
bogdanm 82:6473597d706e 2749 * register, changes from 0 to 1. See the Buffer Read Enable bit in the Present
bogdanm 82:6473597d706e 2750 * State register for additional information.
bogdanm 82:6473597d706e 2751 *
bogdanm 82:6473597d706e 2752 * Values:
bogdanm 82:6473597d706e 2753 * - 0 - Not ready to read buffer.
bogdanm 82:6473597d706e 2754 * - 1 - Ready to read buffer.
bogdanm 82:6473597d706e 2755 */
bogdanm 82:6473597d706e 2756 //@{
bogdanm 82:6473597d706e 2757 #define BP_SDHC_IRQSTAT_BRR (5U) //!< Bit position for SDHC_IRQSTAT_BRR.
bogdanm 82:6473597d706e 2758 #define BM_SDHC_IRQSTAT_BRR (0x00000020U) //!< Bit mask for SDHC_IRQSTAT_BRR.
bogdanm 82:6473597d706e 2759 #define BS_SDHC_IRQSTAT_BRR (1U) //!< Bit field size in bits for SDHC_IRQSTAT_BRR.
bogdanm 82:6473597d706e 2760
bogdanm 82:6473597d706e 2761 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2762 //! @brief Read current value of the SDHC_IRQSTAT_BRR field.
bogdanm 82:6473597d706e 2763 #define BR_SDHC_IRQSTAT_BRR (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BRR))
bogdanm 82:6473597d706e 2764 #endif
bogdanm 82:6473597d706e 2765
bogdanm 82:6473597d706e 2766 //! @brief Format value for bitfield SDHC_IRQSTAT_BRR.
bogdanm 82:6473597d706e 2767 #define BF_SDHC_IRQSTAT_BRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_BRR), uint32_t) & BM_SDHC_IRQSTAT_BRR)
bogdanm 82:6473597d706e 2768
bogdanm 82:6473597d706e 2769 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2770 //! @brief Set the BRR field to a new value.
bogdanm 82:6473597d706e 2771 #define BW_SDHC_IRQSTAT_BRR(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_BRR) = (v))
bogdanm 82:6473597d706e 2772 #endif
bogdanm 82:6473597d706e 2773 //@}
bogdanm 82:6473597d706e 2774
bogdanm 82:6473597d706e 2775 /*!
bogdanm 82:6473597d706e 2776 * @name Register SDHC_IRQSTAT, field CINS[6] (W1C)
bogdanm 82:6473597d706e 2777 *
bogdanm 82:6473597d706e 2778 * This status bit is set if the Card Inserted bit in the Present State register
bogdanm 82:6473597d706e 2779 * changes from 0 to 1. When the host driver writes this bit to 1 to clear this
bogdanm 82:6473597d706e 2780 * status, the status of the Card Inserted in the Present State register must be
bogdanm 82:6473597d706e 2781 * confirmed. Because the card state may possibly be changed when the host driver
bogdanm 82:6473597d706e 2782 * clears this bit and the interrupt event may not be generated. When this bit
bogdanm 82:6473597d706e 2783 * is cleared, it will be set again if a card is inserted. To leave it cleared,
bogdanm 82:6473597d706e 2784 * clear the Card Inserted Status Enable bit in Interrupt Status Enable register.
bogdanm 82:6473597d706e 2785 *
bogdanm 82:6473597d706e 2786 * Values:
bogdanm 82:6473597d706e 2787 * - 0 - Card state unstable or removed.
bogdanm 82:6473597d706e 2788 * - 1 - Card inserted.
bogdanm 82:6473597d706e 2789 */
bogdanm 82:6473597d706e 2790 //@{
bogdanm 82:6473597d706e 2791 #define BP_SDHC_IRQSTAT_CINS (6U) //!< Bit position for SDHC_IRQSTAT_CINS.
bogdanm 82:6473597d706e 2792 #define BM_SDHC_IRQSTAT_CINS (0x00000040U) //!< Bit mask for SDHC_IRQSTAT_CINS.
bogdanm 82:6473597d706e 2793 #define BS_SDHC_IRQSTAT_CINS (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CINS.
bogdanm 82:6473597d706e 2794
bogdanm 82:6473597d706e 2795 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2796 //! @brief Read current value of the SDHC_IRQSTAT_CINS field.
bogdanm 82:6473597d706e 2797 #define BR_SDHC_IRQSTAT_CINS (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINS))
bogdanm 82:6473597d706e 2798 #endif
bogdanm 82:6473597d706e 2799
bogdanm 82:6473597d706e 2800 //! @brief Format value for bitfield SDHC_IRQSTAT_CINS.
bogdanm 82:6473597d706e 2801 #define BF_SDHC_IRQSTAT_CINS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CINS), uint32_t) & BM_SDHC_IRQSTAT_CINS)
bogdanm 82:6473597d706e 2802
bogdanm 82:6473597d706e 2803 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2804 //! @brief Set the CINS field to a new value.
bogdanm 82:6473597d706e 2805 #define BW_SDHC_IRQSTAT_CINS(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINS) = (v))
bogdanm 82:6473597d706e 2806 #endif
bogdanm 82:6473597d706e 2807 //@}
bogdanm 82:6473597d706e 2808
bogdanm 82:6473597d706e 2809 /*!
bogdanm 82:6473597d706e 2810 * @name Register SDHC_IRQSTAT, field CRM[7] (W1C)
bogdanm 82:6473597d706e 2811 *
bogdanm 82:6473597d706e 2812 * This status bit is set if the Card Inserted bit in the Present State register
bogdanm 82:6473597d706e 2813 * changes from 1 to 0. When the host driver writes this bit to 1 to clear this
bogdanm 82:6473597d706e 2814 * status, the status of the Card Inserted in the Present State register must be
bogdanm 82:6473597d706e 2815 * confirmed. Because the card state may possibly be changed when the host driver
bogdanm 82:6473597d706e 2816 * clears this bit and the interrupt event may not be generated. When this bit
bogdanm 82:6473597d706e 2817 * is cleared, it will be set again if no card is inserted. To leave it cleared,
bogdanm 82:6473597d706e 2818 * clear the Card Removal Status Enable bit in Interrupt Status Enable register.
bogdanm 82:6473597d706e 2819 *
bogdanm 82:6473597d706e 2820 * Values:
bogdanm 82:6473597d706e 2821 * - 0 - Card state unstable or inserted.
bogdanm 82:6473597d706e 2822 * - 1 - Card removed.
bogdanm 82:6473597d706e 2823 */
bogdanm 82:6473597d706e 2824 //@{
bogdanm 82:6473597d706e 2825 #define BP_SDHC_IRQSTAT_CRM (7U) //!< Bit position for SDHC_IRQSTAT_CRM.
bogdanm 82:6473597d706e 2826 #define BM_SDHC_IRQSTAT_CRM (0x00000080U) //!< Bit mask for SDHC_IRQSTAT_CRM.
bogdanm 82:6473597d706e 2827 #define BS_SDHC_IRQSTAT_CRM (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CRM.
bogdanm 82:6473597d706e 2828
bogdanm 82:6473597d706e 2829 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2830 //! @brief Read current value of the SDHC_IRQSTAT_CRM field.
bogdanm 82:6473597d706e 2831 #define BR_SDHC_IRQSTAT_CRM (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CRM))
bogdanm 82:6473597d706e 2832 #endif
bogdanm 82:6473597d706e 2833
bogdanm 82:6473597d706e 2834 //! @brief Format value for bitfield SDHC_IRQSTAT_CRM.
bogdanm 82:6473597d706e 2835 #define BF_SDHC_IRQSTAT_CRM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CRM), uint32_t) & BM_SDHC_IRQSTAT_CRM)
bogdanm 82:6473597d706e 2836
bogdanm 82:6473597d706e 2837 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2838 //! @brief Set the CRM field to a new value.
bogdanm 82:6473597d706e 2839 #define BW_SDHC_IRQSTAT_CRM(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CRM) = (v))
bogdanm 82:6473597d706e 2840 #endif
bogdanm 82:6473597d706e 2841 //@}
bogdanm 82:6473597d706e 2842
bogdanm 82:6473597d706e 2843 /*!
bogdanm 82:6473597d706e 2844 * @name Register SDHC_IRQSTAT, field CINT[8] (W1C)
bogdanm 82:6473597d706e 2845 *
bogdanm 82:6473597d706e 2846 * This status bit is set when an interrupt signal is detected from the external
bogdanm 82:6473597d706e 2847 * card. In 1-bit mode, the SDHC will detect the Card Interrupt without the SD
bogdanm 82:6473597d706e 2848 * Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled
bogdanm 82:6473597d706e 2849 * during the interrupt cycle, so the interrupt from card can only be sampled
bogdanm 82:6473597d706e 2850 * during interrupt cycle, introducing some delay between the interrupt signal from
bogdanm 82:6473597d706e 2851 * the SDIO card and the interrupt to the host system. Writing this bit to 1 can
bogdanm 82:6473597d706e 2852 * clear this bit, but as the interrupt factor from the SDIO card does not clear,
bogdanm 82:6473597d706e 2853 * this bit is set again. To clear this bit, it is required to reset the interrupt
bogdanm 82:6473597d706e 2854 * factor from the external card followed by a writing 1 to this bit. When this
bogdanm 82:6473597d706e 2855 * status has been set, and the host driver needs to service this interrupt, the
bogdanm 82:6473597d706e 2856 * Card Interrupt Signal Enable in the Interrupt Signal Enable register should be
bogdanm 82:6473597d706e 2857 * 0 to stop driving the interrupt signal to the host system. After completion
bogdanm 82:6473597d706e 2858 * of the card interrupt service (it must reset the interrupt factors in the SDIO
bogdanm 82:6473597d706e 2859 * card and the interrupt signal may not be asserted), write 1 to clear this bit,
bogdanm 82:6473597d706e 2860 * set the Card Interrupt Signal Enable to 1, and start sampling the interrupt
bogdanm 82:6473597d706e 2861 * signal again.
bogdanm 82:6473597d706e 2862 *
bogdanm 82:6473597d706e 2863 * Values:
bogdanm 82:6473597d706e 2864 * - 0 - No Card Interrupt.
bogdanm 82:6473597d706e 2865 * - 1 - Generate Card Interrupt.
bogdanm 82:6473597d706e 2866 */
bogdanm 82:6473597d706e 2867 //@{
bogdanm 82:6473597d706e 2868 #define BP_SDHC_IRQSTAT_CINT (8U) //!< Bit position for SDHC_IRQSTAT_CINT.
bogdanm 82:6473597d706e 2869 #define BM_SDHC_IRQSTAT_CINT (0x00000100U) //!< Bit mask for SDHC_IRQSTAT_CINT.
bogdanm 82:6473597d706e 2870 #define BS_SDHC_IRQSTAT_CINT (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CINT.
bogdanm 82:6473597d706e 2871
bogdanm 82:6473597d706e 2872 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2873 //! @brief Read current value of the SDHC_IRQSTAT_CINT field.
bogdanm 82:6473597d706e 2874 #define BR_SDHC_IRQSTAT_CINT (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINT))
bogdanm 82:6473597d706e 2875 #endif
bogdanm 82:6473597d706e 2876
bogdanm 82:6473597d706e 2877 //! @brief Format value for bitfield SDHC_IRQSTAT_CINT.
bogdanm 82:6473597d706e 2878 #define BF_SDHC_IRQSTAT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CINT), uint32_t) & BM_SDHC_IRQSTAT_CINT)
bogdanm 82:6473597d706e 2879
bogdanm 82:6473597d706e 2880 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2881 //! @brief Set the CINT field to a new value.
bogdanm 82:6473597d706e 2882 #define BW_SDHC_IRQSTAT_CINT(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CINT) = (v))
bogdanm 82:6473597d706e 2883 #endif
bogdanm 82:6473597d706e 2884 //@}
bogdanm 82:6473597d706e 2885
bogdanm 82:6473597d706e 2886 /*!
bogdanm 82:6473597d706e 2887 * @name Register SDHC_IRQSTAT, field CTOE[16] (W1C)
bogdanm 82:6473597d706e 2888 *
bogdanm 82:6473597d706e 2889 * Occurs only if no response is returned within 64 SDCLK cycles from the end
bogdanm 82:6473597d706e 2890 * bit of the command. If the SDHC detects a CMD line conflict, in which case a
bogdanm 82:6473597d706e 2891 * Command CRC Error shall also be set, this bit shall be set without waiting for 64
bogdanm 82:6473597d706e 2892 * SDCLK cycles. This is because the command will be aborted by the SDHC.
bogdanm 82:6473597d706e 2893 *
bogdanm 82:6473597d706e 2894 * Values:
bogdanm 82:6473597d706e 2895 * - 0 - No error.
bogdanm 82:6473597d706e 2896 * - 1 - Time out.
bogdanm 82:6473597d706e 2897 */
bogdanm 82:6473597d706e 2898 //@{
bogdanm 82:6473597d706e 2899 #define BP_SDHC_IRQSTAT_CTOE (16U) //!< Bit position for SDHC_IRQSTAT_CTOE.
bogdanm 82:6473597d706e 2900 #define BM_SDHC_IRQSTAT_CTOE (0x00010000U) //!< Bit mask for SDHC_IRQSTAT_CTOE.
bogdanm 82:6473597d706e 2901 #define BS_SDHC_IRQSTAT_CTOE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CTOE.
bogdanm 82:6473597d706e 2902
bogdanm 82:6473597d706e 2903 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2904 //! @brief Read current value of the SDHC_IRQSTAT_CTOE field.
bogdanm 82:6473597d706e 2905 #define BR_SDHC_IRQSTAT_CTOE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CTOE))
bogdanm 82:6473597d706e 2906 #endif
bogdanm 82:6473597d706e 2907
bogdanm 82:6473597d706e 2908 //! @brief Format value for bitfield SDHC_IRQSTAT_CTOE.
bogdanm 82:6473597d706e 2909 #define BF_SDHC_IRQSTAT_CTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CTOE), uint32_t) & BM_SDHC_IRQSTAT_CTOE)
bogdanm 82:6473597d706e 2910
bogdanm 82:6473597d706e 2911 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2912 //! @brief Set the CTOE field to a new value.
bogdanm 82:6473597d706e 2913 #define BW_SDHC_IRQSTAT_CTOE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CTOE) = (v))
bogdanm 82:6473597d706e 2914 #endif
bogdanm 82:6473597d706e 2915 //@}
bogdanm 82:6473597d706e 2916
bogdanm 82:6473597d706e 2917 /*!
bogdanm 82:6473597d706e 2918 * @name Register SDHC_IRQSTAT, field CCE[17] (W1C)
bogdanm 82:6473597d706e 2919 *
bogdanm 82:6473597d706e 2920 * Command CRC Error is generated in two cases. If a response is returned and
bogdanm 82:6473597d706e 2921 * the Command Timeout Error is set to 0, indicating no time-out, this bit is set
bogdanm 82:6473597d706e 2922 * when detecting a CRC error in the command response. The SDHC detects a CMD line
bogdanm 82:6473597d706e 2923 * conflict by monitoring the CMD line when a command is issued. If the SDHC
bogdanm 82:6473597d706e 2924 * drives the CMD line to 1, but detects 0 on the CMD line at the next SDCLK edge,
bogdanm 82:6473597d706e 2925 * then the SDHC shall abort the command (Stop driving CMD line) and set this bit
bogdanm 82:6473597d706e 2926 * to 1. The Command Timeout Error shall also be set to 1 to distinguish CMD line
bogdanm 82:6473597d706e 2927 * conflict.
bogdanm 82:6473597d706e 2928 *
bogdanm 82:6473597d706e 2929 * Values:
bogdanm 82:6473597d706e 2930 * - 0 - No error.
bogdanm 82:6473597d706e 2931 * - 1 - CRC Error generated.
bogdanm 82:6473597d706e 2932 */
bogdanm 82:6473597d706e 2933 //@{
bogdanm 82:6473597d706e 2934 #define BP_SDHC_IRQSTAT_CCE (17U) //!< Bit position for SDHC_IRQSTAT_CCE.
bogdanm 82:6473597d706e 2935 #define BM_SDHC_IRQSTAT_CCE (0x00020000U) //!< Bit mask for SDHC_IRQSTAT_CCE.
bogdanm 82:6473597d706e 2936 #define BS_SDHC_IRQSTAT_CCE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CCE.
bogdanm 82:6473597d706e 2937
bogdanm 82:6473597d706e 2938 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2939 //! @brief Read current value of the SDHC_IRQSTAT_CCE field.
bogdanm 82:6473597d706e 2940 #define BR_SDHC_IRQSTAT_CCE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CCE))
bogdanm 82:6473597d706e 2941 #endif
bogdanm 82:6473597d706e 2942
bogdanm 82:6473597d706e 2943 //! @brief Format value for bitfield SDHC_IRQSTAT_CCE.
bogdanm 82:6473597d706e 2944 #define BF_SDHC_IRQSTAT_CCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CCE), uint32_t) & BM_SDHC_IRQSTAT_CCE)
bogdanm 82:6473597d706e 2945
bogdanm 82:6473597d706e 2946 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2947 //! @brief Set the CCE field to a new value.
bogdanm 82:6473597d706e 2948 #define BW_SDHC_IRQSTAT_CCE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CCE) = (v))
bogdanm 82:6473597d706e 2949 #endif
bogdanm 82:6473597d706e 2950 //@}
bogdanm 82:6473597d706e 2951
bogdanm 82:6473597d706e 2952 /*!
bogdanm 82:6473597d706e 2953 * @name Register SDHC_IRQSTAT, field CEBE[18] (W1C)
bogdanm 82:6473597d706e 2954 *
bogdanm 82:6473597d706e 2955 * Occurs when detecting that the end bit of a command response is 0.
bogdanm 82:6473597d706e 2956 *
bogdanm 82:6473597d706e 2957 * Values:
bogdanm 82:6473597d706e 2958 * - 0 - No error.
bogdanm 82:6473597d706e 2959 * - 1 - End Bit Error generated.
bogdanm 82:6473597d706e 2960 */
bogdanm 82:6473597d706e 2961 //@{
bogdanm 82:6473597d706e 2962 #define BP_SDHC_IRQSTAT_CEBE (18U) //!< Bit position for SDHC_IRQSTAT_CEBE.
bogdanm 82:6473597d706e 2963 #define BM_SDHC_IRQSTAT_CEBE (0x00040000U) //!< Bit mask for SDHC_IRQSTAT_CEBE.
bogdanm 82:6473597d706e 2964 #define BS_SDHC_IRQSTAT_CEBE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CEBE.
bogdanm 82:6473597d706e 2965
bogdanm 82:6473597d706e 2966 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2967 //! @brief Read current value of the SDHC_IRQSTAT_CEBE field.
bogdanm 82:6473597d706e 2968 #define BR_SDHC_IRQSTAT_CEBE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CEBE))
bogdanm 82:6473597d706e 2969 #endif
bogdanm 82:6473597d706e 2970
bogdanm 82:6473597d706e 2971 //! @brief Format value for bitfield SDHC_IRQSTAT_CEBE.
bogdanm 82:6473597d706e 2972 #define BF_SDHC_IRQSTAT_CEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CEBE), uint32_t) & BM_SDHC_IRQSTAT_CEBE)
bogdanm 82:6473597d706e 2973
bogdanm 82:6473597d706e 2974 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2975 //! @brief Set the CEBE field to a new value.
bogdanm 82:6473597d706e 2976 #define BW_SDHC_IRQSTAT_CEBE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CEBE) = (v))
bogdanm 82:6473597d706e 2977 #endif
bogdanm 82:6473597d706e 2978 //@}
bogdanm 82:6473597d706e 2979
bogdanm 82:6473597d706e 2980 /*!
bogdanm 82:6473597d706e 2981 * @name Register SDHC_IRQSTAT, field CIE[19] (W1C)
bogdanm 82:6473597d706e 2982 *
bogdanm 82:6473597d706e 2983 * Occurs if a Command Index error occurs in the command response.
bogdanm 82:6473597d706e 2984 *
bogdanm 82:6473597d706e 2985 * Values:
bogdanm 82:6473597d706e 2986 * - 0 - No error.
bogdanm 82:6473597d706e 2987 * - 1 - Error.
bogdanm 82:6473597d706e 2988 */
bogdanm 82:6473597d706e 2989 //@{
bogdanm 82:6473597d706e 2990 #define BP_SDHC_IRQSTAT_CIE (19U) //!< Bit position for SDHC_IRQSTAT_CIE.
bogdanm 82:6473597d706e 2991 #define BM_SDHC_IRQSTAT_CIE (0x00080000U) //!< Bit mask for SDHC_IRQSTAT_CIE.
bogdanm 82:6473597d706e 2992 #define BS_SDHC_IRQSTAT_CIE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_CIE.
bogdanm 82:6473597d706e 2993
bogdanm 82:6473597d706e 2994 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 2995 //! @brief Read current value of the SDHC_IRQSTAT_CIE field.
bogdanm 82:6473597d706e 2996 #define BR_SDHC_IRQSTAT_CIE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CIE))
bogdanm 82:6473597d706e 2997 #endif
bogdanm 82:6473597d706e 2998
bogdanm 82:6473597d706e 2999 //! @brief Format value for bitfield SDHC_IRQSTAT_CIE.
bogdanm 82:6473597d706e 3000 #define BF_SDHC_IRQSTAT_CIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_CIE), uint32_t) & BM_SDHC_IRQSTAT_CIE)
bogdanm 82:6473597d706e 3001
bogdanm 82:6473597d706e 3002 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3003 //! @brief Set the CIE field to a new value.
bogdanm 82:6473597d706e 3004 #define BW_SDHC_IRQSTAT_CIE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_CIE) = (v))
bogdanm 82:6473597d706e 3005 #endif
bogdanm 82:6473597d706e 3006 //@}
bogdanm 82:6473597d706e 3007
bogdanm 82:6473597d706e 3008 /*!
bogdanm 82:6473597d706e 3009 * @name Register SDHC_IRQSTAT, field DTOE[20] (W1C)
bogdanm 82:6473597d706e 3010 *
bogdanm 82:6473597d706e 3011 * Occurs when detecting one of following time-out conditions. Busy time-out for
bogdanm 82:6473597d706e 3012 * R1b,R5b type Busy time-out after Write CRC status Read Data time-out
bogdanm 82:6473597d706e 3013 *
bogdanm 82:6473597d706e 3014 * Values:
bogdanm 82:6473597d706e 3015 * - 0 - No error.
bogdanm 82:6473597d706e 3016 * - 1 - Time out.
bogdanm 82:6473597d706e 3017 */
bogdanm 82:6473597d706e 3018 //@{
bogdanm 82:6473597d706e 3019 #define BP_SDHC_IRQSTAT_DTOE (20U) //!< Bit position for SDHC_IRQSTAT_DTOE.
bogdanm 82:6473597d706e 3020 #define BM_SDHC_IRQSTAT_DTOE (0x00100000U) //!< Bit mask for SDHC_IRQSTAT_DTOE.
bogdanm 82:6473597d706e 3021 #define BS_SDHC_IRQSTAT_DTOE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DTOE.
bogdanm 82:6473597d706e 3022
bogdanm 82:6473597d706e 3023 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3024 //! @brief Read current value of the SDHC_IRQSTAT_DTOE field.
bogdanm 82:6473597d706e 3025 #define BR_SDHC_IRQSTAT_DTOE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DTOE))
bogdanm 82:6473597d706e 3026 #endif
bogdanm 82:6473597d706e 3027
bogdanm 82:6473597d706e 3028 //! @brief Format value for bitfield SDHC_IRQSTAT_DTOE.
bogdanm 82:6473597d706e 3029 #define BF_SDHC_IRQSTAT_DTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DTOE), uint32_t) & BM_SDHC_IRQSTAT_DTOE)
bogdanm 82:6473597d706e 3030
bogdanm 82:6473597d706e 3031 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3032 //! @brief Set the DTOE field to a new value.
bogdanm 82:6473597d706e 3033 #define BW_SDHC_IRQSTAT_DTOE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DTOE) = (v))
bogdanm 82:6473597d706e 3034 #endif
bogdanm 82:6473597d706e 3035 //@}
bogdanm 82:6473597d706e 3036
bogdanm 82:6473597d706e 3037 /*!
bogdanm 82:6473597d706e 3038 * @name Register SDHC_IRQSTAT, field DCE[21] (W1C)
bogdanm 82:6473597d706e 3039 *
bogdanm 82:6473597d706e 3040 * Occurs when detecting a CRC error when transferring read data, which uses the
bogdanm 82:6473597d706e 3041 * DAT line, or when detecting the Write CRC status having a value other than
bogdanm 82:6473597d706e 3042 * 010.
bogdanm 82:6473597d706e 3043 *
bogdanm 82:6473597d706e 3044 * Values:
bogdanm 82:6473597d706e 3045 * - 0 - No error.
bogdanm 82:6473597d706e 3046 * - 1 - Error.
bogdanm 82:6473597d706e 3047 */
bogdanm 82:6473597d706e 3048 //@{
bogdanm 82:6473597d706e 3049 #define BP_SDHC_IRQSTAT_DCE (21U) //!< Bit position for SDHC_IRQSTAT_DCE.
bogdanm 82:6473597d706e 3050 #define BM_SDHC_IRQSTAT_DCE (0x00200000U) //!< Bit mask for SDHC_IRQSTAT_DCE.
bogdanm 82:6473597d706e 3051 #define BS_SDHC_IRQSTAT_DCE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DCE.
bogdanm 82:6473597d706e 3052
bogdanm 82:6473597d706e 3053 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3054 //! @brief Read current value of the SDHC_IRQSTAT_DCE field.
bogdanm 82:6473597d706e 3055 #define BR_SDHC_IRQSTAT_DCE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DCE))
bogdanm 82:6473597d706e 3056 #endif
bogdanm 82:6473597d706e 3057
bogdanm 82:6473597d706e 3058 //! @brief Format value for bitfield SDHC_IRQSTAT_DCE.
bogdanm 82:6473597d706e 3059 #define BF_SDHC_IRQSTAT_DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DCE), uint32_t) & BM_SDHC_IRQSTAT_DCE)
bogdanm 82:6473597d706e 3060
bogdanm 82:6473597d706e 3061 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3062 //! @brief Set the DCE field to a new value.
bogdanm 82:6473597d706e 3063 #define BW_SDHC_IRQSTAT_DCE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DCE) = (v))
bogdanm 82:6473597d706e 3064 #endif
bogdanm 82:6473597d706e 3065 //@}
bogdanm 82:6473597d706e 3066
bogdanm 82:6473597d706e 3067 /*!
bogdanm 82:6473597d706e 3068 * @name Register SDHC_IRQSTAT, field DEBE[22] (W1C)
bogdanm 82:6473597d706e 3069 *
bogdanm 82:6473597d706e 3070 * Occurs either when detecting 0 at the end bit position of read data, which
bogdanm 82:6473597d706e 3071 * uses the DAT line, or at the end bit position of the CRC.
bogdanm 82:6473597d706e 3072 *
bogdanm 82:6473597d706e 3073 * Values:
bogdanm 82:6473597d706e 3074 * - 0 - No error.
bogdanm 82:6473597d706e 3075 * - 1 - Error.
bogdanm 82:6473597d706e 3076 */
bogdanm 82:6473597d706e 3077 //@{
bogdanm 82:6473597d706e 3078 #define BP_SDHC_IRQSTAT_DEBE (22U) //!< Bit position for SDHC_IRQSTAT_DEBE.
bogdanm 82:6473597d706e 3079 #define BM_SDHC_IRQSTAT_DEBE (0x00400000U) //!< Bit mask for SDHC_IRQSTAT_DEBE.
bogdanm 82:6473597d706e 3080 #define BS_SDHC_IRQSTAT_DEBE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DEBE.
bogdanm 82:6473597d706e 3081
bogdanm 82:6473597d706e 3082 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3083 //! @brief Read current value of the SDHC_IRQSTAT_DEBE field.
bogdanm 82:6473597d706e 3084 #define BR_SDHC_IRQSTAT_DEBE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DEBE))
bogdanm 82:6473597d706e 3085 #endif
bogdanm 82:6473597d706e 3086
bogdanm 82:6473597d706e 3087 //! @brief Format value for bitfield SDHC_IRQSTAT_DEBE.
bogdanm 82:6473597d706e 3088 #define BF_SDHC_IRQSTAT_DEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DEBE), uint32_t) & BM_SDHC_IRQSTAT_DEBE)
bogdanm 82:6473597d706e 3089
bogdanm 82:6473597d706e 3090 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3091 //! @brief Set the DEBE field to a new value.
bogdanm 82:6473597d706e 3092 #define BW_SDHC_IRQSTAT_DEBE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DEBE) = (v))
bogdanm 82:6473597d706e 3093 #endif
bogdanm 82:6473597d706e 3094 //@}
bogdanm 82:6473597d706e 3095
bogdanm 82:6473597d706e 3096 /*!
bogdanm 82:6473597d706e 3097 * @name Register SDHC_IRQSTAT, field AC12E[24] (W1C)
bogdanm 82:6473597d706e 3098 *
bogdanm 82:6473597d706e 3099 * Occurs when detecting that one of the bits in the Auto CMD12 Error Status
bogdanm 82:6473597d706e 3100 * register has changed from 0 to 1. This bit is set to 1, not only when the errors
bogdanm 82:6473597d706e 3101 * in Auto CMD12 occur, but also when the Auto CMD12 is not executed due to the
bogdanm 82:6473597d706e 3102 * previous command error.
bogdanm 82:6473597d706e 3103 *
bogdanm 82:6473597d706e 3104 * Values:
bogdanm 82:6473597d706e 3105 * - 0 - No error.
bogdanm 82:6473597d706e 3106 * - 1 - Error.
bogdanm 82:6473597d706e 3107 */
bogdanm 82:6473597d706e 3108 //@{
bogdanm 82:6473597d706e 3109 #define BP_SDHC_IRQSTAT_AC12E (24U) //!< Bit position for SDHC_IRQSTAT_AC12E.
bogdanm 82:6473597d706e 3110 #define BM_SDHC_IRQSTAT_AC12E (0x01000000U) //!< Bit mask for SDHC_IRQSTAT_AC12E.
bogdanm 82:6473597d706e 3111 #define BS_SDHC_IRQSTAT_AC12E (1U) //!< Bit field size in bits for SDHC_IRQSTAT_AC12E.
bogdanm 82:6473597d706e 3112
bogdanm 82:6473597d706e 3113 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3114 //! @brief Read current value of the SDHC_IRQSTAT_AC12E field.
bogdanm 82:6473597d706e 3115 #define BR_SDHC_IRQSTAT_AC12E (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_AC12E))
bogdanm 82:6473597d706e 3116 #endif
bogdanm 82:6473597d706e 3117
bogdanm 82:6473597d706e 3118 //! @brief Format value for bitfield SDHC_IRQSTAT_AC12E.
bogdanm 82:6473597d706e 3119 #define BF_SDHC_IRQSTAT_AC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_AC12E), uint32_t) & BM_SDHC_IRQSTAT_AC12E)
bogdanm 82:6473597d706e 3120
bogdanm 82:6473597d706e 3121 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3122 //! @brief Set the AC12E field to a new value.
bogdanm 82:6473597d706e 3123 #define BW_SDHC_IRQSTAT_AC12E(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_AC12E) = (v))
bogdanm 82:6473597d706e 3124 #endif
bogdanm 82:6473597d706e 3125 //@}
bogdanm 82:6473597d706e 3126
bogdanm 82:6473597d706e 3127 /*!
bogdanm 82:6473597d706e 3128 * @name Register SDHC_IRQSTAT, field DMAE[28] (W1C)
bogdanm 82:6473597d706e 3129 *
bogdanm 82:6473597d706e 3130 * Occurs when an Internal DMA transfer has failed. This bit is set to 1, when
bogdanm 82:6473597d706e 3131 * some error occurs in the data transfer. This error can be caused by either
bogdanm 82:6473597d706e 3132 * Simple DMA or ADMA, depending on which DMA is in use. The value in DMA System
bogdanm 82:6473597d706e 3133 * Address register is the next fetch address where the error occurs. Because any
bogdanm 82:6473597d706e 3134 * error corrupts the whole data block, the host driver shall restart the transfer
bogdanm 82:6473597d706e 3135 * from the corrupted block boundary. The address of the block boundary can be
bogdanm 82:6473597d706e 3136 * calculated either from the current DSADDR value or from the remaining number of
bogdanm 82:6473597d706e 3137 * blocks and the block size.
bogdanm 82:6473597d706e 3138 *
bogdanm 82:6473597d706e 3139 * Values:
bogdanm 82:6473597d706e 3140 * - 0 - No error.
bogdanm 82:6473597d706e 3141 * - 1 - Error.
bogdanm 82:6473597d706e 3142 */
bogdanm 82:6473597d706e 3143 //@{
bogdanm 82:6473597d706e 3144 #define BP_SDHC_IRQSTAT_DMAE (28U) //!< Bit position for SDHC_IRQSTAT_DMAE.
bogdanm 82:6473597d706e 3145 #define BM_SDHC_IRQSTAT_DMAE (0x10000000U) //!< Bit mask for SDHC_IRQSTAT_DMAE.
bogdanm 82:6473597d706e 3146 #define BS_SDHC_IRQSTAT_DMAE (1U) //!< Bit field size in bits for SDHC_IRQSTAT_DMAE.
bogdanm 82:6473597d706e 3147
bogdanm 82:6473597d706e 3148 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3149 //! @brief Read current value of the SDHC_IRQSTAT_DMAE field.
bogdanm 82:6473597d706e 3150 #define BR_SDHC_IRQSTAT_DMAE (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DMAE))
bogdanm 82:6473597d706e 3151 #endif
bogdanm 82:6473597d706e 3152
bogdanm 82:6473597d706e 3153 //! @brief Format value for bitfield SDHC_IRQSTAT_DMAE.
bogdanm 82:6473597d706e 3154 #define BF_SDHC_IRQSTAT_DMAE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTAT_DMAE), uint32_t) & BM_SDHC_IRQSTAT_DMAE)
bogdanm 82:6473597d706e 3155
bogdanm 82:6473597d706e 3156 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3157 //! @brief Set the DMAE field to a new value.
bogdanm 82:6473597d706e 3158 #define BW_SDHC_IRQSTAT_DMAE(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTAT_ADDR, BP_SDHC_IRQSTAT_DMAE) = (v))
bogdanm 82:6473597d706e 3159 #endif
bogdanm 82:6473597d706e 3160 //@}
bogdanm 82:6473597d706e 3161
bogdanm 82:6473597d706e 3162 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3163 // HW_SDHC_IRQSTATEN - Interrupt Status Enable register
bogdanm 82:6473597d706e 3164 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3165
bogdanm 82:6473597d706e 3166 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3167 /*!
bogdanm 82:6473597d706e 3168 * @brief HW_SDHC_IRQSTATEN - Interrupt Status Enable register (RW)
bogdanm 82:6473597d706e 3169 *
bogdanm 82:6473597d706e 3170 * Reset value: 0x117F013FU
bogdanm 82:6473597d706e 3171 *
bogdanm 82:6473597d706e 3172 * Setting the bits in this register to 1 enables the corresponding interrupt
bogdanm 82:6473597d706e 3173 * status to be set by the specified event. If any bit is cleared, the
bogdanm 82:6473597d706e 3174 * corresponding interrupt status bit is also cleared, that is, when the bit in this register
bogdanm 82:6473597d706e 3175 * is cleared, the corresponding bit in interrupt status register is always 0.
bogdanm 82:6473597d706e 3176 * Depending on PROCTL[IABG] bit setting, SDHC may be programmed to sample the
bogdanm 82:6473597d706e 3177 * card interrupt signal during the interrupt period and hold its value in the
bogdanm 82:6473597d706e 3178 * flip-flop. There will be some delays on the card interrupt, asserted from the card,
bogdanm 82:6473597d706e 3179 * to the time the host system is informed. To detect a CMD line conflict, the
bogdanm 82:6473597d706e 3180 * host driver must set both IRQSTATEN[CTOESEN] and IRQSTATEN[CCESEN] to 1.
bogdanm 82:6473597d706e 3181 */
bogdanm 82:6473597d706e 3182 typedef union _hw_sdhc_irqstaten
bogdanm 82:6473597d706e 3183 {
bogdanm 82:6473597d706e 3184 uint32_t U;
bogdanm 82:6473597d706e 3185 struct _hw_sdhc_irqstaten_bitfields
bogdanm 82:6473597d706e 3186 {
bogdanm 82:6473597d706e 3187 uint32_t CCSEN : 1; //!< [0] Command Complete Status Enable
bogdanm 82:6473597d706e 3188 uint32_t TCSEN : 1; //!< [1] Transfer Complete Status Enable
bogdanm 82:6473597d706e 3189 uint32_t BGESEN : 1; //!< [2] Block Gap Event Status Enable
bogdanm 82:6473597d706e 3190 uint32_t DINTSEN : 1; //!< [3] DMA Interrupt Status Enable
bogdanm 82:6473597d706e 3191 uint32_t BWRSEN : 1; //!< [4] Buffer Write Ready Status Enable
bogdanm 82:6473597d706e 3192 uint32_t BRRSEN : 1; //!< [5] Buffer Read Ready Status Enable
bogdanm 82:6473597d706e 3193 uint32_t CINSEN : 1; //!< [6] Card Insertion Status Enable
bogdanm 82:6473597d706e 3194 uint32_t CRMSEN : 1; //!< [7] Card Removal Status Enable
bogdanm 82:6473597d706e 3195 uint32_t CINTSEN : 1; //!< [8] Card Interrupt Status Enable
bogdanm 82:6473597d706e 3196 uint32_t RESERVED0 : 7; //!< [15:9]
bogdanm 82:6473597d706e 3197 uint32_t CTOESEN : 1; //!< [16] Command Timeout Error Status Enable
bogdanm 82:6473597d706e 3198 uint32_t CCESEN : 1; //!< [17] Command CRC Error Status Enable
bogdanm 82:6473597d706e 3199 uint32_t CEBESEN : 1; //!< [18] Command End Bit Error Status Enable
bogdanm 82:6473597d706e 3200 uint32_t CIESEN : 1; //!< [19] Command Index Error Status Enable
bogdanm 82:6473597d706e 3201 uint32_t DTOESEN : 1; //!< [20] Data Timeout Error Status Enable
bogdanm 82:6473597d706e 3202 uint32_t DCESEN : 1; //!< [21] Data CRC Error Status Enable
bogdanm 82:6473597d706e 3203 uint32_t DEBESEN : 1; //!< [22] Data End Bit Error Status Enable
bogdanm 82:6473597d706e 3204 uint32_t RESERVED1 : 1; //!< [23]
bogdanm 82:6473597d706e 3205 uint32_t AC12ESEN : 1; //!< [24] Auto CMD12 Error Status Enable
bogdanm 82:6473597d706e 3206 uint32_t RESERVED2 : 3; //!< [27:25]
bogdanm 82:6473597d706e 3207 uint32_t DMAESEN : 1; //!< [28] DMA Error Status Enable
bogdanm 82:6473597d706e 3208 uint32_t RESERVED3 : 3; //!< [31:29]
bogdanm 82:6473597d706e 3209 } B;
bogdanm 82:6473597d706e 3210 } hw_sdhc_irqstaten_t;
bogdanm 82:6473597d706e 3211 #endif
bogdanm 82:6473597d706e 3212
bogdanm 82:6473597d706e 3213 /*!
bogdanm 82:6473597d706e 3214 * @name Constants and macros for entire SDHC_IRQSTATEN register
bogdanm 82:6473597d706e 3215 */
bogdanm 82:6473597d706e 3216 //@{
bogdanm 82:6473597d706e 3217 #define HW_SDHC_IRQSTATEN_ADDR (REGS_SDHC_BASE + 0x34U)
bogdanm 82:6473597d706e 3218
bogdanm 82:6473597d706e 3219 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3220 #define HW_SDHC_IRQSTATEN (*(__IO hw_sdhc_irqstaten_t *) HW_SDHC_IRQSTATEN_ADDR)
bogdanm 82:6473597d706e 3221 #define HW_SDHC_IRQSTATEN_RD() (HW_SDHC_IRQSTATEN.U)
bogdanm 82:6473597d706e 3222 #define HW_SDHC_IRQSTATEN_WR(v) (HW_SDHC_IRQSTATEN.U = (v))
bogdanm 82:6473597d706e 3223 #define HW_SDHC_IRQSTATEN_SET(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() | (v)))
bogdanm 82:6473597d706e 3224 #define HW_SDHC_IRQSTATEN_CLR(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() & ~(v)))
bogdanm 82:6473597d706e 3225 #define HW_SDHC_IRQSTATEN_TOG(v) (HW_SDHC_IRQSTATEN_WR(HW_SDHC_IRQSTATEN_RD() ^ (v)))
bogdanm 82:6473597d706e 3226 #endif
bogdanm 82:6473597d706e 3227 //@}
bogdanm 82:6473597d706e 3228
bogdanm 82:6473597d706e 3229 /*
bogdanm 82:6473597d706e 3230 * Constants & macros for individual SDHC_IRQSTATEN bitfields
bogdanm 82:6473597d706e 3231 */
bogdanm 82:6473597d706e 3232
bogdanm 82:6473597d706e 3233 /*!
bogdanm 82:6473597d706e 3234 * @name Register SDHC_IRQSTATEN, field CCSEN[0] (RW)
bogdanm 82:6473597d706e 3235 *
bogdanm 82:6473597d706e 3236 * Values:
bogdanm 82:6473597d706e 3237 * - 0 - Masked
bogdanm 82:6473597d706e 3238 * - 1 - Enabled
bogdanm 82:6473597d706e 3239 */
bogdanm 82:6473597d706e 3240 //@{
bogdanm 82:6473597d706e 3241 #define BP_SDHC_IRQSTATEN_CCSEN (0U) //!< Bit position for SDHC_IRQSTATEN_CCSEN.
bogdanm 82:6473597d706e 3242 #define BM_SDHC_IRQSTATEN_CCSEN (0x00000001U) //!< Bit mask for SDHC_IRQSTATEN_CCSEN.
bogdanm 82:6473597d706e 3243 #define BS_SDHC_IRQSTATEN_CCSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CCSEN.
bogdanm 82:6473597d706e 3244
bogdanm 82:6473597d706e 3245 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3246 //! @brief Read current value of the SDHC_IRQSTATEN_CCSEN field.
bogdanm 82:6473597d706e 3247 #define BR_SDHC_IRQSTATEN_CCSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCSEN))
bogdanm 82:6473597d706e 3248 #endif
bogdanm 82:6473597d706e 3249
bogdanm 82:6473597d706e 3250 //! @brief Format value for bitfield SDHC_IRQSTATEN_CCSEN.
bogdanm 82:6473597d706e 3251 #define BF_SDHC_IRQSTATEN_CCSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CCSEN), uint32_t) & BM_SDHC_IRQSTATEN_CCSEN)
bogdanm 82:6473597d706e 3252
bogdanm 82:6473597d706e 3253 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3254 //! @brief Set the CCSEN field to a new value.
bogdanm 82:6473597d706e 3255 #define BW_SDHC_IRQSTATEN_CCSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCSEN) = (v))
bogdanm 82:6473597d706e 3256 #endif
bogdanm 82:6473597d706e 3257 //@}
bogdanm 82:6473597d706e 3258
bogdanm 82:6473597d706e 3259 /*!
bogdanm 82:6473597d706e 3260 * @name Register SDHC_IRQSTATEN, field TCSEN[1] (RW)
bogdanm 82:6473597d706e 3261 *
bogdanm 82:6473597d706e 3262 * Values:
bogdanm 82:6473597d706e 3263 * - 0 - Masked
bogdanm 82:6473597d706e 3264 * - 1 - Enabled
bogdanm 82:6473597d706e 3265 */
bogdanm 82:6473597d706e 3266 //@{
bogdanm 82:6473597d706e 3267 #define BP_SDHC_IRQSTATEN_TCSEN (1U) //!< Bit position for SDHC_IRQSTATEN_TCSEN.
bogdanm 82:6473597d706e 3268 #define BM_SDHC_IRQSTATEN_TCSEN (0x00000002U) //!< Bit mask for SDHC_IRQSTATEN_TCSEN.
bogdanm 82:6473597d706e 3269 #define BS_SDHC_IRQSTATEN_TCSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_TCSEN.
bogdanm 82:6473597d706e 3270
bogdanm 82:6473597d706e 3271 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3272 //! @brief Read current value of the SDHC_IRQSTATEN_TCSEN field.
bogdanm 82:6473597d706e 3273 #define BR_SDHC_IRQSTATEN_TCSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_TCSEN))
bogdanm 82:6473597d706e 3274 #endif
bogdanm 82:6473597d706e 3275
bogdanm 82:6473597d706e 3276 //! @brief Format value for bitfield SDHC_IRQSTATEN_TCSEN.
bogdanm 82:6473597d706e 3277 #define BF_SDHC_IRQSTATEN_TCSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_TCSEN), uint32_t) & BM_SDHC_IRQSTATEN_TCSEN)
bogdanm 82:6473597d706e 3278
bogdanm 82:6473597d706e 3279 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3280 //! @brief Set the TCSEN field to a new value.
bogdanm 82:6473597d706e 3281 #define BW_SDHC_IRQSTATEN_TCSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_TCSEN) = (v))
bogdanm 82:6473597d706e 3282 #endif
bogdanm 82:6473597d706e 3283 //@}
bogdanm 82:6473597d706e 3284
bogdanm 82:6473597d706e 3285 /*!
bogdanm 82:6473597d706e 3286 * @name Register SDHC_IRQSTATEN, field BGESEN[2] (RW)
bogdanm 82:6473597d706e 3287 *
bogdanm 82:6473597d706e 3288 * Values:
bogdanm 82:6473597d706e 3289 * - 0 - Masked
bogdanm 82:6473597d706e 3290 * - 1 - Enabled
bogdanm 82:6473597d706e 3291 */
bogdanm 82:6473597d706e 3292 //@{
bogdanm 82:6473597d706e 3293 #define BP_SDHC_IRQSTATEN_BGESEN (2U) //!< Bit position for SDHC_IRQSTATEN_BGESEN.
bogdanm 82:6473597d706e 3294 #define BM_SDHC_IRQSTATEN_BGESEN (0x00000004U) //!< Bit mask for SDHC_IRQSTATEN_BGESEN.
bogdanm 82:6473597d706e 3295 #define BS_SDHC_IRQSTATEN_BGESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BGESEN.
bogdanm 82:6473597d706e 3296
bogdanm 82:6473597d706e 3297 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3298 //! @brief Read current value of the SDHC_IRQSTATEN_BGESEN field.
bogdanm 82:6473597d706e 3299 #define BR_SDHC_IRQSTATEN_BGESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BGESEN))
bogdanm 82:6473597d706e 3300 #endif
bogdanm 82:6473597d706e 3301
bogdanm 82:6473597d706e 3302 //! @brief Format value for bitfield SDHC_IRQSTATEN_BGESEN.
bogdanm 82:6473597d706e 3303 #define BF_SDHC_IRQSTATEN_BGESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BGESEN), uint32_t) & BM_SDHC_IRQSTATEN_BGESEN)
bogdanm 82:6473597d706e 3304
bogdanm 82:6473597d706e 3305 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3306 //! @brief Set the BGESEN field to a new value.
bogdanm 82:6473597d706e 3307 #define BW_SDHC_IRQSTATEN_BGESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BGESEN) = (v))
bogdanm 82:6473597d706e 3308 #endif
bogdanm 82:6473597d706e 3309 //@}
bogdanm 82:6473597d706e 3310
bogdanm 82:6473597d706e 3311 /*!
bogdanm 82:6473597d706e 3312 * @name Register SDHC_IRQSTATEN, field DINTSEN[3] (RW)
bogdanm 82:6473597d706e 3313 *
bogdanm 82:6473597d706e 3314 * Values:
bogdanm 82:6473597d706e 3315 * - 0 - Masked
bogdanm 82:6473597d706e 3316 * - 1 - Enabled
bogdanm 82:6473597d706e 3317 */
bogdanm 82:6473597d706e 3318 //@{
bogdanm 82:6473597d706e 3319 #define BP_SDHC_IRQSTATEN_DINTSEN (3U) //!< Bit position for SDHC_IRQSTATEN_DINTSEN.
bogdanm 82:6473597d706e 3320 #define BM_SDHC_IRQSTATEN_DINTSEN (0x00000008U) //!< Bit mask for SDHC_IRQSTATEN_DINTSEN.
bogdanm 82:6473597d706e 3321 #define BS_SDHC_IRQSTATEN_DINTSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DINTSEN.
bogdanm 82:6473597d706e 3322
bogdanm 82:6473597d706e 3323 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3324 //! @brief Read current value of the SDHC_IRQSTATEN_DINTSEN field.
bogdanm 82:6473597d706e 3325 #define BR_SDHC_IRQSTATEN_DINTSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DINTSEN))
bogdanm 82:6473597d706e 3326 #endif
bogdanm 82:6473597d706e 3327
bogdanm 82:6473597d706e 3328 //! @brief Format value for bitfield SDHC_IRQSTATEN_DINTSEN.
bogdanm 82:6473597d706e 3329 #define BF_SDHC_IRQSTATEN_DINTSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DINTSEN), uint32_t) & BM_SDHC_IRQSTATEN_DINTSEN)
bogdanm 82:6473597d706e 3330
bogdanm 82:6473597d706e 3331 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3332 //! @brief Set the DINTSEN field to a new value.
bogdanm 82:6473597d706e 3333 #define BW_SDHC_IRQSTATEN_DINTSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DINTSEN) = (v))
bogdanm 82:6473597d706e 3334 #endif
bogdanm 82:6473597d706e 3335 //@}
bogdanm 82:6473597d706e 3336
bogdanm 82:6473597d706e 3337 /*!
bogdanm 82:6473597d706e 3338 * @name Register SDHC_IRQSTATEN, field BWRSEN[4] (RW)
bogdanm 82:6473597d706e 3339 *
bogdanm 82:6473597d706e 3340 * Values:
bogdanm 82:6473597d706e 3341 * - 0 - Masked
bogdanm 82:6473597d706e 3342 * - 1 - Enabled
bogdanm 82:6473597d706e 3343 */
bogdanm 82:6473597d706e 3344 //@{
bogdanm 82:6473597d706e 3345 #define BP_SDHC_IRQSTATEN_BWRSEN (4U) //!< Bit position for SDHC_IRQSTATEN_BWRSEN.
bogdanm 82:6473597d706e 3346 #define BM_SDHC_IRQSTATEN_BWRSEN (0x00000010U) //!< Bit mask for SDHC_IRQSTATEN_BWRSEN.
bogdanm 82:6473597d706e 3347 #define BS_SDHC_IRQSTATEN_BWRSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BWRSEN.
bogdanm 82:6473597d706e 3348
bogdanm 82:6473597d706e 3349 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3350 //! @brief Read current value of the SDHC_IRQSTATEN_BWRSEN field.
bogdanm 82:6473597d706e 3351 #define BR_SDHC_IRQSTATEN_BWRSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BWRSEN))
bogdanm 82:6473597d706e 3352 #endif
bogdanm 82:6473597d706e 3353
bogdanm 82:6473597d706e 3354 //! @brief Format value for bitfield SDHC_IRQSTATEN_BWRSEN.
bogdanm 82:6473597d706e 3355 #define BF_SDHC_IRQSTATEN_BWRSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BWRSEN), uint32_t) & BM_SDHC_IRQSTATEN_BWRSEN)
bogdanm 82:6473597d706e 3356
bogdanm 82:6473597d706e 3357 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3358 //! @brief Set the BWRSEN field to a new value.
bogdanm 82:6473597d706e 3359 #define BW_SDHC_IRQSTATEN_BWRSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BWRSEN) = (v))
bogdanm 82:6473597d706e 3360 #endif
bogdanm 82:6473597d706e 3361 //@}
bogdanm 82:6473597d706e 3362
bogdanm 82:6473597d706e 3363 /*!
bogdanm 82:6473597d706e 3364 * @name Register SDHC_IRQSTATEN, field BRRSEN[5] (RW)
bogdanm 82:6473597d706e 3365 *
bogdanm 82:6473597d706e 3366 * Values:
bogdanm 82:6473597d706e 3367 * - 0 - Masked
bogdanm 82:6473597d706e 3368 * - 1 - Enabled
bogdanm 82:6473597d706e 3369 */
bogdanm 82:6473597d706e 3370 //@{
bogdanm 82:6473597d706e 3371 #define BP_SDHC_IRQSTATEN_BRRSEN (5U) //!< Bit position for SDHC_IRQSTATEN_BRRSEN.
bogdanm 82:6473597d706e 3372 #define BM_SDHC_IRQSTATEN_BRRSEN (0x00000020U) //!< Bit mask for SDHC_IRQSTATEN_BRRSEN.
bogdanm 82:6473597d706e 3373 #define BS_SDHC_IRQSTATEN_BRRSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_BRRSEN.
bogdanm 82:6473597d706e 3374
bogdanm 82:6473597d706e 3375 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3376 //! @brief Read current value of the SDHC_IRQSTATEN_BRRSEN field.
bogdanm 82:6473597d706e 3377 #define BR_SDHC_IRQSTATEN_BRRSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BRRSEN))
bogdanm 82:6473597d706e 3378 #endif
bogdanm 82:6473597d706e 3379
bogdanm 82:6473597d706e 3380 //! @brief Format value for bitfield SDHC_IRQSTATEN_BRRSEN.
bogdanm 82:6473597d706e 3381 #define BF_SDHC_IRQSTATEN_BRRSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_BRRSEN), uint32_t) & BM_SDHC_IRQSTATEN_BRRSEN)
bogdanm 82:6473597d706e 3382
bogdanm 82:6473597d706e 3383 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3384 //! @brief Set the BRRSEN field to a new value.
bogdanm 82:6473597d706e 3385 #define BW_SDHC_IRQSTATEN_BRRSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_BRRSEN) = (v))
bogdanm 82:6473597d706e 3386 #endif
bogdanm 82:6473597d706e 3387 //@}
bogdanm 82:6473597d706e 3388
bogdanm 82:6473597d706e 3389 /*!
bogdanm 82:6473597d706e 3390 * @name Register SDHC_IRQSTATEN, field CINSEN[6] (RW)
bogdanm 82:6473597d706e 3391 *
bogdanm 82:6473597d706e 3392 * Values:
bogdanm 82:6473597d706e 3393 * - 0 - Masked
bogdanm 82:6473597d706e 3394 * - 1 - Enabled
bogdanm 82:6473597d706e 3395 */
bogdanm 82:6473597d706e 3396 //@{
bogdanm 82:6473597d706e 3397 #define BP_SDHC_IRQSTATEN_CINSEN (6U) //!< Bit position for SDHC_IRQSTATEN_CINSEN.
bogdanm 82:6473597d706e 3398 #define BM_SDHC_IRQSTATEN_CINSEN (0x00000040U) //!< Bit mask for SDHC_IRQSTATEN_CINSEN.
bogdanm 82:6473597d706e 3399 #define BS_SDHC_IRQSTATEN_CINSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CINSEN.
bogdanm 82:6473597d706e 3400
bogdanm 82:6473597d706e 3401 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3402 //! @brief Read current value of the SDHC_IRQSTATEN_CINSEN field.
bogdanm 82:6473597d706e 3403 #define BR_SDHC_IRQSTATEN_CINSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINSEN))
bogdanm 82:6473597d706e 3404 #endif
bogdanm 82:6473597d706e 3405
bogdanm 82:6473597d706e 3406 //! @brief Format value for bitfield SDHC_IRQSTATEN_CINSEN.
bogdanm 82:6473597d706e 3407 #define BF_SDHC_IRQSTATEN_CINSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CINSEN), uint32_t) & BM_SDHC_IRQSTATEN_CINSEN)
bogdanm 82:6473597d706e 3408
bogdanm 82:6473597d706e 3409 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3410 //! @brief Set the CINSEN field to a new value.
bogdanm 82:6473597d706e 3411 #define BW_SDHC_IRQSTATEN_CINSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINSEN) = (v))
bogdanm 82:6473597d706e 3412 #endif
bogdanm 82:6473597d706e 3413 //@}
bogdanm 82:6473597d706e 3414
bogdanm 82:6473597d706e 3415 /*!
bogdanm 82:6473597d706e 3416 * @name Register SDHC_IRQSTATEN, field CRMSEN[7] (RW)
bogdanm 82:6473597d706e 3417 *
bogdanm 82:6473597d706e 3418 * Values:
bogdanm 82:6473597d706e 3419 * - 0 - Masked
bogdanm 82:6473597d706e 3420 * - 1 - Enabled
bogdanm 82:6473597d706e 3421 */
bogdanm 82:6473597d706e 3422 //@{
bogdanm 82:6473597d706e 3423 #define BP_SDHC_IRQSTATEN_CRMSEN (7U) //!< Bit position for SDHC_IRQSTATEN_CRMSEN.
bogdanm 82:6473597d706e 3424 #define BM_SDHC_IRQSTATEN_CRMSEN (0x00000080U) //!< Bit mask for SDHC_IRQSTATEN_CRMSEN.
bogdanm 82:6473597d706e 3425 #define BS_SDHC_IRQSTATEN_CRMSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CRMSEN.
bogdanm 82:6473597d706e 3426
bogdanm 82:6473597d706e 3427 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3428 //! @brief Read current value of the SDHC_IRQSTATEN_CRMSEN field.
bogdanm 82:6473597d706e 3429 #define BR_SDHC_IRQSTATEN_CRMSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CRMSEN))
bogdanm 82:6473597d706e 3430 #endif
bogdanm 82:6473597d706e 3431
bogdanm 82:6473597d706e 3432 //! @brief Format value for bitfield SDHC_IRQSTATEN_CRMSEN.
bogdanm 82:6473597d706e 3433 #define BF_SDHC_IRQSTATEN_CRMSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CRMSEN), uint32_t) & BM_SDHC_IRQSTATEN_CRMSEN)
bogdanm 82:6473597d706e 3434
bogdanm 82:6473597d706e 3435 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3436 //! @brief Set the CRMSEN field to a new value.
bogdanm 82:6473597d706e 3437 #define BW_SDHC_IRQSTATEN_CRMSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CRMSEN) = (v))
bogdanm 82:6473597d706e 3438 #endif
bogdanm 82:6473597d706e 3439 //@}
bogdanm 82:6473597d706e 3440
bogdanm 82:6473597d706e 3441 /*!
bogdanm 82:6473597d706e 3442 * @name Register SDHC_IRQSTATEN, field CINTSEN[8] (RW)
bogdanm 82:6473597d706e 3443 *
bogdanm 82:6473597d706e 3444 * If this bit is set to 0, the SDHC will clear the interrupt request to the
bogdanm 82:6473597d706e 3445 * system. The card interrupt detection is stopped when this bit is cleared and
bogdanm 82:6473597d706e 3446 * restarted when this bit is set to 1. The host driver must clear the this bit
bogdanm 82:6473597d706e 3447 * before servicing the card interrupt and must set this bit again after all interrupt
bogdanm 82:6473597d706e 3448 * requests from the card are cleared to prevent inadvertent interrupts.
bogdanm 82:6473597d706e 3449 *
bogdanm 82:6473597d706e 3450 * Values:
bogdanm 82:6473597d706e 3451 * - 0 - Masked
bogdanm 82:6473597d706e 3452 * - 1 - Enabled
bogdanm 82:6473597d706e 3453 */
bogdanm 82:6473597d706e 3454 //@{
bogdanm 82:6473597d706e 3455 #define BP_SDHC_IRQSTATEN_CINTSEN (8U) //!< Bit position for SDHC_IRQSTATEN_CINTSEN.
bogdanm 82:6473597d706e 3456 #define BM_SDHC_IRQSTATEN_CINTSEN (0x00000100U) //!< Bit mask for SDHC_IRQSTATEN_CINTSEN.
bogdanm 82:6473597d706e 3457 #define BS_SDHC_IRQSTATEN_CINTSEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CINTSEN.
bogdanm 82:6473597d706e 3458
bogdanm 82:6473597d706e 3459 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3460 //! @brief Read current value of the SDHC_IRQSTATEN_CINTSEN field.
bogdanm 82:6473597d706e 3461 #define BR_SDHC_IRQSTATEN_CINTSEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINTSEN))
bogdanm 82:6473597d706e 3462 #endif
bogdanm 82:6473597d706e 3463
bogdanm 82:6473597d706e 3464 //! @brief Format value for bitfield SDHC_IRQSTATEN_CINTSEN.
bogdanm 82:6473597d706e 3465 #define BF_SDHC_IRQSTATEN_CINTSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CINTSEN), uint32_t) & BM_SDHC_IRQSTATEN_CINTSEN)
bogdanm 82:6473597d706e 3466
bogdanm 82:6473597d706e 3467 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3468 //! @brief Set the CINTSEN field to a new value.
bogdanm 82:6473597d706e 3469 #define BW_SDHC_IRQSTATEN_CINTSEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CINTSEN) = (v))
bogdanm 82:6473597d706e 3470 #endif
bogdanm 82:6473597d706e 3471 //@}
bogdanm 82:6473597d706e 3472
bogdanm 82:6473597d706e 3473 /*!
bogdanm 82:6473597d706e 3474 * @name Register SDHC_IRQSTATEN, field CTOESEN[16] (RW)
bogdanm 82:6473597d706e 3475 *
bogdanm 82:6473597d706e 3476 * Values:
bogdanm 82:6473597d706e 3477 * - 0 - Masked
bogdanm 82:6473597d706e 3478 * - 1 - Enabled
bogdanm 82:6473597d706e 3479 */
bogdanm 82:6473597d706e 3480 //@{
bogdanm 82:6473597d706e 3481 #define BP_SDHC_IRQSTATEN_CTOESEN (16U) //!< Bit position for SDHC_IRQSTATEN_CTOESEN.
bogdanm 82:6473597d706e 3482 #define BM_SDHC_IRQSTATEN_CTOESEN (0x00010000U) //!< Bit mask for SDHC_IRQSTATEN_CTOESEN.
bogdanm 82:6473597d706e 3483 #define BS_SDHC_IRQSTATEN_CTOESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CTOESEN.
bogdanm 82:6473597d706e 3484
bogdanm 82:6473597d706e 3485 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3486 //! @brief Read current value of the SDHC_IRQSTATEN_CTOESEN field.
bogdanm 82:6473597d706e 3487 #define BR_SDHC_IRQSTATEN_CTOESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CTOESEN))
bogdanm 82:6473597d706e 3488 #endif
bogdanm 82:6473597d706e 3489
bogdanm 82:6473597d706e 3490 //! @brief Format value for bitfield SDHC_IRQSTATEN_CTOESEN.
bogdanm 82:6473597d706e 3491 #define BF_SDHC_IRQSTATEN_CTOESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CTOESEN), uint32_t) & BM_SDHC_IRQSTATEN_CTOESEN)
bogdanm 82:6473597d706e 3492
bogdanm 82:6473597d706e 3493 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3494 //! @brief Set the CTOESEN field to a new value.
bogdanm 82:6473597d706e 3495 #define BW_SDHC_IRQSTATEN_CTOESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CTOESEN) = (v))
bogdanm 82:6473597d706e 3496 #endif
bogdanm 82:6473597d706e 3497 //@}
bogdanm 82:6473597d706e 3498
bogdanm 82:6473597d706e 3499 /*!
bogdanm 82:6473597d706e 3500 * @name Register SDHC_IRQSTATEN, field CCESEN[17] (RW)
bogdanm 82:6473597d706e 3501 *
bogdanm 82:6473597d706e 3502 * Values:
bogdanm 82:6473597d706e 3503 * - 0 - Masked
bogdanm 82:6473597d706e 3504 * - 1 - Enabled
bogdanm 82:6473597d706e 3505 */
bogdanm 82:6473597d706e 3506 //@{
bogdanm 82:6473597d706e 3507 #define BP_SDHC_IRQSTATEN_CCESEN (17U) //!< Bit position for SDHC_IRQSTATEN_CCESEN.
bogdanm 82:6473597d706e 3508 #define BM_SDHC_IRQSTATEN_CCESEN (0x00020000U) //!< Bit mask for SDHC_IRQSTATEN_CCESEN.
bogdanm 82:6473597d706e 3509 #define BS_SDHC_IRQSTATEN_CCESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CCESEN.
bogdanm 82:6473597d706e 3510
bogdanm 82:6473597d706e 3511 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3512 //! @brief Read current value of the SDHC_IRQSTATEN_CCESEN field.
bogdanm 82:6473597d706e 3513 #define BR_SDHC_IRQSTATEN_CCESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCESEN))
bogdanm 82:6473597d706e 3514 #endif
bogdanm 82:6473597d706e 3515
bogdanm 82:6473597d706e 3516 //! @brief Format value for bitfield SDHC_IRQSTATEN_CCESEN.
bogdanm 82:6473597d706e 3517 #define BF_SDHC_IRQSTATEN_CCESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CCESEN), uint32_t) & BM_SDHC_IRQSTATEN_CCESEN)
bogdanm 82:6473597d706e 3518
bogdanm 82:6473597d706e 3519 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3520 //! @brief Set the CCESEN field to a new value.
bogdanm 82:6473597d706e 3521 #define BW_SDHC_IRQSTATEN_CCESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CCESEN) = (v))
bogdanm 82:6473597d706e 3522 #endif
bogdanm 82:6473597d706e 3523 //@}
bogdanm 82:6473597d706e 3524
bogdanm 82:6473597d706e 3525 /*!
bogdanm 82:6473597d706e 3526 * @name Register SDHC_IRQSTATEN, field CEBESEN[18] (RW)
bogdanm 82:6473597d706e 3527 *
bogdanm 82:6473597d706e 3528 * Values:
bogdanm 82:6473597d706e 3529 * - 0 - Masked
bogdanm 82:6473597d706e 3530 * - 1 - Enabled
bogdanm 82:6473597d706e 3531 */
bogdanm 82:6473597d706e 3532 //@{
bogdanm 82:6473597d706e 3533 #define BP_SDHC_IRQSTATEN_CEBESEN (18U) //!< Bit position for SDHC_IRQSTATEN_CEBESEN.
bogdanm 82:6473597d706e 3534 #define BM_SDHC_IRQSTATEN_CEBESEN (0x00040000U) //!< Bit mask for SDHC_IRQSTATEN_CEBESEN.
bogdanm 82:6473597d706e 3535 #define BS_SDHC_IRQSTATEN_CEBESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CEBESEN.
bogdanm 82:6473597d706e 3536
bogdanm 82:6473597d706e 3537 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3538 //! @brief Read current value of the SDHC_IRQSTATEN_CEBESEN field.
bogdanm 82:6473597d706e 3539 #define BR_SDHC_IRQSTATEN_CEBESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CEBESEN))
bogdanm 82:6473597d706e 3540 #endif
bogdanm 82:6473597d706e 3541
bogdanm 82:6473597d706e 3542 //! @brief Format value for bitfield SDHC_IRQSTATEN_CEBESEN.
bogdanm 82:6473597d706e 3543 #define BF_SDHC_IRQSTATEN_CEBESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CEBESEN), uint32_t) & BM_SDHC_IRQSTATEN_CEBESEN)
bogdanm 82:6473597d706e 3544
bogdanm 82:6473597d706e 3545 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3546 //! @brief Set the CEBESEN field to a new value.
bogdanm 82:6473597d706e 3547 #define BW_SDHC_IRQSTATEN_CEBESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CEBESEN) = (v))
bogdanm 82:6473597d706e 3548 #endif
bogdanm 82:6473597d706e 3549 //@}
bogdanm 82:6473597d706e 3550
bogdanm 82:6473597d706e 3551 /*!
bogdanm 82:6473597d706e 3552 * @name Register SDHC_IRQSTATEN, field CIESEN[19] (RW)
bogdanm 82:6473597d706e 3553 *
bogdanm 82:6473597d706e 3554 * Values:
bogdanm 82:6473597d706e 3555 * - 0 - Masked
bogdanm 82:6473597d706e 3556 * - 1 - Enabled
bogdanm 82:6473597d706e 3557 */
bogdanm 82:6473597d706e 3558 //@{
bogdanm 82:6473597d706e 3559 #define BP_SDHC_IRQSTATEN_CIESEN (19U) //!< Bit position for SDHC_IRQSTATEN_CIESEN.
bogdanm 82:6473597d706e 3560 #define BM_SDHC_IRQSTATEN_CIESEN (0x00080000U) //!< Bit mask for SDHC_IRQSTATEN_CIESEN.
bogdanm 82:6473597d706e 3561 #define BS_SDHC_IRQSTATEN_CIESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_CIESEN.
bogdanm 82:6473597d706e 3562
bogdanm 82:6473597d706e 3563 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3564 //! @brief Read current value of the SDHC_IRQSTATEN_CIESEN field.
bogdanm 82:6473597d706e 3565 #define BR_SDHC_IRQSTATEN_CIESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CIESEN))
bogdanm 82:6473597d706e 3566 #endif
bogdanm 82:6473597d706e 3567
bogdanm 82:6473597d706e 3568 //! @brief Format value for bitfield SDHC_IRQSTATEN_CIESEN.
bogdanm 82:6473597d706e 3569 #define BF_SDHC_IRQSTATEN_CIESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_CIESEN), uint32_t) & BM_SDHC_IRQSTATEN_CIESEN)
bogdanm 82:6473597d706e 3570
bogdanm 82:6473597d706e 3571 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3572 //! @brief Set the CIESEN field to a new value.
bogdanm 82:6473597d706e 3573 #define BW_SDHC_IRQSTATEN_CIESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_CIESEN) = (v))
bogdanm 82:6473597d706e 3574 #endif
bogdanm 82:6473597d706e 3575 //@}
bogdanm 82:6473597d706e 3576
bogdanm 82:6473597d706e 3577 /*!
bogdanm 82:6473597d706e 3578 * @name Register SDHC_IRQSTATEN, field DTOESEN[20] (RW)
bogdanm 82:6473597d706e 3579 *
bogdanm 82:6473597d706e 3580 * Values:
bogdanm 82:6473597d706e 3581 * - 0 - Masked
bogdanm 82:6473597d706e 3582 * - 1 - Enabled
bogdanm 82:6473597d706e 3583 */
bogdanm 82:6473597d706e 3584 //@{
bogdanm 82:6473597d706e 3585 #define BP_SDHC_IRQSTATEN_DTOESEN (20U) //!< Bit position for SDHC_IRQSTATEN_DTOESEN.
bogdanm 82:6473597d706e 3586 #define BM_SDHC_IRQSTATEN_DTOESEN (0x00100000U) //!< Bit mask for SDHC_IRQSTATEN_DTOESEN.
bogdanm 82:6473597d706e 3587 #define BS_SDHC_IRQSTATEN_DTOESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DTOESEN.
bogdanm 82:6473597d706e 3588
bogdanm 82:6473597d706e 3589 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3590 //! @brief Read current value of the SDHC_IRQSTATEN_DTOESEN field.
bogdanm 82:6473597d706e 3591 #define BR_SDHC_IRQSTATEN_DTOESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DTOESEN))
bogdanm 82:6473597d706e 3592 #endif
bogdanm 82:6473597d706e 3593
bogdanm 82:6473597d706e 3594 //! @brief Format value for bitfield SDHC_IRQSTATEN_DTOESEN.
bogdanm 82:6473597d706e 3595 #define BF_SDHC_IRQSTATEN_DTOESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DTOESEN), uint32_t) & BM_SDHC_IRQSTATEN_DTOESEN)
bogdanm 82:6473597d706e 3596
bogdanm 82:6473597d706e 3597 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3598 //! @brief Set the DTOESEN field to a new value.
bogdanm 82:6473597d706e 3599 #define BW_SDHC_IRQSTATEN_DTOESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DTOESEN) = (v))
bogdanm 82:6473597d706e 3600 #endif
bogdanm 82:6473597d706e 3601 //@}
bogdanm 82:6473597d706e 3602
bogdanm 82:6473597d706e 3603 /*!
bogdanm 82:6473597d706e 3604 * @name Register SDHC_IRQSTATEN, field DCESEN[21] (RW)
bogdanm 82:6473597d706e 3605 *
bogdanm 82:6473597d706e 3606 * Values:
bogdanm 82:6473597d706e 3607 * - 0 - Masked
bogdanm 82:6473597d706e 3608 * - 1 - Enabled
bogdanm 82:6473597d706e 3609 */
bogdanm 82:6473597d706e 3610 //@{
bogdanm 82:6473597d706e 3611 #define BP_SDHC_IRQSTATEN_DCESEN (21U) //!< Bit position for SDHC_IRQSTATEN_DCESEN.
bogdanm 82:6473597d706e 3612 #define BM_SDHC_IRQSTATEN_DCESEN (0x00200000U) //!< Bit mask for SDHC_IRQSTATEN_DCESEN.
bogdanm 82:6473597d706e 3613 #define BS_SDHC_IRQSTATEN_DCESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DCESEN.
bogdanm 82:6473597d706e 3614
bogdanm 82:6473597d706e 3615 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3616 //! @brief Read current value of the SDHC_IRQSTATEN_DCESEN field.
bogdanm 82:6473597d706e 3617 #define BR_SDHC_IRQSTATEN_DCESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DCESEN))
bogdanm 82:6473597d706e 3618 #endif
bogdanm 82:6473597d706e 3619
bogdanm 82:6473597d706e 3620 //! @brief Format value for bitfield SDHC_IRQSTATEN_DCESEN.
bogdanm 82:6473597d706e 3621 #define BF_SDHC_IRQSTATEN_DCESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DCESEN), uint32_t) & BM_SDHC_IRQSTATEN_DCESEN)
bogdanm 82:6473597d706e 3622
bogdanm 82:6473597d706e 3623 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3624 //! @brief Set the DCESEN field to a new value.
bogdanm 82:6473597d706e 3625 #define BW_SDHC_IRQSTATEN_DCESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DCESEN) = (v))
bogdanm 82:6473597d706e 3626 #endif
bogdanm 82:6473597d706e 3627 //@}
bogdanm 82:6473597d706e 3628
bogdanm 82:6473597d706e 3629 /*!
bogdanm 82:6473597d706e 3630 * @name Register SDHC_IRQSTATEN, field DEBESEN[22] (RW)
bogdanm 82:6473597d706e 3631 *
bogdanm 82:6473597d706e 3632 * Values:
bogdanm 82:6473597d706e 3633 * - 0 - Masked
bogdanm 82:6473597d706e 3634 * - 1 - Enabled
bogdanm 82:6473597d706e 3635 */
bogdanm 82:6473597d706e 3636 //@{
bogdanm 82:6473597d706e 3637 #define BP_SDHC_IRQSTATEN_DEBESEN (22U) //!< Bit position for SDHC_IRQSTATEN_DEBESEN.
bogdanm 82:6473597d706e 3638 #define BM_SDHC_IRQSTATEN_DEBESEN (0x00400000U) //!< Bit mask for SDHC_IRQSTATEN_DEBESEN.
bogdanm 82:6473597d706e 3639 #define BS_SDHC_IRQSTATEN_DEBESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DEBESEN.
bogdanm 82:6473597d706e 3640
bogdanm 82:6473597d706e 3641 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3642 //! @brief Read current value of the SDHC_IRQSTATEN_DEBESEN field.
bogdanm 82:6473597d706e 3643 #define BR_SDHC_IRQSTATEN_DEBESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DEBESEN))
bogdanm 82:6473597d706e 3644 #endif
bogdanm 82:6473597d706e 3645
bogdanm 82:6473597d706e 3646 //! @brief Format value for bitfield SDHC_IRQSTATEN_DEBESEN.
bogdanm 82:6473597d706e 3647 #define BF_SDHC_IRQSTATEN_DEBESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DEBESEN), uint32_t) & BM_SDHC_IRQSTATEN_DEBESEN)
bogdanm 82:6473597d706e 3648
bogdanm 82:6473597d706e 3649 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3650 //! @brief Set the DEBESEN field to a new value.
bogdanm 82:6473597d706e 3651 #define BW_SDHC_IRQSTATEN_DEBESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DEBESEN) = (v))
bogdanm 82:6473597d706e 3652 #endif
bogdanm 82:6473597d706e 3653 //@}
bogdanm 82:6473597d706e 3654
bogdanm 82:6473597d706e 3655 /*!
bogdanm 82:6473597d706e 3656 * @name Register SDHC_IRQSTATEN, field AC12ESEN[24] (RW)
bogdanm 82:6473597d706e 3657 *
bogdanm 82:6473597d706e 3658 * Values:
bogdanm 82:6473597d706e 3659 * - 0 - Masked
bogdanm 82:6473597d706e 3660 * - 1 - Enabled
bogdanm 82:6473597d706e 3661 */
bogdanm 82:6473597d706e 3662 //@{
bogdanm 82:6473597d706e 3663 #define BP_SDHC_IRQSTATEN_AC12ESEN (24U) //!< Bit position for SDHC_IRQSTATEN_AC12ESEN.
bogdanm 82:6473597d706e 3664 #define BM_SDHC_IRQSTATEN_AC12ESEN (0x01000000U) //!< Bit mask for SDHC_IRQSTATEN_AC12ESEN.
bogdanm 82:6473597d706e 3665 #define BS_SDHC_IRQSTATEN_AC12ESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_AC12ESEN.
bogdanm 82:6473597d706e 3666
bogdanm 82:6473597d706e 3667 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3668 //! @brief Read current value of the SDHC_IRQSTATEN_AC12ESEN field.
bogdanm 82:6473597d706e 3669 #define BR_SDHC_IRQSTATEN_AC12ESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_AC12ESEN))
bogdanm 82:6473597d706e 3670 #endif
bogdanm 82:6473597d706e 3671
bogdanm 82:6473597d706e 3672 //! @brief Format value for bitfield SDHC_IRQSTATEN_AC12ESEN.
bogdanm 82:6473597d706e 3673 #define BF_SDHC_IRQSTATEN_AC12ESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_AC12ESEN), uint32_t) & BM_SDHC_IRQSTATEN_AC12ESEN)
bogdanm 82:6473597d706e 3674
bogdanm 82:6473597d706e 3675 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3676 //! @brief Set the AC12ESEN field to a new value.
bogdanm 82:6473597d706e 3677 #define BW_SDHC_IRQSTATEN_AC12ESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_AC12ESEN) = (v))
bogdanm 82:6473597d706e 3678 #endif
bogdanm 82:6473597d706e 3679 //@}
bogdanm 82:6473597d706e 3680
bogdanm 82:6473597d706e 3681 /*!
bogdanm 82:6473597d706e 3682 * @name Register SDHC_IRQSTATEN, field DMAESEN[28] (RW)
bogdanm 82:6473597d706e 3683 *
bogdanm 82:6473597d706e 3684 * Values:
bogdanm 82:6473597d706e 3685 * - 0 - Masked
bogdanm 82:6473597d706e 3686 * - 1 - Enabled
bogdanm 82:6473597d706e 3687 */
bogdanm 82:6473597d706e 3688 //@{
bogdanm 82:6473597d706e 3689 #define BP_SDHC_IRQSTATEN_DMAESEN (28U) //!< Bit position for SDHC_IRQSTATEN_DMAESEN.
bogdanm 82:6473597d706e 3690 #define BM_SDHC_IRQSTATEN_DMAESEN (0x10000000U) //!< Bit mask for SDHC_IRQSTATEN_DMAESEN.
bogdanm 82:6473597d706e 3691 #define BS_SDHC_IRQSTATEN_DMAESEN (1U) //!< Bit field size in bits for SDHC_IRQSTATEN_DMAESEN.
bogdanm 82:6473597d706e 3692
bogdanm 82:6473597d706e 3693 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3694 //! @brief Read current value of the SDHC_IRQSTATEN_DMAESEN field.
bogdanm 82:6473597d706e 3695 #define BR_SDHC_IRQSTATEN_DMAESEN (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DMAESEN))
bogdanm 82:6473597d706e 3696 #endif
bogdanm 82:6473597d706e 3697
bogdanm 82:6473597d706e 3698 //! @brief Format value for bitfield SDHC_IRQSTATEN_DMAESEN.
bogdanm 82:6473597d706e 3699 #define BF_SDHC_IRQSTATEN_DMAESEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSTATEN_DMAESEN), uint32_t) & BM_SDHC_IRQSTATEN_DMAESEN)
bogdanm 82:6473597d706e 3700
bogdanm 82:6473597d706e 3701 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3702 //! @brief Set the DMAESEN field to a new value.
bogdanm 82:6473597d706e 3703 #define BW_SDHC_IRQSTATEN_DMAESEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSTATEN_ADDR, BP_SDHC_IRQSTATEN_DMAESEN) = (v))
bogdanm 82:6473597d706e 3704 #endif
bogdanm 82:6473597d706e 3705 //@}
bogdanm 82:6473597d706e 3706
bogdanm 82:6473597d706e 3707 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3708 // HW_SDHC_IRQSIGEN - Interrupt Signal Enable register
bogdanm 82:6473597d706e 3709 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 3710
bogdanm 82:6473597d706e 3711 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3712 /*!
bogdanm 82:6473597d706e 3713 * @brief HW_SDHC_IRQSIGEN - Interrupt Signal Enable register (RW)
bogdanm 82:6473597d706e 3714 *
bogdanm 82:6473597d706e 3715 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 3716 *
bogdanm 82:6473597d706e 3717 * This register is used to select which interrupt status is indicated to the
bogdanm 82:6473597d706e 3718 * host system as the interrupt. All of these status bits share the same interrupt
bogdanm 82:6473597d706e 3719 * line. Setting any of these bits to 1 enables interrupt generation. The
bogdanm 82:6473597d706e 3720 * corresponding status register bit will generate an interrupt when the corresponding
bogdanm 82:6473597d706e 3721 * interrupt signal enable bit is set.
bogdanm 82:6473597d706e 3722 */
bogdanm 82:6473597d706e 3723 typedef union _hw_sdhc_irqsigen
bogdanm 82:6473597d706e 3724 {
bogdanm 82:6473597d706e 3725 uint32_t U;
bogdanm 82:6473597d706e 3726 struct _hw_sdhc_irqsigen_bitfields
bogdanm 82:6473597d706e 3727 {
bogdanm 82:6473597d706e 3728 uint32_t CCIEN : 1; //!< [0] Command Complete Interrupt Enable
bogdanm 82:6473597d706e 3729 uint32_t TCIEN : 1; //!< [1] Transfer Complete Interrupt Enable
bogdanm 82:6473597d706e 3730 uint32_t BGEIEN : 1; //!< [2] Block Gap Event Interrupt Enable
bogdanm 82:6473597d706e 3731 uint32_t DINTIEN : 1; //!< [3] DMA Interrupt Enable
bogdanm 82:6473597d706e 3732 uint32_t BWRIEN : 1; //!< [4] Buffer Write Ready Interrupt Enable
bogdanm 82:6473597d706e 3733 uint32_t BRRIEN : 1; //!< [5] Buffer Read Ready Interrupt Enable
bogdanm 82:6473597d706e 3734 uint32_t CINSIEN : 1; //!< [6] Card Insertion Interrupt Enable
bogdanm 82:6473597d706e 3735 uint32_t CRMIEN : 1; //!< [7] Card Removal Interrupt Enable
bogdanm 82:6473597d706e 3736 uint32_t CINTIEN : 1; //!< [8] Card Interrupt Enable
bogdanm 82:6473597d706e 3737 uint32_t RESERVED0 : 7; //!< [15:9]
bogdanm 82:6473597d706e 3738 uint32_t CTOEIEN : 1; //!< [16] Command Timeout Error Interrupt Enable
bogdanm 82:6473597d706e 3739 uint32_t CCEIEN : 1; //!< [17] Command CRC Error Interrupt Enable
bogdanm 82:6473597d706e 3740 uint32_t CEBEIEN : 1; //!< [18] Command End Bit Error Interrupt Enable
bogdanm 82:6473597d706e 3741 uint32_t CIEIEN : 1; //!< [19] Command Index Error Interrupt Enable
bogdanm 82:6473597d706e 3742 uint32_t DTOEIEN : 1; //!< [20] Data Timeout Error Interrupt Enable
bogdanm 82:6473597d706e 3743 uint32_t DCEIEN : 1; //!< [21] Data CRC Error Interrupt Enable
bogdanm 82:6473597d706e 3744 uint32_t DEBEIEN : 1; //!< [22] Data End Bit Error Interrupt Enable
bogdanm 82:6473597d706e 3745 uint32_t RESERVED1 : 1; //!< [23]
bogdanm 82:6473597d706e 3746 uint32_t AC12EIEN : 1; //!< [24] Auto CMD12 Error Interrupt Enable
bogdanm 82:6473597d706e 3747 uint32_t RESERVED2 : 3; //!< [27:25]
bogdanm 82:6473597d706e 3748 uint32_t DMAEIEN : 1; //!< [28] DMA Error Interrupt Enable
bogdanm 82:6473597d706e 3749 uint32_t RESERVED3 : 3; //!< [31:29]
bogdanm 82:6473597d706e 3750 } B;
bogdanm 82:6473597d706e 3751 } hw_sdhc_irqsigen_t;
bogdanm 82:6473597d706e 3752 #endif
bogdanm 82:6473597d706e 3753
bogdanm 82:6473597d706e 3754 /*!
bogdanm 82:6473597d706e 3755 * @name Constants and macros for entire SDHC_IRQSIGEN register
bogdanm 82:6473597d706e 3756 */
bogdanm 82:6473597d706e 3757 //@{
bogdanm 82:6473597d706e 3758 #define HW_SDHC_IRQSIGEN_ADDR (REGS_SDHC_BASE + 0x38U)
bogdanm 82:6473597d706e 3759
bogdanm 82:6473597d706e 3760 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3761 #define HW_SDHC_IRQSIGEN (*(__IO hw_sdhc_irqsigen_t *) HW_SDHC_IRQSIGEN_ADDR)
bogdanm 82:6473597d706e 3762 #define HW_SDHC_IRQSIGEN_RD() (HW_SDHC_IRQSIGEN.U)
bogdanm 82:6473597d706e 3763 #define HW_SDHC_IRQSIGEN_WR(v) (HW_SDHC_IRQSIGEN.U = (v))
bogdanm 82:6473597d706e 3764 #define HW_SDHC_IRQSIGEN_SET(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() | (v)))
bogdanm 82:6473597d706e 3765 #define HW_SDHC_IRQSIGEN_CLR(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() & ~(v)))
bogdanm 82:6473597d706e 3766 #define HW_SDHC_IRQSIGEN_TOG(v) (HW_SDHC_IRQSIGEN_WR(HW_SDHC_IRQSIGEN_RD() ^ (v)))
bogdanm 82:6473597d706e 3767 #endif
bogdanm 82:6473597d706e 3768 //@}
bogdanm 82:6473597d706e 3769
bogdanm 82:6473597d706e 3770 /*
bogdanm 82:6473597d706e 3771 * Constants & macros for individual SDHC_IRQSIGEN bitfields
bogdanm 82:6473597d706e 3772 */
bogdanm 82:6473597d706e 3773
bogdanm 82:6473597d706e 3774 /*!
bogdanm 82:6473597d706e 3775 * @name Register SDHC_IRQSIGEN, field CCIEN[0] (RW)
bogdanm 82:6473597d706e 3776 *
bogdanm 82:6473597d706e 3777 * Values:
bogdanm 82:6473597d706e 3778 * - 0 - Masked
bogdanm 82:6473597d706e 3779 * - 1 - Enabled
bogdanm 82:6473597d706e 3780 */
bogdanm 82:6473597d706e 3781 //@{
bogdanm 82:6473597d706e 3782 #define BP_SDHC_IRQSIGEN_CCIEN (0U) //!< Bit position for SDHC_IRQSIGEN_CCIEN.
bogdanm 82:6473597d706e 3783 #define BM_SDHC_IRQSIGEN_CCIEN (0x00000001U) //!< Bit mask for SDHC_IRQSIGEN_CCIEN.
bogdanm 82:6473597d706e 3784 #define BS_SDHC_IRQSIGEN_CCIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CCIEN.
bogdanm 82:6473597d706e 3785
bogdanm 82:6473597d706e 3786 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3787 //! @brief Read current value of the SDHC_IRQSIGEN_CCIEN field.
bogdanm 82:6473597d706e 3788 #define BR_SDHC_IRQSIGEN_CCIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCIEN))
bogdanm 82:6473597d706e 3789 #endif
bogdanm 82:6473597d706e 3790
bogdanm 82:6473597d706e 3791 //! @brief Format value for bitfield SDHC_IRQSIGEN_CCIEN.
bogdanm 82:6473597d706e 3792 #define BF_SDHC_IRQSIGEN_CCIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CCIEN), uint32_t) & BM_SDHC_IRQSIGEN_CCIEN)
bogdanm 82:6473597d706e 3793
bogdanm 82:6473597d706e 3794 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3795 //! @brief Set the CCIEN field to a new value.
bogdanm 82:6473597d706e 3796 #define BW_SDHC_IRQSIGEN_CCIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCIEN) = (v))
bogdanm 82:6473597d706e 3797 #endif
bogdanm 82:6473597d706e 3798 //@}
bogdanm 82:6473597d706e 3799
bogdanm 82:6473597d706e 3800 /*!
bogdanm 82:6473597d706e 3801 * @name Register SDHC_IRQSIGEN, field TCIEN[1] (RW)
bogdanm 82:6473597d706e 3802 *
bogdanm 82:6473597d706e 3803 * Values:
bogdanm 82:6473597d706e 3804 * - 0 - Masked
bogdanm 82:6473597d706e 3805 * - 1 - Enabled
bogdanm 82:6473597d706e 3806 */
bogdanm 82:6473597d706e 3807 //@{
bogdanm 82:6473597d706e 3808 #define BP_SDHC_IRQSIGEN_TCIEN (1U) //!< Bit position for SDHC_IRQSIGEN_TCIEN.
bogdanm 82:6473597d706e 3809 #define BM_SDHC_IRQSIGEN_TCIEN (0x00000002U) //!< Bit mask for SDHC_IRQSIGEN_TCIEN.
bogdanm 82:6473597d706e 3810 #define BS_SDHC_IRQSIGEN_TCIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_TCIEN.
bogdanm 82:6473597d706e 3811
bogdanm 82:6473597d706e 3812 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3813 //! @brief Read current value of the SDHC_IRQSIGEN_TCIEN field.
bogdanm 82:6473597d706e 3814 #define BR_SDHC_IRQSIGEN_TCIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_TCIEN))
bogdanm 82:6473597d706e 3815 #endif
bogdanm 82:6473597d706e 3816
bogdanm 82:6473597d706e 3817 //! @brief Format value for bitfield SDHC_IRQSIGEN_TCIEN.
bogdanm 82:6473597d706e 3818 #define BF_SDHC_IRQSIGEN_TCIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_TCIEN), uint32_t) & BM_SDHC_IRQSIGEN_TCIEN)
bogdanm 82:6473597d706e 3819
bogdanm 82:6473597d706e 3820 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3821 //! @brief Set the TCIEN field to a new value.
bogdanm 82:6473597d706e 3822 #define BW_SDHC_IRQSIGEN_TCIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_TCIEN) = (v))
bogdanm 82:6473597d706e 3823 #endif
bogdanm 82:6473597d706e 3824 //@}
bogdanm 82:6473597d706e 3825
bogdanm 82:6473597d706e 3826 /*!
bogdanm 82:6473597d706e 3827 * @name Register SDHC_IRQSIGEN, field BGEIEN[2] (RW)
bogdanm 82:6473597d706e 3828 *
bogdanm 82:6473597d706e 3829 * Values:
bogdanm 82:6473597d706e 3830 * - 0 - Masked
bogdanm 82:6473597d706e 3831 * - 1 - Enabled
bogdanm 82:6473597d706e 3832 */
bogdanm 82:6473597d706e 3833 //@{
bogdanm 82:6473597d706e 3834 #define BP_SDHC_IRQSIGEN_BGEIEN (2U) //!< Bit position for SDHC_IRQSIGEN_BGEIEN.
bogdanm 82:6473597d706e 3835 #define BM_SDHC_IRQSIGEN_BGEIEN (0x00000004U) //!< Bit mask for SDHC_IRQSIGEN_BGEIEN.
bogdanm 82:6473597d706e 3836 #define BS_SDHC_IRQSIGEN_BGEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BGEIEN.
bogdanm 82:6473597d706e 3837
bogdanm 82:6473597d706e 3838 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3839 //! @brief Read current value of the SDHC_IRQSIGEN_BGEIEN field.
bogdanm 82:6473597d706e 3840 #define BR_SDHC_IRQSIGEN_BGEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BGEIEN))
bogdanm 82:6473597d706e 3841 #endif
bogdanm 82:6473597d706e 3842
bogdanm 82:6473597d706e 3843 //! @brief Format value for bitfield SDHC_IRQSIGEN_BGEIEN.
bogdanm 82:6473597d706e 3844 #define BF_SDHC_IRQSIGEN_BGEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BGEIEN), uint32_t) & BM_SDHC_IRQSIGEN_BGEIEN)
bogdanm 82:6473597d706e 3845
bogdanm 82:6473597d706e 3846 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3847 //! @brief Set the BGEIEN field to a new value.
bogdanm 82:6473597d706e 3848 #define BW_SDHC_IRQSIGEN_BGEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BGEIEN) = (v))
bogdanm 82:6473597d706e 3849 #endif
bogdanm 82:6473597d706e 3850 //@}
bogdanm 82:6473597d706e 3851
bogdanm 82:6473597d706e 3852 /*!
bogdanm 82:6473597d706e 3853 * @name Register SDHC_IRQSIGEN, field DINTIEN[3] (RW)
bogdanm 82:6473597d706e 3854 *
bogdanm 82:6473597d706e 3855 * Values:
bogdanm 82:6473597d706e 3856 * - 0 - Masked
bogdanm 82:6473597d706e 3857 * - 1 - Enabled
bogdanm 82:6473597d706e 3858 */
bogdanm 82:6473597d706e 3859 //@{
bogdanm 82:6473597d706e 3860 #define BP_SDHC_IRQSIGEN_DINTIEN (3U) //!< Bit position for SDHC_IRQSIGEN_DINTIEN.
bogdanm 82:6473597d706e 3861 #define BM_SDHC_IRQSIGEN_DINTIEN (0x00000008U) //!< Bit mask for SDHC_IRQSIGEN_DINTIEN.
bogdanm 82:6473597d706e 3862 #define BS_SDHC_IRQSIGEN_DINTIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DINTIEN.
bogdanm 82:6473597d706e 3863
bogdanm 82:6473597d706e 3864 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3865 //! @brief Read current value of the SDHC_IRQSIGEN_DINTIEN field.
bogdanm 82:6473597d706e 3866 #define BR_SDHC_IRQSIGEN_DINTIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DINTIEN))
bogdanm 82:6473597d706e 3867 #endif
bogdanm 82:6473597d706e 3868
bogdanm 82:6473597d706e 3869 //! @brief Format value for bitfield SDHC_IRQSIGEN_DINTIEN.
bogdanm 82:6473597d706e 3870 #define BF_SDHC_IRQSIGEN_DINTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DINTIEN), uint32_t) & BM_SDHC_IRQSIGEN_DINTIEN)
bogdanm 82:6473597d706e 3871
bogdanm 82:6473597d706e 3872 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3873 //! @brief Set the DINTIEN field to a new value.
bogdanm 82:6473597d706e 3874 #define BW_SDHC_IRQSIGEN_DINTIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DINTIEN) = (v))
bogdanm 82:6473597d706e 3875 #endif
bogdanm 82:6473597d706e 3876 //@}
bogdanm 82:6473597d706e 3877
bogdanm 82:6473597d706e 3878 /*!
bogdanm 82:6473597d706e 3879 * @name Register SDHC_IRQSIGEN, field BWRIEN[4] (RW)
bogdanm 82:6473597d706e 3880 *
bogdanm 82:6473597d706e 3881 * Values:
bogdanm 82:6473597d706e 3882 * - 0 - Masked
bogdanm 82:6473597d706e 3883 * - 1 - Enabled
bogdanm 82:6473597d706e 3884 */
bogdanm 82:6473597d706e 3885 //@{
bogdanm 82:6473597d706e 3886 #define BP_SDHC_IRQSIGEN_BWRIEN (4U) //!< Bit position for SDHC_IRQSIGEN_BWRIEN.
bogdanm 82:6473597d706e 3887 #define BM_SDHC_IRQSIGEN_BWRIEN (0x00000010U) //!< Bit mask for SDHC_IRQSIGEN_BWRIEN.
bogdanm 82:6473597d706e 3888 #define BS_SDHC_IRQSIGEN_BWRIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BWRIEN.
bogdanm 82:6473597d706e 3889
bogdanm 82:6473597d706e 3890 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3891 //! @brief Read current value of the SDHC_IRQSIGEN_BWRIEN field.
bogdanm 82:6473597d706e 3892 #define BR_SDHC_IRQSIGEN_BWRIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BWRIEN))
bogdanm 82:6473597d706e 3893 #endif
bogdanm 82:6473597d706e 3894
bogdanm 82:6473597d706e 3895 //! @brief Format value for bitfield SDHC_IRQSIGEN_BWRIEN.
bogdanm 82:6473597d706e 3896 #define BF_SDHC_IRQSIGEN_BWRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BWRIEN), uint32_t) & BM_SDHC_IRQSIGEN_BWRIEN)
bogdanm 82:6473597d706e 3897
bogdanm 82:6473597d706e 3898 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3899 //! @brief Set the BWRIEN field to a new value.
bogdanm 82:6473597d706e 3900 #define BW_SDHC_IRQSIGEN_BWRIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BWRIEN) = (v))
bogdanm 82:6473597d706e 3901 #endif
bogdanm 82:6473597d706e 3902 //@}
bogdanm 82:6473597d706e 3903
bogdanm 82:6473597d706e 3904 /*!
bogdanm 82:6473597d706e 3905 * @name Register SDHC_IRQSIGEN, field BRRIEN[5] (RW)
bogdanm 82:6473597d706e 3906 *
bogdanm 82:6473597d706e 3907 * Values:
bogdanm 82:6473597d706e 3908 * - 0 - Masked
bogdanm 82:6473597d706e 3909 * - 1 - Enabled
bogdanm 82:6473597d706e 3910 */
bogdanm 82:6473597d706e 3911 //@{
bogdanm 82:6473597d706e 3912 #define BP_SDHC_IRQSIGEN_BRRIEN (5U) //!< Bit position for SDHC_IRQSIGEN_BRRIEN.
bogdanm 82:6473597d706e 3913 #define BM_SDHC_IRQSIGEN_BRRIEN (0x00000020U) //!< Bit mask for SDHC_IRQSIGEN_BRRIEN.
bogdanm 82:6473597d706e 3914 #define BS_SDHC_IRQSIGEN_BRRIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_BRRIEN.
bogdanm 82:6473597d706e 3915
bogdanm 82:6473597d706e 3916 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3917 //! @brief Read current value of the SDHC_IRQSIGEN_BRRIEN field.
bogdanm 82:6473597d706e 3918 #define BR_SDHC_IRQSIGEN_BRRIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BRRIEN))
bogdanm 82:6473597d706e 3919 #endif
bogdanm 82:6473597d706e 3920
bogdanm 82:6473597d706e 3921 //! @brief Format value for bitfield SDHC_IRQSIGEN_BRRIEN.
bogdanm 82:6473597d706e 3922 #define BF_SDHC_IRQSIGEN_BRRIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_BRRIEN), uint32_t) & BM_SDHC_IRQSIGEN_BRRIEN)
bogdanm 82:6473597d706e 3923
bogdanm 82:6473597d706e 3924 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3925 //! @brief Set the BRRIEN field to a new value.
bogdanm 82:6473597d706e 3926 #define BW_SDHC_IRQSIGEN_BRRIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_BRRIEN) = (v))
bogdanm 82:6473597d706e 3927 #endif
bogdanm 82:6473597d706e 3928 //@}
bogdanm 82:6473597d706e 3929
bogdanm 82:6473597d706e 3930 /*!
bogdanm 82:6473597d706e 3931 * @name Register SDHC_IRQSIGEN, field CINSIEN[6] (RW)
bogdanm 82:6473597d706e 3932 *
bogdanm 82:6473597d706e 3933 * Values:
bogdanm 82:6473597d706e 3934 * - 0 - Masked
bogdanm 82:6473597d706e 3935 * - 1 - Enabled
bogdanm 82:6473597d706e 3936 */
bogdanm 82:6473597d706e 3937 //@{
bogdanm 82:6473597d706e 3938 #define BP_SDHC_IRQSIGEN_CINSIEN (6U) //!< Bit position for SDHC_IRQSIGEN_CINSIEN.
bogdanm 82:6473597d706e 3939 #define BM_SDHC_IRQSIGEN_CINSIEN (0x00000040U) //!< Bit mask for SDHC_IRQSIGEN_CINSIEN.
bogdanm 82:6473597d706e 3940 #define BS_SDHC_IRQSIGEN_CINSIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CINSIEN.
bogdanm 82:6473597d706e 3941
bogdanm 82:6473597d706e 3942 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3943 //! @brief Read current value of the SDHC_IRQSIGEN_CINSIEN field.
bogdanm 82:6473597d706e 3944 #define BR_SDHC_IRQSIGEN_CINSIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINSIEN))
bogdanm 82:6473597d706e 3945 #endif
bogdanm 82:6473597d706e 3946
bogdanm 82:6473597d706e 3947 //! @brief Format value for bitfield SDHC_IRQSIGEN_CINSIEN.
bogdanm 82:6473597d706e 3948 #define BF_SDHC_IRQSIGEN_CINSIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CINSIEN), uint32_t) & BM_SDHC_IRQSIGEN_CINSIEN)
bogdanm 82:6473597d706e 3949
bogdanm 82:6473597d706e 3950 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3951 //! @brief Set the CINSIEN field to a new value.
bogdanm 82:6473597d706e 3952 #define BW_SDHC_IRQSIGEN_CINSIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINSIEN) = (v))
bogdanm 82:6473597d706e 3953 #endif
bogdanm 82:6473597d706e 3954 //@}
bogdanm 82:6473597d706e 3955
bogdanm 82:6473597d706e 3956 /*!
bogdanm 82:6473597d706e 3957 * @name Register SDHC_IRQSIGEN, field CRMIEN[7] (RW)
bogdanm 82:6473597d706e 3958 *
bogdanm 82:6473597d706e 3959 * Values:
bogdanm 82:6473597d706e 3960 * - 0 - Masked
bogdanm 82:6473597d706e 3961 * - 1 - Enabled
bogdanm 82:6473597d706e 3962 */
bogdanm 82:6473597d706e 3963 //@{
bogdanm 82:6473597d706e 3964 #define BP_SDHC_IRQSIGEN_CRMIEN (7U) //!< Bit position for SDHC_IRQSIGEN_CRMIEN.
bogdanm 82:6473597d706e 3965 #define BM_SDHC_IRQSIGEN_CRMIEN (0x00000080U) //!< Bit mask for SDHC_IRQSIGEN_CRMIEN.
bogdanm 82:6473597d706e 3966 #define BS_SDHC_IRQSIGEN_CRMIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CRMIEN.
bogdanm 82:6473597d706e 3967
bogdanm 82:6473597d706e 3968 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3969 //! @brief Read current value of the SDHC_IRQSIGEN_CRMIEN field.
bogdanm 82:6473597d706e 3970 #define BR_SDHC_IRQSIGEN_CRMIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CRMIEN))
bogdanm 82:6473597d706e 3971 #endif
bogdanm 82:6473597d706e 3972
bogdanm 82:6473597d706e 3973 //! @brief Format value for bitfield SDHC_IRQSIGEN_CRMIEN.
bogdanm 82:6473597d706e 3974 #define BF_SDHC_IRQSIGEN_CRMIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CRMIEN), uint32_t) & BM_SDHC_IRQSIGEN_CRMIEN)
bogdanm 82:6473597d706e 3975
bogdanm 82:6473597d706e 3976 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3977 //! @brief Set the CRMIEN field to a new value.
bogdanm 82:6473597d706e 3978 #define BW_SDHC_IRQSIGEN_CRMIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CRMIEN) = (v))
bogdanm 82:6473597d706e 3979 #endif
bogdanm 82:6473597d706e 3980 //@}
bogdanm 82:6473597d706e 3981
bogdanm 82:6473597d706e 3982 /*!
bogdanm 82:6473597d706e 3983 * @name Register SDHC_IRQSIGEN, field CINTIEN[8] (RW)
bogdanm 82:6473597d706e 3984 *
bogdanm 82:6473597d706e 3985 * Values:
bogdanm 82:6473597d706e 3986 * - 0 - Masked
bogdanm 82:6473597d706e 3987 * - 1 - Enabled
bogdanm 82:6473597d706e 3988 */
bogdanm 82:6473597d706e 3989 //@{
bogdanm 82:6473597d706e 3990 #define BP_SDHC_IRQSIGEN_CINTIEN (8U) //!< Bit position for SDHC_IRQSIGEN_CINTIEN.
bogdanm 82:6473597d706e 3991 #define BM_SDHC_IRQSIGEN_CINTIEN (0x00000100U) //!< Bit mask for SDHC_IRQSIGEN_CINTIEN.
bogdanm 82:6473597d706e 3992 #define BS_SDHC_IRQSIGEN_CINTIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CINTIEN.
bogdanm 82:6473597d706e 3993
bogdanm 82:6473597d706e 3994 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 3995 //! @brief Read current value of the SDHC_IRQSIGEN_CINTIEN field.
bogdanm 82:6473597d706e 3996 #define BR_SDHC_IRQSIGEN_CINTIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINTIEN))
bogdanm 82:6473597d706e 3997 #endif
bogdanm 82:6473597d706e 3998
bogdanm 82:6473597d706e 3999 //! @brief Format value for bitfield SDHC_IRQSIGEN_CINTIEN.
bogdanm 82:6473597d706e 4000 #define BF_SDHC_IRQSIGEN_CINTIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CINTIEN), uint32_t) & BM_SDHC_IRQSIGEN_CINTIEN)
bogdanm 82:6473597d706e 4001
bogdanm 82:6473597d706e 4002 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4003 //! @brief Set the CINTIEN field to a new value.
bogdanm 82:6473597d706e 4004 #define BW_SDHC_IRQSIGEN_CINTIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CINTIEN) = (v))
bogdanm 82:6473597d706e 4005 #endif
bogdanm 82:6473597d706e 4006 //@}
bogdanm 82:6473597d706e 4007
bogdanm 82:6473597d706e 4008 /*!
bogdanm 82:6473597d706e 4009 * @name Register SDHC_IRQSIGEN, field CTOEIEN[16] (RW)
bogdanm 82:6473597d706e 4010 *
bogdanm 82:6473597d706e 4011 * Values:
bogdanm 82:6473597d706e 4012 * - 0 - Masked
bogdanm 82:6473597d706e 4013 * - 1 - Enabled
bogdanm 82:6473597d706e 4014 */
bogdanm 82:6473597d706e 4015 //@{
bogdanm 82:6473597d706e 4016 #define BP_SDHC_IRQSIGEN_CTOEIEN (16U) //!< Bit position for SDHC_IRQSIGEN_CTOEIEN.
bogdanm 82:6473597d706e 4017 #define BM_SDHC_IRQSIGEN_CTOEIEN (0x00010000U) //!< Bit mask for SDHC_IRQSIGEN_CTOEIEN.
bogdanm 82:6473597d706e 4018 #define BS_SDHC_IRQSIGEN_CTOEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CTOEIEN.
bogdanm 82:6473597d706e 4019
bogdanm 82:6473597d706e 4020 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4021 //! @brief Read current value of the SDHC_IRQSIGEN_CTOEIEN field.
bogdanm 82:6473597d706e 4022 #define BR_SDHC_IRQSIGEN_CTOEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CTOEIEN))
bogdanm 82:6473597d706e 4023 #endif
bogdanm 82:6473597d706e 4024
bogdanm 82:6473597d706e 4025 //! @brief Format value for bitfield SDHC_IRQSIGEN_CTOEIEN.
bogdanm 82:6473597d706e 4026 #define BF_SDHC_IRQSIGEN_CTOEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CTOEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CTOEIEN)
bogdanm 82:6473597d706e 4027
bogdanm 82:6473597d706e 4028 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4029 //! @brief Set the CTOEIEN field to a new value.
bogdanm 82:6473597d706e 4030 #define BW_SDHC_IRQSIGEN_CTOEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CTOEIEN) = (v))
bogdanm 82:6473597d706e 4031 #endif
bogdanm 82:6473597d706e 4032 //@}
bogdanm 82:6473597d706e 4033
bogdanm 82:6473597d706e 4034 /*!
bogdanm 82:6473597d706e 4035 * @name Register SDHC_IRQSIGEN, field CCEIEN[17] (RW)
bogdanm 82:6473597d706e 4036 *
bogdanm 82:6473597d706e 4037 * Values:
bogdanm 82:6473597d706e 4038 * - 0 - Masked
bogdanm 82:6473597d706e 4039 * - 1 - Enabled
bogdanm 82:6473597d706e 4040 */
bogdanm 82:6473597d706e 4041 //@{
bogdanm 82:6473597d706e 4042 #define BP_SDHC_IRQSIGEN_CCEIEN (17U) //!< Bit position for SDHC_IRQSIGEN_CCEIEN.
bogdanm 82:6473597d706e 4043 #define BM_SDHC_IRQSIGEN_CCEIEN (0x00020000U) //!< Bit mask for SDHC_IRQSIGEN_CCEIEN.
bogdanm 82:6473597d706e 4044 #define BS_SDHC_IRQSIGEN_CCEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CCEIEN.
bogdanm 82:6473597d706e 4045
bogdanm 82:6473597d706e 4046 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4047 //! @brief Read current value of the SDHC_IRQSIGEN_CCEIEN field.
bogdanm 82:6473597d706e 4048 #define BR_SDHC_IRQSIGEN_CCEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCEIEN))
bogdanm 82:6473597d706e 4049 #endif
bogdanm 82:6473597d706e 4050
bogdanm 82:6473597d706e 4051 //! @brief Format value for bitfield SDHC_IRQSIGEN_CCEIEN.
bogdanm 82:6473597d706e 4052 #define BF_SDHC_IRQSIGEN_CCEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CCEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CCEIEN)
bogdanm 82:6473597d706e 4053
bogdanm 82:6473597d706e 4054 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4055 //! @brief Set the CCEIEN field to a new value.
bogdanm 82:6473597d706e 4056 #define BW_SDHC_IRQSIGEN_CCEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CCEIEN) = (v))
bogdanm 82:6473597d706e 4057 #endif
bogdanm 82:6473597d706e 4058 //@}
bogdanm 82:6473597d706e 4059
bogdanm 82:6473597d706e 4060 /*!
bogdanm 82:6473597d706e 4061 * @name Register SDHC_IRQSIGEN, field CEBEIEN[18] (RW)
bogdanm 82:6473597d706e 4062 *
bogdanm 82:6473597d706e 4063 * Values:
bogdanm 82:6473597d706e 4064 * - 0 - Masked
bogdanm 82:6473597d706e 4065 * - 1 - Enabled
bogdanm 82:6473597d706e 4066 */
bogdanm 82:6473597d706e 4067 //@{
bogdanm 82:6473597d706e 4068 #define BP_SDHC_IRQSIGEN_CEBEIEN (18U) //!< Bit position for SDHC_IRQSIGEN_CEBEIEN.
bogdanm 82:6473597d706e 4069 #define BM_SDHC_IRQSIGEN_CEBEIEN (0x00040000U) //!< Bit mask for SDHC_IRQSIGEN_CEBEIEN.
bogdanm 82:6473597d706e 4070 #define BS_SDHC_IRQSIGEN_CEBEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CEBEIEN.
bogdanm 82:6473597d706e 4071
bogdanm 82:6473597d706e 4072 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4073 //! @brief Read current value of the SDHC_IRQSIGEN_CEBEIEN field.
bogdanm 82:6473597d706e 4074 #define BR_SDHC_IRQSIGEN_CEBEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CEBEIEN))
bogdanm 82:6473597d706e 4075 #endif
bogdanm 82:6473597d706e 4076
bogdanm 82:6473597d706e 4077 //! @brief Format value for bitfield SDHC_IRQSIGEN_CEBEIEN.
bogdanm 82:6473597d706e 4078 #define BF_SDHC_IRQSIGEN_CEBEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CEBEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CEBEIEN)
bogdanm 82:6473597d706e 4079
bogdanm 82:6473597d706e 4080 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4081 //! @brief Set the CEBEIEN field to a new value.
bogdanm 82:6473597d706e 4082 #define BW_SDHC_IRQSIGEN_CEBEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CEBEIEN) = (v))
bogdanm 82:6473597d706e 4083 #endif
bogdanm 82:6473597d706e 4084 //@}
bogdanm 82:6473597d706e 4085
bogdanm 82:6473597d706e 4086 /*!
bogdanm 82:6473597d706e 4087 * @name Register SDHC_IRQSIGEN, field CIEIEN[19] (RW)
bogdanm 82:6473597d706e 4088 *
bogdanm 82:6473597d706e 4089 * Values:
bogdanm 82:6473597d706e 4090 * - 0 - Masked
bogdanm 82:6473597d706e 4091 * - 1 - Enabled
bogdanm 82:6473597d706e 4092 */
bogdanm 82:6473597d706e 4093 //@{
bogdanm 82:6473597d706e 4094 #define BP_SDHC_IRQSIGEN_CIEIEN (19U) //!< Bit position for SDHC_IRQSIGEN_CIEIEN.
bogdanm 82:6473597d706e 4095 #define BM_SDHC_IRQSIGEN_CIEIEN (0x00080000U) //!< Bit mask for SDHC_IRQSIGEN_CIEIEN.
bogdanm 82:6473597d706e 4096 #define BS_SDHC_IRQSIGEN_CIEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_CIEIEN.
bogdanm 82:6473597d706e 4097
bogdanm 82:6473597d706e 4098 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4099 //! @brief Read current value of the SDHC_IRQSIGEN_CIEIEN field.
bogdanm 82:6473597d706e 4100 #define BR_SDHC_IRQSIGEN_CIEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CIEIEN))
bogdanm 82:6473597d706e 4101 #endif
bogdanm 82:6473597d706e 4102
bogdanm 82:6473597d706e 4103 //! @brief Format value for bitfield SDHC_IRQSIGEN_CIEIEN.
bogdanm 82:6473597d706e 4104 #define BF_SDHC_IRQSIGEN_CIEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_CIEIEN), uint32_t) & BM_SDHC_IRQSIGEN_CIEIEN)
bogdanm 82:6473597d706e 4105
bogdanm 82:6473597d706e 4106 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4107 //! @brief Set the CIEIEN field to a new value.
bogdanm 82:6473597d706e 4108 #define BW_SDHC_IRQSIGEN_CIEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_CIEIEN) = (v))
bogdanm 82:6473597d706e 4109 #endif
bogdanm 82:6473597d706e 4110 //@}
bogdanm 82:6473597d706e 4111
bogdanm 82:6473597d706e 4112 /*!
bogdanm 82:6473597d706e 4113 * @name Register SDHC_IRQSIGEN, field DTOEIEN[20] (RW)
bogdanm 82:6473597d706e 4114 *
bogdanm 82:6473597d706e 4115 * Values:
bogdanm 82:6473597d706e 4116 * - 0 - Masked
bogdanm 82:6473597d706e 4117 * - 1 - Enabled
bogdanm 82:6473597d706e 4118 */
bogdanm 82:6473597d706e 4119 //@{
bogdanm 82:6473597d706e 4120 #define BP_SDHC_IRQSIGEN_DTOEIEN (20U) //!< Bit position for SDHC_IRQSIGEN_DTOEIEN.
bogdanm 82:6473597d706e 4121 #define BM_SDHC_IRQSIGEN_DTOEIEN (0x00100000U) //!< Bit mask for SDHC_IRQSIGEN_DTOEIEN.
bogdanm 82:6473597d706e 4122 #define BS_SDHC_IRQSIGEN_DTOEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DTOEIEN.
bogdanm 82:6473597d706e 4123
bogdanm 82:6473597d706e 4124 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4125 //! @brief Read current value of the SDHC_IRQSIGEN_DTOEIEN field.
bogdanm 82:6473597d706e 4126 #define BR_SDHC_IRQSIGEN_DTOEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DTOEIEN))
bogdanm 82:6473597d706e 4127 #endif
bogdanm 82:6473597d706e 4128
bogdanm 82:6473597d706e 4129 //! @brief Format value for bitfield SDHC_IRQSIGEN_DTOEIEN.
bogdanm 82:6473597d706e 4130 #define BF_SDHC_IRQSIGEN_DTOEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DTOEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DTOEIEN)
bogdanm 82:6473597d706e 4131
bogdanm 82:6473597d706e 4132 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4133 //! @brief Set the DTOEIEN field to a new value.
bogdanm 82:6473597d706e 4134 #define BW_SDHC_IRQSIGEN_DTOEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DTOEIEN) = (v))
bogdanm 82:6473597d706e 4135 #endif
bogdanm 82:6473597d706e 4136 //@}
bogdanm 82:6473597d706e 4137
bogdanm 82:6473597d706e 4138 /*!
bogdanm 82:6473597d706e 4139 * @name Register SDHC_IRQSIGEN, field DCEIEN[21] (RW)
bogdanm 82:6473597d706e 4140 *
bogdanm 82:6473597d706e 4141 * Values:
bogdanm 82:6473597d706e 4142 * - 0 - Masked
bogdanm 82:6473597d706e 4143 * - 1 - Enabled
bogdanm 82:6473597d706e 4144 */
bogdanm 82:6473597d706e 4145 //@{
bogdanm 82:6473597d706e 4146 #define BP_SDHC_IRQSIGEN_DCEIEN (21U) //!< Bit position for SDHC_IRQSIGEN_DCEIEN.
bogdanm 82:6473597d706e 4147 #define BM_SDHC_IRQSIGEN_DCEIEN (0x00200000U) //!< Bit mask for SDHC_IRQSIGEN_DCEIEN.
bogdanm 82:6473597d706e 4148 #define BS_SDHC_IRQSIGEN_DCEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DCEIEN.
bogdanm 82:6473597d706e 4149
bogdanm 82:6473597d706e 4150 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4151 //! @brief Read current value of the SDHC_IRQSIGEN_DCEIEN field.
bogdanm 82:6473597d706e 4152 #define BR_SDHC_IRQSIGEN_DCEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DCEIEN))
bogdanm 82:6473597d706e 4153 #endif
bogdanm 82:6473597d706e 4154
bogdanm 82:6473597d706e 4155 //! @brief Format value for bitfield SDHC_IRQSIGEN_DCEIEN.
bogdanm 82:6473597d706e 4156 #define BF_SDHC_IRQSIGEN_DCEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DCEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DCEIEN)
bogdanm 82:6473597d706e 4157
bogdanm 82:6473597d706e 4158 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4159 //! @brief Set the DCEIEN field to a new value.
bogdanm 82:6473597d706e 4160 #define BW_SDHC_IRQSIGEN_DCEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DCEIEN) = (v))
bogdanm 82:6473597d706e 4161 #endif
bogdanm 82:6473597d706e 4162 //@}
bogdanm 82:6473597d706e 4163
bogdanm 82:6473597d706e 4164 /*!
bogdanm 82:6473597d706e 4165 * @name Register SDHC_IRQSIGEN, field DEBEIEN[22] (RW)
bogdanm 82:6473597d706e 4166 *
bogdanm 82:6473597d706e 4167 * Values:
bogdanm 82:6473597d706e 4168 * - 0 - Masked
bogdanm 82:6473597d706e 4169 * - 1 - Enabled
bogdanm 82:6473597d706e 4170 */
bogdanm 82:6473597d706e 4171 //@{
bogdanm 82:6473597d706e 4172 #define BP_SDHC_IRQSIGEN_DEBEIEN (22U) //!< Bit position for SDHC_IRQSIGEN_DEBEIEN.
bogdanm 82:6473597d706e 4173 #define BM_SDHC_IRQSIGEN_DEBEIEN (0x00400000U) //!< Bit mask for SDHC_IRQSIGEN_DEBEIEN.
bogdanm 82:6473597d706e 4174 #define BS_SDHC_IRQSIGEN_DEBEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DEBEIEN.
bogdanm 82:6473597d706e 4175
bogdanm 82:6473597d706e 4176 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4177 //! @brief Read current value of the SDHC_IRQSIGEN_DEBEIEN field.
bogdanm 82:6473597d706e 4178 #define BR_SDHC_IRQSIGEN_DEBEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DEBEIEN))
bogdanm 82:6473597d706e 4179 #endif
bogdanm 82:6473597d706e 4180
bogdanm 82:6473597d706e 4181 //! @brief Format value for bitfield SDHC_IRQSIGEN_DEBEIEN.
bogdanm 82:6473597d706e 4182 #define BF_SDHC_IRQSIGEN_DEBEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DEBEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DEBEIEN)
bogdanm 82:6473597d706e 4183
bogdanm 82:6473597d706e 4184 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4185 //! @brief Set the DEBEIEN field to a new value.
bogdanm 82:6473597d706e 4186 #define BW_SDHC_IRQSIGEN_DEBEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DEBEIEN) = (v))
bogdanm 82:6473597d706e 4187 #endif
bogdanm 82:6473597d706e 4188 //@}
bogdanm 82:6473597d706e 4189
bogdanm 82:6473597d706e 4190 /*!
bogdanm 82:6473597d706e 4191 * @name Register SDHC_IRQSIGEN, field AC12EIEN[24] (RW)
bogdanm 82:6473597d706e 4192 *
bogdanm 82:6473597d706e 4193 * Values:
bogdanm 82:6473597d706e 4194 * - 0 - Masked
bogdanm 82:6473597d706e 4195 * - 1 - Enabled
bogdanm 82:6473597d706e 4196 */
bogdanm 82:6473597d706e 4197 //@{
bogdanm 82:6473597d706e 4198 #define BP_SDHC_IRQSIGEN_AC12EIEN (24U) //!< Bit position for SDHC_IRQSIGEN_AC12EIEN.
bogdanm 82:6473597d706e 4199 #define BM_SDHC_IRQSIGEN_AC12EIEN (0x01000000U) //!< Bit mask for SDHC_IRQSIGEN_AC12EIEN.
bogdanm 82:6473597d706e 4200 #define BS_SDHC_IRQSIGEN_AC12EIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_AC12EIEN.
bogdanm 82:6473597d706e 4201
bogdanm 82:6473597d706e 4202 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4203 //! @brief Read current value of the SDHC_IRQSIGEN_AC12EIEN field.
bogdanm 82:6473597d706e 4204 #define BR_SDHC_IRQSIGEN_AC12EIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_AC12EIEN))
bogdanm 82:6473597d706e 4205 #endif
bogdanm 82:6473597d706e 4206
bogdanm 82:6473597d706e 4207 //! @brief Format value for bitfield SDHC_IRQSIGEN_AC12EIEN.
bogdanm 82:6473597d706e 4208 #define BF_SDHC_IRQSIGEN_AC12EIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_AC12EIEN), uint32_t) & BM_SDHC_IRQSIGEN_AC12EIEN)
bogdanm 82:6473597d706e 4209
bogdanm 82:6473597d706e 4210 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4211 //! @brief Set the AC12EIEN field to a new value.
bogdanm 82:6473597d706e 4212 #define BW_SDHC_IRQSIGEN_AC12EIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_AC12EIEN) = (v))
bogdanm 82:6473597d706e 4213 #endif
bogdanm 82:6473597d706e 4214 //@}
bogdanm 82:6473597d706e 4215
bogdanm 82:6473597d706e 4216 /*!
bogdanm 82:6473597d706e 4217 * @name Register SDHC_IRQSIGEN, field DMAEIEN[28] (RW)
bogdanm 82:6473597d706e 4218 *
bogdanm 82:6473597d706e 4219 * Values:
bogdanm 82:6473597d706e 4220 * - 0 - Masked
bogdanm 82:6473597d706e 4221 * - 1 - Enabled
bogdanm 82:6473597d706e 4222 */
bogdanm 82:6473597d706e 4223 //@{
bogdanm 82:6473597d706e 4224 #define BP_SDHC_IRQSIGEN_DMAEIEN (28U) //!< Bit position for SDHC_IRQSIGEN_DMAEIEN.
bogdanm 82:6473597d706e 4225 #define BM_SDHC_IRQSIGEN_DMAEIEN (0x10000000U) //!< Bit mask for SDHC_IRQSIGEN_DMAEIEN.
bogdanm 82:6473597d706e 4226 #define BS_SDHC_IRQSIGEN_DMAEIEN (1U) //!< Bit field size in bits for SDHC_IRQSIGEN_DMAEIEN.
bogdanm 82:6473597d706e 4227
bogdanm 82:6473597d706e 4228 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4229 //! @brief Read current value of the SDHC_IRQSIGEN_DMAEIEN field.
bogdanm 82:6473597d706e 4230 #define BR_SDHC_IRQSIGEN_DMAEIEN (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DMAEIEN))
bogdanm 82:6473597d706e 4231 #endif
bogdanm 82:6473597d706e 4232
bogdanm 82:6473597d706e 4233 //! @brief Format value for bitfield SDHC_IRQSIGEN_DMAEIEN.
bogdanm 82:6473597d706e 4234 #define BF_SDHC_IRQSIGEN_DMAEIEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_IRQSIGEN_DMAEIEN), uint32_t) & BM_SDHC_IRQSIGEN_DMAEIEN)
bogdanm 82:6473597d706e 4235
bogdanm 82:6473597d706e 4236 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4237 //! @brief Set the DMAEIEN field to a new value.
bogdanm 82:6473597d706e 4238 #define BW_SDHC_IRQSIGEN_DMAEIEN(v) (BITBAND_ACCESS32(HW_SDHC_IRQSIGEN_ADDR, BP_SDHC_IRQSIGEN_DMAEIEN) = (v))
bogdanm 82:6473597d706e 4239 #endif
bogdanm 82:6473597d706e 4240 //@}
bogdanm 82:6473597d706e 4241
bogdanm 82:6473597d706e 4242 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4243 // HW_SDHC_AC12ERR - Auto CMD12 Error Status Register
bogdanm 82:6473597d706e 4244 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4245
bogdanm 82:6473597d706e 4246 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4247 /*!
bogdanm 82:6473597d706e 4248 * @brief HW_SDHC_AC12ERR - Auto CMD12 Error Status Register (RO)
bogdanm 82:6473597d706e 4249 *
bogdanm 82:6473597d706e 4250 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4251 *
bogdanm 82:6473597d706e 4252 * When the AC12ESEN bit in the Status register is set, the host driver shall
bogdanm 82:6473597d706e 4253 * check this register to identify what kind of error the Auto CMD12 indicated.
bogdanm 82:6473597d706e 4254 * This register is valid only when the Auto CMD12 Error status bit is set. The
bogdanm 82:6473597d706e 4255 * following table shows the relationship between the Auto CMGD12 CRC error and the
bogdanm 82:6473597d706e 4256 * Auto CMD12 command timeout error. Relationship between Command CRC Error and
bogdanm 82:6473597d706e 4257 * Command Timeout Error For Auto CMD12 Auto CMD12 CRC error Auto CMD12 timeout
bogdanm 82:6473597d706e 4258 * error Type of error 0 0 No error 0 1 Response timeout error 1 0 Response CRC
bogdanm 82:6473597d706e 4259 * error 1 1 CMD line conflict Changes in Auto CMD12 Error Status register can be
bogdanm 82:6473597d706e 4260 * classified in three scenarios: When the SDHC is going to issue an Auto CMD12: Set
bogdanm 82:6473597d706e 4261 * bit 0 to 1 if the Auto CMD12 can't be issued due to an error in the previous
bogdanm 82:6473597d706e 4262 * command. Set bit 0 to 0 if the auto CMD12 is issued. At the end bit of an auto
bogdanm 82:6473597d706e 4263 * CMD12 response: Check errors corresponding to bits 1-4. Set bits 1-4
bogdanm 82:6473597d706e 4264 * corresponding to detected errors. Clear bits 1-4 corresponding to detected errors.
bogdanm 82:6473597d706e 4265 * Before reading the Auto CMD12 error status bit 7: Set bit 7 to 1 if there is a
bogdanm 82:6473597d706e 4266 * command that can't be issued. Clear bit 7 if there is no command to issue. The
bogdanm 82:6473597d706e 4267 * timing for generating the auto CMD12 error and writing to the command register
bogdanm 82:6473597d706e 4268 * are asynchronous. After that, bit 7 shall be sampled when the driver is not
bogdanm 82:6473597d706e 4269 * writing to the command register. So it is suggested to read this register only
bogdanm 82:6473597d706e 4270 * when IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one
bogdanm 82:6473597d706e 4271 * of the error bits (0-4) is set to 1. The command not issued by auto CMD12
bogdanm 82:6473597d706e 4272 * error does not generate an interrupt.
bogdanm 82:6473597d706e 4273 */
bogdanm 82:6473597d706e 4274 typedef union _hw_sdhc_ac12err
bogdanm 82:6473597d706e 4275 {
bogdanm 82:6473597d706e 4276 uint32_t U;
bogdanm 82:6473597d706e 4277 struct _hw_sdhc_ac12err_bitfields
bogdanm 82:6473597d706e 4278 {
bogdanm 82:6473597d706e 4279 uint32_t AC12NE : 1; //!< [0] Auto CMD12 Not Executed
bogdanm 82:6473597d706e 4280 uint32_t AC12TOE : 1; //!< [1] Auto CMD12 Timeout Error
bogdanm 82:6473597d706e 4281 uint32_t AC12EBE : 1; //!< [2] Auto CMD12 End Bit Error
bogdanm 82:6473597d706e 4282 uint32_t AC12CE : 1; //!< [3] Auto CMD12 CRC Error
bogdanm 82:6473597d706e 4283 uint32_t AC12IE : 1; //!< [4] Auto CMD12 Index Error
bogdanm 82:6473597d706e 4284 uint32_t RESERVED0 : 2; //!< [6:5]
bogdanm 82:6473597d706e 4285 uint32_t CNIBAC12E : 1; //!< [7] Command Not Issued By Auto CMD12
bogdanm 82:6473597d706e 4286 //! Error
bogdanm 82:6473597d706e 4287 uint32_t RESERVED1 : 24; //!< [31:8]
bogdanm 82:6473597d706e 4288 } B;
bogdanm 82:6473597d706e 4289 } hw_sdhc_ac12err_t;
bogdanm 82:6473597d706e 4290 #endif
bogdanm 82:6473597d706e 4291
bogdanm 82:6473597d706e 4292 /*!
bogdanm 82:6473597d706e 4293 * @name Constants and macros for entire SDHC_AC12ERR register
bogdanm 82:6473597d706e 4294 */
bogdanm 82:6473597d706e 4295 //@{
bogdanm 82:6473597d706e 4296 #define HW_SDHC_AC12ERR_ADDR (REGS_SDHC_BASE + 0x3CU)
bogdanm 82:6473597d706e 4297
bogdanm 82:6473597d706e 4298 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4299 #define HW_SDHC_AC12ERR (*(__I hw_sdhc_ac12err_t *) HW_SDHC_AC12ERR_ADDR)
bogdanm 82:6473597d706e 4300 #define HW_SDHC_AC12ERR_RD() (HW_SDHC_AC12ERR.U)
bogdanm 82:6473597d706e 4301 #endif
bogdanm 82:6473597d706e 4302 //@}
bogdanm 82:6473597d706e 4303
bogdanm 82:6473597d706e 4304 /*
bogdanm 82:6473597d706e 4305 * Constants & macros for individual SDHC_AC12ERR bitfields
bogdanm 82:6473597d706e 4306 */
bogdanm 82:6473597d706e 4307
bogdanm 82:6473597d706e 4308 /*!
bogdanm 82:6473597d706e 4309 * @name Register SDHC_AC12ERR, field AC12NE[0] (RO)
bogdanm 82:6473597d706e 4310 *
bogdanm 82:6473597d706e 4311 * If memory multiple block data transfer is not started, due to a command
bogdanm 82:6473597d706e 4312 * error, this bit is not set because it is not necessary to issue an auto CMD12.
bogdanm 82:6473597d706e 4313 * Setting this bit to 1 means the SDHC cannot issue the auto CMD12 to stop a memory
bogdanm 82:6473597d706e 4314 * multiple block data transfer due to some error. If this bit is set to 1, other
bogdanm 82:6473597d706e 4315 * error status bits (1-4) have no meaning.
bogdanm 82:6473597d706e 4316 *
bogdanm 82:6473597d706e 4317 * Values:
bogdanm 82:6473597d706e 4318 * - 0 - Executed.
bogdanm 82:6473597d706e 4319 * - 1 - Not executed.
bogdanm 82:6473597d706e 4320 */
bogdanm 82:6473597d706e 4321 //@{
bogdanm 82:6473597d706e 4322 #define BP_SDHC_AC12ERR_AC12NE (0U) //!< Bit position for SDHC_AC12ERR_AC12NE.
bogdanm 82:6473597d706e 4323 #define BM_SDHC_AC12ERR_AC12NE (0x00000001U) //!< Bit mask for SDHC_AC12ERR_AC12NE.
bogdanm 82:6473597d706e 4324 #define BS_SDHC_AC12ERR_AC12NE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12NE.
bogdanm 82:6473597d706e 4325
bogdanm 82:6473597d706e 4326 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4327 //! @brief Read current value of the SDHC_AC12ERR_AC12NE field.
bogdanm 82:6473597d706e 4328 #define BR_SDHC_AC12ERR_AC12NE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12NE))
bogdanm 82:6473597d706e 4329 #endif
bogdanm 82:6473597d706e 4330 //@}
bogdanm 82:6473597d706e 4331
bogdanm 82:6473597d706e 4332 /*!
bogdanm 82:6473597d706e 4333 * @name Register SDHC_AC12ERR, field AC12TOE[1] (RO)
bogdanm 82:6473597d706e 4334 *
bogdanm 82:6473597d706e 4335 * Occurs if no response is returned within 64 SDCLK cycles from the end bit of
bogdanm 82:6473597d706e 4336 * the command. If this bit is set to 1, the other error status bits (2-4) have
bogdanm 82:6473597d706e 4337 * no meaning.
bogdanm 82:6473597d706e 4338 *
bogdanm 82:6473597d706e 4339 * Values:
bogdanm 82:6473597d706e 4340 * - 0 - No error.
bogdanm 82:6473597d706e 4341 * - 1 - Time out.
bogdanm 82:6473597d706e 4342 */
bogdanm 82:6473597d706e 4343 //@{
bogdanm 82:6473597d706e 4344 #define BP_SDHC_AC12ERR_AC12TOE (1U) //!< Bit position for SDHC_AC12ERR_AC12TOE.
bogdanm 82:6473597d706e 4345 #define BM_SDHC_AC12ERR_AC12TOE (0x00000002U) //!< Bit mask for SDHC_AC12ERR_AC12TOE.
bogdanm 82:6473597d706e 4346 #define BS_SDHC_AC12ERR_AC12TOE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12TOE.
bogdanm 82:6473597d706e 4347
bogdanm 82:6473597d706e 4348 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4349 //! @brief Read current value of the SDHC_AC12ERR_AC12TOE field.
bogdanm 82:6473597d706e 4350 #define BR_SDHC_AC12ERR_AC12TOE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12TOE))
bogdanm 82:6473597d706e 4351 #endif
bogdanm 82:6473597d706e 4352 //@}
bogdanm 82:6473597d706e 4353
bogdanm 82:6473597d706e 4354 /*!
bogdanm 82:6473597d706e 4355 * @name Register SDHC_AC12ERR, field AC12EBE[2] (RO)
bogdanm 82:6473597d706e 4356 *
bogdanm 82:6473597d706e 4357 * Occurs when detecting that the end bit of command response is 0 which must be
bogdanm 82:6473597d706e 4358 * 1.
bogdanm 82:6473597d706e 4359 *
bogdanm 82:6473597d706e 4360 * Values:
bogdanm 82:6473597d706e 4361 * - 0 - No error.
bogdanm 82:6473597d706e 4362 * - 1 - End bit error generated.
bogdanm 82:6473597d706e 4363 */
bogdanm 82:6473597d706e 4364 //@{
bogdanm 82:6473597d706e 4365 #define BP_SDHC_AC12ERR_AC12EBE (2U) //!< Bit position for SDHC_AC12ERR_AC12EBE.
bogdanm 82:6473597d706e 4366 #define BM_SDHC_AC12ERR_AC12EBE (0x00000004U) //!< Bit mask for SDHC_AC12ERR_AC12EBE.
bogdanm 82:6473597d706e 4367 #define BS_SDHC_AC12ERR_AC12EBE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12EBE.
bogdanm 82:6473597d706e 4368
bogdanm 82:6473597d706e 4369 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4370 //! @brief Read current value of the SDHC_AC12ERR_AC12EBE field.
bogdanm 82:6473597d706e 4371 #define BR_SDHC_AC12ERR_AC12EBE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12EBE))
bogdanm 82:6473597d706e 4372 #endif
bogdanm 82:6473597d706e 4373 //@}
bogdanm 82:6473597d706e 4374
bogdanm 82:6473597d706e 4375 /*!
bogdanm 82:6473597d706e 4376 * @name Register SDHC_AC12ERR, field AC12CE[3] (RO)
bogdanm 82:6473597d706e 4377 *
bogdanm 82:6473597d706e 4378 * Occurs when detecting a CRC error in the command response.
bogdanm 82:6473597d706e 4379 *
bogdanm 82:6473597d706e 4380 * Values:
bogdanm 82:6473597d706e 4381 * - 0 - No CRC error.
bogdanm 82:6473597d706e 4382 * - 1 - CRC error met in Auto CMD12 response.
bogdanm 82:6473597d706e 4383 */
bogdanm 82:6473597d706e 4384 //@{
bogdanm 82:6473597d706e 4385 #define BP_SDHC_AC12ERR_AC12CE (3U) //!< Bit position for SDHC_AC12ERR_AC12CE.
bogdanm 82:6473597d706e 4386 #define BM_SDHC_AC12ERR_AC12CE (0x00000008U) //!< Bit mask for SDHC_AC12ERR_AC12CE.
bogdanm 82:6473597d706e 4387 #define BS_SDHC_AC12ERR_AC12CE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12CE.
bogdanm 82:6473597d706e 4388
bogdanm 82:6473597d706e 4389 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4390 //! @brief Read current value of the SDHC_AC12ERR_AC12CE field.
bogdanm 82:6473597d706e 4391 #define BR_SDHC_AC12ERR_AC12CE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12CE))
bogdanm 82:6473597d706e 4392 #endif
bogdanm 82:6473597d706e 4393 //@}
bogdanm 82:6473597d706e 4394
bogdanm 82:6473597d706e 4395 /*!
bogdanm 82:6473597d706e 4396 * @name Register SDHC_AC12ERR, field AC12IE[4] (RO)
bogdanm 82:6473597d706e 4397 *
bogdanm 82:6473597d706e 4398 * Occurs if the command index error occurs in response to a command.
bogdanm 82:6473597d706e 4399 *
bogdanm 82:6473597d706e 4400 * Values:
bogdanm 82:6473597d706e 4401 * - 0 - No error.
bogdanm 82:6473597d706e 4402 * - 1 - Error, the CMD index in response is not CMD12.
bogdanm 82:6473597d706e 4403 */
bogdanm 82:6473597d706e 4404 //@{
bogdanm 82:6473597d706e 4405 #define BP_SDHC_AC12ERR_AC12IE (4U) //!< Bit position for SDHC_AC12ERR_AC12IE.
bogdanm 82:6473597d706e 4406 #define BM_SDHC_AC12ERR_AC12IE (0x00000010U) //!< Bit mask for SDHC_AC12ERR_AC12IE.
bogdanm 82:6473597d706e 4407 #define BS_SDHC_AC12ERR_AC12IE (1U) //!< Bit field size in bits for SDHC_AC12ERR_AC12IE.
bogdanm 82:6473597d706e 4408
bogdanm 82:6473597d706e 4409 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4410 //! @brief Read current value of the SDHC_AC12ERR_AC12IE field.
bogdanm 82:6473597d706e 4411 #define BR_SDHC_AC12ERR_AC12IE (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_AC12IE))
bogdanm 82:6473597d706e 4412 #endif
bogdanm 82:6473597d706e 4413 //@}
bogdanm 82:6473597d706e 4414
bogdanm 82:6473597d706e 4415 /*!
bogdanm 82:6473597d706e 4416 * @name Register SDHC_AC12ERR, field CNIBAC12E[7] (RO)
bogdanm 82:6473597d706e 4417 *
bogdanm 82:6473597d706e 4418 * Setting this bit to 1 means CMD_wo_DAT is not executed due to an auto CMD12
bogdanm 82:6473597d706e 4419 * error (D04-D01) in this register.
bogdanm 82:6473597d706e 4420 *
bogdanm 82:6473597d706e 4421 * Values:
bogdanm 82:6473597d706e 4422 * - 0 - No error.
bogdanm 82:6473597d706e 4423 * - 1 - Not issued.
bogdanm 82:6473597d706e 4424 */
bogdanm 82:6473597d706e 4425 //@{
bogdanm 82:6473597d706e 4426 #define BP_SDHC_AC12ERR_CNIBAC12E (7U) //!< Bit position for SDHC_AC12ERR_CNIBAC12E.
bogdanm 82:6473597d706e 4427 #define BM_SDHC_AC12ERR_CNIBAC12E (0x00000080U) //!< Bit mask for SDHC_AC12ERR_CNIBAC12E.
bogdanm 82:6473597d706e 4428 #define BS_SDHC_AC12ERR_CNIBAC12E (1U) //!< Bit field size in bits for SDHC_AC12ERR_CNIBAC12E.
bogdanm 82:6473597d706e 4429
bogdanm 82:6473597d706e 4430 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4431 //! @brief Read current value of the SDHC_AC12ERR_CNIBAC12E field.
bogdanm 82:6473597d706e 4432 #define BR_SDHC_AC12ERR_CNIBAC12E (BITBAND_ACCESS32(HW_SDHC_AC12ERR_ADDR, BP_SDHC_AC12ERR_CNIBAC12E))
bogdanm 82:6473597d706e 4433 #endif
bogdanm 82:6473597d706e 4434 //@}
bogdanm 82:6473597d706e 4435
bogdanm 82:6473597d706e 4436 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4437 // HW_SDHC_HTCAPBLT - Host Controller Capabilities
bogdanm 82:6473597d706e 4438 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4439
bogdanm 82:6473597d706e 4440 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4441 /*!
bogdanm 82:6473597d706e 4442 * @brief HW_SDHC_HTCAPBLT - Host Controller Capabilities (RO)
bogdanm 82:6473597d706e 4443 *
bogdanm 82:6473597d706e 4444 * Reset value: 0x07F30000U
bogdanm 82:6473597d706e 4445 *
bogdanm 82:6473597d706e 4446 * This register provides the host driver with information specific to the SDHC
bogdanm 82:6473597d706e 4447 * implementation. The value in this register is the power-on-reset value, and
bogdanm 82:6473597d706e 4448 * does not change with a software reset. Any write to this register is ignored.
bogdanm 82:6473597d706e 4449 */
bogdanm 82:6473597d706e 4450 typedef union _hw_sdhc_htcapblt
bogdanm 82:6473597d706e 4451 {
bogdanm 82:6473597d706e 4452 uint32_t U;
bogdanm 82:6473597d706e 4453 struct _hw_sdhc_htcapblt_bitfields
bogdanm 82:6473597d706e 4454 {
bogdanm 82:6473597d706e 4455 uint32_t RESERVED0 : 16; //!< [15:0]
bogdanm 82:6473597d706e 4456 uint32_t MBL : 3; //!< [18:16] Max Block Length
bogdanm 82:6473597d706e 4457 uint32_t RESERVED1 : 1; //!< [19]
bogdanm 82:6473597d706e 4458 uint32_t ADMAS : 1; //!< [20] ADMA Support
bogdanm 82:6473597d706e 4459 uint32_t HSS : 1; //!< [21] High Speed Support
bogdanm 82:6473597d706e 4460 uint32_t DMAS : 1; //!< [22] DMA Support
bogdanm 82:6473597d706e 4461 uint32_t SRS : 1; //!< [23] Suspend/Resume Support
bogdanm 82:6473597d706e 4462 uint32_t VS33 : 1; //!< [24] Voltage Support 3.3 V
bogdanm 82:6473597d706e 4463 uint32_t RESERVED2 : 7; //!< [31:25]
bogdanm 82:6473597d706e 4464 } B;
bogdanm 82:6473597d706e 4465 } hw_sdhc_htcapblt_t;
bogdanm 82:6473597d706e 4466 #endif
bogdanm 82:6473597d706e 4467
bogdanm 82:6473597d706e 4468 /*!
bogdanm 82:6473597d706e 4469 * @name Constants and macros for entire SDHC_HTCAPBLT register
bogdanm 82:6473597d706e 4470 */
bogdanm 82:6473597d706e 4471 //@{
bogdanm 82:6473597d706e 4472 #define HW_SDHC_HTCAPBLT_ADDR (REGS_SDHC_BASE + 0x40U)
bogdanm 82:6473597d706e 4473
bogdanm 82:6473597d706e 4474 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4475 #define HW_SDHC_HTCAPBLT (*(__I hw_sdhc_htcapblt_t *) HW_SDHC_HTCAPBLT_ADDR)
bogdanm 82:6473597d706e 4476 #define HW_SDHC_HTCAPBLT_RD() (HW_SDHC_HTCAPBLT.U)
bogdanm 82:6473597d706e 4477 #endif
bogdanm 82:6473597d706e 4478 //@}
bogdanm 82:6473597d706e 4479
bogdanm 82:6473597d706e 4480 /*
bogdanm 82:6473597d706e 4481 * Constants & macros for individual SDHC_HTCAPBLT bitfields
bogdanm 82:6473597d706e 4482 */
bogdanm 82:6473597d706e 4483
bogdanm 82:6473597d706e 4484 /*!
bogdanm 82:6473597d706e 4485 * @name Register SDHC_HTCAPBLT, field MBL[18:16] (RO)
bogdanm 82:6473597d706e 4486 *
bogdanm 82:6473597d706e 4487 * This value indicates the maximum block size that the host driver can read and
bogdanm 82:6473597d706e 4488 * write to the buffer in the SDHC. The buffer shall transfer block size without
bogdanm 82:6473597d706e 4489 * wait cycles.
bogdanm 82:6473597d706e 4490 *
bogdanm 82:6473597d706e 4491 * Values:
bogdanm 82:6473597d706e 4492 * - 000 - 512 bytes
bogdanm 82:6473597d706e 4493 * - 001 - 1024 bytes
bogdanm 82:6473597d706e 4494 * - 010 - 2048 bytes
bogdanm 82:6473597d706e 4495 * - 011 - 4096 bytes
bogdanm 82:6473597d706e 4496 */
bogdanm 82:6473597d706e 4497 //@{
bogdanm 82:6473597d706e 4498 #define BP_SDHC_HTCAPBLT_MBL (16U) //!< Bit position for SDHC_HTCAPBLT_MBL.
bogdanm 82:6473597d706e 4499 #define BM_SDHC_HTCAPBLT_MBL (0x00070000U) //!< Bit mask for SDHC_HTCAPBLT_MBL.
bogdanm 82:6473597d706e 4500 #define BS_SDHC_HTCAPBLT_MBL (3U) //!< Bit field size in bits for SDHC_HTCAPBLT_MBL.
bogdanm 82:6473597d706e 4501
bogdanm 82:6473597d706e 4502 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4503 //! @brief Read current value of the SDHC_HTCAPBLT_MBL field.
bogdanm 82:6473597d706e 4504 #define BR_SDHC_HTCAPBLT_MBL (HW_SDHC_HTCAPBLT.B.MBL)
bogdanm 82:6473597d706e 4505 #endif
bogdanm 82:6473597d706e 4506 //@}
bogdanm 82:6473597d706e 4507
bogdanm 82:6473597d706e 4508 /*!
bogdanm 82:6473597d706e 4509 * @name Register SDHC_HTCAPBLT, field ADMAS[20] (RO)
bogdanm 82:6473597d706e 4510 *
bogdanm 82:6473597d706e 4511 * This bit indicates whether the SDHC supports the ADMA feature.
bogdanm 82:6473597d706e 4512 *
bogdanm 82:6473597d706e 4513 * Values:
bogdanm 82:6473597d706e 4514 * - 0 - Advanced DMA not supported.
bogdanm 82:6473597d706e 4515 * - 1 - Advanced DMA supported.
bogdanm 82:6473597d706e 4516 */
bogdanm 82:6473597d706e 4517 //@{
bogdanm 82:6473597d706e 4518 #define BP_SDHC_HTCAPBLT_ADMAS (20U) //!< Bit position for SDHC_HTCAPBLT_ADMAS.
bogdanm 82:6473597d706e 4519 #define BM_SDHC_HTCAPBLT_ADMAS (0x00100000U) //!< Bit mask for SDHC_HTCAPBLT_ADMAS.
bogdanm 82:6473597d706e 4520 #define BS_SDHC_HTCAPBLT_ADMAS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_ADMAS.
bogdanm 82:6473597d706e 4521
bogdanm 82:6473597d706e 4522 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4523 //! @brief Read current value of the SDHC_HTCAPBLT_ADMAS field.
bogdanm 82:6473597d706e 4524 #define BR_SDHC_HTCAPBLT_ADMAS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_ADMAS))
bogdanm 82:6473597d706e 4525 #endif
bogdanm 82:6473597d706e 4526 //@}
bogdanm 82:6473597d706e 4527
bogdanm 82:6473597d706e 4528 /*!
bogdanm 82:6473597d706e 4529 * @name Register SDHC_HTCAPBLT, field HSS[21] (RO)
bogdanm 82:6473597d706e 4530 *
bogdanm 82:6473597d706e 4531 * This bit indicates whether the SDHC supports high speed mode and the host
bogdanm 82:6473597d706e 4532 * system can supply a SD Clock frequency from 25 MHz to 50 MHz.
bogdanm 82:6473597d706e 4533 *
bogdanm 82:6473597d706e 4534 * Values:
bogdanm 82:6473597d706e 4535 * - 0 - High speed not supported.
bogdanm 82:6473597d706e 4536 * - 1 - High speed supported.
bogdanm 82:6473597d706e 4537 */
bogdanm 82:6473597d706e 4538 //@{
bogdanm 82:6473597d706e 4539 #define BP_SDHC_HTCAPBLT_HSS (21U) //!< Bit position for SDHC_HTCAPBLT_HSS.
bogdanm 82:6473597d706e 4540 #define BM_SDHC_HTCAPBLT_HSS (0x00200000U) //!< Bit mask for SDHC_HTCAPBLT_HSS.
bogdanm 82:6473597d706e 4541 #define BS_SDHC_HTCAPBLT_HSS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_HSS.
bogdanm 82:6473597d706e 4542
bogdanm 82:6473597d706e 4543 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4544 //! @brief Read current value of the SDHC_HTCAPBLT_HSS field.
bogdanm 82:6473597d706e 4545 #define BR_SDHC_HTCAPBLT_HSS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_HSS))
bogdanm 82:6473597d706e 4546 #endif
bogdanm 82:6473597d706e 4547 //@}
bogdanm 82:6473597d706e 4548
bogdanm 82:6473597d706e 4549 /*!
bogdanm 82:6473597d706e 4550 * @name Register SDHC_HTCAPBLT, field DMAS[22] (RO)
bogdanm 82:6473597d706e 4551 *
bogdanm 82:6473597d706e 4552 * This bit indicates whether the SDHC is capable of using the internal DMA to
bogdanm 82:6473597d706e 4553 * transfer data between system memory and the data buffer directly.
bogdanm 82:6473597d706e 4554 *
bogdanm 82:6473597d706e 4555 * Values:
bogdanm 82:6473597d706e 4556 * - 0 - DMA not supported.
bogdanm 82:6473597d706e 4557 * - 1 - DMA supported.
bogdanm 82:6473597d706e 4558 */
bogdanm 82:6473597d706e 4559 //@{
bogdanm 82:6473597d706e 4560 #define BP_SDHC_HTCAPBLT_DMAS (22U) //!< Bit position for SDHC_HTCAPBLT_DMAS.
bogdanm 82:6473597d706e 4561 #define BM_SDHC_HTCAPBLT_DMAS (0x00400000U) //!< Bit mask for SDHC_HTCAPBLT_DMAS.
bogdanm 82:6473597d706e 4562 #define BS_SDHC_HTCAPBLT_DMAS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_DMAS.
bogdanm 82:6473597d706e 4563
bogdanm 82:6473597d706e 4564 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4565 //! @brief Read current value of the SDHC_HTCAPBLT_DMAS field.
bogdanm 82:6473597d706e 4566 #define BR_SDHC_HTCAPBLT_DMAS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_DMAS))
bogdanm 82:6473597d706e 4567 #endif
bogdanm 82:6473597d706e 4568 //@}
bogdanm 82:6473597d706e 4569
bogdanm 82:6473597d706e 4570 /*!
bogdanm 82:6473597d706e 4571 * @name Register SDHC_HTCAPBLT, field SRS[23] (RO)
bogdanm 82:6473597d706e 4572 *
bogdanm 82:6473597d706e 4573 * This bit indicates whether the SDHC supports suspend / resume functionality.
bogdanm 82:6473597d706e 4574 * If this bit is 0, the suspend and resume mechanism, as well as the read Wwait,
bogdanm 82:6473597d706e 4575 * are not supported, and the host driver shall not issue either suspend or
bogdanm 82:6473597d706e 4576 * resume commands.
bogdanm 82:6473597d706e 4577 *
bogdanm 82:6473597d706e 4578 * Values:
bogdanm 82:6473597d706e 4579 * - 0 - Not supported.
bogdanm 82:6473597d706e 4580 * - 1 - Supported.
bogdanm 82:6473597d706e 4581 */
bogdanm 82:6473597d706e 4582 //@{
bogdanm 82:6473597d706e 4583 #define BP_SDHC_HTCAPBLT_SRS (23U) //!< Bit position for SDHC_HTCAPBLT_SRS.
bogdanm 82:6473597d706e 4584 #define BM_SDHC_HTCAPBLT_SRS (0x00800000U) //!< Bit mask for SDHC_HTCAPBLT_SRS.
bogdanm 82:6473597d706e 4585 #define BS_SDHC_HTCAPBLT_SRS (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_SRS.
bogdanm 82:6473597d706e 4586
bogdanm 82:6473597d706e 4587 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4588 //! @brief Read current value of the SDHC_HTCAPBLT_SRS field.
bogdanm 82:6473597d706e 4589 #define BR_SDHC_HTCAPBLT_SRS (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_SRS))
bogdanm 82:6473597d706e 4590 #endif
bogdanm 82:6473597d706e 4591 //@}
bogdanm 82:6473597d706e 4592
bogdanm 82:6473597d706e 4593 /*!
bogdanm 82:6473597d706e 4594 * @name Register SDHC_HTCAPBLT, field VS33[24] (RO)
bogdanm 82:6473597d706e 4595 *
bogdanm 82:6473597d706e 4596 * This bit shall depend on the host system ability.
bogdanm 82:6473597d706e 4597 *
bogdanm 82:6473597d706e 4598 * Values:
bogdanm 82:6473597d706e 4599 * - 0 - 3.3 V not supported.
bogdanm 82:6473597d706e 4600 * - 1 - 3.3 V supported.
bogdanm 82:6473597d706e 4601 */
bogdanm 82:6473597d706e 4602 //@{
bogdanm 82:6473597d706e 4603 #define BP_SDHC_HTCAPBLT_VS33 (24U) //!< Bit position for SDHC_HTCAPBLT_VS33.
bogdanm 82:6473597d706e 4604 #define BM_SDHC_HTCAPBLT_VS33 (0x01000000U) //!< Bit mask for SDHC_HTCAPBLT_VS33.
bogdanm 82:6473597d706e 4605 #define BS_SDHC_HTCAPBLT_VS33 (1U) //!< Bit field size in bits for SDHC_HTCAPBLT_VS33.
bogdanm 82:6473597d706e 4606
bogdanm 82:6473597d706e 4607 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4608 //! @brief Read current value of the SDHC_HTCAPBLT_VS33 field.
bogdanm 82:6473597d706e 4609 #define BR_SDHC_HTCAPBLT_VS33 (BITBAND_ACCESS32(HW_SDHC_HTCAPBLT_ADDR, BP_SDHC_HTCAPBLT_VS33))
bogdanm 82:6473597d706e 4610 #endif
bogdanm 82:6473597d706e 4611 //@}
bogdanm 82:6473597d706e 4612
bogdanm 82:6473597d706e 4613 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4614 // HW_SDHC_WML - Watermark Level Register
bogdanm 82:6473597d706e 4615 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4616
bogdanm 82:6473597d706e 4617 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4618 /*!
bogdanm 82:6473597d706e 4619 * @brief HW_SDHC_WML - Watermark Level Register (RW)
bogdanm 82:6473597d706e 4620 *
bogdanm 82:6473597d706e 4621 * Reset value: 0x00100010U
bogdanm 82:6473597d706e 4622 *
bogdanm 82:6473597d706e 4623 * Both write and read watermark levels (FIFO threshold) are configurable. There
bogdanm 82:6473597d706e 4624 * value can range from 1 to 128 words. Both write and read burst lengths are
bogdanm 82:6473597d706e 4625 * also configurable. There value can range from 1 to 31 words.
bogdanm 82:6473597d706e 4626 */
bogdanm 82:6473597d706e 4627 typedef union _hw_sdhc_wml
bogdanm 82:6473597d706e 4628 {
bogdanm 82:6473597d706e 4629 uint32_t U;
bogdanm 82:6473597d706e 4630 struct _hw_sdhc_wml_bitfields
bogdanm 82:6473597d706e 4631 {
bogdanm 82:6473597d706e 4632 uint32_t RDWML : 8; //!< [7:0] Read Watermark Level
bogdanm 82:6473597d706e 4633 uint32_t RESERVED0 : 8; //!< [15:8]
bogdanm 82:6473597d706e 4634 uint32_t WRWML : 8; //!< [23:16] Write Watermark Level
bogdanm 82:6473597d706e 4635 uint32_t RESERVED1 : 8; //!< [31:24]
bogdanm 82:6473597d706e 4636 } B;
bogdanm 82:6473597d706e 4637 } hw_sdhc_wml_t;
bogdanm 82:6473597d706e 4638 #endif
bogdanm 82:6473597d706e 4639
bogdanm 82:6473597d706e 4640 /*!
bogdanm 82:6473597d706e 4641 * @name Constants and macros for entire SDHC_WML register
bogdanm 82:6473597d706e 4642 */
bogdanm 82:6473597d706e 4643 //@{
bogdanm 82:6473597d706e 4644 #define HW_SDHC_WML_ADDR (REGS_SDHC_BASE + 0x44U)
bogdanm 82:6473597d706e 4645
bogdanm 82:6473597d706e 4646 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4647 #define HW_SDHC_WML (*(__IO hw_sdhc_wml_t *) HW_SDHC_WML_ADDR)
bogdanm 82:6473597d706e 4648 #define HW_SDHC_WML_RD() (HW_SDHC_WML.U)
bogdanm 82:6473597d706e 4649 #define HW_SDHC_WML_WR(v) (HW_SDHC_WML.U = (v))
bogdanm 82:6473597d706e 4650 #define HW_SDHC_WML_SET(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() | (v)))
bogdanm 82:6473597d706e 4651 #define HW_SDHC_WML_CLR(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() & ~(v)))
bogdanm 82:6473597d706e 4652 #define HW_SDHC_WML_TOG(v) (HW_SDHC_WML_WR(HW_SDHC_WML_RD() ^ (v)))
bogdanm 82:6473597d706e 4653 #endif
bogdanm 82:6473597d706e 4654 //@}
bogdanm 82:6473597d706e 4655
bogdanm 82:6473597d706e 4656 /*
bogdanm 82:6473597d706e 4657 * Constants & macros for individual SDHC_WML bitfields
bogdanm 82:6473597d706e 4658 */
bogdanm 82:6473597d706e 4659
bogdanm 82:6473597d706e 4660 /*!
bogdanm 82:6473597d706e 4661 * @name Register SDHC_WML, field RDWML[7:0] (RW)
bogdanm 82:6473597d706e 4662 *
bogdanm 82:6473597d706e 4663 * The number of words used as the watermark level (FIFO threshold) in a DMA
bogdanm 82:6473597d706e 4664 * read operation. Also the number of words as a sequence of read bursts in
bogdanm 82:6473597d706e 4665 * back-to-back mode. The maximum legal value for the read water mark level is 128.
bogdanm 82:6473597d706e 4666 */
bogdanm 82:6473597d706e 4667 //@{
bogdanm 82:6473597d706e 4668 #define BP_SDHC_WML_RDWML (0U) //!< Bit position for SDHC_WML_RDWML.
bogdanm 82:6473597d706e 4669 #define BM_SDHC_WML_RDWML (0x000000FFU) //!< Bit mask for SDHC_WML_RDWML.
bogdanm 82:6473597d706e 4670 #define BS_SDHC_WML_RDWML (8U) //!< Bit field size in bits for SDHC_WML_RDWML.
bogdanm 82:6473597d706e 4671
bogdanm 82:6473597d706e 4672 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4673 //! @brief Read current value of the SDHC_WML_RDWML field.
bogdanm 82:6473597d706e 4674 #define BR_SDHC_WML_RDWML (HW_SDHC_WML.B.RDWML)
bogdanm 82:6473597d706e 4675 #endif
bogdanm 82:6473597d706e 4676
bogdanm 82:6473597d706e 4677 //! @brief Format value for bitfield SDHC_WML_RDWML.
bogdanm 82:6473597d706e 4678 #define BF_SDHC_WML_RDWML(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_WML_RDWML), uint32_t) & BM_SDHC_WML_RDWML)
bogdanm 82:6473597d706e 4679
bogdanm 82:6473597d706e 4680 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4681 //! @brief Set the RDWML field to a new value.
bogdanm 82:6473597d706e 4682 #define BW_SDHC_WML_RDWML(v) (HW_SDHC_WML_WR((HW_SDHC_WML_RD() & ~BM_SDHC_WML_RDWML) | BF_SDHC_WML_RDWML(v)))
bogdanm 82:6473597d706e 4683 #endif
bogdanm 82:6473597d706e 4684 //@}
bogdanm 82:6473597d706e 4685
bogdanm 82:6473597d706e 4686 /*!
bogdanm 82:6473597d706e 4687 * @name Register SDHC_WML, field WRWML[23:16] (RW)
bogdanm 82:6473597d706e 4688 *
bogdanm 82:6473597d706e 4689 * The number of words used as the watermark level (FIFO threshold) in a DMA
bogdanm 82:6473597d706e 4690 * write operation. Also the number of words as a sequence of write bursts in
bogdanm 82:6473597d706e 4691 * back-to-back mode. The maximum legal value for the write watermark level is 128.
bogdanm 82:6473597d706e 4692 */
bogdanm 82:6473597d706e 4693 //@{
bogdanm 82:6473597d706e 4694 #define BP_SDHC_WML_WRWML (16U) //!< Bit position for SDHC_WML_WRWML.
bogdanm 82:6473597d706e 4695 #define BM_SDHC_WML_WRWML (0x00FF0000U) //!< Bit mask for SDHC_WML_WRWML.
bogdanm 82:6473597d706e 4696 #define BS_SDHC_WML_WRWML (8U) //!< Bit field size in bits for SDHC_WML_WRWML.
bogdanm 82:6473597d706e 4697
bogdanm 82:6473597d706e 4698 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4699 //! @brief Read current value of the SDHC_WML_WRWML field.
bogdanm 82:6473597d706e 4700 #define BR_SDHC_WML_WRWML (HW_SDHC_WML.B.WRWML)
bogdanm 82:6473597d706e 4701 #endif
bogdanm 82:6473597d706e 4702
bogdanm 82:6473597d706e 4703 //! @brief Format value for bitfield SDHC_WML_WRWML.
bogdanm 82:6473597d706e 4704 #define BF_SDHC_WML_WRWML(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_WML_WRWML), uint32_t) & BM_SDHC_WML_WRWML)
bogdanm 82:6473597d706e 4705
bogdanm 82:6473597d706e 4706 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4707 //! @brief Set the WRWML field to a new value.
bogdanm 82:6473597d706e 4708 #define BW_SDHC_WML_WRWML(v) (HW_SDHC_WML_WR((HW_SDHC_WML_RD() & ~BM_SDHC_WML_WRWML) | BF_SDHC_WML_WRWML(v)))
bogdanm 82:6473597d706e 4709 #endif
bogdanm 82:6473597d706e 4710 //@}
bogdanm 82:6473597d706e 4711
bogdanm 82:6473597d706e 4712 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4713 // HW_SDHC_FEVT - Force Event register
bogdanm 82:6473597d706e 4714 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 4715
bogdanm 82:6473597d706e 4716 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4717 /*!
bogdanm 82:6473597d706e 4718 * @brief HW_SDHC_FEVT - Force Event register (WO)
bogdanm 82:6473597d706e 4719 *
bogdanm 82:6473597d706e 4720 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 4721 *
bogdanm 82:6473597d706e 4722 * The Force Event (FEVT) register is not a physically implemented register.
bogdanm 82:6473597d706e 4723 * Rather, it is an address at which the Interrupt Status register can be written if
bogdanm 82:6473597d706e 4724 * the corresponding bit of the Interrupt Status Enable register is set. This
bogdanm 82:6473597d706e 4725 * register is a write only register and writing 0 to it has no effect. Writing 1
bogdanm 82:6473597d706e 4726 * to this register actually sets the corresponding bit of Interrupt Status
bogdanm 82:6473597d706e 4727 * register. A read from this register always results in 0's. To change the
bogdanm 82:6473597d706e 4728 * corresponding status bits in the interrupt status register, make sure to set
bogdanm 82:6473597d706e 4729 * SYSCTL[IPGEN] so that bus clock is always active. Forcing a card interrupt will generate a
bogdanm 82:6473597d706e 4730 * short pulse on the DAT[1] line, and the driver may treat this interrupt as a
bogdanm 82:6473597d706e 4731 * normal interrupt. The interrupt service routine may skip polling the card
bogdanm 82:6473597d706e 4732 * interrupt factor as the interrupt is selfcleared.
bogdanm 82:6473597d706e 4733 */
bogdanm 82:6473597d706e 4734 typedef union _hw_sdhc_fevt
bogdanm 82:6473597d706e 4735 {
bogdanm 82:6473597d706e 4736 uint32_t U;
bogdanm 82:6473597d706e 4737 struct _hw_sdhc_fevt_bitfields
bogdanm 82:6473597d706e 4738 {
bogdanm 82:6473597d706e 4739 uint32_t AC12NE : 1; //!< [0] Force Event Auto Command 12 Not Executed
bogdanm 82:6473597d706e 4740 uint32_t AC12TOE : 1; //!< [1] Force Event Auto Command 12 Time Out
bogdanm 82:6473597d706e 4741 //! Error
bogdanm 82:6473597d706e 4742 uint32_t AC12CE : 1; //!< [2] Force Event Auto Command 12 CRC Error
bogdanm 82:6473597d706e 4743 uint32_t AC12EBE : 1; //!< [3] Force Event Auto Command 12 End Bit
bogdanm 82:6473597d706e 4744 //! Error
bogdanm 82:6473597d706e 4745 uint32_t AC12IE : 1; //!< [4] Force Event Auto Command 12 Index Error
bogdanm 82:6473597d706e 4746 uint32_t RESERVED0 : 2; //!< [6:5]
bogdanm 82:6473597d706e 4747 uint32_t CNIBAC12E : 1; //!< [7] Force Event Command Not Executed By
bogdanm 82:6473597d706e 4748 //! Auto Command 12 Error
bogdanm 82:6473597d706e 4749 uint32_t RESERVED1 : 8; //!< [15:8]
bogdanm 82:6473597d706e 4750 uint32_t CTOE : 1; //!< [16] Force Event Command Time Out Error
bogdanm 82:6473597d706e 4751 uint32_t CCE : 1; //!< [17] Force Event Command CRC Error
bogdanm 82:6473597d706e 4752 uint32_t CEBE : 1; //!< [18] Force Event Command End Bit Error
bogdanm 82:6473597d706e 4753 uint32_t CIE : 1; //!< [19] Force Event Command Index Error
bogdanm 82:6473597d706e 4754 uint32_t DTOE : 1; //!< [20] Force Event Data Time Out Error
bogdanm 82:6473597d706e 4755 uint32_t DCE : 1; //!< [21] Force Event Data CRC Error
bogdanm 82:6473597d706e 4756 uint32_t DEBE : 1; //!< [22] Force Event Data End Bit Error
bogdanm 82:6473597d706e 4757 uint32_t RESERVED2 : 1; //!< [23]
bogdanm 82:6473597d706e 4758 uint32_t AC12E : 1; //!< [24] Force Event Auto Command 12 Error
bogdanm 82:6473597d706e 4759 uint32_t RESERVED3 : 3; //!< [27:25]
bogdanm 82:6473597d706e 4760 uint32_t DMAE : 1; //!< [28] Force Event DMA Error
bogdanm 82:6473597d706e 4761 uint32_t RESERVED4 : 2; //!< [30:29]
bogdanm 82:6473597d706e 4762 uint32_t CINT : 1; //!< [31] Force Event Card Interrupt
bogdanm 82:6473597d706e 4763 } B;
bogdanm 82:6473597d706e 4764 } hw_sdhc_fevt_t;
bogdanm 82:6473597d706e 4765 #endif
bogdanm 82:6473597d706e 4766
bogdanm 82:6473597d706e 4767 /*!
bogdanm 82:6473597d706e 4768 * @name Constants and macros for entire SDHC_FEVT register
bogdanm 82:6473597d706e 4769 */
bogdanm 82:6473597d706e 4770 //@{
bogdanm 82:6473597d706e 4771 #define HW_SDHC_FEVT_ADDR (REGS_SDHC_BASE + 0x50U)
bogdanm 82:6473597d706e 4772
bogdanm 82:6473597d706e 4773 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4774 #define HW_SDHC_FEVT (*(__O hw_sdhc_fevt_t *) HW_SDHC_FEVT_ADDR)
bogdanm 82:6473597d706e 4775 #define HW_SDHC_FEVT_RD() (HW_SDHC_FEVT.U)
bogdanm 82:6473597d706e 4776 #define HW_SDHC_FEVT_WR(v) (HW_SDHC_FEVT.U = (v))
bogdanm 82:6473597d706e 4777 #endif
bogdanm 82:6473597d706e 4778 //@}
bogdanm 82:6473597d706e 4779
bogdanm 82:6473597d706e 4780 /*
bogdanm 82:6473597d706e 4781 * Constants & macros for individual SDHC_FEVT bitfields
bogdanm 82:6473597d706e 4782 */
bogdanm 82:6473597d706e 4783
bogdanm 82:6473597d706e 4784 /*!
bogdanm 82:6473597d706e 4785 * @name Register SDHC_FEVT, field AC12NE[0] (WORZ)
bogdanm 82:6473597d706e 4786 *
bogdanm 82:6473597d706e 4787 * Forces AC12ERR[AC12NE] to be set.
bogdanm 82:6473597d706e 4788 */
bogdanm 82:6473597d706e 4789 //@{
bogdanm 82:6473597d706e 4790 #define BP_SDHC_FEVT_AC12NE (0U) //!< Bit position for SDHC_FEVT_AC12NE.
bogdanm 82:6473597d706e 4791 #define BM_SDHC_FEVT_AC12NE (0x00000001U) //!< Bit mask for SDHC_FEVT_AC12NE.
bogdanm 82:6473597d706e 4792 #define BS_SDHC_FEVT_AC12NE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12NE.
bogdanm 82:6473597d706e 4793
bogdanm 82:6473597d706e 4794 //! @brief Format value for bitfield SDHC_FEVT_AC12NE.
bogdanm 82:6473597d706e 4795 #define BF_SDHC_FEVT_AC12NE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12NE), uint32_t) & BM_SDHC_FEVT_AC12NE)
bogdanm 82:6473597d706e 4796
bogdanm 82:6473597d706e 4797 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4798 //! @brief Set the AC12NE field to a new value.
bogdanm 82:6473597d706e 4799 #define BW_SDHC_FEVT_AC12NE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12NE) = (v))
bogdanm 82:6473597d706e 4800 #endif
bogdanm 82:6473597d706e 4801 //@}
bogdanm 82:6473597d706e 4802
bogdanm 82:6473597d706e 4803 /*!
bogdanm 82:6473597d706e 4804 * @name Register SDHC_FEVT, field AC12TOE[1] (WORZ)
bogdanm 82:6473597d706e 4805 *
bogdanm 82:6473597d706e 4806 * Forces AC12ERR[AC12TOE] to be set.
bogdanm 82:6473597d706e 4807 */
bogdanm 82:6473597d706e 4808 //@{
bogdanm 82:6473597d706e 4809 #define BP_SDHC_FEVT_AC12TOE (1U) //!< Bit position for SDHC_FEVT_AC12TOE.
bogdanm 82:6473597d706e 4810 #define BM_SDHC_FEVT_AC12TOE (0x00000002U) //!< Bit mask for SDHC_FEVT_AC12TOE.
bogdanm 82:6473597d706e 4811 #define BS_SDHC_FEVT_AC12TOE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12TOE.
bogdanm 82:6473597d706e 4812
bogdanm 82:6473597d706e 4813 //! @brief Format value for bitfield SDHC_FEVT_AC12TOE.
bogdanm 82:6473597d706e 4814 #define BF_SDHC_FEVT_AC12TOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12TOE), uint32_t) & BM_SDHC_FEVT_AC12TOE)
bogdanm 82:6473597d706e 4815
bogdanm 82:6473597d706e 4816 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4817 //! @brief Set the AC12TOE field to a new value.
bogdanm 82:6473597d706e 4818 #define BW_SDHC_FEVT_AC12TOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12TOE) = (v))
bogdanm 82:6473597d706e 4819 #endif
bogdanm 82:6473597d706e 4820 //@}
bogdanm 82:6473597d706e 4821
bogdanm 82:6473597d706e 4822 /*!
bogdanm 82:6473597d706e 4823 * @name Register SDHC_FEVT, field AC12CE[2] (WORZ)
bogdanm 82:6473597d706e 4824 *
bogdanm 82:6473597d706e 4825 * Forces AC12ERR[AC12CE] to be set.
bogdanm 82:6473597d706e 4826 */
bogdanm 82:6473597d706e 4827 //@{
bogdanm 82:6473597d706e 4828 #define BP_SDHC_FEVT_AC12CE (2U) //!< Bit position for SDHC_FEVT_AC12CE.
bogdanm 82:6473597d706e 4829 #define BM_SDHC_FEVT_AC12CE (0x00000004U) //!< Bit mask for SDHC_FEVT_AC12CE.
bogdanm 82:6473597d706e 4830 #define BS_SDHC_FEVT_AC12CE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12CE.
bogdanm 82:6473597d706e 4831
bogdanm 82:6473597d706e 4832 //! @brief Format value for bitfield SDHC_FEVT_AC12CE.
bogdanm 82:6473597d706e 4833 #define BF_SDHC_FEVT_AC12CE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12CE), uint32_t) & BM_SDHC_FEVT_AC12CE)
bogdanm 82:6473597d706e 4834
bogdanm 82:6473597d706e 4835 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4836 //! @brief Set the AC12CE field to a new value.
bogdanm 82:6473597d706e 4837 #define BW_SDHC_FEVT_AC12CE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12CE) = (v))
bogdanm 82:6473597d706e 4838 #endif
bogdanm 82:6473597d706e 4839 //@}
bogdanm 82:6473597d706e 4840
bogdanm 82:6473597d706e 4841 /*!
bogdanm 82:6473597d706e 4842 * @name Register SDHC_FEVT, field AC12EBE[3] (WORZ)
bogdanm 82:6473597d706e 4843 *
bogdanm 82:6473597d706e 4844 * Forces AC12ERR[AC12EBE] to be set.
bogdanm 82:6473597d706e 4845 */
bogdanm 82:6473597d706e 4846 //@{
bogdanm 82:6473597d706e 4847 #define BP_SDHC_FEVT_AC12EBE (3U) //!< Bit position for SDHC_FEVT_AC12EBE.
bogdanm 82:6473597d706e 4848 #define BM_SDHC_FEVT_AC12EBE (0x00000008U) //!< Bit mask for SDHC_FEVT_AC12EBE.
bogdanm 82:6473597d706e 4849 #define BS_SDHC_FEVT_AC12EBE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12EBE.
bogdanm 82:6473597d706e 4850
bogdanm 82:6473597d706e 4851 //! @brief Format value for bitfield SDHC_FEVT_AC12EBE.
bogdanm 82:6473597d706e 4852 #define BF_SDHC_FEVT_AC12EBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12EBE), uint32_t) & BM_SDHC_FEVT_AC12EBE)
bogdanm 82:6473597d706e 4853
bogdanm 82:6473597d706e 4854 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4855 //! @brief Set the AC12EBE field to a new value.
bogdanm 82:6473597d706e 4856 #define BW_SDHC_FEVT_AC12EBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12EBE) = (v))
bogdanm 82:6473597d706e 4857 #endif
bogdanm 82:6473597d706e 4858 //@}
bogdanm 82:6473597d706e 4859
bogdanm 82:6473597d706e 4860 /*!
bogdanm 82:6473597d706e 4861 * @name Register SDHC_FEVT, field AC12IE[4] (WORZ)
bogdanm 82:6473597d706e 4862 *
bogdanm 82:6473597d706e 4863 * Forces AC12ERR[AC12IE] to be set.
bogdanm 82:6473597d706e 4864 */
bogdanm 82:6473597d706e 4865 //@{
bogdanm 82:6473597d706e 4866 #define BP_SDHC_FEVT_AC12IE (4U) //!< Bit position for SDHC_FEVT_AC12IE.
bogdanm 82:6473597d706e 4867 #define BM_SDHC_FEVT_AC12IE (0x00000010U) //!< Bit mask for SDHC_FEVT_AC12IE.
bogdanm 82:6473597d706e 4868 #define BS_SDHC_FEVT_AC12IE (1U) //!< Bit field size in bits for SDHC_FEVT_AC12IE.
bogdanm 82:6473597d706e 4869
bogdanm 82:6473597d706e 4870 //! @brief Format value for bitfield SDHC_FEVT_AC12IE.
bogdanm 82:6473597d706e 4871 #define BF_SDHC_FEVT_AC12IE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12IE), uint32_t) & BM_SDHC_FEVT_AC12IE)
bogdanm 82:6473597d706e 4872
bogdanm 82:6473597d706e 4873 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4874 //! @brief Set the AC12IE field to a new value.
bogdanm 82:6473597d706e 4875 #define BW_SDHC_FEVT_AC12IE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12IE) = (v))
bogdanm 82:6473597d706e 4876 #endif
bogdanm 82:6473597d706e 4877 //@}
bogdanm 82:6473597d706e 4878
bogdanm 82:6473597d706e 4879 /*!
bogdanm 82:6473597d706e 4880 * @name Register SDHC_FEVT, field CNIBAC12E[7] (WORZ)
bogdanm 82:6473597d706e 4881 *
bogdanm 82:6473597d706e 4882 * Forces AC12ERR[CNIBAC12E] to be set.
bogdanm 82:6473597d706e 4883 */
bogdanm 82:6473597d706e 4884 //@{
bogdanm 82:6473597d706e 4885 #define BP_SDHC_FEVT_CNIBAC12E (7U) //!< Bit position for SDHC_FEVT_CNIBAC12E.
bogdanm 82:6473597d706e 4886 #define BM_SDHC_FEVT_CNIBAC12E (0x00000080U) //!< Bit mask for SDHC_FEVT_CNIBAC12E.
bogdanm 82:6473597d706e 4887 #define BS_SDHC_FEVT_CNIBAC12E (1U) //!< Bit field size in bits for SDHC_FEVT_CNIBAC12E.
bogdanm 82:6473597d706e 4888
bogdanm 82:6473597d706e 4889 //! @brief Format value for bitfield SDHC_FEVT_CNIBAC12E.
bogdanm 82:6473597d706e 4890 #define BF_SDHC_FEVT_CNIBAC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CNIBAC12E), uint32_t) & BM_SDHC_FEVT_CNIBAC12E)
bogdanm 82:6473597d706e 4891
bogdanm 82:6473597d706e 4892 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4893 //! @brief Set the CNIBAC12E field to a new value.
bogdanm 82:6473597d706e 4894 #define BW_SDHC_FEVT_CNIBAC12E(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CNIBAC12E) = (v))
bogdanm 82:6473597d706e 4895 #endif
bogdanm 82:6473597d706e 4896 //@}
bogdanm 82:6473597d706e 4897
bogdanm 82:6473597d706e 4898 /*!
bogdanm 82:6473597d706e 4899 * @name Register SDHC_FEVT, field CTOE[16] (WORZ)
bogdanm 82:6473597d706e 4900 *
bogdanm 82:6473597d706e 4901 * Forces IRQSTAT[CTOE] to be set.
bogdanm 82:6473597d706e 4902 */
bogdanm 82:6473597d706e 4903 //@{
bogdanm 82:6473597d706e 4904 #define BP_SDHC_FEVT_CTOE (16U) //!< Bit position for SDHC_FEVT_CTOE.
bogdanm 82:6473597d706e 4905 #define BM_SDHC_FEVT_CTOE (0x00010000U) //!< Bit mask for SDHC_FEVT_CTOE.
bogdanm 82:6473597d706e 4906 #define BS_SDHC_FEVT_CTOE (1U) //!< Bit field size in bits for SDHC_FEVT_CTOE.
bogdanm 82:6473597d706e 4907
bogdanm 82:6473597d706e 4908 //! @brief Format value for bitfield SDHC_FEVT_CTOE.
bogdanm 82:6473597d706e 4909 #define BF_SDHC_FEVT_CTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CTOE), uint32_t) & BM_SDHC_FEVT_CTOE)
bogdanm 82:6473597d706e 4910
bogdanm 82:6473597d706e 4911 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4912 //! @brief Set the CTOE field to a new value.
bogdanm 82:6473597d706e 4913 #define BW_SDHC_FEVT_CTOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CTOE) = (v))
bogdanm 82:6473597d706e 4914 #endif
bogdanm 82:6473597d706e 4915 //@}
bogdanm 82:6473597d706e 4916
bogdanm 82:6473597d706e 4917 /*!
bogdanm 82:6473597d706e 4918 * @name Register SDHC_FEVT, field CCE[17] (WORZ)
bogdanm 82:6473597d706e 4919 *
bogdanm 82:6473597d706e 4920 * Forces IRQSTAT[CCE] to be set.
bogdanm 82:6473597d706e 4921 */
bogdanm 82:6473597d706e 4922 //@{
bogdanm 82:6473597d706e 4923 #define BP_SDHC_FEVT_CCE (17U) //!< Bit position for SDHC_FEVT_CCE.
bogdanm 82:6473597d706e 4924 #define BM_SDHC_FEVT_CCE (0x00020000U) //!< Bit mask for SDHC_FEVT_CCE.
bogdanm 82:6473597d706e 4925 #define BS_SDHC_FEVT_CCE (1U) //!< Bit field size in bits for SDHC_FEVT_CCE.
bogdanm 82:6473597d706e 4926
bogdanm 82:6473597d706e 4927 //! @brief Format value for bitfield SDHC_FEVT_CCE.
bogdanm 82:6473597d706e 4928 #define BF_SDHC_FEVT_CCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CCE), uint32_t) & BM_SDHC_FEVT_CCE)
bogdanm 82:6473597d706e 4929
bogdanm 82:6473597d706e 4930 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4931 //! @brief Set the CCE field to a new value.
bogdanm 82:6473597d706e 4932 #define BW_SDHC_FEVT_CCE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CCE) = (v))
bogdanm 82:6473597d706e 4933 #endif
bogdanm 82:6473597d706e 4934 //@}
bogdanm 82:6473597d706e 4935
bogdanm 82:6473597d706e 4936 /*!
bogdanm 82:6473597d706e 4937 * @name Register SDHC_FEVT, field CEBE[18] (WORZ)
bogdanm 82:6473597d706e 4938 *
bogdanm 82:6473597d706e 4939 * Forces IRQSTAT[CEBE] to be set.
bogdanm 82:6473597d706e 4940 */
bogdanm 82:6473597d706e 4941 //@{
bogdanm 82:6473597d706e 4942 #define BP_SDHC_FEVT_CEBE (18U) //!< Bit position for SDHC_FEVT_CEBE.
bogdanm 82:6473597d706e 4943 #define BM_SDHC_FEVT_CEBE (0x00040000U) //!< Bit mask for SDHC_FEVT_CEBE.
bogdanm 82:6473597d706e 4944 #define BS_SDHC_FEVT_CEBE (1U) //!< Bit field size in bits for SDHC_FEVT_CEBE.
bogdanm 82:6473597d706e 4945
bogdanm 82:6473597d706e 4946 //! @brief Format value for bitfield SDHC_FEVT_CEBE.
bogdanm 82:6473597d706e 4947 #define BF_SDHC_FEVT_CEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CEBE), uint32_t) & BM_SDHC_FEVT_CEBE)
bogdanm 82:6473597d706e 4948
bogdanm 82:6473597d706e 4949 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4950 //! @brief Set the CEBE field to a new value.
bogdanm 82:6473597d706e 4951 #define BW_SDHC_FEVT_CEBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CEBE) = (v))
bogdanm 82:6473597d706e 4952 #endif
bogdanm 82:6473597d706e 4953 //@}
bogdanm 82:6473597d706e 4954
bogdanm 82:6473597d706e 4955 /*!
bogdanm 82:6473597d706e 4956 * @name Register SDHC_FEVT, field CIE[19] (WORZ)
bogdanm 82:6473597d706e 4957 *
bogdanm 82:6473597d706e 4958 * Forces IRQSTAT[CCE] to be set.
bogdanm 82:6473597d706e 4959 */
bogdanm 82:6473597d706e 4960 //@{
bogdanm 82:6473597d706e 4961 #define BP_SDHC_FEVT_CIE (19U) //!< Bit position for SDHC_FEVT_CIE.
bogdanm 82:6473597d706e 4962 #define BM_SDHC_FEVT_CIE (0x00080000U) //!< Bit mask for SDHC_FEVT_CIE.
bogdanm 82:6473597d706e 4963 #define BS_SDHC_FEVT_CIE (1U) //!< Bit field size in bits for SDHC_FEVT_CIE.
bogdanm 82:6473597d706e 4964
bogdanm 82:6473597d706e 4965 //! @brief Format value for bitfield SDHC_FEVT_CIE.
bogdanm 82:6473597d706e 4966 #define BF_SDHC_FEVT_CIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CIE), uint32_t) & BM_SDHC_FEVT_CIE)
bogdanm 82:6473597d706e 4967
bogdanm 82:6473597d706e 4968 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4969 //! @brief Set the CIE field to a new value.
bogdanm 82:6473597d706e 4970 #define BW_SDHC_FEVT_CIE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CIE) = (v))
bogdanm 82:6473597d706e 4971 #endif
bogdanm 82:6473597d706e 4972 //@}
bogdanm 82:6473597d706e 4973
bogdanm 82:6473597d706e 4974 /*!
bogdanm 82:6473597d706e 4975 * @name Register SDHC_FEVT, field DTOE[20] (WORZ)
bogdanm 82:6473597d706e 4976 *
bogdanm 82:6473597d706e 4977 * Forces IRQSTAT[DTOE] to be set.
bogdanm 82:6473597d706e 4978 */
bogdanm 82:6473597d706e 4979 //@{
bogdanm 82:6473597d706e 4980 #define BP_SDHC_FEVT_DTOE (20U) //!< Bit position for SDHC_FEVT_DTOE.
bogdanm 82:6473597d706e 4981 #define BM_SDHC_FEVT_DTOE (0x00100000U) //!< Bit mask for SDHC_FEVT_DTOE.
bogdanm 82:6473597d706e 4982 #define BS_SDHC_FEVT_DTOE (1U) //!< Bit field size in bits for SDHC_FEVT_DTOE.
bogdanm 82:6473597d706e 4983
bogdanm 82:6473597d706e 4984 //! @brief Format value for bitfield SDHC_FEVT_DTOE.
bogdanm 82:6473597d706e 4985 #define BF_SDHC_FEVT_DTOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DTOE), uint32_t) & BM_SDHC_FEVT_DTOE)
bogdanm 82:6473597d706e 4986
bogdanm 82:6473597d706e 4987 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 4988 //! @brief Set the DTOE field to a new value.
bogdanm 82:6473597d706e 4989 #define BW_SDHC_FEVT_DTOE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DTOE) = (v))
bogdanm 82:6473597d706e 4990 #endif
bogdanm 82:6473597d706e 4991 //@}
bogdanm 82:6473597d706e 4992
bogdanm 82:6473597d706e 4993 /*!
bogdanm 82:6473597d706e 4994 * @name Register SDHC_FEVT, field DCE[21] (WORZ)
bogdanm 82:6473597d706e 4995 *
bogdanm 82:6473597d706e 4996 * Forces IRQSTAT[DCE] to be set.
bogdanm 82:6473597d706e 4997 */
bogdanm 82:6473597d706e 4998 //@{
bogdanm 82:6473597d706e 4999 #define BP_SDHC_FEVT_DCE (21U) //!< Bit position for SDHC_FEVT_DCE.
bogdanm 82:6473597d706e 5000 #define BM_SDHC_FEVT_DCE (0x00200000U) //!< Bit mask for SDHC_FEVT_DCE.
bogdanm 82:6473597d706e 5001 #define BS_SDHC_FEVT_DCE (1U) //!< Bit field size in bits for SDHC_FEVT_DCE.
bogdanm 82:6473597d706e 5002
bogdanm 82:6473597d706e 5003 //! @brief Format value for bitfield SDHC_FEVT_DCE.
bogdanm 82:6473597d706e 5004 #define BF_SDHC_FEVT_DCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DCE), uint32_t) & BM_SDHC_FEVT_DCE)
bogdanm 82:6473597d706e 5005
bogdanm 82:6473597d706e 5006 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5007 //! @brief Set the DCE field to a new value.
bogdanm 82:6473597d706e 5008 #define BW_SDHC_FEVT_DCE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DCE) = (v))
bogdanm 82:6473597d706e 5009 #endif
bogdanm 82:6473597d706e 5010 //@}
bogdanm 82:6473597d706e 5011
bogdanm 82:6473597d706e 5012 /*!
bogdanm 82:6473597d706e 5013 * @name Register SDHC_FEVT, field DEBE[22] (WORZ)
bogdanm 82:6473597d706e 5014 *
bogdanm 82:6473597d706e 5015 * Forces IRQSTAT[DEBE] to be set.
bogdanm 82:6473597d706e 5016 */
bogdanm 82:6473597d706e 5017 //@{
bogdanm 82:6473597d706e 5018 #define BP_SDHC_FEVT_DEBE (22U) //!< Bit position for SDHC_FEVT_DEBE.
bogdanm 82:6473597d706e 5019 #define BM_SDHC_FEVT_DEBE (0x00400000U) //!< Bit mask for SDHC_FEVT_DEBE.
bogdanm 82:6473597d706e 5020 #define BS_SDHC_FEVT_DEBE (1U) //!< Bit field size in bits for SDHC_FEVT_DEBE.
bogdanm 82:6473597d706e 5021
bogdanm 82:6473597d706e 5022 //! @brief Format value for bitfield SDHC_FEVT_DEBE.
bogdanm 82:6473597d706e 5023 #define BF_SDHC_FEVT_DEBE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DEBE), uint32_t) & BM_SDHC_FEVT_DEBE)
bogdanm 82:6473597d706e 5024
bogdanm 82:6473597d706e 5025 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5026 //! @brief Set the DEBE field to a new value.
bogdanm 82:6473597d706e 5027 #define BW_SDHC_FEVT_DEBE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DEBE) = (v))
bogdanm 82:6473597d706e 5028 #endif
bogdanm 82:6473597d706e 5029 //@}
bogdanm 82:6473597d706e 5030
bogdanm 82:6473597d706e 5031 /*!
bogdanm 82:6473597d706e 5032 * @name Register SDHC_FEVT, field AC12E[24] (WORZ)
bogdanm 82:6473597d706e 5033 *
bogdanm 82:6473597d706e 5034 * Forces IRQSTAT[AC12E] to be set.
bogdanm 82:6473597d706e 5035 */
bogdanm 82:6473597d706e 5036 //@{
bogdanm 82:6473597d706e 5037 #define BP_SDHC_FEVT_AC12E (24U) //!< Bit position for SDHC_FEVT_AC12E.
bogdanm 82:6473597d706e 5038 #define BM_SDHC_FEVT_AC12E (0x01000000U) //!< Bit mask for SDHC_FEVT_AC12E.
bogdanm 82:6473597d706e 5039 #define BS_SDHC_FEVT_AC12E (1U) //!< Bit field size in bits for SDHC_FEVT_AC12E.
bogdanm 82:6473597d706e 5040
bogdanm 82:6473597d706e 5041 //! @brief Format value for bitfield SDHC_FEVT_AC12E.
bogdanm 82:6473597d706e 5042 #define BF_SDHC_FEVT_AC12E(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_AC12E), uint32_t) & BM_SDHC_FEVT_AC12E)
bogdanm 82:6473597d706e 5043
bogdanm 82:6473597d706e 5044 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5045 //! @brief Set the AC12E field to a new value.
bogdanm 82:6473597d706e 5046 #define BW_SDHC_FEVT_AC12E(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_AC12E) = (v))
bogdanm 82:6473597d706e 5047 #endif
bogdanm 82:6473597d706e 5048 //@}
bogdanm 82:6473597d706e 5049
bogdanm 82:6473597d706e 5050 /*!
bogdanm 82:6473597d706e 5051 * @name Register SDHC_FEVT, field DMAE[28] (WORZ)
bogdanm 82:6473597d706e 5052 *
bogdanm 82:6473597d706e 5053 * Forces the DMAE bit of Interrupt Status Register to be set.
bogdanm 82:6473597d706e 5054 */
bogdanm 82:6473597d706e 5055 //@{
bogdanm 82:6473597d706e 5056 #define BP_SDHC_FEVT_DMAE (28U) //!< Bit position for SDHC_FEVT_DMAE.
bogdanm 82:6473597d706e 5057 #define BM_SDHC_FEVT_DMAE (0x10000000U) //!< Bit mask for SDHC_FEVT_DMAE.
bogdanm 82:6473597d706e 5058 #define BS_SDHC_FEVT_DMAE (1U) //!< Bit field size in bits for SDHC_FEVT_DMAE.
bogdanm 82:6473597d706e 5059
bogdanm 82:6473597d706e 5060 //! @brief Format value for bitfield SDHC_FEVT_DMAE.
bogdanm 82:6473597d706e 5061 #define BF_SDHC_FEVT_DMAE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_DMAE), uint32_t) & BM_SDHC_FEVT_DMAE)
bogdanm 82:6473597d706e 5062
bogdanm 82:6473597d706e 5063 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5064 //! @brief Set the DMAE field to a new value.
bogdanm 82:6473597d706e 5065 #define BW_SDHC_FEVT_DMAE(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_DMAE) = (v))
bogdanm 82:6473597d706e 5066 #endif
bogdanm 82:6473597d706e 5067 //@}
bogdanm 82:6473597d706e 5068
bogdanm 82:6473597d706e 5069 /*!
bogdanm 82:6473597d706e 5070 * @name Register SDHC_FEVT, field CINT[31] (WORZ)
bogdanm 82:6473597d706e 5071 *
bogdanm 82:6473597d706e 5072 * Writing 1 to this bit generates a short low-level pulse on the internal
bogdanm 82:6473597d706e 5073 * DAT[1] line, as if a self-clearing interrupt was received from the external card.
bogdanm 82:6473597d706e 5074 * If enabled, the CINT bit will be set and the interrupt service routine may
bogdanm 82:6473597d706e 5075 * treat this interrupt as a normal interrupt from the external card.
bogdanm 82:6473597d706e 5076 */
bogdanm 82:6473597d706e 5077 //@{
bogdanm 82:6473597d706e 5078 #define BP_SDHC_FEVT_CINT (31U) //!< Bit position for SDHC_FEVT_CINT.
bogdanm 82:6473597d706e 5079 #define BM_SDHC_FEVT_CINT (0x80000000U) //!< Bit mask for SDHC_FEVT_CINT.
bogdanm 82:6473597d706e 5080 #define BS_SDHC_FEVT_CINT (1U) //!< Bit field size in bits for SDHC_FEVT_CINT.
bogdanm 82:6473597d706e 5081
bogdanm 82:6473597d706e 5082 //! @brief Format value for bitfield SDHC_FEVT_CINT.
bogdanm 82:6473597d706e 5083 #define BF_SDHC_FEVT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_FEVT_CINT), uint32_t) & BM_SDHC_FEVT_CINT)
bogdanm 82:6473597d706e 5084
bogdanm 82:6473597d706e 5085 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5086 //! @brief Set the CINT field to a new value.
bogdanm 82:6473597d706e 5087 #define BW_SDHC_FEVT_CINT(v) (BITBAND_ACCESS32(HW_SDHC_FEVT_ADDR, BP_SDHC_FEVT_CINT) = (v))
bogdanm 82:6473597d706e 5088 #endif
bogdanm 82:6473597d706e 5089 //@}
bogdanm 82:6473597d706e 5090
bogdanm 82:6473597d706e 5091 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5092 // HW_SDHC_ADMAES - ADMA Error Status register
bogdanm 82:6473597d706e 5093 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5094
bogdanm 82:6473597d706e 5095 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5096 /*!
bogdanm 82:6473597d706e 5097 * @brief HW_SDHC_ADMAES - ADMA Error Status register (RO)
bogdanm 82:6473597d706e 5098 *
bogdanm 82:6473597d706e 5099 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 5100 *
bogdanm 82:6473597d706e 5101 * When an ADMA error interrupt has occurred, the ADMA Error States field in
bogdanm 82:6473597d706e 5102 * this register holds the ADMA state and the ADMA System Address register holds the
bogdanm 82:6473597d706e 5103 * address around the error descriptor. For recovering from this error, the host
bogdanm 82:6473597d706e 5104 * driver requires the ADMA state to identify the error descriptor address as
bogdanm 82:6473597d706e 5105 * follows: ST_STOP: Previous location set in the ADMA System Address register is
bogdanm 82:6473597d706e 5106 * the error descriptor address. ST_FDS: Current location set in the ADMA System
bogdanm 82:6473597d706e 5107 * Address register is the error descriptor address. ST_CADR: This state is never
bogdanm 82:6473597d706e 5108 * set because it only increments the descriptor pointer and doesn't generate an
bogdanm 82:6473597d706e 5109 * ADMA error. ST_TFR: Previous location set in the ADMA System Address register
bogdanm 82:6473597d706e 5110 * is the error descriptor address. In case of a write operation, the host driver
bogdanm 82:6473597d706e 5111 * must use the ACMD22 to get the number of the written block, rather than using
bogdanm 82:6473597d706e 5112 * this information, because unwritten data may exist in the host controller.
bogdanm 82:6473597d706e 5113 * The host controller generates the ADMA error interrupt when it detects invalid
bogdanm 82:6473597d706e 5114 * descriptor data (valid = 0) in the ST_FDS state. The host driver can
bogdanm 82:6473597d706e 5115 * distinguish this error by reading the valid bit of the error descriptor. ADMA Error
bogdanm 82:6473597d706e 5116 * State coding D01-D00 ADMA Error State when error has occurred Contents of ADMA
bogdanm 82:6473597d706e 5117 * System Address register 00 ST_STOP (Stop DMA) Holds the address of the next
bogdanm 82:6473597d706e 5118 * executable descriptor command 01 ST_FDS (fetch descriptor) Holds the valid
bogdanm 82:6473597d706e 5119 * descriptor address 10 ST_CADR (change address) No ADMA error is generated 11 ST_TFR
bogdanm 82:6473597d706e 5120 * (Transfer Data) Holds the address of the next executable descriptor command
bogdanm 82:6473597d706e 5121 */
bogdanm 82:6473597d706e 5122 typedef union _hw_sdhc_admaes
bogdanm 82:6473597d706e 5123 {
bogdanm 82:6473597d706e 5124 uint32_t U;
bogdanm 82:6473597d706e 5125 struct _hw_sdhc_admaes_bitfields
bogdanm 82:6473597d706e 5126 {
bogdanm 82:6473597d706e 5127 uint32_t ADMAES : 2; //!< [1:0] ADMA Error State (When ADMA Error Is
bogdanm 82:6473597d706e 5128 //! Occurred.)
bogdanm 82:6473597d706e 5129 uint32_t ADMALME : 1; //!< [2] ADMA Length Mismatch Error
bogdanm 82:6473597d706e 5130 uint32_t ADMADCE : 1; //!< [3] ADMA Descriptor Error
bogdanm 82:6473597d706e 5131 uint32_t RESERVED0 : 28; //!< [31:4]
bogdanm 82:6473597d706e 5132 } B;
bogdanm 82:6473597d706e 5133 } hw_sdhc_admaes_t;
bogdanm 82:6473597d706e 5134 #endif
bogdanm 82:6473597d706e 5135
bogdanm 82:6473597d706e 5136 /*!
bogdanm 82:6473597d706e 5137 * @name Constants and macros for entire SDHC_ADMAES register
bogdanm 82:6473597d706e 5138 */
bogdanm 82:6473597d706e 5139 //@{
bogdanm 82:6473597d706e 5140 #define HW_SDHC_ADMAES_ADDR (REGS_SDHC_BASE + 0x54U)
bogdanm 82:6473597d706e 5141
bogdanm 82:6473597d706e 5142 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5143 #define HW_SDHC_ADMAES (*(__I hw_sdhc_admaes_t *) HW_SDHC_ADMAES_ADDR)
bogdanm 82:6473597d706e 5144 #define HW_SDHC_ADMAES_RD() (HW_SDHC_ADMAES.U)
bogdanm 82:6473597d706e 5145 #endif
bogdanm 82:6473597d706e 5146 //@}
bogdanm 82:6473597d706e 5147
bogdanm 82:6473597d706e 5148 /*
bogdanm 82:6473597d706e 5149 * Constants & macros for individual SDHC_ADMAES bitfields
bogdanm 82:6473597d706e 5150 */
bogdanm 82:6473597d706e 5151
bogdanm 82:6473597d706e 5152 /*!
bogdanm 82:6473597d706e 5153 * @name Register SDHC_ADMAES, field ADMAES[1:0] (RO)
bogdanm 82:6473597d706e 5154 *
bogdanm 82:6473597d706e 5155 * Indicates the state of the ADMA when an error has occurred during an ADMA
bogdanm 82:6473597d706e 5156 * data transfer.
bogdanm 82:6473597d706e 5157 */
bogdanm 82:6473597d706e 5158 //@{
bogdanm 82:6473597d706e 5159 #define BP_SDHC_ADMAES_ADMAES (0U) //!< Bit position for SDHC_ADMAES_ADMAES.
bogdanm 82:6473597d706e 5160 #define BM_SDHC_ADMAES_ADMAES (0x00000003U) //!< Bit mask for SDHC_ADMAES_ADMAES.
bogdanm 82:6473597d706e 5161 #define BS_SDHC_ADMAES_ADMAES (2U) //!< Bit field size in bits for SDHC_ADMAES_ADMAES.
bogdanm 82:6473597d706e 5162
bogdanm 82:6473597d706e 5163 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5164 //! @brief Read current value of the SDHC_ADMAES_ADMAES field.
bogdanm 82:6473597d706e 5165 #define BR_SDHC_ADMAES_ADMAES (HW_SDHC_ADMAES.B.ADMAES)
bogdanm 82:6473597d706e 5166 #endif
bogdanm 82:6473597d706e 5167 //@}
bogdanm 82:6473597d706e 5168
bogdanm 82:6473597d706e 5169 /*!
bogdanm 82:6473597d706e 5170 * @name Register SDHC_ADMAES, field ADMALME[2] (RO)
bogdanm 82:6473597d706e 5171 *
bogdanm 82:6473597d706e 5172 * This error occurs in the following 2 cases: While the block count enable is
bogdanm 82:6473597d706e 5173 * being set, the total data length specified by the descriptor table is different
bogdanm 82:6473597d706e 5174 * from that specified by the block count and block length. Total data length
bogdanm 82:6473597d706e 5175 * can not be divided by the block length.
bogdanm 82:6473597d706e 5176 *
bogdanm 82:6473597d706e 5177 * Values:
bogdanm 82:6473597d706e 5178 * - 0 - No error.
bogdanm 82:6473597d706e 5179 * - 1 - Error.
bogdanm 82:6473597d706e 5180 */
bogdanm 82:6473597d706e 5181 //@{
bogdanm 82:6473597d706e 5182 #define BP_SDHC_ADMAES_ADMALME (2U) //!< Bit position for SDHC_ADMAES_ADMALME.
bogdanm 82:6473597d706e 5183 #define BM_SDHC_ADMAES_ADMALME (0x00000004U) //!< Bit mask for SDHC_ADMAES_ADMALME.
bogdanm 82:6473597d706e 5184 #define BS_SDHC_ADMAES_ADMALME (1U) //!< Bit field size in bits for SDHC_ADMAES_ADMALME.
bogdanm 82:6473597d706e 5185
bogdanm 82:6473597d706e 5186 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5187 //! @brief Read current value of the SDHC_ADMAES_ADMALME field.
bogdanm 82:6473597d706e 5188 #define BR_SDHC_ADMAES_ADMALME (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR, BP_SDHC_ADMAES_ADMALME))
bogdanm 82:6473597d706e 5189 #endif
bogdanm 82:6473597d706e 5190 //@}
bogdanm 82:6473597d706e 5191
bogdanm 82:6473597d706e 5192 /*!
bogdanm 82:6473597d706e 5193 * @name Register SDHC_ADMAES, field ADMADCE[3] (RO)
bogdanm 82:6473597d706e 5194 *
bogdanm 82:6473597d706e 5195 * This error occurs when an invalid descriptor is fetched by ADMA.
bogdanm 82:6473597d706e 5196 *
bogdanm 82:6473597d706e 5197 * Values:
bogdanm 82:6473597d706e 5198 * - 0 - No error.
bogdanm 82:6473597d706e 5199 * - 1 - Error.
bogdanm 82:6473597d706e 5200 */
bogdanm 82:6473597d706e 5201 //@{
bogdanm 82:6473597d706e 5202 #define BP_SDHC_ADMAES_ADMADCE (3U) //!< Bit position for SDHC_ADMAES_ADMADCE.
bogdanm 82:6473597d706e 5203 #define BM_SDHC_ADMAES_ADMADCE (0x00000008U) //!< Bit mask for SDHC_ADMAES_ADMADCE.
bogdanm 82:6473597d706e 5204 #define BS_SDHC_ADMAES_ADMADCE (1U) //!< Bit field size in bits for SDHC_ADMAES_ADMADCE.
bogdanm 82:6473597d706e 5205
bogdanm 82:6473597d706e 5206 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5207 //! @brief Read current value of the SDHC_ADMAES_ADMADCE field.
bogdanm 82:6473597d706e 5208 #define BR_SDHC_ADMAES_ADMADCE (BITBAND_ACCESS32(HW_SDHC_ADMAES_ADDR, BP_SDHC_ADMAES_ADMADCE))
bogdanm 82:6473597d706e 5209 #endif
bogdanm 82:6473597d706e 5210 //@}
bogdanm 82:6473597d706e 5211
bogdanm 82:6473597d706e 5212 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5213 // HW_SDHC_ADSADDR - ADMA System Addressregister
bogdanm 82:6473597d706e 5214 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5215
bogdanm 82:6473597d706e 5216 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5217 /*!
bogdanm 82:6473597d706e 5218 * @brief HW_SDHC_ADSADDR - ADMA System Addressregister (RW)
bogdanm 82:6473597d706e 5219 *
bogdanm 82:6473597d706e 5220 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 5221 *
bogdanm 82:6473597d706e 5222 * This register contains the physical system memory address used for ADMA
bogdanm 82:6473597d706e 5223 * transfers.
bogdanm 82:6473597d706e 5224 */
bogdanm 82:6473597d706e 5225 typedef union _hw_sdhc_adsaddr
bogdanm 82:6473597d706e 5226 {
bogdanm 82:6473597d706e 5227 uint32_t U;
bogdanm 82:6473597d706e 5228 struct _hw_sdhc_adsaddr_bitfields
bogdanm 82:6473597d706e 5229 {
bogdanm 82:6473597d706e 5230 uint32_t RESERVED0 : 2; //!< [1:0]
bogdanm 82:6473597d706e 5231 uint32_t ADSADDR : 30; //!< [31:2] ADMA System Address
bogdanm 82:6473597d706e 5232 } B;
bogdanm 82:6473597d706e 5233 } hw_sdhc_adsaddr_t;
bogdanm 82:6473597d706e 5234 #endif
bogdanm 82:6473597d706e 5235
bogdanm 82:6473597d706e 5236 /*!
bogdanm 82:6473597d706e 5237 * @name Constants and macros for entire SDHC_ADSADDR register
bogdanm 82:6473597d706e 5238 */
bogdanm 82:6473597d706e 5239 //@{
bogdanm 82:6473597d706e 5240 #define HW_SDHC_ADSADDR_ADDR (REGS_SDHC_BASE + 0x58U)
bogdanm 82:6473597d706e 5241
bogdanm 82:6473597d706e 5242 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5243 #define HW_SDHC_ADSADDR (*(__IO hw_sdhc_adsaddr_t *) HW_SDHC_ADSADDR_ADDR)
bogdanm 82:6473597d706e 5244 #define HW_SDHC_ADSADDR_RD() (HW_SDHC_ADSADDR.U)
bogdanm 82:6473597d706e 5245 #define HW_SDHC_ADSADDR_WR(v) (HW_SDHC_ADSADDR.U = (v))
bogdanm 82:6473597d706e 5246 #define HW_SDHC_ADSADDR_SET(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() | (v)))
bogdanm 82:6473597d706e 5247 #define HW_SDHC_ADSADDR_CLR(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() & ~(v)))
bogdanm 82:6473597d706e 5248 #define HW_SDHC_ADSADDR_TOG(v) (HW_SDHC_ADSADDR_WR(HW_SDHC_ADSADDR_RD() ^ (v)))
bogdanm 82:6473597d706e 5249 #endif
bogdanm 82:6473597d706e 5250 //@}
bogdanm 82:6473597d706e 5251
bogdanm 82:6473597d706e 5252 /*
bogdanm 82:6473597d706e 5253 * Constants & macros for individual SDHC_ADSADDR bitfields
bogdanm 82:6473597d706e 5254 */
bogdanm 82:6473597d706e 5255
bogdanm 82:6473597d706e 5256 /*!
bogdanm 82:6473597d706e 5257 * @name Register SDHC_ADSADDR, field ADSADDR[31:2] (RW)
bogdanm 82:6473597d706e 5258 *
bogdanm 82:6473597d706e 5259 * Holds the word address of the executing command in the descriptor table. At
bogdanm 82:6473597d706e 5260 * the start of ADMA, the host driver shall set the start address of the
bogdanm 82:6473597d706e 5261 * Descriptor table. The ADMA engine increments this register address whenever fetching a
bogdanm 82:6473597d706e 5262 * descriptor command. When the ADMA is stopped at the block gap, this register
bogdanm 82:6473597d706e 5263 * indicates the address of the next executable descriptor command. When the ADMA
bogdanm 82:6473597d706e 5264 * error interrupt is generated, this register shall hold the valid descriptor
bogdanm 82:6473597d706e 5265 * address depending on the ADMA state. The lower 2 bits of this register is tied
bogdanm 82:6473597d706e 5266 * to '0' so the ADMA address is always word-aligned. Because this register
bogdanm 82:6473597d706e 5267 * supports dynamic address reflecting, when TC bit is set, it automatically alters the
bogdanm 82:6473597d706e 5268 * value of internal address counter, so SW cannot change this register when TC
bogdanm 82:6473597d706e 5269 * bit is set.
bogdanm 82:6473597d706e 5270 */
bogdanm 82:6473597d706e 5271 //@{
bogdanm 82:6473597d706e 5272 #define BP_SDHC_ADSADDR_ADSADDR (2U) //!< Bit position for SDHC_ADSADDR_ADSADDR.
bogdanm 82:6473597d706e 5273 #define BM_SDHC_ADSADDR_ADSADDR (0xFFFFFFFCU) //!< Bit mask for SDHC_ADSADDR_ADSADDR.
bogdanm 82:6473597d706e 5274 #define BS_SDHC_ADSADDR_ADSADDR (30U) //!< Bit field size in bits for SDHC_ADSADDR_ADSADDR.
bogdanm 82:6473597d706e 5275
bogdanm 82:6473597d706e 5276 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5277 //! @brief Read current value of the SDHC_ADSADDR_ADSADDR field.
bogdanm 82:6473597d706e 5278 #define BR_SDHC_ADSADDR_ADSADDR (HW_SDHC_ADSADDR.B.ADSADDR)
bogdanm 82:6473597d706e 5279 #endif
bogdanm 82:6473597d706e 5280
bogdanm 82:6473597d706e 5281 //! @brief Format value for bitfield SDHC_ADSADDR_ADSADDR.
bogdanm 82:6473597d706e 5282 #define BF_SDHC_ADSADDR_ADSADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_ADSADDR_ADSADDR), uint32_t) & BM_SDHC_ADSADDR_ADSADDR)
bogdanm 82:6473597d706e 5283
bogdanm 82:6473597d706e 5284 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5285 //! @brief Set the ADSADDR field to a new value.
bogdanm 82:6473597d706e 5286 #define BW_SDHC_ADSADDR_ADSADDR(v) (HW_SDHC_ADSADDR_WR((HW_SDHC_ADSADDR_RD() & ~BM_SDHC_ADSADDR_ADSADDR) | BF_SDHC_ADSADDR_ADSADDR(v)))
bogdanm 82:6473597d706e 5287 #endif
bogdanm 82:6473597d706e 5288 //@}
bogdanm 82:6473597d706e 5289
bogdanm 82:6473597d706e 5290 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5291 // HW_SDHC_VENDOR - Vendor Specific register
bogdanm 82:6473597d706e 5292 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5293
bogdanm 82:6473597d706e 5294 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5295 /*!
bogdanm 82:6473597d706e 5296 * @brief HW_SDHC_VENDOR - Vendor Specific register (RW)
bogdanm 82:6473597d706e 5297 *
bogdanm 82:6473597d706e 5298 * Reset value: 0x00000001U
bogdanm 82:6473597d706e 5299 *
bogdanm 82:6473597d706e 5300 * This register contains the vendor-specific control/status register.
bogdanm 82:6473597d706e 5301 */
bogdanm 82:6473597d706e 5302 typedef union _hw_sdhc_vendor
bogdanm 82:6473597d706e 5303 {
bogdanm 82:6473597d706e 5304 uint32_t U;
bogdanm 82:6473597d706e 5305 struct _hw_sdhc_vendor_bitfields
bogdanm 82:6473597d706e 5306 {
bogdanm 82:6473597d706e 5307 uint32_t EXTDMAEN : 1; //!< [0] External DMA Request Enable
bogdanm 82:6473597d706e 5308 uint32_t EXBLKNU : 1; //!< [1] Exact Block Number Block Read Enable
bogdanm 82:6473597d706e 5309 //! For SDIO CMD53
bogdanm 82:6473597d706e 5310 uint32_t RESERVED0 : 14; //!< [15:2]
bogdanm 82:6473597d706e 5311 uint32_t INTSTVAL : 8; //!< [23:16] Internal State Value
bogdanm 82:6473597d706e 5312 uint32_t RESERVED1 : 8; //!< [31:24]
bogdanm 82:6473597d706e 5313 } B;
bogdanm 82:6473597d706e 5314 } hw_sdhc_vendor_t;
bogdanm 82:6473597d706e 5315 #endif
bogdanm 82:6473597d706e 5316
bogdanm 82:6473597d706e 5317 /*!
bogdanm 82:6473597d706e 5318 * @name Constants and macros for entire SDHC_VENDOR register
bogdanm 82:6473597d706e 5319 */
bogdanm 82:6473597d706e 5320 //@{
bogdanm 82:6473597d706e 5321 #define HW_SDHC_VENDOR_ADDR (REGS_SDHC_BASE + 0xC0U)
bogdanm 82:6473597d706e 5322
bogdanm 82:6473597d706e 5323 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5324 #define HW_SDHC_VENDOR (*(__IO hw_sdhc_vendor_t *) HW_SDHC_VENDOR_ADDR)
bogdanm 82:6473597d706e 5325 #define HW_SDHC_VENDOR_RD() (HW_SDHC_VENDOR.U)
bogdanm 82:6473597d706e 5326 #define HW_SDHC_VENDOR_WR(v) (HW_SDHC_VENDOR.U = (v))
bogdanm 82:6473597d706e 5327 #define HW_SDHC_VENDOR_SET(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() | (v)))
bogdanm 82:6473597d706e 5328 #define HW_SDHC_VENDOR_CLR(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() & ~(v)))
bogdanm 82:6473597d706e 5329 #define HW_SDHC_VENDOR_TOG(v) (HW_SDHC_VENDOR_WR(HW_SDHC_VENDOR_RD() ^ (v)))
bogdanm 82:6473597d706e 5330 #endif
bogdanm 82:6473597d706e 5331 //@}
bogdanm 82:6473597d706e 5332
bogdanm 82:6473597d706e 5333 /*
bogdanm 82:6473597d706e 5334 * Constants & macros for individual SDHC_VENDOR bitfields
bogdanm 82:6473597d706e 5335 */
bogdanm 82:6473597d706e 5336
bogdanm 82:6473597d706e 5337 /*!
bogdanm 82:6473597d706e 5338 * @name Register SDHC_VENDOR, field EXTDMAEN[0] (RW)
bogdanm 82:6473597d706e 5339 *
bogdanm 82:6473597d706e 5340 * Enables the request to external DMA. When the internal DMA (either simple DMA
bogdanm 82:6473597d706e 5341 * or advanced DMA) is not in use, and this bit is set, SDHC will send out DMA
bogdanm 82:6473597d706e 5342 * request when the internal buffer is ready. This bit is particularly useful when
bogdanm 82:6473597d706e 5343 * transferring data by CPU polling mode, and it is not allowed to send out the
bogdanm 82:6473597d706e 5344 * external DMA request. By default, this bit is set.
bogdanm 82:6473597d706e 5345 *
bogdanm 82:6473597d706e 5346 * Values:
bogdanm 82:6473597d706e 5347 * - 0 - In any scenario, SDHC does not send out the external DMA request.
bogdanm 82:6473597d706e 5348 * - 1 - When internal DMA is not active, the external DMA request will be sent
bogdanm 82:6473597d706e 5349 * out.
bogdanm 82:6473597d706e 5350 */
bogdanm 82:6473597d706e 5351 //@{
bogdanm 82:6473597d706e 5352 #define BP_SDHC_VENDOR_EXTDMAEN (0U) //!< Bit position for SDHC_VENDOR_EXTDMAEN.
bogdanm 82:6473597d706e 5353 #define BM_SDHC_VENDOR_EXTDMAEN (0x00000001U) //!< Bit mask for SDHC_VENDOR_EXTDMAEN.
bogdanm 82:6473597d706e 5354 #define BS_SDHC_VENDOR_EXTDMAEN (1U) //!< Bit field size in bits for SDHC_VENDOR_EXTDMAEN.
bogdanm 82:6473597d706e 5355
bogdanm 82:6473597d706e 5356 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5357 //! @brief Read current value of the SDHC_VENDOR_EXTDMAEN field.
bogdanm 82:6473597d706e 5358 #define BR_SDHC_VENDOR_EXTDMAEN (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXTDMAEN))
bogdanm 82:6473597d706e 5359 #endif
bogdanm 82:6473597d706e 5360
bogdanm 82:6473597d706e 5361 //! @brief Format value for bitfield SDHC_VENDOR_EXTDMAEN.
bogdanm 82:6473597d706e 5362 #define BF_SDHC_VENDOR_EXTDMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_VENDOR_EXTDMAEN), uint32_t) & BM_SDHC_VENDOR_EXTDMAEN)
bogdanm 82:6473597d706e 5363
bogdanm 82:6473597d706e 5364 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5365 //! @brief Set the EXTDMAEN field to a new value.
bogdanm 82:6473597d706e 5366 #define BW_SDHC_VENDOR_EXTDMAEN(v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXTDMAEN) = (v))
bogdanm 82:6473597d706e 5367 #endif
bogdanm 82:6473597d706e 5368 //@}
bogdanm 82:6473597d706e 5369
bogdanm 82:6473597d706e 5370 /*!
bogdanm 82:6473597d706e 5371 * @name Register SDHC_VENDOR, field EXBLKNU[1] (RW)
bogdanm 82:6473597d706e 5372 *
bogdanm 82:6473597d706e 5373 * This bit must be set before S/W issues CMD53 multi-block read with exact
bogdanm 82:6473597d706e 5374 * block number. This bit must not be set if the CMD53 multi-block read is not exact
bogdanm 82:6473597d706e 5375 * block number.
bogdanm 82:6473597d706e 5376 *
bogdanm 82:6473597d706e 5377 * Values:
bogdanm 82:6473597d706e 5378 * - 0 - None exact block read.
bogdanm 82:6473597d706e 5379 * - 1 - Exact block read for SDIO CMD53.
bogdanm 82:6473597d706e 5380 */
bogdanm 82:6473597d706e 5381 //@{
bogdanm 82:6473597d706e 5382 #define BP_SDHC_VENDOR_EXBLKNU (1U) //!< Bit position for SDHC_VENDOR_EXBLKNU.
bogdanm 82:6473597d706e 5383 #define BM_SDHC_VENDOR_EXBLKNU (0x00000002U) //!< Bit mask for SDHC_VENDOR_EXBLKNU.
bogdanm 82:6473597d706e 5384 #define BS_SDHC_VENDOR_EXBLKNU (1U) //!< Bit field size in bits for SDHC_VENDOR_EXBLKNU.
bogdanm 82:6473597d706e 5385
bogdanm 82:6473597d706e 5386 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5387 //! @brief Read current value of the SDHC_VENDOR_EXBLKNU field.
bogdanm 82:6473597d706e 5388 #define BR_SDHC_VENDOR_EXBLKNU (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXBLKNU))
bogdanm 82:6473597d706e 5389 #endif
bogdanm 82:6473597d706e 5390
bogdanm 82:6473597d706e 5391 //! @brief Format value for bitfield SDHC_VENDOR_EXBLKNU.
bogdanm 82:6473597d706e 5392 #define BF_SDHC_VENDOR_EXBLKNU(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_VENDOR_EXBLKNU), uint32_t) & BM_SDHC_VENDOR_EXBLKNU)
bogdanm 82:6473597d706e 5393
bogdanm 82:6473597d706e 5394 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5395 //! @brief Set the EXBLKNU field to a new value.
bogdanm 82:6473597d706e 5396 #define BW_SDHC_VENDOR_EXBLKNU(v) (BITBAND_ACCESS32(HW_SDHC_VENDOR_ADDR, BP_SDHC_VENDOR_EXBLKNU) = (v))
bogdanm 82:6473597d706e 5397 #endif
bogdanm 82:6473597d706e 5398 //@}
bogdanm 82:6473597d706e 5399
bogdanm 82:6473597d706e 5400 /*!
bogdanm 82:6473597d706e 5401 * @name Register SDHC_VENDOR, field INTSTVAL[23:16] (RO)
bogdanm 82:6473597d706e 5402 *
bogdanm 82:6473597d706e 5403 * Internal state value, reflecting the corresponding state value selected by
bogdanm 82:6473597d706e 5404 * Debug Select field. This field is read-only and write to this field does not
bogdanm 82:6473597d706e 5405 * have effect.
bogdanm 82:6473597d706e 5406 */
bogdanm 82:6473597d706e 5407 //@{
bogdanm 82:6473597d706e 5408 #define BP_SDHC_VENDOR_INTSTVAL (16U) //!< Bit position for SDHC_VENDOR_INTSTVAL.
bogdanm 82:6473597d706e 5409 #define BM_SDHC_VENDOR_INTSTVAL (0x00FF0000U) //!< Bit mask for SDHC_VENDOR_INTSTVAL.
bogdanm 82:6473597d706e 5410 #define BS_SDHC_VENDOR_INTSTVAL (8U) //!< Bit field size in bits for SDHC_VENDOR_INTSTVAL.
bogdanm 82:6473597d706e 5411
bogdanm 82:6473597d706e 5412 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5413 //! @brief Read current value of the SDHC_VENDOR_INTSTVAL field.
bogdanm 82:6473597d706e 5414 #define BR_SDHC_VENDOR_INTSTVAL (HW_SDHC_VENDOR.B.INTSTVAL)
bogdanm 82:6473597d706e 5415 #endif
bogdanm 82:6473597d706e 5416 //@}
bogdanm 82:6473597d706e 5417
bogdanm 82:6473597d706e 5418 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5419 // HW_SDHC_MMCBOOT - MMC Boot register
bogdanm 82:6473597d706e 5420 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5421
bogdanm 82:6473597d706e 5422 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5423 /*!
bogdanm 82:6473597d706e 5424 * @brief HW_SDHC_MMCBOOT - MMC Boot register (RW)
bogdanm 82:6473597d706e 5425 *
bogdanm 82:6473597d706e 5426 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 5427 *
bogdanm 82:6473597d706e 5428 * This register contains the MMC fast boot control register.
bogdanm 82:6473597d706e 5429 */
bogdanm 82:6473597d706e 5430 typedef union _hw_sdhc_mmcboot
bogdanm 82:6473597d706e 5431 {
bogdanm 82:6473597d706e 5432 uint32_t U;
bogdanm 82:6473597d706e 5433 struct _hw_sdhc_mmcboot_bitfields
bogdanm 82:6473597d706e 5434 {
bogdanm 82:6473597d706e 5435 uint32_t DTOCVACK : 4; //!< [3:0] Boot ACK Time Out Counter Value
bogdanm 82:6473597d706e 5436 uint32_t BOOTACK : 1; //!< [4] Boot Ack Mode Select
bogdanm 82:6473597d706e 5437 uint32_t BOOTMODE : 1; //!< [5] Boot Mode Select
bogdanm 82:6473597d706e 5438 uint32_t BOOTEN : 1; //!< [6] Boot Mode Enable
bogdanm 82:6473597d706e 5439 uint32_t AUTOSABGEN : 1; //!< [7]
bogdanm 82:6473597d706e 5440 uint32_t RESERVED0 : 8; //!< [15:8]
bogdanm 82:6473597d706e 5441 uint32_t BOOTBLKCNT : 16; //!< [31:16]
bogdanm 82:6473597d706e 5442 } B;
bogdanm 82:6473597d706e 5443 } hw_sdhc_mmcboot_t;
bogdanm 82:6473597d706e 5444 #endif
bogdanm 82:6473597d706e 5445
bogdanm 82:6473597d706e 5446 /*!
bogdanm 82:6473597d706e 5447 * @name Constants and macros for entire SDHC_MMCBOOT register
bogdanm 82:6473597d706e 5448 */
bogdanm 82:6473597d706e 5449 //@{
bogdanm 82:6473597d706e 5450 #define HW_SDHC_MMCBOOT_ADDR (REGS_SDHC_BASE + 0xC4U)
bogdanm 82:6473597d706e 5451
bogdanm 82:6473597d706e 5452 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5453 #define HW_SDHC_MMCBOOT (*(__IO hw_sdhc_mmcboot_t *) HW_SDHC_MMCBOOT_ADDR)
bogdanm 82:6473597d706e 5454 #define HW_SDHC_MMCBOOT_RD() (HW_SDHC_MMCBOOT.U)
bogdanm 82:6473597d706e 5455 #define HW_SDHC_MMCBOOT_WR(v) (HW_SDHC_MMCBOOT.U = (v))
bogdanm 82:6473597d706e 5456 #define HW_SDHC_MMCBOOT_SET(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() | (v)))
bogdanm 82:6473597d706e 5457 #define HW_SDHC_MMCBOOT_CLR(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() & ~(v)))
bogdanm 82:6473597d706e 5458 #define HW_SDHC_MMCBOOT_TOG(v) (HW_SDHC_MMCBOOT_WR(HW_SDHC_MMCBOOT_RD() ^ (v)))
bogdanm 82:6473597d706e 5459 #endif
bogdanm 82:6473597d706e 5460 //@}
bogdanm 82:6473597d706e 5461
bogdanm 82:6473597d706e 5462 /*
bogdanm 82:6473597d706e 5463 * Constants & macros for individual SDHC_MMCBOOT bitfields
bogdanm 82:6473597d706e 5464 */
bogdanm 82:6473597d706e 5465
bogdanm 82:6473597d706e 5466 /*!
bogdanm 82:6473597d706e 5467 * @name Register SDHC_MMCBOOT, field DTOCVACK[3:0] (RW)
bogdanm 82:6473597d706e 5468 *
bogdanm 82:6473597d706e 5469 * Values:
bogdanm 82:6473597d706e 5470 * - 0000 - SDCLK x 2^8
bogdanm 82:6473597d706e 5471 * - 0001 - SDCLK x 2^9
bogdanm 82:6473597d706e 5472 * - 0010 - SDCLK x 2^10
bogdanm 82:6473597d706e 5473 * - 0011 - SDCLK x 2^11
bogdanm 82:6473597d706e 5474 * - 0100 - SDCLK x 2^12
bogdanm 82:6473597d706e 5475 * - 0101 - SDCLK x 2^13
bogdanm 82:6473597d706e 5476 * - 0110 - SDCLK x 2^14
bogdanm 82:6473597d706e 5477 * - 0111 - SDCLK x 2^15
bogdanm 82:6473597d706e 5478 * - 1110 - SDCLK x 2^22
bogdanm 82:6473597d706e 5479 * - 1111 - Reserved
bogdanm 82:6473597d706e 5480 */
bogdanm 82:6473597d706e 5481 //@{
bogdanm 82:6473597d706e 5482 #define BP_SDHC_MMCBOOT_DTOCVACK (0U) //!< Bit position for SDHC_MMCBOOT_DTOCVACK.
bogdanm 82:6473597d706e 5483 #define BM_SDHC_MMCBOOT_DTOCVACK (0x0000000FU) //!< Bit mask for SDHC_MMCBOOT_DTOCVACK.
bogdanm 82:6473597d706e 5484 #define BS_SDHC_MMCBOOT_DTOCVACK (4U) //!< Bit field size in bits for SDHC_MMCBOOT_DTOCVACK.
bogdanm 82:6473597d706e 5485
bogdanm 82:6473597d706e 5486 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5487 //! @brief Read current value of the SDHC_MMCBOOT_DTOCVACK field.
bogdanm 82:6473597d706e 5488 #define BR_SDHC_MMCBOOT_DTOCVACK (HW_SDHC_MMCBOOT.B.DTOCVACK)
bogdanm 82:6473597d706e 5489 #endif
bogdanm 82:6473597d706e 5490
bogdanm 82:6473597d706e 5491 //! @brief Format value for bitfield SDHC_MMCBOOT_DTOCVACK.
bogdanm 82:6473597d706e 5492 #define BF_SDHC_MMCBOOT_DTOCVACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_DTOCVACK), uint32_t) & BM_SDHC_MMCBOOT_DTOCVACK)
bogdanm 82:6473597d706e 5493
bogdanm 82:6473597d706e 5494 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5495 //! @brief Set the DTOCVACK field to a new value.
bogdanm 82:6473597d706e 5496 #define BW_SDHC_MMCBOOT_DTOCVACK(v) (HW_SDHC_MMCBOOT_WR((HW_SDHC_MMCBOOT_RD() & ~BM_SDHC_MMCBOOT_DTOCVACK) | BF_SDHC_MMCBOOT_DTOCVACK(v)))
bogdanm 82:6473597d706e 5497 #endif
bogdanm 82:6473597d706e 5498 //@}
bogdanm 82:6473597d706e 5499
bogdanm 82:6473597d706e 5500 /*!
bogdanm 82:6473597d706e 5501 * @name Register SDHC_MMCBOOT, field BOOTACK[4] (RW)
bogdanm 82:6473597d706e 5502 *
bogdanm 82:6473597d706e 5503 * Values:
bogdanm 82:6473597d706e 5504 * - 0 - No ack.
bogdanm 82:6473597d706e 5505 * - 1 - Ack.
bogdanm 82:6473597d706e 5506 */
bogdanm 82:6473597d706e 5507 //@{
bogdanm 82:6473597d706e 5508 #define BP_SDHC_MMCBOOT_BOOTACK (4U) //!< Bit position for SDHC_MMCBOOT_BOOTACK.
bogdanm 82:6473597d706e 5509 #define BM_SDHC_MMCBOOT_BOOTACK (0x00000010U) //!< Bit mask for SDHC_MMCBOOT_BOOTACK.
bogdanm 82:6473597d706e 5510 #define BS_SDHC_MMCBOOT_BOOTACK (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTACK.
bogdanm 82:6473597d706e 5511
bogdanm 82:6473597d706e 5512 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5513 //! @brief Read current value of the SDHC_MMCBOOT_BOOTACK field.
bogdanm 82:6473597d706e 5514 #define BR_SDHC_MMCBOOT_BOOTACK (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTACK))
bogdanm 82:6473597d706e 5515 #endif
bogdanm 82:6473597d706e 5516
bogdanm 82:6473597d706e 5517 //! @brief Format value for bitfield SDHC_MMCBOOT_BOOTACK.
bogdanm 82:6473597d706e 5518 #define BF_SDHC_MMCBOOT_BOOTACK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTACK), uint32_t) & BM_SDHC_MMCBOOT_BOOTACK)
bogdanm 82:6473597d706e 5519
bogdanm 82:6473597d706e 5520 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5521 //! @brief Set the BOOTACK field to a new value.
bogdanm 82:6473597d706e 5522 #define BW_SDHC_MMCBOOT_BOOTACK(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTACK) = (v))
bogdanm 82:6473597d706e 5523 #endif
bogdanm 82:6473597d706e 5524 //@}
bogdanm 82:6473597d706e 5525
bogdanm 82:6473597d706e 5526 /*!
bogdanm 82:6473597d706e 5527 * @name Register SDHC_MMCBOOT, field BOOTMODE[5] (RW)
bogdanm 82:6473597d706e 5528 *
bogdanm 82:6473597d706e 5529 * Values:
bogdanm 82:6473597d706e 5530 * - 0 - Normal boot.
bogdanm 82:6473597d706e 5531 * - 1 - Alternative boot.
bogdanm 82:6473597d706e 5532 */
bogdanm 82:6473597d706e 5533 //@{
bogdanm 82:6473597d706e 5534 #define BP_SDHC_MMCBOOT_BOOTMODE (5U) //!< Bit position for SDHC_MMCBOOT_BOOTMODE.
bogdanm 82:6473597d706e 5535 #define BM_SDHC_MMCBOOT_BOOTMODE (0x00000020U) //!< Bit mask for SDHC_MMCBOOT_BOOTMODE.
bogdanm 82:6473597d706e 5536 #define BS_SDHC_MMCBOOT_BOOTMODE (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTMODE.
bogdanm 82:6473597d706e 5537
bogdanm 82:6473597d706e 5538 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5539 //! @brief Read current value of the SDHC_MMCBOOT_BOOTMODE field.
bogdanm 82:6473597d706e 5540 #define BR_SDHC_MMCBOOT_BOOTMODE (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTMODE))
bogdanm 82:6473597d706e 5541 #endif
bogdanm 82:6473597d706e 5542
bogdanm 82:6473597d706e 5543 //! @brief Format value for bitfield SDHC_MMCBOOT_BOOTMODE.
bogdanm 82:6473597d706e 5544 #define BF_SDHC_MMCBOOT_BOOTMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTMODE), uint32_t) & BM_SDHC_MMCBOOT_BOOTMODE)
bogdanm 82:6473597d706e 5545
bogdanm 82:6473597d706e 5546 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5547 //! @brief Set the BOOTMODE field to a new value.
bogdanm 82:6473597d706e 5548 #define BW_SDHC_MMCBOOT_BOOTMODE(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTMODE) = (v))
bogdanm 82:6473597d706e 5549 #endif
bogdanm 82:6473597d706e 5550 //@}
bogdanm 82:6473597d706e 5551
bogdanm 82:6473597d706e 5552 /*!
bogdanm 82:6473597d706e 5553 * @name Register SDHC_MMCBOOT, field BOOTEN[6] (RW)
bogdanm 82:6473597d706e 5554 *
bogdanm 82:6473597d706e 5555 * Values:
bogdanm 82:6473597d706e 5556 * - 0 - Fast boot disable.
bogdanm 82:6473597d706e 5557 * - 1 - Fast boot enable.
bogdanm 82:6473597d706e 5558 */
bogdanm 82:6473597d706e 5559 //@{
bogdanm 82:6473597d706e 5560 #define BP_SDHC_MMCBOOT_BOOTEN (6U) //!< Bit position for SDHC_MMCBOOT_BOOTEN.
bogdanm 82:6473597d706e 5561 #define BM_SDHC_MMCBOOT_BOOTEN (0x00000040U) //!< Bit mask for SDHC_MMCBOOT_BOOTEN.
bogdanm 82:6473597d706e 5562 #define BS_SDHC_MMCBOOT_BOOTEN (1U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTEN.
bogdanm 82:6473597d706e 5563
bogdanm 82:6473597d706e 5564 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5565 //! @brief Read current value of the SDHC_MMCBOOT_BOOTEN field.
bogdanm 82:6473597d706e 5566 #define BR_SDHC_MMCBOOT_BOOTEN (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTEN))
bogdanm 82:6473597d706e 5567 #endif
bogdanm 82:6473597d706e 5568
bogdanm 82:6473597d706e 5569 //! @brief Format value for bitfield SDHC_MMCBOOT_BOOTEN.
bogdanm 82:6473597d706e 5570 #define BF_SDHC_MMCBOOT_BOOTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTEN), uint32_t) & BM_SDHC_MMCBOOT_BOOTEN)
bogdanm 82:6473597d706e 5571
bogdanm 82:6473597d706e 5572 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5573 //! @brief Set the BOOTEN field to a new value.
bogdanm 82:6473597d706e 5574 #define BW_SDHC_MMCBOOT_BOOTEN(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_BOOTEN) = (v))
bogdanm 82:6473597d706e 5575 #endif
bogdanm 82:6473597d706e 5576 //@}
bogdanm 82:6473597d706e 5577
bogdanm 82:6473597d706e 5578 /*!
bogdanm 82:6473597d706e 5579 * @name Register SDHC_MMCBOOT, field AUTOSABGEN[7] (RW)
bogdanm 82:6473597d706e 5580 *
bogdanm 82:6473597d706e 5581 * When boot, enable auto stop at block gap function. This function will be
bogdanm 82:6473597d706e 5582 * triggered, and host will stop at block gap when received card block cnt is equal
bogdanm 82:6473597d706e 5583 * to BOOTBLKCNT.
bogdanm 82:6473597d706e 5584 */
bogdanm 82:6473597d706e 5585 //@{
bogdanm 82:6473597d706e 5586 #define BP_SDHC_MMCBOOT_AUTOSABGEN (7U) //!< Bit position for SDHC_MMCBOOT_AUTOSABGEN.
bogdanm 82:6473597d706e 5587 #define BM_SDHC_MMCBOOT_AUTOSABGEN (0x00000080U) //!< Bit mask for SDHC_MMCBOOT_AUTOSABGEN.
bogdanm 82:6473597d706e 5588 #define BS_SDHC_MMCBOOT_AUTOSABGEN (1U) //!< Bit field size in bits for SDHC_MMCBOOT_AUTOSABGEN.
bogdanm 82:6473597d706e 5589
bogdanm 82:6473597d706e 5590 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5591 //! @brief Read current value of the SDHC_MMCBOOT_AUTOSABGEN field.
bogdanm 82:6473597d706e 5592 #define BR_SDHC_MMCBOOT_AUTOSABGEN (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_AUTOSABGEN))
bogdanm 82:6473597d706e 5593 #endif
bogdanm 82:6473597d706e 5594
bogdanm 82:6473597d706e 5595 //! @brief Format value for bitfield SDHC_MMCBOOT_AUTOSABGEN.
bogdanm 82:6473597d706e 5596 #define BF_SDHC_MMCBOOT_AUTOSABGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_AUTOSABGEN), uint32_t) & BM_SDHC_MMCBOOT_AUTOSABGEN)
bogdanm 82:6473597d706e 5597
bogdanm 82:6473597d706e 5598 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5599 //! @brief Set the AUTOSABGEN field to a new value.
bogdanm 82:6473597d706e 5600 #define BW_SDHC_MMCBOOT_AUTOSABGEN(v) (BITBAND_ACCESS32(HW_SDHC_MMCBOOT_ADDR, BP_SDHC_MMCBOOT_AUTOSABGEN) = (v))
bogdanm 82:6473597d706e 5601 #endif
bogdanm 82:6473597d706e 5602 //@}
bogdanm 82:6473597d706e 5603
bogdanm 82:6473597d706e 5604 /*!
bogdanm 82:6473597d706e 5605 * @name Register SDHC_MMCBOOT, field BOOTBLKCNT[31:16] (RW)
bogdanm 82:6473597d706e 5606 *
bogdanm 82:6473597d706e 5607 * Defines the stop at block gap value of automatic mode. When received card
bogdanm 82:6473597d706e 5608 * block cnt is equal to BOOTBLKCNT and AUTOSABGEN is 1, then stop at block gap.
bogdanm 82:6473597d706e 5609 */
bogdanm 82:6473597d706e 5610 //@{
bogdanm 82:6473597d706e 5611 #define BP_SDHC_MMCBOOT_BOOTBLKCNT (16U) //!< Bit position for SDHC_MMCBOOT_BOOTBLKCNT.
bogdanm 82:6473597d706e 5612 #define BM_SDHC_MMCBOOT_BOOTBLKCNT (0xFFFF0000U) //!< Bit mask for SDHC_MMCBOOT_BOOTBLKCNT.
bogdanm 82:6473597d706e 5613 #define BS_SDHC_MMCBOOT_BOOTBLKCNT (16U) //!< Bit field size in bits for SDHC_MMCBOOT_BOOTBLKCNT.
bogdanm 82:6473597d706e 5614
bogdanm 82:6473597d706e 5615 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5616 //! @brief Read current value of the SDHC_MMCBOOT_BOOTBLKCNT field.
bogdanm 82:6473597d706e 5617 #define BR_SDHC_MMCBOOT_BOOTBLKCNT (HW_SDHC_MMCBOOT.B.BOOTBLKCNT)
bogdanm 82:6473597d706e 5618 #endif
bogdanm 82:6473597d706e 5619
bogdanm 82:6473597d706e 5620 //! @brief Format value for bitfield SDHC_MMCBOOT_BOOTBLKCNT.
bogdanm 82:6473597d706e 5621 #define BF_SDHC_MMCBOOT_BOOTBLKCNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_SDHC_MMCBOOT_BOOTBLKCNT), uint32_t) & BM_SDHC_MMCBOOT_BOOTBLKCNT)
bogdanm 82:6473597d706e 5622
bogdanm 82:6473597d706e 5623 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5624 //! @brief Set the BOOTBLKCNT field to a new value.
bogdanm 82:6473597d706e 5625 #define BW_SDHC_MMCBOOT_BOOTBLKCNT(v) (HW_SDHC_MMCBOOT_WR((HW_SDHC_MMCBOOT_RD() & ~BM_SDHC_MMCBOOT_BOOTBLKCNT) | BF_SDHC_MMCBOOT_BOOTBLKCNT(v)))
bogdanm 82:6473597d706e 5626 #endif
bogdanm 82:6473597d706e 5627 //@}
bogdanm 82:6473597d706e 5628
bogdanm 82:6473597d706e 5629 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5630 // HW_SDHC_HOSTVER - Host Controller Version
bogdanm 82:6473597d706e 5631 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5632
bogdanm 82:6473597d706e 5633 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5634 /*!
bogdanm 82:6473597d706e 5635 * @brief HW_SDHC_HOSTVER - Host Controller Version (RO)
bogdanm 82:6473597d706e 5636 *
bogdanm 82:6473597d706e 5637 * Reset value: 0x00001201U
bogdanm 82:6473597d706e 5638 *
bogdanm 82:6473597d706e 5639 * This register contains the vendor host controller version information. All
bogdanm 82:6473597d706e 5640 * bits are read only and will read the same as the power-reset value.
bogdanm 82:6473597d706e 5641 */
bogdanm 82:6473597d706e 5642 typedef union _hw_sdhc_hostver
bogdanm 82:6473597d706e 5643 {
bogdanm 82:6473597d706e 5644 uint32_t U;
bogdanm 82:6473597d706e 5645 struct _hw_sdhc_hostver_bitfields
bogdanm 82:6473597d706e 5646 {
bogdanm 82:6473597d706e 5647 uint32_t SVN : 8; //!< [7:0] Specification Version Number
bogdanm 82:6473597d706e 5648 uint32_t VVN : 8; //!< [15:8] Vendor Version Number
bogdanm 82:6473597d706e 5649 uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm 82:6473597d706e 5650 } B;
bogdanm 82:6473597d706e 5651 } hw_sdhc_hostver_t;
bogdanm 82:6473597d706e 5652 #endif
bogdanm 82:6473597d706e 5653
bogdanm 82:6473597d706e 5654 /*!
bogdanm 82:6473597d706e 5655 * @name Constants and macros for entire SDHC_HOSTVER register
bogdanm 82:6473597d706e 5656 */
bogdanm 82:6473597d706e 5657 //@{
bogdanm 82:6473597d706e 5658 #define HW_SDHC_HOSTVER_ADDR (REGS_SDHC_BASE + 0xFCU)
bogdanm 82:6473597d706e 5659
bogdanm 82:6473597d706e 5660 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5661 #define HW_SDHC_HOSTVER (*(__I hw_sdhc_hostver_t *) HW_SDHC_HOSTVER_ADDR)
bogdanm 82:6473597d706e 5662 #define HW_SDHC_HOSTVER_RD() (HW_SDHC_HOSTVER.U)
bogdanm 82:6473597d706e 5663 #endif
bogdanm 82:6473597d706e 5664 //@}
bogdanm 82:6473597d706e 5665
bogdanm 82:6473597d706e 5666 /*
bogdanm 82:6473597d706e 5667 * Constants & macros for individual SDHC_HOSTVER bitfields
bogdanm 82:6473597d706e 5668 */
bogdanm 82:6473597d706e 5669
bogdanm 82:6473597d706e 5670 /*!
bogdanm 82:6473597d706e 5671 * @name Register SDHC_HOSTVER, field SVN[7:0] (RO)
bogdanm 82:6473597d706e 5672 *
bogdanm 82:6473597d706e 5673 * These status bits indicate the host controller specification version.
bogdanm 82:6473597d706e 5674 *
bogdanm 82:6473597d706e 5675 * Values:
bogdanm 82:6473597d706e 5676 * - 1 - SD host specification version 2.0, supports test event register and
bogdanm 82:6473597d706e 5677 * ADMA.
bogdanm 82:6473597d706e 5678 */
bogdanm 82:6473597d706e 5679 //@{
bogdanm 82:6473597d706e 5680 #define BP_SDHC_HOSTVER_SVN (0U) //!< Bit position for SDHC_HOSTVER_SVN.
bogdanm 82:6473597d706e 5681 #define BM_SDHC_HOSTVER_SVN (0x000000FFU) //!< Bit mask for SDHC_HOSTVER_SVN.
bogdanm 82:6473597d706e 5682 #define BS_SDHC_HOSTVER_SVN (8U) //!< Bit field size in bits for SDHC_HOSTVER_SVN.
bogdanm 82:6473597d706e 5683
bogdanm 82:6473597d706e 5684 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5685 //! @brief Read current value of the SDHC_HOSTVER_SVN field.
bogdanm 82:6473597d706e 5686 #define BR_SDHC_HOSTVER_SVN (HW_SDHC_HOSTVER.B.SVN)
bogdanm 82:6473597d706e 5687 #endif
bogdanm 82:6473597d706e 5688 //@}
bogdanm 82:6473597d706e 5689
bogdanm 82:6473597d706e 5690 /*!
bogdanm 82:6473597d706e 5691 * @name Register SDHC_HOSTVER, field VVN[15:8] (RO)
bogdanm 82:6473597d706e 5692 *
bogdanm 82:6473597d706e 5693 * These status bits are reserved for the vendor version number. The host driver
bogdanm 82:6473597d706e 5694 * shall not use this status.
bogdanm 82:6473597d706e 5695 *
bogdanm 82:6473597d706e 5696 * Values:
bogdanm 82:6473597d706e 5697 * - 0 - Freescale SDHC version 1.0
bogdanm 82:6473597d706e 5698 * - 10000 - Freescale SDHC version 2.0
bogdanm 82:6473597d706e 5699 * - 10001 - Freescale SDHC version 2.1
bogdanm 82:6473597d706e 5700 * - 10010 - Freescale SDHC version 2.2
bogdanm 82:6473597d706e 5701 */
bogdanm 82:6473597d706e 5702 //@{
bogdanm 82:6473597d706e 5703 #define BP_SDHC_HOSTVER_VVN (8U) //!< Bit position for SDHC_HOSTVER_VVN.
bogdanm 82:6473597d706e 5704 #define BM_SDHC_HOSTVER_VVN (0x0000FF00U) //!< Bit mask for SDHC_HOSTVER_VVN.
bogdanm 82:6473597d706e 5705 #define BS_SDHC_HOSTVER_VVN (8U) //!< Bit field size in bits for SDHC_HOSTVER_VVN.
bogdanm 82:6473597d706e 5706
bogdanm 82:6473597d706e 5707 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5708 //! @brief Read current value of the SDHC_HOSTVER_VVN field.
bogdanm 82:6473597d706e 5709 #define BR_SDHC_HOSTVER_VVN (HW_SDHC_HOSTVER.B.VVN)
bogdanm 82:6473597d706e 5710 #endif
bogdanm 82:6473597d706e 5711 //@}
bogdanm 82:6473597d706e 5712
bogdanm 82:6473597d706e 5713 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5714 // hw_sdhc_t - module struct
bogdanm 82:6473597d706e 5715 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 5716 /*!
bogdanm 82:6473597d706e 5717 * @brief All SDHC module registers.
bogdanm 82:6473597d706e 5718 */
bogdanm 82:6473597d706e 5719 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 5720 #pragma pack(1)
bogdanm 82:6473597d706e 5721 typedef struct _hw_sdhc
bogdanm 82:6473597d706e 5722 {
bogdanm 82:6473597d706e 5723 __IO hw_sdhc_dsaddr_t DSADDR; //!< [0x0] DMA System Address register
bogdanm 82:6473597d706e 5724 __IO hw_sdhc_blkattr_t BLKATTR; //!< [0x4] Block Attributes register
bogdanm 82:6473597d706e 5725 __IO hw_sdhc_cmdarg_t CMDARG; //!< [0x8] Command Argument register
bogdanm 82:6473597d706e 5726 __IO hw_sdhc_xfertyp_t XFERTYP; //!< [0xC] Transfer Type register
bogdanm 82:6473597d706e 5727 __I hw_sdhc_cmdrsp0_t CMDRSP0; //!< [0x10] Command Response 0
bogdanm 82:6473597d706e 5728 __I hw_sdhc_cmdrsp1_t CMDRSP1; //!< [0x14] Command Response 1
bogdanm 82:6473597d706e 5729 __I hw_sdhc_cmdrsp2_t CMDRSP2; //!< [0x18] Command Response 2
bogdanm 82:6473597d706e 5730 __I hw_sdhc_cmdrsp3_t CMDRSP3; //!< [0x1C] Command Response 3
bogdanm 82:6473597d706e 5731 __IO hw_sdhc_datport_t DATPORT; //!< [0x20] Buffer Data Port register
bogdanm 82:6473597d706e 5732 __I hw_sdhc_prsstat_t PRSSTAT; //!< [0x24] Present State register
bogdanm 82:6473597d706e 5733 __IO hw_sdhc_proctl_t PROCTL; //!< [0x28] Protocol Control register
bogdanm 82:6473597d706e 5734 __IO hw_sdhc_sysctl_t SYSCTL; //!< [0x2C] System Control register
bogdanm 82:6473597d706e 5735 __IO hw_sdhc_irqstat_t IRQSTAT; //!< [0x30] Interrupt Status register
bogdanm 82:6473597d706e 5736 __IO hw_sdhc_irqstaten_t IRQSTATEN; //!< [0x34] Interrupt Status Enable register
bogdanm 82:6473597d706e 5737 __IO hw_sdhc_irqsigen_t IRQSIGEN; //!< [0x38] Interrupt Signal Enable register
bogdanm 82:6473597d706e 5738 __I hw_sdhc_ac12err_t AC12ERR; //!< [0x3C] Auto CMD12 Error Status Register
bogdanm 82:6473597d706e 5739 __I hw_sdhc_htcapblt_t HTCAPBLT; //!< [0x40] Host Controller Capabilities
bogdanm 82:6473597d706e 5740 __IO hw_sdhc_wml_t WML; //!< [0x44] Watermark Level Register
bogdanm 82:6473597d706e 5741 uint8_t _reserved0[8];
bogdanm 82:6473597d706e 5742 __O hw_sdhc_fevt_t FEVT; //!< [0x50] Force Event register
bogdanm 82:6473597d706e 5743 __I hw_sdhc_admaes_t ADMAES; //!< [0x54] ADMA Error Status register
bogdanm 82:6473597d706e 5744 __IO hw_sdhc_adsaddr_t ADSADDR; //!< [0x58] ADMA System Addressregister
bogdanm 82:6473597d706e 5745 uint8_t _reserved1[100];
bogdanm 82:6473597d706e 5746 __IO hw_sdhc_vendor_t VENDOR; //!< [0xC0] Vendor Specific register
bogdanm 82:6473597d706e 5747 __IO hw_sdhc_mmcboot_t MMCBOOT; //!< [0xC4] MMC Boot register
bogdanm 82:6473597d706e 5748 uint8_t _reserved2[52];
bogdanm 82:6473597d706e 5749 __I hw_sdhc_hostver_t HOSTVER; //!< [0xFC] Host Controller Version
bogdanm 82:6473597d706e 5750 } hw_sdhc_t;
bogdanm 82:6473597d706e 5751 #pragma pack()
bogdanm 82:6473597d706e 5752
bogdanm 82:6473597d706e 5753 //! @brief Macro to access all SDHC registers.
bogdanm 82:6473597d706e 5754 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 5755 //! use the '&' operator, like <code>&HW_SDHC</code>.
bogdanm 82:6473597d706e 5756 #define HW_SDHC (*(hw_sdhc_t *) REGS_SDHC_BASE)
bogdanm 82:6473597d706e 5757 #endif
bogdanm 82:6473597d706e 5758
bogdanm 82:6473597d706e 5759 #endif // __HW_SDHC_REGISTERS_H__
bogdanm 82:6473597d706e 5760 // v22/130726/0.9
bogdanm 82:6473597d706e 5761 // EOF