mbed - mbed(SerialHalfDuplex入り)

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mbed(SerialHalfDuplex入り)

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rtc.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:: bogdanm
Date:: Mon Apr 07 18:28:36 2014 +0100
Revision:: 82:6473597d706e

Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_RTC_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_RTC_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 RTC
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Secure Real Time Clock
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_RTC_TSR - RTC Time Seconds Register
bogdanm	82:6473597d706e	33	* - HW_RTC_TPR - RTC Time Prescaler Register
bogdanm	82:6473597d706e	34	* - HW_RTC_TAR - RTC Time Alarm Register
bogdanm	82:6473597d706e	35	* - HW_RTC_TCR - RTC Time Compensation Register
bogdanm	82:6473597d706e	36	* - HW_RTC_CR - RTC Control Register
bogdanm	82:6473597d706e	37	* - HW_RTC_SR - RTC Status Register
bogdanm	82:6473597d706e	38	* - HW_RTC_LR - RTC Lock Register
bogdanm	82:6473597d706e	39	* - HW_RTC_IER - RTC Interrupt Enable Register
bogdanm	82:6473597d706e	40	* - HW_RTC_WAR - RTC Write Access Register
bogdanm	82:6473597d706e	41	* - HW_RTC_RAR - RTC Read Access Register
bogdanm	82:6473597d706e	42	*
bogdanm	82:6473597d706e	43	* - hw_rtc_t - Struct containing all module registers.
bogdanm	82:6473597d706e	44	*/
bogdanm	82:6473597d706e	45
bogdanm	82:6473597d706e	46	//! @name Module base addresses
bogdanm	82:6473597d706e	47	//@{
bogdanm	82:6473597d706e	48	#ifndef REGS_RTC_BASE
bogdanm	82:6473597d706e	49	#define HW_RTC_INSTANCE_COUNT (1U) //!< Number of instances of the RTC module.
bogdanm	82:6473597d706e	50	#define REGS_RTC_BASE (0x4003D000U) //!< Base address for RTC.
bogdanm	82:6473597d706e	51	#endif
bogdanm	82:6473597d706e	52	//@}
bogdanm	82:6473597d706e	53
bogdanm	82:6473597d706e	54	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	55	// HW_RTC_TSR - RTC Time Seconds Register
bogdanm	82:6473597d706e	56	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	57
bogdanm	82:6473597d706e	58	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	59	/*!
bogdanm	82:6473597d706e	60	* @brief HW_RTC_TSR - RTC Time Seconds Register (RW)
bogdanm	82:6473597d706e	61	*
bogdanm	82:6473597d706e	62	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	63	*/
bogdanm	82:6473597d706e	64	typedef union _hw_rtc_tsr
bogdanm	82:6473597d706e	65	{
bogdanm	82:6473597d706e	66	uint32_t U;
bogdanm	82:6473597d706e	67	struct _hw_rtc_tsr_bitfields
bogdanm	82:6473597d706e	68	{
bogdanm	82:6473597d706e	69	uint32_t TSR : 32; //!< [31:0] Time Seconds Register
bogdanm	82:6473597d706e	70	} B;
bogdanm	82:6473597d706e	71	} hw_rtc_tsr_t;
bogdanm	82:6473597d706e	72	#endif
bogdanm	82:6473597d706e	73
bogdanm	82:6473597d706e	74	/*!
bogdanm	82:6473597d706e	75	* @name Constants and macros for entire RTC_TSR register
bogdanm	82:6473597d706e	76	*/
bogdanm	82:6473597d706e	77	//@{
bogdanm	82:6473597d706e	78	#define HW_RTC_TSR_ADDR (REGS_RTC_BASE + 0x0U)
bogdanm	82:6473597d706e	79
bogdanm	82:6473597d706e	80	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	81	#define HW_RTC_TSR ((__IO hw_rtc_tsr_t ) HW_RTC_TSR_ADDR)
bogdanm	82:6473597d706e	82	#define HW_RTC_TSR_RD() (HW_RTC_TSR.U)
bogdanm	82:6473597d706e	83	#define HW_RTC_TSR_WR(v) (HW_RTC_TSR.U = (v))
bogdanm	82:6473597d706e	84	#define HW_RTC_TSR_SET(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() \| (v)))
bogdanm	82:6473597d706e	85	#define HW_RTC_TSR_CLR(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() & ~(v)))
bogdanm	82:6473597d706e	86	#define HW_RTC_TSR_TOG(v) (HW_RTC_TSR_WR(HW_RTC_TSR_RD() ^ (v)))
bogdanm	82:6473597d706e	87	#endif
bogdanm	82:6473597d706e	88	//@}
bogdanm	82:6473597d706e	89
bogdanm	82:6473597d706e	90	/*
bogdanm	82:6473597d706e	91	* Constants & macros for individual RTC_TSR bitfields
bogdanm	82:6473597d706e	92	*/
bogdanm	82:6473597d706e	93
bogdanm	82:6473597d706e	94	/*!
bogdanm	82:6473597d706e	95	* @name Register RTC_TSR, field TSR[31:0] (RW)
bogdanm	82:6473597d706e	96	*
bogdanm	82:6473597d706e	97	* When the time counter is enabled, the TSR is read only and increments once a
bogdanm	82:6473597d706e	98	* second provided SR[TOF] or SR[TIF] are not set. The time counter will read as
bogdanm	82:6473597d706e	99	* zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the
bogdanm	82:6473597d706e	100	* TSR can be read or written. Writing to the TSR when the time counter is
bogdanm	82:6473597d706e	101	* disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is
bogdanm	82:6473597d706e	102	* supported, but not recommended because TSR will read as zero when SR[TIF] or
bogdanm	82:6473597d706e	103	* SR[TOF] are set (indicating the time is invalid).
bogdanm	82:6473597d706e	104	*/
bogdanm	82:6473597d706e	105	//@{
bogdanm	82:6473597d706e	106	#define BP_RTC_TSR_TSR (0U) //!< Bit position for RTC_TSR_TSR.
bogdanm	82:6473597d706e	107	#define BM_RTC_TSR_TSR (0xFFFFFFFFU) //!< Bit mask for RTC_TSR_TSR.
bogdanm	82:6473597d706e	108	#define BS_RTC_TSR_TSR (32U) //!< Bit field size in bits for RTC_TSR_TSR.
bogdanm	82:6473597d706e	109
bogdanm	82:6473597d706e	110	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	111	//! @brief Read current value of the RTC_TSR_TSR field.
bogdanm	82:6473597d706e	112	#define BR_RTC_TSR_TSR (HW_RTC_TSR.U)
bogdanm	82:6473597d706e	113	#endif
bogdanm	82:6473597d706e	114
bogdanm	82:6473597d706e	115	//! @brief Format value for bitfield RTC_TSR_TSR.
bogdanm	82:6473597d706e	116	#define BF_RTC_TSR_TSR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TSR_TSR), uint32_t) & BM_RTC_TSR_TSR)
bogdanm	82:6473597d706e	117
bogdanm	82:6473597d706e	118	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	119	//! @brief Set the TSR field to a new value.
bogdanm	82:6473597d706e	120	#define BW_RTC_TSR_TSR(v) (HW_RTC_TSR_WR(v))
bogdanm	82:6473597d706e	121	#endif
bogdanm	82:6473597d706e	122	//@}
bogdanm	82:6473597d706e	123
bogdanm	82:6473597d706e	124	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	125	// HW_RTC_TPR - RTC Time Prescaler Register
bogdanm	82:6473597d706e	126	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	127
bogdanm	82:6473597d706e	128	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	129	/*!
bogdanm	82:6473597d706e	130	* @brief HW_RTC_TPR - RTC Time Prescaler Register (RW)
bogdanm	82:6473597d706e	131	*
bogdanm	82:6473597d706e	132	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	133	*/
bogdanm	82:6473597d706e	134	typedef union _hw_rtc_tpr
bogdanm	82:6473597d706e	135	{
bogdanm	82:6473597d706e	136	uint32_t U;
bogdanm	82:6473597d706e	137	struct _hw_rtc_tpr_bitfields
bogdanm	82:6473597d706e	138	{
bogdanm	82:6473597d706e	139	uint32_t TPR : 16; //!< [15:0] Time Prescaler Register
bogdanm	82:6473597d706e	140	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	141	} B;
bogdanm	82:6473597d706e	142	} hw_rtc_tpr_t;
bogdanm	82:6473597d706e	143	#endif
bogdanm	82:6473597d706e	144
bogdanm	82:6473597d706e	145	/*!
bogdanm	82:6473597d706e	146	* @name Constants and macros for entire RTC_TPR register
bogdanm	82:6473597d706e	147	*/
bogdanm	82:6473597d706e	148	//@{
bogdanm	82:6473597d706e	149	#define HW_RTC_TPR_ADDR (REGS_RTC_BASE + 0x4U)
bogdanm	82:6473597d706e	150
bogdanm	82:6473597d706e	151	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	152	#define HW_RTC_TPR ((__IO hw_rtc_tpr_t ) HW_RTC_TPR_ADDR)
bogdanm	82:6473597d706e	153	#define HW_RTC_TPR_RD() (HW_RTC_TPR.U)
bogdanm	82:6473597d706e	154	#define HW_RTC_TPR_WR(v) (HW_RTC_TPR.U = (v))
bogdanm	82:6473597d706e	155	#define HW_RTC_TPR_SET(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() \| (v)))
bogdanm	82:6473597d706e	156	#define HW_RTC_TPR_CLR(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() & ~(v)))
bogdanm	82:6473597d706e	157	#define HW_RTC_TPR_TOG(v) (HW_RTC_TPR_WR(HW_RTC_TPR_RD() ^ (v)))
bogdanm	82:6473597d706e	158	#endif
bogdanm	82:6473597d706e	159	//@}
bogdanm	82:6473597d706e	160
bogdanm	82:6473597d706e	161	/*
bogdanm	82:6473597d706e	162	* Constants & macros for individual RTC_TPR bitfields
bogdanm	82:6473597d706e	163	*/
bogdanm	82:6473597d706e	164
bogdanm	82:6473597d706e	165	/*!
bogdanm	82:6473597d706e	166	* @name Register RTC_TPR, field TPR[15:0] (RW)
bogdanm	82:6473597d706e	167	*
bogdanm	82:6473597d706e	168	* When the time counter is enabled, the TPR is read only and increments every
bogdanm	82:6473597d706e	169	* 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
bogdanm	82:6473597d706e	170	* SR[TIF] are set. When the time counter is disabled, the TPR can be read or
bogdanm	82:6473597d706e	171	* written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
bogdanm	82:6473597d706e	172	* to a logic zero.
bogdanm	82:6473597d706e	173	*/
bogdanm	82:6473597d706e	174	//@{
bogdanm	82:6473597d706e	175	#define BP_RTC_TPR_TPR (0U) //!< Bit position for RTC_TPR_TPR.
bogdanm	82:6473597d706e	176	#define BM_RTC_TPR_TPR (0x0000FFFFU) //!< Bit mask for RTC_TPR_TPR.
bogdanm	82:6473597d706e	177	#define BS_RTC_TPR_TPR (16U) //!< Bit field size in bits for RTC_TPR_TPR.
bogdanm	82:6473597d706e	178
bogdanm	82:6473597d706e	179	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	180	//! @brief Read current value of the RTC_TPR_TPR field.
bogdanm	82:6473597d706e	181	#define BR_RTC_TPR_TPR (HW_RTC_TPR.B.TPR)
bogdanm	82:6473597d706e	182	#endif
bogdanm	82:6473597d706e	183
bogdanm	82:6473597d706e	184	//! @brief Format value for bitfield RTC_TPR_TPR.
bogdanm	82:6473597d706e	185	#define BF_RTC_TPR_TPR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TPR_TPR), uint32_t) & BM_RTC_TPR_TPR)
bogdanm	82:6473597d706e	186
bogdanm	82:6473597d706e	187	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	188	//! @brief Set the TPR field to a new value.
bogdanm	82:6473597d706e	189	#define BW_RTC_TPR_TPR(v) (HW_RTC_TPR_WR((HW_RTC_TPR_RD() & ~BM_RTC_TPR_TPR) \| BF_RTC_TPR_TPR(v)))
bogdanm	82:6473597d706e	190	#endif
bogdanm	82:6473597d706e	191	//@}
bogdanm	82:6473597d706e	192
bogdanm	82:6473597d706e	193	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	194	// HW_RTC_TAR - RTC Time Alarm Register
bogdanm	82:6473597d706e	195	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	196
bogdanm	82:6473597d706e	197	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	198	/*!
bogdanm	82:6473597d706e	199	* @brief HW_RTC_TAR - RTC Time Alarm Register (RW)
bogdanm	82:6473597d706e	200	*
bogdanm	82:6473597d706e	201	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	202	*/
bogdanm	82:6473597d706e	203	typedef union _hw_rtc_tar
bogdanm	82:6473597d706e	204	{
bogdanm	82:6473597d706e	205	uint32_t U;
bogdanm	82:6473597d706e	206	struct _hw_rtc_tar_bitfields
bogdanm	82:6473597d706e	207	{
bogdanm	82:6473597d706e	208	uint32_t TAR : 32; //!< [31:0] Time Alarm Register
bogdanm	82:6473597d706e	209	} B;
bogdanm	82:6473597d706e	210	} hw_rtc_tar_t;
bogdanm	82:6473597d706e	211	#endif
bogdanm	82:6473597d706e	212
bogdanm	82:6473597d706e	213	/*!
bogdanm	82:6473597d706e	214	* @name Constants and macros for entire RTC_TAR register
bogdanm	82:6473597d706e	215	*/
bogdanm	82:6473597d706e	216	//@{
bogdanm	82:6473597d706e	217	#define HW_RTC_TAR_ADDR (REGS_RTC_BASE + 0x8U)
bogdanm	82:6473597d706e	218
bogdanm	82:6473597d706e	219	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	220	#define HW_RTC_TAR ((__IO hw_rtc_tar_t ) HW_RTC_TAR_ADDR)
bogdanm	82:6473597d706e	221	#define HW_RTC_TAR_RD() (HW_RTC_TAR.U)
bogdanm	82:6473597d706e	222	#define HW_RTC_TAR_WR(v) (HW_RTC_TAR.U = (v))
bogdanm	82:6473597d706e	223	#define HW_RTC_TAR_SET(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() \| (v)))
bogdanm	82:6473597d706e	224	#define HW_RTC_TAR_CLR(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() & ~(v)))
bogdanm	82:6473597d706e	225	#define HW_RTC_TAR_TOG(v) (HW_RTC_TAR_WR(HW_RTC_TAR_RD() ^ (v)))
bogdanm	82:6473597d706e	226	#endif
bogdanm	82:6473597d706e	227	//@}
bogdanm	82:6473597d706e	228
bogdanm	82:6473597d706e	229	/*
bogdanm	82:6473597d706e	230	* Constants & macros for individual RTC_TAR bitfields
bogdanm	82:6473597d706e	231	*/
bogdanm	82:6473597d706e	232
bogdanm	82:6473597d706e	233	/*!
bogdanm	82:6473597d706e	234	* @name Register RTC_TAR, field TAR[31:0] (RW)
bogdanm	82:6473597d706e	235	*
bogdanm	82:6473597d706e	236	* When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
bogdanm	82:6473597d706e	237	* equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the
bogdanm	82:6473597d706e	238	* SR[TAF].
bogdanm	82:6473597d706e	239	*/
bogdanm	82:6473597d706e	240	//@{
bogdanm	82:6473597d706e	241	#define BP_RTC_TAR_TAR (0U) //!< Bit position for RTC_TAR_TAR.
bogdanm	82:6473597d706e	242	#define BM_RTC_TAR_TAR (0xFFFFFFFFU) //!< Bit mask for RTC_TAR_TAR.
bogdanm	82:6473597d706e	243	#define BS_RTC_TAR_TAR (32U) //!< Bit field size in bits for RTC_TAR_TAR.
bogdanm	82:6473597d706e	244
bogdanm	82:6473597d706e	245	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	246	//! @brief Read current value of the RTC_TAR_TAR field.
bogdanm	82:6473597d706e	247	#define BR_RTC_TAR_TAR (HW_RTC_TAR.U)
bogdanm	82:6473597d706e	248	#endif
bogdanm	82:6473597d706e	249
bogdanm	82:6473597d706e	250	//! @brief Format value for bitfield RTC_TAR_TAR.
bogdanm	82:6473597d706e	251	#define BF_RTC_TAR_TAR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TAR_TAR), uint32_t) & BM_RTC_TAR_TAR)
bogdanm	82:6473597d706e	252
bogdanm	82:6473597d706e	253	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	254	//! @brief Set the TAR field to a new value.
bogdanm	82:6473597d706e	255	#define BW_RTC_TAR_TAR(v) (HW_RTC_TAR_WR(v))
bogdanm	82:6473597d706e	256	#endif
bogdanm	82:6473597d706e	257	//@}
bogdanm	82:6473597d706e	258
bogdanm	82:6473597d706e	259	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	260	// HW_RTC_TCR - RTC Time Compensation Register
bogdanm	82:6473597d706e	261	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	262
bogdanm	82:6473597d706e	263	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	264	/*!
bogdanm	82:6473597d706e	265	* @brief HW_RTC_TCR - RTC Time Compensation Register (RW)
bogdanm	82:6473597d706e	266	*
bogdanm	82:6473597d706e	267	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	268	*/
bogdanm	82:6473597d706e	269	typedef union _hw_rtc_tcr
bogdanm	82:6473597d706e	270	{
bogdanm	82:6473597d706e	271	uint32_t U;
bogdanm	82:6473597d706e	272	struct _hw_rtc_tcr_bitfields
bogdanm	82:6473597d706e	273	{
bogdanm	82:6473597d706e	274	uint32_t TCR : 8; //!< [7:0] Time Compensation Register
bogdanm	82:6473597d706e	275	uint32_t CIR : 8; //!< [15:8] Compensation Interval Register
bogdanm	82:6473597d706e	276	uint32_t TCV : 8; //!< [23:16] Time Compensation Value
bogdanm	82:6473597d706e	277	uint32_t CIC : 8; //!< [31:24] Compensation Interval Counter
bogdanm	82:6473597d706e	278	} B;
bogdanm	82:6473597d706e	279	} hw_rtc_tcr_t;
bogdanm	82:6473597d706e	280	#endif
bogdanm	82:6473597d706e	281
bogdanm	82:6473597d706e	282	/*!
bogdanm	82:6473597d706e	283	* @name Constants and macros for entire RTC_TCR register
bogdanm	82:6473597d706e	284	*/
bogdanm	82:6473597d706e	285	//@{
bogdanm	82:6473597d706e	286	#define HW_RTC_TCR_ADDR (REGS_RTC_BASE + 0xCU)
bogdanm	82:6473597d706e	287
bogdanm	82:6473597d706e	288	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	289	#define HW_RTC_TCR ((__IO hw_rtc_tcr_t ) HW_RTC_TCR_ADDR)
bogdanm	82:6473597d706e	290	#define HW_RTC_TCR_RD() (HW_RTC_TCR.U)
bogdanm	82:6473597d706e	291	#define HW_RTC_TCR_WR(v) (HW_RTC_TCR.U = (v))
bogdanm	82:6473597d706e	292	#define HW_RTC_TCR_SET(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() \| (v)))
bogdanm	82:6473597d706e	293	#define HW_RTC_TCR_CLR(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() & ~(v)))
bogdanm	82:6473597d706e	294	#define HW_RTC_TCR_TOG(v) (HW_RTC_TCR_WR(HW_RTC_TCR_RD() ^ (v)))
bogdanm	82:6473597d706e	295	#endif
bogdanm	82:6473597d706e	296	//@}
bogdanm	82:6473597d706e	297
bogdanm	82:6473597d706e	298	/*
bogdanm	82:6473597d706e	299	* Constants & macros for individual RTC_TCR bitfields
bogdanm	82:6473597d706e	300	*/
bogdanm	82:6473597d706e	301
bogdanm	82:6473597d706e	302	/*!
bogdanm	82:6473597d706e	303	* @name Register RTC_TCR, field TCR[7:0] (RW)
bogdanm	82:6473597d706e	304	*
bogdanm	82:6473597d706e	305	* Configures the number of 32.768 kHz clock cycles in each second. This
bogdanm	82:6473597d706e	306	* register is double buffered and writes do not take affect until the end of the
bogdanm	82:6473597d706e	307	* current compensation interval.
bogdanm	82:6473597d706e	308	*
bogdanm	82:6473597d706e	309	* Values:
bogdanm	82:6473597d706e	310	* - 10000000 - Time Prescaler Register overflows every 32896 clock cycles.
bogdanm	82:6473597d706e	311	* - 11111111 - Time Prescaler Register overflows every 32769 clock cycles.
bogdanm	82:6473597d706e	312	* - 0 - Time Prescaler Register overflows every 32768 clock cycles.
bogdanm	82:6473597d706e	313	* - 1 - Time Prescaler Register overflows every 32767 clock cycles.
bogdanm	82:6473597d706e	314	* - 1111111 - Time Prescaler Register overflows every 32641 clock cycles.
bogdanm	82:6473597d706e	315	*/
bogdanm	82:6473597d706e	316	//@{
bogdanm	82:6473597d706e	317	#define BP_RTC_TCR_TCR (0U) //!< Bit position for RTC_TCR_TCR.
bogdanm	82:6473597d706e	318	#define BM_RTC_TCR_TCR (0x000000FFU) //!< Bit mask for RTC_TCR_TCR.
bogdanm	82:6473597d706e	319	#define BS_RTC_TCR_TCR (8U) //!< Bit field size in bits for RTC_TCR_TCR.
bogdanm	82:6473597d706e	320
bogdanm	82:6473597d706e	321	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	322	//! @brief Read current value of the RTC_TCR_TCR field.
bogdanm	82:6473597d706e	323	#define BR_RTC_TCR_TCR (HW_RTC_TCR.B.TCR)
bogdanm	82:6473597d706e	324	#endif
bogdanm	82:6473597d706e	325
bogdanm	82:6473597d706e	326	//! @brief Format value for bitfield RTC_TCR_TCR.
bogdanm	82:6473597d706e	327	#define BF_RTC_TCR_TCR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TCR_TCR), uint32_t) & BM_RTC_TCR_TCR)
bogdanm	82:6473597d706e	328
bogdanm	82:6473597d706e	329	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	330	//! @brief Set the TCR field to a new value.
bogdanm	82:6473597d706e	331	#define BW_RTC_TCR_TCR(v) (HW_RTC_TCR_WR((HW_RTC_TCR_RD() & ~BM_RTC_TCR_TCR) \| BF_RTC_TCR_TCR(v)))
bogdanm	82:6473597d706e	332	#endif
bogdanm	82:6473597d706e	333	//@}
bogdanm	82:6473597d706e	334
bogdanm	82:6473597d706e	335	/*!
bogdanm	82:6473597d706e	336	* @name Register RTC_TCR, field CIR[15:8] (RW)
bogdanm	82:6473597d706e	337	*
bogdanm	82:6473597d706e	338	* Configures the compensation interval in seconds from 1 to 256 to control how
bogdanm	82:6473597d706e	339	* frequently the TCR should adjust the number of 32.768 kHz cycles in each
bogdanm	82:6473597d706e	340	* second. The value written should be one less than the number of seconds. For
bogdanm	82:6473597d706e	341	* example, write zero to configure for a compensation interval of one second. This
bogdanm	82:6473597d706e	342	* register is double buffered and writes do not take affect until the end of the
bogdanm	82:6473597d706e	343	* current compensation interval.
bogdanm	82:6473597d706e	344	*/
bogdanm	82:6473597d706e	345	//@{
bogdanm	82:6473597d706e	346	#define BP_RTC_TCR_CIR (8U) //!< Bit position for RTC_TCR_CIR.
bogdanm	82:6473597d706e	347	#define BM_RTC_TCR_CIR (0x0000FF00U) //!< Bit mask for RTC_TCR_CIR.
bogdanm	82:6473597d706e	348	#define BS_RTC_TCR_CIR (8U) //!< Bit field size in bits for RTC_TCR_CIR.
bogdanm	82:6473597d706e	349
bogdanm	82:6473597d706e	350	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	351	//! @brief Read current value of the RTC_TCR_CIR field.
bogdanm	82:6473597d706e	352	#define BR_RTC_TCR_CIR (HW_RTC_TCR.B.CIR)
bogdanm	82:6473597d706e	353	#endif
bogdanm	82:6473597d706e	354
bogdanm	82:6473597d706e	355	//! @brief Format value for bitfield RTC_TCR_CIR.
bogdanm	82:6473597d706e	356	#define BF_RTC_TCR_CIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_TCR_CIR), uint32_t) & BM_RTC_TCR_CIR)
bogdanm	82:6473597d706e	357
bogdanm	82:6473597d706e	358	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	359	//! @brief Set the CIR field to a new value.
bogdanm	82:6473597d706e	360	#define BW_RTC_TCR_CIR(v) (HW_RTC_TCR_WR((HW_RTC_TCR_RD() & ~BM_RTC_TCR_CIR) \| BF_RTC_TCR_CIR(v)))
bogdanm	82:6473597d706e	361	#endif
bogdanm	82:6473597d706e	362	//@}
bogdanm	82:6473597d706e	363
bogdanm	82:6473597d706e	364	/*!
bogdanm	82:6473597d706e	365	* @name Register RTC_TCR, field TCV[23:16] (RO)
bogdanm	82:6473597d706e	366	*
bogdanm	82:6473597d706e	367	* Current value used by the compensation logic for the present second interval.
bogdanm	82:6473597d706e	368	* Updated once a second if the CIC equals 0 with the contents of the TCR field.
bogdanm	82:6473597d706e	369	* If the CIC does not equal zero then it is loaded with zero (compensation is
bogdanm	82:6473597d706e	370	* not enabled for that second increment).
bogdanm	82:6473597d706e	371	*/
bogdanm	82:6473597d706e	372	//@{
bogdanm	82:6473597d706e	373	#define BP_RTC_TCR_TCV (16U) //!< Bit position for RTC_TCR_TCV.
bogdanm	82:6473597d706e	374	#define BM_RTC_TCR_TCV (0x00FF0000U) //!< Bit mask for RTC_TCR_TCV.
bogdanm	82:6473597d706e	375	#define BS_RTC_TCR_TCV (8U) //!< Bit field size in bits for RTC_TCR_TCV.
bogdanm	82:6473597d706e	376
bogdanm	82:6473597d706e	377	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	378	//! @brief Read current value of the RTC_TCR_TCV field.
bogdanm	82:6473597d706e	379	#define BR_RTC_TCR_TCV (HW_RTC_TCR.B.TCV)
bogdanm	82:6473597d706e	380	#endif
bogdanm	82:6473597d706e	381	//@}
bogdanm	82:6473597d706e	382
bogdanm	82:6473597d706e	383	/*!
bogdanm	82:6473597d706e	384	* @name Register RTC_TCR, field CIC[31:24] (RO)
bogdanm	82:6473597d706e	385	*
bogdanm	82:6473597d706e	386	* Current value of the compensation interval counter. If the compensation
bogdanm	82:6473597d706e	387	* interval counter equals zero then it is loaded with the contents of the CIR. If the
bogdanm	82:6473597d706e	388	* CIC does not equal zero then it is decremented once a second.
bogdanm	82:6473597d706e	389	*/
bogdanm	82:6473597d706e	390	//@{
bogdanm	82:6473597d706e	391	#define BP_RTC_TCR_CIC (24U) //!< Bit position for RTC_TCR_CIC.
bogdanm	82:6473597d706e	392	#define BM_RTC_TCR_CIC (0xFF000000U) //!< Bit mask for RTC_TCR_CIC.
bogdanm	82:6473597d706e	393	#define BS_RTC_TCR_CIC (8U) //!< Bit field size in bits for RTC_TCR_CIC.
bogdanm	82:6473597d706e	394
bogdanm	82:6473597d706e	395	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	396	//! @brief Read current value of the RTC_TCR_CIC field.
bogdanm	82:6473597d706e	397	#define BR_RTC_TCR_CIC (HW_RTC_TCR.B.CIC)
bogdanm	82:6473597d706e	398	#endif
bogdanm	82:6473597d706e	399	//@}
bogdanm	82:6473597d706e	400
bogdanm	82:6473597d706e	401	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	402	// HW_RTC_CR - RTC Control Register
bogdanm	82:6473597d706e	403	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	404
bogdanm	82:6473597d706e	405	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	406	/*!
bogdanm	82:6473597d706e	407	* @brief HW_RTC_CR - RTC Control Register (RW)
bogdanm	82:6473597d706e	408	*
bogdanm	82:6473597d706e	409	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	410	*/
bogdanm	82:6473597d706e	411	typedef union _hw_rtc_cr
bogdanm	82:6473597d706e	412	{
bogdanm	82:6473597d706e	413	uint32_t U;
bogdanm	82:6473597d706e	414	struct _hw_rtc_cr_bitfields
bogdanm	82:6473597d706e	415	{
bogdanm	82:6473597d706e	416	uint32_t SWR : 1; //!< [0] Software Reset
bogdanm	82:6473597d706e	417	uint32_t WPE : 1; //!< [1] Wakeup Pin Enable
bogdanm	82:6473597d706e	418	uint32_t SUP : 1; //!< [2] Supervisor Access
bogdanm	82:6473597d706e	419	uint32_t UM : 1; //!< [3] Update Mode
bogdanm	82:6473597d706e	420	uint32_t WPS : 1; //!< [4] Wakeup Pin Select
bogdanm	82:6473597d706e	421	uint32_t RESERVED0 : 3; //!< [7:5]
bogdanm	82:6473597d706e	422	uint32_t OSCE : 1; //!< [8] Oscillator Enable
bogdanm	82:6473597d706e	423	uint32_t CLKO : 1; //!< [9] Clock Output
bogdanm	82:6473597d706e	424	uint32_t SC16P : 1; //!< [10] Oscillator 16pF Load Configure
bogdanm	82:6473597d706e	425	uint32_t SC8P : 1; //!< [11] Oscillator 8pF Load Configure
bogdanm	82:6473597d706e	426	uint32_t SC4P : 1; //!< [12] Oscillator 4pF Load Configure
bogdanm	82:6473597d706e	427	uint32_t SC2P : 1; //!< [13] Oscillator 2pF Load Configure
bogdanm	82:6473597d706e	428	uint32_t RESERVED1 : 18; //!< [31:14]
bogdanm	82:6473597d706e	429	} B;
bogdanm	82:6473597d706e	430	} hw_rtc_cr_t;
bogdanm	82:6473597d706e	431	#endif
bogdanm	82:6473597d706e	432
bogdanm	82:6473597d706e	433	/*!
bogdanm	82:6473597d706e	434	* @name Constants and macros for entire RTC_CR register
bogdanm	82:6473597d706e	435	*/
bogdanm	82:6473597d706e	436	//@{
bogdanm	82:6473597d706e	437	#define HW_RTC_CR_ADDR (REGS_RTC_BASE + 0x10U)
bogdanm	82:6473597d706e	438
bogdanm	82:6473597d706e	439	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	440	#define HW_RTC_CR ((__IO hw_rtc_cr_t ) HW_RTC_CR_ADDR)
bogdanm	82:6473597d706e	441	#define HW_RTC_CR_RD() (HW_RTC_CR.U)
bogdanm	82:6473597d706e	442	#define HW_RTC_CR_WR(v) (HW_RTC_CR.U = (v))
bogdanm	82:6473597d706e	443	#define HW_RTC_CR_SET(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() \| (v)))
bogdanm	82:6473597d706e	444	#define HW_RTC_CR_CLR(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() & ~(v)))
bogdanm	82:6473597d706e	445	#define HW_RTC_CR_TOG(v) (HW_RTC_CR_WR(HW_RTC_CR_RD() ^ (v)))
bogdanm	82:6473597d706e	446	#endif
bogdanm	82:6473597d706e	447	//@}
bogdanm	82:6473597d706e	448
bogdanm	82:6473597d706e	449	/*
bogdanm	82:6473597d706e	450	* Constants & macros for individual RTC_CR bitfields
bogdanm	82:6473597d706e	451	*/
bogdanm	82:6473597d706e	452
bogdanm	82:6473597d706e	453	/*!
bogdanm	82:6473597d706e	454	* @name Register RTC_CR, field SWR[0] (RW)
bogdanm	82:6473597d706e	455	*
bogdanm	82:6473597d706e	456	* Values:
bogdanm	82:6473597d706e	457	* - 0 - No effect.
bogdanm	82:6473597d706e	458	* - 1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
bogdanm	82:6473597d706e	459	* RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
bogdanm	82:6473597d706e	460	* explicitly clearing it.
bogdanm	82:6473597d706e	461	*/
bogdanm	82:6473597d706e	462	//@{
bogdanm	82:6473597d706e	463	#define BP_RTC_CR_SWR (0U) //!< Bit position for RTC_CR_SWR.
bogdanm	82:6473597d706e	464	#define BM_RTC_CR_SWR (0x00000001U) //!< Bit mask for RTC_CR_SWR.
bogdanm	82:6473597d706e	465	#define BS_RTC_CR_SWR (1U) //!< Bit field size in bits for RTC_CR_SWR.
bogdanm	82:6473597d706e	466
bogdanm	82:6473597d706e	467	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	468	//! @brief Read current value of the RTC_CR_SWR field.
bogdanm	82:6473597d706e	469	#define BR_RTC_CR_SWR (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SWR))
bogdanm	82:6473597d706e	470	#endif
bogdanm	82:6473597d706e	471
bogdanm	82:6473597d706e	472	//! @brief Format value for bitfield RTC_CR_SWR.
bogdanm	82:6473597d706e	473	#define BF_RTC_CR_SWR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SWR), uint32_t) & BM_RTC_CR_SWR)
bogdanm	82:6473597d706e	474
bogdanm	82:6473597d706e	475	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	476	//! @brief Set the SWR field to a new value.
bogdanm	82:6473597d706e	477	#define BW_RTC_CR_SWR(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SWR) = (v))
bogdanm	82:6473597d706e	478	#endif
bogdanm	82:6473597d706e	479	//@}
bogdanm	82:6473597d706e	480
bogdanm	82:6473597d706e	481	/*!
bogdanm	82:6473597d706e	482	* @name Register RTC_CR, field WPE[1] (RW)
bogdanm	82:6473597d706e	483	*
bogdanm	82:6473597d706e	484	* The wakeup pin is optional and not available on all devices.
bogdanm	82:6473597d706e	485	*
bogdanm	82:6473597d706e	486	* Values:
bogdanm	82:6473597d706e	487	* - 0 - Wakeup pin is disabled.
bogdanm	82:6473597d706e	488	* - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
bogdanm	82:6473597d706e	489	* asserts or the wakeup pin is turned on.
bogdanm	82:6473597d706e	490	*/
bogdanm	82:6473597d706e	491	//@{
bogdanm	82:6473597d706e	492	#define BP_RTC_CR_WPE (1U) //!< Bit position for RTC_CR_WPE.
bogdanm	82:6473597d706e	493	#define BM_RTC_CR_WPE (0x00000002U) //!< Bit mask for RTC_CR_WPE.
bogdanm	82:6473597d706e	494	#define BS_RTC_CR_WPE (1U) //!< Bit field size in bits for RTC_CR_WPE.
bogdanm	82:6473597d706e	495
bogdanm	82:6473597d706e	496	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	497	//! @brief Read current value of the RTC_CR_WPE field.
bogdanm	82:6473597d706e	498	#define BR_RTC_CR_WPE (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPE))
bogdanm	82:6473597d706e	499	#endif
bogdanm	82:6473597d706e	500
bogdanm	82:6473597d706e	501	//! @brief Format value for bitfield RTC_CR_WPE.
bogdanm	82:6473597d706e	502	#define BF_RTC_CR_WPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_WPE), uint32_t) & BM_RTC_CR_WPE)
bogdanm	82:6473597d706e	503
bogdanm	82:6473597d706e	504	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	505	//! @brief Set the WPE field to a new value.
bogdanm	82:6473597d706e	506	#define BW_RTC_CR_WPE(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPE) = (v))
bogdanm	82:6473597d706e	507	#endif
bogdanm	82:6473597d706e	508	//@}
bogdanm	82:6473597d706e	509
bogdanm	82:6473597d706e	510	/*!
bogdanm	82:6473597d706e	511	* @name Register RTC_CR, field SUP[2] (RW)
bogdanm	82:6473597d706e	512	*
bogdanm	82:6473597d706e	513	* Values:
bogdanm	82:6473597d706e	514	* - 0 - Non-supervisor mode write accesses are not supported and generate a bus
bogdanm	82:6473597d706e	515	* error.
bogdanm	82:6473597d706e	516	* - 1 - Non-supervisor mode write accesses are supported.
bogdanm	82:6473597d706e	517	*/
bogdanm	82:6473597d706e	518	//@{
bogdanm	82:6473597d706e	519	#define BP_RTC_CR_SUP (2U) //!< Bit position for RTC_CR_SUP.
bogdanm	82:6473597d706e	520	#define BM_RTC_CR_SUP (0x00000004U) //!< Bit mask for RTC_CR_SUP.
bogdanm	82:6473597d706e	521	#define BS_RTC_CR_SUP (1U) //!< Bit field size in bits for RTC_CR_SUP.
bogdanm	82:6473597d706e	522
bogdanm	82:6473597d706e	523	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	524	//! @brief Read current value of the RTC_CR_SUP field.
bogdanm	82:6473597d706e	525	#define BR_RTC_CR_SUP (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SUP))
bogdanm	82:6473597d706e	526	#endif
bogdanm	82:6473597d706e	527
bogdanm	82:6473597d706e	528	//! @brief Format value for bitfield RTC_CR_SUP.
bogdanm	82:6473597d706e	529	#define BF_RTC_CR_SUP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SUP), uint32_t) & BM_RTC_CR_SUP)
bogdanm	82:6473597d706e	530
bogdanm	82:6473597d706e	531	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	532	//! @brief Set the SUP field to a new value.
bogdanm	82:6473597d706e	533	#define BW_RTC_CR_SUP(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SUP) = (v))
bogdanm	82:6473597d706e	534	#endif
bogdanm	82:6473597d706e	535	//@}
bogdanm	82:6473597d706e	536
bogdanm	82:6473597d706e	537	/*!
bogdanm	82:6473597d706e	538	* @name Register RTC_CR, field UM[3] (RW)
bogdanm	82:6473597d706e	539	*
bogdanm	82:6473597d706e	540	* Allows SR[TCE] to be written even when the Status Register is locked. When
bogdanm	82:6473597d706e	541	* set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
bogdanm	82:6473597d706e	542	* the SR[TCE] is clear.
bogdanm	82:6473597d706e	543	*
bogdanm	82:6473597d706e	544	* Values:
bogdanm	82:6473597d706e	545	* - 0 - Registers cannot be written when locked.
bogdanm	82:6473597d706e	546	* - 1 - Registers can be written when locked under limited conditions.
bogdanm	82:6473597d706e	547	*/
bogdanm	82:6473597d706e	548	//@{
bogdanm	82:6473597d706e	549	#define BP_RTC_CR_UM (3U) //!< Bit position for RTC_CR_UM.
bogdanm	82:6473597d706e	550	#define BM_RTC_CR_UM (0x00000008U) //!< Bit mask for RTC_CR_UM.
bogdanm	82:6473597d706e	551	#define BS_RTC_CR_UM (1U) //!< Bit field size in bits for RTC_CR_UM.
bogdanm	82:6473597d706e	552
bogdanm	82:6473597d706e	553	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	554	//! @brief Read current value of the RTC_CR_UM field.
bogdanm	82:6473597d706e	555	#define BR_RTC_CR_UM (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_UM))
bogdanm	82:6473597d706e	556	#endif
bogdanm	82:6473597d706e	557
bogdanm	82:6473597d706e	558	//! @brief Format value for bitfield RTC_CR_UM.
bogdanm	82:6473597d706e	559	#define BF_RTC_CR_UM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_UM), uint32_t) & BM_RTC_CR_UM)
bogdanm	82:6473597d706e	560
bogdanm	82:6473597d706e	561	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	562	//! @brief Set the UM field to a new value.
bogdanm	82:6473597d706e	563	#define BW_RTC_CR_UM(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_UM) = (v))
bogdanm	82:6473597d706e	564	#endif
bogdanm	82:6473597d706e	565	//@}
bogdanm	82:6473597d706e	566
bogdanm	82:6473597d706e	567	/*!
bogdanm	82:6473597d706e	568	* @name Register RTC_CR, field WPS[4] (RW)
bogdanm	82:6473597d706e	569	*
bogdanm	82:6473597d706e	570	* The wakeup pin is optional and not available on all devices.
bogdanm	82:6473597d706e	571	*
bogdanm	82:6473597d706e	572	* Values:
bogdanm	82:6473597d706e	573	* - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
bogdanm	82:6473597d706e	574	* asserts or the wakeup pin is turned on.
bogdanm	82:6473597d706e	575	* - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin
bogdanm	82:6473597d706e	576	* is turned on and the 32kHz clock is output to other peripherals.
bogdanm	82:6473597d706e	577	*/
bogdanm	82:6473597d706e	578	//@{
bogdanm	82:6473597d706e	579	#define BP_RTC_CR_WPS (4U) //!< Bit position for RTC_CR_WPS.
bogdanm	82:6473597d706e	580	#define BM_RTC_CR_WPS (0x00000010U) //!< Bit mask for RTC_CR_WPS.
bogdanm	82:6473597d706e	581	#define BS_RTC_CR_WPS (1U) //!< Bit field size in bits for RTC_CR_WPS.
bogdanm	82:6473597d706e	582
bogdanm	82:6473597d706e	583	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	584	//! @brief Read current value of the RTC_CR_WPS field.
bogdanm	82:6473597d706e	585	#define BR_RTC_CR_WPS (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPS))
bogdanm	82:6473597d706e	586	#endif
bogdanm	82:6473597d706e	587
bogdanm	82:6473597d706e	588	//! @brief Format value for bitfield RTC_CR_WPS.
bogdanm	82:6473597d706e	589	#define BF_RTC_CR_WPS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_WPS), uint32_t) & BM_RTC_CR_WPS)
bogdanm	82:6473597d706e	590
bogdanm	82:6473597d706e	591	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	592	//! @brief Set the WPS field to a new value.
bogdanm	82:6473597d706e	593	#define BW_RTC_CR_WPS(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_WPS) = (v))
bogdanm	82:6473597d706e	594	#endif
bogdanm	82:6473597d706e	595	//@}
bogdanm	82:6473597d706e	596
bogdanm	82:6473597d706e	597	/*!
bogdanm	82:6473597d706e	598	* @name Register RTC_CR, field OSCE[8] (RW)
bogdanm	82:6473597d706e	599	*
bogdanm	82:6473597d706e	600	* Values:
bogdanm	82:6473597d706e	601	* - 0 - 32.768 kHz oscillator is disabled.
bogdanm	82:6473597d706e	602	* - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
bogdanm	82:6473597d706e	603	* oscillator startup time before enabling the time counter to allow the 32.768
bogdanm	82:6473597d706e	604	* kHz clock time to stabilize.
bogdanm	82:6473597d706e	605	*/
bogdanm	82:6473597d706e	606	//@{
bogdanm	82:6473597d706e	607	#define BP_RTC_CR_OSCE (8U) //!< Bit position for RTC_CR_OSCE.
bogdanm	82:6473597d706e	608	#define BM_RTC_CR_OSCE (0x00000100U) //!< Bit mask for RTC_CR_OSCE.
bogdanm	82:6473597d706e	609	#define BS_RTC_CR_OSCE (1U) //!< Bit field size in bits for RTC_CR_OSCE.
bogdanm	82:6473597d706e	610
bogdanm	82:6473597d706e	611	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	612	//! @brief Read current value of the RTC_CR_OSCE field.
bogdanm	82:6473597d706e	613	#define BR_RTC_CR_OSCE (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_OSCE))
bogdanm	82:6473597d706e	614	#endif
bogdanm	82:6473597d706e	615
bogdanm	82:6473597d706e	616	//! @brief Format value for bitfield RTC_CR_OSCE.
bogdanm	82:6473597d706e	617	#define BF_RTC_CR_OSCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_OSCE), uint32_t) & BM_RTC_CR_OSCE)
bogdanm	82:6473597d706e	618
bogdanm	82:6473597d706e	619	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	620	//! @brief Set the OSCE field to a new value.
bogdanm	82:6473597d706e	621	#define BW_RTC_CR_OSCE(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_OSCE) = (v))
bogdanm	82:6473597d706e	622	#endif
bogdanm	82:6473597d706e	623	//@}
bogdanm	82:6473597d706e	624
bogdanm	82:6473597d706e	625	/*!
bogdanm	82:6473597d706e	626	* @name Register RTC_CR, field CLKO[9] (RW)
bogdanm	82:6473597d706e	627	*
bogdanm	82:6473597d706e	628	* Values:
bogdanm	82:6473597d706e	629	* - 0 - The 32 kHz clock is output to other peripherals.
bogdanm	82:6473597d706e	630	* - 1 - The 32 kHz clock is not output to other peripherals.
bogdanm	82:6473597d706e	631	*/
bogdanm	82:6473597d706e	632	//@{
bogdanm	82:6473597d706e	633	#define BP_RTC_CR_CLKO (9U) //!< Bit position for RTC_CR_CLKO.
bogdanm	82:6473597d706e	634	#define BM_RTC_CR_CLKO (0x00000200U) //!< Bit mask for RTC_CR_CLKO.
bogdanm	82:6473597d706e	635	#define BS_RTC_CR_CLKO (1U) //!< Bit field size in bits for RTC_CR_CLKO.
bogdanm	82:6473597d706e	636
bogdanm	82:6473597d706e	637	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	638	//! @brief Read current value of the RTC_CR_CLKO field.
bogdanm	82:6473597d706e	639	#define BR_RTC_CR_CLKO (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_CLKO))
bogdanm	82:6473597d706e	640	#endif
bogdanm	82:6473597d706e	641
bogdanm	82:6473597d706e	642	//! @brief Format value for bitfield RTC_CR_CLKO.
bogdanm	82:6473597d706e	643	#define BF_RTC_CR_CLKO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_CLKO), uint32_t) & BM_RTC_CR_CLKO)
bogdanm	82:6473597d706e	644
bogdanm	82:6473597d706e	645	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	646	//! @brief Set the CLKO field to a new value.
bogdanm	82:6473597d706e	647	#define BW_RTC_CR_CLKO(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_CLKO) = (v))
bogdanm	82:6473597d706e	648	#endif
bogdanm	82:6473597d706e	649	//@}
bogdanm	82:6473597d706e	650
bogdanm	82:6473597d706e	651	/*!
bogdanm	82:6473597d706e	652	* @name Register RTC_CR, field SC16P[10] (RW)
bogdanm	82:6473597d706e	653	*
bogdanm	82:6473597d706e	654	* Values:
bogdanm	82:6473597d706e	655	* - 0 - Disable the load.
bogdanm	82:6473597d706e	656	* - 1 - Enable the additional load.
bogdanm	82:6473597d706e	657	*/
bogdanm	82:6473597d706e	658	//@{
bogdanm	82:6473597d706e	659	#define BP_RTC_CR_SC16P (10U) //!< Bit position for RTC_CR_SC16P.
bogdanm	82:6473597d706e	660	#define BM_RTC_CR_SC16P (0x00000400U) //!< Bit mask for RTC_CR_SC16P.
bogdanm	82:6473597d706e	661	#define BS_RTC_CR_SC16P (1U) //!< Bit field size in bits for RTC_CR_SC16P.
bogdanm	82:6473597d706e	662
bogdanm	82:6473597d706e	663	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	664	//! @brief Read current value of the RTC_CR_SC16P field.
bogdanm	82:6473597d706e	665	#define BR_RTC_CR_SC16P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC16P))
bogdanm	82:6473597d706e	666	#endif
bogdanm	82:6473597d706e	667
bogdanm	82:6473597d706e	668	//! @brief Format value for bitfield RTC_CR_SC16P.
bogdanm	82:6473597d706e	669	#define BF_RTC_CR_SC16P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC16P), uint32_t) & BM_RTC_CR_SC16P)
bogdanm	82:6473597d706e	670
bogdanm	82:6473597d706e	671	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	672	//! @brief Set the SC16P field to a new value.
bogdanm	82:6473597d706e	673	#define BW_RTC_CR_SC16P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC16P) = (v))
bogdanm	82:6473597d706e	674	#endif
bogdanm	82:6473597d706e	675	//@}
bogdanm	82:6473597d706e	676
bogdanm	82:6473597d706e	677	/*!
bogdanm	82:6473597d706e	678	* @name Register RTC_CR, field SC8P[11] (RW)
bogdanm	82:6473597d706e	679	*
bogdanm	82:6473597d706e	680	* Values:
bogdanm	82:6473597d706e	681	* - 0 - Disable the load.
bogdanm	82:6473597d706e	682	* - 1 - Enable the additional load.
bogdanm	82:6473597d706e	683	*/
bogdanm	82:6473597d706e	684	//@{
bogdanm	82:6473597d706e	685	#define BP_RTC_CR_SC8P (11U) //!< Bit position for RTC_CR_SC8P.
bogdanm	82:6473597d706e	686	#define BM_RTC_CR_SC8P (0x00000800U) //!< Bit mask for RTC_CR_SC8P.
bogdanm	82:6473597d706e	687	#define BS_RTC_CR_SC8P (1U) //!< Bit field size in bits for RTC_CR_SC8P.
bogdanm	82:6473597d706e	688
bogdanm	82:6473597d706e	689	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	690	//! @brief Read current value of the RTC_CR_SC8P field.
bogdanm	82:6473597d706e	691	#define BR_RTC_CR_SC8P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC8P))
bogdanm	82:6473597d706e	692	#endif
bogdanm	82:6473597d706e	693
bogdanm	82:6473597d706e	694	//! @brief Format value for bitfield RTC_CR_SC8P.
bogdanm	82:6473597d706e	695	#define BF_RTC_CR_SC8P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC8P), uint32_t) & BM_RTC_CR_SC8P)
bogdanm	82:6473597d706e	696
bogdanm	82:6473597d706e	697	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	698	//! @brief Set the SC8P field to a new value.
bogdanm	82:6473597d706e	699	#define BW_RTC_CR_SC8P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC8P) = (v))
bogdanm	82:6473597d706e	700	#endif
bogdanm	82:6473597d706e	701	//@}
bogdanm	82:6473597d706e	702
bogdanm	82:6473597d706e	703	/*!
bogdanm	82:6473597d706e	704	* @name Register RTC_CR, field SC4P[12] (RW)
bogdanm	82:6473597d706e	705	*
bogdanm	82:6473597d706e	706	* Values:
bogdanm	82:6473597d706e	707	* - 0 - Disable the load.
bogdanm	82:6473597d706e	708	* - 1 - Enable the additional load.
bogdanm	82:6473597d706e	709	*/
bogdanm	82:6473597d706e	710	//@{
bogdanm	82:6473597d706e	711	#define BP_RTC_CR_SC4P (12U) //!< Bit position for RTC_CR_SC4P.
bogdanm	82:6473597d706e	712	#define BM_RTC_CR_SC4P (0x00001000U) //!< Bit mask for RTC_CR_SC4P.
bogdanm	82:6473597d706e	713	#define BS_RTC_CR_SC4P (1U) //!< Bit field size in bits for RTC_CR_SC4P.
bogdanm	82:6473597d706e	714
bogdanm	82:6473597d706e	715	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	716	//! @brief Read current value of the RTC_CR_SC4P field.
bogdanm	82:6473597d706e	717	#define BR_RTC_CR_SC4P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC4P))
bogdanm	82:6473597d706e	718	#endif
bogdanm	82:6473597d706e	719
bogdanm	82:6473597d706e	720	//! @brief Format value for bitfield RTC_CR_SC4P.
bogdanm	82:6473597d706e	721	#define BF_RTC_CR_SC4P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC4P), uint32_t) & BM_RTC_CR_SC4P)
bogdanm	82:6473597d706e	722
bogdanm	82:6473597d706e	723	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	724	//! @brief Set the SC4P field to a new value.
bogdanm	82:6473597d706e	725	#define BW_RTC_CR_SC4P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC4P) = (v))
bogdanm	82:6473597d706e	726	#endif
bogdanm	82:6473597d706e	727	//@}
bogdanm	82:6473597d706e	728
bogdanm	82:6473597d706e	729	/*!
bogdanm	82:6473597d706e	730	* @name Register RTC_CR, field SC2P[13] (RW)
bogdanm	82:6473597d706e	731	*
bogdanm	82:6473597d706e	732	* Values:
bogdanm	82:6473597d706e	733	* - 0 - Disable the load.
bogdanm	82:6473597d706e	734	* - 1 - Enable the additional load.
bogdanm	82:6473597d706e	735	*/
bogdanm	82:6473597d706e	736	//@{
bogdanm	82:6473597d706e	737	#define BP_RTC_CR_SC2P (13U) //!< Bit position for RTC_CR_SC2P.
bogdanm	82:6473597d706e	738	#define BM_RTC_CR_SC2P (0x00002000U) //!< Bit mask for RTC_CR_SC2P.
bogdanm	82:6473597d706e	739	#define BS_RTC_CR_SC2P (1U) //!< Bit field size in bits for RTC_CR_SC2P.
bogdanm	82:6473597d706e	740
bogdanm	82:6473597d706e	741	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	742	//! @brief Read current value of the RTC_CR_SC2P field.
bogdanm	82:6473597d706e	743	#define BR_RTC_CR_SC2P (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC2P))
bogdanm	82:6473597d706e	744	#endif
bogdanm	82:6473597d706e	745
bogdanm	82:6473597d706e	746	//! @brief Format value for bitfield RTC_CR_SC2P.
bogdanm	82:6473597d706e	747	#define BF_RTC_CR_SC2P(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_CR_SC2P), uint32_t) & BM_RTC_CR_SC2P)
bogdanm	82:6473597d706e	748
bogdanm	82:6473597d706e	749	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	750	//! @brief Set the SC2P field to a new value.
bogdanm	82:6473597d706e	751	#define BW_RTC_CR_SC2P(v) (BITBAND_ACCESS32(HW_RTC_CR_ADDR, BP_RTC_CR_SC2P) = (v))
bogdanm	82:6473597d706e	752	#endif
bogdanm	82:6473597d706e	753	//@}
bogdanm	82:6473597d706e	754
bogdanm	82:6473597d706e	755	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	756	// HW_RTC_SR - RTC Status Register
bogdanm	82:6473597d706e	757	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	758
bogdanm	82:6473597d706e	759	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	760	/*!
bogdanm	82:6473597d706e	761	* @brief HW_RTC_SR - RTC Status Register (RW)
bogdanm	82:6473597d706e	762	*
bogdanm	82:6473597d706e	763	* Reset value: 0x00000001U
bogdanm	82:6473597d706e	764	*/
bogdanm	82:6473597d706e	765	typedef union _hw_rtc_sr
bogdanm	82:6473597d706e	766	{
bogdanm	82:6473597d706e	767	uint32_t U;
bogdanm	82:6473597d706e	768	struct _hw_rtc_sr_bitfields
bogdanm	82:6473597d706e	769	{
bogdanm	82:6473597d706e	770	uint32_t TIF : 1; //!< [0] Time Invalid Flag
bogdanm	82:6473597d706e	771	uint32_t TOF : 1; //!< [1] Time Overflow Flag
bogdanm	82:6473597d706e	772	uint32_t TAF : 1; //!< [2] Time Alarm Flag
bogdanm	82:6473597d706e	773	uint32_t RESERVED0 : 1; //!< [3]
bogdanm	82:6473597d706e	774	uint32_t TCE : 1; //!< [4] Time Counter Enable
bogdanm	82:6473597d706e	775	uint32_t RESERVED1 : 27; //!< [31:5]
bogdanm	82:6473597d706e	776	} B;
bogdanm	82:6473597d706e	777	} hw_rtc_sr_t;
bogdanm	82:6473597d706e	778	#endif
bogdanm	82:6473597d706e	779
bogdanm	82:6473597d706e	780	/*!
bogdanm	82:6473597d706e	781	* @name Constants and macros for entire RTC_SR register
bogdanm	82:6473597d706e	782	*/
bogdanm	82:6473597d706e	783	//@{
bogdanm	82:6473597d706e	784	#define HW_RTC_SR_ADDR (REGS_RTC_BASE + 0x14U)
bogdanm	82:6473597d706e	785
bogdanm	82:6473597d706e	786	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	787	#define HW_RTC_SR ((__IO hw_rtc_sr_t ) HW_RTC_SR_ADDR)
bogdanm	82:6473597d706e	788	#define HW_RTC_SR_RD() (HW_RTC_SR.U)
bogdanm	82:6473597d706e	789	#define HW_RTC_SR_WR(v) (HW_RTC_SR.U = (v))
bogdanm	82:6473597d706e	790	#define HW_RTC_SR_SET(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() \| (v)))
bogdanm	82:6473597d706e	791	#define HW_RTC_SR_CLR(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() & ~(v)))
bogdanm	82:6473597d706e	792	#define HW_RTC_SR_TOG(v) (HW_RTC_SR_WR(HW_RTC_SR_RD() ^ (v)))
bogdanm	82:6473597d706e	793	#endif
bogdanm	82:6473597d706e	794	//@}
bogdanm	82:6473597d706e	795
bogdanm	82:6473597d706e	796	/*
bogdanm	82:6473597d706e	797	* Constants & macros for individual RTC_SR bitfields
bogdanm	82:6473597d706e	798	*/
bogdanm	82:6473597d706e	799
bogdanm	82:6473597d706e	800	/*!
bogdanm	82:6473597d706e	801	* @name Register RTC_SR, field TIF[0] (RO)
bogdanm	82:6473597d706e	802	*
bogdanm	82:6473597d706e	803	* The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
bogdanm	82:6473597d706e	804	* do not increment and read as zero when this bit is set. This bit is cleared by
bogdanm	82:6473597d706e	805	* writing the TSR register when the time counter is disabled.
bogdanm	82:6473597d706e	806	*
bogdanm	82:6473597d706e	807	* Values:
bogdanm	82:6473597d706e	808	* - 0 - Time is valid.
bogdanm	82:6473597d706e	809	* - 1 - Time is invalid and time counter is read as zero.
bogdanm	82:6473597d706e	810	*/
bogdanm	82:6473597d706e	811	//@{
bogdanm	82:6473597d706e	812	#define BP_RTC_SR_TIF (0U) //!< Bit position for RTC_SR_TIF.
bogdanm	82:6473597d706e	813	#define BM_RTC_SR_TIF (0x00000001U) //!< Bit mask for RTC_SR_TIF.
bogdanm	82:6473597d706e	814	#define BS_RTC_SR_TIF (1U) //!< Bit field size in bits for RTC_SR_TIF.
bogdanm	82:6473597d706e	815
bogdanm	82:6473597d706e	816	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	817	//! @brief Read current value of the RTC_SR_TIF field.
bogdanm	82:6473597d706e	818	#define BR_RTC_SR_TIF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TIF))
bogdanm	82:6473597d706e	819	#endif
bogdanm	82:6473597d706e	820	//@}
bogdanm	82:6473597d706e	821
bogdanm	82:6473597d706e	822	/*!
bogdanm	82:6473597d706e	823	* @name Register RTC_SR, field TOF[1] (RO)
bogdanm	82:6473597d706e	824	*
bogdanm	82:6473597d706e	825	* Time overflow flag is set when the time counter is enabled and overflows. The
bogdanm	82:6473597d706e	826	* TSR and TPR do not increment and read as zero when this bit is set. This bit
bogdanm	82:6473597d706e	827	* is cleared by writing the TSR register when the time counter is disabled.
bogdanm	82:6473597d706e	828	*
bogdanm	82:6473597d706e	829	* Values:
bogdanm	82:6473597d706e	830	* - 0 - Time overflow has not occurred.
bogdanm	82:6473597d706e	831	* - 1 - Time overflow has occurred and time counter is read as zero.
bogdanm	82:6473597d706e	832	*/
bogdanm	82:6473597d706e	833	//@{
bogdanm	82:6473597d706e	834	#define BP_RTC_SR_TOF (1U) //!< Bit position for RTC_SR_TOF.
bogdanm	82:6473597d706e	835	#define BM_RTC_SR_TOF (0x00000002U) //!< Bit mask for RTC_SR_TOF.
bogdanm	82:6473597d706e	836	#define BS_RTC_SR_TOF (1U) //!< Bit field size in bits for RTC_SR_TOF.
bogdanm	82:6473597d706e	837
bogdanm	82:6473597d706e	838	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	839	//! @brief Read current value of the RTC_SR_TOF field.
bogdanm	82:6473597d706e	840	#define BR_RTC_SR_TOF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TOF))
bogdanm	82:6473597d706e	841	#endif
bogdanm	82:6473597d706e	842	//@}
bogdanm	82:6473597d706e	843
bogdanm	82:6473597d706e	844	/*!
bogdanm	82:6473597d706e	845	* @name Register RTC_SR, field TAF[2] (RO)
bogdanm	82:6473597d706e	846	*
bogdanm	82:6473597d706e	847	* Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
bogdanm	82:6473597d706e	848	* increments. This bit is cleared by writing the TAR register.
bogdanm	82:6473597d706e	849	*
bogdanm	82:6473597d706e	850	* Values:
bogdanm	82:6473597d706e	851	* - 0 - Time alarm has not occurred.
bogdanm	82:6473597d706e	852	* - 1 - Time alarm has occurred.
bogdanm	82:6473597d706e	853	*/
bogdanm	82:6473597d706e	854	//@{
bogdanm	82:6473597d706e	855	#define BP_RTC_SR_TAF (2U) //!< Bit position for RTC_SR_TAF.
bogdanm	82:6473597d706e	856	#define BM_RTC_SR_TAF (0x00000004U) //!< Bit mask for RTC_SR_TAF.
bogdanm	82:6473597d706e	857	#define BS_RTC_SR_TAF (1U) //!< Bit field size in bits for RTC_SR_TAF.
bogdanm	82:6473597d706e	858
bogdanm	82:6473597d706e	859	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	860	//! @brief Read current value of the RTC_SR_TAF field.
bogdanm	82:6473597d706e	861	#define BR_RTC_SR_TAF (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TAF))
bogdanm	82:6473597d706e	862	#endif
bogdanm	82:6473597d706e	863	//@}
bogdanm	82:6473597d706e	864
bogdanm	82:6473597d706e	865	/*!
bogdanm	82:6473597d706e	866	* @name Register RTC_SR, field TCE[4] (RW)
bogdanm	82:6473597d706e	867	*
bogdanm	82:6473597d706e	868	* When time counter is disabled the TSR register and TPR register are
bogdanm	82:6473597d706e	869	* writeable, but do not increment. When time counter is enabled the TSR register and TPR
bogdanm	82:6473597d706e	870	* register are not writeable, but increment.
bogdanm	82:6473597d706e	871	*
bogdanm	82:6473597d706e	872	* Values:
bogdanm	82:6473597d706e	873	* - 0 - Time counter is disabled.
bogdanm	82:6473597d706e	874	* - 1 - Time counter is enabled.
bogdanm	82:6473597d706e	875	*/
bogdanm	82:6473597d706e	876	//@{
bogdanm	82:6473597d706e	877	#define BP_RTC_SR_TCE (4U) //!< Bit position for RTC_SR_TCE.
bogdanm	82:6473597d706e	878	#define BM_RTC_SR_TCE (0x00000010U) //!< Bit mask for RTC_SR_TCE.
bogdanm	82:6473597d706e	879	#define BS_RTC_SR_TCE (1U) //!< Bit field size in bits for RTC_SR_TCE.
bogdanm	82:6473597d706e	880
bogdanm	82:6473597d706e	881	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	882	//! @brief Read current value of the RTC_SR_TCE field.
bogdanm	82:6473597d706e	883	#define BR_RTC_SR_TCE (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TCE))
bogdanm	82:6473597d706e	884	#endif
bogdanm	82:6473597d706e	885
bogdanm	82:6473597d706e	886	//! @brief Format value for bitfield RTC_SR_TCE.
bogdanm	82:6473597d706e	887	#define BF_RTC_SR_TCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_SR_TCE), uint32_t) & BM_RTC_SR_TCE)
bogdanm	82:6473597d706e	888
bogdanm	82:6473597d706e	889	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	890	//! @brief Set the TCE field to a new value.
bogdanm	82:6473597d706e	891	#define BW_RTC_SR_TCE(v) (BITBAND_ACCESS32(HW_RTC_SR_ADDR, BP_RTC_SR_TCE) = (v))
bogdanm	82:6473597d706e	892	#endif
bogdanm	82:6473597d706e	893	//@}
bogdanm	82:6473597d706e	894
bogdanm	82:6473597d706e	895	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	896	// HW_RTC_LR - RTC Lock Register
bogdanm	82:6473597d706e	897	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	898
bogdanm	82:6473597d706e	899	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	900	/*!
bogdanm	82:6473597d706e	901	* @brief HW_RTC_LR - RTC Lock Register (RW)
bogdanm	82:6473597d706e	902	*
bogdanm	82:6473597d706e	903	* Reset value: 0x000000FFU
bogdanm	82:6473597d706e	904	*/
bogdanm	82:6473597d706e	905	typedef union _hw_rtc_lr
bogdanm	82:6473597d706e	906	{
bogdanm	82:6473597d706e	907	uint32_t U;
bogdanm	82:6473597d706e	908	struct _hw_rtc_lr_bitfields
bogdanm	82:6473597d706e	909	{
bogdanm	82:6473597d706e	910	uint32_t RESERVED0 : 3; //!< [2:0]
bogdanm	82:6473597d706e	911	uint32_t TCL : 1; //!< [3] Time Compensation Lock
bogdanm	82:6473597d706e	912	uint32_t CRL : 1; //!< [4] Control Register Lock
bogdanm	82:6473597d706e	913	uint32_t SRL : 1; //!< [5] Status Register Lock
bogdanm	82:6473597d706e	914	uint32_t LRL : 1; //!< [6] Lock Register Lock
bogdanm	82:6473597d706e	915	uint32_t RESERVED1 : 25; //!< [31:7]
bogdanm	82:6473597d706e	916	} B;
bogdanm	82:6473597d706e	917	} hw_rtc_lr_t;
bogdanm	82:6473597d706e	918	#endif
bogdanm	82:6473597d706e	919
bogdanm	82:6473597d706e	920	/*!
bogdanm	82:6473597d706e	921	* @name Constants and macros for entire RTC_LR register
bogdanm	82:6473597d706e	922	*/
bogdanm	82:6473597d706e	923	//@{
bogdanm	82:6473597d706e	924	#define HW_RTC_LR_ADDR (REGS_RTC_BASE + 0x18U)
bogdanm	82:6473597d706e	925
bogdanm	82:6473597d706e	926	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	927	#define HW_RTC_LR ((__IO hw_rtc_lr_t ) HW_RTC_LR_ADDR)
bogdanm	82:6473597d706e	928	#define HW_RTC_LR_RD() (HW_RTC_LR.U)
bogdanm	82:6473597d706e	929	#define HW_RTC_LR_WR(v) (HW_RTC_LR.U = (v))
bogdanm	82:6473597d706e	930	#define HW_RTC_LR_SET(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() \| (v)))
bogdanm	82:6473597d706e	931	#define HW_RTC_LR_CLR(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() & ~(v)))
bogdanm	82:6473597d706e	932	#define HW_RTC_LR_TOG(v) (HW_RTC_LR_WR(HW_RTC_LR_RD() ^ (v)))
bogdanm	82:6473597d706e	933	#endif
bogdanm	82:6473597d706e	934	//@}
bogdanm	82:6473597d706e	935
bogdanm	82:6473597d706e	936	/*
bogdanm	82:6473597d706e	937	* Constants & macros for individual RTC_LR bitfields
bogdanm	82:6473597d706e	938	*/
bogdanm	82:6473597d706e	939
bogdanm	82:6473597d706e	940	/*!
bogdanm	82:6473597d706e	941	* @name Register RTC_LR, field TCL[3] (RW)
bogdanm	82:6473597d706e	942	*
bogdanm	82:6473597d706e	943	* After being cleared, this bit can be set only by VBAT POR or software reset.
bogdanm	82:6473597d706e	944	*
bogdanm	82:6473597d706e	945	* Values:
bogdanm	82:6473597d706e	946	* - 0 - Time Compensation Register is locked and writes are ignored.
bogdanm	82:6473597d706e	947	* - 1 - Time Compensation Register is not locked and writes complete as normal.
bogdanm	82:6473597d706e	948	*/
bogdanm	82:6473597d706e	949	//@{
bogdanm	82:6473597d706e	950	#define BP_RTC_LR_TCL (3U) //!< Bit position for RTC_LR_TCL.
bogdanm	82:6473597d706e	951	#define BM_RTC_LR_TCL (0x00000008U) //!< Bit mask for RTC_LR_TCL.
bogdanm	82:6473597d706e	952	#define BS_RTC_LR_TCL (1U) //!< Bit field size in bits for RTC_LR_TCL.
bogdanm	82:6473597d706e	953
bogdanm	82:6473597d706e	954	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	955	//! @brief Read current value of the RTC_LR_TCL field.
bogdanm	82:6473597d706e	956	#define BR_RTC_LR_TCL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_TCL))
bogdanm	82:6473597d706e	957	#endif
bogdanm	82:6473597d706e	958
bogdanm	82:6473597d706e	959	//! @brief Format value for bitfield RTC_LR_TCL.
bogdanm	82:6473597d706e	960	#define BF_RTC_LR_TCL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_TCL), uint32_t) & BM_RTC_LR_TCL)
bogdanm	82:6473597d706e	961
bogdanm	82:6473597d706e	962	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	963	//! @brief Set the TCL field to a new value.
bogdanm	82:6473597d706e	964	#define BW_RTC_LR_TCL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_TCL) = (v))
bogdanm	82:6473597d706e	965	#endif
bogdanm	82:6473597d706e	966	//@}
bogdanm	82:6473597d706e	967
bogdanm	82:6473597d706e	968	/*!
bogdanm	82:6473597d706e	969	* @name Register RTC_LR, field CRL[4] (RW)
bogdanm	82:6473597d706e	970	*
bogdanm	82:6473597d706e	971	* After being cleared, this bit can only be set by VBAT POR.
bogdanm	82:6473597d706e	972	*
bogdanm	82:6473597d706e	973	* Values:
bogdanm	82:6473597d706e	974	* - 0 - Control Register is locked and writes are ignored.
bogdanm	82:6473597d706e	975	* - 1 - Control Register is not locked and writes complete as normal.
bogdanm	82:6473597d706e	976	*/
bogdanm	82:6473597d706e	977	//@{
bogdanm	82:6473597d706e	978	#define BP_RTC_LR_CRL (4U) //!< Bit position for RTC_LR_CRL.
bogdanm	82:6473597d706e	979	#define BM_RTC_LR_CRL (0x00000010U) //!< Bit mask for RTC_LR_CRL.
bogdanm	82:6473597d706e	980	#define BS_RTC_LR_CRL (1U) //!< Bit field size in bits for RTC_LR_CRL.
bogdanm	82:6473597d706e	981
bogdanm	82:6473597d706e	982	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	983	//! @brief Read current value of the RTC_LR_CRL field.
bogdanm	82:6473597d706e	984	#define BR_RTC_LR_CRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_CRL))
bogdanm	82:6473597d706e	985	#endif
bogdanm	82:6473597d706e	986
bogdanm	82:6473597d706e	987	//! @brief Format value for bitfield RTC_LR_CRL.
bogdanm	82:6473597d706e	988	#define BF_RTC_LR_CRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_CRL), uint32_t) & BM_RTC_LR_CRL)
bogdanm	82:6473597d706e	989
bogdanm	82:6473597d706e	990	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	991	//! @brief Set the CRL field to a new value.
bogdanm	82:6473597d706e	992	#define BW_RTC_LR_CRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_CRL) = (v))
bogdanm	82:6473597d706e	993	#endif
bogdanm	82:6473597d706e	994	//@}
bogdanm	82:6473597d706e	995
bogdanm	82:6473597d706e	996	/*!
bogdanm	82:6473597d706e	997	* @name Register RTC_LR, field SRL[5] (RW)
bogdanm	82:6473597d706e	998	*
bogdanm	82:6473597d706e	999	* After being cleared, this bit can be set only by VBAT POR or software reset.
bogdanm	82:6473597d706e	1000	*
bogdanm	82:6473597d706e	1001	* Values:
bogdanm	82:6473597d706e	1002	* - 0 - Status Register is locked and writes are ignored.
bogdanm	82:6473597d706e	1003	* - 1 - Status Register is not locked and writes complete as normal.
bogdanm	82:6473597d706e	1004	*/
bogdanm	82:6473597d706e	1005	//@{
bogdanm	82:6473597d706e	1006	#define BP_RTC_LR_SRL (5U) //!< Bit position for RTC_LR_SRL.
bogdanm	82:6473597d706e	1007	#define BM_RTC_LR_SRL (0x00000020U) //!< Bit mask for RTC_LR_SRL.
bogdanm	82:6473597d706e	1008	#define BS_RTC_LR_SRL (1U) //!< Bit field size in bits for RTC_LR_SRL.
bogdanm	82:6473597d706e	1009
bogdanm	82:6473597d706e	1010	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1011	//! @brief Read current value of the RTC_LR_SRL field.
bogdanm	82:6473597d706e	1012	#define BR_RTC_LR_SRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_SRL))
bogdanm	82:6473597d706e	1013	#endif
bogdanm	82:6473597d706e	1014
bogdanm	82:6473597d706e	1015	//! @brief Format value for bitfield RTC_LR_SRL.
bogdanm	82:6473597d706e	1016	#define BF_RTC_LR_SRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_SRL), uint32_t) & BM_RTC_LR_SRL)
bogdanm	82:6473597d706e	1017
bogdanm	82:6473597d706e	1018	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1019	//! @brief Set the SRL field to a new value.
bogdanm	82:6473597d706e	1020	#define BW_RTC_LR_SRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_SRL) = (v))
bogdanm	82:6473597d706e	1021	#endif
bogdanm	82:6473597d706e	1022	//@}
bogdanm	82:6473597d706e	1023
bogdanm	82:6473597d706e	1024	/*!
bogdanm	82:6473597d706e	1025	* @name Register RTC_LR, field LRL[6] (RW)
bogdanm	82:6473597d706e	1026	*
bogdanm	82:6473597d706e	1027	* After being cleared, this bit can be set only by VBAT POR or software reset.
bogdanm	82:6473597d706e	1028	*
bogdanm	82:6473597d706e	1029	* Values:
bogdanm	82:6473597d706e	1030	* - 0 - Lock Register is locked and writes are ignored.
bogdanm	82:6473597d706e	1031	* - 1 - Lock Register is not locked and writes complete as normal.
bogdanm	82:6473597d706e	1032	*/
bogdanm	82:6473597d706e	1033	//@{
bogdanm	82:6473597d706e	1034	#define BP_RTC_LR_LRL (6U) //!< Bit position for RTC_LR_LRL.
bogdanm	82:6473597d706e	1035	#define BM_RTC_LR_LRL (0x00000040U) //!< Bit mask for RTC_LR_LRL.
bogdanm	82:6473597d706e	1036	#define BS_RTC_LR_LRL (1U) //!< Bit field size in bits for RTC_LR_LRL.
bogdanm	82:6473597d706e	1037
bogdanm	82:6473597d706e	1038	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1039	//! @brief Read current value of the RTC_LR_LRL field.
bogdanm	82:6473597d706e	1040	#define BR_RTC_LR_LRL (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_LRL))
bogdanm	82:6473597d706e	1041	#endif
bogdanm	82:6473597d706e	1042
bogdanm	82:6473597d706e	1043	//! @brief Format value for bitfield RTC_LR_LRL.
bogdanm	82:6473597d706e	1044	#define BF_RTC_LR_LRL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_LR_LRL), uint32_t) & BM_RTC_LR_LRL)
bogdanm	82:6473597d706e	1045
bogdanm	82:6473597d706e	1046	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1047	//! @brief Set the LRL field to a new value.
bogdanm	82:6473597d706e	1048	#define BW_RTC_LR_LRL(v) (BITBAND_ACCESS32(HW_RTC_LR_ADDR, BP_RTC_LR_LRL) = (v))
bogdanm	82:6473597d706e	1049	#endif
bogdanm	82:6473597d706e	1050	//@}
bogdanm	82:6473597d706e	1051
bogdanm	82:6473597d706e	1052	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1053	// HW_RTC_IER - RTC Interrupt Enable Register
bogdanm	82:6473597d706e	1054	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1055
bogdanm	82:6473597d706e	1056	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1057	/*!
bogdanm	82:6473597d706e	1058	* @brief HW_RTC_IER - RTC Interrupt Enable Register (RW)
bogdanm	82:6473597d706e	1059	*
bogdanm	82:6473597d706e	1060	* Reset value: 0x00000007U
bogdanm	82:6473597d706e	1061	*/
bogdanm	82:6473597d706e	1062	typedef union _hw_rtc_ier
bogdanm	82:6473597d706e	1063	{
bogdanm	82:6473597d706e	1064	uint32_t U;
bogdanm	82:6473597d706e	1065	struct _hw_rtc_ier_bitfields
bogdanm	82:6473597d706e	1066	{
bogdanm	82:6473597d706e	1067	uint32_t TIIE : 1; //!< [0] Time Invalid Interrupt Enable
bogdanm	82:6473597d706e	1068	uint32_t TOIE : 1; //!< [1] Time Overflow Interrupt Enable
bogdanm	82:6473597d706e	1069	uint32_t TAIE : 1; //!< [2] Time Alarm Interrupt Enable
bogdanm	82:6473597d706e	1070	uint32_t RESERVED0 : 1; //!< [3]
bogdanm	82:6473597d706e	1071	uint32_t TSIE : 1; //!< [4] Time Seconds Interrupt Enable
bogdanm	82:6473597d706e	1072	uint32_t RESERVED1 : 2; //!< [6:5]
bogdanm	82:6473597d706e	1073	uint32_t WPON : 1; //!< [7] Wakeup Pin On
bogdanm	82:6473597d706e	1074	uint32_t RESERVED2 : 24; //!< [31:8]
bogdanm	82:6473597d706e	1075	} B;
bogdanm	82:6473597d706e	1076	} hw_rtc_ier_t;
bogdanm	82:6473597d706e	1077	#endif
bogdanm	82:6473597d706e	1078
bogdanm	82:6473597d706e	1079	/*!
bogdanm	82:6473597d706e	1080	* @name Constants and macros for entire RTC_IER register
bogdanm	82:6473597d706e	1081	*/
bogdanm	82:6473597d706e	1082	//@{
bogdanm	82:6473597d706e	1083	#define HW_RTC_IER_ADDR (REGS_RTC_BASE + 0x1CU)
bogdanm	82:6473597d706e	1084
bogdanm	82:6473597d706e	1085	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1086	#define HW_RTC_IER ((__IO hw_rtc_ier_t ) HW_RTC_IER_ADDR)
bogdanm	82:6473597d706e	1087	#define HW_RTC_IER_RD() (HW_RTC_IER.U)
bogdanm	82:6473597d706e	1088	#define HW_RTC_IER_WR(v) (HW_RTC_IER.U = (v))
bogdanm	82:6473597d706e	1089	#define HW_RTC_IER_SET(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() \| (v)))
bogdanm	82:6473597d706e	1090	#define HW_RTC_IER_CLR(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() & ~(v)))
bogdanm	82:6473597d706e	1091	#define HW_RTC_IER_TOG(v) (HW_RTC_IER_WR(HW_RTC_IER_RD() ^ (v)))
bogdanm	82:6473597d706e	1092	#endif
bogdanm	82:6473597d706e	1093	//@}
bogdanm	82:6473597d706e	1094
bogdanm	82:6473597d706e	1095	/*
bogdanm	82:6473597d706e	1096	* Constants & macros for individual RTC_IER bitfields
bogdanm	82:6473597d706e	1097	*/
bogdanm	82:6473597d706e	1098
bogdanm	82:6473597d706e	1099	/*!
bogdanm	82:6473597d706e	1100	* @name Register RTC_IER, field TIIE[0] (RW)
bogdanm	82:6473597d706e	1101	*
bogdanm	82:6473597d706e	1102	* Values:
bogdanm	82:6473597d706e	1103	* - 0 - Time invalid flag does not generate an interrupt.
bogdanm	82:6473597d706e	1104	* - 1 - Time invalid flag does generate an interrupt.
bogdanm	82:6473597d706e	1105	*/
bogdanm	82:6473597d706e	1106	//@{
bogdanm	82:6473597d706e	1107	#define BP_RTC_IER_TIIE (0U) //!< Bit position for RTC_IER_TIIE.
bogdanm	82:6473597d706e	1108	#define BM_RTC_IER_TIIE (0x00000001U) //!< Bit mask for RTC_IER_TIIE.
bogdanm	82:6473597d706e	1109	#define BS_RTC_IER_TIIE (1U) //!< Bit field size in bits for RTC_IER_TIIE.
bogdanm	82:6473597d706e	1110
bogdanm	82:6473597d706e	1111	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1112	//! @brief Read current value of the RTC_IER_TIIE field.
bogdanm	82:6473597d706e	1113	#define BR_RTC_IER_TIIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TIIE))
bogdanm	82:6473597d706e	1114	#endif
bogdanm	82:6473597d706e	1115
bogdanm	82:6473597d706e	1116	//! @brief Format value for bitfield RTC_IER_TIIE.
bogdanm	82:6473597d706e	1117	#define BF_RTC_IER_TIIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TIIE), uint32_t) & BM_RTC_IER_TIIE)
bogdanm	82:6473597d706e	1118
bogdanm	82:6473597d706e	1119	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1120	//! @brief Set the TIIE field to a new value.
bogdanm	82:6473597d706e	1121	#define BW_RTC_IER_TIIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TIIE) = (v))
bogdanm	82:6473597d706e	1122	#endif
bogdanm	82:6473597d706e	1123	//@}
bogdanm	82:6473597d706e	1124
bogdanm	82:6473597d706e	1125	/*!
bogdanm	82:6473597d706e	1126	* @name Register RTC_IER, field TOIE[1] (RW)
bogdanm	82:6473597d706e	1127	*
bogdanm	82:6473597d706e	1128	* Values:
bogdanm	82:6473597d706e	1129	* - 0 - Time overflow flag does not generate an interrupt.
bogdanm	82:6473597d706e	1130	* - 1 - Time overflow flag does generate an interrupt.
bogdanm	82:6473597d706e	1131	*/
bogdanm	82:6473597d706e	1132	//@{
bogdanm	82:6473597d706e	1133	#define BP_RTC_IER_TOIE (1U) //!< Bit position for RTC_IER_TOIE.
bogdanm	82:6473597d706e	1134	#define BM_RTC_IER_TOIE (0x00000002U) //!< Bit mask for RTC_IER_TOIE.
bogdanm	82:6473597d706e	1135	#define BS_RTC_IER_TOIE (1U) //!< Bit field size in bits for RTC_IER_TOIE.
bogdanm	82:6473597d706e	1136
bogdanm	82:6473597d706e	1137	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1138	//! @brief Read current value of the RTC_IER_TOIE field.
bogdanm	82:6473597d706e	1139	#define BR_RTC_IER_TOIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TOIE))
bogdanm	82:6473597d706e	1140	#endif
bogdanm	82:6473597d706e	1141
bogdanm	82:6473597d706e	1142	//! @brief Format value for bitfield RTC_IER_TOIE.
bogdanm	82:6473597d706e	1143	#define BF_RTC_IER_TOIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TOIE), uint32_t) & BM_RTC_IER_TOIE)
bogdanm	82:6473597d706e	1144
bogdanm	82:6473597d706e	1145	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1146	//! @brief Set the TOIE field to a new value.
bogdanm	82:6473597d706e	1147	#define BW_RTC_IER_TOIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TOIE) = (v))
bogdanm	82:6473597d706e	1148	#endif
bogdanm	82:6473597d706e	1149	//@}
bogdanm	82:6473597d706e	1150
bogdanm	82:6473597d706e	1151	/*!
bogdanm	82:6473597d706e	1152	* @name Register RTC_IER, field TAIE[2] (RW)
bogdanm	82:6473597d706e	1153	*
bogdanm	82:6473597d706e	1154	* Values:
bogdanm	82:6473597d706e	1155	* - 0 - Time alarm flag does not generate an interrupt.
bogdanm	82:6473597d706e	1156	* - 1 - Time alarm flag does generate an interrupt.
bogdanm	82:6473597d706e	1157	*/
bogdanm	82:6473597d706e	1158	//@{
bogdanm	82:6473597d706e	1159	#define BP_RTC_IER_TAIE (2U) //!< Bit position for RTC_IER_TAIE.
bogdanm	82:6473597d706e	1160	#define BM_RTC_IER_TAIE (0x00000004U) //!< Bit mask for RTC_IER_TAIE.
bogdanm	82:6473597d706e	1161	#define BS_RTC_IER_TAIE (1U) //!< Bit field size in bits for RTC_IER_TAIE.
bogdanm	82:6473597d706e	1162
bogdanm	82:6473597d706e	1163	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1164	//! @brief Read current value of the RTC_IER_TAIE field.
bogdanm	82:6473597d706e	1165	#define BR_RTC_IER_TAIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TAIE))
bogdanm	82:6473597d706e	1166	#endif
bogdanm	82:6473597d706e	1167
bogdanm	82:6473597d706e	1168	//! @brief Format value for bitfield RTC_IER_TAIE.
bogdanm	82:6473597d706e	1169	#define BF_RTC_IER_TAIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TAIE), uint32_t) & BM_RTC_IER_TAIE)
bogdanm	82:6473597d706e	1170
bogdanm	82:6473597d706e	1171	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1172	//! @brief Set the TAIE field to a new value.
bogdanm	82:6473597d706e	1173	#define BW_RTC_IER_TAIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TAIE) = (v))
bogdanm	82:6473597d706e	1174	#endif
bogdanm	82:6473597d706e	1175	//@}
bogdanm	82:6473597d706e	1176
bogdanm	82:6473597d706e	1177	/*!
bogdanm	82:6473597d706e	1178	* @name Register RTC_IER, field TSIE[4] (RW)
bogdanm	82:6473597d706e	1179	*
bogdanm	82:6473597d706e	1180	* The seconds interrupt is an edge-sensitive interrupt with a dedicated
bogdanm	82:6473597d706e	1181	* interrupt vector. It is generated once a second and requires no software overhead
bogdanm	82:6473597d706e	1182	* (there is no corresponding status flag to clear).
bogdanm	82:6473597d706e	1183	*
bogdanm	82:6473597d706e	1184	* Values:
bogdanm	82:6473597d706e	1185	* - 0 - Seconds interrupt is disabled.
bogdanm	82:6473597d706e	1186	* - 1 - Seconds interrupt is enabled.
bogdanm	82:6473597d706e	1187	*/
bogdanm	82:6473597d706e	1188	//@{
bogdanm	82:6473597d706e	1189	#define BP_RTC_IER_TSIE (4U) //!< Bit position for RTC_IER_TSIE.
bogdanm	82:6473597d706e	1190	#define BM_RTC_IER_TSIE (0x00000010U) //!< Bit mask for RTC_IER_TSIE.
bogdanm	82:6473597d706e	1191	#define BS_RTC_IER_TSIE (1U) //!< Bit field size in bits for RTC_IER_TSIE.
bogdanm	82:6473597d706e	1192
bogdanm	82:6473597d706e	1193	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1194	//! @brief Read current value of the RTC_IER_TSIE field.
bogdanm	82:6473597d706e	1195	#define BR_RTC_IER_TSIE (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TSIE))
bogdanm	82:6473597d706e	1196	#endif
bogdanm	82:6473597d706e	1197
bogdanm	82:6473597d706e	1198	//! @brief Format value for bitfield RTC_IER_TSIE.
bogdanm	82:6473597d706e	1199	#define BF_RTC_IER_TSIE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_TSIE), uint32_t) & BM_RTC_IER_TSIE)
bogdanm	82:6473597d706e	1200
bogdanm	82:6473597d706e	1201	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1202	//! @brief Set the TSIE field to a new value.
bogdanm	82:6473597d706e	1203	#define BW_RTC_IER_TSIE(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_TSIE) = (v))
bogdanm	82:6473597d706e	1204	#endif
bogdanm	82:6473597d706e	1205	//@}
bogdanm	82:6473597d706e	1206
bogdanm	82:6473597d706e	1207	/*!
bogdanm	82:6473597d706e	1208	* @name Register RTC_IER, field WPON[7] (RW)
bogdanm	82:6473597d706e	1209	*
bogdanm	82:6473597d706e	1210	* The wakeup pin is optional and not available on all devices. Whenever the
bogdanm	82:6473597d706e	1211	* wakeup pin is enabled and this bit is set, the wakeup pin will assert.
bogdanm	82:6473597d706e	1212	*
bogdanm	82:6473597d706e	1213	* Values:
bogdanm	82:6473597d706e	1214	* - 0 - No effect.
bogdanm	82:6473597d706e	1215	* - 1 - If the wakeup pin is enabled, then the wakeup pin will assert.
bogdanm	82:6473597d706e	1216	*/
bogdanm	82:6473597d706e	1217	//@{
bogdanm	82:6473597d706e	1218	#define BP_RTC_IER_WPON (7U) //!< Bit position for RTC_IER_WPON.
bogdanm	82:6473597d706e	1219	#define BM_RTC_IER_WPON (0x00000080U) //!< Bit mask for RTC_IER_WPON.
bogdanm	82:6473597d706e	1220	#define BS_RTC_IER_WPON (1U) //!< Bit field size in bits for RTC_IER_WPON.
bogdanm	82:6473597d706e	1221
bogdanm	82:6473597d706e	1222	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1223	//! @brief Read current value of the RTC_IER_WPON field.
bogdanm	82:6473597d706e	1224	#define BR_RTC_IER_WPON (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_WPON))
bogdanm	82:6473597d706e	1225	#endif
bogdanm	82:6473597d706e	1226
bogdanm	82:6473597d706e	1227	//! @brief Format value for bitfield RTC_IER_WPON.
bogdanm	82:6473597d706e	1228	#define BF_RTC_IER_WPON(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_IER_WPON), uint32_t) & BM_RTC_IER_WPON)
bogdanm	82:6473597d706e	1229
bogdanm	82:6473597d706e	1230	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1231	//! @brief Set the WPON field to a new value.
bogdanm	82:6473597d706e	1232	#define BW_RTC_IER_WPON(v) (BITBAND_ACCESS32(HW_RTC_IER_ADDR, BP_RTC_IER_WPON) = (v))
bogdanm	82:6473597d706e	1233	#endif
bogdanm	82:6473597d706e	1234	//@}
bogdanm	82:6473597d706e	1235
bogdanm	82:6473597d706e	1236	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1237	// HW_RTC_WAR - RTC Write Access Register
bogdanm	82:6473597d706e	1238	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1239
bogdanm	82:6473597d706e	1240	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1241	/*!
bogdanm	82:6473597d706e	1242	* @brief HW_RTC_WAR - RTC Write Access Register (RW)
bogdanm	82:6473597d706e	1243	*
bogdanm	82:6473597d706e	1244	* Reset value: 0x000000FFU
bogdanm	82:6473597d706e	1245	*/
bogdanm	82:6473597d706e	1246	typedef union _hw_rtc_war
bogdanm	82:6473597d706e	1247	{
bogdanm	82:6473597d706e	1248	uint32_t U;
bogdanm	82:6473597d706e	1249	struct _hw_rtc_war_bitfields
bogdanm	82:6473597d706e	1250	{
bogdanm	82:6473597d706e	1251	uint32_t TSRW : 1; //!< [0] Time Seconds Register Write
bogdanm	82:6473597d706e	1252	uint32_t TPRW : 1; //!< [1] Time Prescaler Register Write
bogdanm	82:6473597d706e	1253	uint32_t TARW : 1; //!< [2] Time Alarm Register Write
bogdanm	82:6473597d706e	1254	uint32_t TCRW : 1; //!< [3] Time Compensation Register Write
bogdanm	82:6473597d706e	1255	uint32_t CRW : 1; //!< [4] Control Register Write
bogdanm	82:6473597d706e	1256	uint32_t SRW : 1; //!< [5] Status Register Write
bogdanm	82:6473597d706e	1257	uint32_t LRW : 1; //!< [6] Lock Register Write
bogdanm	82:6473597d706e	1258	uint32_t IERW : 1; //!< [7] Interrupt Enable Register Write
bogdanm	82:6473597d706e	1259	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	1260	} B;
bogdanm	82:6473597d706e	1261	} hw_rtc_war_t;
bogdanm	82:6473597d706e	1262	#endif
bogdanm	82:6473597d706e	1263
bogdanm	82:6473597d706e	1264	/*!
bogdanm	82:6473597d706e	1265	* @name Constants and macros for entire RTC_WAR register
bogdanm	82:6473597d706e	1266	*/
bogdanm	82:6473597d706e	1267	//@{
bogdanm	82:6473597d706e	1268	#define HW_RTC_WAR_ADDR (REGS_RTC_BASE + 0x800U)
bogdanm	82:6473597d706e	1269
bogdanm	82:6473597d706e	1270	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1271	#define HW_RTC_WAR ((__IO hw_rtc_war_t ) HW_RTC_WAR_ADDR)
bogdanm	82:6473597d706e	1272	#define HW_RTC_WAR_RD() (HW_RTC_WAR.U)
bogdanm	82:6473597d706e	1273	#define HW_RTC_WAR_WR(v) (HW_RTC_WAR.U = (v))
bogdanm	82:6473597d706e	1274	#define HW_RTC_WAR_SET(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() \| (v)))
bogdanm	82:6473597d706e	1275	#define HW_RTC_WAR_CLR(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() & ~(v)))
bogdanm	82:6473597d706e	1276	#define HW_RTC_WAR_TOG(v) (HW_RTC_WAR_WR(HW_RTC_WAR_RD() ^ (v)))
bogdanm	82:6473597d706e	1277	#endif
bogdanm	82:6473597d706e	1278	//@}
bogdanm	82:6473597d706e	1279
bogdanm	82:6473597d706e	1280	/*
bogdanm	82:6473597d706e	1281	* Constants & macros for individual RTC_WAR bitfields
bogdanm	82:6473597d706e	1282	*/
bogdanm	82:6473597d706e	1283
bogdanm	82:6473597d706e	1284	/*!
bogdanm	82:6473597d706e	1285	* @name Register RTC_WAR, field TSRW[0] (RW)
bogdanm	82:6473597d706e	1286	*
bogdanm	82:6473597d706e	1287	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1288	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1289	*
bogdanm	82:6473597d706e	1290	* Values:
bogdanm	82:6473597d706e	1291	* - 0 - Writes to the Time Seconds Register are ignored.
bogdanm	82:6473597d706e	1292	* - 1 - Writes to the Time Seconds Register complete as normal.
bogdanm	82:6473597d706e	1293	*/
bogdanm	82:6473597d706e	1294	//@{
bogdanm	82:6473597d706e	1295	#define BP_RTC_WAR_TSRW (0U) //!< Bit position for RTC_WAR_TSRW.
bogdanm	82:6473597d706e	1296	#define BM_RTC_WAR_TSRW (0x00000001U) //!< Bit mask for RTC_WAR_TSRW.
bogdanm	82:6473597d706e	1297	#define BS_RTC_WAR_TSRW (1U) //!< Bit field size in bits for RTC_WAR_TSRW.
bogdanm	82:6473597d706e	1298
bogdanm	82:6473597d706e	1299	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1300	//! @brief Read current value of the RTC_WAR_TSRW field.
bogdanm	82:6473597d706e	1301	#define BR_RTC_WAR_TSRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TSRW))
bogdanm	82:6473597d706e	1302	#endif
bogdanm	82:6473597d706e	1303
bogdanm	82:6473597d706e	1304	//! @brief Format value for bitfield RTC_WAR_TSRW.
bogdanm	82:6473597d706e	1305	#define BF_RTC_WAR_TSRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TSRW), uint32_t) & BM_RTC_WAR_TSRW)
bogdanm	82:6473597d706e	1306
bogdanm	82:6473597d706e	1307	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1308	//! @brief Set the TSRW field to a new value.
bogdanm	82:6473597d706e	1309	#define BW_RTC_WAR_TSRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TSRW) = (v))
bogdanm	82:6473597d706e	1310	#endif
bogdanm	82:6473597d706e	1311	//@}
bogdanm	82:6473597d706e	1312
bogdanm	82:6473597d706e	1313	/*!
bogdanm	82:6473597d706e	1314	* @name Register RTC_WAR, field TPRW[1] (RW)
bogdanm	82:6473597d706e	1315	*
bogdanm	82:6473597d706e	1316	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1317	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1318	*
bogdanm	82:6473597d706e	1319	* Values:
bogdanm	82:6473597d706e	1320	* - 0 - Writes to the Time Prescaler Register are ignored.
bogdanm	82:6473597d706e	1321	* - 1 - Writes to the Time Prescaler Register complete as normal.
bogdanm	82:6473597d706e	1322	*/
bogdanm	82:6473597d706e	1323	//@{
bogdanm	82:6473597d706e	1324	#define BP_RTC_WAR_TPRW (1U) //!< Bit position for RTC_WAR_TPRW.
bogdanm	82:6473597d706e	1325	#define BM_RTC_WAR_TPRW (0x00000002U) //!< Bit mask for RTC_WAR_TPRW.
bogdanm	82:6473597d706e	1326	#define BS_RTC_WAR_TPRW (1U) //!< Bit field size in bits for RTC_WAR_TPRW.
bogdanm	82:6473597d706e	1327
bogdanm	82:6473597d706e	1328	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1329	//! @brief Read current value of the RTC_WAR_TPRW field.
bogdanm	82:6473597d706e	1330	#define BR_RTC_WAR_TPRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TPRW))
bogdanm	82:6473597d706e	1331	#endif
bogdanm	82:6473597d706e	1332
bogdanm	82:6473597d706e	1333	//! @brief Format value for bitfield RTC_WAR_TPRW.
bogdanm	82:6473597d706e	1334	#define BF_RTC_WAR_TPRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TPRW), uint32_t) & BM_RTC_WAR_TPRW)
bogdanm	82:6473597d706e	1335
bogdanm	82:6473597d706e	1336	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1337	//! @brief Set the TPRW field to a new value.
bogdanm	82:6473597d706e	1338	#define BW_RTC_WAR_TPRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TPRW) = (v))
bogdanm	82:6473597d706e	1339	#endif
bogdanm	82:6473597d706e	1340	//@}
bogdanm	82:6473597d706e	1341
bogdanm	82:6473597d706e	1342	/*!
bogdanm	82:6473597d706e	1343	* @name Register RTC_WAR, field TARW[2] (RW)
bogdanm	82:6473597d706e	1344	*
bogdanm	82:6473597d706e	1345	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1346	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1347	*
bogdanm	82:6473597d706e	1348	* Values:
bogdanm	82:6473597d706e	1349	* - 0 - Writes to the Time Alarm Register are ignored.
bogdanm	82:6473597d706e	1350	* - 1 - Writes to the Time Alarm Register complete as normal.
bogdanm	82:6473597d706e	1351	*/
bogdanm	82:6473597d706e	1352	//@{
bogdanm	82:6473597d706e	1353	#define BP_RTC_WAR_TARW (2U) //!< Bit position for RTC_WAR_TARW.
bogdanm	82:6473597d706e	1354	#define BM_RTC_WAR_TARW (0x00000004U) //!< Bit mask for RTC_WAR_TARW.
bogdanm	82:6473597d706e	1355	#define BS_RTC_WAR_TARW (1U) //!< Bit field size in bits for RTC_WAR_TARW.
bogdanm	82:6473597d706e	1356
bogdanm	82:6473597d706e	1357	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1358	//! @brief Read current value of the RTC_WAR_TARW field.
bogdanm	82:6473597d706e	1359	#define BR_RTC_WAR_TARW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TARW))
bogdanm	82:6473597d706e	1360	#endif
bogdanm	82:6473597d706e	1361
bogdanm	82:6473597d706e	1362	//! @brief Format value for bitfield RTC_WAR_TARW.
bogdanm	82:6473597d706e	1363	#define BF_RTC_WAR_TARW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TARW), uint32_t) & BM_RTC_WAR_TARW)
bogdanm	82:6473597d706e	1364
bogdanm	82:6473597d706e	1365	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1366	//! @brief Set the TARW field to a new value.
bogdanm	82:6473597d706e	1367	#define BW_RTC_WAR_TARW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TARW) = (v))
bogdanm	82:6473597d706e	1368	#endif
bogdanm	82:6473597d706e	1369	//@}
bogdanm	82:6473597d706e	1370
bogdanm	82:6473597d706e	1371	/*!
bogdanm	82:6473597d706e	1372	* @name Register RTC_WAR, field TCRW[3] (RW)
bogdanm	82:6473597d706e	1373	*
bogdanm	82:6473597d706e	1374	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1375	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1376	*
bogdanm	82:6473597d706e	1377	* Values:
bogdanm	82:6473597d706e	1378	* - 0 - Writes to the Time Compensation Register are ignored.
bogdanm	82:6473597d706e	1379	* - 1 - Writes to the Time Compensation Register complete as normal.
bogdanm	82:6473597d706e	1380	*/
bogdanm	82:6473597d706e	1381	//@{
bogdanm	82:6473597d706e	1382	#define BP_RTC_WAR_TCRW (3U) //!< Bit position for RTC_WAR_TCRW.
bogdanm	82:6473597d706e	1383	#define BM_RTC_WAR_TCRW (0x00000008U) //!< Bit mask for RTC_WAR_TCRW.
bogdanm	82:6473597d706e	1384	#define BS_RTC_WAR_TCRW (1U) //!< Bit field size in bits for RTC_WAR_TCRW.
bogdanm	82:6473597d706e	1385
bogdanm	82:6473597d706e	1386	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1387	//! @brief Read current value of the RTC_WAR_TCRW field.
bogdanm	82:6473597d706e	1388	#define BR_RTC_WAR_TCRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TCRW))
bogdanm	82:6473597d706e	1389	#endif
bogdanm	82:6473597d706e	1390
bogdanm	82:6473597d706e	1391	//! @brief Format value for bitfield RTC_WAR_TCRW.
bogdanm	82:6473597d706e	1392	#define BF_RTC_WAR_TCRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_TCRW), uint32_t) & BM_RTC_WAR_TCRW)
bogdanm	82:6473597d706e	1393
bogdanm	82:6473597d706e	1394	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1395	//! @brief Set the TCRW field to a new value.
bogdanm	82:6473597d706e	1396	#define BW_RTC_WAR_TCRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_TCRW) = (v))
bogdanm	82:6473597d706e	1397	#endif
bogdanm	82:6473597d706e	1398	//@}
bogdanm	82:6473597d706e	1399
bogdanm	82:6473597d706e	1400	/*!
bogdanm	82:6473597d706e	1401	* @name Register RTC_WAR, field CRW[4] (RW)
bogdanm	82:6473597d706e	1402	*
bogdanm	82:6473597d706e	1403	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1404	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1405	*
bogdanm	82:6473597d706e	1406	* Values:
bogdanm	82:6473597d706e	1407	* - 0 - Writes to the Control Register are ignored.
bogdanm	82:6473597d706e	1408	* - 1 - Writes to the Control Register complete as normal.
bogdanm	82:6473597d706e	1409	*/
bogdanm	82:6473597d706e	1410	//@{
bogdanm	82:6473597d706e	1411	#define BP_RTC_WAR_CRW (4U) //!< Bit position for RTC_WAR_CRW.
bogdanm	82:6473597d706e	1412	#define BM_RTC_WAR_CRW (0x00000010U) //!< Bit mask for RTC_WAR_CRW.
bogdanm	82:6473597d706e	1413	#define BS_RTC_WAR_CRW (1U) //!< Bit field size in bits for RTC_WAR_CRW.
bogdanm	82:6473597d706e	1414
bogdanm	82:6473597d706e	1415	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1416	//! @brief Read current value of the RTC_WAR_CRW field.
bogdanm	82:6473597d706e	1417	#define BR_RTC_WAR_CRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_CRW))
bogdanm	82:6473597d706e	1418	#endif
bogdanm	82:6473597d706e	1419
bogdanm	82:6473597d706e	1420	//! @brief Format value for bitfield RTC_WAR_CRW.
bogdanm	82:6473597d706e	1421	#define BF_RTC_WAR_CRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_CRW), uint32_t) & BM_RTC_WAR_CRW)
bogdanm	82:6473597d706e	1422
bogdanm	82:6473597d706e	1423	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1424	//! @brief Set the CRW field to a new value.
bogdanm	82:6473597d706e	1425	#define BW_RTC_WAR_CRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_CRW) = (v))
bogdanm	82:6473597d706e	1426	#endif
bogdanm	82:6473597d706e	1427	//@}
bogdanm	82:6473597d706e	1428
bogdanm	82:6473597d706e	1429	/*!
bogdanm	82:6473597d706e	1430	* @name Register RTC_WAR, field SRW[5] (RW)
bogdanm	82:6473597d706e	1431	*
bogdanm	82:6473597d706e	1432	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1433	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1434	*
bogdanm	82:6473597d706e	1435	* Values:
bogdanm	82:6473597d706e	1436	* - 0 - Writes to the Status Register are ignored.
bogdanm	82:6473597d706e	1437	* - 1 - Writes to the Status Register complete as normal.
bogdanm	82:6473597d706e	1438	*/
bogdanm	82:6473597d706e	1439	//@{
bogdanm	82:6473597d706e	1440	#define BP_RTC_WAR_SRW (5U) //!< Bit position for RTC_WAR_SRW.
bogdanm	82:6473597d706e	1441	#define BM_RTC_WAR_SRW (0x00000020U) //!< Bit mask for RTC_WAR_SRW.
bogdanm	82:6473597d706e	1442	#define BS_RTC_WAR_SRW (1U) //!< Bit field size in bits for RTC_WAR_SRW.
bogdanm	82:6473597d706e	1443
bogdanm	82:6473597d706e	1444	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1445	//! @brief Read current value of the RTC_WAR_SRW field.
bogdanm	82:6473597d706e	1446	#define BR_RTC_WAR_SRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_SRW))
bogdanm	82:6473597d706e	1447	#endif
bogdanm	82:6473597d706e	1448
bogdanm	82:6473597d706e	1449	//! @brief Format value for bitfield RTC_WAR_SRW.
bogdanm	82:6473597d706e	1450	#define BF_RTC_WAR_SRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_SRW), uint32_t) & BM_RTC_WAR_SRW)
bogdanm	82:6473597d706e	1451
bogdanm	82:6473597d706e	1452	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1453	//! @brief Set the SRW field to a new value.
bogdanm	82:6473597d706e	1454	#define BW_RTC_WAR_SRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_SRW) = (v))
bogdanm	82:6473597d706e	1455	#endif
bogdanm	82:6473597d706e	1456	//@}
bogdanm	82:6473597d706e	1457
bogdanm	82:6473597d706e	1458	/*!
bogdanm	82:6473597d706e	1459	* @name Register RTC_WAR, field LRW[6] (RW)
bogdanm	82:6473597d706e	1460	*
bogdanm	82:6473597d706e	1461	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1462	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1463	*
bogdanm	82:6473597d706e	1464	* Values:
bogdanm	82:6473597d706e	1465	* - 0 - Writes to the Lock Register are ignored.
bogdanm	82:6473597d706e	1466	* - 1 - Writes to the Lock Register complete as normal.
bogdanm	82:6473597d706e	1467	*/
bogdanm	82:6473597d706e	1468	//@{
bogdanm	82:6473597d706e	1469	#define BP_RTC_WAR_LRW (6U) //!< Bit position for RTC_WAR_LRW.
bogdanm	82:6473597d706e	1470	#define BM_RTC_WAR_LRW (0x00000040U) //!< Bit mask for RTC_WAR_LRW.
bogdanm	82:6473597d706e	1471	#define BS_RTC_WAR_LRW (1U) //!< Bit field size in bits for RTC_WAR_LRW.
bogdanm	82:6473597d706e	1472
bogdanm	82:6473597d706e	1473	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1474	//! @brief Read current value of the RTC_WAR_LRW field.
bogdanm	82:6473597d706e	1475	#define BR_RTC_WAR_LRW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_LRW))
bogdanm	82:6473597d706e	1476	#endif
bogdanm	82:6473597d706e	1477
bogdanm	82:6473597d706e	1478	//! @brief Format value for bitfield RTC_WAR_LRW.
bogdanm	82:6473597d706e	1479	#define BF_RTC_WAR_LRW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_LRW), uint32_t) & BM_RTC_WAR_LRW)
bogdanm	82:6473597d706e	1480
bogdanm	82:6473597d706e	1481	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1482	//! @brief Set the LRW field to a new value.
bogdanm	82:6473597d706e	1483	#define BW_RTC_WAR_LRW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_LRW) = (v))
bogdanm	82:6473597d706e	1484	#endif
bogdanm	82:6473597d706e	1485	//@}
bogdanm	82:6473597d706e	1486
bogdanm	82:6473597d706e	1487	/*!
bogdanm	82:6473597d706e	1488	* @name Register RTC_WAR, field IERW[7] (RW)
bogdanm	82:6473597d706e	1489	*
bogdanm	82:6473597d706e	1490	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1491	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1492	*
bogdanm	82:6473597d706e	1493	* Values:
bogdanm	82:6473597d706e	1494	* - 0 - Writes to the Interupt Enable Register are ignored.
bogdanm	82:6473597d706e	1495	* - 1 - Writes to the Interrupt Enable Register complete as normal.
bogdanm	82:6473597d706e	1496	*/
bogdanm	82:6473597d706e	1497	//@{
bogdanm	82:6473597d706e	1498	#define BP_RTC_WAR_IERW (7U) //!< Bit position for RTC_WAR_IERW.
bogdanm	82:6473597d706e	1499	#define BM_RTC_WAR_IERW (0x00000080U) //!< Bit mask for RTC_WAR_IERW.
bogdanm	82:6473597d706e	1500	#define BS_RTC_WAR_IERW (1U) //!< Bit field size in bits for RTC_WAR_IERW.
bogdanm	82:6473597d706e	1501
bogdanm	82:6473597d706e	1502	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1503	//! @brief Read current value of the RTC_WAR_IERW field.
bogdanm	82:6473597d706e	1504	#define BR_RTC_WAR_IERW (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_IERW))
bogdanm	82:6473597d706e	1505	#endif
bogdanm	82:6473597d706e	1506
bogdanm	82:6473597d706e	1507	//! @brief Format value for bitfield RTC_WAR_IERW.
bogdanm	82:6473597d706e	1508	#define BF_RTC_WAR_IERW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_WAR_IERW), uint32_t) & BM_RTC_WAR_IERW)
bogdanm	82:6473597d706e	1509
bogdanm	82:6473597d706e	1510	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1511	//! @brief Set the IERW field to a new value.
bogdanm	82:6473597d706e	1512	#define BW_RTC_WAR_IERW(v) (BITBAND_ACCESS32(HW_RTC_WAR_ADDR, BP_RTC_WAR_IERW) = (v))
bogdanm	82:6473597d706e	1513	#endif
bogdanm	82:6473597d706e	1514	//@}
bogdanm	82:6473597d706e	1515
bogdanm	82:6473597d706e	1516	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1517	// HW_RTC_RAR - RTC Read Access Register
bogdanm	82:6473597d706e	1518	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1519
bogdanm	82:6473597d706e	1520	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1521	/*!
bogdanm	82:6473597d706e	1522	* @brief HW_RTC_RAR - RTC Read Access Register (RW)
bogdanm	82:6473597d706e	1523	*
bogdanm	82:6473597d706e	1524	* Reset value: 0x000000FFU
bogdanm	82:6473597d706e	1525	*/
bogdanm	82:6473597d706e	1526	typedef union _hw_rtc_rar
bogdanm	82:6473597d706e	1527	{
bogdanm	82:6473597d706e	1528	uint32_t U;
bogdanm	82:6473597d706e	1529	struct _hw_rtc_rar_bitfields
bogdanm	82:6473597d706e	1530	{
bogdanm	82:6473597d706e	1531	uint32_t TSRR : 1; //!< [0] Time Seconds Register Read
bogdanm	82:6473597d706e	1532	uint32_t TPRR : 1; //!< [1] Time Prescaler Register Read
bogdanm	82:6473597d706e	1533	uint32_t TARR : 1; //!< [2] Time Alarm Register Read
bogdanm	82:6473597d706e	1534	uint32_t TCRR : 1; //!< [3] Time Compensation Register Read
bogdanm	82:6473597d706e	1535	uint32_t CRR : 1; //!< [4] Control Register Read
bogdanm	82:6473597d706e	1536	uint32_t SRR : 1; //!< [5] Status Register Read
bogdanm	82:6473597d706e	1537	uint32_t LRR : 1; //!< [6] Lock Register Read
bogdanm	82:6473597d706e	1538	uint32_t IERR : 1; //!< [7] Interrupt Enable Register Read
bogdanm	82:6473597d706e	1539	uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm	82:6473597d706e	1540	} B;
bogdanm	82:6473597d706e	1541	} hw_rtc_rar_t;
bogdanm	82:6473597d706e	1542	#endif
bogdanm	82:6473597d706e	1543
bogdanm	82:6473597d706e	1544	/*!
bogdanm	82:6473597d706e	1545	* @name Constants and macros for entire RTC_RAR register
bogdanm	82:6473597d706e	1546	*/
bogdanm	82:6473597d706e	1547	//@{
bogdanm	82:6473597d706e	1548	#define HW_RTC_RAR_ADDR (REGS_RTC_BASE + 0x804U)
bogdanm	82:6473597d706e	1549
bogdanm	82:6473597d706e	1550	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1551	#define HW_RTC_RAR ((__IO hw_rtc_rar_t ) HW_RTC_RAR_ADDR)
bogdanm	82:6473597d706e	1552	#define HW_RTC_RAR_RD() (HW_RTC_RAR.U)
bogdanm	82:6473597d706e	1553	#define HW_RTC_RAR_WR(v) (HW_RTC_RAR.U = (v))
bogdanm	82:6473597d706e	1554	#define HW_RTC_RAR_SET(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() \| (v)))
bogdanm	82:6473597d706e	1555	#define HW_RTC_RAR_CLR(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() & ~(v)))
bogdanm	82:6473597d706e	1556	#define HW_RTC_RAR_TOG(v) (HW_RTC_RAR_WR(HW_RTC_RAR_RD() ^ (v)))
bogdanm	82:6473597d706e	1557	#endif
bogdanm	82:6473597d706e	1558	//@}
bogdanm	82:6473597d706e	1559
bogdanm	82:6473597d706e	1560	/*
bogdanm	82:6473597d706e	1561	* Constants & macros for individual RTC_RAR bitfields
bogdanm	82:6473597d706e	1562	*/
bogdanm	82:6473597d706e	1563
bogdanm	82:6473597d706e	1564	/*!
bogdanm	82:6473597d706e	1565	* @name Register RTC_RAR, field TSRR[0] (RW)
bogdanm	82:6473597d706e	1566	*
bogdanm	82:6473597d706e	1567	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1568	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1569	*
bogdanm	82:6473597d706e	1570	* Values:
bogdanm	82:6473597d706e	1571	* - 0 - Reads to the Time Seconds Register are ignored.
bogdanm	82:6473597d706e	1572	* - 1 - Reads to the Time Seconds Register complete as normal.
bogdanm	82:6473597d706e	1573	*/
bogdanm	82:6473597d706e	1574	//@{
bogdanm	82:6473597d706e	1575	#define BP_RTC_RAR_TSRR (0U) //!< Bit position for RTC_RAR_TSRR.
bogdanm	82:6473597d706e	1576	#define BM_RTC_RAR_TSRR (0x00000001U) //!< Bit mask for RTC_RAR_TSRR.
bogdanm	82:6473597d706e	1577	#define BS_RTC_RAR_TSRR (1U) //!< Bit field size in bits for RTC_RAR_TSRR.
bogdanm	82:6473597d706e	1578
bogdanm	82:6473597d706e	1579	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1580	//! @brief Read current value of the RTC_RAR_TSRR field.
bogdanm	82:6473597d706e	1581	#define BR_RTC_RAR_TSRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TSRR))
bogdanm	82:6473597d706e	1582	#endif
bogdanm	82:6473597d706e	1583
bogdanm	82:6473597d706e	1584	//! @brief Format value for bitfield RTC_RAR_TSRR.
bogdanm	82:6473597d706e	1585	#define BF_RTC_RAR_TSRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TSRR), uint32_t) & BM_RTC_RAR_TSRR)
bogdanm	82:6473597d706e	1586
bogdanm	82:6473597d706e	1587	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1588	//! @brief Set the TSRR field to a new value.
bogdanm	82:6473597d706e	1589	#define BW_RTC_RAR_TSRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TSRR) = (v))
bogdanm	82:6473597d706e	1590	#endif
bogdanm	82:6473597d706e	1591	//@}
bogdanm	82:6473597d706e	1592
bogdanm	82:6473597d706e	1593	/*!
bogdanm	82:6473597d706e	1594	* @name Register RTC_RAR, field TPRR[1] (RW)
bogdanm	82:6473597d706e	1595	*
bogdanm	82:6473597d706e	1596	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1597	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1598	*
bogdanm	82:6473597d706e	1599	* Values:
bogdanm	82:6473597d706e	1600	* - 0 - Reads to the Time Pprescaler Register are ignored.
bogdanm	82:6473597d706e	1601	* - 1 - Reads to the Time Prescaler Register complete as normal.
bogdanm	82:6473597d706e	1602	*/
bogdanm	82:6473597d706e	1603	//@{
bogdanm	82:6473597d706e	1604	#define BP_RTC_RAR_TPRR (1U) //!< Bit position for RTC_RAR_TPRR.
bogdanm	82:6473597d706e	1605	#define BM_RTC_RAR_TPRR (0x00000002U) //!< Bit mask for RTC_RAR_TPRR.
bogdanm	82:6473597d706e	1606	#define BS_RTC_RAR_TPRR (1U) //!< Bit field size in bits for RTC_RAR_TPRR.
bogdanm	82:6473597d706e	1607
bogdanm	82:6473597d706e	1608	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1609	//! @brief Read current value of the RTC_RAR_TPRR field.
bogdanm	82:6473597d706e	1610	#define BR_RTC_RAR_TPRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TPRR))
bogdanm	82:6473597d706e	1611	#endif
bogdanm	82:6473597d706e	1612
bogdanm	82:6473597d706e	1613	//! @brief Format value for bitfield RTC_RAR_TPRR.
bogdanm	82:6473597d706e	1614	#define BF_RTC_RAR_TPRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TPRR), uint32_t) & BM_RTC_RAR_TPRR)
bogdanm	82:6473597d706e	1615
bogdanm	82:6473597d706e	1616	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1617	//! @brief Set the TPRR field to a new value.
bogdanm	82:6473597d706e	1618	#define BW_RTC_RAR_TPRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TPRR) = (v))
bogdanm	82:6473597d706e	1619	#endif
bogdanm	82:6473597d706e	1620	//@}
bogdanm	82:6473597d706e	1621
bogdanm	82:6473597d706e	1622	/*!
bogdanm	82:6473597d706e	1623	* @name Register RTC_RAR, field TARR[2] (RW)
bogdanm	82:6473597d706e	1624	*
bogdanm	82:6473597d706e	1625	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1626	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1627	*
bogdanm	82:6473597d706e	1628	* Values:
bogdanm	82:6473597d706e	1629	* - 0 - Reads to the Time Alarm Register are ignored.
bogdanm	82:6473597d706e	1630	* - 1 - Reads to the Time Alarm Register complete as normal.
bogdanm	82:6473597d706e	1631	*/
bogdanm	82:6473597d706e	1632	//@{
bogdanm	82:6473597d706e	1633	#define BP_RTC_RAR_TARR (2U) //!< Bit position for RTC_RAR_TARR.
bogdanm	82:6473597d706e	1634	#define BM_RTC_RAR_TARR (0x00000004U) //!< Bit mask for RTC_RAR_TARR.
bogdanm	82:6473597d706e	1635	#define BS_RTC_RAR_TARR (1U) //!< Bit field size in bits for RTC_RAR_TARR.
bogdanm	82:6473597d706e	1636
bogdanm	82:6473597d706e	1637	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1638	//! @brief Read current value of the RTC_RAR_TARR field.
bogdanm	82:6473597d706e	1639	#define BR_RTC_RAR_TARR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TARR))
bogdanm	82:6473597d706e	1640	#endif
bogdanm	82:6473597d706e	1641
bogdanm	82:6473597d706e	1642	//! @brief Format value for bitfield RTC_RAR_TARR.
bogdanm	82:6473597d706e	1643	#define BF_RTC_RAR_TARR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TARR), uint32_t) & BM_RTC_RAR_TARR)
bogdanm	82:6473597d706e	1644
bogdanm	82:6473597d706e	1645	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1646	//! @brief Set the TARR field to a new value.
bogdanm	82:6473597d706e	1647	#define BW_RTC_RAR_TARR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TARR) = (v))
bogdanm	82:6473597d706e	1648	#endif
bogdanm	82:6473597d706e	1649	//@}
bogdanm	82:6473597d706e	1650
bogdanm	82:6473597d706e	1651	/*!
bogdanm	82:6473597d706e	1652	* @name Register RTC_RAR, field TCRR[3] (RW)
bogdanm	82:6473597d706e	1653	*
bogdanm	82:6473597d706e	1654	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1655	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1656	*
bogdanm	82:6473597d706e	1657	* Values:
bogdanm	82:6473597d706e	1658	* - 0 - Reads to the Time Compensation Register are ignored.
bogdanm	82:6473597d706e	1659	* - 1 - Reads to the Time Compensation Register complete as normal.
bogdanm	82:6473597d706e	1660	*/
bogdanm	82:6473597d706e	1661	//@{
bogdanm	82:6473597d706e	1662	#define BP_RTC_RAR_TCRR (3U) //!< Bit position for RTC_RAR_TCRR.
bogdanm	82:6473597d706e	1663	#define BM_RTC_RAR_TCRR (0x00000008U) //!< Bit mask for RTC_RAR_TCRR.
bogdanm	82:6473597d706e	1664	#define BS_RTC_RAR_TCRR (1U) //!< Bit field size in bits for RTC_RAR_TCRR.
bogdanm	82:6473597d706e	1665
bogdanm	82:6473597d706e	1666	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1667	//! @brief Read current value of the RTC_RAR_TCRR field.
bogdanm	82:6473597d706e	1668	#define BR_RTC_RAR_TCRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TCRR))
bogdanm	82:6473597d706e	1669	#endif
bogdanm	82:6473597d706e	1670
bogdanm	82:6473597d706e	1671	//! @brief Format value for bitfield RTC_RAR_TCRR.
bogdanm	82:6473597d706e	1672	#define BF_RTC_RAR_TCRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_TCRR), uint32_t) & BM_RTC_RAR_TCRR)
bogdanm	82:6473597d706e	1673
bogdanm	82:6473597d706e	1674	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1675	//! @brief Set the TCRR field to a new value.
bogdanm	82:6473597d706e	1676	#define BW_RTC_RAR_TCRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_TCRR) = (v))
bogdanm	82:6473597d706e	1677	#endif
bogdanm	82:6473597d706e	1678	//@}
bogdanm	82:6473597d706e	1679
bogdanm	82:6473597d706e	1680	/*!
bogdanm	82:6473597d706e	1681	* @name Register RTC_RAR, field CRR[4] (RW)
bogdanm	82:6473597d706e	1682	*
bogdanm	82:6473597d706e	1683	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1684	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1685	*
bogdanm	82:6473597d706e	1686	* Values:
bogdanm	82:6473597d706e	1687	* - 0 - Reads to the Control Register are ignored.
bogdanm	82:6473597d706e	1688	* - 1 - Reads to the Control Register complete as normal.
bogdanm	82:6473597d706e	1689	*/
bogdanm	82:6473597d706e	1690	//@{
bogdanm	82:6473597d706e	1691	#define BP_RTC_RAR_CRR (4U) //!< Bit position for RTC_RAR_CRR.
bogdanm	82:6473597d706e	1692	#define BM_RTC_RAR_CRR (0x00000010U) //!< Bit mask for RTC_RAR_CRR.
bogdanm	82:6473597d706e	1693	#define BS_RTC_RAR_CRR (1U) //!< Bit field size in bits for RTC_RAR_CRR.
bogdanm	82:6473597d706e	1694
bogdanm	82:6473597d706e	1695	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1696	//! @brief Read current value of the RTC_RAR_CRR field.
bogdanm	82:6473597d706e	1697	#define BR_RTC_RAR_CRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_CRR))
bogdanm	82:6473597d706e	1698	#endif
bogdanm	82:6473597d706e	1699
bogdanm	82:6473597d706e	1700	//! @brief Format value for bitfield RTC_RAR_CRR.
bogdanm	82:6473597d706e	1701	#define BF_RTC_RAR_CRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_CRR), uint32_t) & BM_RTC_RAR_CRR)
bogdanm	82:6473597d706e	1702
bogdanm	82:6473597d706e	1703	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1704	//! @brief Set the CRR field to a new value.
bogdanm	82:6473597d706e	1705	#define BW_RTC_RAR_CRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_CRR) = (v))
bogdanm	82:6473597d706e	1706	#endif
bogdanm	82:6473597d706e	1707	//@}
bogdanm	82:6473597d706e	1708
bogdanm	82:6473597d706e	1709	/*!
bogdanm	82:6473597d706e	1710	* @name Register RTC_RAR, field SRR[5] (RW)
bogdanm	82:6473597d706e	1711	*
bogdanm	82:6473597d706e	1712	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1713	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1714	*
bogdanm	82:6473597d706e	1715	* Values:
bogdanm	82:6473597d706e	1716	* - 0 - Reads to the Status Register are ignored.
bogdanm	82:6473597d706e	1717	* - 1 - Reads to the Status Register complete as normal.
bogdanm	82:6473597d706e	1718	*/
bogdanm	82:6473597d706e	1719	//@{
bogdanm	82:6473597d706e	1720	#define BP_RTC_RAR_SRR (5U) //!< Bit position for RTC_RAR_SRR.
bogdanm	82:6473597d706e	1721	#define BM_RTC_RAR_SRR (0x00000020U) //!< Bit mask for RTC_RAR_SRR.
bogdanm	82:6473597d706e	1722	#define BS_RTC_RAR_SRR (1U) //!< Bit field size in bits for RTC_RAR_SRR.
bogdanm	82:6473597d706e	1723
bogdanm	82:6473597d706e	1724	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1725	//! @brief Read current value of the RTC_RAR_SRR field.
bogdanm	82:6473597d706e	1726	#define BR_RTC_RAR_SRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_SRR))
bogdanm	82:6473597d706e	1727	#endif
bogdanm	82:6473597d706e	1728
bogdanm	82:6473597d706e	1729	//! @brief Format value for bitfield RTC_RAR_SRR.
bogdanm	82:6473597d706e	1730	#define BF_RTC_RAR_SRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_SRR), uint32_t) & BM_RTC_RAR_SRR)
bogdanm	82:6473597d706e	1731
bogdanm	82:6473597d706e	1732	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1733	//! @brief Set the SRR field to a new value.
bogdanm	82:6473597d706e	1734	#define BW_RTC_RAR_SRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_SRR) = (v))
bogdanm	82:6473597d706e	1735	#endif
bogdanm	82:6473597d706e	1736	//@}
bogdanm	82:6473597d706e	1737
bogdanm	82:6473597d706e	1738	/*!
bogdanm	82:6473597d706e	1739	* @name Register RTC_RAR, field LRR[6] (RW)
bogdanm	82:6473597d706e	1740	*
bogdanm	82:6473597d706e	1741	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1742	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1743	*
bogdanm	82:6473597d706e	1744	* Values:
bogdanm	82:6473597d706e	1745	* - 0 - Reads to the Lock Register are ignored.
bogdanm	82:6473597d706e	1746	* - 1 - Reads to the Lock Register complete as normal.
bogdanm	82:6473597d706e	1747	*/
bogdanm	82:6473597d706e	1748	//@{
bogdanm	82:6473597d706e	1749	#define BP_RTC_RAR_LRR (6U) //!< Bit position for RTC_RAR_LRR.
bogdanm	82:6473597d706e	1750	#define BM_RTC_RAR_LRR (0x00000040U) //!< Bit mask for RTC_RAR_LRR.
bogdanm	82:6473597d706e	1751	#define BS_RTC_RAR_LRR (1U) //!< Bit field size in bits for RTC_RAR_LRR.
bogdanm	82:6473597d706e	1752
bogdanm	82:6473597d706e	1753	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1754	//! @brief Read current value of the RTC_RAR_LRR field.
bogdanm	82:6473597d706e	1755	#define BR_RTC_RAR_LRR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_LRR))
bogdanm	82:6473597d706e	1756	#endif
bogdanm	82:6473597d706e	1757
bogdanm	82:6473597d706e	1758	//! @brief Format value for bitfield RTC_RAR_LRR.
bogdanm	82:6473597d706e	1759	#define BF_RTC_RAR_LRR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_LRR), uint32_t) & BM_RTC_RAR_LRR)
bogdanm	82:6473597d706e	1760
bogdanm	82:6473597d706e	1761	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1762	//! @brief Set the LRR field to a new value.
bogdanm	82:6473597d706e	1763	#define BW_RTC_RAR_LRR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_LRR) = (v))
bogdanm	82:6473597d706e	1764	#endif
bogdanm	82:6473597d706e	1765	//@}
bogdanm	82:6473597d706e	1766
bogdanm	82:6473597d706e	1767	/*!
bogdanm	82:6473597d706e	1768	* @name Register RTC_RAR, field IERR[7] (RW)
bogdanm	82:6473597d706e	1769	*
bogdanm	82:6473597d706e	1770	* After being cleared, this bit is set only by system reset. It is not affected
bogdanm	82:6473597d706e	1771	* by VBAT POR or software reset.
bogdanm	82:6473597d706e	1772	*
bogdanm	82:6473597d706e	1773	* Values:
bogdanm	82:6473597d706e	1774	* - 0 - Reads to the Interrupt Enable Register are ignored.
bogdanm	82:6473597d706e	1775	* - 1 - Reads to the Interrupt Enable Register complete as normal.
bogdanm	82:6473597d706e	1776	*/
bogdanm	82:6473597d706e	1777	//@{
bogdanm	82:6473597d706e	1778	#define BP_RTC_RAR_IERR (7U) //!< Bit position for RTC_RAR_IERR.
bogdanm	82:6473597d706e	1779	#define BM_RTC_RAR_IERR (0x00000080U) //!< Bit mask for RTC_RAR_IERR.
bogdanm	82:6473597d706e	1780	#define BS_RTC_RAR_IERR (1U) //!< Bit field size in bits for RTC_RAR_IERR.
bogdanm	82:6473597d706e	1781
bogdanm	82:6473597d706e	1782	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1783	//! @brief Read current value of the RTC_RAR_IERR field.
bogdanm	82:6473597d706e	1784	#define BR_RTC_RAR_IERR (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_IERR))
bogdanm	82:6473597d706e	1785	#endif
bogdanm	82:6473597d706e	1786
bogdanm	82:6473597d706e	1787	//! @brief Format value for bitfield RTC_RAR_IERR.
bogdanm	82:6473597d706e	1788	#define BF_RTC_RAR_IERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RTC_RAR_IERR), uint32_t) & BM_RTC_RAR_IERR)
bogdanm	82:6473597d706e	1789
bogdanm	82:6473597d706e	1790	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1791	//! @brief Set the IERR field to a new value.
bogdanm	82:6473597d706e	1792	#define BW_RTC_RAR_IERR(v) (BITBAND_ACCESS32(HW_RTC_RAR_ADDR, BP_RTC_RAR_IERR) = (v))
bogdanm	82:6473597d706e	1793	#endif
bogdanm	82:6473597d706e	1794	//@}
bogdanm	82:6473597d706e	1795
bogdanm	82:6473597d706e	1796	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1797	// hw_rtc_t - module struct
bogdanm	82:6473597d706e	1798	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1799	/*!
bogdanm	82:6473597d706e	1800	* @brief All RTC module registers.
bogdanm	82:6473597d706e	1801	*/
bogdanm	82:6473597d706e	1802	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1803	#pragma pack(1)
bogdanm	82:6473597d706e	1804	typedef struct _hw_rtc
bogdanm	82:6473597d706e	1805	{
bogdanm	82:6473597d706e	1806	__IO hw_rtc_tsr_t TSR; //!< [0x0] RTC Time Seconds Register
bogdanm	82:6473597d706e	1807	__IO hw_rtc_tpr_t TPR; //!< [0x4] RTC Time Prescaler Register
bogdanm	82:6473597d706e	1808	__IO hw_rtc_tar_t TAR; //!< [0x8] RTC Time Alarm Register
bogdanm	82:6473597d706e	1809	__IO hw_rtc_tcr_t TCR; //!< [0xC] RTC Time Compensation Register
bogdanm	82:6473597d706e	1810	__IO hw_rtc_cr_t CR; //!< [0x10] RTC Control Register
bogdanm	82:6473597d706e	1811	__IO hw_rtc_sr_t SR; //!< [0x14] RTC Status Register
bogdanm	82:6473597d706e	1812	__IO hw_rtc_lr_t LR; //!< [0x18] RTC Lock Register
bogdanm	82:6473597d706e	1813	__IO hw_rtc_ier_t IER; //!< [0x1C] RTC Interrupt Enable Register
bogdanm	82:6473597d706e	1814	uint8_t _reserved0[2016];
bogdanm	82:6473597d706e	1815	__IO hw_rtc_war_t WAR; //!< [0x800] RTC Write Access Register
bogdanm	82:6473597d706e	1816	__IO hw_rtc_rar_t RAR; //!< [0x804] RTC Read Access Register
bogdanm	82:6473597d706e	1817	} hw_rtc_t;
bogdanm	82:6473597d706e	1818	#pragma pack()
bogdanm	82:6473597d706e	1819
bogdanm	82:6473597d706e	1820	//! @brief Macro to access all RTC registers.
bogdanm	82:6473597d706e	1821	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	1822	//! use the '&' operator, like <code>&HW_RTC</code>.
bogdanm	82:6473597d706e	1823	#define HW_RTC ((hw_rtc_t ) REGS_RTC_BASE)
bogdanm	82:6473597d706e	1824	#endif
bogdanm	82:6473597d706e	1825
bogdanm	82:6473597d706e	1826	#endif // __HW_RTC_REGISTERS_H__
bogdanm	82:6473597d706e	1827	// v22/130726/0.9
bogdanm	82:6473597d706e	1828	// EOF

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Type:	Library
Created:	31 Mar 2015
Imports:	13
Forks:	0
Commits:	99
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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rtc.h@82:6473597d706e, 2014-04-07 (annotated)

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