雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_rng.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_RNG_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_RNG_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 RNG
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * Random Number Generator Accelerator
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_RNG_CR - RNGA Control Register
bogdanm 82:6473597d706e 33 * - HW_RNG_SR - RNGA Status Register
bogdanm 82:6473597d706e 34 * - HW_RNG_ER - RNGA Entropy Register
bogdanm 82:6473597d706e 35 * - HW_RNG_OR - RNGA Output Register
bogdanm 82:6473597d706e 36 *
bogdanm 82:6473597d706e 37 * - hw_rng_t - Struct containing all module registers.
bogdanm 82:6473597d706e 38 */
bogdanm 82:6473597d706e 39
bogdanm 82:6473597d706e 40 //! @name Module base addresses
bogdanm 82:6473597d706e 41 //@{
bogdanm 82:6473597d706e 42 #ifndef REGS_RNG_BASE
bogdanm 82:6473597d706e 43 #define HW_RNG_INSTANCE_COUNT (1U) //!< Number of instances of the RNG module.
bogdanm 82:6473597d706e 44 #define REGS_RNG_BASE (0x40029000U) //!< Base address for RNG.
bogdanm 82:6473597d706e 45 #endif
bogdanm 82:6473597d706e 46 //@}
bogdanm 82:6473597d706e 47
bogdanm 82:6473597d706e 48 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 49 // HW_RNG_CR - RNGA Control Register
bogdanm 82:6473597d706e 50 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 51
bogdanm 82:6473597d706e 52 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 53 /*!
bogdanm 82:6473597d706e 54 * @brief HW_RNG_CR - RNGA Control Register (RW)
bogdanm 82:6473597d706e 55 *
bogdanm 82:6473597d706e 56 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 57 *
bogdanm 82:6473597d706e 58 * Controls the operation of RNGA.
bogdanm 82:6473597d706e 59 */
bogdanm 82:6473597d706e 60 typedef union _hw_rng_cr
bogdanm 82:6473597d706e 61 {
bogdanm 82:6473597d706e 62 uint32_t U;
bogdanm 82:6473597d706e 63 struct _hw_rng_cr_bitfields
bogdanm 82:6473597d706e 64 {
bogdanm 82:6473597d706e 65 uint32_t GO : 1; //!< [0] Go
bogdanm 82:6473597d706e 66 uint32_t HA : 1; //!< [1] High Assurance
bogdanm 82:6473597d706e 67 uint32_t INTM : 1; //!< [2] Interrupt Mask
bogdanm 82:6473597d706e 68 uint32_t CLRI : 1; //!< [3] Clear Interrupt
bogdanm 82:6473597d706e 69 uint32_t SLP : 1; //!< [4] Sleep
bogdanm 82:6473597d706e 70 uint32_t RESERVED0 : 27; //!< [31:5]
bogdanm 82:6473597d706e 71 } B;
bogdanm 82:6473597d706e 72 } hw_rng_cr_t;
bogdanm 82:6473597d706e 73 #endif
bogdanm 82:6473597d706e 74
bogdanm 82:6473597d706e 75 /*!
bogdanm 82:6473597d706e 76 * @name Constants and macros for entire RNG_CR register
bogdanm 82:6473597d706e 77 */
bogdanm 82:6473597d706e 78 //@{
bogdanm 82:6473597d706e 79 #define HW_RNG_CR_ADDR (REGS_RNG_BASE + 0x0U)
bogdanm 82:6473597d706e 80
bogdanm 82:6473597d706e 81 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 82 #define HW_RNG_CR (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR)
bogdanm 82:6473597d706e 83 #define HW_RNG_CR_RD() (HW_RNG_CR.U)
bogdanm 82:6473597d706e 84 #define HW_RNG_CR_WR(v) (HW_RNG_CR.U = (v))
bogdanm 82:6473597d706e 85 #define HW_RNG_CR_SET(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() | (v)))
bogdanm 82:6473597d706e 86 #define HW_RNG_CR_CLR(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() & ~(v)))
bogdanm 82:6473597d706e 87 #define HW_RNG_CR_TOG(v) (HW_RNG_CR_WR(HW_RNG_CR_RD() ^ (v)))
bogdanm 82:6473597d706e 88 #endif
bogdanm 82:6473597d706e 89 //@}
bogdanm 82:6473597d706e 90
bogdanm 82:6473597d706e 91 /*
bogdanm 82:6473597d706e 92 * Constants & macros for individual RNG_CR bitfields
bogdanm 82:6473597d706e 93 */
bogdanm 82:6473597d706e 94
bogdanm 82:6473597d706e 95 /*!
bogdanm 82:6473597d706e 96 * @name Register RNG_CR, field GO[0] (RW)
bogdanm 82:6473597d706e 97 *
bogdanm 82:6473597d706e 98 * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
bogdanm 82:6473597d706e 99 * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
bogdanm 82:6473597d706e 100 * OR[RANDOUT] with data.
bogdanm 82:6473597d706e 101 *
bogdanm 82:6473597d706e 102 * Values:
bogdanm 82:6473597d706e 103 * - 0 - Disabled
bogdanm 82:6473597d706e 104 * - 1 - Enabled
bogdanm 82:6473597d706e 105 */
bogdanm 82:6473597d706e 106 //@{
bogdanm 82:6473597d706e 107 #define BP_RNG_CR_GO (0U) //!< Bit position for RNG_CR_GO.
bogdanm 82:6473597d706e 108 #define BM_RNG_CR_GO (0x00000001U) //!< Bit mask for RNG_CR_GO.
bogdanm 82:6473597d706e 109 #define BS_RNG_CR_GO (1U) //!< Bit field size in bits for RNG_CR_GO.
bogdanm 82:6473597d706e 110
bogdanm 82:6473597d706e 111 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 112 //! @brief Read current value of the RNG_CR_GO field.
bogdanm 82:6473597d706e 113 #define BR_RNG_CR_GO (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO))
bogdanm 82:6473597d706e 114 #endif
bogdanm 82:6473597d706e 115
bogdanm 82:6473597d706e 116 //! @brief Format value for bitfield RNG_CR_GO.
bogdanm 82:6473597d706e 117 #define BF_RNG_CR_GO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_GO), uint32_t) & BM_RNG_CR_GO)
bogdanm 82:6473597d706e 118
bogdanm 82:6473597d706e 119 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 120 //! @brief Set the GO field to a new value.
bogdanm 82:6473597d706e 121 #define BW_RNG_CR_GO(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_GO) = (v))
bogdanm 82:6473597d706e 122 #endif
bogdanm 82:6473597d706e 123 //@}
bogdanm 82:6473597d706e 124
bogdanm 82:6473597d706e 125 /*!
bogdanm 82:6473597d706e 126 * @name Register RNG_CR, field HA[1] (RW)
bogdanm 82:6473597d706e 127 *
bogdanm 82:6473597d706e 128 * Enables notification of security violations (via SR[SECV]). A security
bogdanm 82:6473597d706e 129 * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
bogdanm 82:6473597d706e 130 * After enabling notification of security violations, you must reset RNGA to
bogdanm 82:6473597d706e 131 * disable them again.
bogdanm 82:6473597d706e 132 *
bogdanm 82:6473597d706e 133 * Values:
bogdanm 82:6473597d706e 134 * - 0 - Disabled
bogdanm 82:6473597d706e 135 * - 1 - Enabled
bogdanm 82:6473597d706e 136 */
bogdanm 82:6473597d706e 137 //@{
bogdanm 82:6473597d706e 138 #define BP_RNG_CR_HA (1U) //!< Bit position for RNG_CR_HA.
bogdanm 82:6473597d706e 139 #define BM_RNG_CR_HA (0x00000002U) //!< Bit mask for RNG_CR_HA.
bogdanm 82:6473597d706e 140 #define BS_RNG_CR_HA (1U) //!< Bit field size in bits for RNG_CR_HA.
bogdanm 82:6473597d706e 141
bogdanm 82:6473597d706e 142 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 143 //! @brief Read current value of the RNG_CR_HA field.
bogdanm 82:6473597d706e 144 #define BR_RNG_CR_HA (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA))
bogdanm 82:6473597d706e 145 #endif
bogdanm 82:6473597d706e 146
bogdanm 82:6473597d706e 147 //! @brief Format value for bitfield RNG_CR_HA.
bogdanm 82:6473597d706e 148 #define BF_RNG_CR_HA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_HA), uint32_t) & BM_RNG_CR_HA)
bogdanm 82:6473597d706e 149
bogdanm 82:6473597d706e 150 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 151 //! @brief Set the HA field to a new value.
bogdanm 82:6473597d706e 152 #define BW_RNG_CR_HA(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_HA) = (v))
bogdanm 82:6473597d706e 153 #endif
bogdanm 82:6473597d706e 154 //@}
bogdanm 82:6473597d706e 155
bogdanm 82:6473597d706e 156 /*!
bogdanm 82:6473597d706e 157 * @name Register RNG_CR, field INTM[2] (RW)
bogdanm 82:6473597d706e 158 *
bogdanm 82:6473597d706e 159 * Masks the triggering of an error interrupt to the interrupt controller when
bogdanm 82:6473597d706e 160 * an OR underflow condition occurs. An OR underflow condition occurs when you
bogdanm 82:6473597d706e 161 * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
bogdanm 82:6473597d706e 162 *
bogdanm 82:6473597d706e 163 * Values:
bogdanm 82:6473597d706e 164 * - 0 - Not masked
bogdanm 82:6473597d706e 165 * - 1 - Masked
bogdanm 82:6473597d706e 166 */
bogdanm 82:6473597d706e 167 //@{
bogdanm 82:6473597d706e 168 #define BP_RNG_CR_INTM (2U) //!< Bit position for RNG_CR_INTM.
bogdanm 82:6473597d706e 169 #define BM_RNG_CR_INTM (0x00000004U) //!< Bit mask for RNG_CR_INTM.
bogdanm 82:6473597d706e 170 #define BS_RNG_CR_INTM (1U) //!< Bit field size in bits for RNG_CR_INTM.
bogdanm 82:6473597d706e 171
bogdanm 82:6473597d706e 172 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 173 //! @brief Read current value of the RNG_CR_INTM field.
bogdanm 82:6473597d706e 174 #define BR_RNG_CR_INTM (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM))
bogdanm 82:6473597d706e 175 #endif
bogdanm 82:6473597d706e 176
bogdanm 82:6473597d706e 177 //! @brief Format value for bitfield RNG_CR_INTM.
bogdanm 82:6473597d706e 178 #define BF_RNG_CR_INTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_INTM), uint32_t) & BM_RNG_CR_INTM)
bogdanm 82:6473597d706e 179
bogdanm 82:6473597d706e 180 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 181 //! @brief Set the INTM field to a new value.
bogdanm 82:6473597d706e 182 #define BW_RNG_CR_INTM(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_INTM) = (v))
bogdanm 82:6473597d706e 183 #endif
bogdanm 82:6473597d706e 184 //@}
bogdanm 82:6473597d706e 185
bogdanm 82:6473597d706e 186 /*!
bogdanm 82:6473597d706e 187 * @name Register RNG_CR, field CLRI[3] (WORZ)
bogdanm 82:6473597d706e 188 *
bogdanm 82:6473597d706e 189 * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
bogdanm 82:6473597d706e 190 *
bogdanm 82:6473597d706e 191 * Values:
bogdanm 82:6473597d706e 192 * - 0 - Do not clear the interrupt.
bogdanm 82:6473597d706e 193 * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
bogdanm 82:6473597d706e 194 * the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
bogdanm 82:6473597d706e 195 */
bogdanm 82:6473597d706e 196 //@{
bogdanm 82:6473597d706e 197 #define BP_RNG_CR_CLRI (3U) //!< Bit position for RNG_CR_CLRI.
bogdanm 82:6473597d706e 198 #define BM_RNG_CR_CLRI (0x00000008U) //!< Bit mask for RNG_CR_CLRI.
bogdanm 82:6473597d706e 199 #define BS_RNG_CR_CLRI (1U) //!< Bit field size in bits for RNG_CR_CLRI.
bogdanm 82:6473597d706e 200
bogdanm 82:6473597d706e 201 //! @brief Format value for bitfield RNG_CR_CLRI.
bogdanm 82:6473597d706e 202 #define BF_RNG_CR_CLRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_CLRI), uint32_t) & BM_RNG_CR_CLRI)
bogdanm 82:6473597d706e 203
bogdanm 82:6473597d706e 204 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 205 //! @brief Set the CLRI field to a new value.
bogdanm 82:6473597d706e 206 #define BW_RNG_CR_CLRI(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_CLRI) = (v))
bogdanm 82:6473597d706e 207 #endif
bogdanm 82:6473597d706e 208 //@}
bogdanm 82:6473597d706e 209
bogdanm 82:6473597d706e 210 /*!
bogdanm 82:6473597d706e 211 * @name Register RNG_CR, field SLP[4] (RW)
bogdanm 82:6473597d706e 212 *
bogdanm 82:6473597d706e 213 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
bogdanm 82:6473597d706e 214 * mode by asserting the DOZE signal.
bogdanm 82:6473597d706e 215 *
bogdanm 82:6473597d706e 216 * Values:
bogdanm 82:6473597d706e 217 * - 0 - Normal mode
bogdanm 82:6473597d706e 218 * - 1 - Sleep (low-power) mode
bogdanm 82:6473597d706e 219 */
bogdanm 82:6473597d706e 220 //@{
bogdanm 82:6473597d706e 221 #define BP_RNG_CR_SLP (4U) //!< Bit position for RNG_CR_SLP.
bogdanm 82:6473597d706e 222 #define BM_RNG_CR_SLP (0x00000010U) //!< Bit mask for RNG_CR_SLP.
bogdanm 82:6473597d706e 223 #define BS_RNG_CR_SLP (1U) //!< Bit field size in bits for RNG_CR_SLP.
bogdanm 82:6473597d706e 224
bogdanm 82:6473597d706e 225 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 226 //! @brief Read current value of the RNG_CR_SLP field.
bogdanm 82:6473597d706e 227 #define BR_RNG_CR_SLP (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP))
bogdanm 82:6473597d706e 228 #endif
bogdanm 82:6473597d706e 229
bogdanm 82:6473597d706e 230 //! @brief Format value for bitfield RNG_CR_SLP.
bogdanm 82:6473597d706e 231 #define BF_RNG_CR_SLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_CR_SLP), uint32_t) & BM_RNG_CR_SLP)
bogdanm 82:6473597d706e 232
bogdanm 82:6473597d706e 233 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 234 //! @brief Set the SLP field to a new value.
bogdanm 82:6473597d706e 235 #define BW_RNG_CR_SLP(v) (BITBAND_ACCESS32(HW_RNG_CR_ADDR, BP_RNG_CR_SLP) = (v))
bogdanm 82:6473597d706e 236 #endif
bogdanm 82:6473597d706e 237 //@}
bogdanm 82:6473597d706e 238
bogdanm 82:6473597d706e 239 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 240 // HW_RNG_SR - RNGA Status Register
bogdanm 82:6473597d706e 241 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 242
bogdanm 82:6473597d706e 243 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 244 /*!
bogdanm 82:6473597d706e 245 * @brief HW_RNG_SR - RNGA Status Register (RO)
bogdanm 82:6473597d706e 246 *
bogdanm 82:6473597d706e 247 * Reset value: 0x00010000U
bogdanm 82:6473597d706e 248 *
bogdanm 82:6473597d706e 249 * Indicates the status of RNGA. This register is read-only.
bogdanm 82:6473597d706e 250 */
bogdanm 82:6473597d706e 251 typedef union _hw_rng_sr
bogdanm 82:6473597d706e 252 {
bogdanm 82:6473597d706e 253 uint32_t U;
bogdanm 82:6473597d706e 254 struct _hw_rng_sr_bitfields
bogdanm 82:6473597d706e 255 {
bogdanm 82:6473597d706e 256 uint32_t SECV : 1; //!< [0] Security Violation
bogdanm 82:6473597d706e 257 uint32_t LRS : 1; //!< [1] Last Read Status
bogdanm 82:6473597d706e 258 uint32_t ORU : 1; //!< [2] Output Register Underflow
bogdanm 82:6473597d706e 259 uint32_t ERRI : 1; //!< [3] Error Interrupt
bogdanm 82:6473597d706e 260 uint32_t SLP : 1; //!< [4] Sleep
bogdanm 82:6473597d706e 261 uint32_t RESERVED0 : 3; //!< [7:5]
bogdanm 82:6473597d706e 262 uint32_t OREG_LVL : 8; //!< [15:8] Output Register Level
bogdanm 82:6473597d706e 263 uint32_t OREG_SIZE : 8; //!< [23:16] Output Register Size
bogdanm 82:6473597d706e 264 uint32_t RESERVED1 : 8; //!< [31:24]
bogdanm 82:6473597d706e 265 } B;
bogdanm 82:6473597d706e 266 } hw_rng_sr_t;
bogdanm 82:6473597d706e 267 #endif
bogdanm 82:6473597d706e 268
bogdanm 82:6473597d706e 269 /*!
bogdanm 82:6473597d706e 270 * @name Constants and macros for entire RNG_SR register
bogdanm 82:6473597d706e 271 */
bogdanm 82:6473597d706e 272 //@{
bogdanm 82:6473597d706e 273 #define HW_RNG_SR_ADDR (REGS_RNG_BASE + 0x4U)
bogdanm 82:6473597d706e 274
bogdanm 82:6473597d706e 275 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 276 #define HW_RNG_SR (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR)
bogdanm 82:6473597d706e 277 #define HW_RNG_SR_RD() (HW_RNG_SR.U)
bogdanm 82:6473597d706e 278 #endif
bogdanm 82:6473597d706e 279 //@}
bogdanm 82:6473597d706e 280
bogdanm 82:6473597d706e 281 /*
bogdanm 82:6473597d706e 282 * Constants & macros for individual RNG_SR bitfields
bogdanm 82:6473597d706e 283 */
bogdanm 82:6473597d706e 284
bogdanm 82:6473597d706e 285 /*!
bogdanm 82:6473597d706e 286 * @name Register RNG_SR, field SECV[0] (RO)
bogdanm 82:6473597d706e 287 *
bogdanm 82:6473597d706e 288 * Used only when high assurance is enabled (CR[HA]). Indicates that a security
bogdanm 82:6473597d706e 289 * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
bogdanm 82:6473597d706e 290 * RNGA.
bogdanm 82:6473597d706e 291 *
bogdanm 82:6473597d706e 292 * Values:
bogdanm 82:6473597d706e 293 * - 0 - No security violation
bogdanm 82:6473597d706e 294 * - 1 - Security violation
bogdanm 82:6473597d706e 295 */
bogdanm 82:6473597d706e 296 //@{
bogdanm 82:6473597d706e 297 #define BP_RNG_SR_SECV (0U) //!< Bit position for RNG_SR_SECV.
bogdanm 82:6473597d706e 298 #define BM_RNG_SR_SECV (0x00000001U) //!< Bit mask for RNG_SR_SECV.
bogdanm 82:6473597d706e 299 #define BS_RNG_SR_SECV (1U) //!< Bit field size in bits for RNG_SR_SECV.
bogdanm 82:6473597d706e 300
bogdanm 82:6473597d706e 301 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 302 //! @brief Read current value of the RNG_SR_SECV field.
bogdanm 82:6473597d706e 303 #define BR_RNG_SR_SECV (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SECV))
bogdanm 82:6473597d706e 304 #endif
bogdanm 82:6473597d706e 305 //@}
bogdanm 82:6473597d706e 306
bogdanm 82:6473597d706e 307 /*!
bogdanm 82:6473597d706e 308 * @name Register RNG_SR, field LRS[1] (RO)
bogdanm 82:6473597d706e 309 *
bogdanm 82:6473597d706e 310 * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
bogdanm 82:6473597d706e 311 * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
bogdanm 82:6473597d706e 312 * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
bogdanm 82:6473597d706e 313 * After you read this register, RNGA writes 0 to this field.
bogdanm 82:6473597d706e 314 *
bogdanm 82:6473597d706e 315 * Values:
bogdanm 82:6473597d706e 316 * - 0 - No underflow
bogdanm 82:6473597d706e 317 * - 1 - Underflow
bogdanm 82:6473597d706e 318 */
bogdanm 82:6473597d706e 319 //@{
bogdanm 82:6473597d706e 320 #define BP_RNG_SR_LRS (1U) //!< Bit position for RNG_SR_LRS.
bogdanm 82:6473597d706e 321 #define BM_RNG_SR_LRS (0x00000002U) //!< Bit mask for RNG_SR_LRS.
bogdanm 82:6473597d706e 322 #define BS_RNG_SR_LRS (1U) //!< Bit field size in bits for RNG_SR_LRS.
bogdanm 82:6473597d706e 323
bogdanm 82:6473597d706e 324 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 325 //! @brief Read current value of the RNG_SR_LRS field.
bogdanm 82:6473597d706e 326 #define BR_RNG_SR_LRS (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_LRS))
bogdanm 82:6473597d706e 327 #endif
bogdanm 82:6473597d706e 328 //@}
bogdanm 82:6473597d706e 329
bogdanm 82:6473597d706e 330 /*!
bogdanm 82:6473597d706e 331 * @name Register RNG_SR, field ORU[2] (RO)
bogdanm 82:6473597d706e 332 *
bogdanm 82:6473597d706e 333 * Indicates whether an OR underflow condition has occurred since you last read
bogdanm 82:6473597d706e 334 * this register (SR) or RNGA was reset, regardless of whether the error
bogdanm 82:6473597d706e 335 * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
bogdanm 82:6473597d706e 336 * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
bogdanm 82:6473597d706e 337 * field.
bogdanm 82:6473597d706e 338 *
bogdanm 82:6473597d706e 339 * Values:
bogdanm 82:6473597d706e 340 * - 0 - No underflow
bogdanm 82:6473597d706e 341 * - 1 - Underflow
bogdanm 82:6473597d706e 342 */
bogdanm 82:6473597d706e 343 //@{
bogdanm 82:6473597d706e 344 #define BP_RNG_SR_ORU (2U) //!< Bit position for RNG_SR_ORU.
bogdanm 82:6473597d706e 345 #define BM_RNG_SR_ORU (0x00000004U) //!< Bit mask for RNG_SR_ORU.
bogdanm 82:6473597d706e 346 #define BS_RNG_SR_ORU (1U) //!< Bit field size in bits for RNG_SR_ORU.
bogdanm 82:6473597d706e 347
bogdanm 82:6473597d706e 348 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 349 //! @brief Read current value of the RNG_SR_ORU field.
bogdanm 82:6473597d706e 350 #define BR_RNG_SR_ORU (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ORU))
bogdanm 82:6473597d706e 351 #endif
bogdanm 82:6473597d706e 352 //@}
bogdanm 82:6473597d706e 353
bogdanm 82:6473597d706e 354 /*!
bogdanm 82:6473597d706e 355 * @name Register RNG_SR, field ERRI[3] (RO)
bogdanm 82:6473597d706e 356 *
bogdanm 82:6473597d706e 357 * Indicates whether an OR underflow condition has occurred since you last
bogdanm 82:6473597d706e 358 * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
bogdanm 82:6473597d706e 359 * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
bogdanm 82:6473597d706e 360 * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
bogdanm 82:6473597d706e 361 * indicator (via CR[CLRI]), RNGA writes 0 to this field.
bogdanm 82:6473597d706e 362 *
bogdanm 82:6473597d706e 363 * Values:
bogdanm 82:6473597d706e 364 * - 0 - No underflow
bogdanm 82:6473597d706e 365 * - 1 - Underflow
bogdanm 82:6473597d706e 366 */
bogdanm 82:6473597d706e 367 //@{
bogdanm 82:6473597d706e 368 #define BP_RNG_SR_ERRI (3U) //!< Bit position for RNG_SR_ERRI.
bogdanm 82:6473597d706e 369 #define BM_RNG_SR_ERRI (0x00000008U) //!< Bit mask for RNG_SR_ERRI.
bogdanm 82:6473597d706e 370 #define BS_RNG_SR_ERRI (1U) //!< Bit field size in bits for RNG_SR_ERRI.
bogdanm 82:6473597d706e 371
bogdanm 82:6473597d706e 372 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 373 //! @brief Read current value of the RNG_SR_ERRI field.
bogdanm 82:6473597d706e 374 #define BR_RNG_SR_ERRI (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_ERRI))
bogdanm 82:6473597d706e 375 #endif
bogdanm 82:6473597d706e 376 //@}
bogdanm 82:6473597d706e 377
bogdanm 82:6473597d706e 378 /*!
bogdanm 82:6473597d706e 379 * @name Register RNG_SR, field SLP[4] (RO)
bogdanm 82:6473597d706e 380 *
bogdanm 82:6473597d706e 381 * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
bogdanm 82:6473597d706e 382 * mode by asserting the DOZE signal.
bogdanm 82:6473597d706e 383 *
bogdanm 82:6473597d706e 384 * Values:
bogdanm 82:6473597d706e 385 * - 0 - Normal mode
bogdanm 82:6473597d706e 386 * - 1 - Sleep (low-power) mode
bogdanm 82:6473597d706e 387 */
bogdanm 82:6473597d706e 388 //@{
bogdanm 82:6473597d706e 389 #define BP_RNG_SR_SLP (4U) //!< Bit position for RNG_SR_SLP.
bogdanm 82:6473597d706e 390 #define BM_RNG_SR_SLP (0x00000010U) //!< Bit mask for RNG_SR_SLP.
bogdanm 82:6473597d706e 391 #define BS_RNG_SR_SLP (1U) //!< Bit field size in bits for RNG_SR_SLP.
bogdanm 82:6473597d706e 392
bogdanm 82:6473597d706e 393 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 394 //! @brief Read current value of the RNG_SR_SLP field.
bogdanm 82:6473597d706e 395 #define BR_RNG_SR_SLP (BITBAND_ACCESS32(HW_RNG_SR_ADDR, BP_RNG_SR_SLP))
bogdanm 82:6473597d706e 396 #endif
bogdanm 82:6473597d706e 397 //@}
bogdanm 82:6473597d706e 398
bogdanm 82:6473597d706e 399 /*!
bogdanm 82:6473597d706e 400 * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
bogdanm 82:6473597d706e 401 *
bogdanm 82:6473597d706e 402 * Indicates the number of random-data words that are in OR[RANDOUT], which
bogdanm 82:6473597d706e 403 * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
bogdanm 82:6473597d706e 404 * is not 0, then the contents of a random number contained in OR[RANDOUT] are
bogdanm 82:6473597d706e 405 * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
bogdanm 82:6473597d706e 406 *
bogdanm 82:6473597d706e 407 * Values:
bogdanm 82:6473597d706e 408 * - 0 - No words (empty)
bogdanm 82:6473597d706e 409 * - 1 - One word (valid)
bogdanm 82:6473597d706e 410 */
bogdanm 82:6473597d706e 411 //@{
bogdanm 82:6473597d706e 412 #define BP_RNG_SR_OREG_LVL (8U) //!< Bit position for RNG_SR_OREG_LVL.
bogdanm 82:6473597d706e 413 #define BM_RNG_SR_OREG_LVL (0x0000FF00U) //!< Bit mask for RNG_SR_OREG_LVL.
bogdanm 82:6473597d706e 414 #define BS_RNG_SR_OREG_LVL (8U) //!< Bit field size in bits for RNG_SR_OREG_LVL.
bogdanm 82:6473597d706e 415
bogdanm 82:6473597d706e 416 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 417 //! @brief Read current value of the RNG_SR_OREG_LVL field.
bogdanm 82:6473597d706e 418 #define BR_RNG_SR_OREG_LVL (HW_RNG_SR.B.OREG_LVL)
bogdanm 82:6473597d706e 419 #endif
bogdanm 82:6473597d706e 420 //@}
bogdanm 82:6473597d706e 421
bogdanm 82:6473597d706e 422 /*!
bogdanm 82:6473597d706e 423 * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
bogdanm 82:6473597d706e 424 *
bogdanm 82:6473597d706e 425 * Indicates the size of the Output (OR) register in terms of the number of
bogdanm 82:6473597d706e 426 * 32-bit random-data words it can hold.
bogdanm 82:6473597d706e 427 *
bogdanm 82:6473597d706e 428 * Values:
bogdanm 82:6473597d706e 429 * - 1 - One word (this value is fixed)
bogdanm 82:6473597d706e 430 */
bogdanm 82:6473597d706e 431 //@{
bogdanm 82:6473597d706e 432 #define BP_RNG_SR_OREG_SIZE (16U) //!< Bit position for RNG_SR_OREG_SIZE.
bogdanm 82:6473597d706e 433 #define BM_RNG_SR_OREG_SIZE (0x00FF0000U) //!< Bit mask for RNG_SR_OREG_SIZE.
bogdanm 82:6473597d706e 434 #define BS_RNG_SR_OREG_SIZE (8U) //!< Bit field size in bits for RNG_SR_OREG_SIZE.
bogdanm 82:6473597d706e 435
bogdanm 82:6473597d706e 436 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 437 //! @brief Read current value of the RNG_SR_OREG_SIZE field.
bogdanm 82:6473597d706e 438 #define BR_RNG_SR_OREG_SIZE (HW_RNG_SR.B.OREG_SIZE)
bogdanm 82:6473597d706e 439 #endif
bogdanm 82:6473597d706e 440 //@}
bogdanm 82:6473597d706e 441
bogdanm 82:6473597d706e 442 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 443 // HW_RNG_ER - RNGA Entropy Register
bogdanm 82:6473597d706e 444 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 445
bogdanm 82:6473597d706e 446 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 447 /*!
bogdanm 82:6473597d706e 448 * @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
bogdanm 82:6473597d706e 449 *
bogdanm 82:6473597d706e 450 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 451 *
bogdanm 82:6473597d706e 452 * Specifies an entropy value that RNGA uses in addition to its ring oscillators
bogdanm 82:6473597d706e 453 * to seed its pseudorandom algorithm. This is a write-only register; reads
bogdanm 82:6473597d706e 454 * return all zeros.
bogdanm 82:6473597d706e 455 */
bogdanm 82:6473597d706e 456 typedef union _hw_rng_er
bogdanm 82:6473597d706e 457 {
bogdanm 82:6473597d706e 458 uint32_t U;
bogdanm 82:6473597d706e 459 struct _hw_rng_er_bitfields
bogdanm 82:6473597d706e 460 {
bogdanm 82:6473597d706e 461 uint32_t EXT_ENT : 32; //!< [31:0] External Entropy
bogdanm 82:6473597d706e 462 } B;
bogdanm 82:6473597d706e 463 } hw_rng_er_t;
bogdanm 82:6473597d706e 464 #endif
bogdanm 82:6473597d706e 465
bogdanm 82:6473597d706e 466 /*!
bogdanm 82:6473597d706e 467 * @name Constants and macros for entire RNG_ER register
bogdanm 82:6473597d706e 468 */
bogdanm 82:6473597d706e 469 //@{
bogdanm 82:6473597d706e 470 #define HW_RNG_ER_ADDR (REGS_RNG_BASE + 0x8U)
bogdanm 82:6473597d706e 471
bogdanm 82:6473597d706e 472 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 473 #define HW_RNG_ER (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR)
bogdanm 82:6473597d706e 474 #define HW_RNG_ER_RD() (HW_RNG_ER.U)
bogdanm 82:6473597d706e 475 #define HW_RNG_ER_WR(v) (HW_RNG_ER.U = (v))
bogdanm 82:6473597d706e 476 #endif
bogdanm 82:6473597d706e 477 //@}
bogdanm 82:6473597d706e 478
bogdanm 82:6473597d706e 479 /*
bogdanm 82:6473597d706e 480 * Constants & macros for individual RNG_ER bitfields
bogdanm 82:6473597d706e 481 */
bogdanm 82:6473597d706e 482
bogdanm 82:6473597d706e 483 /*!
bogdanm 82:6473597d706e 484 * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
bogdanm 82:6473597d706e 485 *
bogdanm 82:6473597d706e 486 * Specifies an entropy value that RNGA uses in addition to its ring oscillators
bogdanm 82:6473597d706e 487 * to seed its pseudorandom algorithm.Specifying a value for this field is
bogdanm 82:6473597d706e 488 * optional but recommended. You can write to this field at any time during operation.
bogdanm 82:6473597d706e 489 */
bogdanm 82:6473597d706e 490 //@{
bogdanm 82:6473597d706e 491 #define BP_RNG_ER_EXT_ENT (0U) //!< Bit position for RNG_ER_EXT_ENT.
bogdanm 82:6473597d706e 492 #define BM_RNG_ER_EXT_ENT (0xFFFFFFFFU) //!< Bit mask for RNG_ER_EXT_ENT.
bogdanm 82:6473597d706e 493 #define BS_RNG_ER_EXT_ENT (32U) //!< Bit field size in bits for RNG_ER_EXT_ENT.
bogdanm 82:6473597d706e 494
bogdanm 82:6473597d706e 495 //! @brief Format value for bitfield RNG_ER_EXT_ENT.
bogdanm 82:6473597d706e 496 #define BF_RNG_ER_EXT_ENT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_RNG_ER_EXT_ENT), uint32_t) & BM_RNG_ER_EXT_ENT)
bogdanm 82:6473597d706e 497
bogdanm 82:6473597d706e 498 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 499 //! @brief Set the EXT_ENT field to a new value.
bogdanm 82:6473597d706e 500 #define BW_RNG_ER_EXT_ENT(v) (HW_RNG_ER_WR(v))
bogdanm 82:6473597d706e 501 #endif
bogdanm 82:6473597d706e 502 //@}
bogdanm 82:6473597d706e 503
bogdanm 82:6473597d706e 504 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 505 // HW_RNG_OR - RNGA Output Register
bogdanm 82:6473597d706e 506 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 507
bogdanm 82:6473597d706e 508 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 509 /*!
bogdanm 82:6473597d706e 510 * @brief HW_RNG_OR - RNGA Output Register (RO)
bogdanm 82:6473597d706e 511 *
bogdanm 82:6473597d706e 512 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 513 *
bogdanm 82:6473597d706e 514 * Stores a random-data word generated by RNGA.
bogdanm 82:6473597d706e 515 */
bogdanm 82:6473597d706e 516 typedef union _hw_rng_or
bogdanm 82:6473597d706e 517 {
bogdanm 82:6473597d706e 518 uint32_t U;
bogdanm 82:6473597d706e 519 struct _hw_rng_or_bitfields
bogdanm 82:6473597d706e 520 {
bogdanm 82:6473597d706e 521 uint32_t RANDOUT : 32; //!< [31:0] Random Output
bogdanm 82:6473597d706e 522 } B;
bogdanm 82:6473597d706e 523 } hw_rng_or_t;
bogdanm 82:6473597d706e 524 #endif
bogdanm 82:6473597d706e 525
bogdanm 82:6473597d706e 526 /*!
bogdanm 82:6473597d706e 527 * @name Constants and macros for entire RNG_OR register
bogdanm 82:6473597d706e 528 */
bogdanm 82:6473597d706e 529 //@{
bogdanm 82:6473597d706e 530 #define HW_RNG_OR_ADDR (REGS_RNG_BASE + 0xCU)
bogdanm 82:6473597d706e 531
bogdanm 82:6473597d706e 532 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 533 #define HW_RNG_OR (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR)
bogdanm 82:6473597d706e 534 #define HW_RNG_OR_RD() (HW_RNG_OR.U)
bogdanm 82:6473597d706e 535 #endif
bogdanm 82:6473597d706e 536 //@}
bogdanm 82:6473597d706e 537
bogdanm 82:6473597d706e 538 /*
bogdanm 82:6473597d706e 539 * Constants & macros for individual RNG_OR bitfields
bogdanm 82:6473597d706e 540 */
bogdanm 82:6473597d706e 541
bogdanm 82:6473597d706e 542 /*!
bogdanm 82:6473597d706e 543 * @name Register RNG_OR, field RANDOUT[31:0] (RO)
bogdanm 82:6473597d706e 544 *
bogdanm 82:6473597d706e 545 * Stores a random-data word generated by RNGA. This is a read-only field.Before
bogdanm 82:6473597d706e 546 * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
bogdanm 82:6473597d706e 547 *
bogdanm 82:6473597d706e 548 * Values:
bogdanm 82:6473597d706e 549 * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
bogdanm 82:6473597d706e 550 * 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
bogdanm 82:6473597d706e 551 * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
bogdanm 82:6473597d706e 552 * request to the interrupt controller).
bogdanm 82:6473597d706e 553 */
bogdanm 82:6473597d706e 554 //@{
bogdanm 82:6473597d706e 555 #define BP_RNG_OR_RANDOUT (0U) //!< Bit position for RNG_OR_RANDOUT.
bogdanm 82:6473597d706e 556 #define BM_RNG_OR_RANDOUT (0xFFFFFFFFU) //!< Bit mask for RNG_OR_RANDOUT.
bogdanm 82:6473597d706e 557 #define BS_RNG_OR_RANDOUT (32U) //!< Bit field size in bits for RNG_OR_RANDOUT.
bogdanm 82:6473597d706e 558
bogdanm 82:6473597d706e 559 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 560 //! @brief Read current value of the RNG_OR_RANDOUT field.
bogdanm 82:6473597d706e 561 #define BR_RNG_OR_RANDOUT (HW_RNG_OR.U)
bogdanm 82:6473597d706e 562 #endif
bogdanm 82:6473597d706e 563 //@}
bogdanm 82:6473597d706e 564
bogdanm 82:6473597d706e 565 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 566 // hw_rng_t - module struct
bogdanm 82:6473597d706e 567 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 568 /*!
bogdanm 82:6473597d706e 569 * @brief All RNG module registers.
bogdanm 82:6473597d706e 570 */
bogdanm 82:6473597d706e 571 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 572 #pragma pack(1)
bogdanm 82:6473597d706e 573 typedef struct _hw_rng
bogdanm 82:6473597d706e 574 {
bogdanm 82:6473597d706e 575 __IO hw_rng_cr_t CR; //!< [0x0] RNGA Control Register
bogdanm 82:6473597d706e 576 __I hw_rng_sr_t SR; //!< [0x4] RNGA Status Register
bogdanm 82:6473597d706e 577 __O hw_rng_er_t ER; //!< [0x8] RNGA Entropy Register
bogdanm 82:6473597d706e 578 __I hw_rng_or_t OR; //!< [0xC] RNGA Output Register
bogdanm 82:6473597d706e 579 } hw_rng_t;
bogdanm 82:6473597d706e 580 #pragma pack()
bogdanm 82:6473597d706e 581
bogdanm 82:6473597d706e 582 //! @brief Macro to access all RNG registers.
bogdanm 82:6473597d706e 583 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 584 //! use the '&' operator, like <code>&HW_RNG</code>.
bogdanm 82:6473597d706e 585 #define HW_RNG (*(hw_rng_t *) REGS_RNG_BASE)
bogdanm 82:6473597d706e 586 #endif
bogdanm 82:6473597d706e 587
bogdanm 82:6473597d706e 588 #endif // __HW_RNG_REGISTERS_H__
bogdanm 82:6473597d706e 589 // v22/130726/0.9
bogdanm 82:6473597d706e 590 // EOF