雄介 太田 / mbed

mbed(SerialHalfDuplex入り)

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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_cmp.h@82:6473597d706e, 2014-04-07 (annotated)

Committer:
bogdanm
Date:
Mon Apr 07 18:28:36 2014 +0100
Revision:
82:6473597d706e
Release 82 of the mbed library



Main changes:



- support for K64F

- Revisited Nordic code structure

- Test infrastructure improvements

- various bug fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_CMP_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_CMP_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 CMP
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_CMP_CR0 - CMP Control Register 0
bogdanm 82:6473597d706e 33 * - HW_CMP_CR1 - CMP Control Register 1
bogdanm 82:6473597d706e 34 * - HW_CMP_FPR - CMP Filter Period Register
bogdanm 82:6473597d706e 35 * - HW_CMP_SCR - CMP Status and Control Register
bogdanm 82:6473597d706e 36 * - HW_CMP_DACCR - DAC Control Register
bogdanm 82:6473597d706e 37 * - HW_CMP_MUXCR - MUX Control Register
bogdanm 82:6473597d706e 38 *
bogdanm 82:6473597d706e 39 * - hw_cmp_t - Struct containing all module registers.
bogdanm 82:6473597d706e 40 */
bogdanm 82:6473597d706e 41
bogdanm 82:6473597d706e 42 //! @name Module base addresses
bogdanm 82:6473597d706e 43 //@{
bogdanm 82:6473597d706e 44 #ifndef REGS_CMP_BASE
bogdanm 82:6473597d706e 45 #define HW_CMP_INSTANCE_COUNT (3U) //!< Number of instances of the CMP module.
bogdanm 82:6473597d706e 46 #define HW_CMP0 (0U) //!< Instance number for CMP0.
bogdanm 82:6473597d706e 47 #define HW_CMP1 (1U) //!< Instance number for CMP1.
bogdanm 82:6473597d706e 48 #define HW_CMP2 (2U) //!< Instance number for CMP2.
bogdanm 82:6473597d706e 49 #define REGS_CMP0_BASE (0x40073000U) //!< Base address for CMP0.
bogdanm 82:6473597d706e 50 #define REGS_CMP1_BASE (0x40073008U) //!< Base address for CMP1.
bogdanm 82:6473597d706e 51 #define REGS_CMP2_BASE (0x40073010U) //!< Base address for CMP2.
bogdanm 82:6473597d706e 52
bogdanm 82:6473597d706e 53 //! @brief Table of base addresses for CMP instances.
bogdanm 82:6473597d706e 54 static const uint32_t __g_regs_CMP_base_addresses[] = {
bogdanm 82:6473597d706e 55 REGS_CMP0_BASE,
bogdanm 82:6473597d706e 56 REGS_CMP1_BASE,
bogdanm 82:6473597d706e 57 REGS_CMP2_BASE,
bogdanm 82:6473597d706e 58 };
bogdanm 82:6473597d706e 59
bogdanm 82:6473597d706e 60 //! @brief Get the base address of CMP by instance number.
bogdanm 82:6473597d706e 61 //! @param x CMP instance number, from 0 through 2.
bogdanm 82:6473597d706e 62 #define REGS_CMP_BASE(x) (__g_regs_CMP_base_addresses[(x)])
bogdanm 82:6473597d706e 63
bogdanm 82:6473597d706e 64 //! @brief Get the instance number given a base address.
bogdanm 82:6473597d706e 65 //! @param b Base address for an instance of CMP.
bogdanm 82:6473597d706e 66 #define REGS_CMP_INSTANCE(b) ((b) == REGS_CMP0_BASE ? HW_CMP0 : (b) == REGS_CMP1_BASE ? HW_CMP1 : (b) == REGS_CMP2_BASE ? HW_CMP2 : 0)
bogdanm 82:6473597d706e 67 #endif
bogdanm 82:6473597d706e 68 //@}
bogdanm 82:6473597d706e 69
bogdanm 82:6473597d706e 70 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 71 // HW_CMP_CR0 - CMP Control Register 0
bogdanm 82:6473597d706e 72 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 73
bogdanm 82:6473597d706e 74 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 75 /*!
bogdanm 82:6473597d706e 76 * @brief HW_CMP_CR0 - CMP Control Register 0 (RW)
bogdanm 82:6473597d706e 77 *
bogdanm 82:6473597d706e 78 * Reset value: 0x00U
bogdanm 82:6473597d706e 79 */
bogdanm 82:6473597d706e 80 typedef union _hw_cmp_cr0
bogdanm 82:6473597d706e 81 {
bogdanm 82:6473597d706e 82 uint8_t U;
bogdanm 82:6473597d706e 83 struct _hw_cmp_cr0_bitfields
bogdanm 82:6473597d706e 84 {
bogdanm 82:6473597d706e 85 uint8_t HYSTCTR : 2; //!< [1:0] Comparator hard block hysteresis
bogdanm 82:6473597d706e 86 //! control
bogdanm 82:6473597d706e 87 uint8_t RESERVED0 : 2; //!< [3:2]
bogdanm 82:6473597d706e 88 uint8_t FILTER_CNT : 3; //!< [6:4] Filter Sample Count
bogdanm 82:6473597d706e 89 uint8_t RESERVED1 : 1; //!< [7]
bogdanm 82:6473597d706e 90 } B;
bogdanm 82:6473597d706e 91 } hw_cmp_cr0_t;
bogdanm 82:6473597d706e 92 #endif
bogdanm 82:6473597d706e 93
bogdanm 82:6473597d706e 94 /*!
bogdanm 82:6473597d706e 95 * @name Constants and macros for entire CMP_CR0 register
bogdanm 82:6473597d706e 96 */
bogdanm 82:6473597d706e 97 //@{
bogdanm 82:6473597d706e 98 #define HW_CMP_CR0_ADDR(x) (REGS_CMP_BASE(x) + 0x0U)
bogdanm 82:6473597d706e 99
bogdanm 82:6473597d706e 100 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 101 #define HW_CMP_CR0(x) (*(__IO hw_cmp_cr0_t *) HW_CMP_CR0_ADDR(x))
bogdanm 82:6473597d706e 102 #define HW_CMP_CR0_RD(x) (HW_CMP_CR0(x).U)
bogdanm 82:6473597d706e 103 #define HW_CMP_CR0_WR(x, v) (HW_CMP_CR0(x).U = (v))
bogdanm 82:6473597d706e 104 #define HW_CMP_CR0_SET(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) | (v)))
bogdanm 82:6473597d706e 105 #define HW_CMP_CR0_CLR(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) & ~(v)))
bogdanm 82:6473597d706e 106 #define HW_CMP_CR0_TOG(x, v) (HW_CMP_CR0_WR(x, HW_CMP_CR0_RD(x) ^ (v)))
bogdanm 82:6473597d706e 107 #endif
bogdanm 82:6473597d706e 108 //@}
bogdanm 82:6473597d706e 109
bogdanm 82:6473597d706e 110 /*
bogdanm 82:6473597d706e 111 * Constants & macros for individual CMP_CR0 bitfields
bogdanm 82:6473597d706e 112 */
bogdanm 82:6473597d706e 113
bogdanm 82:6473597d706e 114 /*!
bogdanm 82:6473597d706e 115 * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
bogdanm 82:6473597d706e 116 *
bogdanm 82:6473597d706e 117 * Defines the programmable hysteresis level. The hysteresis values associated
bogdanm 82:6473597d706e 118 * with each level are device-specific. See the Data Sheet of the device for the
bogdanm 82:6473597d706e 119 * exact values.
bogdanm 82:6473597d706e 120 *
bogdanm 82:6473597d706e 121 * Values:
bogdanm 82:6473597d706e 122 * - 00 - Level 0
bogdanm 82:6473597d706e 123 * - 01 - Level 1
bogdanm 82:6473597d706e 124 * - 10 - Level 2
bogdanm 82:6473597d706e 125 * - 11 - Level 3
bogdanm 82:6473597d706e 126 */
bogdanm 82:6473597d706e 127 //@{
bogdanm 82:6473597d706e 128 #define BP_CMP_CR0_HYSTCTR (0U) //!< Bit position for CMP_CR0_HYSTCTR.
bogdanm 82:6473597d706e 129 #define BM_CMP_CR0_HYSTCTR (0x03U) //!< Bit mask for CMP_CR0_HYSTCTR.
bogdanm 82:6473597d706e 130 #define BS_CMP_CR0_HYSTCTR (2U) //!< Bit field size in bits for CMP_CR0_HYSTCTR.
bogdanm 82:6473597d706e 131
bogdanm 82:6473597d706e 132 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 133 //! @brief Read current value of the CMP_CR0_HYSTCTR field.
bogdanm 82:6473597d706e 134 #define BR_CMP_CR0_HYSTCTR(x) (HW_CMP_CR0(x).B.HYSTCTR)
bogdanm 82:6473597d706e 135 #endif
bogdanm 82:6473597d706e 136
bogdanm 82:6473597d706e 137 //! @brief Format value for bitfield CMP_CR0_HYSTCTR.
bogdanm 82:6473597d706e 138 #define BF_CMP_CR0_HYSTCTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR0_HYSTCTR), uint8_t) & BM_CMP_CR0_HYSTCTR)
bogdanm 82:6473597d706e 139
bogdanm 82:6473597d706e 140 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 141 //! @brief Set the HYSTCTR field to a new value.
bogdanm 82:6473597d706e 142 #define BW_CMP_CR0_HYSTCTR(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_HYSTCTR) | BF_CMP_CR0_HYSTCTR(v)))
bogdanm 82:6473597d706e 143 #endif
bogdanm 82:6473597d706e 144 //@}
bogdanm 82:6473597d706e 145
bogdanm 82:6473597d706e 146 /*!
bogdanm 82:6473597d706e 147 * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
bogdanm 82:6473597d706e 148 *
bogdanm 82:6473597d706e 149 * Represents the number of consecutive samples that must agree prior to the
bogdanm 82:6473597d706e 150 * comparator ouput filter accepting a new output state. For information regarding
bogdanm 82:6473597d706e 151 * filter programming and latency, see the Functional descriptionThe CMP module
bogdanm 82:6473597d706e 152 * can be used to compare two analog input voltages applied to INP and INM. .
bogdanm 82:6473597d706e 153 *
bogdanm 82:6473597d706e 154 * Values:
bogdanm 82:6473597d706e 155 * - 000 - Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a
bogdanm 82:6473597d706e 156 * legal state, and is not recommended. If SE = 0, COUT = COUTA.
bogdanm 82:6473597d706e 157 * - 001 - One sample must agree. The comparator output is simply sampled.
bogdanm 82:6473597d706e 158 * - 010 - 2 consecutive samples must agree.
bogdanm 82:6473597d706e 159 * - 011 - 3 consecutive samples must agree.
bogdanm 82:6473597d706e 160 * - 100 - 4 consecutive samples must agree.
bogdanm 82:6473597d706e 161 * - 101 - 5 consecutive samples must agree.
bogdanm 82:6473597d706e 162 * - 110 - 6 consecutive samples must agree.
bogdanm 82:6473597d706e 163 * - 111 - 7 consecutive samples must agree.
bogdanm 82:6473597d706e 164 */
bogdanm 82:6473597d706e 165 //@{
bogdanm 82:6473597d706e 166 #define BP_CMP_CR0_FILTER_CNT (4U) //!< Bit position for CMP_CR0_FILTER_CNT.
bogdanm 82:6473597d706e 167 #define BM_CMP_CR0_FILTER_CNT (0x70U) //!< Bit mask for CMP_CR0_FILTER_CNT.
bogdanm 82:6473597d706e 168 #define BS_CMP_CR0_FILTER_CNT (3U) //!< Bit field size in bits for CMP_CR0_FILTER_CNT.
bogdanm 82:6473597d706e 169
bogdanm 82:6473597d706e 170 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 171 //! @brief Read current value of the CMP_CR0_FILTER_CNT field.
bogdanm 82:6473597d706e 172 #define BR_CMP_CR0_FILTER_CNT(x) (HW_CMP_CR0(x).B.FILTER_CNT)
bogdanm 82:6473597d706e 173 #endif
bogdanm 82:6473597d706e 174
bogdanm 82:6473597d706e 175 //! @brief Format value for bitfield CMP_CR0_FILTER_CNT.
bogdanm 82:6473597d706e 176 #define BF_CMP_CR0_FILTER_CNT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR0_FILTER_CNT), uint8_t) & BM_CMP_CR0_FILTER_CNT)
bogdanm 82:6473597d706e 177
bogdanm 82:6473597d706e 178 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 179 //! @brief Set the FILTER_CNT field to a new value.
bogdanm 82:6473597d706e 180 #define BW_CMP_CR0_FILTER_CNT(x, v) (HW_CMP_CR0_WR(x, (HW_CMP_CR0_RD(x) & ~BM_CMP_CR0_FILTER_CNT) | BF_CMP_CR0_FILTER_CNT(v)))
bogdanm 82:6473597d706e 181 #endif
bogdanm 82:6473597d706e 182 //@}
bogdanm 82:6473597d706e 183
bogdanm 82:6473597d706e 184 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 185 // HW_CMP_CR1 - CMP Control Register 1
bogdanm 82:6473597d706e 186 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 187
bogdanm 82:6473597d706e 188 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 189 /*!
bogdanm 82:6473597d706e 190 * @brief HW_CMP_CR1 - CMP Control Register 1 (RW)
bogdanm 82:6473597d706e 191 *
bogdanm 82:6473597d706e 192 * Reset value: 0x00U
bogdanm 82:6473597d706e 193 */
bogdanm 82:6473597d706e 194 typedef union _hw_cmp_cr1
bogdanm 82:6473597d706e 195 {
bogdanm 82:6473597d706e 196 uint8_t U;
bogdanm 82:6473597d706e 197 struct _hw_cmp_cr1_bitfields
bogdanm 82:6473597d706e 198 {
bogdanm 82:6473597d706e 199 uint8_t EN : 1; //!< [0] Comparator Module Enable
bogdanm 82:6473597d706e 200 uint8_t OPE : 1; //!< [1] Comparator Output Pin Enable
bogdanm 82:6473597d706e 201 uint8_t COS : 1; //!< [2] Comparator Output Select
bogdanm 82:6473597d706e 202 uint8_t INV : 1; //!< [3] Comparator INVERT
bogdanm 82:6473597d706e 203 uint8_t PMODE : 1; //!< [4] Power Mode Select
bogdanm 82:6473597d706e 204 uint8_t RESERVED0 : 1; //!< [5]
bogdanm 82:6473597d706e 205 uint8_t WE : 1; //!< [6] Windowing Enable
bogdanm 82:6473597d706e 206 uint8_t SE : 1; //!< [7] Sample Enable
bogdanm 82:6473597d706e 207 } B;
bogdanm 82:6473597d706e 208 } hw_cmp_cr1_t;
bogdanm 82:6473597d706e 209 #endif
bogdanm 82:6473597d706e 210
bogdanm 82:6473597d706e 211 /*!
bogdanm 82:6473597d706e 212 * @name Constants and macros for entire CMP_CR1 register
bogdanm 82:6473597d706e 213 */
bogdanm 82:6473597d706e 214 //@{
bogdanm 82:6473597d706e 215 #define HW_CMP_CR1_ADDR(x) (REGS_CMP_BASE(x) + 0x1U)
bogdanm 82:6473597d706e 216
bogdanm 82:6473597d706e 217 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 218 #define HW_CMP_CR1(x) (*(__IO hw_cmp_cr1_t *) HW_CMP_CR1_ADDR(x))
bogdanm 82:6473597d706e 219 #define HW_CMP_CR1_RD(x) (HW_CMP_CR1(x).U)
bogdanm 82:6473597d706e 220 #define HW_CMP_CR1_WR(x, v) (HW_CMP_CR1(x).U = (v))
bogdanm 82:6473597d706e 221 #define HW_CMP_CR1_SET(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) | (v)))
bogdanm 82:6473597d706e 222 #define HW_CMP_CR1_CLR(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) & ~(v)))
bogdanm 82:6473597d706e 223 #define HW_CMP_CR1_TOG(x, v) (HW_CMP_CR1_WR(x, HW_CMP_CR1_RD(x) ^ (v)))
bogdanm 82:6473597d706e 224 #endif
bogdanm 82:6473597d706e 225 //@}
bogdanm 82:6473597d706e 226
bogdanm 82:6473597d706e 227 /*
bogdanm 82:6473597d706e 228 * Constants & macros for individual CMP_CR1 bitfields
bogdanm 82:6473597d706e 229 */
bogdanm 82:6473597d706e 230
bogdanm 82:6473597d706e 231 /*!
bogdanm 82:6473597d706e 232 * @name Register CMP_CR1, field EN[0] (RW)
bogdanm 82:6473597d706e 233 *
bogdanm 82:6473597d706e 234 * Enables the Analog Comparator module. When the module is not enabled, it
bogdanm 82:6473597d706e 235 * remains in the off state, and consumes no power. When the user selects the same
bogdanm 82:6473597d706e 236 * input from analog mux to the positive and negative port, the comparator is
bogdanm 82:6473597d706e 237 * disabled automatically.
bogdanm 82:6473597d706e 238 *
bogdanm 82:6473597d706e 239 * Values:
bogdanm 82:6473597d706e 240 * - 0 - Analog Comparator is disabled.
bogdanm 82:6473597d706e 241 * - 1 - Analog Comparator is enabled.
bogdanm 82:6473597d706e 242 */
bogdanm 82:6473597d706e 243 //@{
bogdanm 82:6473597d706e 244 #define BP_CMP_CR1_EN (0U) //!< Bit position for CMP_CR1_EN.
bogdanm 82:6473597d706e 245 #define BM_CMP_CR1_EN (0x01U) //!< Bit mask for CMP_CR1_EN.
bogdanm 82:6473597d706e 246 #define BS_CMP_CR1_EN (1U) //!< Bit field size in bits for CMP_CR1_EN.
bogdanm 82:6473597d706e 247
bogdanm 82:6473597d706e 248 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 249 //! @brief Read current value of the CMP_CR1_EN field.
bogdanm 82:6473597d706e 250 #define BR_CMP_CR1_EN(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN))
bogdanm 82:6473597d706e 251 #endif
bogdanm 82:6473597d706e 252
bogdanm 82:6473597d706e 253 //! @brief Format value for bitfield CMP_CR1_EN.
bogdanm 82:6473597d706e 254 #define BF_CMP_CR1_EN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_EN), uint8_t) & BM_CMP_CR1_EN)
bogdanm 82:6473597d706e 255
bogdanm 82:6473597d706e 256 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 257 //! @brief Set the EN field to a new value.
bogdanm 82:6473597d706e 258 #define BW_CMP_CR1_EN(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_EN) = (v))
bogdanm 82:6473597d706e 259 #endif
bogdanm 82:6473597d706e 260 //@}
bogdanm 82:6473597d706e 261
bogdanm 82:6473597d706e 262 /*!
bogdanm 82:6473597d706e 263 * @name Register CMP_CR1, field OPE[1] (RW)
bogdanm 82:6473597d706e 264 *
bogdanm 82:6473597d706e 265 * Values:
bogdanm 82:6473597d706e 266 * - 0 - CMPO is not available on the associated CMPO output pin. If the
bogdanm 82:6473597d706e 267 * comparator does not own the pin, this field has no effect.
bogdanm 82:6473597d706e 268 * - 1 - CMPO is available on the associated CMPO output pin. The comparator
bogdanm 82:6473597d706e 269 * output (CMPO) is driven out on the associated CMPO output pin if the
bogdanm 82:6473597d706e 270 * comparator owns the pin. If the comparator does not own the field, this bit has no
bogdanm 82:6473597d706e 271 * effect.
bogdanm 82:6473597d706e 272 */
bogdanm 82:6473597d706e 273 //@{
bogdanm 82:6473597d706e 274 #define BP_CMP_CR1_OPE (1U) //!< Bit position for CMP_CR1_OPE.
bogdanm 82:6473597d706e 275 #define BM_CMP_CR1_OPE (0x02U) //!< Bit mask for CMP_CR1_OPE.
bogdanm 82:6473597d706e 276 #define BS_CMP_CR1_OPE (1U) //!< Bit field size in bits for CMP_CR1_OPE.
bogdanm 82:6473597d706e 277
bogdanm 82:6473597d706e 278 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 279 //! @brief Read current value of the CMP_CR1_OPE field.
bogdanm 82:6473597d706e 280 #define BR_CMP_CR1_OPE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE))
bogdanm 82:6473597d706e 281 #endif
bogdanm 82:6473597d706e 282
bogdanm 82:6473597d706e 283 //! @brief Format value for bitfield CMP_CR1_OPE.
bogdanm 82:6473597d706e 284 #define BF_CMP_CR1_OPE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_OPE), uint8_t) & BM_CMP_CR1_OPE)
bogdanm 82:6473597d706e 285
bogdanm 82:6473597d706e 286 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 287 //! @brief Set the OPE field to a new value.
bogdanm 82:6473597d706e 288 #define BW_CMP_CR1_OPE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_OPE) = (v))
bogdanm 82:6473597d706e 289 #endif
bogdanm 82:6473597d706e 290 //@}
bogdanm 82:6473597d706e 291
bogdanm 82:6473597d706e 292 /*!
bogdanm 82:6473597d706e 293 * @name Register CMP_CR1, field COS[2] (RW)
bogdanm 82:6473597d706e 294 *
bogdanm 82:6473597d706e 295 * Values:
bogdanm 82:6473597d706e 296 * - 0 - Set the filtered comparator output (CMPO) to equal COUT.
bogdanm 82:6473597d706e 297 * - 1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
bogdanm 82:6473597d706e 298 */
bogdanm 82:6473597d706e 299 //@{
bogdanm 82:6473597d706e 300 #define BP_CMP_CR1_COS (2U) //!< Bit position for CMP_CR1_COS.
bogdanm 82:6473597d706e 301 #define BM_CMP_CR1_COS (0x04U) //!< Bit mask for CMP_CR1_COS.
bogdanm 82:6473597d706e 302 #define BS_CMP_CR1_COS (1U) //!< Bit field size in bits for CMP_CR1_COS.
bogdanm 82:6473597d706e 303
bogdanm 82:6473597d706e 304 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 305 //! @brief Read current value of the CMP_CR1_COS field.
bogdanm 82:6473597d706e 306 #define BR_CMP_CR1_COS(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS))
bogdanm 82:6473597d706e 307 #endif
bogdanm 82:6473597d706e 308
bogdanm 82:6473597d706e 309 //! @brief Format value for bitfield CMP_CR1_COS.
bogdanm 82:6473597d706e 310 #define BF_CMP_CR1_COS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_COS), uint8_t) & BM_CMP_CR1_COS)
bogdanm 82:6473597d706e 311
bogdanm 82:6473597d706e 312 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 313 //! @brief Set the COS field to a new value.
bogdanm 82:6473597d706e 314 #define BW_CMP_CR1_COS(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_COS) = (v))
bogdanm 82:6473597d706e 315 #endif
bogdanm 82:6473597d706e 316 //@}
bogdanm 82:6473597d706e 317
bogdanm 82:6473597d706e 318 /*!
bogdanm 82:6473597d706e 319 * @name Register CMP_CR1, field INV[3] (RW)
bogdanm 82:6473597d706e 320 *
bogdanm 82:6473597d706e 321 * Allows selection of the polarity of the analog comparator function. It is
bogdanm 82:6473597d706e 322 * also driven to the COUT output, on both the device pin and as SCR[COUT], when
bogdanm 82:6473597d706e 323 * OPE=0.
bogdanm 82:6473597d706e 324 *
bogdanm 82:6473597d706e 325 * Values:
bogdanm 82:6473597d706e 326 * - 0 - Does not invert the comparator output.
bogdanm 82:6473597d706e 327 * - 1 - Inverts the comparator output.
bogdanm 82:6473597d706e 328 */
bogdanm 82:6473597d706e 329 //@{
bogdanm 82:6473597d706e 330 #define BP_CMP_CR1_INV (3U) //!< Bit position for CMP_CR1_INV.
bogdanm 82:6473597d706e 331 #define BM_CMP_CR1_INV (0x08U) //!< Bit mask for CMP_CR1_INV.
bogdanm 82:6473597d706e 332 #define BS_CMP_CR1_INV (1U) //!< Bit field size in bits for CMP_CR1_INV.
bogdanm 82:6473597d706e 333
bogdanm 82:6473597d706e 334 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 335 //! @brief Read current value of the CMP_CR1_INV field.
bogdanm 82:6473597d706e 336 #define BR_CMP_CR1_INV(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV))
bogdanm 82:6473597d706e 337 #endif
bogdanm 82:6473597d706e 338
bogdanm 82:6473597d706e 339 //! @brief Format value for bitfield CMP_CR1_INV.
bogdanm 82:6473597d706e 340 #define BF_CMP_CR1_INV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_INV), uint8_t) & BM_CMP_CR1_INV)
bogdanm 82:6473597d706e 341
bogdanm 82:6473597d706e 342 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 343 //! @brief Set the INV field to a new value.
bogdanm 82:6473597d706e 344 #define BW_CMP_CR1_INV(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_INV) = (v))
bogdanm 82:6473597d706e 345 #endif
bogdanm 82:6473597d706e 346 //@}
bogdanm 82:6473597d706e 347
bogdanm 82:6473597d706e 348 /*!
bogdanm 82:6473597d706e 349 * @name Register CMP_CR1, field PMODE[4] (RW)
bogdanm 82:6473597d706e 350 *
bogdanm 82:6473597d706e 351 * See the electrical specifications table in the device Data Sheet for details.
bogdanm 82:6473597d706e 352 *
bogdanm 82:6473597d706e 353 * Values:
bogdanm 82:6473597d706e 354 * - 0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
bogdanm 82:6473597d706e 355 * output propagation delay and lower current consumption.
bogdanm 82:6473597d706e 356 * - 1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has faster
bogdanm 82:6473597d706e 357 * output propagation delay and higher current consumption.
bogdanm 82:6473597d706e 358 */
bogdanm 82:6473597d706e 359 //@{
bogdanm 82:6473597d706e 360 #define BP_CMP_CR1_PMODE (4U) //!< Bit position for CMP_CR1_PMODE.
bogdanm 82:6473597d706e 361 #define BM_CMP_CR1_PMODE (0x10U) //!< Bit mask for CMP_CR1_PMODE.
bogdanm 82:6473597d706e 362 #define BS_CMP_CR1_PMODE (1U) //!< Bit field size in bits for CMP_CR1_PMODE.
bogdanm 82:6473597d706e 363
bogdanm 82:6473597d706e 364 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 365 //! @brief Read current value of the CMP_CR1_PMODE field.
bogdanm 82:6473597d706e 366 #define BR_CMP_CR1_PMODE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE))
bogdanm 82:6473597d706e 367 #endif
bogdanm 82:6473597d706e 368
bogdanm 82:6473597d706e 369 //! @brief Format value for bitfield CMP_CR1_PMODE.
bogdanm 82:6473597d706e 370 #define BF_CMP_CR1_PMODE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_PMODE), uint8_t) & BM_CMP_CR1_PMODE)
bogdanm 82:6473597d706e 371
bogdanm 82:6473597d706e 372 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 373 //! @brief Set the PMODE field to a new value.
bogdanm 82:6473597d706e 374 #define BW_CMP_CR1_PMODE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_PMODE) = (v))
bogdanm 82:6473597d706e 375 #endif
bogdanm 82:6473597d706e 376 //@}
bogdanm 82:6473597d706e 377
bogdanm 82:6473597d706e 378 /*!
bogdanm 82:6473597d706e 379 * @name Register CMP_CR1, field WE[6] (RW)
bogdanm 82:6473597d706e 380 *
bogdanm 82:6473597d706e 381 * At any given time, either SE or WE can be set. If a write to this register
bogdanm 82:6473597d706e 382 * attempts to set both, then SE is set and WE is cleared. However, avoid writing
bogdanm 82:6473597d706e 383 * 1s to both field locations because this "11" case is reserved and may change in
bogdanm 82:6473597d706e 384 * future implementations.
bogdanm 82:6473597d706e 385 *
bogdanm 82:6473597d706e 386 * Values:
bogdanm 82:6473597d706e 387 * - 0 - Windowing mode is not selected.
bogdanm 82:6473597d706e 388 * - 1 - Windowing mode is selected.
bogdanm 82:6473597d706e 389 */
bogdanm 82:6473597d706e 390 //@{
bogdanm 82:6473597d706e 391 #define BP_CMP_CR1_WE (6U) //!< Bit position for CMP_CR1_WE.
bogdanm 82:6473597d706e 392 #define BM_CMP_CR1_WE (0x40U) //!< Bit mask for CMP_CR1_WE.
bogdanm 82:6473597d706e 393 #define BS_CMP_CR1_WE (1U) //!< Bit field size in bits for CMP_CR1_WE.
bogdanm 82:6473597d706e 394
bogdanm 82:6473597d706e 395 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 396 //! @brief Read current value of the CMP_CR1_WE field.
bogdanm 82:6473597d706e 397 #define BR_CMP_CR1_WE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE))
bogdanm 82:6473597d706e 398 #endif
bogdanm 82:6473597d706e 399
bogdanm 82:6473597d706e 400 //! @brief Format value for bitfield CMP_CR1_WE.
bogdanm 82:6473597d706e 401 #define BF_CMP_CR1_WE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_WE), uint8_t) & BM_CMP_CR1_WE)
bogdanm 82:6473597d706e 402
bogdanm 82:6473597d706e 403 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 404 //! @brief Set the WE field to a new value.
bogdanm 82:6473597d706e 405 #define BW_CMP_CR1_WE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_WE) = (v))
bogdanm 82:6473597d706e 406 #endif
bogdanm 82:6473597d706e 407 //@}
bogdanm 82:6473597d706e 408
bogdanm 82:6473597d706e 409 /*!
bogdanm 82:6473597d706e 410 * @name Register CMP_CR1, field SE[7] (RW)
bogdanm 82:6473597d706e 411 *
bogdanm 82:6473597d706e 412 * At any given time, either SE or WE can be set. If a write to this register
bogdanm 82:6473597d706e 413 * attempts to set both, then SE is set and WE is cleared. However, avoid writing
bogdanm 82:6473597d706e 414 * 1s to both field locations because this "11" case is reserved and may change in
bogdanm 82:6473597d706e 415 * future implementations.
bogdanm 82:6473597d706e 416 *
bogdanm 82:6473597d706e 417 * Values:
bogdanm 82:6473597d706e 418 * - 0 - Sampling mode is not selected.
bogdanm 82:6473597d706e 419 * - 1 - Sampling mode is selected.
bogdanm 82:6473597d706e 420 */
bogdanm 82:6473597d706e 421 //@{
bogdanm 82:6473597d706e 422 #define BP_CMP_CR1_SE (7U) //!< Bit position for CMP_CR1_SE.
bogdanm 82:6473597d706e 423 #define BM_CMP_CR1_SE (0x80U) //!< Bit mask for CMP_CR1_SE.
bogdanm 82:6473597d706e 424 #define BS_CMP_CR1_SE (1U) //!< Bit field size in bits for CMP_CR1_SE.
bogdanm 82:6473597d706e 425
bogdanm 82:6473597d706e 426 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 427 //! @brief Read current value of the CMP_CR1_SE field.
bogdanm 82:6473597d706e 428 #define BR_CMP_CR1_SE(x) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE))
bogdanm 82:6473597d706e 429 #endif
bogdanm 82:6473597d706e 430
bogdanm 82:6473597d706e 431 //! @brief Format value for bitfield CMP_CR1_SE.
bogdanm 82:6473597d706e 432 #define BF_CMP_CR1_SE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_CR1_SE), uint8_t) & BM_CMP_CR1_SE)
bogdanm 82:6473597d706e 433
bogdanm 82:6473597d706e 434 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 435 //! @brief Set the SE field to a new value.
bogdanm 82:6473597d706e 436 #define BW_CMP_CR1_SE(x, v) (BITBAND_ACCESS8(HW_CMP_CR1_ADDR(x), BP_CMP_CR1_SE) = (v))
bogdanm 82:6473597d706e 437 #endif
bogdanm 82:6473597d706e 438 //@}
bogdanm 82:6473597d706e 439
bogdanm 82:6473597d706e 440 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 441 // HW_CMP_FPR - CMP Filter Period Register
bogdanm 82:6473597d706e 442 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 443
bogdanm 82:6473597d706e 444 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 445 /*!
bogdanm 82:6473597d706e 446 * @brief HW_CMP_FPR - CMP Filter Period Register (RW)
bogdanm 82:6473597d706e 447 *
bogdanm 82:6473597d706e 448 * Reset value: 0x00U
bogdanm 82:6473597d706e 449 */
bogdanm 82:6473597d706e 450 typedef union _hw_cmp_fpr
bogdanm 82:6473597d706e 451 {
bogdanm 82:6473597d706e 452 uint8_t U;
bogdanm 82:6473597d706e 453 struct _hw_cmp_fpr_bitfields
bogdanm 82:6473597d706e 454 {
bogdanm 82:6473597d706e 455 uint8_t FILT_PER : 8; //!< [7:0] Filter Sample Period
bogdanm 82:6473597d706e 456 } B;
bogdanm 82:6473597d706e 457 } hw_cmp_fpr_t;
bogdanm 82:6473597d706e 458 #endif
bogdanm 82:6473597d706e 459
bogdanm 82:6473597d706e 460 /*!
bogdanm 82:6473597d706e 461 * @name Constants and macros for entire CMP_FPR register
bogdanm 82:6473597d706e 462 */
bogdanm 82:6473597d706e 463 //@{
bogdanm 82:6473597d706e 464 #define HW_CMP_FPR_ADDR(x) (REGS_CMP_BASE(x) + 0x2U)
bogdanm 82:6473597d706e 465
bogdanm 82:6473597d706e 466 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 467 #define HW_CMP_FPR(x) (*(__IO hw_cmp_fpr_t *) HW_CMP_FPR_ADDR(x))
bogdanm 82:6473597d706e 468 #define HW_CMP_FPR_RD(x) (HW_CMP_FPR(x).U)
bogdanm 82:6473597d706e 469 #define HW_CMP_FPR_WR(x, v) (HW_CMP_FPR(x).U = (v))
bogdanm 82:6473597d706e 470 #define HW_CMP_FPR_SET(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) | (v)))
bogdanm 82:6473597d706e 471 #define HW_CMP_FPR_CLR(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) & ~(v)))
bogdanm 82:6473597d706e 472 #define HW_CMP_FPR_TOG(x, v) (HW_CMP_FPR_WR(x, HW_CMP_FPR_RD(x) ^ (v)))
bogdanm 82:6473597d706e 473 #endif
bogdanm 82:6473597d706e 474 //@}
bogdanm 82:6473597d706e 475
bogdanm 82:6473597d706e 476 /*
bogdanm 82:6473597d706e 477 * Constants & macros for individual CMP_FPR bitfields
bogdanm 82:6473597d706e 478 */
bogdanm 82:6473597d706e 479
bogdanm 82:6473597d706e 480 /*!
bogdanm 82:6473597d706e 481 * @name Register CMP_FPR, field FILT_PER[7:0] (RW)
bogdanm 82:6473597d706e 482 *
bogdanm 82:6473597d706e 483 * Specifies the sampling period, in bus clock cycles, of the comparator output
bogdanm 82:6473597d706e 484 * filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter. Filter
bogdanm 82:6473597d706e 485 * programming and latency details appear in the Functional descriptionThe CMP
bogdanm 82:6473597d706e 486 * module can be used to compare two analog input voltages applied to INP and INM. .
bogdanm 82:6473597d706e 487 * This field has no effect when CR1[SE]=1. In that case, the external SAMPLE
bogdanm 82:6473597d706e 488 * signal is used to determine the sampling period.
bogdanm 82:6473597d706e 489 */
bogdanm 82:6473597d706e 490 //@{
bogdanm 82:6473597d706e 491 #define BP_CMP_FPR_FILT_PER (0U) //!< Bit position for CMP_FPR_FILT_PER.
bogdanm 82:6473597d706e 492 #define BM_CMP_FPR_FILT_PER (0xFFU) //!< Bit mask for CMP_FPR_FILT_PER.
bogdanm 82:6473597d706e 493 #define BS_CMP_FPR_FILT_PER (8U) //!< Bit field size in bits for CMP_FPR_FILT_PER.
bogdanm 82:6473597d706e 494
bogdanm 82:6473597d706e 495 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 496 //! @brief Read current value of the CMP_FPR_FILT_PER field.
bogdanm 82:6473597d706e 497 #define BR_CMP_FPR_FILT_PER(x) (HW_CMP_FPR(x).U)
bogdanm 82:6473597d706e 498 #endif
bogdanm 82:6473597d706e 499
bogdanm 82:6473597d706e 500 //! @brief Format value for bitfield CMP_FPR_FILT_PER.
bogdanm 82:6473597d706e 501 #define BF_CMP_FPR_FILT_PER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_FPR_FILT_PER), uint8_t) & BM_CMP_FPR_FILT_PER)
bogdanm 82:6473597d706e 502
bogdanm 82:6473597d706e 503 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 504 //! @brief Set the FILT_PER field to a new value.
bogdanm 82:6473597d706e 505 #define BW_CMP_FPR_FILT_PER(x, v) (HW_CMP_FPR_WR(x, v))
bogdanm 82:6473597d706e 506 #endif
bogdanm 82:6473597d706e 507 //@}
bogdanm 82:6473597d706e 508
bogdanm 82:6473597d706e 509 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 510 // HW_CMP_SCR - CMP Status and Control Register
bogdanm 82:6473597d706e 511 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 512
bogdanm 82:6473597d706e 513 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 514 /*!
bogdanm 82:6473597d706e 515 * @brief HW_CMP_SCR - CMP Status and Control Register (RW)
bogdanm 82:6473597d706e 516 *
bogdanm 82:6473597d706e 517 * Reset value: 0x00U
bogdanm 82:6473597d706e 518 */
bogdanm 82:6473597d706e 519 typedef union _hw_cmp_scr
bogdanm 82:6473597d706e 520 {
bogdanm 82:6473597d706e 521 uint8_t U;
bogdanm 82:6473597d706e 522 struct _hw_cmp_scr_bitfields
bogdanm 82:6473597d706e 523 {
bogdanm 82:6473597d706e 524 uint8_t COUT : 1; //!< [0] Analog Comparator Output
bogdanm 82:6473597d706e 525 uint8_t CFF : 1; //!< [1] Analog Comparator Flag Falling
bogdanm 82:6473597d706e 526 uint8_t CFR : 1; //!< [2] Analog Comparator Flag Rising
bogdanm 82:6473597d706e 527 uint8_t IEF : 1; //!< [3] Comparator Interrupt Enable Falling
bogdanm 82:6473597d706e 528 uint8_t IER : 1; //!< [4] Comparator Interrupt Enable Rising
bogdanm 82:6473597d706e 529 uint8_t RESERVED0 : 1; //!< [5]
bogdanm 82:6473597d706e 530 uint8_t DMAEN : 1; //!< [6] DMA Enable Control
bogdanm 82:6473597d706e 531 uint8_t RESERVED1 : 1; //!< [7]
bogdanm 82:6473597d706e 532 } B;
bogdanm 82:6473597d706e 533 } hw_cmp_scr_t;
bogdanm 82:6473597d706e 534 #endif
bogdanm 82:6473597d706e 535
bogdanm 82:6473597d706e 536 /*!
bogdanm 82:6473597d706e 537 * @name Constants and macros for entire CMP_SCR register
bogdanm 82:6473597d706e 538 */
bogdanm 82:6473597d706e 539 //@{
bogdanm 82:6473597d706e 540 #define HW_CMP_SCR_ADDR(x) (REGS_CMP_BASE(x) + 0x3U)
bogdanm 82:6473597d706e 541
bogdanm 82:6473597d706e 542 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 543 #define HW_CMP_SCR(x) (*(__IO hw_cmp_scr_t *) HW_CMP_SCR_ADDR(x))
bogdanm 82:6473597d706e 544 #define HW_CMP_SCR_RD(x) (HW_CMP_SCR(x).U)
bogdanm 82:6473597d706e 545 #define HW_CMP_SCR_WR(x, v) (HW_CMP_SCR(x).U = (v))
bogdanm 82:6473597d706e 546 #define HW_CMP_SCR_SET(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) | (v)))
bogdanm 82:6473597d706e 547 #define HW_CMP_SCR_CLR(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) & ~(v)))
bogdanm 82:6473597d706e 548 #define HW_CMP_SCR_TOG(x, v) (HW_CMP_SCR_WR(x, HW_CMP_SCR_RD(x) ^ (v)))
bogdanm 82:6473597d706e 549 #endif
bogdanm 82:6473597d706e 550 //@}
bogdanm 82:6473597d706e 551
bogdanm 82:6473597d706e 552 /*
bogdanm 82:6473597d706e 553 * Constants & macros for individual CMP_SCR bitfields
bogdanm 82:6473597d706e 554 */
bogdanm 82:6473597d706e 555
bogdanm 82:6473597d706e 556 /*!
bogdanm 82:6473597d706e 557 * @name Register CMP_SCR, field COUT[0] (RO)
bogdanm 82:6473597d706e 558 *
bogdanm 82:6473597d706e 559 * Returns the current value of the Analog Comparator output, when read. The
bogdanm 82:6473597d706e 560 * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
bogdanm 82:6473597d706e 561 * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
bogdanm 82:6473597d706e 562 */
bogdanm 82:6473597d706e 563 //@{
bogdanm 82:6473597d706e 564 #define BP_CMP_SCR_COUT (0U) //!< Bit position for CMP_SCR_COUT.
bogdanm 82:6473597d706e 565 #define BM_CMP_SCR_COUT (0x01U) //!< Bit mask for CMP_SCR_COUT.
bogdanm 82:6473597d706e 566 #define BS_CMP_SCR_COUT (1U) //!< Bit field size in bits for CMP_SCR_COUT.
bogdanm 82:6473597d706e 567
bogdanm 82:6473597d706e 568 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 569 //! @brief Read current value of the CMP_SCR_COUT field.
bogdanm 82:6473597d706e 570 #define BR_CMP_SCR_COUT(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_COUT))
bogdanm 82:6473597d706e 571 #endif
bogdanm 82:6473597d706e 572 //@}
bogdanm 82:6473597d706e 573
bogdanm 82:6473597d706e 574 /*!
bogdanm 82:6473597d706e 575 * @name Register CMP_SCR, field CFF[1] (W1C)
bogdanm 82:6473597d706e 576 *
bogdanm 82:6473597d706e 577 * Detects a falling-edge on COUT, when set, during normal operation. CFF is
bogdanm 82:6473597d706e 578 * cleared by writing 1 to it. During Stop modes, CFF is level sensitive is edge
bogdanm 82:6473597d706e 579 * sensitive .
bogdanm 82:6473597d706e 580 *
bogdanm 82:6473597d706e 581 * Values:
bogdanm 82:6473597d706e 582 * - 0 - Falling-edge on COUT has not been detected.
bogdanm 82:6473597d706e 583 * - 1 - Falling-edge on COUT has occurred.
bogdanm 82:6473597d706e 584 */
bogdanm 82:6473597d706e 585 //@{
bogdanm 82:6473597d706e 586 #define BP_CMP_SCR_CFF (1U) //!< Bit position for CMP_SCR_CFF.
bogdanm 82:6473597d706e 587 #define BM_CMP_SCR_CFF (0x02U) //!< Bit mask for CMP_SCR_CFF.
bogdanm 82:6473597d706e 588 #define BS_CMP_SCR_CFF (1U) //!< Bit field size in bits for CMP_SCR_CFF.
bogdanm 82:6473597d706e 589
bogdanm 82:6473597d706e 590 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 591 //! @brief Read current value of the CMP_SCR_CFF field.
bogdanm 82:6473597d706e 592 #define BR_CMP_SCR_CFF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF))
bogdanm 82:6473597d706e 593 #endif
bogdanm 82:6473597d706e 594
bogdanm 82:6473597d706e 595 //! @brief Format value for bitfield CMP_SCR_CFF.
bogdanm 82:6473597d706e 596 #define BF_CMP_SCR_CFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_CFF), uint8_t) & BM_CMP_SCR_CFF)
bogdanm 82:6473597d706e 597
bogdanm 82:6473597d706e 598 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 599 //! @brief Set the CFF field to a new value.
bogdanm 82:6473597d706e 600 #define BW_CMP_SCR_CFF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFF) = (v))
bogdanm 82:6473597d706e 601 #endif
bogdanm 82:6473597d706e 602 //@}
bogdanm 82:6473597d706e 603
bogdanm 82:6473597d706e 604 /*!
bogdanm 82:6473597d706e 605 * @name Register CMP_SCR, field CFR[2] (W1C)
bogdanm 82:6473597d706e 606 *
bogdanm 82:6473597d706e 607 * Detects a rising-edge on COUT, when set, during normal operation. CFR is
bogdanm 82:6473597d706e 608 * cleared by writing 1 to it. During Stop modes, CFR is level sensitive is edge
bogdanm 82:6473597d706e 609 * sensitive .
bogdanm 82:6473597d706e 610 *
bogdanm 82:6473597d706e 611 * Values:
bogdanm 82:6473597d706e 612 * - 0 - Rising-edge on COUT has not been detected.
bogdanm 82:6473597d706e 613 * - 1 - Rising-edge on COUT has occurred.
bogdanm 82:6473597d706e 614 */
bogdanm 82:6473597d706e 615 //@{
bogdanm 82:6473597d706e 616 #define BP_CMP_SCR_CFR (2U) //!< Bit position for CMP_SCR_CFR.
bogdanm 82:6473597d706e 617 #define BM_CMP_SCR_CFR (0x04U) //!< Bit mask for CMP_SCR_CFR.
bogdanm 82:6473597d706e 618 #define BS_CMP_SCR_CFR (1U) //!< Bit field size in bits for CMP_SCR_CFR.
bogdanm 82:6473597d706e 619
bogdanm 82:6473597d706e 620 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 621 //! @brief Read current value of the CMP_SCR_CFR field.
bogdanm 82:6473597d706e 622 #define BR_CMP_SCR_CFR(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR))
bogdanm 82:6473597d706e 623 #endif
bogdanm 82:6473597d706e 624
bogdanm 82:6473597d706e 625 //! @brief Format value for bitfield CMP_SCR_CFR.
bogdanm 82:6473597d706e 626 #define BF_CMP_SCR_CFR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_CFR), uint8_t) & BM_CMP_SCR_CFR)
bogdanm 82:6473597d706e 627
bogdanm 82:6473597d706e 628 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 629 //! @brief Set the CFR field to a new value.
bogdanm 82:6473597d706e 630 #define BW_CMP_SCR_CFR(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_CFR) = (v))
bogdanm 82:6473597d706e 631 #endif
bogdanm 82:6473597d706e 632 //@}
bogdanm 82:6473597d706e 633
bogdanm 82:6473597d706e 634 /*!
bogdanm 82:6473597d706e 635 * @name Register CMP_SCR, field IEF[3] (RW)
bogdanm 82:6473597d706e 636 *
bogdanm 82:6473597d706e 637 * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
bogdanm 82:6473597d706e 638 * will be asserted when CFF is set.
bogdanm 82:6473597d706e 639 *
bogdanm 82:6473597d706e 640 * Values:
bogdanm 82:6473597d706e 641 * - 0 - Interrupt is disabled.
bogdanm 82:6473597d706e 642 * - 1 - Interrupt is enabled.
bogdanm 82:6473597d706e 643 */
bogdanm 82:6473597d706e 644 //@{
bogdanm 82:6473597d706e 645 #define BP_CMP_SCR_IEF (3U) //!< Bit position for CMP_SCR_IEF.
bogdanm 82:6473597d706e 646 #define BM_CMP_SCR_IEF (0x08U) //!< Bit mask for CMP_SCR_IEF.
bogdanm 82:6473597d706e 647 #define BS_CMP_SCR_IEF (1U) //!< Bit field size in bits for CMP_SCR_IEF.
bogdanm 82:6473597d706e 648
bogdanm 82:6473597d706e 649 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 650 //! @brief Read current value of the CMP_SCR_IEF field.
bogdanm 82:6473597d706e 651 #define BR_CMP_SCR_IEF(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF))
bogdanm 82:6473597d706e 652 #endif
bogdanm 82:6473597d706e 653
bogdanm 82:6473597d706e 654 //! @brief Format value for bitfield CMP_SCR_IEF.
bogdanm 82:6473597d706e 655 #define BF_CMP_SCR_IEF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_IEF), uint8_t) & BM_CMP_SCR_IEF)
bogdanm 82:6473597d706e 656
bogdanm 82:6473597d706e 657 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 658 //! @brief Set the IEF field to a new value.
bogdanm 82:6473597d706e 659 #define BW_CMP_SCR_IEF(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IEF) = (v))
bogdanm 82:6473597d706e 660 #endif
bogdanm 82:6473597d706e 661 //@}
bogdanm 82:6473597d706e 662
bogdanm 82:6473597d706e 663 /*!
bogdanm 82:6473597d706e 664 * @name Register CMP_SCR, field IER[4] (RW)
bogdanm 82:6473597d706e 665 *
bogdanm 82:6473597d706e 666 * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
bogdanm 82:6473597d706e 667 * will be asserted when CFR is set.
bogdanm 82:6473597d706e 668 *
bogdanm 82:6473597d706e 669 * Values:
bogdanm 82:6473597d706e 670 * - 0 - Interrupt is disabled.
bogdanm 82:6473597d706e 671 * - 1 - Interrupt is enabled.
bogdanm 82:6473597d706e 672 */
bogdanm 82:6473597d706e 673 //@{
bogdanm 82:6473597d706e 674 #define BP_CMP_SCR_IER (4U) //!< Bit position for CMP_SCR_IER.
bogdanm 82:6473597d706e 675 #define BM_CMP_SCR_IER (0x10U) //!< Bit mask for CMP_SCR_IER.
bogdanm 82:6473597d706e 676 #define BS_CMP_SCR_IER (1U) //!< Bit field size in bits for CMP_SCR_IER.
bogdanm 82:6473597d706e 677
bogdanm 82:6473597d706e 678 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 679 //! @brief Read current value of the CMP_SCR_IER field.
bogdanm 82:6473597d706e 680 #define BR_CMP_SCR_IER(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER))
bogdanm 82:6473597d706e 681 #endif
bogdanm 82:6473597d706e 682
bogdanm 82:6473597d706e 683 //! @brief Format value for bitfield CMP_SCR_IER.
bogdanm 82:6473597d706e 684 #define BF_CMP_SCR_IER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_IER), uint8_t) & BM_CMP_SCR_IER)
bogdanm 82:6473597d706e 685
bogdanm 82:6473597d706e 686 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 687 //! @brief Set the IER field to a new value.
bogdanm 82:6473597d706e 688 #define BW_CMP_SCR_IER(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_IER) = (v))
bogdanm 82:6473597d706e 689 #endif
bogdanm 82:6473597d706e 690 //@}
bogdanm 82:6473597d706e 691
bogdanm 82:6473597d706e 692 /*!
bogdanm 82:6473597d706e 693 * @name Register CMP_SCR, field DMAEN[6] (RW)
bogdanm 82:6473597d706e 694 *
bogdanm 82:6473597d706e 695 * Enables the DMA transfer triggered from the CMP module. When this field is
bogdanm 82:6473597d706e 696 * set, a DMA request is asserted when CFR or CFF is set.
bogdanm 82:6473597d706e 697 *
bogdanm 82:6473597d706e 698 * Values:
bogdanm 82:6473597d706e 699 * - 0 - DMA is disabled.
bogdanm 82:6473597d706e 700 * - 1 - DMA is enabled.
bogdanm 82:6473597d706e 701 */
bogdanm 82:6473597d706e 702 //@{
bogdanm 82:6473597d706e 703 #define BP_CMP_SCR_DMAEN (6U) //!< Bit position for CMP_SCR_DMAEN.
bogdanm 82:6473597d706e 704 #define BM_CMP_SCR_DMAEN (0x40U) //!< Bit mask for CMP_SCR_DMAEN.
bogdanm 82:6473597d706e 705 #define BS_CMP_SCR_DMAEN (1U) //!< Bit field size in bits for CMP_SCR_DMAEN.
bogdanm 82:6473597d706e 706
bogdanm 82:6473597d706e 707 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 708 //! @brief Read current value of the CMP_SCR_DMAEN field.
bogdanm 82:6473597d706e 709 #define BR_CMP_SCR_DMAEN(x) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN))
bogdanm 82:6473597d706e 710 #endif
bogdanm 82:6473597d706e 711
bogdanm 82:6473597d706e 712 //! @brief Format value for bitfield CMP_SCR_DMAEN.
bogdanm 82:6473597d706e 713 #define BF_CMP_SCR_DMAEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_SCR_DMAEN), uint8_t) & BM_CMP_SCR_DMAEN)
bogdanm 82:6473597d706e 714
bogdanm 82:6473597d706e 715 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 716 //! @brief Set the DMAEN field to a new value.
bogdanm 82:6473597d706e 717 #define BW_CMP_SCR_DMAEN(x, v) (BITBAND_ACCESS8(HW_CMP_SCR_ADDR(x), BP_CMP_SCR_DMAEN) = (v))
bogdanm 82:6473597d706e 718 #endif
bogdanm 82:6473597d706e 719 //@}
bogdanm 82:6473597d706e 720
bogdanm 82:6473597d706e 721 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 722 // HW_CMP_DACCR - DAC Control Register
bogdanm 82:6473597d706e 723 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 724
bogdanm 82:6473597d706e 725 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 726 /*!
bogdanm 82:6473597d706e 727 * @brief HW_CMP_DACCR - DAC Control Register (RW)
bogdanm 82:6473597d706e 728 *
bogdanm 82:6473597d706e 729 * Reset value: 0x00U
bogdanm 82:6473597d706e 730 */
bogdanm 82:6473597d706e 731 typedef union _hw_cmp_daccr
bogdanm 82:6473597d706e 732 {
bogdanm 82:6473597d706e 733 uint8_t U;
bogdanm 82:6473597d706e 734 struct _hw_cmp_daccr_bitfields
bogdanm 82:6473597d706e 735 {
bogdanm 82:6473597d706e 736 uint8_t VOSEL : 6; //!< [5:0] DAC Output Voltage Select
bogdanm 82:6473597d706e 737 uint8_t VRSEL : 1; //!< [6] Supply Voltage Reference Source Select
bogdanm 82:6473597d706e 738 uint8_t DACEN : 1; //!< [7] DAC Enable
bogdanm 82:6473597d706e 739 } B;
bogdanm 82:6473597d706e 740 } hw_cmp_daccr_t;
bogdanm 82:6473597d706e 741 #endif
bogdanm 82:6473597d706e 742
bogdanm 82:6473597d706e 743 /*!
bogdanm 82:6473597d706e 744 * @name Constants and macros for entire CMP_DACCR register
bogdanm 82:6473597d706e 745 */
bogdanm 82:6473597d706e 746 //@{
bogdanm 82:6473597d706e 747 #define HW_CMP_DACCR_ADDR(x) (REGS_CMP_BASE(x) + 0x4U)
bogdanm 82:6473597d706e 748
bogdanm 82:6473597d706e 749 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 750 #define HW_CMP_DACCR(x) (*(__IO hw_cmp_daccr_t *) HW_CMP_DACCR_ADDR(x))
bogdanm 82:6473597d706e 751 #define HW_CMP_DACCR_RD(x) (HW_CMP_DACCR(x).U)
bogdanm 82:6473597d706e 752 #define HW_CMP_DACCR_WR(x, v) (HW_CMP_DACCR(x).U = (v))
bogdanm 82:6473597d706e 753 #define HW_CMP_DACCR_SET(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) | (v)))
bogdanm 82:6473597d706e 754 #define HW_CMP_DACCR_CLR(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) & ~(v)))
bogdanm 82:6473597d706e 755 #define HW_CMP_DACCR_TOG(x, v) (HW_CMP_DACCR_WR(x, HW_CMP_DACCR_RD(x) ^ (v)))
bogdanm 82:6473597d706e 756 #endif
bogdanm 82:6473597d706e 757 //@}
bogdanm 82:6473597d706e 758
bogdanm 82:6473597d706e 759 /*
bogdanm 82:6473597d706e 760 * Constants & macros for individual CMP_DACCR bitfields
bogdanm 82:6473597d706e 761 */
bogdanm 82:6473597d706e 762
bogdanm 82:6473597d706e 763 /*!
bogdanm 82:6473597d706e 764 * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
bogdanm 82:6473597d706e 765 *
bogdanm 82:6473597d706e 766 * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
bogdanm 82:6473597d706e 767 * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
bogdanm 82:6473597d706e 768 */
bogdanm 82:6473597d706e 769 //@{
bogdanm 82:6473597d706e 770 #define BP_CMP_DACCR_VOSEL (0U) //!< Bit position for CMP_DACCR_VOSEL.
bogdanm 82:6473597d706e 771 #define BM_CMP_DACCR_VOSEL (0x3FU) //!< Bit mask for CMP_DACCR_VOSEL.
bogdanm 82:6473597d706e 772 #define BS_CMP_DACCR_VOSEL (6U) //!< Bit field size in bits for CMP_DACCR_VOSEL.
bogdanm 82:6473597d706e 773
bogdanm 82:6473597d706e 774 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 775 //! @brief Read current value of the CMP_DACCR_VOSEL field.
bogdanm 82:6473597d706e 776 #define BR_CMP_DACCR_VOSEL(x) (HW_CMP_DACCR(x).B.VOSEL)
bogdanm 82:6473597d706e 777 #endif
bogdanm 82:6473597d706e 778
bogdanm 82:6473597d706e 779 //! @brief Format value for bitfield CMP_DACCR_VOSEL.
bogdanm 82:6473597d706e 780 #define BF_CMP_DACCR_VOSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_VOSEL), uint8_t) & BM_CMP_DACCR_VOSEL)
bogdanm 82:6473597d706e 781
bogdanm 82:6473597d706e 782 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 783 //! @brief Set the VOSEL field to a new value.
bogdanm 82:6473597d706e 784 #define BW_CMP_DACCR_VOSEL(x, v) (HW_CMP_DACCR_WR(x, (HW_CMP_DACCR_RD(x) & ~BM_CMP_DACCR_VOSEL) | BF_CMP_DACCR_VOSEL(v)))
bogdanm 82:6473597d706e 785 #endif
bogdanm 82:6473597d706e 786 //@}
bogdanm 82:6473597d706e 787
bogdanm 82:6473597d706e 788 /*!
bogdanm 82:6473597d706e 789 * @name Register CMP_DACCR, field VRSEL[6] (RW)
bogdanm 82:6473597d706e 790 *
bogdanm 82:6473597d706e 791 * Values:
bogdanm 82:6473597d706e 792 * - 0 - V is selected as resistor ladder network supply reference V. in1 in
bogdanm 82:6473597d706e 793 * - 1 - V is selected as resistor ladder network supply reference V. in2 in
bogdanm 82:6473597d706e 794 */
bogdanm 82:6473597d706e 795 //@{
bogdanm 82:6473597d706e 796 #define BP_CMP_DACCR_VRSEL (6U) //!< Bit position for CMP_DACCR_VRSEL.
bogdanm 82:6473597d706e 797 #define BM_CMP_DACCR_VRSEL (0x40U) //!< Bit mask for CMP_DACCR_VRSEL.
bogdanm 82:6473597d706e 798 #define BS_CMP_DACCR_VRSEL (1U) //!< Bit field size in bits for CMP_DACCR_VRSEL.
bogdanm 82:6473597d706e 799
bogdanm 82:6473597d706e 800 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 801 //! @brief Read current value of the CMP_DACCR_VRSEL field.
bogdanm 82:6473597d706e 802 #define BR_CMP_DACCR_VRSEL(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL))
bogdanm 82:6473597d706e 803 #endif
bogdanm 82:6473597d706e 804
bogdanm 82:6473597d706e 805 //! @brief Format value for bitfield CMP_DACCR_VRSEL.
bogdanm 82:6473597d706e 806 #define BF_CMP_DACCR_VRSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_VRSEL), uint8_t) & BM_CMP_DACCR_VRSEL)
bogdanm 82:6473597d706e 807
bogdanm 82:6473597d706e 808 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 809 //! @brief Set the VRSEL field to a new value.
bogdanm 82:6473597d706e 810 #define BW_CMP_DACCR_VRSEL(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_VRSEL) = (v))
bogdanm 82:6473597d706e 811 #endif
bogdanm 82:6473597d706e 812 //@}
bogdanm 82:6473597d706e 813
bogdanm 82:6473597d706e 814 /*!
bogdanm 82:6473597d706e 815 * @name Register CMP_DACCR, field DACEN[7] (RW)
bogdanm 82:6473597d706e 816 *
bogdanm 82:6473597d706e 817 * Enables the DAC. When the DAC is disabled, it is powered down to conserve
bogdanm 82:6473597d706e 818 * power.
bogdanm 82:6473597d706e 819 *
bogdanm 82:6473597d706e 820 * Values:
bogdanm 82:6473597d706e 821 * - 0 - DAC is disabled.
bogdanm 82:6473597d706e 822 * - 1 - DAC is enabled.
bogdanm 82:6473597d706e 823 */
bogdanm 82:6473597d706e 824 //@{
bogdanm 82:6473597d706e 825 #define BP_CMP_DACCR_DACEN (7U) //!< Bit position for CMP_DACCR_DACEN.
bogdanm 82:6473597d706e 826 #define BM_CMP_DACCR_DACEN (0x80U) //!< Bit mask for CMP_DACCR_DACEN.
bogdanm 82:6473597d706e 827 #define BS_CMP_DACCR_DACEN (1U) //!< Bit field size in bits for CMP_DACCR_DACEN.
bogdanm 82:6473597d706e 828
bogdanm 82:6473597d706e 829 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 830 //! @brief Read current value of the CMP_DACCR_DACEN field.
bogdanm 82:6473597d706e 831 #define BR_CMP_DACCR_DACEN(x) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN))
bogdanm 82:6473597d706e 832 #endif
bogdanm 82:6473597d706e 833
bogdanm 82:6473597d706e 834 //! @brief Format value for bitfield CMP_DACCR_DACEN.
bogdanm 82:6473597d706e 835 #define BF_CMP_DACCR_DACEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_DACCR_DACEN), uint8_t) & BM_CMP_DACCR_DACEN)
bogdanm 82:6473597d706e 836
bogdanm 82:6473597d706e 837 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 838 //! @brief Set the DACEN field to a new value.
bogdanm 82:6473597d706e 839 #define BW_CMP_DACCR_DACEN(x, v) (BITBAND_ACCESS8(HW_CMP_DACCR_ADDR(x), BP_CMP_DACCR_DACEN) = (v))
bogdanm 82:6473597d706e 840 #endif
bogdanm 82:6473597d706e 841 //@}
bogdanm 82:6473597d706e 842
bogdanm 82:6473597d706e 843 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 844 // HW_CMP_MUXCR - MUX Control Register
bogdanm 82:6473597d706e 845 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 846
bogdanm 82:6473597d706e 847 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 848 /*!
bogdanm 82:6473597d706e 849 * @brief HW_CMP_MUXCR - MUX Control Register (RW)
bogdanm 82:6473597d706e 850 *
bogdanm 82:6473597d706e 851 * Reset value: 0x00U
bogdanm 82:6473597d706e 852 */
bogdanm 82:6473597d706e 853 typedef union _hw_cmp_muxcr
bogdanm 82:6473597d706e 854 {
bogdanm 82:6473597d706e 855 uint8_t U;
bogdanm 82:6473597d706e 856 struct _hw_cmp_muxcr_bitfields
bogdanm 82:6473597d706e 857 {
bogdanm 82:6473597d706e 858 uint8_t MSEL : 3; //!< [2:0] Minus Input Mux Control
bogdanm 82:6473597d706e 859 uint8_t PSEL : 3; //!< [5:3] Plus Input Mux Control
bogdanm 82:6473597d706e 860 uint8_t RESERVED0 : 1; //!< [6]
bogdanm 82:6473597d706e 861 uint8_t PSTM : 1; //!< [7] Pass Through Mode Enable
bogdanm 82:6473597d706e 862 } B;
bogdanm 82:6473597d706e 863 } hw_cmp_muxcr_t;
bogdanm 82:6473597d706e 864 #endif
bogdanm 82:6473597d706e 865
bogdanm 82:6473597d706e 866 /*!
bogdanm 82:6473597d706e 867 * @name Constants and macros for entire CMP_MUXCR register
bogdanm 82:6473597d706e 868 */
bogdanm 82:6473597d706e 869 //@{
bogdanm 82:6473597d706e 870 #define HW_CMP_MUXCR_ADDR(x) (REGS_CMP_BASE(x) + 0x5U)
bogdanm 82:6473597d706e 871
bogdanm 82:6473597d706e 872 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 873 #define HW_CMP_MUXCR(x) (*(__IO hw_cmp_muxcr_t *) HW_CMP_MUXCR_ADDR(x))
bogdanm 82:6473597d706e 874 #define HW_CMP_MUXCR_RD(x) (HW_CMP_MUXCR(x).U)
bogdanm 82:6473597d706e 875 #define HW_CMP_MUXCR_WR(x, v) (HW_CMP_MUXCR(x).U = (v))
bogdanm 82:6473597d706e 876 #define HW_CMP_MUXCR_SET(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) | (v)))
bogdanm 82:6473597d706e 877 #define HW_CMP_MUXCR_CLR(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) & ~(v)))
bogdanm 82:6473597d706e 878 #define HW_CMP_MUXCR_TOG(x, v) (HW_CMP_MUXCR_WR(x, HW_CMP_MUXCR_RD(x) ^ (v)))
bogdanm 82:6473597d706e 879 #endif
bogdanm 82:6473597d706e 880 //@}
bogdanm 82:6473597d706e 881
bogdanm 82:6473597d706e 882 /*
bogdanm 82:6473597d706e 883 * Constants & macros for individual CMP_MUXCR bitfields
bogdanm 82:6473597d706e 884 */
bogdanm 82:6473597d706e 885
bogdanm 82:6473597d706e 886 /*!
bogdanm 82:6473597d706e 887 * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
bogdanm 82:6473597d706e 888 *
bogdanm 82:6473597d706e 889 * Determines which input is selected for the minus input of the comparator. For
bogdanm 82:6473597d706e 890 * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
bogdanm 82:6473597d706e 891 * operation selects the same input for both muxes, the comparator automatically
bogdanm 82:6473597d706e 892 * shuts down to prevent itself from becoming a noise generator.
bogdanm 82:6473597d706e 893 *
bogdanm 82:6473597d706e 894 * Values:
bogdanm 82:6473597d706e 895 * - 000 - IN0
bogdanm 82:6473597d706e 896 * - 001 - IN1
bogdanm 82:6473597d706e 897 * - 010 - IN2
bogdanm 82:6473597d706e 898 * - 011 - IN3
bogdanm 82:6473597d706e 899 * - 100 - IN4
bogdanm 82:6473597d706e 900 * - 101 - IN5
bogdanm 82:6473597d706e 901 * - 110 - IN6
bogdanm 82:6473597d706e 902 * - 111 - IN7
bogdanm 82:6473597d706e 903 */
bogdanm 82:6473597d706e 904 //@{
bogdanm 82:6473597d706e 905 #define BP_CMP_MUXCR_MSEL (0U) //!< Bit position for CMP_MUXCR_MSEL.
bogdanm 82:6473597d706e 906 #define BM_CMP_MUXCR_MSEL (0x07U) //!< Bit mask for CMP_MUXCR_MSEL.
bogdanm 82:6473597d706e 907 #define BS_CMP_MUXCR_MSEL (3U) //!< Bit field size in bits for CMP_MUXCR_MSEL.
bogdanm 82:6473597d706e 908
bogdanm 82:6473597d706e 909 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 910 //! @brief Read current value of the CMP_MUXCR_MSEL field.
bogdanm 82:6473597d706e 911 #define BR_CMP_MUXCR_MSEL(x) (HW_CMP_MUXCR(x).B.MSEL)
bogdanm 82:6473597d706e 912 #endif
bogdanm 82:6473597d706e 913
bogdanm 82:6473597d706e 914 //! @brief Format value for bitfield CMP_MUXCR_MSEL.
bogdanm 82:6473597d706e 915 #define BF_CMP_MUXCR_MSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_MSEL), uint8_t) & BM_CMP_MUXCR_MSEL)
bogdanm 82:6473597d706e 916
bogdanm 82:6473597d706e 917 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 918 //! @brief Set the MSEL field to a new value.
bogdanm 82:6473597d706e 919 #define BW_CMP_MUXCR_MSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_MSEL) | BF_CMP_MUXCR_MSEL(v)))
bogdanm 82:6473597d706e 920 #endif
bogdanm 82:6473597d706e 921 //@}
bogdanm 82:6473597d706e 922
bogdanm 82:6473597d706e 923 /*!
bogdanm 82:6473597d706e 924 * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
bogdanm 82:6473597d706e 925 *
bogdanm 82:6473597d706e 926 * Determines which input is selected for the plus input of the comparator. For
bogdanm 82:6473597d706e 927 * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
bogdanm 82:6473597d706e 928 * operation selects the same input for both muxes, the comparator automatically
bogdanm 82:6473597d706e 929 * shuts down to prevent itself from becoming a noise generator.
bogdanm 82:6473597d706e 930 *
bogdanm 82:6473597d706e 931 * Values:
bogdanm 82:6473597d706e 932 * - 000 - IN0
bogdanm 82:6473597d706e 933 * - 001 - IN1
bogdanm 82:6473597d706e 934 * - 010 - IN2
bogdanm 82:6473597d706e 935 * - 011 - IN3
bogdanm 82:6473597d706e 936 * - 100 - IN4
bogdanm 82:6473597d706e 937 * - 101 - IN5
bogdanm 82:6473597d706e 938 * - 110 - IN6
bogdanm 82:6473597d706e 939 * - 111 - IN7
bogdanm 82:6473597d706e 940 */
bogdanm 82:6473597d706e 941 //@{
bogdanm 82:6473597d706e 942 #define BP_CMP_MUXCR_PSEL (3U) //!< Bit position for CMP_MUXCR_PSEL.
bogdanm 82:6473597d706e 943 #define BM_CMP_MUXCR_PSEL (0x38U) //!< Bit mask for CMP_MUXCR_PSEL.
bogdanm 82:6473597d706e 944 #define BS_CMP_MUXCR_PSEL (3U) //!< Bit field size in bits for CMP_MUXCR_PSEL.
bogdanm 82:6473597d706e 945
bogdanm 82:6473597d706e 946 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 947 //! @brief Read current value of the CMP_MUXCR_PSEL field.
bogdanm 82:6473597d706e 948 #define BR_CMP_MUXCR_PSEL(x) (HW_CMP_MUXCR(x).B.PSEL)
bogdanm 82:6473597d706e 949 #endif
bogdanm 82:6473597d706e 950
bogdanm 82:6473597d706e 951 //! @brief Format value for bitfield CMP_MUXCR_PSEL.
bogdanm 82:6473597d706e 952 #define BF_CMP_MUXCR_PSEL(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_PSEL), uint8_t) & BM_CMP_MUXCR_PSEL)
bogdanm 82:6473597d706e 953
bogdanm 82:6473597d706e 954 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 955 //! @brief Set the PSEL field to a new value.
bogdanm 82:6473597d706e 956 #define BW_CMP_MUXCR_PSEL(x, v) (HW_CMP_MUXCR_WR(x, (HW_CMP_MUXCR_RD(x) & ~BM_CMP_MUXCR_PSEL) | BF_CMP_MUXCR_PSEL(v)))
bogdanm 82:6473597d706e 957 #endif
bogdanm 82:6473597d706e 958 //@}
bogdanm 82:6473597d706e 959
bogdanm 82:6473597d706e 960 /*!
bogdanm 82:6473597d706e 961 * @name Register CMP_MUXCR, field PSTM[7] (RW)
bogdanm 82:6473597d706e 962 *
bogdanm 82:6473597d706e 963 * This bit is used to enable to MUX pass through mode. Pass through mode is
bogdanm 82:6473597d706e 964 * always available but for some devices this feature must be always disabled due to
bogdanm 82:6473597d706e 965 * the lack of package pins.
bogdanm 82:6473597d706e 966 *
bogdanm 82:6473597d706e 967 * Values:
bogdanm 82:6473597d706e 968 * - 0 - Pass Through Mode is disabled.
bogdanm 82:6473597d706e 969 * - 1 - Pass Through Mode is enabled.
bogdanm 82:6473597d706e 970 */
bogdanm 82:6473597d706e 971 //@{
bogdanm 82:6473597d706e 972 #define BP_CMP_MUXCR_PSTM (7U) //!< Bit position for CMP_MUXCR_PSTM.
bogdanm 82:6473597d706e 973 #define BM_CMP_MUXCR_PSTM (0x80U) //!< Bit mask for CMP_MUXCR_PSTM.
bogdanm 82:6473597d706e 974 #define BS_CMP_MUXCR_PSTM (1U) //!< Bit field size in bits for CMP_MUXCR_PSTM.
bogdanm 82:6473597d706e 975
bogdanm 82:6473597d706e 976 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 977 //! @brief Read current value of the CMP_MUXCR_PSTM field.
bogdanm 82:6473597d706e 978 #define BR_CMP_MUXCR_PSTM(x) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM))
bogdanm 82:6473597d706e 979 #endif
bogdanm 82:6473597d706e 980
bogdanm 82:6473597d706e 981 //! @brief Format value for bitfield CMP_MUXCR_PSTM.
bogdanm 82:6473597d706e 982 #define BF_CMP_MUXCR_PSTM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_CMP_MUXCR_PSTM), uint8_t) & BM_CMP_MUXCR_PSTM)
bogdanm 82:6473597d706e 983
bogdanm 82:6473597d706e 984 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 985 //! @brief Set the PSTM field to a new value.
bogdanm 82:6473597d706e 986 #define BW_CMP_MUXCR_PSTM(x, v) (BITBAND_ACCESS8(HW_CMP_MUXCR_ADDR(x), BP_CMP_MUXCR_PSTM) = (v))
bogdanm 82:6473597d706e 987 #endif
bogdanm 82:6473597d706e 988 //@}
bogdanm 82:6473597d706e 989
bogdanm 82:6473597d706e 990 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 991 // hw_cmp_t - module struct
bogdanm 82:6473597d706e 992 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 993 /*!
bogdanm 82:6473597d706e 994 * @brief All CMP module registers.
bogdanm 82:6473597d706e 995 */
bogdanm 82:6473597d706e 996 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 997 #pragma pack(1)
bogdanm 82:6473597d706e 998 typedef struct _hw_cmp
bogdanm 82:6473597d706e 999 {
bogdanm 82:6473597d706e 1000 __IO hw_cmp_cr0_t CR0; //!< [0x0] CMP Control Register 0
bogdanm 82:6473597d706e 1001 __IO hw_cmp_cr1_t CR1; //!< [0x1] CMP Control Register 1
bogdanm 82:6473597d706e 1002 __IO hw_cmp_fpr_t FPR; //!< [0x2] CMP Filter Period Register
bogdanm 82:6473597d706e 1003 __IO hw_cmp_scr_t SCR; //!< [0x3] CMP Status and Control Register
bogdanm 82:6473597d706e 1004 __IO hw_cmp_daccr_t DACCR; //!< [0x4] DAC Control Register
bogdanm 82:6473597d706e 1005 __IO hw_cmp_muxcr_t MUXCR; //!< [0x5] MUX Control Register
bogdanm 82:6473597d706e 1006 } hw_cmp_t;
bogdanm 82:6473597d706e 1007 #pragma pack()
bogdanm 82:6473597d706e 1008
bogdanm 82:6473597d706e 1009 //! @brief Macro to access all CMP registers.
bogdanm 82:6473597d706e 1010 //! @param x CMP instance number.
bogdanm 82:6473597d706e 1011 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 1012 //! use the '&' operator, like <code>&HW_CMP(0)</code>.
bogdanm 82:6473597d706e 1013 #define HW_CMP(x) (*(hw_cmp_t *) REGS_CMP_BASE(x))
bogdanm 82:6473597d706e 1014 #endif
bogdanm 82:6473597d706e 1015
bogdanm 82:6473597d706e 1016 #endif // __HW_CMP_REGISTERS_H__
bogdanm 82:6473597d706e 1017 // v22/130726/0.9
bogdanm 82:6473597d706e 1018 // EOF