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mbed(SerialHalfDuplex入り)

TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@85:024bf7f99721, 2014-06-11 (annotated)

Committer:: bogdanm
Date:: Wed Jun 11 15:14:05 2014 +0100
Revision:: 85:024bf7f99721
Child:: 92:4fc01daae5a5

Release 85 of the mbed library



Main changes:



- K64F Ethernet fixes

- Updated tests

- Fixes for various mbed targets

- Code cleanup: fixed warnings, more consistent code style

- GCC support for K64F



There is a known issue with the I2C interface on some ST targets. If you

find the I2C interface problematic on your ST board, please log a bug

against this on mbed.org.

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_rcc_ex.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
bogdanm	85:024bf7f99721	5	* @version V1.0.0
bogdanm	85:024bf7f99721	6	* @date 28-May-2014
bogdanm	85:024bf7f99721	7	* @brief Header file of RCC HAL Extension module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
bogdanm	85:024bf7f99721	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
bogdanm	85:024bf7f99721	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
bogdanm	85:024bf7f99721	40	#define __STM32F0xx_HAL_RCC_EX_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
bogdanm	85:024bf7f99721	53	/** @addtogroup RCCEx
bogdanm	85:024bf7f99721	54	* @{
bogdanm	85:024bf7f99721	55	*/
bogdanm	85:024bf7f99721	56
bogdanm	85:024bf7f99721	57	/* Exported types ------------------------------------------------------------*/
bogdanm	85:024bf7f99721	58
bogdanm	85:024bf7f99721	59	/**
bogdanm	85:024bf7f99721	60	* @brief RCC extended clocks structure definition
bogdanm	85:024bf7f99721	61	*/
bogdanm	85:024bf7f99721	62	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)
bogdanm	85:024bf7f99721	63	typedef struct
bogdanm	85:024bf7f99721	64	{
bogdanm	85:024bf7f99721	65	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	66	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	67
bogdanm	85:024bf7f99721	68	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	69	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	70
bogdanm	85:024bf7f99721	71	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	72	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	73
bogdanm	85:024bf7f99721	74	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	75	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	76
bogdanm	85:024bf7f99721	77	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	78	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx */
bogdanm	85:024bf7f99721	79
bogdanm	85:024bf7f99721	80	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
bogdanm	85:024bf7f99721	81	typedef struct
bogdanm	85:024bf7f99721	82	{
bogdanm	85:024bf7f99721	83	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	84	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	85
bogdanm	85:024bf7f99721	86	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	87	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	88
bogdanm	85:024bf7f99721	89	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	90	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	91
bogdanm	85:024bf7f99721	92	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	93	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	94
bogdanm	85:024bf7f99721	95	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	96	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	97
bogdanm	85:024bf7f99721	98	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	85:024bf7f99721	99	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	85:024bf7f99721	100
bogdanm	85:024bf7f99721	101	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	102	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	85:024bf7f99721	103
bogdanm	85:024bf7f99721	104	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	105	typedef struct
bogdanm	85:024bf7f99721	106	{
bogdanm	85:024bf7f99721	107	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	108	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	109
bogdanm	85:024bf7f99721	110	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	111	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	112
bogdanm	85:024bf7f99721	113	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	114	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	115
bogdanm	85:024bf7f99721	116	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	117	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	118
bogdanm	85:024bf7f99721	119	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	120	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	121
bogdanm	85:024bf7f99721	122	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	123	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	124
bogdanm	85:024bf7f99721	125	#if defined(STM32F071xB)
bogdanm	85:024bf7f99721	126	typedef struct
bogdanm	85:024bf7f99721	127	{
bogdanm	85:024bf7f99721	128	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	129	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	130
bogdanm	85:024bf7f99721	131	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	132	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	133
bogdanm	85:024bf7f99721	134	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	135	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	136
bogdanm	85:024bf7f99721	137	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	138	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	139
bogdanm	85:024bf7f99721	140	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	141	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	142
bogdanm	85:024bf7f99721	143	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	144	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	145
bogdanm	85:024bf7f99721	146	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	147	#endif /* STM32F071xB */
bogdanm	85:024bf7f99721	148
bogdanm	85:024bf7f99721	149	#if defined(STM32F072xB)
bogdanm	85:024bf7f99721	150	typedef struct
bogdanm	85:024bf7f99721	151	{
bogdanm	85:024bf7f99721	152	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	153	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	154
bogdanm	85:024bf7f99721	155	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	156	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	157
bogdanm	85:024bf7f99721	158	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	159	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	160
bogdanm	85:024bf7f99721	161	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	162	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	163
bogdanm	85:024bf7f99721	164	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	165	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	166
bogdanm	85:024bf7f99721	167	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	168	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	169
bogdanm	85:024bf7f99721	170	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	85:024bf7f99721	171	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	85:024bf7f99721	172
bogdanm	85:024bf7f99721	173	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	174	#endif /* STM32F072xB */
bogdanm	85:024bf7f99721	175
bogdanm	85:024bf7f99721	176	#if defined(STM32F078xx)
bogdanm	85:024bf7f99721	177	typedef struct
bogdanm	85:024bf7f99721	178	{
bogdanm	85:024bf7f99721	179	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	180	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	181
bogdanm	85:024bf7f99721	182	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	183	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	184
bogdanm	85:024bf7f99721	185	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	186	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	187
bogdanm	85:024bf7f99721	188	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	189	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	190
bogdanm	85:024bf7f99721	191	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	192	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	193
bogdanm	85:024bf7f99721	194	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	195	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	196
bogdanm	85:024bf7f99721	197	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	198	#endif /* STM32F078xx */
bogdanm	85:024bf7f99721	199
bogdanm	85:024bf7f99721	200
bogdanm	85:024bf7f99721	201	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	202	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	203	/**
bogdanm	85:024bf7f99721	204	* @brief RCC CRS Status structures definition
bogdanm	85:024bf7f99721	205	*/
bogdanm	85:024bf7f99721	206	typedef enum
bogdanm	85:024bf7f99721	207	{
bogdanm	85:024bf7f99721	208	RCC_CRS_NONE = 0x00,
bogdanm	85:024bf7f99721	209	RCC_CRS_TIMEOUT = 0x01,
bogdanm	85:024bf7f99721	210	RCC_CRS_SYNCOK = 0x02,
bogdanm	85:024bf7f99721	211	RCC_CRS_SYNCWARM = 0x04,
bogdanm	85:024bf7f99721	212	RCC_CRS_SYNCERR = 0x08,
bogdanm	85:024bf7f99721	213	RCC_CRS_SYNCMISS = 0x10,
bogdanm	85:024bf7f99721	214	RCC_CRS_TRIMOV = 0x20
bogdanm	85:024bf7f99721	215	} RCC_CRSStatusTypeDef;
bogdanm	85:024bf7f99721	216
bogdanm	85:024bf7f99721	217	/**
bogdanm	85:024bf7f99721	218	* @brief RCC_CRS Init structure definition
bogdanm	85:024bf7f99721	219	*/
bogdanm	85:024bf7f99721	220	typedef struct
bogdanm	85:024bf7f99721	221	{
bogdanm	85:024bf7f99721	222	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
bogdanm	85:024bf7f99721	223	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
bogdanm	85:024bf7f99721	224
bogdanm	85:024bf7f99721	225	uint32_t Source; /*!< Specifies the SYNC signal source.
bogdanm	85:024bf7f99721	226	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
bogdanm	85:024bf7f99721	227
bogdanm	85:024bf7f99721	228	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
bogdanm	85:024bf7f99721	229	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
bogdanm	85:024bf7f99721	230
bogdanm	85:024bf7f99721	231	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
bogdanm	85:024bf7f99721	232	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
bogdanm	85:024bf7f99721	233	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
bogdanm	85:024bf7f99721	234
bogdanm	85:024bf7f99721	235	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
bogdanm	85:024bf7f99721	236	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
bogdanm	85:024bf7f99721	237
bogdanm	85:024bf7f99721	238	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
bogdanm	85:024bf7f99721	239	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
bogdanm	85:024bf7f99721	240
bogdanm	85:024bf7f99721	241	}RCC_CRSInitTypeDef;
bogdanm	85:024bf7f99721	242
bogdanm	85:024bf7f99721	243	/**
bogdanm	85:024bf7f99721	244	* @brief RCC_CRS Synchronization structure definition
bogdanm	85:024bf7f99721	245	*/
bogdanm	85:024bf7f99721	246	typedef struct
bogdanm	85:024bf7f99721	247	{
bogdanm	85:024bf7f99721	248	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
bogdanm	85:024bf7f99721	249	This parameter must be a number between 0 and 0xFFFF*/
bogdanm	85:024bf7f99721	250
bogdanm	85:024bf7f99721	251	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
bogdanm	85:024bf7f99721	252	This parameter must be a number between 0 and 0x3F */
bogdanm	85:024bf7f99721	253
bogdanm	85:024bf7f99721	254	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
bogdanm	85:024bf7f99721	255	value latched in the time of the last SYNC event.
bogdanm	85:024bf7f99721	256	This parameter must be a number between 0 and 0xFFFF */
bogdanm	85:024bf7f99721	257
bogdanm	85:024bf7f99721	258	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
bogdanm	85:024bf7f99721	259	frequency error counter latched in the time of the last SYNC event.
bogdanm	85:024bf7f99721	260	It shows whether the actual frequency is below or above the target.
bogdanm	85:024bf7f99721	261	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
bogdanm	85:024bf7f99721	262
bogdanm	85:024bf7f99721	263	}RCC_CRSSynchroInfoTypeDef;
bogdanm	85:024bf7f99721	264
bogdanm	85:024bf7f99721	265	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	266	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	267
bogdanm	85:024bf7f99721	268	/* Exported constants --------------------------------------------------------*/
bogdanm	85:024bf7f99721	269	/** @defgroup RCCEx_Exported_Constants
bogdanm	85:024bf7f99721	270	* @{
bogdanm	85:024bf7f99721	271	*/
bogdanm	85:024bf7f99721	272
bogdanm	85:024bf7f99721	273	/** @defgroup RCCEx_Periph_Clock_Selection
bogdanm	85:024bf7f99721	274	* @{
bogdanm	85:024bf7f99721	275	*/
bogdanm	85:024bf7f99721	276	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)
bogdanm	85:024bf7f99721	277	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	278	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	279	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	280
bogdanm	85:024bf7f99721	281	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
bogdanm	85:024bf7f99721	282	RCC_PERIPHCLK_RTC))
bogdanm	85:024bf7f99721	283	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 */
bogdanm	85:024bf7f99721	284
bogdanm	85:024bf7f99721	285	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	286	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	287	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	288	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	289	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	290
bogdanm	85:024bf7f99721	291	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
bogdanm	85:024bf7f99721	292	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
bogdanm	85:024bf7f99721	293	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	294
bogdanm	85:024bf7f99721	295	#if defined(STM32F071xB)
bogdanm	85:024bf7f99721	296	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	297	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	298	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	299	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	300	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	301
bogdanm	85:024bf7f99721	302	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
bogdanm	85:024bf7f99721	303	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
bogdanm	85:024bf7f99721	304	RCC_PERIPHCLK_RTC))
bogdanm	85:024bf7f99721	305	#endif /* STM32F071xB */
bogdanm	85:024bf7f99721	306
bogdanm	85:024bf7f99721	307	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
bogdanm	85:024bf7f99721	308	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	309	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	310	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	311	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	312	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	313
bogdanm	85:024bf7f99721	314	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
bogdanm	85:024bf7f99721	315	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
bogdanm	85:024bf7f99721	316	RCC_PERIPHCLK_USB))
bogdanm	85:024bf7f99721	317	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	85:024bf7f99721	318
bogdanm	85:024bf7f99721	319	#if defined(STM32F072xB)
bogdanm	85:024bf7f99721	320	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	321	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	322	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	323	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	324	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	325	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	326
bogdanm	85:024bf7f99721	327	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
bogdanm	85:024bf7f99721	328	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
bogdanm	85:024bf7f99721	329	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
bogdanm	85:024bf7f99721	330	#endif /* STM32F072xB */
bogdanm	85:024bf7f99721	331
bogdanm	85:024bf7f99721	332	#if defined(STM32F078xx)
bogdanm	85:024bf7f99721	333	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	334	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	335	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	336	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	337	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	338
bogdanm	85:024bf7f99721	339	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
bogdanm	85:024bf7f99721	340	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
bogdanm	85:024bf7f99721	341	RCC_PERIPHCLK_RTC))
bogdanm	85:024bf7f99721	342	#endif /* STM32F078xx */
bogdanm	85:024bf7f99721	343
bogdanm	85:024bf7f99721	344	/**
bogdanm	85:024bf7f99721	345	* @}
bogdanm	85:024bf7f99721	346	*/
bogdanm	85:024bf7f99721	347
bogdanm	85:024bf7f99721	348	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)
bogdanm	85:024bf7f99721	349
bogdanm	85:024bf7f99721	350	/** @defgroup RCCEx_MCO_Clock_Source
bogdanm	85:024bf7f99721	351	* @{
bogdanm	85:024bf7f99721	352	*/
bogdanm	85:024bf7f99721	353	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
bogdanm	85:024bf7f99721	354
bogdanm	85:024bf7f99721	355	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	85:024bf7f99721	356	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	85:024bf7f99721	357	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	85:024bf7f99721	358	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	85:024bf7f99721	359	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	360	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	85:024bf7f99721	361	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
bogdanm	85:024bf7f99721	362	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
bogdanm	85:024bf7f99721	363	((SOURCE) == RCC_MCOSOURCE_HSI14))
bogdanm	85:024bf7f99721	364	/**
bogdanm	85:024bf7f99721	365	* @}
bogdanm	85:024bf7f99721	366	*/
bogdanm	85:024bf7f99721	367
bogdanm	85:024bf7f99721	368	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx */
bogdanm	85:024bf7f99721	369
bogdanm	85:024bf7f99721	370	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	371
bogdanm	85:024bf7f99721	372	/** @defgroup RCCEx_MCO_Clock_Source
bogdanm	85:024bf7f99721	373	* @{
bogdanm	85:024bf7f99721	374	*/
bogdanm	85:024bf7f99721	375	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	85:024bf7f99721	376	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	85:024bf7f99721	377	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	85:024bf7f99721	378	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	85:024bf7f99721	379	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	380	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	85:024bf7f99721	381	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
bogdanm	85:024bf7f99721	382	((SOURCE) == RCC_MCOSOURCE_HSI14))
bogdanm	85:024bf7f99721	383	/**
bogdanm	85:024bf7f99721	384	* @}
bogdanm	85:024bf7f99721	385	*/
bogdanm	85:024bf7f99721	386
bogdanm	85:024bf7f99721	387	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	388
bogdanm	85:024bf7f99721	389	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	390	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	391	/** @defgroup RCCEx_MCO_Clock_Source
bogdanm	85:024bf7f99721	392	* @{
bogdanm	85:024bf7f99721	393	*/
bogdanm	85:024bf7f99721	394	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
bogdanm	85:024bf7f99721	395	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
bogdanm	85:024bf7f99721	396
bogdanm	85:024bf7f99721	397	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	85:024bf7f99721	398	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	85:024bf7f99721	399	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	85:024bf7f99721	400	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	85:024bf7f99721	401	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	402	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	85:024bf7f99721	403	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
bogdanm	85:024bf7f99721	404	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
bogdanm	85:024bf7f99721	405	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
bogdanm	85:024bf7f99721	406	((SOURCE) == RCC_MCOSOURCE_HSI48))
bogdanm	85:024bf7f99721	407	/**
bogdanm	85:024bf7f99721	408	* @}
bogdanm	85:024bf7f99721	409	*/
bogdanm	85:024bf7f99721	410
bogdanm	85:024bf7f99721	411	/** @defgroup RCCEx_Interrupt
bogdanm	85:024bf7f99721	412	* @{
bogdanm	85:024bf7f99721	413	*/
bogdanm	85:024bf7f99721	414	#define RCC_IT_HSI48 ((uint8_t)0x40)
bogdanm	85:024bf7f99721	415	/**
bogdanm	85:024bf7f99721	416	* @}
bogdanm	85:024bf7f99721	417	*/
bogdanm	85:024bf7f99721	418
bogdanm	85:024bf7f99721	419	/* Flags in the CR2 register */
bogdanm	85:024bf7f99721	420	#define RCC_CR2_HSI48RDY_BitNumber 16
bogdanm	85:024bf7f99721	421
bogdanm	85:024bf7f99721	422	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
bogdanm	85:024bf7f99721	423
bogdanm	85:024bf7f99721	424	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	425	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	426
bogdanm	85:024bf7f99721	427	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)
bogdanm	85:024bf7f99721	428
bogdanm	85:024bf7f99721	429	/** @defgroup RCCEx_USB_Clock_Source
bogdanm	85:024bf7f99721	430	* @{
bogdanm	85:024bf7f99721	431	*/
bogdanm	85:024bf7f99721	432	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
bogdanm	85:024bf7f99721	433	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
bogdanm	85:024bf7f99721	434
bogdanm	85:024bf7f99721	435	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
bogdanm	85:024bf7f99721	436	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
bogdanm	85:024bf7f99721	437	/**
bogdanm	85:024bf7f99721	438	* @}
bogdanm	85:024bf7f99721	439	*/
bogdanm	85:024bf7f99721	440
bogdanm	85:024bf7f99721	441	#endif /* STM32F042x6 \|\| STM32F072xB */
bogdanm	85:024bf7f99721	442
bogdanm	85:024bf7f99721	443	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	444
bogdanm	85:024bf7f99721	445	/** @defgroup RCCEx_USART2_Clock_Source
bogdanm	85:024bf7f99721	446	* @{
bogdanm	85:024bf7f99721	447	*/
bogdanm	85:024bf7f99721	448	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
bogdanm	85:024bf7f99721	449	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
bogdanm	85:024bf7f99721	450	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
bogdanm	85:024bf7f99721	451	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
bogdanm	85:024bf7f99721	452
bogdanm	85:024bf7f99721	453	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
bogdanm	85:024bf7f99721	454	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
bogdanm	85:024bf7f99721	455	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
bogdanm	85:024bf7f99721	456	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
bogdanm	85:024bf7f99721	457	/**
bogdanm	85:024bf7f99721	458	* @}
bogdanm	85:024bf7f99721	459	*/
bogdanm	85:024bf7f99721	460
bogdanm	85:024bf7f99721	461	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	462
bogdanm	85:024bf7f99721	463	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	464	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	465	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	466
bogdanm	85:024bf7f99721	467	/** @defgroup RCCEx_CEC_Clock_Source
bogdanm	85:024bf7f99721	468	* @{
bogdanm	85:024bf7f99721	469	*/
bogdanm	85:024bf7f99721	470	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
bogdanm	85:024bf7f99721	471	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
bogdanm	85:024bf7f99721	472
bogdanm	85:024bf7f99721	473	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	474	((SOURCE) == RCC_CECCLKSOURCE_LSE))
bogdanm	85:024bf7f99721	475	/**
bogdanm	85:024bf7f99721	476	* @}
bogdanm	85:024bf7f99721	477	*/
bogdanm	85:024bf7f99721	478
bogdanm	85:024bf7f99721	479	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	480	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	481	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	482
bogdanm	85:024bf7f99721	483	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	484	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	485	/** @addtogroup RCC_PLL_Clock_Source
bogdanm	85:024bf7f99721	486	* @{
bogdanm	85:024bf7f99721	487	*/
bogdanm	85:024bf7f99721	488	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
bogdanm	85:024bf7f99721	489	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
bogdanm	85:024bf7f99721	490
bogdanm	85:024bf7f99721	491	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	492	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
bogdanm	85:024bf7f99721	493	((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm	85:024bf7f99721	494	/**
bogdanm	85:024bf7f99721	495	* @}
bogdanm	85:024bf7f99721	496	*/
bogdanm	85:024bf7f99721	497
bogdanm	85:024bf7f99721	498	/** @addtogroup RCC_System_Clock_Source
bogdanm	85:024bf7f99721	499	* @{
bogdanm	85:024bf7f99721	500	*/
bogdanm	85:024bf7f99721	501	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
bogdanm	85:024bf7f99721	502
bogdanm	85:024bf7f99721	503	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	504	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	85:024bf7f99721	505	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
bogdanm	85:024bf7f99721	506	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
bogdanm	85:024bf7f99721	507	/**
bogdanm	85:024bf7f99721	508	* @}
bogdanm	85:024bf7f99721	509	*/
bogdanm	85:024bf7f99721	510
bogdanm	85:024bf7f99721	511	/** @addtogroup RCC_System_Clock_Source_Status
bogdanm	85:024bf7f99721	512	* @{
bogdanm	85:024bf7f99721	513	*/
bogdanm	85:024bf7f99721	514	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
bogdanm	85:024bf7f99721	515
bogdanm	85:024bf7f99721	516	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
bogdanm	85:024bf7f99721	517	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
bogdanm	85:024bf7f99721	518	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
bogdanm	85:024bf7f99721	519	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
bogdanm	85:024bf7f99721	520	/**
bogdanm	85:024bf7f99721	521	* @}
bogdanm	85:024bf7f99721	522	*/
bogdanm	85:024bf7f99721	523
bogdanm	85:024bf7f99721	524	/** @defgroup RCCEx_HSI48_Config
bogdanm	85:024bf7f99721	525	* @{
bogdanm	85:024bf7f99721	526	*/
bogdanm	85:024bf7f99721	527	#define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm	85:024bf7f99721	528	#define RCC_HSI48_ON ((uint8_t)0x01)
bogdanm	85:024bf7f99721	529
bogdanm	85:024bf7f99721	530	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
bogdanm	85:024bf7f99721	531	/**
bogdanm	85:024bf7f99721	532	* @}
bogdanm	85:024bf7f99721	533	*/
bogdanm	85:024bf7f99721	534
bogdanm	85:024bf7f99721	535	#else
bogdanm	85:024bf7f99721	536	/** @addtogroup RCC_PLL_Clock_Source
bogdanm	85:024bf7f99721	537	* @{
bogdanm	85:024bf7f99721	538	*/
bogdanm	85:024bf7f99721	539	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
bogdanm	85:024bf7f99721	540	/**
bogdanm	85:024bf7f99721	541	* @}
bogdanm	85:024bf7f99721	542	*/
bogdanm	85:024bf7f99721	543
bogdanm	85:024bf7f99721	544	/** @addtogroup RCC_PLL_Clock_Source
bogdanm	85:024bf7f99721	545	* @{
bogdanm	85:024bf7f99721	546	*/
bogdanm	85:024bf7f99721	547	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	548	((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm	85:024bf7f99721	549	/**
bogdanm	85:024bf7f99721	550	* @}
bogdanm	85:024bf7f99721	551	*/
bogdanm	85:024bf7f99721	552	/** @addtogroup RCC_System_Clock_Source
bogdanm	85:024bf7f99721	553	* @{
bogdanm	85:024bf7f99721	554	*/
bogdanm	85:024bf7f99721	555	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	556	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	85:024bf7f99721	557	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm	85:024bf7f99721	558	/**
bogdanm	85:024bf7f99721	559	* @}
bogdanm	85:024bf7f99721	560	*/
bogdanm	85:024bf7f99721	561
bogdanm	85:024bf7f99721	562	/** @addtogroup RCC_System_Clock_Source_Status
bogdanm	85:024bf7f99721	563	* @{
bogdanm	85:024bf7f99721	564	*/
bogdanm	85:024bf7f99721	565	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
bogdanm	85:024bf7f99721	566	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
bogdanm	85:024bf7f99721	567	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
bogdanm	85:024bf7f99721	568	/**
bogdanm	85:024bf7f99721	569	* @}
bogdanm	85:024bf7f99721	570	*/
bogdanm	85:024bf7f99721	571
bogdanm	85:024bf7f99721	572	/** @defgroup RCCEx_HSI48_Config
bogdanm	85:024bf7f99721	573	* @{
bogdanm	85:024bf7f99721	574	*/
bogdanm	85:024bf7f99721	575	#define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm	85:024bf7f99721	576
bogdanm	85:024bf7f99721	577	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
bogdanm	85:024bf7f99721	578	/**
bogdanm	85:024bf7f99721	579	* @}
bogdanm	85:024bf7f99721	580	*/
bogdanm	85:024bf7f99721	581
bogdanm	85:024bf7f99721	582	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	583	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	584
bogdanm	85:024bf7f99721	585
bogdanm	85:024bf7f99721	586	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	587
bogdanm	85:024bf7f99721	588	/** @defgroup RCCEx_MCOx_Clock_Prescaler
bogdanm	85:024bf7f99721	589	* @{
bogdanm	85:024bf7f99721	590	*/
bogdanm	85:024bf7f99721	591	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	592
bogdanm	85:024bf7f99721	593	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
bogdanm	85:024bf7f99721	594	/**
bogdanm	85:024bf7f99721	595	* @}
bogdanm	85:024bf7f99721	596	*/
bogdanm	85:024bf7f99721	597
bogdanm	85:024bf7f99721	598	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	599
bogdanm	85:024bf7f99721	600	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
bogdanm	85:024bf7f99721	601	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| \
bogdanm	85:024bf7f99721	602	defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	603
bogdanm	85:024bf7f99721	604	/** @defgroup RCCEx_MCOx_Clock_Prescaler
bogdanm	85:024bf7f99721	605	* @{
bogdanm	85:024bf7f99721	606	*/
bogdanm	85:024bf7f99721	607	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	608	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
bogdanm	85:024bf7f99721	609	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
bogdanm	85:024bf7f99721	610	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
bogdanm	85:024bf7f99721	611	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
bogdanm	85:024bf7f99721	612	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
bogdanm	85:024bf7f99721	613	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
bogdanm	85:024bf7f99721	614	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
bogdanm	85:024bf7f99721	615
bogdanm	85:024bf7f99721	616	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
bogdanm	85:024bf7f99721	617	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
bogdanm	85:024bf7f99721	618	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
bogdanm	85:024bf7f99721	619	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
bogdanm	85:024bf7f99721	620	/**
bogdanm	85:024bf7f99721	621	* @}
bogdanm	85:024bf7f99721	622	*/
bogdanm	85:024bf7f99721	623
bogdanm	85:024bf7f99721	624	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	625	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	626
bogdanm	85:024bf7f99721	627	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	628	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	629	/** @defgroup RCCEx_CRS_SynchroSource
bogdanm	85:024bf7f99721	630	* @{
bogdanm	85:024bf7f99721	631	*/
bogdanm	85:024bf7f99721	632	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
bogdanm	85:024bf7f99721	633	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
bogdanm	85:024bf7f99721	634	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
bogdanm	85:024bf7f99721	635
bogdanm	85:024bf7f99721	636	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
bogdanm	85:024bf7f99721	637	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\|\
bogdanm	85:024bf7f99721	638	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
bogdanm	85:024bf7f99721	639	/**
bogdanm	85:024bf7f99721	640	* @}
bogdanm	85:024bf7f99721	641	*/
bogdanm	85:024bf7f99721	642
bogdanm	85:024bf7f99721	643	/** @defgroup RCCEx_CRS_SynchroDivider
bogdanm	85:024bf7f99721	644	* @{
bogdanm	85:024bf7f99721	645	*/
bogdanm	85:024bf7f99721	646	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
bogdanm	85:024bf7f99721	647	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
bogdanm	85:024bf7f99721	648	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
bogdanm	85:024bf7f99721	649	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
bogdanm	85:024bf7f99721	650	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
bogdanm	85:024bf7f99721	651	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
bogdanm	85:024bf7f99721	652	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
bogdanm	85:024bf7f99721	653	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
bogdanm	85:024bf7f99721	654
bogdanm	85:024bf7f99721	655	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\|\
bogdanm	85:024bf7f99721	656	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
bogdanm	85:024bf7f99721	657	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
bogdanm	85:024bf7f99721	658	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
bogdanm	85:024bf7f99721	659	/**
bogdanm	85:024bf7f99721	660	* @}
bogdanm	85:024bf7f99721	661	*/
bogdanm	85:024bf7f99721	662
bogdanm	85:024bf7f99721	663	/** @defgroup RCCEx_CRS_SynchroPolarity
bogdanm	85:024bf7f99721	664	* @{
bogdanm	85:024bf7f99721	665	*/
bogdanm	85:024bf7f99721	666	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
bogdanm	85:024bf7f99721	667	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
bogdanm	85:024bf7f99721	668
bogdanm	85:024bf7f99721	669	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
bogdanm	85:024bf7f99721	670	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
bogdanm	85:024bf7f99721	671	/**
bogdanm	85:024bf7f99721	672	* @}
bogdanm	85:024bf7f99721	673	*/
bogdanm	85:024bf7f99721	674
bogdanm	85:024bf7f99721	675	/** @defgroup RCCEx_CRS_ReloadValueDefault
bogdanm	85:024bf7f99721	676	* @{
bogdanm	85:024bf7f99721	677	*/
bogdanm	85:024bf7f99721	678	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
bogdanm	85:024bf7f99721	679	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
bogdanm	85:024bf7f99721	680
bogdanm	85:024bf7f99721	681	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
bogdanm	85:024bf7f99721	682	/**
bogdanm	85:024bf7f99721	683	* @}
bogdanm	85:024bf7f99721	684	*/
bogdanm	85:024bf7f99721	685
bogdanm	85:024bf7f99721	686	/** @defgroup RCCEx_CRS_ErrorLimitDefault
bogdanm	85:024bf7f99721	687	* @{
bogdanm	85:024bf7f99721	688	*/
bogdanm	85:024bf7f99721	689	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
bogdanm	85:024bf7f99721	690
bogdanm	85:024bf7f99721	691	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
bogdanm	85:024bf7f99721	692	/**
bogdanm	85:024bf7f99721	693	* @}
bogdanm	85:024bf7f99721	694	*/
bogdanm	85:024bf7f99721	695
bogdanm	85:024bf7f99721	696	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault
bogdanm	85:024bf7f99721	697	* @{
bogdanm	85:024bf7f99721	698	*/
bogdanm	85:024bf7f99721	699	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
bogdanm	85:024bf7f99721	700	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
bogdanm	85:024bf7f99721	701	corresponds to a higher output frequency */
bogdanm	85:024bf7f99721	702
bogdanm	85:024bf7f99721	703	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
bogdanm	85:024bf7f99721	704	/**
bogdanm	85:024bf7f99721	705	* @}
bogdanm	85:024bf7f99721	706	*/
bogdanm	85:024bf7f99721	707
bogdanm	85:024bf7f99721	708	/** @defgroup RCCEx_CRS_FreqErrorDirection
bogdanm	85:024bf7f99721	709	* @{
bogdanm	85:024bf7f99721	710	*/
bogdanm	85:024bf7f99721	711	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
bogdanm	85:024bf7f99721	712	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
bogdanm	85:024bf7f99721	713
bogdanm	85:024bf7f99721	714	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
bogdanm	85:024bf7f99721	715	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
bogdanm	85:024bf7f99721	716	/**
bogdanm	85:024bf7f99721	717	* @}
bogdanm	85:024bf7f99721	718	*/
bogdanm	85:024bf7f99721	719
bogdanm	85:024bf7f99721	720	/** @defgroup RCCEx_CRS_Interrupt_Sources
bogdanm	85:024bf7f99721	721	* @{
bogdanm	85:024bf7f99721	722	*/
bogdanm	85:024bf7f99721	723	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
bogdanm	85:024bf7f99721	724	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
bogdanm	85:024bf7f99721	725	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
bogdanm	85:024bf7f99721	726	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
bogdanm	85:024bf7f99721	727	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	85:024bf7f99721	728	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	85:024bf7f99721	729	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	85:024bf7f99721	730
bogdanm	85:024bf7f99721	731	/**
bogdanm	85:024bf7f99721	732	* @}
bogdanm	85:024bf7f99721	733	*/
bogdanm	85:024bf7f99721	734
bogdanm	85:024bf7f99721	735	/** @defgroup RCCEx_CRS_Flags
bogdanm	85:024bf7f99721	736	* @{
bogdanm	85:024bf7f99721	737	*/
bogdanm	85:024bf7f99721	738	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
bogdanm	85:024bf7f99721	739	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
bogdanm	85:024bf7f99721	740	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
bogdanm	85:024bf7f99721	741	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
bogdanm	85:024bf7f99721	742	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	85:024bf7f99721	743	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	85:024bf7f99721	744	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	85:024bf7f99721	745
bogdanm	85:024bf7f99721	746	/**
bogdanm	85:024bf7f99721	747	* @}
bogdanm	85:024bf7f99721	748	*/
bogdanm	85:024bf7f99721	749
bogdanm	85:024bf7f99721	750	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	751	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	752
bogdanm	85:024bf7f99721	753	/**
bogdanm	85:024bf7f99721	754	* @}
bogdanm	85:024bf7f99721	755	*/
bogdanm	85:024bf7f99721	756
bogdanm	85:024bf7f99721	757	/* Exported macros -----------------------------------------------------------*/
bogdanm	85:024bf7f99721	758	/** @defgroup RCCEx_Exported_Macros
bogdanm	85:024bf7f99721	759	* @{
bogdanm	85:024bf7f99721	760	*/
bogdanm	85:024bf7f99721	761
bogdanm	85:024bf7f99721	762	/** @brief Enable or disable the AHB peripheral clock.
bogdanm	85:024bf7f99721	763	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	764	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	765	* using it.
bogdanm	85:024bf7f99721	766	*/
bogdanm	85:024bf7f99721	767	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
bogdanm	85:024bf7f99721	768	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	769	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	770
bogdanm	85:024bf7f99721	771	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
bogdanm	85:024bf7f99721	772
bogdanm	85:024bf7f99721	773	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
bogdanm	85:024bf7f99721	774
bogdanm	85:024bf7f99721	775	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	776	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	777	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	778
bogdanm	85:024bf7f99721	779	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	780
bogdanm	85:024bf7f99721	781	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
bogdanm	85:024bf7f99721	782
bogdanm	85:024bf7f99721	783	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm	85:024bf7f99721	784
bogdanm	85:024bf7f99721	785	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	786
bogdanm	85:024bf7f99721	787	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	788	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	789	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	790
bogdanm	85:024bf7f99721	791	#define __TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
bogdanm	85:024bf7f99721	792
bogdanm	85:024bf7f99721	793	#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
bogdanm	85:024bf7f99721	794
bogdanm	85:024bf7f99721	795	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	796	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	797	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	798
bogdanm	85:024bf7f99721	799	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	85:024bf7f99721	800	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	801	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	802	* using it.
bogdanm	85:024bf7f99721	803	*/
bogdanm	85:024bf7f99721	804	#if defined(STM32F030x8) \|\| \
bogdanm	85:024bf7f99721	805	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	806	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	807	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	808
bogdanm	85:024bf7f99721	809	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
bogdanm	85:024bf7f99721	810	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
bogdanm	85:024bf7f99721	811
bogdanm	85:024bf7f99721	812	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	85:024bf7f99721	813	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	85:024bf7f99721	814
bogdanm	85:024bf7f99721	815	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	816	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	817	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	818
bogdanm	85:024bf7f99721	819	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
bogdanm	85:024bf7f99721	820	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	821	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	822	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	823
bogdanm	85:024bf7f99721	824	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
bogdanm	85:024bf7f99721	825
bogdanm	85:024bf7f99721	826	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	85:024bf7f99721	827
bogdanm	85:024bf7f99721	828	#endif /* STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	829	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	830
bogdanm	85:024bf7f99721	831	#if defined(STM32F030x8) \|\| \
bogdanm	85:024bf7f99721	832	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	833	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	834
bogdanm	85:024bf7f99721	835	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
bogdanm	85:024bf7f99721	836	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
bogdanm	85:024bf7f99721	837
bogdanm	85:024bf7f99721	838	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm	85:024bf7f99721	839	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	85:024bf7f99721	840
bogdanm	85:024bf7f99721	841	#endif /* STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	842	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	843	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	844
bogdanm	85:024bf7f99721	845	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	846	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	847
bogdanm	85:024bf7f99721	848	#define __DAC1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
bogdanm	85:024bf7f99721	849
bogdanm	85:024bf7f99721	850	#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	85:024bf7f99721	851
bogdanm	85:024bf7f99721	852	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	853	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	854
bogdanm	85:024bf7f99721	855	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	856	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	857	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	858
bogdanm	85:024bf7f99721	859	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
bogdanm	85:024bf7f99721	860
bogdanm	85:024bf7f99721	861	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm	85:024bf7f99721	862
bogdanm	85:024bf7f99721	863	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	864	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	865	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	866
bogdanm	85:024bf7f99721	867	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	868
bogdanm	85:024bf7f99721	869	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
bogdanm	85:024bf7f99721	870	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
bogdanm	85:024bf7f99721	871	#define __USART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART4EN))
bogdanm	85:024bf7f99721	872
bogdanm	85:024bf7f99721	873	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm	85:024bf7f99721	874	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm	85:024bf7f99721	875	#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
bogdanm	85:024bf7f99721	876
bogdanm	85:024bf7f99721	877	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	878
bogdanm	85:024bf7f99721	879	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)
bogdanm	85:024bf7f99721	880
bogdanm	85:024bf7f99721	881	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
bogdanm	85:024bf7f99721	882
bogdanm	85:024bf7f99721	883	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
bogdanm	85:024bf7f99721	884
bogdanm	85:024bf7f99721	885	#endif /* STM32F042x6 \|\| STM32F072xB */
bogdanm	85:024bf7f99721	886
bogdanm	85:024bf7f99721	887	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)
bogdanm	85:024bf7f99721	888
bogdanm	85:024bf7f99721	889	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
bogdanm	85:024bf7f99721	890	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
bogdanm	85:024bf7f99721	891
bogdanm	85:024bf7f99721	892	#endif /* STM32F042x6 \|\| STM32F072xB */
bogdanm	85:024bf7f99721	893
bogdanm	85:024bf7f99721	894	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	895	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	896
bogdanm	85:024bf7f99721	897	#define __CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
bogdanm	85:024bf7f99721	898
bogdanm	85:024bf7f99721	899	#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
bogdanm	85:024bf7f99721	900
bogdanm	85:024bf7f99721	901	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	902	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	903
bogdanm	85:024bf7f99721	904	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	85:024bf7f99721	905	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	906	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	907	* using it.
bogdanm	85:024bf7f99721	908	*/
bogdanm	85:024bf7f99721	909	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	910	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	911	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	912
bogdanm	85:024bf7f99721	913	#define __TIM15_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM15EN))
bogdanm	85:024bf7f99721	914
bogdanm	85:024bf7f99721	915	#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
bogdanm	85:024bf7f99721	916
bogdanm	85:024bf7f99721	917	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	918	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	919	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	920
bogdanm	85:024bf7f99721	921	/** @brief Force or release AHB peripheral reset.
bogdanm	85:024bf7f99721	922	*/
bogdanm	85:024bf7f99721	923	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
bogdanm	85:024bf7f99721	924	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	925	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	926
bogdanm	85:024bf7f99721	927	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
bogdanm	85:024bf7f99721	928
bogdanm	85:024bf7f99721	929	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
bogdanm	85:024bf7f99721	930
bogdanm	85:024bf7f99721	931	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	932	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	933	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	934
bogdanm	85:024bf7f99721	935	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	936
bogdanm	85:024bf7f99721	937	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
bogdanm	85:024bf7f99721	938
bogdanm	85:024bf7f99721	939	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm	85:024bf7f99721	940
bogdanm	85:024bf7f99721	941	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	942
bogdanm	85:024bf7f99721	943	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	944	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	945	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	946
bogdanm	85:024bf7f99721	947	#define __TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
bogdanm	85:024bf7f99721	948
bogdanm	85:024bf7f99721	949	#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
bogdanm	85:024bf7f99721	950
bogdanm	85:024bf7f99721	951	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	952	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	953	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	954
bogdanm	85:024bf7f99721	955	/** @brief Force or release APB1 peripheral reset.
bogdanm	85:024bf7f99721	956	*/
bogdanm	85:024bf7f99721	957	#if defined(STM32F030x8) \|\| \
bogdanm	85:024bf7f99721	958	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	959	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	960	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	961
bogdanm	85:024bf7f99721	962	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	85:024bf7f99721	963	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	85:024bf7f99721	964
bogdanm	85:024bf7f99721	965	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm	85:024bf7f99721	966	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	85:024bf7f99721	967
bogdanm	85:024bf7f99721	968	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	969	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	970	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	971
bogdanm	85:024bf7f99721	972	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
bogdanm	85:024bf7f99721	973	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	974	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	975	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	976
bogdanm	85:024bf7f99721	977	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	85:024bf7f99721	978
bogdanm	85:024bf7f99721	979	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	85:024bf7f99721	980
bogdanm	85:024bf7f99721	981	#endif /* STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	982	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	983
bogdanm	85:024bf7f99721	984	#if defined(STM32F030x8) \|\| \
bogdanm	85:024bf7f99721	985	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	986	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	987
bogdanm	85:024bf7f99721	988	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	85:024bf7f99721	989	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	85:024bf7f99721	990
bogdanm	85:024bf7f99721	991	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm	85:024bf7f99721	992	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	85:024bf7f99721	993
bogdanm	85:024bf7f99721	994	#endif /* STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	995	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	996	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	997
bogdanm	85:024bf7f99721	998	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	999	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	1000
bogdanm	85:024bf7f99721	1001	#define __DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	85:024bf7f99721	1002
bogdanm	85:024bf7f99721	1003	#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	85:024bf7f99721	1004
bogdanm	85:024bf7f99721	1005	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	1006	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	1007
bogdanm	85:024bf7f99721	1008	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1009	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	1010	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	1011
bogdanm	85:024bf7f99721	1012	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
bogdanm	85:024bf7f99721	1013
bogdanm	85:024bf7f99721	1014	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm	85:024bf7f99721	1015
bogdanm	85:024bf7f99721	1016	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	1017	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	1018	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	1019
bogdanm	85:024bf7f99721	1020	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	1021
bogdanm	85:024bf7f99721	1022	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	85:024bf7f99721	1023	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
bogdanm	85:024bf7f99721	1024	#define __USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
bogdanm	85:024bf7f99721	1025
bogdanm	85:024bf7f99721	1026	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm	85:024bf7f99721	1027	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm	85:024bf7f99721	1028	#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
bogdanm	85:024bf7f99721	1029
bogdanm	85:024bf7f99721	1030	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	1031
bogdanm	85:024bf7f99721	1032	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)
bogdanm	85:024bf7f99721	1033
bogdanm	85:024bf7f99721	1034	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
bogdanm	85:024bf7f99721	1035
bogdanm	85:024bf7f99721	1036	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
bogdanm	85:024bf7f99721	1037
bogdanm	85:024bf7f99721	1038	#endif /* STM32F042x6 \|\| STM32F072xB */
bogdanm	85:024bf7f99721	1039
bogdanm	85:024bf7f99721	1040	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)
bogdanm	85:024bf7f99721	1041
bogdanm	85:024bf7f99721	1042	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
bogdanm	85:024bf7f99721	1043
bogdanm	85:024bf7f99721	1044	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
bogdanm	85:024bf7f99721	1045
bogdanm	85:024bf7f99721	1046	#endif /* STM32F042x6 \|\| STM32F072xB */
bogdanm	85:024bf7f99721	1047
bogdanm	85:024bf7f99721	1048	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1049	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	1050
bogdanm	85:024bf7f99721	1051	#define __CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
bogdanm	85:024bf7f99721	1052
bogdanm	85:024bf7f99721	1053	#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
bogdanm	85:024bf7f99721	1054
bogdanm	85:024bf7f99721	1055	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	1056	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	1057
bogdanm	85:024bf7f99721	1058
bogdanm	85:024bf7f99721	1059	/** @brief Force or release APB2 peripheral reset.
bogdanm	85:024bf7f99721	1060	*/
bogdanm	85:024bf7f99721	1061	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1062	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	1063	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	1064
bogdanm	85:024bf7f99721	1065	#define __TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
bogdanm	85:024bf7f99721	1066
bogdanm	85:024bf7f99721	1067	#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
bogdanm	85:024bf7f99721	1068
bogdanm	85:024bf7f99721	1069	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1070	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	1071	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	1072
bogdanm	85:024bf7f99721	1073	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1074	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	1075
bogdanm	85:024bf7f99721	1076	/** @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
bogdanm	85:024bf7f99721	1077	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	85:024bf7f99721	1078	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
bogdanm	85:024bf7f99721	1079	* you have to select another source of the system clock then stop the HSI14.
bogdanm	85:024bf7f99721	1080	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
bogdanm	85:024bf7f99721	1081	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
bogdanm	85:024bf7f99721	1082	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
bogdanm	85:024bf7f99721	1083	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
bogdanm	85:024bf7f99721	1084	* clock cycles.
bogdanm	85:024bf7f99721	1085	*/
bogdanm	85:024bf7f99721	1086	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm	85:024bf7f99721	1087	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm	85:024bf7f99721	1088
bogdanm	85:024bf7f99721	1089	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm	85:024bf7f99721	1090	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1091	* @arg RCC_HSI48_ON: HSI48 enabled
bogdanm	85:024bf7f99721	1092	* @arg RCC_HSI48_OFF: HSI48 disabled
bogdanm	85:024bf7f99721	1093	*/
bogdanm	85:024bf7f99721	1094	#define __HAL_RCC_GET_HSI48_STATE() \
bogdanm	85:024bf7f99721	1095	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
bogdanm	85:024bf7f99721	1096
bogdanm	85:024bf7f99721	1097	#else
bogdanm	85:024bf7f99721	1098
bogdanm	85:024bf7f99721	1099	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm	85:024bf7f99721	1100	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1101	* @arg RCC_HSI_OFF: HSI48 disabled
bogdanm	85:024bf7f99721	1102	*/
bogdanm	85:024bf7f99721	1103	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
bogdanm	85:024bf7f99721	1104
bogdanm	85:024bf7f99721	1105	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	1106	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	1107
bogdanm	85:024bf7f99721	1108	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)
bogdanm	85:024bf7f99721	1109
bogdanm	85:024bf7f99721	1110	/** @brief Macro to configure the USB clock (USBCLK).
bogdanm	85:024bf7f99721	1111	* @param __USBCLKSource__: specifies the USB clock source.
bogdanm	85:024bf7f99721	1112	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1113	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm	85:024bf7f99721	1114	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	85:024bf7f99721	1115	*/
bogdanm	85:024bf7f99721	1116	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm	85:024bf7f99721	1117	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
bogdanm	85:024bf7f99721	1118
bogdanm	85:024bf7f99721	1119	/** @brief Macro to get the USB clock source.
bogdanm	85:024bf7f99721	1120	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1121	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm	85:024bf7f99721	1122	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	85:024bf7f99721	1123	*/
bogdanm	85:024bf7f99721	1124	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
bogdanm	85:024bf7f99721	1125
bogdanm	85:024bf7f99721	1126	#endif /* STM32F042x6 \|\| STM32F072xB */
bogdanm	85:024bf7f99721	1127
bogdanm	85:024bf7f99721	1128	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1129	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	85:024bf7f99721	1130	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	1131
bogdanm	85:024bf7f99721	1132	/** @brief Macro to configure the CEC clock.
bogdanm	85:024bf7f99721	1133	* @param __CECCLKSource__: specifies the CEC clock source.
bogdanm	85:024bf7f99721	1134	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1135	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	85:024bf7f99721	1136	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	85:024bf7f99721	1137	*/
bogdanm	85:024bf7f99721	1138	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
bogdanm	85:024bf7f99721	1139	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
bogdanm	85:024bf7f99721	1140
bogdanm	85:024bf7f99721	1141	/** @brief Macro to get the HDMI CEC clock source.
bogdanm	85:024bf7f99721	1142	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1143	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	85:024bf7f99721	1144	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	85:024bf7f99721	1145	*/
bogdanm	85:024bf7f99721	1146	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
bogdanm	85:024bf7f99721	1147
bogdanm	85:024bf7f99721	1148	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	1149	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	85:024bf7f99721	1150	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	1151
bogdanm	85:024bf7f99721	1152	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
bogdanm	85:024bf7f99721	1153	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| \
bogdanm	85:024bf7f99721	1154	defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	1155
bogdanm	85:024bf7f99721	1156	/** @brief Macro to configure the MCO clock.
bogdanm	85:024bf7f99721	1157	* @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm	85:024bf7f99721	1158	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1159	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm	85:024bf7f99721	1160	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm	85:024bf7f99721	1161	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm	85:024bf7f99721	1162	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm	85:024bf7f99721	1163	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
bogdanm	85:024bf7f99721	1164	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm	85:024bf7f99721	1165	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm	85:024bf7f99721	1166	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm	85:024bf7f99721	1167	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm	85:024bf7f99721	1168	* @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm	85:024bf7f99721	1169	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1170	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
bogdanm	85:024bf7f99721	1171	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
bogdanm	85:024bf7f99721	1172	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
bogdanm	85:024bf7f99721	1173	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
bogdanm	85:024bf7f99721	1174	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
bogdanm	85:024bf7f99721	1175	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
bogdanm	85:024bf7f99721	1176	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
bogdanm	85:024bf7f99721	1177	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
bogdanm	85:024bf7f99721	1178	*/
bogdanm	85:024bf7f99721	1179	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm	85:024bf7f99721	1180	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
bogdanm	85:024bf7f99721	1181	#else
bogdanm	85:024bf7f99721	1182
bogdanm	85:024bf7f99721	1183	/** @brief Macro to configure the MCO clock.
bogdanm	85:024bf7f99721	1184	* @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm	85:024bf7f99721	1185	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1186	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm	85:024bf7f99721	1187	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm	85:024bf7f99721	1188	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm	85:024bf7f99721	1189	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm	85:024bf7f99721	1190	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm	85:024bf7f99721	1191	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm	85:024bf7f99721	1192	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm	85:024bf7f99721	1193	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm	85:024bf7f99721	1194	* @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm	85:024bf7f99721	1195	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1196	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
bogdanm	85:024bf7f99721	1197	*/
bogdanm	85:024bf7f99721	1198	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm	85:024bf7f99721	1199	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
bogdanm	85:024bf7f99721	1200
bogdanm	85:024bf7f99721	1201	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| */
bogdanm	85:024bf7f99721	1202	/* STM32F042x6 \|\| STM32F071xB \|\| */
bogdanm	85:024bf7f99721	1203	/* STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	1204
bogdanm	85:024bf7f99721	1205	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1206	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	1207	/* Interrupt & Flag management */
bogdanm	85:024bf7f99721	1208
bogdanm	85:024bf7f99721	1209	/**
bogdanm	85:024bf7f99721	1210	* @brief Enables the specified CRS interrupts.
bogdanm	85:024bf7f99721	1211	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
bogdanm	85:024bf7f99721	1212	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	1213	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	1214	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	1215	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	1216	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	1217	* @retval None
bogdanm	85:024bf7f99721	1218	*/
bogdanm	85:024bf7f99721	1219	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
bogdanm	85:024bf7f99721	1220
bogdanm	85:024bf7f99721	1221	/**
bogdanm	85:024bf7f99721	1222	* @brief Disables the specified CRS interrupts.
bogdanm	85:024bf7f99721	1223	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
bogdanm	85:024bf7f99721	1224	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	1225	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	1226	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	1227	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	1228	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	1229	* @retval None
bogdanm	85:024bf7f99721	1230	*/
bogdanm	85:024bf7f99721	1231	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
bogdanm	85:024bf7f99721	1232
bogdanm	85:024bf7f99721	1233	/** @brief Check the CRS's interrupt has occurred or not.
bogdanm	85:024bf7f99721	1234	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
bogdanm	85:024bf7f99721	1235	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1236	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	1237	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	1238	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	1239	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	1240	* @retval The new state of __INTERRUPT__ (SET or RESET).
bogdanm	85:024bf7f99721	1241	*/
bogdanm	85:024bf7f99721	1242	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
bogdanm	85:024bf7f99721	1243
bogdanm	85:024bf7f99721	1244	/** @brief Clear the CRS's interrupt pending bits
bogdanm	85:024bf7f99721	1245	* bits to clear the selected interrupt pending bits.
bogdanm	85:024bf7f99721	1246	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	85:024bf7f99721	1247	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	1248	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	1249	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	1250	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	1251	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	1252	* @arg RCC_CRS_IT_TRIMOVF
bogdanm	85:024bf7f99721	1253	* @arg RCC_CRS_IT_SYNCERR
bogdanm	85:024bf7f99721	1254	* @arg RCC_CRS_IT_SYNCMISS
bogdanm	85:024bf7f99721	1255	*/
bogdanm	85:024bf7f99721	1256	/* CRS IT Error Mask */
bogdanm	85:024bf7f99721	1257	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
bogdanm	85:024bf7f99721	1258
bogdanm	85:024bf7f99721	1259	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	85:024bf7f99721	1260	(CRS->ICR \|= (__INTERRUPT__)))
bogdanm	85:024bf7f99721	1261
bogdanm	85:024bf7f99721	1262	/**
bogdanm	85:024bf7f99721	1263	* @brief Checks whether the specified CRS flag is set or not.
bogdanm	85:024bf7f99721	1264	* @param _FLAG_: specifies the flag to check.
bogdanm	85:024bf7f99721	1265	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1266	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	85:024bf7f99721	1267	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	85:024bf7f99721	1268	* @arg RCC_CRS_FLAG_ERR
bogdanm	85:024bf7f99721	1269	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	85:024bf7f99721	1270	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	85:024bf7f99721	1271	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	85:024bf7f99721	1272	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	85:024bf7f99721	1273	* @retval The new state of _FLAG_ (TRUE or FALSE).
bogdanm	85:024bf7f99721	1274	*/
bogdanm	85:024bf7f99721	1275	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
bogdanm	85:024bf7f99721	1276
bogdanm	85:024bf7f99721	1277	/**
bogdanm	85:024bf7f99721	1278	* @brief Clears the CRS specified FLAG.
bogdanm	85:024bf7f99721	1279	* @param _FLAG_: specifies the flag to clear.
bogdanm	85:024bf7f99721	1280	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1281	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	85:024bf7f99721	1282	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	85:024bf7f99721	1283	* @arg RCC_CRS_FLAG_ERR
bogdanm	85:024bf7f99721	1284	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	85:024bf7f99721	1285	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	85:024bf7f99721	1286	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	85:024bf7f99721	1287	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	85:024bf7f99721	1288	* @retval None
bogdanm	85:024bf7f99721	1289	*/
bogdanm	85:024bf7f99721	1290
bogdanm	85:024bf7f99721	1291	/* CRS Flag Error Mask */
bogdanm	85:024bf7f99721	1292	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
bogdanm	85:024bf7f99721	1293
bogdanm	85:024bf7f99721	1294	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	85:024bf7f99721	1295	(CRS->ICR \|= (__FLAG__)))
bogdanm	85:024bf7f99721	1296
bogdanm	85:024bf7f99721	1297
bogdanm	85:024bf7f99721	1298	/**
bogdanm	85:024bf7f99721	1299	* @brief Enables the oscillator clock for frequency error counter.
bogdanm	85:024bf7f99721	1300	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	85:024bf7f99721	1301	* @param None
bogdanm	85:024bf7f99721	1302	* @retval None
bogdanm	85:024bf7f99721	1303	*/
bogdanm	85:024bf7f99721	1304	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
bogdanm	85:024bf7f99721	1305
bogdanm	85:024bf7f99721	1306	/**
bogdanm	85:024bf7f99721	1307	* @brief Disables the oscillator clock for frequency error counter.
bogdanm	85:024bf7f99721	1308	* @param None
bogdanm	85:024bf7f99721	1309	* @retval None
bogdanm	85:024bf7f99721	1310	*/
bogdanm	85:024bf7f99721	1311	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
bogdanm	85:024bf7f99721	1312
bogdanm	85:024bf7f99721	1313	/**
bogdanm	85:024bf7f99721	1314	* @brief Enables the automatic hardware adjustement of TRIM bits.
bogdanm	85:024bf7f99721	1315	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	85:024bf7f99721	1316	* @param None
bogdanm	85:024bf7f99721	1317	* @retval None
bogdanm	85:024bf7f99721	1318	*/
bogdanm	85:024bf7f99721	1319	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
bogdanm	85:024bf7f99721	1320
bogdanm	85:024bf7f99721	1321	/**
bogdanm	85:024bf7f99721	1322	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
bogdanm	85:024bf7f99721	1323	* @param None
bogdanm	85:024bf7f99721	1324	* @retval None
bogdanm	85:024bf7f99721	1325	*/
bogdanm	85:024bf7f99721	1326	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
bogdanm	85:024bf7f99721	1327
bogdanm	85:024bf7f99721	1328	/**
bogdanm	85:024bf7f99721	1329	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
bogdanm	85:024bf7f99721	1330	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
bogdanm	85:024bf7f99721	1331	* of the synchronization source after prescaling. It is then decreased by one in order to
bogdanm	85:024bf7f99721	1332	* reach the expected synchronization on the zero value. The formula is the following:
bogdanm	85:024bf7f99721	1333	* RELOAD = (fTARGET / fSYNC) -1
bogdanm	85:024bf7f99721	1334	* @param _FTARGET_ Target frequency (value in Hz)
bogdanm	85:024bf7f99721	1335	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
bogdanm	85:024bf7f99721	1336	* @retval None
bogdanm	85:024bf7f99721	1337	*/
bogdanm	85:024bf7f99721	1338	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
bogdanm	85:024bf7f99721	1339
bogdanm	85:024bf7f99721	1340	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	1341	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	1342
bogdanm	85:024bf7f99721	1343	/**
bogdanm	85:024bf7f99721	1344	* @}
bogdanm	85:024bf7f99721	1345	*/
bogdanm	85:024bf7f99721	1346
bogdanm	85:024bf7f99721	1347	/* Exported functions --------------------------------------------------------*/
bogdanm	85:024bf7f99721	1348	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	85:024bf7f99721	1349	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	85:024bf7f99721	1350
bogdanm	85:024bf7f99721	1351	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1352	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	1353	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
bogdanm	85:024bf7f99721	1354	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
bogdanm	85:024bf7f99721	1355	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
bogdanm	85:024bf7f99721	1356	RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
bogdanm	85:024bf7f99721	1357	#endif /* STM32F042x6 \|\| */
bogdanm	85:024bf7f99721	1358	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	1359
bogdanm	85:024bf7f99721	1360
bogdanm	85:024bf7f99721	1361	/**
bogdanm	85:024bf7f99721	1362	* @}
bogdanm	85:024bf7f99721	1363	*/
bogdanm	85:024bf7f99721	1364
bogdanm	85:024bf7f99721	1365	/**
bogdanm	85:024bf7f99721	1366	* @}
bogdanm	85:024bf7f99721	1367	*/
bogdanm	85:024bf7f99721	1368
bogdanm	85:024bf7f99721	1369	#ifdef __cplusplus
bogdanm	85:024bf7f99721	1370	}
bogdanm	85:024bf7f99721	1371	#endif
bogdanm	85:024bf7f99721	1372
bogdanm	85:024bf7f99721	1373	#endif /* __STM32F0xx_HAL_RCC_EX_H */
bogdanm	85:024bf7f99721	1374
bogdanm	85:024bf7f99721	1375	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	31 Mar 2015
Imports:	13
Forks:	0
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TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@85:024bf7f99721, 2014-06-11 (annotated)

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