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mbed(SerialHalfDuplex入り)

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TARGET_KL43Z/MKL43Z4.h@98:01a414ca7d6d, 2015-04-08 (annotated)

Committer:
yusuke_kyo
Date:
Wed Apr 08 08:04:18 2015 +0000
Revision:
98:01a414ca7d6d
Parent:
90:cb3d968589d8 
remove SerialHalfDuplex.h

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /*
Kojto 90:cb3d968589d8 2 ** ###################################################################
Kojto 90:cb3d968589d8 3 ** Processors: MKL43Z256VLH4
Kojto 90:cb3d968589d8 4 ** MKL43Z128VLH4
Kojto 90:cb3d968589d8 5 ** MKL43Z64VLH4
Kojto 90:cb3d968589d8 6 ** MKL43Z256VMP4
Kojto 90:cb3d968589d8 7 ** MKL43Z128VMP4
Kojto 90:cb3d968589d8 8 ** MKL43Z64VMP4
Kojto 90:cb3d968589d8 9 **
Kojto 90:cb3d968589d8 10 ** Compilers: Keil ARM C/C++ Compiler
Kojto 90:cb3d968589d8 11 ** Freescale C/C++ for Embedded ARM
Kojto 90:cb3d968589d8 12 ** GNU C Compiler
Kojto 90:cb3d968589d8 13 ** GNU C Compiler - CodeSourcery Sourcery G++
Kojto 90:cb3d968589d8 14 ** IAR ANSI C/C++ Compiler for ARM
Kojto 90:cb3d968589d8 15 **
Kojto 90:cb3d968589d8 16 ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
Kojto 90:cb3d968589d8 17 ** Version: rev. 1.5, 2014-09-05
Kojto 90:cb3d968589d8 18 ** Build: b140905
Kojto 90:cb3d968589d8 19 **
Kojto 90:cb3d968589d8 20 ** Abstract:
Kojto 90:cb3d968589d8 21 ** CMSIS Peripheral Access Layer for MKL43Z4
Kojto 90:cb3d968589d8 22 **
Kojto 90:cb3d968589d8 23 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
Kojto 90:cb3d968589d8 24 ** All rights reserved.
Kojto 90:cb3d968589d8 25 **
Kojto 90:cb3d968589d8 26 ** Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 27 ** are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 28 **
Kojto 90:cb3d968589d8 29 ** o Redistributions of source code must retain the above copyright notice, this list
Kojto 90:cb3d968589d8 30 ** of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 31 **
Kojto 90:cb3d968589d8 32 ** o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 90:cb3d968589d8 33 ** list of conditions and the following disclaimer in the documentation and/or
Kojto 90:cb3d968589d8 34 ** other materials provided with the distribution.
Kojto 90:cb3d968589d8 35 **
Kojto 90:cb3d968589d8 36 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 90:cb3d968589d8 37 ** contributors may be used to endorse or promote products derived from this
Kojto 90:cb3d968589d8 38 ** software without specific prior written permission.
Kojto 90:cb3d968589d8 39 **
Kojto 90:cb3d968589d8 40 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 90:cb3d968589d8 41 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 90:cb3d968589d8 42 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 43 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 90:cb3d968589d8 44 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 90:cb3d968589d8 45 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 90:cb3d968589d8 46 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 90:cb3d968589d8 47 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 90:cb3d968589d8 48 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 90:cb3d968589d8 49 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 50 **
Kojto 90:cb3d968589d8 51 ** http: www.freescale.com
Kojto 90:cb3d968589d8 52 ** mail: support@freescale.com
Kojto 90:cb3d968589d8 53 **
Kojto 90:cb3d968589d8 54 ** Revisions:
Kojto 90:cb3d968589d8 55 ** - rev. 1.0 (2014-03-27)
Kojto 90:cb3d968589d8 56 ** Initial version.
Kojto 90:cb3d968589d8 57 ** - rev. 1.1 (2014-05-26)
Kojto 90:cb3d968589d8 58 ** I2S registers TCR2/RCR2 and others were changed.
Kojto 90:cb3d968589d8 59 ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
Kojto 90:cb3d968589d8 60 ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
Kojto 90:cb3d968589d8 61 ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
Kojto 90:cb3d968589d8 62 ** Clock configuration for high range external oscillator has been added.
Kojto 90:cb3d968589d8 63 ** RFSYS module access has been added.
Kojto 90:cb3d968589d8 64 ** - rev. 1.2 (2014-07-10)
Kojto 90:cb3d968589d8 65 ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
Kojto 90:cb3d968589d8 66 ** UART0 - UART0 module renamed to UART2.
Kojto 90:cb3d968589d8 67 ** I2S - removed MDR register.
Kojto 90:cb3d968589d8 68 ** - rev. 1.3 (2014-08-21)
Kojto 90:cb3d968589d8 69 ** UART2 - Removed ED register.
Kojto 90:cb3d968589d8 70 ** UART2 - Removed MODEM register.
Kojto 90:cb3d968589d8 71 ** UART2 - Removed IR register.
Kojto 90:cb3d968589d8 72 ** UART2 - Removed PFIFO register.
Kojto 90:cb3d968589d8 73 ** UART2 - Removed CFIFO register.
Kojto 90:cb3d968589d8 74 ** UART2 - Removed SFIFO register.
Kojto 90:cb3d968589d8 75 ** UART2 - Removed TWFIFO register.
Kojto 90:cb3d968589d8 76 ** UART2 - Removed TCFIFO register.
Kojto 90:cb3d968589d8 77 ** UART2 - Removed RWFIFO register.
Kojto 90:cb3d968589d8 78 ** UART2 - Removed RCFIFO register.
Kojto 90:cb3d968589d8 79 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
Kojto 90:cb3d968589d8 80 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
Kojto 90:cb3d968589d8 81 ** SIM - Removed bitfield DIEID in SDID register.
Kojto 90:cb3d968589d8 82 ** - rev. 1.4 (2014-09-01)
Kojto 90:cb3d968589d8 83 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
Kojto 90:cb3d968589d8 84 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
Kojto 90:cb3d968589d8 85 ** - rev. 1.5 (2014-09-05)
Kojto 90:cb3d968589d8 86 ** USB - USBEN bitfield of the USB0_CTL renamed to USBENSOFEN.
Kojto 90:cb3d968589d8 87 **
Kojto 90:cb3d968589d8 88 ** ###################################################################
Kojto 90:cb3d968589d8 89 */
Kojto 90:cb3d968589d8 90
Kojto 90:cb3d968589d8 91 /*!
Kojto 90:cb3d968589d8 92 * @file MKL43Z4.h
Kojto 90:cb3d968589d8 93 * @version 1.5
Kojto 90:cb3d968589d8 94 * @date 2014-09-05
Kojto 90:cb3d968589d8 95 * @brief CMSIS Peripheral Access Layer for MKL43Z4
Kojto 90:cb3d968589d8 96 *
Kojto 90:cb3d968589d8 97 * CMSIS Peripheral Access Layer for MKL43Z4
Kojto 90:cb3d968589d8 98 */
Kojto 90:cb3d968589d8 99
Kojto 90:cb3d968589d8 100
Kojto 90:cb3d968589d8 101 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 102 -- MCU activation
Kojto 90:cb3d968589d8 103 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 104
Kojto 90:cb3d968589d8 105 /* Prevention from multiple including the same memory map */
Kojto 90:cb3d968589d8 106 #if !defined(MKL43Z4_H_) /* Check if memory map has not been already included */
Kojto 90:cb3d968589d8 107 #define MKL43Z4_H_
Kojto 90:cb3d968589d8 108 #define MCU_MKL43Z4
Kojto 90:cb3d968589d8 109
Kojto 90:cb3d968589d8 110 /* Check if another memory map has not been also included */
Kojto 90:cb3d968589d8 111 #if (defined(MCU_ACTIVE))
Kojto 90:cb3d968589d8 112 #error MKL43Z4 memory map: There is already included another memory map. Only one memory map can be included.
Kojto 90:cb3d968589d8 113 #endif /* (defined(MCU_ACTIVE)) */
Kojto 90:cb3d968589d8 114 #define MCU_ACTIVE
Kojto 90:cb3d968589d8 115
Kojto 90:cb3d968589d8 116 #include <stdint.h>
Kojto 90:cb3d968589d8 117
Kojto 90:cb3d968589d8 118 /** Memory map major version (memory maps with equal major version number are
Kojto 90:cb3d968589d8 119 * compatible) */
Kojto 90:cb3d968589d8 120 #define MCU_MEM_MAP_VERSION 0x0100u
Kojto 90:cb3d968589d8 121 /** Memory map minor version */
Kojto 90:cb3d968589d8 122 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
Kojto 90:cb3d968589d8 123
Kojto 90:cb3d968589d8 124
Kojto 90:cb3d968589d8 125 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 126 -- Interrupt vector numbers
Kojto 90:cb3d968589d8 127 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 128
Kojto 90:cb3d968589d8 129 /*!
Kojto 90:cb3d968589d8 130 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
Kojto 90:cb3d968589d8 131 * @{
Kojto 90:cb3d968589d8 132 */
Kojto 90:cb3d968589d8 133
Kojto 90:cb3d968589d8 134 /** Interrupt Number Definitions */
Kojto 90:cb3d968589d8 135 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
Kojto 90:cb3d968589d8 136
Kojto 90:cb3d968589d8 137 typedef enum IRQn {
Kojto 90:cb3d968589d8 138 /* Auxiliary constants */
Kojto 90:cb3d968589d8 139 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
Kojto 90:cb3d968589d8 140
Kojto 90:cb3d968589d8 141 /* Core interrupts */
Kojto 90:cb3d968589d8 142 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
Kojto 90:cb3d968589d8 143 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
Kojto 90:cb3d968589d8 144 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
Kojto 90:cb3d968589d8 145 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
Kojto 90:cb3d968589d8 146 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
Kojto 90:cb3d968589d8 147
Kojto 90:cb3d968589d8 148 /* Device specific interrupts */
Kojto 90:cb3d968589d8 149 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
Kojto 90:cb3d968589d8 150 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
Kojto 90:cb3d968589d8 151 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
Kojto 90:cb3d968589d8 152 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
Kojto 90:cb3d968589d8 153 Reserved20_IRQn = 4, /**< Reserved interrupt */
Kojto 90:cb3d968589d8 154 FTFA_IRQn = 5, /**< Command complete and read collision */
Kojto 90:cb3d968589d8 155 PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
Kojto 90:cb3d968589d8 156 LLWU_IRQn = 7, /**< Low leakage wakeup */
Kojto 90:cb3d968589d8 157 I2C0_IRQn = 8, /**< I2C0 interrupt */
Kojto 90:cb3d968589d8 158 I2C1_IRQn = 9, /**< I2C1 interrupt */
Kojto 90:cb3d968589d8 159 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
Kojto 90:cb3d968589d8 160 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
Kojto 90:cb3d968589d8 161 LPUART0_IRQn = 12, /**< LPUART0 status and error */
Kojto 90:cb3d968589d8 162 LPUART1_IRQn = 13, /**< LPUART1 status and error */
Kojto 90:cb3d968589d8 163 UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */
Kojto 90:cb3d968589d8 164 ADC0_IRQn = 15, /**< ADC0 interrupt */
Kojto 90:cb3d968589d8 165 CMP0_IRQn = 16, /**< CMP0 interrupt */
Kojto 90:cb3d968589d8 166 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
Kojto 90:cb3d968589d8 167 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
Kojto 90:cb3d968589d8 168 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
Kojto 90:cb3d968589d8 169 RTC_IRQn = 20, /**< RTC alarm */
Kojto 90:cb3d968589d8 170 RTC_Seconds_IRQn = 21, /**< RTC seconds */
Kojto 90:cb3d968589d8 171 PIT_IRQn = 22, /**< PIT interrupt */
Kojto 90:cb3d968589d8 172 I2S0_IRQn = 23, /**< I2S0 interrupt */
Kojto 90:cb3d968589d8 173 USB0_IRQn = 24, /**< USB0 interrupt */
Kojto 90:cb3d968589d8 174 DAC0_IRQn = 25, /**< DAC0 interrupt */
Kojto 90:cb3d968589d8 175 Reserved42_IRQn = 26, /**< Reserved interrupt */
Kojto 90:cb3d968589d8 176 Reserved43_IRQn = 27, /**< Reserved interrupt */
Kojto 90:cb3d968589d8 177 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
Kojto 90:cb3d968589d8 178 LCD_IRQn = 29, /**< LCD interrupt */
Kojto 90:cb3d968589d8 179 PORTA_IRQn = 30, /**< PORTA Pin detect */
Kojto 90:cb3d968589d8 180 PORTCD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */
Kojto 90:cb3d968589d8 181 } IRQn_Type;
Kojto 90:cb3d968589d8 182
Kojto 90:cb3d968589d8 183 /*!
Kojto 90:cb3d968589d8 184 * @}
Kojto 90:cb3d968589d8 185 */ /* end of group Interrupt_vector_numbers */
Kojto 90:cb3d968589d8 186
Kojto 90:cb3d968589d8 187
Kojto 90:cb3d968589d8 188 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 189 -- Cortex M0 Core Configuration
Kojto 90:cb3d968589d8 190 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 191
Kojto 90:cb3d968589d8 192 /*!
Kojto 90:cb3d968589d8 193 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
Kojto 90:cb3d968589d8 194 * @{
Kojto 90:cb3d968589d8 195 */
Kojto 90:cb3d968589d8 196
Kojto 90:cb3d968589d8 197 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
Kojto 90:cb3d968589d8 198 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
Kojto 90:cb3d968589d8 199 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
Kojto 90:cb3d968589d8 200 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
Kojto 90:cb3d968589d8 201 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
Kojto 90:cb3d968589d8 202
Kojto 90:cb3d968589d8 203 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
Kojto 90:cb3d968589d8 204 #include "system_MKL43Z4.h" /* Device specific configuration file */
Kojto 90:cb3d968589d8 205
Kojto 90:cb3d968589d8 206 /*!
Kojto 90:cb3d968589d8 207 * @}
Kojto 90:cb3d968589d8 208 */ /* end of group Cortex_Core_Configuration */
Kojto 90:cb3d968589d8 209
Kojto 90:cb3d968589d8 210
Kojto 90:cb3d968589d8 211 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 212 -- Device Peripheral Access Layer
Kojto 90:cb3d968589d8 213 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 214
Kojto 90:cb3d968589d8 215 /*!
Kojto 90:cb3d968589d8 216 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
Kojto 90:cb3d968589d8 217 * @{
Kojto 90:cb3d968589d8 218 */
Kojto 90:cb3d968589d8 219
Kojto 90:cb3d968589d8 220
Kojto 90:cb3d968589d8 221 /*
Kojto 90:cb3d968589d8 222 ** Start of section using anonymous unions
Kojto 90:cb3d968589d8 223 */
Kojto 90:cb3d968589d8 224
Kojto 90:cb3d968589d8 225 #if defined(__ARMCC_VERSION)
Kojto 90:cb3d968589d8 226 #pragma push
Kojto 90:cb3d968589d8 227 #pragma anon_unions
Kojto 90:cb3d968589d8 228 #elif defined(__CWCC__)
Kojto 90:cb3d968589d8 229 #pragma push
Kojto 90:cb3d968589d8 230 #pragma cpp_extensions on
Kojto 90:cb3d968589d8 231 #elif defined(__GNUC__)
Kojto 90:cb3d968589d8 232 /* anonymous unions are enabled by default */
Kojto 90:cb3d968589d8 233 #elif defined(__IAR_SYSTEMS_ICC__)
Kojto 90:cb3d968589d8 234 #pragma language=extended
Kojto 90:cb3d968589d8 235 #else
Kojto 90:cb3d968589d8 236 #error Not supported compiler type
Kojto 90:cb3d968589d8 237 #endif
Kojto 90:cb3d968589d8 238
Kojto 90:cb3d968589d8 239 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 240 -- ADC Peripheral Access Layer
Kojto 90:cb3d968589d8 241 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 242
Kojto 90:cb3d968589d8 243 /*!
Kojto 90:cb3d968589d8 244 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
Kojto 90:cb3d968589d8 245 * @{
Kojto 90:cb3d968589d8 246 */
Kojto 90:cb3d968589d8 247
Kojto 90:cb3d968589d8 248 /** ADC - Register Layout Typedef */
Kojto 90:cb3d968589d8 249 typedef struct {
Kojto 90:cb3d968589d8 250 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
Kojto 90:cb3d968589d8 251 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
Kojto 90:cb3d968589d8 252 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
Kojto 90:cb3d968589d8 253 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
Kojto 90:cb3d968589d8 254 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
Kojto 90:cb3d968589d8 255 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
Kojto 90:cb3d968589d8 256 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
Kojto 90:cb3d968589d8 257 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
Kojto 90:cb3d968589d8 258 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
Kojto 90:cb3d968589d8 259 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
Kojto 90:cb3d968589d8 260 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
Kojto 90:cb3d968589d8 261 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
Kojto 90:cb3d968589d8 262 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
Kojto 90:cb3d968589d8 263 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
Kojto 90:cb3d968589d8 264 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
Kojto 90:cb3d968589d8 265 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
Kojto 90:cb3d968589d8 266 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
Kojto 90:cb3d968589d8 267 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
Kojto 90:cb3d968589d8 268 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 269 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
Kojto 90:cb3d968589d8 270 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
Kojto 90:cb3d968589d8 271 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
Kojto 90:cb3d968589d8 272 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
Kojto 90:cb3d968589d8 273 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
Kojto 90:cb3d968589d8 274 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
Kojto 90:cb3d968589d8 275 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
Kojto 90:cb3d968589d8 276 } ADC_Type, *ADC_MemMapPtr;
Kojto 90:cb3d968589d8 277
Kojto 90:cb3d968589d8 278 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 279 -- ADC - Register accessor macros
Kojto 90:cb3d968589d8 280 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 281
Kojto 90:cb3d968589d8 282 /*!
Kojto 90:cb3d968589d8 283 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
Kojto 90:cb3d968589d8 284 * @{
Kojto 90:cb3d968589d8 285 */
Kojto 90:cb3d968589d8 286
Kojto 90:cb3d968589d8 287
Kojto 90:cb3d968589d8 288 /* ADC - Register accessors */
Kojto 90:cb3d968589d8 289 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
Kojto 90:cb3d968589d8 290 #define ADC_CFG1_REG(base) ((base)->CFG1)
Kojto 90:cb3d968589d8 291 #define ADC_CFG2_REG(base) ((base)->CFG2)
Kojto 90:cb3d968589d8 292 #define ADC_R_REG(base,index) ((base)->R[index])
Kojto 90:cb3d968589d8 293 #define ADC_CV1_REG(base) ((base)->CV1)
Kojto 90:cb3d968589d8 294 #define ADC_CV2_REG(base) ((base)->CV2)
Kojto 90:cb3d968589d8 295 #define ADC_SC2_REG(base) ((base)->SC2)
Kojto 90:cb3d968589d8 296 #define ADC_SC3_REG(base) ((base)->SC3)
Kojto 90:cb3d968589d8 297 #define ADC_OFS_REG(base) ((base)->OFS)
Kojto 90:cb3d968589d8 298 #define ADC_PG_REG(base) ((base)->PG)
Kojto 90:cb3d968589d8 299 #define ADC_MG_REG(base) ((base)->MG)
Kojto 90:cb3d968589d8 300 #define ADC_CLPD_REG(base) ((base)->CLPD)
Kojto 90:cb3d968589d8 301 #define ADC_CLPS_REG(base) ((base)->CLPS)
Kojto 90:cb3d968589d8 302 #define ADC_CLP4_REG(base) ((base)->CLP4)
Kojto 90:cb3d968589d8 303 #define ADC_CLP3_REG(base) ((base)->CLP3)
Kojto 90:cb3d968589d8 304 #define ADC_CLP2_REG(base) ((base)->CLP2)
Kojto 90:cb3d968589d8 305 #define ADC_CLP1_REG(base) ((base)->CLP1)
Kojto 90:cb3d968589d8 306 #define ADC_CLP0_REG(base) ((base)->CLP0)
Kojto 90:cb3d968589d8 307 #define ADC_CLMD_REG(base) ((base)->CLMD)
Kojto 90:cb3d968589d8 308 #define ADC_CLMS_REG(base) ((base)->CLMS)
Kojto 90:cb3d968589d8 309 #define ADC_CLM4_REG(base) ((base)->CLM4)
Kojto 90:cb3d968589d8 310 #define ADC_CLM3_REG(base) ((base)->CLM3)
Kojto 90:cb3d968589d8 311 #define ADC_CLM2_REG(base) ((base)->CLM2)
Kojto 90:cb3d968589d8 312 #define ADC_CLM1_REG(base) ((base)->CLM1)
Kojto 90:cb3d968589d8 313 #define ADC_CLM0_REG(base) ((base)->CLM0)
Kojto 90:cb3d968589d8 314
Kojto 90:cb3d968589d8 315 /*!
Kojto 90:cb3d968589d8 316 * @}
Kojto 90:cb3d968589d8 317 */ /* end of group ADC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 318
Kojto 90:cb3d968589d8 319
Kojto 90:cb3d968589d8 320 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 321 -- ADC Register Masks
Kojto 90:cb3d968589d8 322 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 323
Kojto 90:cb3d968589d8 324 /*!
Kojto 90:cb3d968589d8 325 * @addtogroup ADC_Register_Masks ADC Register Masks
Kojto 90:cb3d968589d8 326 * @{
Kojto 90:cb3d968589d8 327 */
Kojto 90:cb3d968589d8 328
Kojto 90:cb3d968589d8 329 /* SC1 Bit Fields */
Kojto 90:cb3d968589d8 330 #define ADC_SC1_ADCH_MASK 0x1Fu
Kojto 90:cb3d968589d8 331 #define ADC_SC1_ADCH_SHIFT 0
Kojto 90:cb3d968589d8 332 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
Kojto 90:cb3d968589d8 333 #define ADC_SC1_DIFF_MASK 0x20u
Kojto 90:cb3d968589d8 334 #define ADC_SC1_DIFF_SHIFT 5
Kojto 90:cb3d968589d8 335 #define ADC_SC1_AIEN_MASK 0x40u
Kojto 90:cb3d968589d8 336 #define ADC_SC1_AIEN_SHIFT 6
Kojto 90:cb3d968589d8 337 #define ADC_SC1_COCO_MASK 0x80u
Kojto 90:cb3d968589d8 338 #define ADC_SC1_COCO_SHIFT 7
Kojto 90:cb3d968589d8 339 /* CFG1 Bit Fields */
Kojto 90:cb3d968589d8 340 #define ADC_CFG1_ADICLK_MASK 0x3u
Kojto 90:cb3d968589d8 341 #define ADC_CFG1_ADICLK_SHIFT 0
Kojto 90:cb3d968589d8 342 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
Kojto 90:cb3d968589d8 343 #define ADC_CFG1_MODE_MASK 0xCu
Kojto 90:cb3d968589d8 344 #define ADC_CFG1_MODE_SHIFT 2
Kojto 90:cb3d968589d8 345 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
Kojto 90:cb3d968589d8 346 #define ADC_CFG1_ADLSMP_MASK 0x10u
Kojto 90:cb3d968589d8 347 #define ADC_CFG1_ADLSMP_SHIFT 4
Kojto 90:cb3d968589d8 348 #define ADC_CFG1_ADIV_MASK 0x60u
Kojto 90:cb3d968589d8 349 #define ADC_CFG1_ADIV_SHIFT 5
Kojto 90:cb3d968589d8 350 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
Kojto 90:cb3d968589d8 351 #define ADC_CFG1_ADLPC_MASK 0x80u
Kojto 90:cb3d968589d8 352 #define ADC_CFG1_ADLPC_SHIFT 7
Kojto 90:cb3d968589d8 353 /* CFG2 Bit Fields */
Kojto 90:cb3d968589d8 354 #define ADC_CFG2_ADLSTS_MASK 0x3u
Kojto 90:cb3d968589d8 355 #define ADC_CFG2_ADLSTS_SHIFT 0
Kojto 90:cb3d968589d8 356 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
Kojto 90:cb3d968589d8 357 #define ADC_CFG2_ADHSC_MASK 0x4u
Kojto 90:cb3d968589d8 358 #define ADC_CFG2_ADHSC_SHIFT 2
Kojto 90:cb3d968589d8 359 #define ADC_CFG2_ADACKEN_MASK 0x8u
Kojto 90:cb3d968589d8 360 #define ADC_CFG2_ADACKEN_SHIFT 3
Kojto 90:cb3d968589d8 361 #define ADC_CFG2_MUXSEL_MASK 0x10u
Kojto 90:cb3d968589d8 362 #define ADC_CFG2_MUXSEL_SHIFT 4
Kojto 90:cb3d968589d8 363 /* R Bit Fields */
Kojto 90:cb3d968589d8 364 #define ADC_R_D_MASK 0xFFFFu
Kojto 90:cb3d968589d8 365 #define ADC_R_D_SHIFT 0
Kojto 90:cb3d968589d8 366 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
Kojto 90:cb3d968589d8 367 /* CV1 Bit Fields */
Kojto 90:cb3d968589d8 368 #define ADC_CV1_CV_MASK 0xFFFFu
Kojto 90:cb3d968589d8 369 #define ADC_CV1_CV_SHIFT 0
Kojto 90:cb3d968589d8 370 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
Kojto 90:cb3d968589d8 371 /* CV2 Bit Fields */
Kojto 90:cb3d968589d8 372 #define ADC_CV2_CV_MASK 0xFFFFu
Kojto 90:cb3d968589d8 373 #define ADC_CV2_CV_SHIFT 0
Kojto 90:cb3d968589d8 374 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
Kojto 90:cb3d968589d8 375 /* SC2 Bit Fields */
Kojto 90:cb3d968589d8 376 #define ADC_SC2_REFSEL_MASK 0x3u
Kojto 90:cb3d968589d8 377 #define ADC_SC2_REFSEL_SHIFT 0
Kojto 90:cb3d968589d8 378 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
Kojto 90:cb3d968589d8 379 #define ADC_SC2_DMAEN_MASK 0x4u
Kojto 90:cb3d968589d8 380 #define ADC_SC2_DMAEN_SHIFT 2
Kojto 90:cb3d968589d8 381 #define ADC_SC2_ACREN_MASK 0x8u
Kojto 90:cb3d968589d8 382 #define ADC_SC2_ACREN_SHIFT 3
Kojto 90:cb3d968589d8 383 #define ADC_SC2_ACFGT_MASK 0x10u
Kojto 90:cb3d968589d8 384 #define ADC_SC2_ACFGT_SHIFT 4
Kojto 90:cb3d968589d8 385 #define ADC_SC2_ACFE_MASK 0x20u
Kojto 90:cb3d968589d8 386 #define ADC_SC2_ACFE_SHIFT 5
Kojto 90:cb3d968589d8 387 #define ADC_SC2_ADTRG_MASK 0x40u
Kojto 90:cb3d968589d8 388 #define ADC_SC2_ADTRG_SHIFT 6
Kojto 90:cb3d968589d8 389 #define ADC_SC2_ADACT_MASK 0x80u
Kojto 90:cb3d968589d8 390 #define ADC_SC2_ADACT_SHIFT 7
Kojto 90:cb3d968589d8 391 /* SC3 Bit Fields */
Kojto 90:cb3d968589d8 392 #define ADC_SC3_AVGS_MASK 0x3u
Kojto 90:cb3d968589d8 393 #define ADC_SC3_AVGS_SHIFT 0
Kojto 90:cb3d968589d8 394 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
Kojto 90:cb3d968589d8 395 #define ADC_SC3_AVGE_MASK 0x4u
Kojto 90:cb3d968589d8 396 #define ADC_SC3_AVGE_SHIFT 2
Kojto 90:cb3d968589d8 397 #define ADC_SC3_ADCO_MASK 0x8u
Kojto 90:cb3d968589d8 398 #define ADC_SC3_ADCO_SHIFT 3
Kojto 90:cb3d968589d8 399 #define ADC_SC3_CALF_MASK 0x40u
Kojto 90:cb3d968589d8 400 #define ADC_SC3_CALF_SHIFT 6
Kojto 90:cb3d968589d8 401 #define ADC_SC3_CAL_MASK 0x80u
Kojto 90:cb3d968589d8 402 #define ADC_SC3_CAL_SHIFT 7
Kojto 90:cb3d968589d8 403 /* OFS Bit Fields */
Kojto 90:cb3d968589d8 404 #define ADC_OFS_OFS_MASK 0xFFFFu
Kojto 90:cb3d968589d8 405 #define ADC_OFS_OFS_SHIFT 0
Kojto 90:cb3d968589d8 406 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
Kojto 90:cb3d968589d8 407 /* PG Bit Fields */
Kojto 90:cb3d968589d8 408 #define ADC_PG_PG_MASK 0xFFFFu
Kojto 90:cb3d968589d8 409 #define ADC_PG_PG_SHIFT 0
Kojto 90:cb3d968589d8 410 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
Kojto 90:cb3d968589d8 411 /* MG Bit Fields */
Kojto 90:cb3d968589d8 412 #define ADC_MG_MG_MASK 0xFFFFu
Kojto 90:cb3d968589d8 413 #define ADC_MG_MG_SHIFT 0
Kojto 90:cb3d968589d8 414 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
Kojto 90:cb3d968589d8 415 /* CLPD Bit Fields */
Kojto 90:cb3d968589d8 416 #define ADC_CLPD_CLPD_MASK 0x3Fu
Kojto 90:cb3d968589d8 417 #define ADC_CLPD_CLPD_SHIFT 0
Kojto 90:cb3d968589d8 418 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
Kojto 90:cb3d968589d8 419 /* CLPS Bit Fields */
Kojto 90:cb3d968589d8 420 #define ADC_CLPS_CLPS_MASK 0x3Fu
Kojto 90:cb3d968589d8 421 #define ADC_CLPS_CLPS_SHIFT 0
Kojto 90:cb3d968589d8 422 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
Kojto 90:cb3d968589d8 423 /* CLP4 Bit Fields */
Kojto 90:cb3d968589d8 424 #define ADC_CLP4_CLP4_MASK 0x3FFu
Kojto 90:cb3d968589d8 425 #define ADC_CLP4_CLP4_SHIFT 0
Kojto 90:cb3d968589d8 426 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
Kojto 90:cb3d968589d8 427 /* CLP3 Bit Fields */
Kojto 90:cb3d968589d8 428 #define ADC_CLP3_CLP3_MASK 0x1FFu
Kojto 90:cb3d968589d8 429 #define ADC_CLP3_CLP3_SHIFT 0
Kojto 90:cb3d968589d8 430 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
Kojto 90:cb3d968589d8 431 /* CLP2 Bit Fields */
Kojto 90:cb3d968589d8 432 #define ADC_CLP2_CLP2_MASK 0xFFu
Kojto 90:cb3d968589d8 433 #define ADC_CLP2_CLP2_SHIFT 0
Kojto 90:cb3d968589d8 434 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
Kojto 90:cb3d968589d8 435 /* CLP1 Bit Fields */
Kojto 90:cb3d968589d8 436 #define ADC_CLP1_CLP1_MASK 0x7Fu
Kojto 90:cb3d968589d8 437 #define ADC_CLP1_CLP1_SHIFT 0
Kojto 90:cb3d968589d8 438 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
Kojto 90:cb3d968589d8 439 /* CLP0 Bit Fields */
Kojto 90:cb3d968589d8 440 #define ADC_CLP0_CLP0_MASK 0x3Fu
Kojto 90:cb3d968589d8 441 #define ADC_CLP0_CLP0_SHIFT 0
Kojto 90:cb3d968589d8 442 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
Kojto 90:cb3d968589d8 443 /* CLMD Bit Fields */
Kojto 90:cb3d968589d8 444 #define ADC_CLMD_CLMD_MASK 0x3Fu
Kojto 90:cb3d968589d8 445 #define ADC_CLMD_CLMD_SHIFT 0
Kojto 90:cb3d968589d8 446 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
Kojto 90:cb3d968589d8 447 /* CLMS Bit Fields */
Kojto 90:cb3d968589d8 448 #define ADC_CLMS_CLMS_MASK 0x3Fu
Kojto 90:cb3d968589d8 449 #define ADC_CLMS_CLMS_SHIFT 0
Kojto 90:cb3d968589d8 450 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
Kojto 90:cb3d968589d8 451 /* CLM4 Bit Fields */
Kojto 90:cb3d968589d8 452 #define ADC_CLM4_CLM4_MASK 0x3FFu
Kojto 90:cb3d968589d8 453 #define ADC_CLM4_CLM4_SHIFT 0
Kojto 90:cb3d968589d8 454 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
Kojto 90:cb3d968589d8 455 /* CLM3 Bit Fields */
Kojto 90:cb3d968589d8 456 #define ADC_CLM3_CLM3_MASK 0x1FFu
Kojto 90:cb3d968589d8 457 #define ADC_CLM3_CLM3_SHIFT 0
Kojto 90:cb3d968589d8 458 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
Kojto 90:cb3d968589d8 459 /* CLM2 Bit Fields */
Kojto 90:cb3d968589d8 460 #define ADC_CLM2_CLM2_MASK 0xFFu
Kojto 90:cb3d968589d8 461 #define ADC_CLM2_CLM2_SHIFT 0
Kojto 90:cb3d968589d8 462 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
Kojto 90:cb3d968589d8 463 /* CLM1 Bit Fields */
Kojto 90:cb3d968589d8 464 #define ADC_CLM1_CLM1_MASK 0x7Fu
Kojto 90:cb3d968589d8 465 #define ADC_CLM1_CLM1_SHIFT 0
Kojto 90:cb3d968589d8 466 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
Kojto 90:cb3d968589d8 467 /* CLM0 Bit Fields */
Kojto 90:cb3d968589d8 468 #define ADC_CLM0_CLM0_MASK 0x3Fu
Kojto 90:cb3d968589d8 469 #define ADC_CLM0_CLM0_SHIFT 0
Kojto 90:cb3d968589d8 470 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
Kojto 90:cb3d968589d8 471
Kojto 90:cb3d968589d8 472 /*!
Kojto 90:cb3d968589d8 473 * @}
Kojto 90:cb3d968589d8 474 */ /* end of group ADC_Register_Masks */
Kojto 90:cb3d968589d8 475
Kojto 90:cb3d968589d8 476
Kojto 90:cb3d968589d8 477 /* ADC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 478 /** Peripheral ADC0 base address */
Kojto 90:cb3d968589d8 479 #define ADC0_BASE (0x4003B000u)
Kojto 90:cb3d968589d8 480 /** Peripheral ADC0 base pointer */
Kojto 90:cb3d968589d8 481 #define ADC0 ((ADC_Type *)ADC0_BASE)
Kojto 90:cb3d968589d8 482 #define ADC0_BASE_PTR (ADC0)
Kojto 90:cb3d968589d8 483 /** Array initializer of ADC peripheral base addresses */
Kojto 90:cb3d968589d8 484 #define ADC_BASE_ADDRS { ADC0_BASE }
Kojto 90:cb3d968589d8 485 /** Array initializer of ADC peripheral base pointers */
Kojto 90:cb3d968589d8 486 #define ADC_BASE_PTRS { ADC0 }
Kojto 90:cb3d968589d8 487 /** Interrupt vectors for the ADC peripheral type */
Kojto 90:cb3d968589d8 488 #define ADC_IRQS { ADC0_IRQn }
Kojto 90:cb3d968589d8 489
Kojto 90:cb3d968589d8 490 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 491 -- ADC - Register accessor macros
Kojto 90:cb3d968589d8 492 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 493
Kojto 90:cb3d968589d8 494 /*!
Kojto 90:cb3d968589d8 495 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
Kojto 90:cb3d968589d8 496 * @{
Kojto 90:cb3d968589d8 497 */
Kojto 90:cb3d968589d8 498
Kojto 90:cb3d968589d8 499
Kojto 90:cb3d968589d8 500 /* ADC - Register instance definitions */
Kojto 90:cb3d968589d8 501 /* ADC0 */
Kojto 90:cb3d968589d8 502 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
Kojto 90:cb3d968589d8 503 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
Kojto 90:cb3d968589d8 504 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
Kojto 90:cb3d968589d8 505 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
Kojto 90:cb3d968589d8 506 #define ADC0_RA ADC_R_REG(ADC0,0)
Kojto 90:cb3d968589d8 507 #define ADC0_RB ADC_R_REG(ADC0,1)
Kojto 90:cb3d968589d8 508 #define ADC0_CV1 ADC_CV1_REG(ADC0)
Kojto 90:cb3d968589d8 509 #define ADC0_CV2 ADC_CV2_REG(ADC0)
Kojto 90:cb3d968589d8 510 #define ADC0_SC2 ADC_SC2_REG(ADC0)
Kojto 90:cb3d968589d8 511 #define ADC0_SC3 ADC_SC3_REG(ADC0)
Kojto 90:cb3d968589d8 512 #define ADC0_OFS ADC_OFS_REG(ADC0)
Kojto 90:cb3d968589d8 513 #define ADC0_PG ADC_PG_REG(ADC0)
Kojto 90:cb3d968589d8 514 #define ADC0_MG ADC_MG_REG(ADC0)
Kojto 90:cb3d968589d8 515 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
Kojto 90:cb3d968589d8 516 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
Kojto 90:cb3d968589d8 517 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
Kojto 90:cb3d968589d8 518 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
Kojto 90:cb3d968589d8 519 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
Kojto 90:cb3d968589d8 520 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
Kojto 90:cb3d968589d8 521 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
Kojto 90:cb3d968589d8 522 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
Kojto 90:cb3d968589d8 523 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
Kojto 90:cb3d968589d8 524 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
Kojto 90:cb3d968589d8 525 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
Kojto 90:cb3d968589d8 526 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
Kojto 90:cb3d968589d8 527 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
Kojto 90:cb3d968589d8 528 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
Kojto 90:cb3d968589d8 529
Kojto 90:cb3d968589d8 530 /* ADC - Register array accessors */
Kojto 90:cb3d968589d8 531 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
Kojto 90:cb3d968589d8 532 #define ADC0_R(index) ADC_R_REG(ADC0,index)
Kojto 90:cb3d968589d8 533
Kojto 90:cb3d968589d8 534 /*!
Kojto 90:cb3d968589d8 535 * @}
Kojto 90:cb3d968589d8 536 */ /* end of group ADC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 537
Kojto 90:cb3d968589d8 538
Kojto 90:cb3d968589d8 539 /*!
Kojto 90:cb3d968589d8 540 * @}
Kojto 90:cb3d968589d8 541 */ /* end of group ADC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 542
Kojto 90:cb3d968589d8 543
Kojto 90:cb3d968589d8 544 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 545 -- CMP Peripheral Access Layer
Kojto 90:cb3d968589d8 546 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 547
Kojto 90:cb3d968589d8 548 /*!
Kojto 90:cb3d968589d8 549 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
Kojto 90:cb3d968589d8 550 * @{
Kojto 90:cb3d968589d8 551 */
Kojto 90:cb3d968589d8 552
Kojto 90:cb3d968589d8 553 /** CMP - Register Layout Typedef */
Kojto 90:cb3d968589d8 554 typedef struct {
Kojto 90:cb3d968589d8 555 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
Kojto 90:cb3d968589d8 556 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
Kojto 90:cb3d968589d8 557 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
Kojto 90:cb3d968589d8 558 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
Kojto 90:cb3d968589d8 559 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
Kojto 90:cb3d968589d8 560 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
Kojto 90:cb3d968589d8 561 } CMP_Type, *CMP_MemMapPtr;
Kojto 90:cb3d968589d8 562
Kojto 90:cb3d968589d8 563 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 564 -- CMP - Register accessor macros
Kojto 90:cb3d968589d8 565 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 566
Kojto 90:cb3d968589d8 567 /*!
Kojto 90:cb3d968589d8 568 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
Kojto 90:cb3d968589d8 569 * @{
Kojto 90:cb3d968589d8 570 */
Kojto 90:cb3d968589d8 571
Kojto 90:cb3d968589d8 572
Kojto 90:cb3d968589d8 573 /* CMP - Register accessors */
Kojto 90:cb3d968589d8 574 #define CMP_CR0_REG(base) ((base)->CR0)
Kojto 90:cb3d968589d8 575 #define CMP_CR1_REG(base) ((base)->CR1)
Kojto 90:cb3d968589d8 576 #define CMP_FPR_REG(base) ((base)->FPR)
Kojto 90:cb3d968589d8 577 #define CMP_SCR_REG(base) ((base)->SCR)
Kojto 90:cb3d968589d8 578 #define CMP_DACCR_REG(base) ((base)->DACCR)
Kojto 90:cb3d968589d8 579 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
Kojto 90:cb3d968589d8 580
Kojto 90:cb3d968589d8 581 /*!
Kojto 90:cb3d968589d8 582 * @}
Kojto 90:cb3d968589d8 583 */ /* end of group CMP_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 584
Kojto 90:cb3d968589d8 585
Kojto 90:cb3d968589d8 586 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 587 -- CMP Register Masks
Kojto 90:cb3d968589d8 588 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 589
Kojto 90:cb3d968589d8 590 /*!
Kojto 90:cb3d968589d8 591 * @addtogroup CMP_Register_Masks CMP Register Masks
Kojto 90:cb3d968589d8 592 * @{
Kojto 90:cb3d968589d8 593 */
Kojto 90:cb3d968589d8 594
Kojto 90:cb3d968589d8 595 /* CR0 Bit Fields */
Kojto 90:cb3d968589d8 596 #define CMP_CR0_HYSTCTR_MASK 0x3u
Kojto 90:cb3d968589d8 597 #define CMP_CR0_HYSTCTR_SHIFT 0
Kojto 90:cb3d968589d8 598 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
Kojto 90:cb3d968589d8 599 #define CMP_CR0_FILTER_CNT_MASK 0x70u
Kojto 90:cb3d968589d8 600 #define CMP_CR0_FILTER_CNT_SHIFT 4
Kojto 90:cb3d968589d8 601 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
Kojto 90:cb3d968589d8 602 /* CR1 Bit Fields */
Kojto 90:cb3d968589d8 603 #define CMP_CR1_EN_MASK 0x1u
Kojto 90:cb3d968589d8 604 #define CMP_CR1_EN_SHIFT 0
Kojto 90:cb3d968589d8 605 #define CMP_CR1_OPE_MASK 0x2u
Kojto 90:cb3d968589d8 606 #define CMP_CR1_OPE_SHIFT 1
Kojto 90:cb3d968589d8 607 #define CMP_CR1_COS_MASK 0x4u
Kojto 90:cb3d968589d8 608 #define CMP_CR1_COS_SHIFT 2
Kojto 90:cb3d968589d8 609 #define CMP_CR1_INV_MASK 0x8u
Kojto 90:cb3d968589d8 610 #define CMP_CR1_INV_SHIFT 3
Kojto 90:cb3d968589d8 611 #define CMP_CR1_PMODE_MASK 0x10u
Kojto 90:cb3d968589d8 612 #define CMP_CR1_PMODE_SHIFT 4
Kojto 90:cb3d968589d8 613 #define CMP_CR1_TRIGM_MASK 0x20u
Kojto 90:cb3d968589d8 614 #define CMP_CR1_TRIGM_SHIFT 5
Kojto 90:cb3d968589d8 615 #define CMP_CR1_WE_MASK 0x40u
Kojto 90:cb3d968589d8 616 #define CMP_CR1_WE_SHIFT 6
Kojto 90:cb3d968589d8 617 #define CMP_CR1_SE_MASK 0x80u
Kojto 90:cb3d968589d8 618 #define CMP_CR1_SE_SHIFT 7
Kojto 90:cb3d968589d8 619 /* FPR Bit Fields */
Kojto 90:cb3d968589d8 620 #define CMP_FPR_FILT_PER_MASK 0xFFu
Kojto 90:cb3d968589d8 621 #define CMP_FPR_FILT_PER_SHIFT 0
Kojto 90:cb3d968589d8 622 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
Kojto 90:cb3d968589d8 623 /* SCR Bit Fields */
Kojto 90:cb3d968589d8 624 #define CMP_SCR_COUT_MASK 0x1u
Kojto 90:cb3d968589d8 625 #define CMP_SCR_COUT_SHIFT 0
Kojto 90:cb3d968589d8 626 #define CMP_SCR_CFF_MASK 0x2u
Kojto 90:cb3d968589d8 627 #define CMP_SCR_CFF_SHIFT 1
Kojto 90:cb3d968589d8 628 #define CMP_SCR_CFR_MASK 0x4u
Kojto 90:cb3d968589d8 629 #define CMP_SCR_CFR_SHIFT 2
Kojto 90:cb3d968589d8 630 #define CMP_SCR_IEF_MASK 0x8u
Kojto 90:cb3d968589d8 631 #define CMP_SCR_IEF_SHIFT 3
Kojto 90:cb3d968589d8 632 #define CMP_SCR_IER_MASK 0x10u
Kojto 90:cb3d968589d8 633 #define CMP_SCR_IER_SHIFT 4
Kojto 90:cb3d968589d8 634 #define CMP_SCR_DMAEN_MASK 0x40u
Kojto 90:cb3d968589d8 635 #define CMP_SCR_DMAEN_SHIFT 6
Kojto 90:cb3d968589d8 636 /* DACCR Bit Fields */
Kojto 90:cb3d968589d8 637 #define CMP_DACCR_VOSEL_MASK 0x3Fu
Kojto 90:cb3d968589d8 638 #define CMP_DACCR_VOSEL_SHIFT 0
Kojto 90:cb3d968589d8 639 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
Kojto 90:cb3d968589d8 640 #define CMP_DACCR_VRSEL_MASK 0x40u
Kojto 90:cb3d968589d8 641 #define CMP_DACCR_VRSEL_SHIFT 6
Kojto 90:cb3d968589d8 642 #define CMP_DACCR_DACEN_MASK 0x80u
Kojto 90:cb3d968589d8 643 #define CMP_DACCR_DACEN_SHIFT 7
Kojto 90:cb3d968589d8 644 /* MUXCR Bit Fields */
Kojto 90:cb3d968589d8 645 #define CMP_MUXCR_MSEL_MASK 0x7u
Kojto 90:cb3d968589d8 646 #define CMP_MUXCR_MSEL_SHIFT 0
Kojto 90:cb3d968589d8 647 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
Kojto 90:cb3d968589d8 648 #define CMP_MUXCR_PSEL_MASK 0x38u
Kojto 90:cb3d968589d8 649 #define CMP_MUXCR_PSEL_SHIFT 3
Kojto 90:cb3d968589d8 650 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
Kojto 90:cb3d968589d8 651 #define CMP_MUXCR_PSTM_MASK 0x80u
Kojto 90:cb3d968589d8 652 #define CMP_MUXCR_PSTM_SHIFT 7
Kojto 90:cb3d968589d8 653
Kojto 90:cb3d968589d8 654 /*!
Kojto 90:cb3d968589d8 655 * @}
Kojto 90:cb3d968589d8 656 */ /* end of group CMP_Register_Masks */
Kojto 90:cb3d968589d8 657
Kojto 90:cb3d968589d8 658
Kojto 90:cb3d968589d8 659 /* CMP - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 660 /** Peripheral CMP0 base address */
Kojto 90:cb3d968589d8 661 #define CMP0_BASE (0x40073000u)
Kojto 90:cb3d968589d8 662 /** Peripheral CMP0 base pointer */
Kojto 90:cb3d968589d8 663 #define CMP0 ((CMP_Type *)CMP0_BASE)
Kojto 90:cb3d968589d8 664 #define CMP0_BASE_PTR (CMP0)
Kojto 90:cb3d968589d8 665 /** Array initializer of CMP peripheral base addresses */
Kojto 90:cb3d968589d8 666 #define CMP_BASE_ADDRS { CMP0_BASE }
Kojto 90:cb3d968589d8 667 /** Array initializer of CMP peripheral base pointers */
Kojto 90:cb3d968589d8 668 #define CMP_BASE_PTRS { CMP0 }
Kojto 90:cb3d968589d8 669 /** Interrupt vectors for the CMP peripheral type */
Kojto 90:cb3d968589d8 670 #define CMP_IRQS { CMP0_IRQn }
Kojto 90:cb3d968589d8 671
Kojto 90:cb3d968589d8 672 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 673 -- CMP - Register accessor macros
Kojto 90:cb3d968589d8 674 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 675
Kojto 90:cb3d968589d8 676 /*!
Kojto 90:cb3d968589d8 677 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
Kojto 90:cb3d968589d8 678 * @{
Kojto 90:cb3d968589d8 679 */
Kojto 90:cb3d968589d8 680
Kojto 90:cb3d968589d8 681
Kojto 90:cb3d968589d8 682 /* CMP - Register instance definitions */
Kojto 90:cb3d968589d8 683 /* CMP0 */
Kojto 90:cb3d968589d8 684 #define CMP0_CR0 CMP_CR0_REG(CMP0)
Kojto 90:cb3d968589d8 685 #define CMP0_CR1 CMP_CR1_REG(CMP0)
Kojto 90:cb3d968589d8 686 #define CMP0_FPR CMP_FPR_REG(CMP0)
Kojto 90:cb3d968589d8 687 #define CMP0_SCR CMP_SCR_REG(CMP0)
Kojto 90:cb3d968589d8 688 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
Kojto 90:cb3d968589d8 689 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
Kojto 90:cb3d968589d8 690
Kojto 90:cb3d968589d8 691 /*!
Kojto 90:cb3d968589d8 692 * @}
Kojto 90:cb3d968589d8 693 */ /* end of group CMP_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 694
Kojto 90:cb3d968589d8 695
Kojto 90:cb3d968589d8 696 /*!
Kojto 90:cb3d968589d8 697 * @}
Kojto 90:cb3d968589d8 698 */ /* end of group CMP_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 699
Kojto 90:cb3d968589d8 700
Kojto 90:cb3d968589d8 701 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 702 -- DAC Peripheral Access Layer
Kojto 90:cb3d968589d8 703 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 704
Kojto 90:cb3d968589d8 705 /*!
Kojto 90:cb3d968589d8 706 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
Kojto 90:cb3d968589d8 707 * @{
Kojto 90:cb3d968589d8 708 */
Kojto 90:cb3d968589d8 709
Kojto 90:cb3d968589d8 710 /** DAC - Register Layout Typedef */
Kojto 90:cb3d968589d8 711 typedef struct {
Kojto 90:cb3d968589d8 712 struct { /* offset: 0x0, array step: 0x2 */
Kojto 90:cb3d968589d8 713 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
Kojto 90:cb3d968589d8 714 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
Kojto 90:cb3d968589d8 715 } DAT[2];
Kojto 90:cb3d968589d8 716 uint8_t RESERVED_0[28];
Kojto 90:cb3d968589d8 717 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
Kojto 90:cb3d968589d8 718 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
Kojto 90:cb3d968589d8 719 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
Kojto 90:cb3d968589d8 720 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
Kojto 90:cb3d968589d8 721 } DAC_Type, *DAC_MemMapPtr;
Kojto 90:cb3d968589d8 722
Kojto 90:cb3d968589d8 723 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 724 -- DAC - Register accessor macros
Kojto 90:cb3d968589d8 725 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 726
Kojto 90:cb3d968589d8 727 /*!
Kojto 90:cb3d968589d8 728 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
Kojto 90:cb3d968589d8 729 * @{
Kojto 90:cb3d968589d8 730 */
Kojto 90:cb3d968589d8 731
Kojto 90:cb3d968589d8 732
Kojto 90:cb3d968589d8 733 /* DAC - Register accessors */
Kojto 90:cb3d968589d8 734 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
Kojto 90:cb3d968589d8 735 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
Kojto 90:cb3d968589d8 736 #define DAC_SR_REG(base) ((base)->SR)
Kojto 90:cb3d968589d8 737 #define DAC_C0_REG(base) ((base)->C0)
Kojto 90:cb3d968589d8 738 #define DAC_C1_REG(base) ((base)->C1)
Kojto 90:cb3d968589d8 739 #define DAC_C2_REG(base) ((base)->C2)
Kojto 90:cb3d968589d8 740
Kojto 90:cb3d968589d8 741 /*!
Kojto 90:cb3d968589d8 742 * @}
Kojto 90:cb3d968589d8 743 */ /* end of group DAC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 744
Kojto 90:cb3d968589d8 745
Kojto 90:cb3d968589d8 746 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 747 -- DAC Register Masks
Kojto 90:cb3d968589d8 748 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 749
Kojto 90:cb3d968589d8 750 /*!
Kojto 90:cb3d968589d8 751 * @addtogroup DAC_Register_Masks DAC Register Masks
Kojto 90:cb3d968589d8 752 * @{
Kojto 90:cb3d968589d8 753 */
Kojto 90:cb3d968589d8 754
Kojto 90:cb3d968589d8 755 /* DATL Bit Fields */
Kojto 90:cb3d968589d8 756 #define DAC_DATL_DATA0_MASK 0xFFu
Kojto 90:cb3d968589d8 757 #define DAC_DATL_DATA0_SHIFT 0
Kojto 90:cb3d968589d8 758 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
Kojto 90:cb3d968589d8 759 /* DATH Bit Fields */
Kojto 90:cb3d968589d8 760 #define DAC_DATH_DATA1_MASK 0xFu
Kojto 90:cb3d968589d8 761 #define DAC_DATH_DATA1_SHIFT 0
Kojto 90:cb3d968589d8 762 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
Kojto 90:cb3d968589d8 763 /* SR Bit Fields */
Kojto 90:cb3d968589d8 764 #define DAC_SR_DACBFRPBF_MASK 0x1u
Kojto 90:cb3d968589d8 765 #define DAC_SR_DACBFRPBF_SHIFT 0
Kojto 90:cb3d968589d8 766 #define DAC_SR_DACBFRPTF_MASK 0x2u
Kojto 90:cb3d968589d8 767 #define DAC_SR_DACBFRPTF_SHIFT 1
Kojto 90:cb3d968589d8 768 /* C0 Bit Fields */
Kojto 90:cb3d968589d8 769 #define DAC_C0_DACBBIEN_MASK 0x1u
Kojto 90:cb3d968589d8 770 #define DAC_C0_DACBBIEN_SHIFT 0
Kojto 90:cb3d968589d8 771 #define DAC_C0_DACBTIEN_MASK 0x2u
Kojto 90:cb3d968589d8 772 #define DAC_C0_DACBTIEN_SHIFT 1
Kojto 90:cb3d968589d8 773 #define DAC_C0_LPEN_MASK 0x8u
Kojto 90:cb3d968589d8 774 #define DAC_C0_LPEN_SHIFT 3
Kojto 90:cb3d968589d8 775 #define DAC_C0_DACSWTRG_MASK 0x10u
Kojto 90:cb3d968589d8 776 #define DAC_C0_DACSWTRG_SHIFT 4
Kojto 90:cb3d968589d8 777 #define DAC_C0_DACTRGSEL_MASK 0x20u
Kojto 90:cb3d968589d8 778 #define DAC_C0_DACTRGSEL_SHIFT 5
Kojto 90:cb3d968589d8 779 #define DAC_C0_DACRFS_MASK 0x40u
Kojto 90:cb3d968589d8 780 #define DAC_C0_DACRFS_SHIFT 6
Kojto 90:cb3d968589d8 781 #define DAC_C0_DACEN_MASK 0x80u
Kojto 90:cb3d968589d8 782 #define DAC_C0_DACEN_SHIFT 7
Kojto 90:cb3d968589d8 783 /* C1 Bit Fields */
Kojto 90:cb3d968589d8 784 #define DAC_C1_DACBFEN_MASK 0x1u
Kojto 90:cb3d968589d8 785 #define DAC_C1_DACBFEN_SHIFT 0
Kojto 90:cb3d968589d8 786 #define DAC_C1_DACBFMD_MASK 0x6u
Kojto 90:cb3d968589d8 787 #define DAC_C1_DACBFMD_SHIFT 1
Kojto 90:cb3d968589d8 788 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
Kojto 90:cb3d968589d8 789 #define DAC_C1_DMAEN_MASK 0x80u
Kojto 90:cb3d968589d8 790 #define DAC_C1_DMAEN_SHIFT 7
Kojto 90:cb3d968589d8 791 /* C2 Bit Fields */
Kojto 90:cb3d968589d8 792 #define DAC_C2_DACBFUP_MASK 0x1u
Kojto 90:cb3d968589d8 793 #define DAC_C2_DACBFUP_SHIFT 0
Kojto 90:cb3d968589d8 794 #define DAC_C2_DACBFRP_MASK 0x10u
Kojto 90:cb3d968589d8 795 #define DAC_C2_DACBFRP_SHIFT 4
Kojto 90:cb3d968589d8 796
Kojto 90:cb3d968589d8 797 /*!
Kojto 90:cb3d968589d8 798 * @}
Kojto 90:cb3d968589d8 799 */ /* end of group DAC_Register_Masks */
Kojto 90:cb3d968589d8 800
Kojto 90:cb3d968589d8 801
Kojto 90:cb3d968589d8 802 /* DAC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 803 /** Peripheral DAC0 base address */
Kojto 90:cb3d968589d8 804 #define DAC0_BASE (0x4003F000u)
Kojto 90:cb3d968589d8 805 /** Peripheral DAC0 base pointer */
Kojto 90:cb3d968589d8 806 #define DAC0 ((DAC_Type *)DAC0_BASE)
Kojto 90:cb3d968589d8 807 #define DAC0_BASE_PTR (DAC0)
Kojto 90:cb3d968589d8 808 /** Array initializer of DAC peripheral base addresses */
Kojto 90:cb3d968589d8 809 #define DAC_BASE_ADDRS { DAC0_BASE }
Kojto 90:cb3d968589d8 810 /** Array initializer of DAC peripheral base pointers */
Kojto 90:cb3d968589d8 811 #define DAC_BASE_PTRS { DAC0 }
Kojto 90:cb3d968589d8 812 /** Interrupt vectors for the DAC peripheral type */
Kojto 90:cb3d968589d8 813 #define DAC_IRQS { DAC0_IRQn }
Kojto 90:cb3d968589d8 814
Kojto 90:cb3d968589d8 815 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 816 -- DAC - Register accessor macros
Kojto 90:cb3d968589d8 817 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 818
Kojto 90:cb3d968589d8 819 /*!
Kojto 90:cb3d968589d8 820 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
Kojto 90:cb3d968589d8 821 * @{
Kojto 90:cb3d968589d8 822 */
Kojto 90:cb3d968589d8 823
Kojto 90:cb3d968589d8 824
Kojto 90:cb3d968589d8 825 /* DAC - Register instance definitions */
Kojto 90:cb3d968589d8 826 /* DAC0 */
Kojto 90:cb3d968589d8 827 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
Kojto 90:cb3d968589d8 828 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
Kojto 90:cb3d968589d8 829 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
Kojto 90:cb3d968589d8 830 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
Kojto 90:cb3d968589d8 831 #define DAC0_SR DAC_SR_REG(DAC0)
Kojto 90:cb3d968589d8 832 #define DAC0_C0 DAC_C0_REG(DAC0)
Kojto 90:cb3d968589d8 833 #define DAC0_C1 DAC_C1_REG(DAC0)
Kojto 90:cb3d968589d8 834 #define DAC0_C2 DAC_C2_REG(DAC0)
Kojto 90:cb3d968589d8 835
Kojto 90:cb3d968589d8 836 /* DAC - Register array accessors */
Kojto 90:cb3d968589d8 837 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
Kojto 90:cb3d968589d8 838 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
Kojto 90:cb3d968589d8 839
Kojto 90:cb3d968589d8 840 /*!
Kojto 90:cb3d968589d8 841 * @}
Kojto 90:cb3d968589d8 842 */ /* end of group DAC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 843
Kojto 90:cb3d968589d8 844
Kojto 90:cb3d968589d8 845 /*!
Kojto 90:cb3d968589d8 846 * @}
Kojto 90:cb3d968589d8 847 */ /* end of group DAC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 848
Kojto 90:cb3d968589d8 849
Kojto 90:cb3d968589d8 850 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 851 -- DMA Peripheral Access Layer
Kojto 90:cb3d968589d8 852 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 853
Kojto 90:cb3d968589d8 854 /*!
Kojto 90:cb3d968589d8 855 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
Kojto 90:cb3d968589d8 856 * @{
Kojto 90:cb3d968589d8 857 */
Kojto 90:cb3d968589d8 858
Kojto 90:cb3d968589d8 859 /** DMA - Register Layout Typedef */
Kojto 90:cb3d968589d8 860 typedef struct {
Kojto 90:cb3d968589d8 861 uint8_t RESERVED_0[256];
Kojto 90:cb3d968589d8 862 struct { /* offset: 0x100, array step: 0x10 */
Kojto 90:cb3d968589d8 863 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
Kojto 90:cb3d968589d8 864 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
Kojto 90:cb3d968589d8 865 union { /* offset: 0x108, array step: 0x10 */
Kojto 90:cb3d968589d8 866 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
Kojto 90:cb3d968589d8 867 struct { /* offset: 0x108, array step: 0x10 */
Kojto 90:cb3d968589d8 868 uint8_t RESERVED_0[3];
Kojto 90:cb3d968589d8 869 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
Kojto 90:cb3d968589d8 870 } DMA_DSR_ACCESS8BIT;
Kojto 90:cb3d968589d8 871 };
Kojto 90:cb3d968589d8 872 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
Kojto 90:cb3d968589d8 873 } DMA[4];
Kojto 90:cb3d968589d8 874 } DMA_Type, *DMA_MemMapPtr;
Kojto 90:cb3d968589d8 875
Kojto 90:cb3d968589d8 876 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 877 -- DMA - Register accessor macros
Kojto 90:cb3d968589d8 878 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 879
Kojto 90:cb3d968589d8 880 /*!
Kojto 90:cb3d968589d8 881 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
Kojto 90:cb3d968589d8 882 * @{
Kojto 90:cb3d968589d8 883 */
Kojto 90:cb3d968589d8 884
Kojto 90:cb3d968589d8 885
Kojto 90:cb3d968589d8 886 /* DMA - Register accessors */
Kojto 90:cb3d968589d8 887 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
Kojto 90:cb3d968589d8 888 #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
Kojto 90:cb3d968589d8 889 #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
Kojto 90:cb3d968589d8 890 #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
Kojto 90:cb3d968589d8 891 #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
Kojto 90:cb3d968589d8 892
Kojto 90:cb3d968589d8 893 /*!
Kojto 90:cb3d968589d8 894 * @}
Kojto 90:cb3d968589d8 895 */ /* end of group DMA_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 896
Kojto 90:cb3d968589d8 897
Kojto 90:cb3d968589d8 898 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 899 -- DMA Register Masks
Kojto 90:cb3d968589d8 900 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 901
Kojto 90:cb3d968589d8 902 /*!
Kojto 90:cb3d968589d8 903 * @addtogroup DMA_Register_Masks DMA Register Masks
Kojto 90:cb3d968589d8 904 * @{
Kojto 90:cb3d968589d8 905 */
Kojto 90:cb3d968589d8 906
Kojto 90:cb3d968589d8 907 /* SAR Bit Fields */
Kojto 90:cb3d968589d8 908 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 909 #define DMA_SAR_SAR_SHIFT 0
Kojto 90:cb3d968589d8 910 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
Kojto 90:cb3d968589d8 911 /* DAR Bit Fields */
Kojto 90:cb3d968589d8 912 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 913 #define DMA_DAR_DAR_SHIFT 0
Kojto 90:cb3d968589d8 914 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
Kojto 90:cb3d968589d8 915 /* DSR_BCR Bit Fields */
Kojto 90:cb3d968589d8 916 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
Kojto 90:cb3d968589d8 917 #define DMA_DSR_BCR_BCR_SHIFT 0
Kojto 90:cb3d968589d8 918 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
Kojto 90:cb3d968589d8 919 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
Kojto 90:cb3d968589d8 920 #define DMA_DSR_BCR_DONE_SHIFT 24
Kojto 90:cb3d968589d8 921 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
Kojto 90:cb3d968589d8 922 #define DMA_DSR_BCR_BSY_SHIFT 25
Kojto 90:cb3d968589d8 923 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
Kojto 90:cb3d968589d8 924 #define DMA_DSR_BCR_REQ_SHIFT 26
Kojto 90:cb3d968589d8 925 #define DMA_DSR_BCR_BED_MASK 0x10000000u
Kojto 90:cb3d968589d8 926 #define DMA_DSR_BCR_BED_SHIFT 28
Kojto 90:cb3d968589d8 927 #define DMA_DSR_BCR_BES_MASK 0x20000000u
Kojto 90:cb3d968589d8 928 #define DMA_DSR_BCR_BES_SHIFT 29
Kojto 90:cb3d968589d8 929 #define DMA_DSR_BCR_CE_MASK 0x40000000u
Kojto 90:cb3d968589d8 930 #define DMA_DSR_BCR_CE_SHIFT 30
Kojto 90:cb3d968589d8 931 /* DCR Bit Fields */
Kojto 90:cb3d968589d8 932 #define DMA_DCR_LCH2_MASK 0x3u
Kojto 90:cb3d968589d8 933 #define DMA_DCR_LCH2_SHIFT 0
Kojto 90:cb3d968589d8 934 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
Kojto 90:cb3d968589d8 935 #define DMA_DCR_LCH1_MASK 0xCu
Kojto 90:cb3d968589d8 936 #define DMA_DCR_LCH1_SHIFT 2
Kojto 90:cb3d968589d8 937 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
Kojto 90:cb3d968589d8 938 #define DMA_DCR_LINKCC_MASK 0x30u
Kojto 90:cb3d968589d8 939 #define DMA_DCR_LINKCC_SHIFT 4
Kojto 90:cb3d968589d8 940 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
Kojto 90:cb3d968589d8 941 #define DMA_DCR_D_REQ_MASK 0x80u
Kojto 90:cb3d968589d8 942 #define DMA_DCR_D_REQ_SHIFT 7
Kojto 90:cb3d968589d8 943 #define DMA_DCR_DMOD_MASK 0xF00u
Kojto 90:cb3d968589d8 944 #define DMA_DCR_DMOD_SHIFT 8
Kojto 90:cb3d968589d8 945 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
Kojto 90:cb3d968589d8 946 #define DMA_DCR_SMOD_MASK 0xF000u
Kojto 90:cb3d968589d8 947 #define DMA_DCR_SMOD_SHIFT 12
Kojto 90:cb3d968589d8 948 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
Kojto 90:cb3d968589d8 949 #define DMA_DCR_START_MASK 0x10000u
Kojto 90:cb3d968589d8 950 #define DMA_DCR_START_SHIFT 16
Kojto 90:cb3d968589d8 951 #define DMA_DCR_DSIZE_MASK 0x60000u
Kojto 90:cb3d968589d8 952 #define DMA_DCR_DSIZE_SHIFT 17
Kojto 90:cb3d968589d8 953 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
Kojto 90:cb3d968589d8 954 #define DMA_DCR_DINC_MASK 0x80000u
Kojto 90:cb3d968589d8 955 #define DMA_DCR_DINC_SHIFT 19
Kojto 90:cb3d968589d8 956 #define DMA_DCR_SSIZE_MASK 0x300000u
Kojto 90:cb3d968589d8 957 #define DMA_DCR_SSIZE_SHIFT 20
Kojto 90:cb3d968589d8 958 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
Kojto 90:cb3d968589d8 959 #define DMA_DCR_SINC_MASK 0x400000u
Kojto 90:cb3d968589d8 960 #define DMA_DCR_SINC_SHIFT 22
Kojto 90:cb3d968589d8 961 #define DMA_DCR_EADREQ_MASK 0x800000u
Kojto 90:cb3d968589d8 962 #define DMA_DCR_EADREQ_SHIFT 23
Kojto 90:cb3d968589d8 963 #define DMA_DCR_AA_MASK 0x10000000u
Kojto 90:cb3d968589d8 964 #define DMA_DCR_AA_SHIFT 28
Kojto 90:cb3d968589d8 965 #define DMA_DCR_CS_MASK 0x20000000u
Kojto 90:cb3d968589d8 966 #define DMA_DCR_CS_SHIFT 29
Kojto 90:cb3d968589d8 967 #define DMA_DCR_ERQ_MASK 0x40000000u
Kojto 90:cb3d968589d8 968 #define DMA_DCR_ERQ_SHIFT 30
Kojto 90:cb3d968589d8 969 #define DMA_DCR_EINT_MASK 0x80000000u
Kojto 90:cb3d968589d8 970 #define DMA_DCR_EINT_SHIFT 31
Kojto 90:cb3d968589d8 971
Kojto 90:cb3d968589d8 972 /*!
Kojto 90:cb3d968589d8 973 * @}
Kojto 90:cb3d968589d8 974 */ /* end of group DMA_Register_Masks */
Kojto 90:cb3d968589d8 975
Kojto 90:cb3d968589d8 976
Kojto 90:cb3d968589d8 977 /* DMA - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 978 /** Peripheral DMA base address */
Kojto 90:cb3d968589d8 979 #define DMA_BASE (0x40008000u)
Kojto 90:cb3d968589d8 980 /** Peripheral DMA base pointer */
Kojto 90:cb3d968589d8 981 #define DMA0 ((DMA_Type *)DMA_BASE)
Kojto 90:cb3d968589d8 982 #define DMA_BASE_PTR (DMA0)
Kojto 90:cb3d968589d8 983 /** Array initializer of DMA peripheral base addresses */
Kojto 90:cb3d968589d8 984 #define DMA_BASE_ADDRS { DMA_BASE }
Kojto 90:cb3d968589d8 985 /** Array initializer of DMA peripheral base pointers */
Kojto 90:cb3d968589d8 986 #define DMA_BASE_PTRS { DMA0 }
Kojto 90:cb3d968589d8 987 /** Interrupt vectors for the DMA peripheral type */
Kojto 90:cb3d968589d8 988 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
Kojto 90:cb3d968589d8 989
Kojto 90:cb3d968589d8 990 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 991 -- DMA - Register accessor macros
Kojto 90:cb3d968589d8 992 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 993
Kojto 90:cb3d968589d8 994 /*!
Kojto 90:cb3d968589d8 995 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
Kojto 90:cb3d968589d8 996 * @{
Kojto 90:cb3d968589d8 997 */
Kojto 90:cb3d968589d8 998
Kojto 90:cb3d968589d8 999
Kojto 90:cb3d968589d8 1000 /* DMA - Register instance definitions */
Kojto 90:cb3d968589d8 1001 /* DMA */
Kojto 90:cb3d968589d8 1002 #define DMA_SAR0 DMA_SAR_REG(DMA0,0)
Kojto 90:cb3d968589d8 1003 #define DMA_DAR0 DMA_DAR_REG(DMA0,0)
Kojto 90:cb3d968589d8 1004 #define DMA_DSR_BCR0 DMA_DSR_BCR_REG(DMA0,0)
Kojto 90:cb3d968589d8 1005 #define DMA_DSR0 DMA_DSR_REG(DMA0,0)
Kojto 90:cb3d968589d8 1006 #define DMA_DCR0 DMA_DCR_REG(DMA0,0)
Kojto 90:cb3d968589d8 1007 #define DMA_SAR1 DMA_SAR_REG(DMA0,1)
Kojto 90:cb3d968589d8 1008 #define DMA_DAR1 DMA_DAR_REG(DMA0,1)
Kojto 90:cb3d968589d8 1009 #define DMA_DSR_BCR1 DMA_DSR_BCR_REG(DMA0,1)
Kojto 90:cb3d968589d8 1010 #define DMA_DSR1 DMA_DSR_REG(DMA0,1)
Kojto 90:cb3d968589d8 1011 #define DMA_DCR1 DMA_DCR_REG(DMA0,1)
Kojto 90:cb3d968589d8 1012 #define DMA_SAR2 DMA_SAR_REG(DMA0,2)
Kojto 90:cb3d968589d8 1013 #define DMA_DAR2 DMA_DAR_REG(DMA0,2)
Kojto 90:cb3d968589d8 1014 #define DMA_DSR_BCR2 DMA_DSR_BCR_REG(DMA0,2)
Kojto 90:cb3d968589d8 1015 #define DMA_DSR2 DMA_DSR_REG(DMA0,2)
Kojto 90:cb3d968589d8 1016 #define DMA_DCR2 DMA_DCR_REG(DMA0,2)
Kojto 90:cb3d968589d8 1017 #define DMA_SAR3 DMA_SAR_REG(DMA0,3)
Kojto 90:cb3d968589d8 1018 #define DMA_DAR3 DMA_DAR_REG(DMA0,3)
Kojto 90:cb3d968589d8 1019 #define DMA_DSR_BCR3 DMA_DSR_BCR_REG(DMA0,3)
Kojto 90:cb3d968589d8 1020 #define DMA_DSR3 DMA_DSR_REG(DMA0,3)
Kojto 90:cb3d968589d8 1021 #define DMA_DCR3 DMA_DCR_REG(DMA0,3)
Kojto 90:cb3d968589d8 1022
Kojto 90:cb3d968589d8 1023 /* DMA - Register array accessors */
Kojto 90:cb3d968589d8 1024 #define DMA_SAR(index) DMA_SAR_REG(DMA0,index)
Kojto 90:cb3d968589d8 1025 #define DMA_DAR(index) DMA_DAR_REG(DMA0,index)
Kojto 90:cb3d968589d8 1026 #define DMA_DSR_BCR(index) DMA_DSR_BCR_REG(DMA0,index)
Kojto 90:cb3d968589d8 1027 #define DMA_DSR(index) DMA_DSR_REG(DMA0,index)
Kojto 90:cb3d968589d8 1028 #define DMA_DCR(index) DMA_DCR_REG(DMA0,index)
Kojto 90:cb3d968589d8 1029
Kojto 90:cb3d968589d8 1030 /*!
Kojto 90:cb3d968589d8 1031 * @}
Kojto 90:cb3d968589d8 1032 */ /* end of group DMA_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1033
Kojto 90:cb3d968589d8 1034
Kojto 90:cb3d968589d8 1035 /*!
Kojto 90:cb3d968589d8 1036 * @}
Kojto 90:cb3d968589d8 1037 */ /* end of group DMA_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 1038
Kojto 90:cb3d968589d8 1039
Kojto 90:cb3d968589d8 1040 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1041 -- DMAMUX Peripheral Access Layer
Kojto 90:cb3d968589d8 1042 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1043
Kojto 90:cb3d968589d8 1044 /*!
Kojto 90:cb3d968589d8 1045 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
Kojto 90:cb3d968589d8 1046 * @{
Kojto 90:cb3d968589d8 1047 */
Kojto 90:cb3d968589d8 1048
Kojto 90:cb3d968589d8 1049 /** DMAMUX - Register Layout Typedef */
Kojto 90:cb3d968589d8 1050 typedef struct {
Kojto 90:cb3d968589d8 1051 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
Kojto 90:cb3d968589d8 1052 } DMAMUX_Type, *DMAMUX_MemMapPtr;
Kojto 90:cb3d968589d8 1053
Kojto 90:cb3d968589d8 1054 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1055 -- DMAMUX - Register accessor macros
Kojto 90:cb3d968589d8 1056 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1057
Kojto 90:cb3d968589d8 1058 /*!
Kojto 90:cb3d968589d8 1059 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
Kojto 90:cb3d968589d8 1060 * @{
Kojto 90:cb3d968589d8 1061 */
Kojto 90:cb3d968589d8 1062
Kojto 90:cb3d968589d8 1063
Kojto 90:cb3d968589d8 1064 /* DMAMUX - Register accessors */
Kojto 90:cb3d968589d8 1065 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
Kojto 90:cb3d968589d8 1066
Kojto 90:cb3d968589d8 1067 /*!
Kojto 90:cb3d968589d8 1068 * @}
Kojto 90:cb3d968589d8 1069 */ /* end of group DMAMUX_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1070
Kojto 90:cb3d968589d8 1071
Kojto 90:cb3d968589d8 1072 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1073 -- DMAMUX Register Masks
Kojto 90:cb3d968589d8 1074 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1075
Kojto 90:cb3d968589d8 1076 /*!
Kojto 90:cb3d968589d8 1077 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
Kojto 90:cb3d968589d8 1078 * @{
Kojto 90:cb3d968589d8 1079 */
Kojto 90:cb3d968589d8 1080
Kojto 90:cb3d968589d8 1081 /* CHCFG Bit Fields */
Kojto 90:cb3d968589d8 1082 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
Kojto 90:cb3d968589d8 1083 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
Kojto 90:cb3d968589d8 1084 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
Kojto 90:cb3d968589d8 1085 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
Kojto 90:cb3d968589d8 1086 #define DMAMUX_CHCFG_TRIG_SHIFT 6
Kojto 90:cb3d968589d8 1087 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
Kojto 90:cb3d968589d8 1088 #define DMAMUX_CHCFG_ENBL_SHIFT 7
Kojto 90:cb3d968589d8 1089
Kojto 90:cb3d968589d8 1090 /*!
Kojto 90:cb3d968589d8 1091 * @}
Kojto 90:cb3d968589d8 1092 */ /* end of group DMAMUX_Register_Masks */
Kojto 90:cb3d968589d8 1093
Kojto 90:cb3d968589d8 1094
Kojto 90:cb3d968589d8 1095 /* DMAMUX - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 1096 /** Peripheral DMAMUX0 base address */
Kojto 90:cb3d968589d8 1097 #define DMAMUX0_BASE (0x40021000u)
Kojto 90:cb3d968589d8 1098 /** Peripheral DMAMUX0 base pointer */
Kojto 90:cb3d968589d8 1099 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
Kojto 90:cb3d968589d8 1100 #define DMAMUX0_BASE_PTR (DMAMUX0)
Kojto 90:cb3d968589d8 1101 /** Array initializer of DMAMUX peripheral base addresses */
Kojto 90:cb3d968589d8 1102 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
Kojto 90:cb3d968589d8 1103 /** Array initializer of DMAMUX peripheral base pointers */
Kojto 90:cb3d968589d8 1104 #define DMAMUX_BASE_PTRS { DMAMUX0 }
Kojto 90:cb3d968589d8 1105
Kojto 90:cb3d968589d8 1106 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1107 -- DMAMUX - Register accessor macros
Kojto 90:cb3d968589d8 1108 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1109
Kojto 90:cb3d968589d8 1110 /*!
Kojto 90:cb3d968589d8 1111 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
Kojto 90:cb3d968589d8 1112 * @{
Kojto 90:cb3d968589d8 1113 */
Kojto 90:cb3d968589d8 1114
Kojto 90:cb3d968589d8 1115
Kojto 90:cb3d968589d8 1116 /* DMAMUX - Register instance definitions */
Kojto 90:cb3d968589d8 1117 /* DMAMUX0 */
Kojto 90:cb3d968589d8 1118 #define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0,0)
Kojto 90:cb3d968589d8 1119 #define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0,1)
Kojto 90:cb3d968589d8 1120 #define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0,2)
Kojto 90:cb3d968589d8 1121 #define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0,3)
Kojto 90:cb3d968589d8 1122
Kojto 90:cb3d968589d8 1123 /* DMAMUX - Register array accessors */
Kojto 90:cb3d968589d8 1124 #define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0,index)
Kojto 90:cb3d968589d8 1125
Kojto 90:cb3d968589d8 1126 /*!
Kojto 90:cb3d968589d8 1127 * @}
Kojto 90:cb3d968589d8 1128 */ /* end of group DMAMUX_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1129
Kojto 90:cb3d968589d8 1130
Kojto 90:cb3d968589d8 1131 /*!
Kojto 90:cb3d968589d8 1132 * @}
Kojto 90:cb3d968589d8 1133 */ /* end of group DMAMUX_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 1134
Kojto 90:cb3d968589d8 1135
Kojto 90:cb3d968589d8 1136 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1137 -- FLEXIO Peripheral Access Layer
Kojto 90:cb3d968589d8 1138 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1139
Kojto 90:cb3d968589d8 1140 /*!
Kojto 90:cb3d968589d8 1141 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
Kojto 90:cb3d968589d8 1142 * @{
Kojto 90:cb3d968589d8 1143 */
Kojto 90:cb3d968589d8 1144
Kojto 90:cb3d968589d8 1145 /** FLEXIO - Register Layout Typedef */
Kojto 90:cb3d968589d8 1146 typedef struct {
Kojto 90:cb3d968589d8 1147 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
Kojto 90:cb3d968589d8 1148 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
Kojto 90:cb3d968589d8 1149 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
Kojto 90:cb3d968589d8 1150 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 1151 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
Kojto 90:cb3d968589d8 1152 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
Kojto 90:cb3d968589d8 1153 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
Kojto 90:cb3d968589d8 1154 uint8_t RESERVED_1[4];
Kojto 90:cb3d968589d8 1155 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
Kojto 90:cb3d968589d8 1156 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
Kojto 90:cb3d968589d8 1157 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
Kojto 90:cb3d968589d8 1158 uint8_t RESERVED_2[4];
Kojto 90:cb3d968589d8 1159 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
Kojto 90:cb3d968589d8 1160 uint8_t RESERVED_3[76];
Kojto 90:cb3d968589d8 1161 __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
Kojto 90:cb3d968589d8 1162 uint8_t RESERVED_4[112];
Kojto 90:cb3d968589d8 1163 __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
Kojto 90:cb3d968589d8 1164 uint8_t RESERVED_5[240];
Kojto 90:cb3d968589d8 1165 __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
Kojto 90:cb3d968589d8 1166 uint8_t RESERVED_6[112];
Kojto 90:cb3d968589d8 1167 __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x280, array step: 0x4 */
Kojto 90:cb3d968589d8 1168 uint8_t RESERVED_7[112];
Kojto 90:cb3d968589d8 1169 __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
Kojto 90:cb3d968589d8 1170 uint8_t RESERVED_8[112];
Kojto 90:cb3d968589d8 1171 __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x380, array step: 0x4 */
Kojto 90:cb3d968589d8 1172 uint8_t RESERVED_9[112];
Kojto 90:cb3d968589d8 1173 __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
Kojto 90:cb3d968589d8 1174 uint8_t RESERVED_10[112];
Kojto 90:cb3d968589d8 1175 __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
Kojto 90:cb3d968589d8 1176 uint8_t RESERVED_11[112];
Kojto 90:cb3d968589d8 1177 __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
Kojto 90:cb3d968589d8 1178 } FLEXIO_Type, *FLEXIO_MemMapPtr;
Kojto 90:cb3d968589d8 1179
Kojto 90:cb3d968589d8 1180 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1181 -- FLEXIO - Register accessor macros
Kojto 90:cb3d968589d8 1182 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1183
Kojto 90:cb3d968589d8 1184 /*!
Kojto 90:cb3d968589d8 1185 * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
Kojto 90:cb3d968589d8 1186 * @{
Kojto 90:cb3d968589d8 1187 */
Kojto 90:cb3d968589d8 1188
Kojto 90:cb3d968589d8 1189
Kojto 90:cb3d968589d8 1190 /* FLEXIO - Register accessors */
Kojto 90:cb3d968589d8 1191 #define FLEXIO_VERID_REG(base) ((base)->VERID)
Kojto 90:cb3d968589d8 1192 #define FLEXIO_PARAM_REG(base) ((base)->PARAM)
Kojto 90:cb3d968589d8 1193 #define FLEXIO_CTRL_REG(base) ((base)->CTRL)
Kojto 90:cb3d968589d8 1194 #define FLEXIO_SHIFTSTAT_REG(base) ((base)->SHIFTSTAT)
Kojto 90:cb3d968589d8 1195 #define FLEXIO_SHIFTERR_REG(base) ((base)->SHIFTERR)
Kojto 90:cb3d968589d8 1196 #define FLEXIO_TIMSTAT_REG(base) ((base)->TIMSTAT)
Kojto 90:cb3d968589d8 1197 #define FLEXIO_SHIFTSIEN_REG(base) ((base)->SHIFTSIEN)
Kojto 90:cb3d968589d8 1198 #define FLEXIO_SHIFTEIEN_REG(base) ((base)->SHIFTEIEN)
Kojto 90:cb3d968589d8 1199 #define FLEXIO_TIMIEN_REG(base) ((base)->TIMIEN)
Kojto 90:cb3d968589d8 1200 #define FLEXIO_SHIFTSDEN_REG(base) ((base)->SHIFTSDEN)
Kojto 90:cb3d968589d8 1201 #define FLEXIO_SHIFTCTL_REG(base,index) ((base)->SHIFTCTL[index])
Kojto 90:cb3d968589d8 1202 #define FLEXIO_SHIFTCFG_REG(base,index) ((base)->SHIFTCFG[index])
Kojto 90:cb3d968589d8 1203 #define FLEXIO_SHIFTBUF_REG(base,index) ((base)->SHIFTBUF[index])
Kojto 90:cb3d968589d8 1204 #define FLEXIO_SHIFTBUFBBS_REG(base,index) ((base)->SHIFTBUFBBS[index])
Kojto 90:cb3d968589d8 1205 #define FLEXIO_SHIFTBUFBYS_REG(base,index) ((base)->SHIFTBUFBYS[index])
Kojto 90:cb3d968589d8 1206 #define FLEXIO_SHIFTBUFBIS_REG(base,index) ((base)->SHIFTBUFBIS[index])
Kojto 90:cb3d968589d8 1207 #define FLEXIO_TIMCTL_REG(base,index) ((base)->TIMCTL[index])
Kojto 90:cb3d968589d8 1208 #define FLEXIO_TIMCFG_REG(base,index) ((base)->TIMCFG[index])
Kojto 90:cb3d968589d8 1209 #define FLEXIO_TIMCMP_REG(base,index) ((base)->TIMCMP[index])
Kojto 90:cb3d968589d8 1210
Kojto 90:cb3d968589d8 1211 /*!
Kojto 90:cb3d968589d8 1212 * @}
Kojto 90:cb3d968589d8 1213 */ /* end of group FLEXIO_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1214
Kojto 90:cb3d968589d8 1215
Kojto 90:cb3d968589d8 1216 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1217 -- FLEXIO Register Masks
Kojto 90:cb3d968589d8 1218 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1219
Kojto 90:cb3d968589d8 1220 /*!
Kojto 90:cb3d968589d8 1221 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
Kojto 90:cb3d968589d8 1222 * @{
Kojto 90:cb3d968589d8 1223 */
Kojto 90:cb3d968589d8 1224
Kojto 90:cb3d968589d8 1225 /* VERID Bit Fields */
Kojto 90:cb3d968589d8 1226 #define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
Kojto 90:cb3d968589d8 1227 #define FLEXIO_VERID_FEATURE_SHIFT 0
Kojto 90:cb3d968589d8 1228 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
Kojto 90:cb3d968589d8 1229 #define FLEXIO_VERID_MINOR_MASK 0xFF0000u
Kojto 90:cb3d968589d8 1230 #define FLEXIO_VERID_MINOR_SHIFT 16
Kojto 90:cb3d968589d8 1231 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
Kojto 90:cb3d968589d8 1232 #define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
Kojto 90:cb3d968589d8 1233 #define FLEXIO_VERID_MAJOR_SHIFT 24
Kojto 90:cb3d968589d8 1234 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
Kojto 90:cb3d968589d8 1235 /* PARAM Bit Fields */
Kojto 90:cb3d968589d8 1236 #define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
Kojto 90:cb3d968589d8 1237 #define FLEXIO_PARAM_SHIFTER_SHIFT 0
Kojto 90:cb3d968589d8 1238 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
Kojto 90:cb3d968589d8 1239 #define FLEXIO_PARAM_TIMER_MASK 0xFF00u
Kojto 90:cb3d968589d8 1240 #define FLEXIO_PARAM_TIMER_SHIFT 8
Kojto 90:cb3d968589d8 1241 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
Kojto 90:cb3d968589d8 1242 #define FLEXIO_PARAM_PIN_MASK 0xFF0000u
Kojto 90:cb3d968589d8 1243 #define FLEXIO_PARAM_PIN_SHIFT 16
Kojto 90:cb3d968589d8 1244 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
Kojto 90:cb3d968589d8 1245 #define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
Kojto 90:cb3d968589d8 1246 #define FLEXIO_PARAM_TRIGGER_SHIFT 24
Kojto 90:cb3d968589d8 1247 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
Kojto 90:cb3d968589d8 1248 /* CTRL Bit Fields */
Kojto 90:cb3d968589d8 1249 #define FLEXIO_CTRL_FLEXEN_MASK 0x1u
Kojto 90:cb3d968589d8 1250 #define FLEXIO_CTRL_FLEXEN_SHIFT 0
Kojto 90:cb3d968589d8 1251 #define FLEXIO_CTRL_SWRST_MASK 0x2u
Kojto 90:cb3d968589d8 1252 #define FLEXIO_CTRL_SWRST_SHIFT 1
Kojto 90:cb3d968589d8 1253 #define FLEXIO_CTRL_FASTACC_MASK 0x4u
Kojto 90:cb3d968589d8 1254 #define FLEXIO_CTRL_FASTACC_SHIFT 2
Kojto 90:cb3d968589d8 1255 #define FLEXIO_CTRL_DBGE_MASK 0x40000000u
Kojto 90:cb3d968589d8 1256 #define FLEXIO_CTRL_DBGE_SHIFT 30
Kojto 90:cb3d968589d8 1257 #define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
Kojto 90:cb3d968589d8 1258 #define FLEXIO_CTRL_DOZEN_SHIFT 31
Kojto 90:cb3d968589d8 1259 /* SHIFTSTAT Bit Fields */
Kojto 90:cb3d968589d8 1260 #define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
Kojto 90:cb3d968589d8 1261 #define FLEXIO_SHIFTSTAT_SSF_SHIFT 0
Kojto 90:cb3d968589d8 1262 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
Kojto 90:cb3d968589d8 1263 /* SHIFTERR Bit Fields */
Kojto 90:cb3d968589d8 1264 #define FLEXIO_SHIFTERR_SEF_MASK 0xFu
Kojto 90:cb3d968589d8 1265 #define FLEXIO_SHIFTERR_SEF_SHIFT 0
Kojto 90:cb3d968589d8 1266 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
Kojto 90:cb3d968589d8 1267 /* TIMSTAT Bit Fields */
Kojto 90:cb3d968589d8 1268 #define FLEXIO_TIMSTAT_TSF_MASK 0xFu
Kojto 90:cb3d968589d8 1269 #define FLEXIO_TIMSTAT_TSF_SHIFT 0
Kojto 90:cb3d968589d8 1270 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
Kojto 90:cb3d968589d8 1271 /* SHIFTSIEN Bit Fields */
Kojto 90:cb3d968589d8 1272 #define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
Kojto 90:cb3d968589d8 1273 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0
Kojto 90:cb3d968589d8 1274 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
Kojto 90:cb3d968589d8 1275 /* SHIFTEIEN Bit Fields */
Kojto 90:cb3d968589d8 1276 #define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
Kojto 90:cb3d968589d8 1277 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0
Kojto 90:cb3d968589d8 1278 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
Kojto 90:cb3d968589d8 1279 /* TIMIEN Bit Fields */
Kojto 90:cb3d968589d8 1280 #define FLEXIO_TIMIEN_TEIE_MASK 0xFu
Kojto 90:cb3d968589d8 1281 #define FLEXIO_TIMIEN_TEIE_SHIFT 0
Kojto 90:cb3d968589d8 1282 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
Kojto 90:cb3d968589d8 1283 /* SHIFTSDEN Bit Fields */
Kojto 90:cb3d968589d8 1284 #define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
Kojto 90:cb3d968589d8 1285 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0
Kojto 90:cb3d968589d8 1286 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
Kojto 90:cb3d968589d8 1287 /* SHIFTCTL Bit Fields */
Kojto 90:cb3d968589d8 1288 #define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
Kojto 90:cb3d968589d8 1289 #define FLEXIO_SHIFTCTL_SMOD_SHIFT 0
Kojto 90:cb3d968589d8 1290 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
Kojto 90:cb3d968589d8 1291 #define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
Kojto 90:cb3d968589d8 1292 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7
Kojto 90:cb3d968589d8 1293 #define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
Kojto 90:cb3d968589d8 1294 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8
Kojto 90:cb3d968589d8 1295 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
Kojto 90:cb3d968589d8 1296 #define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
Kojto 90:cb3d968589d8 1297 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16
Kojto 90:cb3d968589d8 1298 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
Kojto 90:cb3d968589d8 1299 #define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
Kojto 90:cb3d968589d8 1300 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23
Kojto 90:cb3d968589d8 1301 #define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
Kojto 90:cb3d968589d8 1302 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24
Kojto 90:cb3d968589d8 1303 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
Kojto 90:cb3d968589d8 1304 /* SHIFTCFG Bit Fields */
Kojto 90:cb3d968589d8 1305 #define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
Kojto 90:cb3d968589d8 1306 #define FLEXIO_SHIFTCFG_SSTART_SHIFT 0
Kojto 90:cb3d968589d8 1307 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
Kojto 90:cb3d968589d8 1308 #define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
Kojto 90:cb3d968589d8 1309 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4
Kojto 90:cb3d968589d8 1310 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
Kojto 90:cb3d968589d8 1311 #define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
Kojto 90:cb3d968589d8 1312 #define FLEXIO_SHIFTCFG_INSRC_SHIFT 8
Kojto 90:cb3d968589d8 1313 /* SHIFTBUF Bit Fields */
Kojto 90:cb3d968589d8 1314 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 1315 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0
Kojto 90:cb3d968589d8 1316 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
Kojto 90:cb3d968589d8 1317 /* SHIFTBUFBBS Bit Fields */
Kojto 90:cb3d968589d8 1318 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 1319 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0
Kojto 90:cb3d968589d8 1320 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
Kojto 90:cb3d968589d8 1321 /* SHIFTBUFBYS Bit Fields */
Kojto 90:cb3d968589d8 1322 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 1323 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0
Kojto 90:cb3d968589d8 1324 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
Kojto 90:cb3d968589d8 1325 /* SHIFTBUFBIS Bit Fields */
Kojto 90:cb3d968589d8 1326 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 1327 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0
Kojto 90:cb3d968589d8 1328 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
Kojto 90:cb3d968589d8 1329 /* TIMCTL Bit Fields */
Kojto 90:cb3d968589d8 1330 #define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
Kojto 90:cb3d968589d8 1331 #define FLEXIO_TIMCTL_TIMOD_SHIFT 0
Kojto 90:cb3d968589d8 1332 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
Kojto 90:cb3d968589d8 1333 #define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
Kojto 90:cb3d968589d8 1334 #define FLEXIO_TIMCTL_PINPOL_SHIFT 7
Kojto 90:cb3d968589d8 1335 #define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
Kojto 90:cb3d968589d8 1336 #define FLEXIO_TIMCTL_PINSEL_SHIFT 8
Kojto 90:cb3d968589d8 1337 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
Kojto 90:cb3d968589d8 1338 #define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
Kojto 90:cb3d968589d8 1339 #define FLEXIO_TIMCTL_PINCFG_SHIFT 16
Kojto 90:cb3d968589d8 1340 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
Kojto 90:cb3d968589d8 1341 #define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
Kojto 90:cb3d968589d8 1342 #define FLEXIO_TIMCTL_TRGSRC_SHIFT 22
Kojto 90:cb3d968589d8 1343 #define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
Kojto 90:cb3d968589d8 1344 #define FLEXIO_TIMCTL_TRGPOL_SHIFT 23
Kojto 90:cb3d968589d8 1345 #define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
Kojto 90:cb3d968589d8 1346 #define FLEXIO_TIMCTL_TRGSEL_SHIFT 24
Kojto 90:cb3d968589d8 1347 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
Kojto 90:cb3d968589d8 1348 /* TIMCFG Bit Fields */
Kojto 90:cb3d968589d8 1349 #define FLEXIO_TIMCFG_TSTART_MASK 0x2u
Kojto 90:cb3d968589d8 1350 #define FLEXIO_TIMCFG_TSTART_SHIFT 1
Kojto 90:cb3d968589d8 1351 #define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
Kojto 90:cb3d968589d8 1352 #define FLEXIO_TIMCFG_TSTOP_SHIFT 4
Kojto 90:cb3d968589d8 1353 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
Kojto 90:cb3d968589d8 1354 #define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
Kojto 90:cb3d968589d8 1355 #define FLEXIO_TIMCFG_TIMENA_SHIFT 8
Kojto 90:cb3d968589d8 1356 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
Kojto 90:cb3d968589d8 1357 #define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
Kojto 90:cb3d968589d8 1358 #define FLEXIO_TIMCFG_TIMDIS_SHIFT 12
Kojto 90:cb3d968589d8 1359 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
Kojto 90:cb3d968589d8 1360 #define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
Kojto 90:cb3d968589d8 1361 #define FLEXIO_TIMCFG_TIMRST_SHIFT 16
Kojto 90:cb3d968589d8 1362 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
Kojto 90:cb3d968589d8 1363 #define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
Kojto 90:cb3d968589d8 1364 #define FLEXIO_TIMCFG_TIMDEC_SHIFT 20
Kojto 90:cb3d968589d8 1365 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
Kojto 90:cb3d968589d8 1366 #define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
Kojto 90:cb3d968589d8 1367 #define FLEXIO_TIMCFG_TIMOUT_SHIFT 24
Kojto 90:cb3d968589d8 1368 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
Kojto 90:cb3d968589d8 1369 /* TIMCMP Bit Fields */
Kojto 90:cb3d968589d8 1370 #define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
Kojto 90:cb3d968589d8 1371 #define FLEXIO_TIMCMP_CMP_SHIFT 0
Kojto 90:cb3d968589d8 1372 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
Kojto 90:cb3d968589d8 1373
Kojto 90:cb3d968589d8 1374 /*!
Kojto 90:cb3d968589d8 1375 * @}
Kojto 90:cb3d968589d8 1376 */ /* end of group FLEXIO_Register_Masks */
Kojto 90:cb3d968589d8 1377
Kojto 90:cb3d968589d8 1378
Kojto 90:cb3d968589d8 1379 /* FLEXIO - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 1380 /** Peripheral FLEXIO base address */
Kojto 90:cb3d968589d8 1381 #define FLEXIO_BASE (0x4005F000u)
Kojto 90:cb3d968589d8 1382 /** Peripheral FLEXIO base pointer */
Kojto 90:cb3d968589d8 1383 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
Kojto 90:cb3d968589d8 1384 #define FLEXIO_BASE_PTR (FLEXIO)
Kojto 90:cb3d968589d8 1385 /** Array initializer of FLEXIO peripheral base addresses */
Kojto 90:cb3d968589d8 1386 #define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
Kojto 90:cb3d968589d8 1387 /** Array initializer of FLEXIO peripheral base pointers */
Kojto 90:cb3d968589d8 1388 #define FLEXIO_BASE_PTRS { FLEXIO }
Kojto 90:cb3d968589d8 1389
Kojto 90:cb3d968589d8 1390 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1391 -- FLEXIO - Register accessor macros
Kojto 90:cb3d968589d8 1392 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1393
Kojto 90:cb3d968589d8 1394 /*!
Kojto 90:cb3d968589d8 1395 * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
Kojto 90:cb3d968589d8 1396 * @{
Kojto 90:cb3d968589d8 1397 */
Kojto 90:cb3d968589d8 1398
Kojto 90:cb3d968589d8 1399
Kojto 90:cb3d968589d8 1400 /* FLEXIO - Register instance definitions */
Kojto 90:cb3d968589d8 1401 /* FLEXIO */
Kojto 90:cb3d968589d8 1402 #define FLEXIO_VERID FLEXIO_VERID_REG(FLEXIO)
Kojto 90:cb3d968589d8 1403 #define FLEXIO_PARAM FLEXIO_PARAM_REG(FLEXIO)
Kojto 90:cb3d968589d8 1404 #define FLEXIO_CTRL FLEXIO_CTRL_REG(FLEXIO)
Kojto 90:cb3d968589d8 1405 #define FLEXIO_SHIFTSTAT FLEXIO_SHIFTSTAT_REG(FLEXIO)
Kojto 90:cb3d968589d8 1406 #define FLEXIO_SHIFTERR FLEXIO_SHIFTERR_REG(FLEXIO)
Kojto 90:cb3d968589d8 1407 #define FLEXIO_TIMSTAT FLEXIO_TIMSTAT_REG(FLEXIO)
Kojto 90:cb3d968589d8 1408 #define FLEXIO_SHIFTSIEN FLEXIO_SHIFTSIEN_REG(FLEXIO)
Kojto 90:cb3d968589d8 1409 #define FLEXIO_SHIFTEIEN FLEXIO_SHIFTEIEN_REG(FLEXIO)
Kojto 90:cb3d968589d8 1410 #define FLEXIO_TIMIEN FLEXIO_TIMIEN_REG(FLEXIO)
Kojto 90:cb3d968589d8 1411 #define FLEXIO_SHIFTSDEN FLEXIO_SHIFTSDEN_REG(FLEXIO)
Kojto 90:cb3d968589d8 1412 #define FLEXIO_SHIFTCTL0 FLEXIO_SHIFTCTL_REG(FLEXIO,0)
Kojto 90:cb3d968589d8 1413 #define FLEXIO_SHIFTCTL1 FLEXIO_SHIFTCTL_REG(FLEXIO,1)
Kojto 90:cb3d968589d8 1414 #define FLEXIO_SHIFTCTL2 FLEXIO_SHIFTCTL_REG(FLEXIO,2)
Kojto 90:cb3d968589d8 1415 #define FLEXIO_SHIFTCTL3 FLEXIO_SHIFTCTL_REG(FLEXIO,3)
Kojto 90:cb3d968589d8 1416 #define FLEXIO_SHIFTCFG0 FLEXIO_SHIFTCFG_REG(FLEXIO,0)
Kojto 90:cb3d968589d8 1417 #define FLEXIO_SHIFTCFG1 FLEXIO_SHIFTCFG_REG(FLEXIO,1)
Kojto 90:cb3d968589d8 1418 #define FLEXIO_SHIFTCFG2 FLEXIO_SHIFTCFG_REG(FLEXIO,2)
Kojto 90:cb3d968589d8 1419 #define FLEXIO_SHIFTCFG3 FLEXIO_SHIFTCFG_REG(FLEXIO,3)
Kojto 90:cb3d968589d8 1420 #define FLEXIO_SHIFTBUF0 FLEXIO_SHIFTBUF_REG(FLEXIO,0)
Kojto 90:cb3d968589d8 1421 #define FLEXIO_SHIFTBUF1 FLEXIO_SHIFTBUF_REG(FLEXIO,1)
Kojto 90:cb3d968589d8 1422 #define FLEXIO_SHIFTBUF2 FLEXIO_SHIFTBUF_REG(FLEXIO,2)
Kojto 90:cb3d968589d8 1423 #define FLEXIO_SHIFTBUF3 FLEXIO_SHIFTBUF_REG(FLEXIO,3)
Kojto 90:cb3d968589d8 1424 #define FLEXIO_SHIFTBUFBBS0 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,0)
Kojto 90:cb3d968589d8 1425 #define FLEXIO_SHIFTBUFBBS1 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,1)
Kojto 90:cb3d968589d8 1426 #define FLEXIO_SHIFTBUFBBS2 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,2)
Kojto 90:cb3d968589d8 1427 #define FLEXIO_SHIFTBUFBBS3 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,3)
Kojto 90:cb3d968589d8 1428 #define FLEXIO_SHIFTBUFBYS0 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,0)
Kojto 90:cb3d968589d8 1429 #define FLEXIO_SHIFTBUFBYS1 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,1)
Kojto 90:cb3d968589d8 1430 #define FLEXIO_SHIFTBUFBYS2 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,2)
Kojto 90:cb3d968589d8 1431 #define FLEXIO_SHIFTBUFBYS3 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,3)
Kojto 90:cb3d968589d8 1432 #define FLEXIO_SHIFTBUFBIS0 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,0)
Kojto 90:cb3d968589d8 1433 #define FLEXIO_SHIFTBUFBIS1 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,1)
Kojto 90:cb3d968589d8 1434 #define FLEXIO_SHIFTBUFBIS2 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,2)
Kojto 90:cb3d968589d8 1435 #define FLEXIO_SHIFTBUFBIS3 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,3)
Kojto 90:cb3d968589d8 1436 #define FLEXIO_TIMCTL0 FLEXIO_TIMCTL_REG(FLEXIO,0)
Kojto 90:cb3d968589d8 1437 #define FLEXIO_TIMCTL1 FLEXIO_TIMCTL_REG(FLEXIO,1)
Kojto 90:cb3d968589d8 1438 #define FLEXIO_TIMCTL2 FLEXIO_TIMCTL_REG(FLEXIO,2)
Kojto 90:cb3d968589d8 1439 #define FLEXIO_TIMCTL3 FLEXIO_TIMCTL_REG(FLEXIO,3)
Kojto 90:cb3d968589d8 1440 #define FLEXIO_TIMCFG0 FLEXIO_TIMCFG_REG(FLEXIO,0)
Kojto 90:cb3d968589d8 1441 #define FLEXIO_TIMCFG1 FLEXIO_TIMCFG_REG(FLEXIO,1)
Kojto 90:cb3d968589d8 1442 #define FLEXIO_TIMCFG2 FLEXIO_TIMCFG_REG(FLEXIO,2)
Kojto 90:cb3d968589d8 1443 #define FLEXIO_TIMCFG3 FLEXIO_TIMCFG_REG(FLEXIO,3)
Kojto 90:cb3d968589d8 1444 #define FLEXIO_TIMCMP0 FLEXIO_TIMCMP_REG(FLEXIO,0)
Kojto 90:cb3d968589d8 1445 #define FLEXIO_TIMCMP1 FLEXIO_TIMCMP_REG(FLEXIO,1)
Kojto 90:cb3d968589d8 1446 #define FLEXIO_TIMCMP2 FLEXIO_TIMCMP_REG(FLEXIO,2)
Kojto 90:cb3d968589d8 1447 #define FLEXIO_TIMCMP3 FLEXIO_TIMCMP_REG(FLEXIO,3)
Kojto 90:cb3d968589d8 1448
Kojto 90:cb3d968589d8 1449 /* FLEXIO - Register array accessors */
Kojto 90:cb3d968589d8 1450 #define FLEXIO_SHIFTCTL(index) FLEXIO_SHIFTCTL_REG(FLEXIO,index)
Kojto 90:cb3d968589d8 1451 #define FLEXIO_SHIFTCFG(index) FLEXIO_SHIFTCFG_REG(FLEXIO,index)
Kojto 90:cb3d968589d8 1452 #define FLEXIO_SHIFTBUF(index) FLEXIO_SHIFTBUF_REG(FLEXIO,index)
Kojto 90:cb3d968589d8 1453 #define FLEXIO_SHIFTBUFBBS(index) FLEXIO_SHIFTBUFBBS_REG(FLEXIO,index)
Kojto 90:cb3d968589d8 1454 #define FLEXIO_SHIFTBUFBYS(index) FLEXIO_SHIFTBUFBYS_REG(FLEXIO,index)
Kojto 90:cb3d968589d8 1455 #define FLEXIO_SHIFTBUFBIS(index) FLEXIO_SHIFTBUFBIS_REG(FLEXIO,index)
Kojto 90:cb3d968589d8 1456 #define FLEXIO_TIMCTL(index) FLEXIO_TIMCTL_REG(FLEXIO,index)
Kojto 90:cb3d968589d8 1457 #define FLEXIO_TIMCFG(index) FLEXIO_TIMCFG_REG(FLEXIO,index)
Kojto 90:cb3d968589d8 1458 #define FLEXIO_TIMCMP(index) FLEXIO_TIMCMP_REG(FLEXIO,index)
Kojto 90:cb3d968589d8 1459
Kojto 90:cb3d968589d8 1460 /*!
Kojto 90:cb3d968589d8 1461 * @}
Kojto 90:cb3d968589d8 1462 */ /* end of group FLEXIO_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1463
Kojto 90:cb3d968589d8 1464
Kojto 90:cb3d968589d8 1465 /*!
Kojto 90:cb3d968589d8 1466 * @}
Kojto 90:cb3d968589d8 1467 */ /* end of group FLEXIO_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 1468
Kojto 90:cb3d968589d8 1469
Kojto 90:cb3d968589d8 1470 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1471 -- FTFA Peripheral Access Layer
Kojto 90:cb3d968589d8 1472 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1473
Kojto 90:cb3d968589d8 1474 /*!
Kojto 90:cb3d968589d8 1475 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
Kojto 90:cb3d968589d8 1476 * @{
Kojto 90:cb3d968589d8 1477 */
Kojto 90:cb3d968589d8 1478
Kojto 90:cb3d968589d8 1479 /** FTFA - Register Layout Typedef */
Kojto 90:cb3d968589d8 1480 typedef struct {
Kojto 90:cb3d968589d8 1481 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
Kojto 90:cb3d968589d8 1482 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
Kojto 90:cb3d968589d8 1483 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
Kojto 90:cb3d968589d8 1484 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
Kojto 90:cb3d968589d8 1485 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
Kojto 90:cb3d968589d8 1486 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
Kojto 90:cb3d968589d8 1487 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
Kojto 90:cb3d968589d8 1488 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
Kojto 90:cb3d968589d8 1489 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
Kojto 90:cb3d968589d8 1490 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
Kojto 90:cb3d968589d8 1491 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
Kojto 90:cb3d968589d8 1492 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
Kojto 90:cb3d968589d8 1493 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
Kojto 90:cb3d968589d8 1494 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
Kojto 90:cb3d968589d8 1495 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
Kojto 90:cb3d968589d8 1496 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
Kojto 90:cb3d968589d8 1497 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
Kojto 90:cb3d968589d8 1498 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
Kojto 90:cb3d968589d8 1499 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
Kojto 90:cb3d968589d8 1500 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
Kojto 90:cb3d968589d8 1501 } FTFA_Type, *FTFA_MemMapPtr;
Kojto 90:cb3d968589d8 1502
Kojto 90:cb3d968589d8 1503 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1504 -- FTFA - Register accessor macros
Kojto 90:cb3d968589d8 1505 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1506
Kojto 90:cb3d968589d8 1507 /*!
Kojto 90:cb3d968589d8 1508 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
Kojto 90:cb3d968589d8 1509 * @{
Kojto 90:cb3d968589d8 1510 */
Kojto 90:cb3d968589d8 1511
Kojto 90:cb3d968589d8 1512
Kojto 90:cb3d968589d8 1513 /* FTFA - Register accessors */
Kojto 90:cb3d968589d8 1514 #define FTFA_FSTAT_REG(base) ((base)->FSTAT)
Kojto 90:cb3d968589d8 1515 #define FTFA_FCNFG_REG(base) ((base)->FCNFG)
Kojto 90:cb3d968589d8 1516 #define FTFA_FSEC_REG(base) ((base)->FSEC)
Kojto 90:cb3d968589d8 1517 #define FTFA_FOPT_REG(base) ((base)->FOPT)
Kojto 90:cb3d968589d8 1518 #define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
Kojto 90:cb3d968589d8 1519 #define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
Kojto 90:cb3d968589d8 1520 #define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
Kojto 90:cb3d968589d8 1521 #define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
Kojto 90:cb3d968589d8 1522 #define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
Kojto 90:cb3d968589d8 1523 #define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
Kojto 90:cb3d968589d8 1524 #define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
Kojto 90:cb3d968589d8 1525 #define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
Kojto 90:cb3d968589d8 1526 #define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
Kojto 90:cb3d968589d8 1527 #define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
Kojto 90:cb3d968589d8 1528 #define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
Kojto 90:cb3d968589d8 1529 #define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
Kojto 90:cb3d968589d8 1530 #define FTFA_FPROT3_REG(base) ((base)->FPROT3)
Kojto 90:cb3d968589d8 1531 #define FTFA_FPROT2_REG(base) ((base)->FPROT2)
Kojto 90:cb3d968589d8 1532 #define FTFA_FPROT1_REG(base) ((base)->FPROT1)
Kojto 90:cb3d968589d8 1533 #define FTFA_FPROT0_REG(base) ((base)->FPROT0)
Kojto 90:cb3d968589d8 1534
Kojto 90:cb3d968589d8 1535 /*!
Kojto 90:cb3d968589d8 1536 * @}
Kojto 90:cb3d968589d8 1537 */ /* end of group FTFA_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1538
Kojto 90:cb3d968589d8 1539
Kojto 90:cb3d968589d8 1540 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1541 -- FTFA Register Masks
Kojto 90:cb3d968589d8 1542 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1543
Kojto 90:cb3d968589d8 1544 /*!
Kojto 90:cb3d968589d8 1545 * @addtogroup FTFA_Register_Masks FTFA Register Masks
Kojto 90:cb3d968589d8 1546 * @{
Kojto 90:cb3d968589d8 1547 */
Kojto 90:cb3d968589d8 1548
Kojto 90:cb3d968589d8 1549 /* FSTAT Bit Fields */
Kojto 90:cb3d968589d8 1550 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
Kojto 90:cb3d968589d8 1551 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
Kojto 90:cb3d968589d8 1552 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
Kojto 90:cb3d968589d8 1553 #define FTFA_FSTAT_FPVIOL_SHIFT 4
Kojto 90:cb3d968589d8 1554 #define FTFA_FSTAT_ACCERR_MASK 0x20u
Kojto 90:cb3d968589d8 1555 #define FTFA_FSTAT_ACCERR_SHIFT 5
Kojto 90:cb3d968589d8 1556 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
Kojto 90:cb3d968589d8 1557 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
Kojto 90:cb3d968589d8 1558 #define FTFA_FSTAT_CCIF_MASK 0x80u
Kojto 90:cb3d968589d8 1559 #define FTFA_FSTAT_CCIF_SHIFT 7
Kojto 90:cb3d968589d8 1560 /* FCNFG Bit Fields */
Kojto 90:cb3d968589d8 1561 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
Kojto 90:cb3d968589d8 1562 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
Kojto 90:cb3d968589d8 1563 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
Kojto 90:cb3d968589d8 1564 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
Kojto 90:cb3d968589d8 1565 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
Kojto 90:cb3d968589d8 1566 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
Kojto 90:cb3d968589d8 1567 #define FTFA_FCNFG_CCIE_MASK 0x80u
Kojto 90:cb3d968589d8 1568 #define FTFA_FCNFG_CCIE_SHIFT 7
Kojto 90:cb3d968589d8 1569 /* FSEC Bit Fields */
Kojto 90:cb3d968589d8 1570 #define FTFA_FSEC_SEC_MASK 0x3u
Kojto 90:cb3d968589d8 1571 #define FTFA_FSEC_SEC_SHIFT 0
Kojto 90:cb3d968589d8 1572 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
Kojto 90:cb3d968589d8 1573 #define FTFA_FSEC_FSLACC_MASK 0xCu
Kojto 90:cb3d968589d8 1574 #define FTFA_FSEC_FSLACC_SHIFT 2
Kojto 90:cb3d968589d8 1575 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
Kojto 90:cb3d968589d8 1576 #define FTFA_FSEC_MEEN_MASK 0x30u
Kojto 90:cb3d968589d8 1577 #define FTFA_FSEC_MEEN_SHIFT 4
Kojto 90:cb3d968589d8 1578 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
Kojto 90:cb3d968589d8 1579 #define FTFA_FSEC_KEYEN_MASK 0xC0u
Kojto 90:cb3d968589d8 1580 #define FTFA_FSEC_KEYEN_SHIFT 6
Kojto 90:cb3d968589d8 1581 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
Kojto 90:cb3d968589d8 1582 /* FOPT Bit Fields */
Kojto 90:cb3d968589d8 1583 #define FTFA_FOPT_OPT_MASK 0xFFu
Kojto 90:cb3d968589d8 1584 #define FTFA_FOPT_OPT_SHIFT 0
Kojto 90:cb3d968589d8 1585 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
Kojto 90:cb3d968589d8 1586 /* FCCOB3 Bit Fields */
Kojto 90:cb3d968589d8 1587 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1588 #define FTFA_FCCOB3_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1589 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
Kojto 90:cb3d968589d8 1590 /* FCCOB2 Bit Fields */
Kojto 90:cb3d968589d8 1591 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1592 #define FTFA_FCCOB2_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1593 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
Kojto 90:cb3d968589d8 1594 /* FCCOB1 Bit Fields */
Kojto 90:cb3d968589d8 1595 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1596 #define FTFA_FCCOB1_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1597 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
Kojto 90:cb3d968589d8 1598 /* FCCOB0 Bit Fields */
Kojto 90:cb3d968589d8 1599 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1600 #define FTFA_FCCOB0_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1601 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
Kojto 90:cb3d968589d8 1602 /* FCCOB7 Bit Fields */
Kojto 90:cb3d968589d8 1603 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1604 #define FTFA_FCCOB7_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1605 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
Kojto 90:cb3d968589d8 1606 /* FCCOB6 Bit Fields */
Kojto 90:cb3d968589d8 1607 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1608 #define FTFA_FCCOB6_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1609 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
Kojto 90:cb3d968589d8 1610 /* FCCOB5 Bit Fields */
Kojto 90:cb3d968589d8 1611 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1612 #define FTFA_FCCOB5_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1613 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
Kojto 90:cb3d968589d8 1614 /* FCCOB4 Bit Fields */
Kojto 90:cb3d968589d8 1615 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1616 #define FTFA_FCCOB4_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1617 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
Kojto 90:cb3d968589d8 1618 /* FCCOBB Bit Fields */
Kojto 90:cb3d968589d8 1619 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1620 #define FTFA_FCCOBB_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1621 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
Kojto 90:cb3d968589d8 1622 /* FCCOBA Bit Fields */
Kojto 90:cb3d968589d8 1623 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1624 #define FTFA_FCCOBA_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1625 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
Kojto 90:cb3d968589d8 1626 /* FCCOB9 Bit Fields */
Kojto 90:cb3d968589d8 1627 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1628 #define FTFA_FCCOB9_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1629 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
Kojto 90:cb3d968589d8 1630 /* FCCOB8 Bit Fields */
Kojto 90:cb3d968589d8 1631 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
Kojto 90:cb3d968589d8 1632 #define FTFA_FCCOB8_CCOBn_SHIFT 0
Kojto 90:cb3d968589d8 1633 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
Kojto 90:cb3d968589d8 1634 /* FPROT3 Bit Fields */
Kojto 90:cb3d968589d8 1635 #define FTFA_FPROT3_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 1636 #define FTFA_FPROT3_PROT_SHIFT 0
Kojto 90:cb3d968589d8 1637 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
Kojto 90:cb3d968589d8 1638 /* FPROT2 Bit Fields */
Kojto 90:cb3d968589d8 1639 #define FTFA_FPROT2_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 1640 #define FTFA_FPROT2_PROT_SHIFT 0
Kojto 90:cb3d968589d8 1641 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
Kojto 90:cb3d968589d8 1642 /* FPROT1 Bit Fields */
Kojto 90:cb3d968589d8 1643 #define FTFA_FPROT1_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 1644 #define FTFA_FPROT1_PROT_SHIFT 0
Kojto 90:cb3d968589d8 1645 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
Kojto 90:cb3d968589d8 1646 /* FPROT0 Bit Fields */
Kojto 90:cb3d968589d8 1647 #define FTFA_FPROT0_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 1648 #define FTFA_FPROT0_PROT_SHIFT 0
Kojto 90:cb3d968589d8 1649 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
Kojto 90:cb3d968589d8 1650
Kojto 90:cb3d968589d8 1651 /*!
Kojto 90:cb3d968589d8 1652 * @}
Kojto 90:cb3d968589d8 1653 */ /* end of group FTFA_Register_Masks */
Kojto 90:cb3d968589d8 1654
Kojto 90:cb3d968589d8 1655
Kojto 90:cb3d968589d8 1656 /* FTFA - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 1657 /** Peripheral FTFA base address */
Kojto 90:cb3d968589d8 1658 #define FTFA_BASE (0x40020000u)
Kojto 90:cb3d968589d8 1659 /** Peripheral FTFA base pointer */
Kojto 90:cb3d968589d8 1660 #define FTFA ((FTFA_Type *)FTFA_BASE)
Kojto 90:cb3d968589d8 1661 #define FTFA_BASE_PTR (FTFA)
Kojto 90:cb3d968589d8 1662 /** Array initializer of FTFA peripheral base addresses */
Kojto 90:cb3d968589d8 1663 #define FTFA_BASE_ADDRS { FTFA_BASE }
Kojto 90:cb3d968589d8 1664 /** Array initializer of FTFA peripheral base pointers */
Kojto 90:cb3d968589d8 1665 #define FTFA_BASE_PTRS { FTFA }
Kojto 90:cb3d968589d8 1666 /** Interrupt vectors for the FTFA peripheral type */
Kojto 90:cb3d968589d8 1667 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
Kojto 90:cb3d968589d8 1668
Kojto 90:cb3d968589d8 1669 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1670 -- FTFA - Register accessor macros
Kojto 90:cb3d968589d8 1671 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1672
Kojto 90:cb3d968589d8 1673 /*!
Kojto 90:cb3d968589d8 1674 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
Kojto 90:cb3d968589d8 1675 * @{
Kojto 90:cb3d968589d8 1676 */
Kojto 90:cb3d968589d8 1677
Kojto 90:cb3d968589d8 1678
Kojto 90:cb3d968589d8 1679 /* FTFA - Register instance definitions */
Kojto 90:cb3d968589d8 1680 /* FTFA */
Kojto 90:cb3d968589d8 1681 #define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
Kojto 90:cb3d968589d8 1682 #define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
Kojto 90:cb3d968589d8 1683 #define FTFA_FSEC FTFA_FSEC_REG(FTFA)
Kojto 90:cb3d968589d8 1684 #define FTFA_FOPT FTFA_FOPT_REG(FTFA)
Kojto 90:cb3d968589d8 1685 #define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
Kojto 90:cb3d968589d8 1686 #define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
Kojto 90:cb3d968589d8 1687 #define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
Kojto 90:cb3d968589d8 1688 #define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
Kojto 90:cb3d968589d8 1689 #define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
Kojto 90:cb3d968589d8 1690 #define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
Kojto 90:cb3d968589d8 1691 #define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
Kojto 90:cb3d968589d8 1692 #define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
Kojto 90:cb3d968589d8 1693 #define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
Kojto 90:cb3d968589d8 1694 #define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
Kojto 90:cb3d968589d8 1695 #define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
Kojto 90:cb3d968589d8 1696 #define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
Kojto 90:cb3d968589d8 1697 #define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
Kojto 90:cb3d968589d8 1698 #define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
Kojto 90:cb3d968589d8 1699 #define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
Kojto 90:cb3d968589d8 1700 #define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
Kojto 90:cb3d968589d8 1701
Kojto 90:cb3d968589d8 1702 /*!
Kojto 90:cb3d968589d8 1703 * @}
Kojto 90:cb3d968589d8 1704 */ /* end of group FTFA_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1705
Kojto 90:cb3d968589d8 1706
Kojto 90:cb3d968589d8 1707 /*!
Kojto 90:cb3d968589d8 1708 * @}
Kojto 90:cb3d968589d8 1709 */ /* end of group FTFA_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 1710
Kojto 90:cb3d968589d8 1711
Kojto 90:cb3d968589d8 1712 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1713 -- GPIO Peripheral Access Layer
Kojto 90:cb3d968589d8 1714 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1715
Kojto 90:cb3d968589d8 1716 /*!
Kojto 90:cb3d968589d8 1717 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
Kojto 90:cb3d968589d8 1718 * @{
Kojto 90:cb3d968589d8 1719 */
Kojto 90:cb3d968589d8 1720
Kojto 90:cb3d968589d8 1721 /** GPIO - Register Layout Typedef */
Kojto 90:cb3d968589d8 1722 typedef struct {
Kojto 90:cb3d968589d8 1723 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
Kojto 90:cb3d968589d8 1724 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
Kojto 90:cb3d968589d8 1725 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
Kojto 90:cb3d968589d8 1726 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
Kojto 90:cb3d968589d8 1727 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
Kojto 90:cb3d968589d8 1728 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
Kojto 90:cb3d968589d8 1729 } GPIO_Type, *GPIO_MemMapPtr;
Kojto 90:cb3d968589d8 1730
Kojto 90:cb3d968589d8 1731 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1732 -- GPIO - Register accessor macros
Kojto 90:cb3d968589d8 1733 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1734
Kojto 90:cb3d968589d8 1735 /*!
Kojto 90:cb3d968589d8 1736 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
Kojto 90:cb3d968589d8 1737 * @{
Kojto 90:cb3d968589d8 1738 */
Kojto 90:cb3d968589d8 1739
Kojto 90:cb3d968589d8 1740
Kojto 90:cb3d968589d8 1741 /* GPIO - Register accessors */
Kojto 90:cb3d968589d8 1742 #define GPIO_PDOR_REG(base) ((base)->PDOR)
Kojto 90:cb3d968589d8 1743 #define GPIO_PSOR_REG(base) ((base)->PSOR)
Kojto 90:cb3d968589d8 1744 #define GPIO_PCOR_REG(base) ((base)->PCOR)
Kojto 90:cb3d968589d8 1745 #define GPIO_PTOR_REG(base) ((base)->PTOR)
Kojto 90:cb3d968589d8 1746 #define GPIO_PDIR_REG(base) ((base)->PDIR)
Kojto 90:cb3d968589d8 1747 #define GPIO_PDDR_REG(base) ((base)->PDDR)
Kojto 90:cb3d968589d8 1748
Kojto 90:cb3d968589d8 1749 /*!
Kojto 90:cb3d968589d8 1750 * @}
Kojto 90:cb3d968589d8 1751 */ /* end of group GPIO_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1752
Kojto 90:cb3d968589d8 1753
Kojto 90:cb3d968589d8 1754 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1755 -- GPIO Register Masks
Kojto 90:cb3d968589d8 1756 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1757
Kojto 90:cb3d968589d8 1758 /*!
Kojto 90:cb3d968589d8 1759 * @addtogroup GPIO_Register_Masks GPIO Register Masks
Kojto 90:cb3d968589d8 1760 * @{
Kojto 90:cb3d968589d8 1761 */
Kojto 90:cb3d968589d8 1762
Kojto 90:cb3d968589d8 1763 /* PDOR Bit Fields */
Kojto 90:cb3d968589d8 1764 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 1765 #define GPIO_PDOR_PDO_SHIFT 0
Kojto 90:cb3d968589d8 1766 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
Kojto 90:cb3d968589d8 1767 /* PSOR Bit Fields */
Kojto 90:cb3d968589d8 1768 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 1769 #define GPIO_PSOR_PTSO_SHIFT 0
Kojto 90:cb3d968589d8 1770 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
Kojto 90:cb3d968589d8 1771 /* PCOR Bit Fields */
Kojto 90:cb3d968589d8 1772 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 1773 #define GPIO_PCOR_PTCO_SHIFT 0
Kojto 90:cb3d968589d8 1774 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
Kojto 90:cb3d968589d8 1775 /* PTOR Bit Fields */
Kojto 90:cb3d968589d8 1776 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 1777 #define GPIO_PTOR_PTTO_SHIFT 0
Kojto 90:cb3d968589d8 1778 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
Kojto 90:cb3d968589d8 1779 /* PDIR Bit Fields */
Kojto 90:cb3d968589d8 1780 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 1781 #define GPIO_PDIR_PDI_SHIFT 0
Kojto 90:cb3d968589d8 1782 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
Kojto 90:cb3d968589d8 1783 /* PDDR Bit Fields */
Kojto 90:cb3d968589d8 1784 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 1785 #define GPIO_PDDR_PDD_SHIFT 0
Kojto 90:cb3d968589d8 1786 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
Kojto 90:cb3d968589d8 1787
Kojto 90:cb3d968589d8 1788 /*!
Kojto 90:cb3d968589d8 1789 * @}
Kojto 90:cb3d968589d8 1790 */ /* end of group GPIO_Register_Masks */
Kojto 90:cb3d968589d8 1791
Kojto 90:cb3d968589d8 1792
Kojto 90:cb3d968589d8 1793 /* GPIO - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 1794 /** Peripheral GPIOA base address */
Kojto 90:cb3d968589d8 1795 #define GPIOA_BASE (0x400FF000u)
Kojto 90:cb3d968589d8 1796 /** Peripheral GPIOA base pointer */
Kojto 90:cb3d968589d8 1797 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
Kojto 90:cb3d968589d8 1798 #define GPIOA_BASE_PTR (GPIOA)
Kojto 90:cb3d968589d8 1799 /** Peripheral GPIOB base address */
Kojto 90:cb3d968589d8 1800 #define GPIOB_BASE (0x400FF040u)
Kojto 90:cb3d968589d8 1801 /** Peripheral GPIOB base pointer */
Kojto 90:cb3d968589d8 1802 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
Kojto 90:cb3d968589d8 1803 #define GPIOB_BASE_PTR (GPIOB)
Kojto 90:cb3d968589d8 1804 /** Peripheral GPIOC base address */
Kojto 90:cb3d968589d8 1805 #define GPIOC_BASE (0x400FF080u)
Kojto 90:cb3d968589d8 1806 /** Peripheral GPIOC base pointer */
Kojto 90:cb3d968589d8 1807 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
Kojto 90:cb3d968589d8 1808 #define GPIOC_BASE_PTR (GPIOC)
Kojto 90:cb3d968589d8 1809 /** Peripheral GPIOD base address */
Kojto 90:cb3d968589d8 1810 #define GPIOD_BASE (0x400FF0C0u)
Kojto 90:cb3d968589d8 1811 /** Peripheral GPIOD base pointer */
Kojto 90:cb3d968589d8 1812 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
Kojto 90:cb3d968589d8 1813 #define GPIOD_BASE_PTR (GPIOD)
Kojto 90:cb3d968589d8 1814 /** Peripheral GPIOE base address */
Kojto 90:cb3d968589d8 1815 #define GPIOE_BASE (0x400FF100u)
Kojto 90:cb3d968589d8 1816 /** Peripheral GPIOE base pointer */
Kojto 90:cb3d968589d8 1817 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
Kojto 90:cb3d968589d8 1818 #define GPIOE_BASE_PTR (GPIOE)
Kojto 90:cb3d968589d8 1819 /** Array initializer of GPIO peripheral base addresses */
Kojto 90:cb3d968589d8 1820 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
Kojto 90:cb3d968589d8 1821 /** Array initializer of GPIO peripheral base pointers */
Kojto 90:cb3d968589d8 1822 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
Kojto 90:cb3d968589d8 1823
Kojto 90:cb3d968589d8 1824 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1825 -- GPIO - Register accessor macros
Kojto 90:cb3d968589d8 1826 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1827
Kojto 90:cb3d968589d8 1828 /*!
Kojto 90:cb3d968589d8 1829 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
Kojto 90:cb3d968589d8 1830 * @{
Kojto 90:cb3d968589d8 1831 */
Kojto 90:cb3d968589d8 1832
Kojto 90:cb3d968589d8 1833
Kojto 90:cb3d968589d8 1834 /* GPIO - Register instance definitions */
Kojto 90:cb3d968589d8 1835 /* GPIOA */
Kojto 90:cb3d968589d8 1836 #define GPIOA_PDOR GPIO_PDOR_REG(GPIOA)
Kojto 90:cb3d968589d8 1837 #define GPIOA_PSOR GPIO_PSOR_REG(GPIOA)
Kojto 90:cb3d968589d8 1838 #define GPIOA_PCOR GPIO_PCOR_REG(GPIOA)
Kojto 90:cb3d968589d8 1839 #define GPIOA_PTOR GPIO_PTOR_REG(GPIOA)
Kojto 90:cb3d968589d8 1840 #define GPIOA_PDIR GPIO_PDIR_REG(GPIOA)
Kojto 90:cb3d968589d8 1841 #define GPIOA_PDDR GPIO_PDDR_REG(GPIOA)
Kojto 90:cb3d968589d8 1842 /* GPIOB */
Kojto 90:cb3d968589d8 1843 #define GPIOB_PDOR GPIO_PDOR_REG(GPIOB)
Kojto 90:cb3d968589d8 1844 #define GPIOB_PSOR GPIO_PSOR_REG(GPIOB)
Kojto 90:cb3d968589d8 1845 #define GPIOB_PCOR GPIO_PCOR_REG(GPIOB)
Kojto 90:cb3d968589d8 1846 #define GPIOB_PTOR GPIO_PTOR_REG(GPIOB)
Kojto 90:cb3d968589d8 1847 #define GPIOB_PDIR GPIO_PDIR_REG(GPIOB)
Kojto 90:cb3d968589d8 1848 #define GPIOB_PDDR GPIO_PDDR_REG(GPIOB)
Kojto 90:cb3d968589d8 1849 /* GPIOC */
Kojto 90:cb3d968589d8 1850 #define GPIOC_PDOR GPIO_PDOR_REG(GPIOC)
Kojto 90:cb3d968589d8 1851 #define GPIOC_PSOR GPIO_PSOR_REG(GPIOC)
Kojto 90:cb3d968589d8 1852 #define GPIOC_PCOR GPIO_PCOR_REG(GPIOC)
Kojto 90:cb3d968589d8 1853 #define GPIOC_PTOR GPIO_PTOR_REG(GPIOC)
Kojto 90:cb3d968589d8 1854 #define GPIOC_PDIR GPIO_PDIR_REG(GPIOC)
Kojto 90:cb3d968589d8 1855 #define GPIOC_PDDR GPIO_PDDR_REG(GPIOC)
Kojto 90:cb3d968589d8 1856 /* GPIOD */
Kojto 90:cb3d968589d8 1857 #define GPIOD_PDOR GPIO_PDOR_REG(GPIOD)
Kojto 90:cb3d968589d8 1858 #define GPIOD_PSOR GPIO_PSOR_REG(GPIOD)
Kojto 90:cb3d968589d8 1859 #define GPIOD_PCOR GPIO_PCOR_REG(GPIOD)
Kojto 90:cb3d968589d8 1860 #define GPIOD_PTOR GPIO_PTOR_REG(GPIOD)
Kojto 90:cb3d968589d8 1861 #define GPIOD_PDIR GPIO_PDIR_REG(GPIOD)
Kojto 90:cb3d968589d8 1862 #define GPIOD_PDDR GPIO_PDDR_REG(GPIOD)
Kojto 90:cb3d968589d8 1863 /* GPIOE */
Kojto 90:cb3d968589d8 1864 #define GPIOE_PDOR GPIO_PDOR_REG(GPIOE)
Kojto 90:cb3d968589d8 1865 #define GPIOE_PSOR GPIO_PSOR_REG(GPIOE)
Kojto 90:cb3d968589d8 1866 #define GPIOE_PCOR GPIO_PCOR_REG(GPIOE)
Kojto 90:cb3d968589d8 1867 #define GPIOE_PTOR GPIO_PTOR_REG(GPIOE)
Kojto 90:cb3d968589d8 1868 #define GPIOE_PDIR GPIO_PDIR_REG(GPIOE)
Kojto 90:cb3d968589d8 1869 #define GPIOE_PDDR GPIO_PDDR_REG(GPIOE)
Kojto 90:cb3d968589d8 1870
Kojto 90:cb3d968589d8 1871 /*!
Kojto 90:cb3d968589d8 1872 * @}
Kojto 90:cb3d968589d8 1873 */ /* end of group GPIO_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1874
Kojto 90:cb3d968589d8 1875
Kojto 90:cb3d968589d8 1876 /*!
Kojto 90:cb3d968589d8 1877 * @}
Kojto 90:cb3d968589d8 1878 */ /* end of group GPIO_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 1879
Kojto 90:cb3d968589d8 1880
Kojto 90:cb3d968589d8 1881 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1882 -- I2C Peripheral Access Layer
Kojto 90:cb3d968589d8 1883 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1884
Kojto 90:cb3d968589d8 1885 /*!
Kojto 90:cb3d968589d8 1886 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
Kojto 90:cb3d968589d8 1887 * @{
Kojto 90:cb3d968589d8 1888 */
Kojto 90:cb3d968589d8 1889
Kojto 90:cb3d968589d8 1890 /** I2C - Register Layout Typedef */
Kojto 90:cb3d968589d8 1891 typedef struct {
Kojto 90:cb3d968589d8 1892 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
Kojto 90:cb3d968589d8 1893 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
Kojto 90:cb3d968589d8 1894 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
Kojto 90:cb3d968589d8 1895 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
Kojto 90:cb3d968589d8 1896 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
Kojto 90:cb3d968589d8 1897 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
Kojto 90:cb3d968589d8 1898 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
Kojto 90:cb3d968589d8 1899 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
Kojto 90:cb3d968589d8 1900 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
Kojto 90:cb3d968589d8 1901 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
Kojto 90:cb3d968589d8 1902 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
Kojto 90:cb3d968589d8 1903 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
Kojto 90:cb3d968589d8 1904 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
Kojto 90:cb3d968589d8 1905 } I2C_Type, *I2C_MemMapPtr;
Kojto 90:cb3d968589d8 1906
Kojto 90:cb3d968589d8 1907 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1908 -- I2C - Register accessor macros
Kojto 90:cb3d968589d8 1909 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1910
Kojto 90:cb3d968589d8 1911 /*!
Kojto 90:cb3d968589d8 1912 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
Kojto 90:cb3d968589d8 1913 * @{
Kojto 90:cb3d968589d8 1914 */
Kojto 90:cb3d968589d8 1915
Kojto 90:cb3d968589d8 1916
Kojto 90:cb3d968589d8 1917 /* I2C - Register accessors */
Kojto 90:cb3d968589d8 1918 #define I2C_A1_REG(base) ((base)->A1)
Kojto 90:cb3d968589d8 1919 #define I2C_F_REG(base) ((base)->F)
Kojto 90:cb3d968589d8 1920 #define I2C_C1_REG(base) ((base)->C1)
Kojto 90:cb3d968589d8 1921 #define I2C_S_REG(base) ((base)->S)
Kojto 90:cb3d968589d8 1922 #define I2C_D_REG(base) ((base)->D)
Kojto 90:cb3d968589d8 1923 #define I2C_C2_REG(base) ((base)->C2)
Kojto 90:cb3d968589d8 1924 #define I2C_FLT_REG(base) ((base)->FLT)
Kojto 90:cb3d968589d8 1925 #define I2C_RA_REG(base) ((base)->RA)
Kojto 90:cb3d968589d8 1926 #define I2C_SMB_REG(base) ((base)->SMB)
Kojto 90:cb3d968589d8 1927 #define I2C_A2_REG(base) ((base)->A2)
Kojto 90:cb3d968589d8 1928 #define I2C_SLTH_REG(base) ((base)->SLTH)
Kojto 90:cb3d968589d8 1929 #define I2C_SLTL_REG(base) ((base)->SLTL)
Kojto 90:cb3d968589d8 1930 #define I2C_S2_REG(base) ((base)->S2)
Kojto 90:cb3d968589d8 1931
Kojto 90:cb3d968589d8 1932 /*!
Kojto 90:cb3d968589d8 1933 * @}
Kojto 90:cb3d968589d8 1934 */ /* end of group I2C_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 1935
Kojto 90:cb3d968589d8 1936
Kojto 90:cb3d968589d8 1937 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 1938 -- I2C Register Masks
Kojto 90:cb3d968589d8 1939 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 1940
Kojto 90:cb3d968589d8 1941 /*!
Kojto 90:cb3d968589d8 1942 * @addtogroup I2C_Register_Masks I2C Register Masks
Kojto 90:cb3d968589d8 1943 * @{
Kojto 90:cb3d968589d8 1944 */
Kojto 90:cb3d968589d8 1945
Kojto 90:cb3d968589d8 1946 /* A1 Bit Fields */
Kojto 90:cb3d968589d8 1947 #define I2C_A1_AD_MASK 0xFEu
Kojto 90:cb3d968589d8 1948 #define I2C_A1_AD_SHIFT 1
Kojto 90:cb3d968589d8 1949 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
Kojto 90:cb3d968589d8 1950 /* F Bit Fields */
Kojto 90:cb3d968589d8 1951 #define I2C_F_ICR_MASK 0x3Fu
Kojto 90:cb3d968589d8 1952 #define I2C_F_ICR_SHIFT 0
Kojto 90:cb3d968589d8 1953 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
Kojto 90:cb3d968589d8 1954 #define I2C_F_MULT_MASK 0xC0u
Kojto 90:cb3d968589d8 1955 #define I2C_F_MULT_SHIFT 6
Kojto 90:cb3d968589d8 1956 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
Kojto 90:cb3d968589d8 1957 /* C1 Bit Fields */
Kojto 90:cb3d968589d8 1958 #define I2C_C1_DMAEN_MASK 0x1u
Kojto 90:cb3d968589d8 1959 #define I2C_C1_DMAEN_SHIFT 0
Kojto 90:cb3d968589d8 1960 #define I2C_C1_WUEN_MASK 0x2u
Kojto 90:cb3d968589d8 1961 #define I2C_C1_WUEN_SHIFT 1
Kojto 90:cb3d968589d8 1962 #define I2C_C1_RSTA_MASK 0x4u
Kojto 90:cb3d968589d8 1963 #define I2C_C1_RSTA_SHIFT 2
Kojto 90:cb3d968589d8 1964 #define I2C_C1_TXAK_MASK 0x8u
Kojto 90:cb3d968589d8 1965 #define I2C_C1_TXAK_SHIFT 3
Kojto 90:cb3d968589d8 1966 #define I2C_C1_TX_MASK 0x10u
Kojto 90:cb3d968589d8 1967 #define I2C_C1_TX_SHIFT 4
Kojto 90:cb3d968589d8 1968 #define I2C_C1_MST_MASK 0x20u
Kojto 90:cb3d968589d8 1969 #define I2C_C1_MST_SHIFT 5
Kojto 90:cb3d968589d8 1970 #define I2C_C1_IICIE_MASK 0x40u
Kojto 90:cb3d968589d8 1971 #define I2C_C1_IICIE_SHIFT 6
Kojto 90:cb3d968589d8 1972 #define I2C_C1_IICEN_MASK 0x80u
Kojto 90:cb3d968589d8 1973 #define I2C_C1_IICEN_SHIFT 7
Kojto 90:cb3d968589d8 1974 /* S Bit Fields */
Kojto 90:cb3d968589d8 1975 #define I2C_S_RXAK_MASK 0x1u
Kojto 90:cb3d968589d8 1976 #define I2C_S_RXAK_SHIFT 0
Kojto 90:cb3d968589d8 1977 #define I2C_S_IICIF_MASK 0x2u
Kojto 90:cb3d968589d8 1978 #define I2C_S_IICIF_SHIFT 1
Kojto 90:cb3d968589d8 1979 #define I2C_S_SRW_MASK 0x4u
Kojto 90:cb3d968589d8 1980 #define I2C_S_SRW_SHIFT 2
Kojto 90:cb3d968589d8 1981 #define I2C_S_RAM_MASK 0x8u
Kojto 90:cb3d968589d8 1982 #define I2C_S_RAM_SHIFT 3
Kojto 90:cb3d968589d8 1983 #define I2C_S_ARBL_MASK 0x10u
Kojto 90:cb3d968589d8 1984 #define I2C_S_ARBL_SHIFT 4
Kojto 90:cb3d968589d8 1985 #define I2C_S_BUSY_MASK 0x20u
Kojto 90:cb3d968589d8 1986 #define I2C_S_BUSY_SHIFT 5
Kojto 90:cb3d968589d8 1987 #define I2C_S_IAAS_MASK 0x40u
Kojto 90:cb3d968589d8 1988 #define I2C_S_IAAS_SHIFT 6
Kojto 90:cb3d968589d8 1989 #define I2C_S_TCF_MASK 0x80u
Kojto 90:cb3d968589d8 1990 #define I2C_S_TCF_SHIFT 7
Kojto 90:cb3d968589d8 1991 /* D Bit Fields */
Kojto 90:cb3d968589d8 1992 #define I2C_D_DATA_MASK 0xFFu
Kojto 90:cb3d968589d8 1993 #define I2C_D_DATA_SHIFT 0
Kojto 90:cb3d968589d8 1994 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
Kojto 90:cb3d968589d8 1995 /* C2 Bit Fields */
Kojto 90:cb3d968589d8 1996 #define I2C_C2_AD_MASK 0x7u
Kojto 90:cb3d968589d8 1997 #define I2C_C2_AD_SHIFT 0
Kojto 90:cb3d968589d8 1998 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
Kojto 90:cb3d968589d8 1999 #define I2C_C2_RMEN_MASK 0x8u
Kojto 90:cb3d968589d8 2000 #define I2C_C2_RMEN_SHIFT 3
Kojto 90:cb3d968589d8 2001 #define I2C_C2_SBRC_MASK 0x10u
Kojto 90:cb3d968589d8 2002 #define I2C_C2_SBRC_SHIFT 4
Kojto 90:cb3d968589d8 2003 #define I2C_C2_HDRS_MASK 0x20u
Kojto 90:cb3d968589d8 2004 #define I2C_C2_HDRS_SHIFT 5
Kojto 90:cb3d968589d8 2005 #define I2C_C2_ADEXT_MASK 0x40u
Kojto 90:cb3d968589d8 2006 #define I2C_C2_ADEXT_SHIFT 6
Kojto 90:cb3d968589d8 2007 #define I2C_C2_GCAEN_MASK 0x80u
Kojto 90:cb3d968589d8 2008 #define I2C_C2_GCAEN_SHIFT 7
Kojto 90:cb3d968589d8 2009 /* FLT Bit Fields */
Kojto 90:cb3d968589d8 2010 #define I2C_FLT_FLT_MASK 0xFu
Kojto 90:cb3d968589d8 2011 #define I2C_FLT_FLT_SHIFT 0
Kojto 90:cb3d968589d8 2012 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
Kojto 90:cb3d968589d8 2013 #define I2C_FLT_STARTF_MASK 0x10u
Kojto 90:cb3d968589d8 2014 #define I2C_FLT_STARTF_SHIFT 4
Kojto 90:cb3d968589d8 2015 #define I2C_FLT_SSIE_MASK 0x20u
Kojto 90:cb3d968589d8 2016 #define I2C_FLT_SSIE_SHIFT 5
Kojto 90:cb3d968589d8 2017 #define I2C_FLT_STOPF_MASK 0x40u
Kojto 90:cb3d968589d8 2018 #define I2C_FLT_STOPF_SHIFT 6
Kojto 90:cb3d968589d8 2019 #define I2C_FLT_SHEN_MASK 0x80u
Kojto 90:cb3d968589d8 2020 #define I2C_FLT_SHEN_SHIFT 7
Kojto 90:cb3d968589d8 2021 /* RA Bit Fields */
Kojto 90:cb3d968589d8 2022 #define I2C_RA_RAD_MASK 0xFEu
Kojto 90:cb3d968589d8 2023 #define I2C_RA_RAD_SHIFT 1
Kojto 90:cb3d968589d8 2024 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
Kojto 90:cb3d968589d8 2025 /* SMB Bit Fields */
Kojto 90:cb3d968589d8 2026 #define I2C_SMB_SHTF2IE_MASK 0x1u
Kojto 90:cb3d968589d8 2027 #define I2C_SMB_SHTF2IE_SHIFT 0
Kojto 90:cb3d968589d8 2028 #define I2C_SMB_SHTF2_MASK 0x2u
Kojto 90:cb3d968589d8 2029 #define I2C_SMB_SHTF2_SHIFT 1
Kojto 90:cb3d968589d8 2030 #define I2C_SMB_SHTF1_MASK 0x4u
Kojto 90:cb3d968589d8 2031 #define I2C_SMB_SHTF1_SHIFT 2
Kojto 90:cb3d968589d8 2032 #define I2C_SMB_SLTF_MASK 0x8u
Kojto 90:cb3d968589d8 2033 #define I2C_SMB_SLTF_SHIFT 3
Kojto 90:cb3d968589d8 2034 #define I2C_SMB_TCKSEL_MASK 0x10u
Kojto 90:cb3d968589d8 2035 #define I2C_SMB_TCKSEL_SHIFT 4
Kojto 90:cb3d968589d8 2036 #define I2C_SMB_SIICAEN_MASK 0x20u
Kojto 90:cb3d968589d8 2037 #define I2C_SMB_SIICAEN_SHIFT 5
Kojto 90:cb3d968589d8 2038 #define I2C_SMB_ALERTEN_MASK 0x40u
Kojto 90:cb3d968589d8 2039 #define I2C_SMB_ALERTEN_SHIFT 6
Kojto 90:cb3d968589d8 2040 #define I2C_SMB_FACK_MASK 0x80u
Kojto 90:cb3d968589d8 2041 #define I2C_SMB_FACK_SHIFT 7
Kojto 90:cb3d968589d8 2042 /* A2 Bit Fields */
Kojto 90:cb3d968589d8 2043 #define I2C_A2_SAD_MASK 0xFEu
Kojto 90:cb3d968589d8 2044 #define I2C_A2_SAD_SHIFT 1
Kojto 90:cb3d968589d8 2045 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
Kojto 90:cb3d968589d8 2046 /* SLTH Bit Fields */
Kojto 90:cb3d968589d8 2047 #define I2C_SLTH_SSLT_MASK 0xFFu
Kojto 90:cb3d968589d8 2048 #define I2C_SLTH_SSLT_SHIFT 0
Kojto 90:cb3d968589d8 2049 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
Kojto 90:cb3d968589d8 2050 /* SLTL Bit Fields */
Kojto 90:cb3d968589d8 2051 #define I2C_SLTL_SSLT_MASK 0xFFu
Kojto 90:cb3d968589d8 2052 #define I2C_SLTL_SSLT_SHIFT 0
Kojto 90:cb3d968589d8 2053 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
Kojto 90:cb3d968589d8 2054 /* S2 Bit Fields */
Kojto 90:cb3d968589d8 2055 #define I2C_S2_EMPTY_MASK 0x1u
Kojto 90:cb3d968589d8 2056 #define I2C_S2_EMPTY_SHIFT 0
Kojto 90:cb3d968589d8 2057 #define I2C_S2_ERROR_MASK 0x2u
Kojto 90:cb3d968589d8 2058 #define I2C_S2_ERROR_SHIFT 1
Kojto 90:cb3d968589d8 2059
Kojto 90:cb3d968589d8 2060 /*!
Kojto 90:cb3d968589d8 2061 * @}
Kojto 90:cb3d968589d8 2062 */ /* end of group I2C_Register_Masks */
Kojto 90:cb3d968589d8 2063
Kojto 90:cb3d968589d8 2064
Kojto 90:cb3d968589d8 2065 /* I2C - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 2066 /** Peripheral I2C0 base address */
Kojto 90:cb3d968589d8 2067 #define I2C0_BASE (0x40066000u)
Kojto 90:cb3d968589d8 2068 /** Peripheral I2C0 base pointer */
Kojto 90:cb3d968589d8 2069 #define I2C0 ((I2C_Type *)I2C0_BASE)
Kojto 90:cb3d968589d8 2070 #define I2C0_BASE_PTR (I2C0)
Kojto 90:cb3d968589d8 2071 /** Peripheral I2C1 base address */
Kojto 90:cb3d968589d8 2072 #define I2C1_BASE (0x40067000u)
Kojto 90:cb3d968589d8 2073 /** Peripheral I2C1 base pointer */
Kojto 90:cb3d968589d8 2074 #define I2C1 ((I2C_Type *)I2C1_BASE)
Kojto 90:cb3d968589d8 2075 #define I2C1_BASE_PTR (I2C1)
Kojto 90:cb3d968589d8 2076 /** Array initializer of I2C peripheral base addresses */
Kojto 90:cb3d968589d8 2077 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
Kojto 90:cb3d968589d8 2078 /** Array initializer of I2C peripheral base pointers */
Kojto 90:cb3d968589d8 2079 #define I2C_BASE_PTRS { I2C0, I2C1 }
Kojto 90:cb3d968589d8 2080 /** Interrupt vectors for the I2C peripheral type */
Kojto 90:cb3d968589d8 2081 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
Kojto 90:cb3d968589d8 2082
Kojto 90:cb3d968589d8 2083 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2084 -- I2C - Register accessor macros
Kojto 90:cb3d968589d8 2085 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2086
Kojto 90:cb3d968589d8 2087 /*!
Kojto 90:cb3d968589d8 2088 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
Kojto 90:cb3d968589d8 2089 * @{
Kojto 90:cb3d968589d8 2090 */
Kojto 90:cb3d968589d8 2091
Kojto 90:cb3d968589d8 2092
Kojto 90:cb3d968589d8 2093 /* I2C - Register instance definitions */
Kojto 90:cb3d968589d8 2094 /* I2C0 */
Kojto 90:cb3d968589d8 2095 #define I2C0_A1 I2C_A1_REG(I2C0)
Kojto 90:cb3d968589d8 2096 #define I2C0_F I2C_F_REG(I2C0)
Kojto 90:cb3d968589d8 2097 #define I2C0_C1 I2C_C1_REG(I2C0)
Kojto 90:cb3d968589d8 2098 #define I2C0_S I2C_S_REG(I2C0)
Kojto 90:cb3d968589d8 2099 #define I2C0_D I2C_D_REG(I2C0)
Kojto 90:cb3d968589d8 2100 #define I2C0_C2 I2C_C2_REG(I2C0)
Kojto 90:cb3d968589d8 2101 #define I2C0_FLT I2C_FLT_REG(I2C0)
Kojto 90:cb3d968589d8 2102 #define I2C0_RA I2C_RA_REG(I2C0)
Kojto 90:cb3d968589d8 2103 #define I2C0_SMB I2C_SMB_REG(I2C0)
Kojto 90:cb3d968589d8 2104 #define I2C0_A2 I2C_A2_REG(I2C0)
Kojto 90:cb3d968589d8 2105 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
Kojto 90:cb3d968589d8 2106 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
Kojto 90:cb3d968589d8 2107 #define I2C0_S2 I2C_S2_REG(I2C0)
Kojto 90:cb3d968589d8 2108 /* I2C1 */
Kojto 90:cb3d968589d8 2109 #define I2C1_A1 I2C_A1_REG(I2C1)
Kojto 90:cb3d968589d8 2110 #define I2C1_F I2C_F_REG(I2C1)
Kojto 90:cb3d968589d8 2111 #define I2C1_C1 I2C_C1_REG(I2C1)
Kojto 90:cb3d968589d8 2112 #define I2C1_S I2C_S_REG(I2C1)
Kojto 90:cb3d968589d8 2113 #define I2C1_D I2C_D_REG(I2C1)
Kojto 90:cb3d968589d8 2114 #define I2C1_C2 I2C_C2_REG(I2C1)
Kojto 90:cb3d968589d8 2115 #define I2C1_FLT I2C_FLT_REG(I2C1)
Kojto 90:cb3d968589d8 2116 #define I2C1_RA I2C_RA_REG(I2C1)
Kojto 90:cb3d968589d8 2117 #define I2C1_SMB I2C_SMB_REG(I2C1)
Kojto 90:cb3d968589d8 2118 #define I2C1_A2 I2C_A2_REG(I2C1)
Kojto 90:cb3d968589d8 2119 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
Kojto 90:cb3d968589d8 2120 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
Kojto 90:cb3d968589d8 2121 #define I2C1_S2 I2C_S2_REG(I2C1)
Kojto 90:cb3d968589d8 2122
Kojto 90:cb3d968589d8 2123 /*!
Kojto 90:cb3d968589d8 2124 * @}
Kojto 90:cb3d968589d8 2125 */ /* end of group I2C_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 2126
Kojto 90:cb3d968589d8 2127
Kojto 90:cb3d968589d8 2128 /*!
Kojto 90:cb3d968589d8 2129 * @}
Kojto 90:cb3d968589d8 2130 */ /* end of group I2C_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 2131
Kojto 90:cb3d968589d8 2132
Kojto 90:cb3d968589d8 2133 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2134 -- I2S Peripheral Access Layer
Kojto 90:cb3d968589d8 2135 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2136
Kojto 90:cb3d968589d8 2137 /*!
Kojto 90:cb3d968589d8 2138 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
Kojto 90:cb3d968589d8 2139 * @{
Kojto 90:cb3d968589d8 2140 */
Kojto 90:cb3d968589d8 2141
Kojto 90:cb3d968589d8 2142 /** I2S - Register Layout Typedef */
Kojto 90:cb3d968589d8 2143 typedef struct {
Kojto 90:cb3d968589d8 2144 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 2145 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 2146 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
Kojto 90:cb3d968589d8 2147 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
Kojto 90:cb3d968589d8 2148 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
Kojto 90:cb3d968589d8 2149 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
Kojto 90:cb3d968589d8 2150 uint8_t RESERVED_1[8];
Kojto 90:cb3d968589d8 2151 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
Kojto 90:cb3d968589d8 2152 uint8_t RESERVED_2[60];
Kojto 90:cb3d968589d8 2153 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
Kojto 90:cb3d968589d8 2154 uint8_t RESERVED_3[28];
Kojto 90:cb3d968589d8 2155 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
Kojto 90:cb3d968589d8 2156 uint8_t RESERVED_4[4];
Kojto 90:cb3d968589d8 2157 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
Kojto 90:cb3d968589d8 2158 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
Kojto 90:cb3d968589d8 2159 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
Kojto 90:cb3d968589d8 2160 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
Kojto 90:cb3d968589d8 2161 uint8_t RESERVED_5[8];
Kojto 90:cb3d968589d8 2162 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
Kojto 90:cb3d968589d8 2163 uint8_t RESERVED_6[60];
Kojto 90:cb3d968589d8 2164 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
Kojto 90:cb3d968589d8 2165 uint8_t RESERVED_7[28];
Kojto 90:cb3d968589d8 2166 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
Kojto 90:cb3d968589d8 2167 } I2S_Type, *I2S_MemMapPtr;
Kojto 90:cb3d968589d8 2168
Kojto 90:cb3d968589d8 2169 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2170 -- I2S - Register accessor macros
Kojto 90:cb3d968589d8 2171 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2172
Kojto 90:cb3d968589d8 2173 /*!
Kojto 90:cb3d968589d8 2174 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
Kojto 90:cb3d968589d8 2175 * @{
Kojto 90:cb3d968589d8 2176 */
Kojto 90:cb3d968589d8 2177
Kojto 90:cb3d968589d8 2178
Kojto 90:cb3d968589d8 2179 /* I2S - Register accessors */
Kojto 90:cb3d968589d8 2180 #define I2S_TCSR_REG(base) ((base)->TCSR)
Kojto 90:cb3d968589d8 2181 #define I2S_TCR2_REG(base) ((base)->TCR2)
Kojto 90:cb3d968589d8 2182 #define I2S_TCR3_REG(base) ((base)->TCR3)
Kojto 90:cb3d968589d8 2183 #define I2S_TCR4_REG(base) ((base)->TCR4)
Kojto 90:cb3d968589d8 2184 #define I2S_TCR5_REG(base) ((base)->TCR5)
Kojto 90:cb3d968589d8 2185 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
Kojto 90:cb3d968589d8 2186 #define I2S_TMR_REG(base) ((base)->TMR)
Kojto 90:cb3d968589d8 2187 #define I2S_RCSR_REG(base) ((base)->RCSR)
Kojto 90:cb3d968589d8 2188 #define I2S_RCR2_REG(base) ((base)->RCR2)
Kojto 90:cb3d968589d8 2189 #define I2S_RCR3_REG(base) ((base)->RCR3)
Kojto 90:cb3d968589d8 2190 #define I2S_RCR4_REG(base) ((base)->RCR4)
Kojto 90:cb3d968589d8 2191 #define I2S_RCR5_REG(base) ((base)->RCR5)
Kojto 90:cb3d968589d8 2192 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
Kojto 90:cb3d968589d8 2193 #define I2S_RMR_REG(base) ((base)->RMR)
Kojto 90:cb3d968589d8 2194 #define I2S_MCR_REG(base) ((base)->MCR)
Kojto 90:cb3d968589d8 2195
Kojto 90:cb3d968589d8 2196 /*!
Kojto 90:cb3d968589d8 2197 * @}
Kojto 90:cb3d968589d8 2198 */ /* end of group I2S_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 2199
Kojto 90:cb3d968589d8 2200
Kojto 90:cb3d968589d8 2201 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2202 -- I2S Register Masks
Kojto 90:cb3d968589d8 2203 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2204
Kojto 90:cb3d968589d8 2205 /*!
Kojto 90:cb3d968589d8 2206 * @addtogroup I2S_Register_Masks I2S Register Masks
Kojto 90:cb3d968589d8 2207 * @{
Kojto 90:cb3d968589d8 2208 */
Kojto 90:cb3d968589d8 2209
Kojto 90:cb3d968589d8 2210 /* TCSR Bit Fields */
Kojto 90:cb3d968589d8 2211 #define I2S_TCSR_FWDE_MASK 0x2u
Kojto 90:cb3d968589d8 2212 #define I2S_TCSR_FWDE_SHIFT 1
Kojto 90:cb3d968589d8 2213 #define I2S_TCSR_FWIE_MASK 0x200u
Kojto 90:cb3d968589d8 2214 #define I2S_TCSR_FWIE_SHIFT 9
Kojto 90:cb3d968589d8 2215 #define I2S_TCSR_FEIE_MASK 0x400u
Kojto 90:cb3d968589d8 2216 #define I2S_TCSR_FEIE_SHIFT 10
Kojto 90:cb3d968589d8 2217 #define I2S_TCSR_SEIE_MASK 0x800u
Kojto 90:cb3d968589d8 2218 #define I2S_TCSR_SEIE_SHIFT 11
Kojto 90:cb3d968589d8 2219 #define I2S_TCSR_WSIE_MASK 0x1000u
Kojto 90:cb3d968589d8 2220 #define I2S_TCSR_WSIE_SHIFT 12
Kojto 90:cb3d968589d8 2221 #define I2S_TCSR_FWF_MASK 0x20000u
Kojto 90:cb3d968589d8 2222 #define I2S_TCSR_FWF_SHIFT 17
Kojto 90:cb3d968589d8 2223 #define I2S_TCSR_FEF_MASK 0x40000u
Kojto 90:cb3d968589d8 2224 #define I2S_TCSR_FEF_SHIFT 18
Kojto 90:cb3d968589d8 2225 #define I2S_TCSR_SEF_MASK 0x80000u
Kojto 90:cb3d968589d8 2226 #define I2S_TCSR_SEF_SHIFT 19
Kojto 90:cb3d968589d8 2227 #define I2S_TCSR_WSF_MASK 0x100000u
Kojto 90:cb3d968589d8 2228 #define I2S_TCSR_WSF_SHIFT 20
Kojto 90:cb3d968589d8 2229 #define I2S_TCSR_SR_MASK 0x1000000u
Kojto 90:cb3d968589d8 2230 #define I2S_TCSR_SR_SHIFT 24
Kojto 90:cb3d968589d8 2231 #define I2S_TCSR_FR_MASK 0x2000000u
Kojto 90:cb3d968589d8 2232 #define I2S_TCSR_FR_SHIFT 25
Kojto 90:cb3d968589d8 2233 #define I2S_TCSR_BCE_MASK 0x10000000u
Kojto 90:cb3d968589d8 2234 #define I2S_TCSR_BCE_SHIFT 28
Kojto 90:cb3d968589d8 2235 #define I2S_TCSR_DBGE_MASK 0x20000000u
Kojto 90:cb3d968589d8 2236 #define I2S_TCSR_DBGE_SHIFT 29
Kojto 90:cb3d968589d8 2237 #define I2S_TCSR_STOPE_MASK 0x40000000u
Kojto 90:cb3d968589d8 2238 #define I2S_TCSR_STOPE_SHIFT 30
Kojto 90:cb3d968589d8 2239 #define I2S_TCSR_TE_MASK 0x80000000u
Kojto 90:cb3d968589d8 2240 #define I2S_TCSR_TE_SHIFT 31
Kojto 90:cb3d968589d8 2241 /* TCR2 Bit Fields */
Kojto 90:cb3d968589d8 2242 #define I2S_TCR2_DIV_MASK 0xFFu
Kojto 90:cb3d968589d8 2243 #define I2S_TCR2_DIV_SHIFT 0
Kojto 90:cb3d968589d8 2244 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
Kojto 90:cb3d968589d8 2245 #define I2S_TCR2_BCD_MASK 0x1000000u
Kojto 90:cb3d968589d8 2246 #define I2S_TCR2_BCD_SHIFT 24
Kojto 90:cb3d968589d8 2247 #define I2S_TCR2_BCP_MASK 0x2000000u
Kojto 90:cb3d968589d8 2248 #define I2S_TCR2_BCP_SHIFT 25
Kojto 90:cb3d968589d8 2249 #define I2S_TCR2_MSEL_MASK 0xC000000u
Kojto 90:cb3d968589d8 2250 #define I2S_TCR2_MSEL_SHIFT 26
Kojto 90:cb3d968589d8 2251 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
Kojto 90:cb3d968589d8 2252 #define I2S_TCR2_BCI_MASK 0x10000000u
Kojto 90:cb3d968589d8 2253 #define I2S_TCR2_BCI_SHIFT 28
Kojto 90:cb3d968589d8 2254 #define I2S_TCR2_BCS_MASK 0x20000000u
Kojto 90:cb3d968589d8 2255 #define I2S_TCR2_BCS_SHIFT 29
Kojto 90:cb3d968589d8 2256 #define I2S_TCR2_SYNC_MASK 0xC0000000u
Kojto 90:cb3d968589d8 2257 #define I2S_TCR2_SYNC_SHIFT 30
Kojto 90:cb3d968589d8 2258 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
Kojto 90:cb3d968589d8 2259 /* TCR3 Bit Fields */
Kojto 90:cb3d968589d8 2260 #define I2S_TCR3_WDFL_MASK 0x1u
Kojto 90:cb3d968589d8 2261 #define I2S_TCR3_WDFL_SHIFT 0
Kojto 90:cb3d968589d8 2262 #define I2S_TCR3_TCE_MASK 0x10000u
Kojto 90:cb3d968589d8 2263 #define I2S_TCR3_TCE_SHIFT 16
Kojto 90:cb3d968589d8 2264 /* TCR4 Bit Fields */
Kojto 90:cb3d968589d8 2265 #define I2S_TCR4_FSD_MASK 0x1u
Kojto 90:cb3d968589d8 2266 #define I2S_TCR4_FSD_SHIFT 0
Kojto 90:cb3d968589d8 2267 #define I2S_TCR4_FSP_MASK 0x2u
Kojto 90:cb3d968589d8 2268 #define I2S_TCR4_FSP_SHIFT 1
Kojto 90:cb3d968589d8 2269 #define I2S_TCR4_ONDEM_MASK 0x4u
Kojto 90:cb3d968589d8 2270 #define I2S_TCR4_ONDEM_SHIFT 2
Kojto 90:cb3d968589d8 2271 #define I2S_TCR4_FSE_MASK 0x8u
Kojto 90:cb3d968589d8 2272 #define I2S_TCR4_FSE_SHIFT 3
Kojto 90:cb3d968589d8 2273 #define I2S_TCR4_MF_MASK 0x10u
Kojto 90:cb3d968589d8 2274 #define I2S_TCR4_MF_SHIFT 4
Kojto 90:cb3d968589d8 2275 #define I2S_TCR4_SYWD_MASK 0x1F00u
Kojto 90:cb3d968589d8 2276 #define I2S_TCR4_SYWD_SHIFT 8
Kojto 90:cb3d968589d8 2277 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
Kojto 90:cb3d968589d8 2278 #define I2S_TCR4_FRSZ_MASK 0x10000u
Kojto 90:cb3d968589d8 2279 #define I2S_TCR4_FRSZ_SHIFT 16
Kojto 90:cb3d968589d8 2280 #define I2S_TCR4_FPACK_MASK 0x3000000u
Kojto 90:cb3d968589d8 2281 #define I2S_TCR4_FPACK_SHIFT 24
Kojto 90:cb3d968589d8 2282 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
Kojto 90:cb3d968589d8 2283 #define I2S_TCR4_FCONT_MASK 0x10000000u
Kojto 90:cb3d968589d8 2284 #define I2S_TCR4_FCONT_SHIFT 28
Kojto 90:cb3d968589d8 2285 /* TCR5 Bit Fields */
Kojto 90:cb3d968589d8 2286 #define I2S_TCR5_FBT_MASK 0x1F00u
Kojto 90:cb3d968589d8 2287 #define I2S_TCR5_FBT_SHIFT 8
Kojto 90:cb3d968589d8 2288 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
Kojto 90:cb3d968589d8 2289 #define I2S_TCR5_W0W_MASK 0x1F0000u
Kojto 90:cb3d968589d8 2290 #define I2S_TCR5_W0W_SHIFT 16
Kojto 90:cb3d968589d8 2291 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
Kojto 90:cb3d968589d8 2292 #define I2S_TCR5_WNW_MASK 0x1F000000u
Kojto 90:cb3d968589d8 2293 #define I2S_TCR5_WNW_SHIFT 24
Kojto 90:cb3d968589d8 2294 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
Kojto 90:cb3d968589d8 2295 /* TDR Bit Fields */
Kojto 90:cb3d968589d8 2296 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2297 #define I2S_TDR_TDR_SHIFT 0
Kojto 90:cb3d968589d8 2298 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
Kojto 90:cb3d968589d8 2299 /* TMR Bit Fields */
Kojto 90:cb3d968589d8 2300 #define I2S_TMR_TWM_MASK 0x3u
Kojto 90:cb3d968589d8 2301 #define I2S_TMR_TWM_SHIFT 0
Kojto 90:cb3d968589d8 2302 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
Kojto 90:cb3d968589d8 2303 /* RCSR Bit Fields */
Kojto 90:cb3d968589d8 2304 #define I2S_RCSR_FWDE_MASK 0x2u
Kojto 90:cb3d968589d8 2305 #define I2S_RCSR_FWDE_SHIFT 1
Kojto 90:cb3d968589d8 2306 #define I2S_RCSR_FWIE_MASK 0x200u
Kojto 90:cb3d968589d8 2307 #define I2S_RCSR_FWIE_SHIFT 9
Kojto 90:cb3d968589d8 2308 #define I2S_RCSR_FEIE_MASK 0x400u
Kojto 90:cb3d968589d8 2309 #define I2S_RCSR_FEIE_SHIFT 10
Kojto 90:cb3d968589d8 2310 #define I2S_RCSR_SEIE_MASK 0x800u
Kojto 90:cb3d968589d8 2311 #define I2S_RCSR_SEIE_SHIFT 11
Kojto 90:cb3d968589d8 2312 #define I2S_RCSR_WSIE_MASK 0x1000u
Kojto 90:cb3d968589d8 2313 #define I2S_RCSR_WSIE_SHIFT 12
Kojto 90:cb3d968589d8 2314 #define I2S_RCSR_FWF_MASK 0x20000u
Kojto 90:cb3d968589d8 2315 #define I2S_RCSR_FWF_SHIFT 17
Kojto 90:cb3d968589d8 2316 #define I2S_RCSR_FEF_MASK 0x40000u
Kojto 90:cb3d968589d8 2317 #define I2S_RCSR_FEF_SHIFT 18
Kojto 90:cb3d968589d8 2318 #define I2S_RCSR_SEF_MASK 0x80000u
Kojto 90:cb3d968589d8 2319 #define I2S_RCSR_SEF_SHIFT 19
Kojto 90:cb3d968589d8 2320 #define I2S_RCSR_WSF_MASK 0x100000u
Kojto 90:cb3d968589d8 2321 #define I2S_RCSR_WSF_SHIFT 20
Kojto 90:cb3d968589d8 2322 #define I2S_RCSR_SR_MASK 0x1000000u
Kojto 90:cb3d968589d8 2323 #define I2S_RCSR_SR_SHIFT 24
Kojto 90:cb3d968589d8 2324 #define I2S_RCSR_FR_MASK 0x2000000u
Kojto 90:cb3d968589d8 2325 #define I2S_RCSR_FR_SHIFT 25
Kojto 90:cb3d968589d8 2326 #define I2S_RCSR_BCE_MASK 0x10000000u
Kojto 90:cb3d968589d8 2327 #define I2S_RCSR_BCE_SHIFT 28
Kojto 90:cb3d968589d8 2328 #define I2S_RCSR_DBGE_MASK 0x20000000u
Kojto 90:cb3d968589d8 2329 #define I2S_RCSR_DBGE_SHIFT 29
Kojto 90:cb3d968589d8 2330 #define I2S_RCSR_STOPE_MASK 0x40000000u
Kojto 90:cb3d968589d8 2331 #define I2S_RCSR_STOPE_SHIFT 30
Kojto 90:cb3d968589d8 2332 #define I2S_RCSR_RE_MASK 0x80000000u
Kojto 90:cb3d968589d8 2333 #define I2S_RCSR_RE_SHIFT 31
Kojto 90:cb3d968589d8 2334 /* RCR2 Bit Fields */
Kojto 90:cb3d968589d8 2335 #define I2S_RCR2_DIV_MASK 0xFFu
Kojto 90:cb3d968589d8 2336 #define I2S_RCR2_DIV_SHIFT 0
Kojto 90:cb3d968589d8 2337 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
Kojto 90:cb3d968589d8 2338 #define I2S_RCR2_BCD_MASK 0x1000000u
Kojto 90:cb3d968589d8 2339 #define I2S_RCR2_BCD_SHIFT 24
Kojto 90:cb3d968589d8 2340 #define I2S_RCR2_BCP_MASK 0x2000000u
Kojto 90:cb3d968589d8 2341 #define I2S_RCR2_BCP_SHIFT 25
Kojto 90:cb3d968589d8 2342 #define I2S_RCR2_MSEL_MASK 0xC000000u
Kojto 90:cb3d968589d8 2343 #define I2S_RCR2_MSEL_SHIFT 26
Kojto 90:cb3d968589d8 2344 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
Kojto 90:cb3d968589d8 2345 #define I2S_RCR2_BCI_MASK 0x10000000u
Kojto 90:cb3d968589d8 2346 #define I2S_RCR2_BCI_SHIFT 28
Kojto 90:cb3d968589d8 2347 #define I2S_RCR2_BCS_MASK 0x20000000u
Kojto 90:cb3d968589d8 2348 #define I2S_RCR2_BCS_SHIFT 29
Kojto 90:cb3d968589d8 2349 #define I2S_RCR2_SYNC_MASK 0xC0000000u
Kojto 90:cb3d968589d8 2350 #define I2S_RCR2_SYNC_SHIFT 30
Kojto 90:cb3d968589d8 2351 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
Kojto 90:cb3d968589d8 2352 /* RCR3 Bit Fields */
Kojto 90:cb3d968589d8 2353 #define I2S_RCR3_WDFL_MASK 0x1u
Kojto 90:cb3d968589d8 2354 #define I2S_RCR3_WDFL_SHIFT 0
Kojto 90:cb3d968589d8 2355 #define I2S_RCR3_RCE_MASK 0x10000u
Kojto 90:cb3d968589d8 2356 #define I2S_RCR3_RCE_SHIFT 16
Kojto 90:cb3d968589d8 2357 /* RCR4 Bit Fields */
Kojto 90:cb3d968589d8 2358 #define I2S_RCR4_FSD_MASK 0x1u
Kojto 90:cb3d968589d8 2359 #define I2S_RCR4_FSD_SHIFT 0
Kojto 90:cb3d968589d8 2360 #define I2S_RCR4_FSP_MASK 0x2u
Kojto 90:cb3d968589d8 2361 #define I2S_RCR4_FSP_SHIFT 1
Kojto 90:cb3d968589d8 2362 #define I2S_RCR4_ONDEM_MASK 0x4u
Kojto 90:cb3d968589d8 2363 #define I2S_RCR4_ONDEM_SHIFT 2
Kojto 90:cb3d968589d8 2364 #define I2S_RCR4_FSE_MASK 0x8u
Kojto 90:cb3d968589d8 2365 #define I2S_RCR4_FSE_SHIFT 3
Kojto 90:cb3d968589d8 2366 #define I2S_RCR4_MF_MASK 0x10u
Kojto 90:cb3d968589d8 2367 #define I2S_RCR4_MF_SHIFT 4
Kojto 90:cb3d968589d8 2368 #define I2S_RCR4_SYWD_MASK 0x1F00u
Kojto 90:cb3d968589d8 2369 #define I2S_RCR4_SYWD_SHIFT 8
Kojto 90:cb3d968589d8 2370 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
Kojto 90:cb3d968589d8 2371 #define I2S_RCR4_FRSZ_MASK 0x10000u
Kojto 90:cb3d968589d8 2372 #define I2S_RCR4_FRSZ_SHIFT 16
Kojto 90:cb3d968589d8 2373 #define I2S_RCR4_FPACK_MASK 0x3000000u
Kojto 90:cb3d968589d8 2374 #define I2S_RCR4_FPACK_SHIFT 24
Kojto 90:cb3d968589d8 2375 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
Kojto 90:cb3d968589d8 2376 #define I2S_RCR4_FCONT_MASK 0x10000000u
Kojto 90:cb3d968589d8 2377 #define I2S_RCR4_FCONT_SHIFT 28
Kojto 90:cb3d968589d8 2378 /* RCR5 Bit Fields */
Kojto 90:cb3d968589d8 2379 #define I2S_RCR5_FBT_MASK 0x1F00u
Kojto 90:cb3d968589d8 2380 #define I2S_RCR5_FBT_SHIFT 8
Kojto 90:cb3d968589d8 2381 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
Kojto 90:cb3d968589d8 2382 #define I2S_RCR5_W0W_MASK 0x1F0000u
Kojto 90:cb3d968589d8 2383 #define I2S_RCR5_W0W_SHIFT 16
Kojto 90:cb3d968589d8 2384 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
Kojto 90:cb3d968589d8 2385 #define I2S_RCR5_WNW_MASK 0x1F000000u
Kojto 90:cb3d968589d8 2386 #define I2S_RCR5_WNW_SHIFT 24
Kojto 90:cb3d968589d8 2387 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
Kojto 90:cb3d968589d8 2388 /* RDR Bit Fields */
Kojto 90:cb3d968589d8 2389 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2390 #define I2S_RDR_RDR_SHIFT 0
Kojto 90:cb3d968589d8 2391 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
Kojto 90:cb3d968589d8 2392 /* RMR Bit Fields */
Kojto 90:cb3d968589d8 2393 #define I2S_RMR_RWM_MASK 0x3u
Kojto 90:cb3d968589d8 2394 #define I2S_RMR_RWM_SHIFT 0
Kojto 90:cb3d968589d8 2395 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
Kojto 90:cb3d968589d8 2396 /* MCR Bit Fields */
Kojto 90:cb3d968589d8 2397 #define I2S_MCR_MICS_MASK 0x3000000u
Kojto 90:cb3d968589d8 2398 #define I2S_MCR_MICS_SHIFT 24
Kojto 90:cb3d968589d8 2399 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
Kojto 90:cb3d968589d8 2400 #define I2S_MCR_MOE_MASK 0x40000000u
Kojto 90:cb3d968589d8 2401 #define I2S_MCR_MOE_SHIFT 30
Kojto 90:cb3d968589d8 2402 #define I2S_MCR_DUF_MASK 0x80000000u
Kojto 90:cb3d968589d8 2403 #define I2S_MCR_DUF_SHIFT 31
Kojto 90:cb3d968589d8 2404
Kojto 90:cb3d968589d8 2405 /*!
Kojto 90:cb3d968589d8 2406 * @}
Kojto 90:cb3d968589d8 2407 */ /* end of group I2S_Register_Masks */
Kojto 90:cb3d968589d8 2408
Kojto 90:cb3d968589d8 2409
Kojto 90:cb3d968589d8 2410 /* I2S - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 2411 /** Peripheral I2S0 base address */
Kojto 90:cb3d968589d8 2412 #define I2S0_BASE (0x4002F000u)
Kojto 90:cb3d968589d8 2413 /** Peripheral I2S0 base pointer */
Kojto 90:cb3d968589d8 2414 #define I2S0 ((I2S_Type *)I2S0_BASE)
Kojto 90:cb3d968589d8 2415 #define I2S0_BASE_PTR (I2S0)
Kojto 90:cb3d968589d8 2416 /** Array initializer of I2S peripheral base addresses */
Kojto 90:cb3d968589d8 2417 #define I2S_BASE_ADDRS { I2S0_BASE }
Kojto 90:cb3d968589d8 2418 /** Array initializer of I2S peripheral base pointers */
Kojto 90:cb3d968589d8 2419 #define I2S_BASE_PTRS { I2S0 }
Kojto 90:cb3d968589d8 2420 /** Interrupt vectors for the I2S peripheral type */
Kojto 90:cb3d968589d8 2421 #define I2S_RX_IRQS { I2S0_IRQn }
Kojto 90:cb3d968589d8 2422 #define I2S_TX_IRQS { I2S0_IRQn }
Kojto 90:cb3d968589d8 2423
Kojto 90:cb3d968589d8 2424 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2425 -- I2S - Register accessor macros
Kojto 90:cb3d968589d8 2426 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2427
Kojto 90:cb3d968589d8 2428 /*!
Kojto 90:cb3d968589d8 2429 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
Kojto 90:cb3d968589d8 2430 * @{
Kojto 90:cb3d968589d8 2431 */
Kojto 90:cb3d968589d8 2432
Kojto 90:cb3d968589d8 2433
Kojto 90:cb3d968589d8 2434 /* I2S - Register instance definitions */
Kojto 90:cb3d968589d8 2435 /* I2S0 */
Kojto 90:cb3d968589d8 2436 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
Kojto 90:cb3d968589d8 2437 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
Kojto 90:cb3d968589d8 2438 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
Kojto 90:cb3d968589d8 2439 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
Kojto 90:cb3d968589d8 2440 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
Kojto 90:cb3d968589d8 2441 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
Kojto 90:cb3d968589d8 2442 #define I2S0_TMR I2S_TMR_REG(I2S0)
Kojto 90:cb3d968589d8 2443 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
Kojto 90:cb3d968589d8 2444 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
Kojto 90:cb3d968589d8 2445 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
Kojto 90:cb3d968589d8 2446 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
Kojto 90:cb3d968589d8 2447 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
Kojto 90:cb3d968589d8 2448 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
Kojto 90:cb3d968589d8 2449 #define I2S0_RMR I2S_RMR_REG(I2S0)
Kojto 90:cb3d968589d8 2450 #define I2S0_MCR I2S_MCR_REG(I2S0)
Kojto 90:cb3d968589d8 2451
Kojto 90:cb3d968589d8 2452 /* I2S - Register array accessors */
Kojto 90:cb3d968589d8 2453 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
Kojto 90:cb3d968589d8 2454 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
Kojto 90:cb3d968589d8 2455
Kojto 90:cb3d968589d8 2456 /*!
Kojto 90:cb3d968589d8 2457 * @}
Kojto 90:cb3d968589d8 2458 */ /* end of group I2S_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 2459
Kojto 90:cb3d968589d8 2460
Kojto 90:cb3d968589d8 2461 /*!
Kojto 90:cb3d968589d8 2462 * @}
Kojto 90:cb3d968589d8 2463 */ /* end of group I2S_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 2464
Kojto 90:cb3d968589d8 2465
Kojto 90:cb3d968589d8 2466 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2467 -- LCD Peripheral Access Layer
Kojto 90:cb3d968589d8 2468 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2469
Kojto 90:cb3d968589d8 2470 /*!
Kojto 90:cb3d968589d8 2471 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
Kojto 90:cb3d968589d8 2472 * @{
Kojto 90:cb3d968589d8 2473 */
Kojto 90:cb3d968589d8 2474
Kojto 90:cb3d968589d8 2475 /** LCD - Register Layout Typedef */
Kojto 90:cb3d968589d8 2476 typedef struct {
Kojto 90:cb3d968589d8 2477 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 2478 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
Kojto 90:cb3d968589d8 2479 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
Kojto 90:cb3d968589d8 2480 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
Kojto 90:cb3d968589d8 2481 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
Kojto 90:cb3d968589d8 2482 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
Kojto 90:cb3d968589d8 2483 union { /* offset: 0x20 */
Kojto 90:cb3d968589d8 2484 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
Kojto 90:cb3d968589d8 2485 __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
Kojto 90:cb3d968589d8 2486 };
Kojto 90:cb3d968589d8 2487 } LCD_Type, *LCD_MemMapPtr;
Kojto 90:cb3d968589d8 2488
Kojto 90:cb3d968589d8 2489 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2490 -- LCD - Register accessor macros
Kojto 90:cb3d968589d8 2491 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2492
Kojto 90:cb3d968589d8 2493 /*!
Kojto 90:cb3d968589d8 2494 * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
Kojto 90:cb3d968589d8 2495 * @{
Kojto 90:cb3d968589d8 2496 */
Kojto 90:cb3d968589d8 2497
Kojto 90:cb3d968589d8 2498
Kojto 90:cb3d968589d8 2499 /* LCD - Register accessors */
Kojto 90:cb3d968589d8 2500 #define LCD_GCR_REG(base) ((base)->GCR)
Kojto 90:cb3d968589d8 2501 #define LCD_AR_REG(base) ((base)->AR)
Kojto 90:cb3d968589d8 2502 #define LCD_FDCR_REG(base) ((base)->FDCR)
Kojto 90:cb3d968589d8 2503 #define LCD_FDSR_REG(base) ((base)->FDSR)
Kojto 90:cb3d968589d8 2504 #define LCD_PEN_REG(base,index) ((base)->PEN[index])
Kojto 90:cb3d968589d8 2505 #define LCD_BPEN_REG(base,index) ((base)->BPEN[index])
Kojto 90:cb3d968589d8 2506 #define LCD_WF_REG(base,index2) ((base)->WF[index2])
Kojto 90:cb3d968589d8 2507 #define LCD_WF8B_REG(base,index2) ((base)->WF8B[index2])
Kojto 90:cb3d968589d8 2508
Kojto 90:cb3d968589d8 2509 /*!
Kojto 90:cb3d968589d8 2510 * @}
Kojto 90:cb3d968589d8 2511 */ /* end of group LCD_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 2512
Kojto 90:cb3d968589d8 2513
Kojto 90:cb3d968589d8 2514 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 2515 -- LCD Register Masks
Kojto 90:cb3d968589d8 2516 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 2517
Kojto 90:cb3d968589d8 2518 /*!
Kojto 90:cb3d968589d8 2519 * @addtogroup LCD_Register_Masks LCD Register Masks
Kojto 90:cb3d968589d8 2520 * @{
Kojto 90:cb3d968589d8 2521 */
Kojto 90:cb3d968589d8 2522
Kojto 90:cb3d968589d8 2523 /* GCR Bit Fields */
Kojto 90:cb3d968589d8 2524 #define LCD_GCR_DUTY_MASK 0x7u
Kojto 90:cb3d968589d8 2525 #define LCD_GCR_DUTY_SHIFT 0
Kojto 90:cb3d968589d8 2526 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
Kojto 90:cb3d968589d8 2527 #define LCD_GCR_LCLK_MASK 0x38u
Kojto 90:cb3d968589d8 2528 #define LCD_GCR_LCLK_SHIFT 3
Kojto 90:cb3d968589d8 2529 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
Kojto 90:cb3d968589d8 2530 #define LCD_GCR_SOURCE_MASK 0x40u
Kojto 90:cb3d968589d8 2531 #define LCD_GCR_SOURCE_SHIFT 6
Kojto 90:cb3d968589d8 2532 #define LCD_GCR_LCDEN_MASK 0x80u
Kojto 90:cb3d968589d8 2533 #define LCD_GCR_LCDEN_SHIFT 7
Kojto 90:cb3d968589d8 2534 #define LCD_GCR_LCDSTP_MASK 0x100u
Kojto 90:cb3d968589d8 2535 #define LCD_GCR_LCDSTP_SHIFT 8
Kojto 90:cb3d968589d8 2536 #define LCD_GCR_LCDDOZE_MASK 0x200u
Kojto 90:cb3d968589d8 2537 #define LCD_GCR_LCDDOZE_SHIFT 9
Kojto 90:cb3d968589d8 2538 #define LCD_GCR_FFR_MASK 0x400u
Kojto 90:cb3d968589d8 2539 #define LCD_GCR_FFR_SHIFT 10
Kojto 90:cb3d968589d8 2540 #define LCD_GCR_ALTSOURCE_MASK 0x800u
Kojto 90:cb3d968589d8 2541 #define LCD_GCR_ALTSOURCE_SHIFT 11
Kojto 90:cb3d968589d8 2542 #define LCD_GCR_ALTDIV_MASK 0x3000u
Kojto 90:cb3d968589d8 2543 #define LCD_GCR_ALTDIV_SHIFT 12
Kojto 90:cb3d968589d8 2544 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
Kojto 90:cb3d968589d8 2545 #define LCD_GCR_FDCIEN_MASK 0x4000u
Kojto 90:cb3d968589d8 2546 #define LCD_GCR_FDCIEN_SHIFT 14
Kojto 90:cb3d968589d8 2547 #define LCD_GCR_PADSAFE_MASK 0x8000u
Kojto 90:cb3d968589d8 2548 #define LCD_GCR_PADSAFE_SHIFT 15
Kojto 90:cb3d968589d8 2549 #define LCD_GCR_VSUPPLY_MASK 0x20000u
Kojto 90:cb3d968589d8 2550 #define LCD_GCR_VSUPPLY_SHIFT 17
Kojto 90:cb3d968589d8 2551 #define LCD_GCR_LADJ_MASK 0x300000u
Kojto 90:cb3d968589d8 2552 #define LCD_GCR_LADJ_SHIFT 20
Kojto 90:cb3d968589d8 2553 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
Kojto 90:cb3d968589d8 2554 #define LCD_GCR_CPSEL_MASK 0x800000u
Kojto 90:cb3d968589d8 2555 #define LCD_GCR_CPSEL_SHIFT 23
Kojto 90:cb3d968589d8 2556 #define LCD_GCR_RVTRIM_MASK 0xF000000u
Kojto 90:cb3d968589d8 2557 #define LCD_GCR_RVTRIM_SHIFT 24
Kojto 90:cb3d968589d8 2558 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
Kojto 90:cb3d968589d8 2559 #define LCD_GCR_RVEN_MASK 0x80000000u
Kojto 90:cb3d968589d8 2560 #define LCD_GCR_RVEN_SHIFT 31
Kojto 90:cb3d968589d8 2561 /* AR Bit Fields */
Kojto 90:cb3d968589d8 2562 #define LCD_AR_BRATE_MASK 0x7u
Kojto 90:cb3d968589d8 2563 #define LCD_AR_BRATE_SHIFT 0
Kojto 90:cb3d968589d8 2564 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
Kojto 90:cb3d968589d8 2565 #define LCD_AR_BMODE_MASK 0x8u
Kojto 90:cb3d968589d8 2566 #define LCD_AR_BMODE_SHIFT 3
Kojto 90:cb3d968589d8 2567 #define LCD_AR_BLANK_MASK 0x20u
Kojto 90:cb3d968589d8 2568 #define LCD_AR_BLANK_SHIFT 5
Kojto 90:cb3d968589d8 2569 #define LCD_AR_ALT_MASK 0x40u
Kojto 90:cb3d968589d8 2570 #define LCD_AR_ALT_SHIFT 6
Kojto 90:cb3d968589d8 2571 #define LCD_AR_BLINK_MASK 0x80u
Kojto 90:cb3d968589d8 2572 #define LCD_AR_BLINK_SHIFT 7
Kojto 90:cb3d968589d8 2573 /* FDCR Bit Fields */
Kojto 90:cb3d968589d8 2574 #define LCD_FDCR_FDPINID_MASK 0x3Fu
Kojto 90:cb3d968589d8 2575 #define LCD_FDCR_FDPINID_SHIFT 0
Kojto 90:cb3d968589d8 2576 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
Kojto 90:cb3d968589d8 2577 #define LCD_FDCR_FDBPEN_MASK 0x40u
Kojto 90:cb3d968589d8 2578 #define LCD_FDCR_FDBPEN_SHIFT 6
Kojto 90:cb3d968589d8 2579 #define LCD_FDCR_FDEN_MASK 0x80u
Kojto 90:cb3d968589d8 2580 #define LCD_FDCR_FDEN_SHIFT 7
Kojto 90:cb3d968589d8 2581 #define LCD_FDCR_FDSWW_MASK 0xE00u
Kojto 90:cb3d968589d8 2582 #define LCD_FDCR_FDSWW_SHIFT 9
Kojto 90:cb3d968589d8 2583 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
Kojto 90:cb3d968589d8 2584 #define LCD_FDCR_FDPRS_MASK 0x7000u
Kojto 90:cb3d968589d8 2585 #define LCD_FDCR_FDPRS_SHIFT 12
Kojto 90:cb3d968589d8 2586 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
Kojto 90:cb3d968589d8 2587 /* FDSR Bit Fields */
Kojto 90:cb3d968589d8 2588 #define LCD_FDSR_FDCNT_MASK 0xFFu
Kojto 90:cb3d968589d8 2589 #define LCD_FDSR_FDCNT_SHIFT 0
Kojto 90:cb3d968589d8 2590 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
Kojto 90:cb3d968589d8 2591 #define LCD_FDSR_FDCF_MASK 0x8000u
Kojto 90:cb3d968589d8 2592 #define LCD_FDSR_FDCF_SHIFT 15
Kojto 90:cb3d968589d8 2593 /* PEN Bit Fields */
Kojto 90:cb3d968589d8 2594 #define LCD_PEN_PEN_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2595 #define LCD_PEN_PEN_SHIFT 0
Kojto 90:cb3d968589d8 2596 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
Kojto 90:cb3d968589d8 2597 /* BPEN Bit Fields */
Kojto 90:cb3d968589d8 2598 #define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 2599 #define LCD_BPEN_BPEN_SHIFT 0
Kojto 90:cb3d968589d8 2600 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
Kojto 90:cb3d968589d8 2601 /* WF Bit Fields */
Kojto 90:cb3d968589d8 2602 #define LCD_WF_WF0_MASK 0xFFu
Kojto 90:cb3d968589d8 2603 #define LCD_WF_WF0_SHIFT 0
Kojto 90:cb3d968589d8 2604 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
Kojto 90:cb3d968589d8 2605 #define LCD_WF_WF60_MASK 0xFFu
Kojto 90:cb3d968589d8 2606 #define LCD_WF_WF60_SHIFT 0
Kojto 90:cb3d968589d8 2607 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
Kojto 90:cb3d968589d8 2608 #define LCD_WF_WF56_MASK 0xFFu
Kojto 90:cb3d968589d8 2609 #define LCD_WF_WF56_SHIFT 0
Kojto 90:cb3d968589d8 2610 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
Kojto 90:cb3d968589d8 2611 #define LCD_WF_WF52_MASK 0xFFu
Kojto 90:cb3d968589d8 2612 #define LCD_WF_WF52_SHIFT 0
Kojto 90:cb3d968589d8 2613 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
Kojto 90:cb3d968589d8 2614 #define LCD_WF_WF4_MASK 0xFFu
Kojto 90:cb3d968589d8 2615 #define LCD_WF_WF4_SHIFT 0
Kojto 90:cb3d968589d8 2616 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
Kojto 90:cb3d968589d8 2617 #define LCD_WF_WF48_MASK 0xFFu
Kojto 90:cb3d968589d8 2618 #define LCD_WF_WF48_SHIFT 0
Kojto 90:cb3d968589d8 2619 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
Kojto 90:cb3d968589d8 2620 #define LCD_WF_WF44_MASK 0xFFu
Kojto 90:cb3d968589d8 2621 #define LCD_WF_WF44_SHIFT 0
Kojto 90:cb3d968589d8 2622 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
Kojto 90:cb3d968589d8 2623 #define LCD_WF_WF40_MASK 0xFFu
Kojto 90:cb3d968589d8 2624 #define LCD_WF_WF40_SHIFT 0
Kojto 90:cb3d968589d8 2625 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
Kojto 90:cb3d968589d8 2626 #define LCD_WF_WF8_MASK 0xFFu
Kojto 90:cb3d968589d8 2627 #define LCD_WF_WF8_SHIFT 0
Kojto 90:cb3d968589d8 2628 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
Kojto 90:cb3d968589d8 2629 #define LCD_WF_WF36_MASK 0xFFu
Kojto 90:cb3d968589d8 2630 #define LCD_WF_WF36_SHIFT 0
Kojto 90:cb3d968589d8 2631 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
Kojto 90:cb3d968589d8 2632 #define LCD_WF_WF32_MASK 0xFFu
Kojto 90:cb3d968589d8 2633 #define LCD_WF_WF32_SHIFT 0
Kojto 90:cb3d968589d8 2634 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
Kojto 90:cb3d968589d8 2635 #define LCD_WF_WF28_MASK 0xFFu
Kojto 90:cb3d968589d8 2636 #define LCD_WF_WF28_SHIFT 0
Kojto 90:cb3d968589d8 2637 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
Kojto 90:cb3d968589d8 2638 #define LCD_WF_WF12_MASK 0xFFu
Kojto 90:cb3d968589d8 2639 #define LCD_WF_WF12_SHIFT 0
Kojto 90:cb3d968589d8 2640 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
Kojto 90:cb3d968589d8 2641 #define LCD_WF_WF24_MASK 0xFFu
Kojto 90:cb3d968589d8 2642 #define LCD_WF_WF24_SHIFT 0
Kojto 90:cb3d968589d8 2643 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
Kojto 90:cb3d968589d8 2644 #define LCD_WF_WF20_MASK 0xFFu
Kojto 90:cb3d968589d8 2645 #define LCD_WF_WF20_SHIFT 0
Kojto 90:cb3d968589d8 2646 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
Kojto 90:cb3d968589d8 2647 #define LCD_WF_WF16_MASK 0xFFu
Kojto 90:cb3d968589d8 2648 #define LCD_WF_WF16_SHIFT 0
Kojto 90:cb3d968589d8 2649 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
Kojto 90:cb3d968589d8 2650 #define LCD_WF_WF5_MASK 0xFF00u
Kojto 90:cb3d968589d8 2651 #define LCD_WF_WF5_SHIFT 8
Kojto 90:cb3d968589d8 2652 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
Kojto 90:cb3d968589d8 2653 #define LCD_WF_WF49_MASK 0xFF00u
Kojto 90:cb3d968589d8 2654 #define LCD_WF_WF49_SHIFT 8
Kojto 90:cb3d968589d8 2655 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
Kojto 90:cb3d968589d8 2656 #define LCD_WF_WF45_MASK 0xFF00u
Kojto 90:cb3d968589d8 2657 #define LCD_WF_WF45_SHIFT 8
Kojto 90:cb3d968589d8 2658 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
Kojto 90:cb3d968589d8 2659 #define LCD_WF_WF61_MASK 0xFF00u
Kojto 90:cb3d968589d8 2660 #define LCD_WF_WF61_SHIFT 8
Kojto 90:cb3d968589d8 2661 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
Kojto 90:cb3d968589d8 2662 #define LCD_WF_WF25_MASK 0xFF00u
Kojto 90:cb3d968589d8 2663 #define LCD_WF_WF25_SHIFT 8
Kojto 90:cb3d968589d8 2664 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
Kojto 90:cb3d968589d8 2665 #define LCD_WF_WF17_MASK 0xFF00u
Kojto 90:cb3d968589d8 2666 #define LCD_WF_WF17_SHIFT 8
Kojto 90:cb3d968589d8 2667 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
Kojto 90:cb3d968589d8 2668 #define LCD_WF_WF41_MASK 0xFF00u
Kojto 90:cb3d968589d8 2669 #define LCD_WF_WF41_SHIFT 8
Kojto 90:cb3d968589d8 2670 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
Kojto 90:cb3d968589d8 2671 #define LCD_WF_WF13_MASK 0xFF00u
Kojto 90:cb3d968589d8 2672 #define LCD_WF_WF13_SHIFT 8
Kojto 90:cb3d968589d8 2673 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
Kojto 90:cb3d968589d8 2674 #define LCD_WF_WF57_MASK 0xFF00u
Kojto 90:cb3d968589d8 2675 #define LCD_WF_WF57_SHIFT 8
Kojto 90:cb3d968589d8 2676 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
Kojto 90:cb3d968589d8 2677 #define LCD_WF_WF53_MASK 0xFF00u
Kojto 90:cb3d968589d8 2678 #define LCD_WF_WF53_SHIFT 8
Kojto 90:cb3d968589d8 2679 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
Kojto 90:cb3d968589d8 2680 #define LCD_WF_WF37_MASK 0xFF00u
Kojto 90:cb3d968589d8 2681 #define LCD_WF_WF37_SHIFT 8
Kojto 90:cb3d968589d8 2682 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
Kojto 90:cb3d968589d8 2683 #define LCD_WF_WF9_MASK 0xFF00u
Kojto 90:cb3d968589d8 2684 #define LCD_WF_WF9_SHIFT 8
Kojto 90:cb3d968589d8 2685 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
Kojto 90:cb3d968589d8 2686 #define LCD_WF_WF1_MASK 0xFF00u
Kojto 90:cb3d968589d8 2687 #define LCD_WF_WF1_SHIFT 8
Kojto 90:cb3d968589d8 2688 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
Kojto 90:cb3d968589d8 2689 #define LCD_WF_WF29_MASK 0xFF00u
Kojto 90:cb3d968589d8 2690 #define LCD_WF_WF29_SHIFT 8
Kojto 90:cb3d968589d8 2691 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
Kojto 90:cb3d968589d8 2692 #define LCD_WF_WF33_MASK 0xFF00u
Kojto 90:cb3d968589d8 2693 #define LCD_WF_WF33_SHIFT 8
Kojto 90:cb3d968589d8 2694 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
Kojto 90:cb3d968589d8 2695 #define LCD_WF_WF21_MASK 0xFF00u
Kojto 90:cb3d968589d8 2696 #define LCD_WF_WF21_SHIFT 8
Kojto 90:cb3d968589d8 2697 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
Kojto 90:cb3d968589d8 2698 #define LCD_WF_WF26_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2699 #define LCD_WF_WF26_SHIFT 16
Kojto 90:cb3d968589d8 2700 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
Kojto 90:cb3d968589d8 2701 #define LCD_WF_WF46_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2702 #define LCD_WF_WF46_SHIFT 16
Kojto 90:cb3d968589d8 2703 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
Kojto 90:cb3d968589d8 2704 #define LCD_WF_WF6_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2705 #define LCD_WF_WF6_SHIFT 16
Kojto 90:cb3d968589d8 2706 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
Kojto 90:cb3d968589d8 2707 #define LCD_WF_WF42_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2708 #define LCD_WF_WF42_SHIFT 16
Kojto 90:cb3d968589d8 2709 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
Kojto 90:cb3d968589d8 2710 #define LCD_WF_WF18_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2711 #define LCD_WF_WF18_SHIFT 16
Kojto 90:cb3d968589d8 2712 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
Kojto 90:cb3d968589d8 2713 #define LCD_WF_WF38_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2714 #define LCD_WF_WF38_SHIFT 16
Kojto 90:cb3d968589d8 2715 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
Kojto 90:cb3d968589d8 2716 #define LCD_WF_WF22_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2717 #define LCD_WF_WF22_SHIFT 16
Kojto 90:cb3d968589d8 2718 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
Kojto 90:cb3d968589d8 2719 #define LCD_WF_WF34_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2720 #define LCD_WF_WF34_SHIFT 16
Kojto 90:cb3d968589d8 2721 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
Kojto 90:cb3d968589d8 2722 #define LCD_WF_WF50_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2723 #define LCD_WF_WF50_SHIFT 16
Kojto 90:cb3d968589d8 2724 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
Kojto 90:cb3d968589d8 2725 #define LCD_WF_WF14_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2726 #define LCD_WF_WF14_SHIFT 16
Kojto 90:cb3d968589d8 2727 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
Kojto 90:cb3d968589d8 2728 #define LCD_WF_WF54_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2729 #define LCD_WF_WF54_SHIFT 16
Kojto 90:cb3d968589d8 2730 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
Kojto 90:cb3d968589d8 2731 #define LCD_WF_WF2_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2732 #define LCD_WF_WF2_SHIFT 16
Kojto 90:cb3d968589d8 2733 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
Kojto 90:cb3d968589d8 2734 #define LCD_WF_WF58_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2735 #define LCD_WF_WF58_SHIFT 16
Kojto 90:cb3d968589d8 2736 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
Kojto 90:cb3d968589d8 2737 #define LCD_WF_WF30_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2738 #define LCD_WF_WF30_SHIFT 16
Kojto 90:cb3d968589d8 2739 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
Kojto 90:cb3d968589d8 2740 #define LCD_WF_WF62_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2741 #define LCD_WF_WF62_SHIFT 16
Kojto 90:cb3d968589d8 2742 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
Kojto 90:cb3d968589d8 2743 #define LCD_WF_WF10_MASK 0xFF0000u
Kojto 90:cb3d968589d8 2744 #define LCD_WF_WF10_SHIFT 16
Kojto 90:cb3d968589d8 2745 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
Kojto 90:cb3d968589d8 2746 #define LCD_WF_WF63_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2747 #define LCD_WF_WF63_SHIFT 24
Kojto 90:cb3d968589d8 2748 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
Kojto 90:cb3d968589d8 2749 #define LCD_WF_WF59_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2750 #define LCD_WF_WF59_SHIFT 24
Kojto 90:cb3d968589d8 2751 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
Kojto 90:cb3d968589d8 2752 #define LCD_WF_WF55_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2753 #define LCD_WF_WF55_SHIFT 24
Kojto 90:cb3d968589d8 2754 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
Kojto 90:cb3d968589d8 2755 #define LCD_WF_WF3_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2756 #define LCD_WF_WF3_SHIFT 24
Kojto 90:cb3d968589d8 2757 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
Kojto 90:cb3d968589d8 2758 #define LCD_WF_WF51_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2759 #define LCD_WF_WF51_SHIFT 24
Kojto 90:cb3d968589d8 2760 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
Kojto 90:cb3d968589d8 2761 #define LCD_WF_WF47_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2762 #define LCD_WF_WF47_SHIFT 24
Kojto 90:cb3d968589d8 2763 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
Kojto 90:cb3d968589d8 2764 #define LCD_WF_WF43_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2765 #define LCD_WF_WF43_SHIFT 24
Kojto 90:cb3d968589d8 2766 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
Kojto 90:cb3d968589d8 2767 #define LCD_WF_WF7_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2768 #define LCD_WF_WF7_SHIFT 24
Kojto 90:cb3d968589d8 2769 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
Kojto 90:cb3d968589d8 2770 #define LCD_WF_WF39_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2771 #define LCD_WF_WF39_SHIFT 24
Kojto 90:cb3d968589d8 2772 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
Kojto 90:cb3d968589d8 2773 #define LCD_WF_WF35_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2774 #define LCD_WF_WF35_SHIFT 24
Kojto 90:cb3d968589d8 2775 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
Kojto 90:cb3d968589d8 2776 #define LCD_WF_WF31_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2777 #define LCD_WF_WF31_SHIFT 24
Kojto 90:cb3d968589d8 2778 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
Kojto 90:cb3d968589d8 2779 #define LCD_WF_WF11_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2780 #define LCD_WF_WF11_SHIFT 24
Kojto 90:cb3d968589d8 2781 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
Kojto 90:cb3d968589d8 2782 #define LCD_WF_WF27_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2783 #define LCD_WF_WF27_SHIFT 24
Kojto 90:cb3d968589d8 2784 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
Kojto 90:cb3d968589d8 2785 #define LCD_WF_WF23_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2786 #define LCD_WF_WF23_SHIFT 24
Kojto 90:cb3d968589d8 2787 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
Kojto 90:cb3d968589d8 2788 #define LCD_WF_WF19_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2789 #define LCD_WF_WF19_SHIFT 24
Kojto 90:cb3d968589d8 2790 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
Kojto 90:cb3d968589d8 2791 #define LCD_WF_WF15_MASK 0xFF000000u
Kojto 90:cb3d968589d8 2792 #define LCD_WF_WF15_SHIFT 24
Kojto 90:cb3d968589d8 2793 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
Kojto 90:cb3d968589d8 2794 /* WF8B Bit Fields */
Kojto 90:cb3d968589d8 2795 #define LCD_WF8B_BPALCD0_MASK 0x1u
Kojto 90:cb3d968589d8 2796 #define LCD_WF8B_BPALCD0_SHIFT 0
Kojto 90:cb3d968589d8 2797 #define LCD_WF8B_BPALCD63_MASK 0x1u
Kojto 90:cb3d968589d8 2798 #define LCD_WF8B_BPALCD63_SHIFT 0
Kojto 90:cb3d968589d8 2799 #define LCD_WF8B_BPALCD62_MASK 0x1u
Kojto 90:cb3d968589d8 2800 #define LCD_WF8B_BPALCD62_SHIFT 0
Kojto 90:cb3d968589d8 2801 #define LCD_WF8B_BPALCD61_MASK 0x1u
Kojto 90:cb3d968589d8 2802 #define LCD_WF8B_BPALCD61_SHIFT 0
Kojto 90:cb3d968589d8 2803 #define LCD_WF8B_BPALCD60_MASK 0x1u
Kojto 90:cb3d968589d8 2804 #define LCD_WF8B_BPALCD60_SHIFT 0
Kojto 90:cb3d968589d8 2805 #define LCD_WF8B_BPALCD59_MASK 0x1u
Kojto 90:cb3d968589d8 2806 #define LCD_WF8B_BPALCD59_SHIFT 0
Kojto 90:cb3d968589d8 2807 #define LCD_WF8B_BPALCD58_MASK 0x1u
Kojto 90:cb3d968589d8 2808 #define LCD_WF8B_BPALCD58_SHIFT 0
Kojto 90:cb3d968589d8 2809 #define LCD_WF8B_BPALCD57_MASK 0x1u
Kojto 90:cb3d968589d8 2810 #define LCD_WF8B_BPALCD57_SHIFT 0
Kojto 90:cb3d968589d8 2811 #define LCD_WF8B_BPALCD1_MASK 0x1u
Kojto 90:cb3d968589d8 2812 #define LCD_WF8B_BPALCD1_SHIFT 0
Kojto 90:cb3d968589d8 2813 #define LCD_WF8B_BPALCD56_MASK 0x1u
Kojto 90:cb3d968589d8 2814 #define LCD_WF8B_BPALCD56_SHIFT 0
Kojto 90:cb3d968589d8 2815 #define LCD_WF8B_BPALCD55_MASK 0x1u
Kojto 90:cb3d968589d8 2816 #define LCD_WF8B_BPALCD55_SHIFT 0
Kojto 90:cb3d968589d8 2817 #define LCD_WF8B_BPALCD54_MASK 0x1u
Kojto 90:cb3d968589d8 2818 #define LCD_WF8B_BPALCD54_SHIFT 0
Kojto 90:cb3d968589d8 2819 #define LCD_WF8B_BPALCD53_MASK 0x1u
Kojto 90:cb3d968589d8 2820 #define LCD_WF8B_BPALCD53_SHIFT 0
Kojto 90:cb3d968589d8 2821 #define LCD_WF8B_BPALCD52_MASK 0x1u
Kojto 90:cb3d968589d8 2822 #define LCD_WF8B_BPALCD52_SHIFT 0
Kojto 90:cb3d968589d8 2823 #define LCD_WF8B_BPALCD51_MASK 0x1u
Kojto 90:cb3d968589d8 2824 #define LCD_WF8B_BPALCD51_SHIFT 0
Kojto 90:cb3d968589d8 2825 #define LCD_WF8B_BPALCD50_MASK 0x1u
Kojto 90:cb3d968589d8 2826 #define LCD_WF8B_BPALCD50_SHIFT 0
Kojto 90:cb3d968589d8 2827 #define LCD_WF8B_BPALCD2_MASK 0x1u
Kojto 90:cb3d968589d8 2828 #define LCD_WF8B_BPALCD2_SHIFT 0
Kojto 90:cb3d968589d8 2829 #define LCD_WF8B_BPALCD49_MASK 0x1u
Kojto 90:cb3d968589d8 2830 #define LCD_WF8B_BPALCD49_SHIFT 0
Kojto 90:cb3d968589d8 2831 #define LCD_WF8B_BPALCD48_MASK 0x1u
Kojto 90:cb3d968589d8 2832 #define LCD_WF8B_BPALCD48_SHIFT 0
Kojto 90:cb3d968589d8 2833 #define LCD_WF8B_BPALCD47_MASK 0x1u
Kojto 90:cb3d968589d8 2834 #define LCD_WF8B_BPALCD47_SHIFT 0
Kojto 90:cb3d968589d8 2835 #define LCD_WF8B_BPALCD46_MASK 0x1u
Kojto 90:cb3d968589d8 2836 #define LCD_WF8B_BPALCD46_SHIFT 0
Kojto 90:cb3d968589d8 2837 #define LCD_WF8B_BPALCD45_MASK 0x1u
Kojto 90:cb3d968589d8 2838 #define LCD_WF8B_BPALCD45_SHIFT 0
Kojto 90:cb3d968589d8 2839 #define LCD_WF8B_BPALCD44_MASK 0x1u
Kojto 90:cb3d968589d8 2840 #define LCD_WF8B_BPALCD44_SHIFT 0
Kojto 90:cb3d968589d8 2841 #define LCD_WF8B_BPALCD43_MASK 0x1u
Kojto 90:cb3d968589d8 2842 #define LCD_WF8B_BPALCD43_SHIFT 0
Kojto 90:cb3d968589d8 2843 #define LCD_WF8B_BPALCD3_MASK 0x1u
Kojto 90:cb3d968589d8 2844 #define LCD_WF8B_BPALCD3_SHIFT 0
Kojto 90:cb3d968589d8 2845 #define LCD_WF8B_BPALCD42_MASK 0x1u
Kojto 90:cb3d968589d8 2846 #define LCD_WF8B_BPALCD42_SHIFT 0
Kojto 90:cb3d968589d8 2847 #define LCD_WF8B_BPALCD41_MASK 0x1u
Kojto 90:cb3d968589d8 2848 #define LCD_WF8B_BPALCD41_SHIFT 0
Kojto 90:cb3d968589d8 2849 #define LCD_WF8B_BPALCD40_MASK 0x1u
Kojto 90:cb3d968589d8 2850 #define LCD_WF8B_BPALCD40_SHIFT 0
Kojto 90:cb3d968589d8 2851 #define LCD_WF8B_BPALCD39_MASK 0x1u
Kojto 90:cb3d968589d8 2852 #define LCD_WF8B_BPALCD39_SHIFT 0
Kojto 90:cb3d968589d8 2853 #define LCD_WF8B_BPALCD38_MASK 0x1u
Kojto 90:cb3d968589d8 2854 #define LCD_WF8B_BPALCD38_SHIFT 0
Kojto 90:cb3d968589d8 2855 #define LCD_WF8B_BPALCD37_MASK 0x1u
Kojto 90:cb3d968589d8 2856 #define LCD_WF8B_BPALCD37_SHIFT 0
Kojto 90:cb3d968589d8 2857 #define LCD_WF8B_BPALCD36_MASK 0x1u
Kojto 90:cb3d968589d8 2858 #define LCD_WF8B_BPALCD36_SHIFT 0
Kojto 90:cb3d968589d8 2859 #define LCD_WF8B_BPALCD4_MASK 0x1u
Kojto 90:cb3d968589d8 2860 #define LCD_WF8B_BPALCD4_SHIFT 0
Kojto 90:cb3d968589d8 2861 #define LCD_WF8B_BPALCD35_MASK 0x1u
Kojto 90:cb3d968589d8 2862 #define LCD_WF8B_BPALCD35_SHIFT 0
Kojto 90:cb3d968589d8 2863 #define LCD_WF8B_BPALCD34_MASK 0x1u
Kojto 90:cb3d968589d8 2864 #define LCD_WF8B_BPALCD34_SHIFT 0
Kojto 90:cb3d968589d8 2865 #define LCD_WF8B_BPALCD33_MASK 0x1u
Kojto 90:cb3d968589d8 2866 #define LCD_WF8B_BPALCD33_SHIFT 0
Kojto 90:cb3d968589d8 2867 #define LCD_WF8B_BPALCD32_MASK 0x1u
Kojto 90:cb3d968589d8 2868 #define LCD_WF8B_BPALCD32_SHIFT 0
Kojto 90:cb3d968589d8 2869 #define LCD_WF8B_BPALCD31_MASK 0x1u
Kojto 90:cb3d968589d8 2870 #define LCD_WF8B_BPALCD31_SHIFT 0
Kojto 90:cb3d968589d8 2871 #define LCD_WF8B_BPALCD30_MASK 0x1u
Kojto 90:cb3d968589d8 2872 #define LCD_WF8B_BPALCD30_SHIFT 0
Kojto 90:cb3d968589d8 2873 #define LCD_WF8B_BPALCD29_MASK 0x1u
Kojto 90:cb3d968589d8 2874 #define LCD_WF8B_BPALCD29_SHIFT 0
Kojto 90:cb3d968589d8 2875 #define LCD_WF8B_BPALCD5_MASK 0x1u
Kojto 90:cb3d968589d8 2876 #define LCD_WF8B_BPALCD5_SHIFT 0
Kojto 90:cb3d968589d8 2877 #define LCD_WF8B_BPALCD28_MASK 0x1u
Kojto 90:cb3d968589d8 2878 #define LCD_WF8B_BPALCD28_SHIFT 0
Kojto 90:cb3d968589d8 2879 #define LCD_WF8B_BPALCD27_MASK 0x1u
Kojto 90:cb3d968589d8 2880 #define LCD_WF8B_BPALCD27_SHIFT 0
Kojto 90:cb3d968589d8 2881 #define LCD_WF8B_BPALCD26_MASK 0x1u
Kojto 90:cb3d968589d8 2882 #define LCD_WF8B_BPALCD26_SHIFT 0
Kojto 90:cb3d968589d8 2883 #define LCD_WF8B_BPALCD25_MASK 0x1u
Kojto 90:cb3d968589d8 2884 #define LCD_WF8B_BPALCD25_SHIFT 0
Kojto 90:cb3d968589d8 2885 #define LCD_WF8B_BPALCD24_MASK 0x1u
Kojto 90:cb3d968589d8 2886 #define LCD_WF8B_BPALCD24_SHIFT 0
Kojto 90:cb3d968589d8 2887 #define LCD_WF8B_BPALCD23_MASK 0x1u
Kojto 90:cb3d968589d8 2888 #define LCD_WF8B_BPALCD23_SHIFT 0
Kojto 90:cb3d968589d8 2889 #define LCD_WF8B_BPALCD22_MASK 0x1u
Kojto 90:cb3d968589d8 2890 #define LCD_WF8B_BPALCD22_SHIFT 0
Kojto 90:cb3d968589d8 2891 #define LCD_WF8B_BPALCD6_MASK 0x1u
Kojto 90:cb3d968589d8 2892 #define LCD_WF8B_BPALCD6_SHIFT 0
Kojto 90:cb3d968589d8 2893 #define LCD_WF8B_BPALCD21_MASK 0x1u
Kojto 90:cb3d968589d8 2894 #define LCD_WF8B_BPALCD21_SHIFT 0
Kojto 90:cb3d968589d8 2895 #define LCD_WF8B_BPALCD20_MASK 0x1u
Kojto 90:cb3d968589d8 2896 #define LCD_WF8B_BPALCD20_SHIFT 0
Kojto 90:cb3d968589d8 2897 #define LCD_WF8B_BPALCD19_MASK 0x1u
Kojto 90:cb3d968589d8 2898 #define LCD_WF8B_BPALCD19_SHIFT 0
Kojto 90:cb3d968589d8 2899 #define LCD_WF8B_BPALCD18_MASK 0x1u
Kojto 90:cb3d968589d8 2900 #define LCD_WF8B_BPALCD18_SHIFT 0
Kojto 90:cb3d968589d8 2901 #define LCD_WF8B_BPALCD17_MASK 0x1u
Kojto 90:cb3d968589d8 2902 #define LCD_WF8B_BPALCD17_SHIFT 0
Kojto 90:cb3d968589d8 2903 #define LCD_WF8B_BPALCD16_MASK 0x1u
Kojto 90:cb3d968589d8 2904 #define LCD_WF8B_BPALCD16_SHIFT 0
Kojto 90:cb3d968589d8 2905 #define LCD_WF8B_BPALCD15_MASK 0x1u
Kojto 90:cb3d968589d8 2906 #define LCD_WF8B_BPALCD15_SHIFT 0
Kojto 90:cb3d968589d8 2907 #define LCD_WF8B_BPALCD7_MASK 0x1u
Kojto 90:cb3d968589d8 2908 #define LCD_WF8B_BPALCD7_SHIFT 0
Kojto 90:cb3d968589d8 2909 #define LCD_WF8B_BPALCD14_MASK 0x1u
Kojto 90:cb3d968589d8 2910 #define LCD_WF8B_BPALCD14_SHIFT 0
Kojto 90:cb3d968589d8 2911 #define LCD_WF8B_BPALCD13_MASK 0x1u
Kojto 90:cb3d968589d8 2912 #define LCD_WF8B_BPALCD13_SHIFT 0
Kojto 90:cb3d968589d8 2913 #define LCD_WF8B_BPALCD12_MASK 0x1u
Kojto 90:cb3d968589d8 2914 #define LCD_WF8B_BPALCD12_SHIFT 0
Kojto 90:cb3d968589d8 2915 #define LCD_WF8B_BPALCD11_MASK 0x1u
Kojto 90:cb3d968589d8 2916 #define LCD_WF8B_BPALCD11_SHIFT 0
Kojto 90:cb3d968589d8 2917 #define LCD_WF8B_BPALCD10_MASK 0x1u
Kojto 90:cb3d968589d8 2918 #define LCD_WF8B_BPALCD10_SHIFT 0
Kojto 90:cb3d968589d8 2919 #define LCD_WF8B_BPALCD9_MASK 0x1u
Kojto 90:cb3d968589d8 2920 #define LCD_WF8B_BPALCD9_SHIFT 0
Kojto 90:cb3d968589d8 2921 #define LCD_WF8B_BPALCD8_MASK 0x1u
Kojto 90:cb3d968589d8 2922 #define LCD_WF8B_BPALCD8_SHIFT 0
Kojto 90:cb3d968589d8 2923 #define LCD_WF8B_BPBLCD1_MASK 0x2u
Kojto 90:cb3d968589d8 2924 #define LCD_WF8B_BPBLCD1_SHIFT 1
Kojto 90:cb3d968589d8 2925 #define LCD_WF8B_BPBLCD32_MASK 0x2u
Kojto 90:cb3d968589d8 2926 #define LCD_WF8B_BPBLCD32_SHIFT 1
Kojto 90:cb3d968589d8 2927 #define LCD_WF8B_BPBLCD30_MASK 0x2u
Kojto 90:cb3d968589d8 2928 #define LCD_WF8B_BPBLCD30_SHIFT 1
Kojto 90:cb3d968589d8 2929 #define LCD_WF8B_BPBLCD60_MASK 0x2u
Kojto 90:cb3d968589d8 2930 #define LCD_WF8B_BPBLCD60_SHIFT 1
Kojto 90:cb3d968589d8 2931 #define LCD_WF8B_BPBLCD24_MASK 0x2u
Kojto 90:cb3d968589d8 2932 #define LCD_WF8B_BPBLCD24_SHIFT 1
Kojto 90:cb3d968589d8 2933 #define LCD_WF8B_BPBLCD28_MASK 0x2u
Kojto 90:cb3d968589d8 2934 #define LCD_WF8B_BPBLCD28_SHIFT 1
Kojto 90:cb3d968589d8 2935 #define LCD_WF8B_BPBLCD23_MASK 0x2u
Kojto 90:cb3d968589d8 2936 #define LCD_WF8B_BPBLCD23_SHIFT 1
Kojto 90:cb3d968589d8 2937 #define LCD_WF8B_BPBLCD48_MASK 0x2u
Kojto 90:cb3d968589d8 2938 #define LCD_WF8B_BPBLCD48_SHIFT 1
Kojto 90:cb3d968589d8 2939 #define LCD_WF8B_BPBLCD10_MASK 0x2u
Kojto 90:cb3d968589d8 2940 #define LCD_WF8B_BPBLCD10_SHIFT 1
Kojto 90:cb3d968589d8 2941 #define LCD_WF8B_BPBLCD15_MASK 0x2u
Kojto 90:cb3d968589d8 2942 #define LCD_WF8B_BPBLCD15_SHIFT 1
Kojto 90:cb3d968589d8 2943 #define LCD_WF8B_BPBLCD36_MASK 0x2u
Kojto 90:cb3d968589d8 2944 #define LCD_WF8B_BPBLCD36_SHIFT 1
Kojto 90:cb3d968589d8 2945 #define LCD_WF8B_BPBLCD44_MASK 0x2u
Kojto 90:cb3d968589d8 2946 #define LCD_WF8B_BPBLCD44_SHIFT 1
Kojto 90:cb3d968589d8 2947 #define LCD_WF8B_BPBLCD62_MASK 0x2u
Kojto 90:cb3d968589d8 2948 #define LCD_WF8B_BPBLCD62_SHIFT 1
Kojto 90:cb3d968589d8 2949 #define LCD_WF8B_BPBLCD53_MASK 0x2u
Kojto 90:cb3d968589d8 2950 #define LCD_WF8B_BPBLCD53_SHIFT 1
Kojto 90:cb3d968589d8 2951 #define LCD_WF8B_BPBLCD22_MASK 0x2u
Kojto 90:cb3d968589d8 2952 #define LCD_WF8B_BPBLCD22_SHIFT 1
Kojto 90:cb3d968589d8 2953 #define LCD_WF8B_BPBLCD47_MASK 0x2u
Kojto 90:cb3d968589d8 2954 #define LCD_WF8B_BPBLCD47_SHIFT 1
Kojto 90:cb3d968589d8 2955 #define LCD_WF8B_BPBLCD33_MASK 0x2u
Kojto 90:cb3d968589d8 2956 #define LCD_WF8B_BPBLCD33_SHIFT 1
Kojto 90:cb3d968589d8 2957 #define LCD_WF8B_BPBLCD2_MASK 0x2u
Kojto 90:cb3d968589d8 2958 #define LCD_WF8B_BPBLCD2_SHIFT 1
Kojto 90:cb3d968589d8 2959 #define LCD_WF8B_BPBLCD49_MASK 0x2u
Kojto 90:cb3d968589d8 2960 #define LCD_WF8B_BPBLCD49_SHIFT 1
Kojto 90:cb3d968589d8 2961 #define LCD_WF8B_BPBLCD0_MASK 0x2u
Kojto 90:cb3d968589d8 2962 #define LCD_WF8B_BPBLCD0_SHIFT 1
Kojto 90:cb3d968589d8 2963 #define LCD_WF8B_BPBLCD55_MASK 0x2u
Kojto 90:cb3d968589d8 2964 #define LCD_WF8B_BPBLCD55_SHIFT 1
Kojto 90:cb3d968589d8 2965 #define LCD_WF8B_BPBLCD56_MASK 0x2u
Kojto 90:cb3d968589d8 2966 #define LCD_WF8B_BPBLCD56_SHIFT 1
Kojto 90:cb3d968589d8 2967 #define LCD_WF8B_BPBLCD21_MASK 0x2u
Kojto 90:cb3d968589d8 2968 #define LCD_WF8B_BPBLCD21_SHIFT 1
Kojto 90:cb3d968589d8 2969 #define LCD_WF8B_BPBLCD6_MASK 0x2u
Kojto 90:cb3d968589d8 2970 #define LCD_WF8B_BPBLCD6_SHIFT 1
Kojto 90:cb3d968589d8 2971 #define LCD_WF8B_BPBLCD29_MASK 0x2u
Kojto 90:cb3d968589d8 2972 #define LCD_WF8B_BPBLCD29_SHIFT 1
Kojto 90:cb3d968589d8 2973 #define LCD_WF8B_BPBLCD25_MASK 0x2u
Kojto 90:cb3d968589d8 2974 #define LCD_WF8B_BPBLCD25_SHIFT 1
Kojto 90:cb3d968589d8 2975 #define LCD_WF8B_BPBLCD8_MASK 0x2u
Kojto 90:cb3d968589d8 2976 #define LCD_WF8B_BPBLCD8_SHIFT 1
Kojto 90:cb3d968589d8 2977 #define LCD_WF8B_BPBLCD54_MASK 0x2u
Kojto 90:cb3d968589d8 2978 #define LCD_WF8B_BPBLCD54_SHIFT 1
Kojto 90:cb3d968589d8 2979 #define LCD_WF8B_BPBLCD38_MASK 0x2u
Kojto 90:cb3d968589d8 2980 #define LCD_WF8B_BPBLCD38_SHIFT 1
Kojto 90:cb3d968589d8 2981 #define LCD_WF8B_BPBLCD43_MASK 0x2u
Kojto 90:cb3d968589d8 2982 #define LCD_WF8B_BPBLCD43_SHIFT 1
Kojto 90:cb3d968589d8 2983 #define LCD_WF8B_BPBLCD20_MASK 0x2u
Kojto 90:cb3d968589d8 2984 #define LCD_WF8B_BPBLCD20_SHIFT 1
Kojto 90:cb3d968589d8 2985 #define LCD_WF8B_BPBLCD9_MASK 0x2u
Kojto 90:cb3d968589d8 2986 #define LCD_WF8B_BPBLCD9_SHIFT 1
Kojto 90:cb3d968589d8 2987 #define LCD_WF8B_BPBLCD7_MASK 0x2u
Kojto 90:cb3d968589d8 2988 #define LCD_WF8B_BPBLCD7_SHIFT 1
Kojto 90:cb3d968589d8 2989 #define LCD_WF8B_BPBLCD50_MASK 0x2u
Kojto 90:cb3d968589d8 2990 #define LCD_WF8B_BPBLCD50_SHIFT 1
Kojto 90:cb3d968589d8 2991 #define LCD_WF8B_BPBLCD40_MASK 0x2u
Kojto 90:cb3d968589d8 2992 #define LCD_WF8B_BPBLCD40_SHIFT 1
Kojto 90:cb3d968589d8 2993 #define LCD_WF8B_BPBLCD63_MASK 0x2u
Kojto 90:cb3d968589d8 2994 #define LCD_WF8B_BPBLCD63_SHIFT 1
Kojto 90:cb3d968589d8 2995 #define LCD_WF8B_BPBLCD26_MASK 0x2u
Kojto 90:cb3d968589d8 2996 #define LCD_WF8B_BPBLCD26_SHIFT 1
Kojto 90:cb3d968589d8 2997 #define LCD_WF8B_BPBLCD12_MASK 0x2u
Kojto 90:cb3d968589d8 2998 #define LCD_WF8B_BPBLCD12_SHIFT 1
Kojto 90:cb3d968589d8 2999 #define LCD_WF8B_BPBLCD19_MASK 0x2u
Kojto 90:cb3d968589d8 3000 #define LCD_WF8B_BPBLCD19_SHIFT 1
Kojto 90:cb3d968589d8 3001 #define LCD_WF8B_BPBLCD34_MASK 0x2u
Kojto 90:cb3d968589d8 3002 #define LCD_WF8B_BPBLCD34_SHIFT 1
Kojto 90:cb3d968589d8 3003 #define LCD_WF8B_BPBLCD39_MASK 0x2u
Kojto 90:cb3d968589d8 3004 #define LCD_WF8B_BPBLCD39_SHIFT 1
Kojto 90:cb3d968589d8 3005 #define LCD_WF8B_BPBLCD59_MASK 0x2u
Kojto 90:cb3d968589d8 3006 #define LCD_WF8B_BPBLCD59_SHIFT 1
Kojto 90:cb3d968589d8 3007 #define LCD_WF8B_BPBLCD61_MASK 0x2u
Kojto 90:cb3d968589d8 3008 #define LCD_WF8B_BPBLCD61_SHIFT 1
Kojto 90:cb3d968589d8 3009 #define LCD_WF8B_BPBLCD37_MASK 0x2u
Kojto 90:cb3d968589d8 3010 #define LCD_WF8B_BPBLCD37_SHIFT 1
Kojto 90:cb3d968589d8 3011 #define LCD_WF8B_BPBLCD31_MASK 0x2u
Kojto 90:cb3d968589d8 3012 #define LCD_WF8B_BPBLCD31_SHIFT 1
Kojto 90:cb3d968589d8 3013 #define LCD_WF8B_BPBLCD58_MASK 0x2u
Kojto 90:cb3d968589d8 3014 #define LCD_WF8B_BPBLCD58_SHIFT 1
Kojto 90:cb3d968589d8 3015 #define LCD_WF8B_BPBLCD18_MASK 0x2u
Kojto 90:cb3d968589d8 3016 #define LCD_WF8B_BPBLCD18_SHIFT 1
Kojto 90:cb3d968589d8 3017 #define LCD_WF8B_BPBLCD45_MASK 0x2u
Kojto 90:cb3d968589d8 3018 #define LCD_WF8B_BPBLCD45_SHIFT 1
Kojto 90:cb3d968589d8 3019 #define LCD_WF8B_BPBLCD27_MASK 0x2u
Kojto 90:cb3d968589d8 3020 #define LCD_WF8B_BPBLCD27_SHIFT 1
Kojto 90:cb3d968589d8 3021 #define LCD_WF8B_BPBLCD14_MASK 0x2u
Kojto 90:cb3d968589d8 3022 #define LCD_WF8B_BPBLCD14_SHIFT 1
Kojto 90:cb3d968589d8 3023 #define LCD_WF8B_BPBLCD51_MASK 0x2u
Kojto 90:cb3d968589d8 3024 #define LCD_WF8B_BPBLCD51_SHIFT 1
Kojto 90:cb3d968589d8 3025 #define LCD_WF8B_BPBLCD52_MASK 0x2u
Kojto 90:cb3d968589d8 3026 #define LCD_WF8B_BPBLCD52_SHIFT 1
Kojto 90:cb3d968589d8 3027 #define LCD_WF8B_BPBLCD4_MASK 0x2u
Kojto 90:cb3d968589d8 3028 #define LCD_WF8B_BPBLCD4_SHIFT 1
Kojto 90:cb3d968589d8 3029 #define LCD_WF8B_BPBLCD35_MASK 0x2u
Kojto 90:cb3d968589d8 3030 #define LCD_WF8B_BPBLCD35_SHIFT 1
Kojto 90:cb3d968589d8 3031 #define LCD_WF8B_BPBLCD17_MASK 0x2u
Kojto 90:cb3d968589d8 3032 #define LCD_WF8B_BPBLCD17_SHIFT 1
Kojto 90:cb3d968589d8 3033 #define LCD_WF8B_BPBLCD41_MASK 0x2u
Kojto 90:cb3d968589d8 3034 #define LCD_WF8B_BPBLCD41_SHIFT 1
Kojto 90:cb3d968589d8 3035 #define LCD_WF8B_BPBLCD11_MASK 0x2u
Kojto 90:cb3d968589d8 3036 #define LCD_WF8B_BPBLCD11_SHIFT 1
Kojto 90:cb3d968589d8 3037 #define LCD_WF8B_BPBLCD46_MASK 0x2u
Kojto 90:cb3d968589d8 3038 #define LCD_WF8B_BPBLCD46_SHIFT 1
Kojto 90:cb3d968589d8 3039 #define LCD_WF8B_BPBLCD57_MASK 0x2u
Kojto 90:cb3d968589d8 3040 #define LCD_WF8B_BPBLCD57_SHIFT 1
Kojto 90:cb3d968589d8 3041 #define LCD_WF8B_BPBLCD42_MASK 0x2u
Kojto 90:cb3d968589d8 3042 #define LCD_WF8B_BPBLCD42_SHIFT 1
Kojto 90:cb3d968589d8 3043 #define LCD_WF8B_BPBLCD5_MASK 0x2u
Kojto 90:cb3d968589d8 3044 #define LCD_WF8B_BPBLCD5_SHIFT 1
Kojto 90:cb3d968589d8 3045 #define LCD_WF8B_BPBLCD3_MASK 0x2u
Kojto 90:cb3d968589d8 3046 #define LCD_WF8B_BPBLCD3_SHIFT 1
Kojto 90:cb3d968589d8 3047 #define LCD_WF8B_BPBLCD16_MASK 0x2u
Kojto 90:cb3d968589d8 3048 #define LCD_WF8B_BPBLCD16_SHIFT 1
Kojto 90:cb3d968589d8 3049 #define LCD_WF8B_BPBLCD13_MASK 0x2u
Kojto 90:cb3d968589d8 3050 #define LCD_WF8B_BPBLCD13_SHIFT 1
Kojto 90:cb3d968589d8 3051 #define LCD_WF8B_BPCLCD10_MASK 0x4u
Kojto 90:cb3d968589d8 3052 #define LCD_WF8B_BPCLCD10_SHIFT 2
Kojto 90:cb3d968589d8 3053 #define LCD_WF8B_BPCLCD55_MASK 0x4u
Kojto 90:cb3d968589d8 3054 #define LCD_WF8B_BPCLCD55_SHIFT 2
Kojto 90:cb3d968589d8 3055 #define LCD_WF8B_BPCLCD2_MASK 0x4u
Kojto 90:cb3d968589d8 3056 #define LCD_WF8B_BPCLCD2_SHIFT 2
Kojto 90:cb3d968589d8 3057 #define LCD_WF8B_BPCLCD23_MASK 0x4u
Kojto 90:cb3d968589d8 3058 #define LCD_WF8B_BPCLCD23_SHIFT 2
Kojto 90:cb3d968589d8 3059 #define LCD_WF8B_BPCLCD48_MASK 0x4u
Kojto 90:cb3d968589d8 3060 #define LCD_WF8B_BPCLCD48_SHIFT 2
Kojto 90:cb3d968589d8 3061 #define LCD_WF8B_BPCLCD24_MASK 0x4u
Kojto 90:cb3d968589d8 3062 #define LCD_WF8B_BPCLCD24_SHIFT 2
Kojto 90:cb3d968589d8 3063 #define LCD_WF8B_BPCLCD60_MASK 0x4u
Kojto 90:cb3d968589d8 3064 #define LCD_WF8B_BPCLCD60_SHIFT 2
Kojto 90:cb3d968589d8 3065 #define LCD_WF8B_BPCLCD47_MASK 0x4u
Kojto 90:cb3d968589d8 3066 #define LCD_WF8B_BPCLCD47_SHIFT 2
Kojto 90:cb3d968589d8 3067 #define LCD_WF8B_BPCLCD22_MASK 0x4u
Kojto 90:cb3d968589d8 3068 #define LCD_WF8B_BPCLCD22_SHIFT 2
Kojto 90:cb3d968589d8 3069 #define LCD_WF8B_BPCLCD8_MASK 0x4u
Kojto 90:cb3d968589d8 3070 #define LCD_WF8B_BPCLCD8_SHIFT 2
Kojto 90:cb3d968589d8 3071 #define LCD_WF8B_BPCLCD21_MASK 0x4u
Kojto 90:cb3d968589d8 3072 #define LCD_WF8B_BPCLCD21_SHIFT 2
Kojto 90:cb3d968589d8 3073 #define LCD_WF8B_BPCLCD49_MASK 0x4u
Kojto 90:cb3d968589d8 3074 #define LCD_WF8B_BPCLCD49_SHIFT 2
Kojto 90:cb3d968589d8 3075 #define LCD_WF8B_BPCLCD25_MASK 0x4u
Kojto 90:cb3d968589d8 3076 #define LCD_WF8B_BPCLCD25_SHIFT 2
Kojto 90:cb3d968589d8 3077 #define LCD_WF8B_BPCLCD1_MASK 0x4u
Kojto 90:cb3d968589d8 3078 #define LCD_WF8B_BPCLCD1_SHIFT 2
Kojto 90:cb3d968589d8 3079 #define LCD_WF8B_BPCLCD20_MASK 0x4u
Kojto 90:cb3d968589d8 3080 #define LCD_WF8B_BPCLCD20_SHIFT 2
Kojto 90:cb3d968589d8 3081 #define LCD_WF8B_BPCLCD50_MASK 0x4u
Kojto 90:cb3d968589d8 3082 #define LCD_WF8B_BPCLCD50_SHIFT 2
Kojto 90:cb3d968589d8 3083 #define LCD_WF8B_BPCLCD19_MASK 0x4u
Kojto 90:cb3d968589d8 3084 #define LCD_WF8B_BPCLCD19_SHIFT 2
Kojto 90:cb3d968589d8 3085 #define LCD_WF8B_BPCLCD26_MASK 0x4u
Kojto 90:cb3d968589d8 3086 #define LCD_WF8B_BPCLCD26_SHIFT 2
Kojto 90:cb3d968589d8 3087 #define LCD_WF8B_BPCLCD59_MASK 0x4u
Kojto 90:cb3d968589d8 3088 #define LCD_WF8B_BPCLCD59_SHIFT 2
Kojto 90:cb3d968589d8 3089 #define LCD_WF8B_BPCLCD61_MASK 0x4u
Kojto 90:cb3d968589d8 3090 #define LCD_WF8B_BPCLCD61_SHIFT 2
Kojto 90:cb3d968589d8 3091 #define LCD_WF8B_BPCLCD46_MASK 0x4u
Kojto 90:cb3d968589d8 3092 #define LCD_WF8B_BPCLCD46_SHIFT 2
Kojto 90:cb3d968589d8 3093 #define LCD_WF8B_BPCLCD18_MASK 0x4u
Kojto 90:cb3d968589d8 3094 #define LCD_WF8B_BPCLCD18_SHIFT 2
Kojto 90:cb3d968589d8 3095 #define LCD_WF8B_BPCLCD5_MASK 0x4u
Kojto 90:cb3d968589d8 3096 #define LCD_WF8B_BPCLCD5_SHIFT 2
Kojto 90:cb3d968589d8 3097 #define LCD_WF8B_BPCLCD63_MASK 0x4u
Kojto 90:cb3d968589d8 3098 #define LCD_WF8B_BPCLCD63_SHIFT 2
Kojto 90:cb3d968589d8 3099 #define LCD_WF8B_BPCLCD27_MASK 0x4u
Kojto 90:cb3d968589d8 3100 #define LCD_WF8B_BPCLCD27_SHIFT 2
Kojto 90:cb3d968589d8 3101 #define LCD_WF8B_BPCLCD17_MASK 0x4u
Kojto 90:cb3d968589d8 3102 #define LCD_WF8B_BPCLCD17_SHIFT 2
Kojto 90:cb3d968589d8 3103 #define LCD_WF8B_BPCLCD51_MASK 0x4u
Kojto 90:cb3d968589d8 3104 #define LCD_WF8B_BPCLCD51_SHIFT 2
Kojto 90:cb3d968589d8 3105 #define LCD_WF8B_BPCLCD9_MASK 0x4u
Kojto 90:cb3d968589d8 3106 #define LCD_WF8B_BPCLCD9_SHIFT 2
Kojto 90:cb3d968589d8 3107 #define LCD_WF8B_BPCLCD54_MASK 0x4u
Kojto 90:cb3d968589d8 3108 #define LCD_WF8B_BPCLCD54_SHIFT 2
Kojto 90:cb3d968589d8 3109 #define LCD_WF8B_BPCLCD15_MASK 0x4u
Kojto 90:cb3d968589d8 3110 #define LCD_WF8B_BPCLCD15_SHIFT 2
Kojto 90:cb3d968589d8 3111 #define LCD_WF8B_BPCLCD16_MASK 0x4u
Kojto 90:cb3d968589d8 3112 #define LCD_WF8B_BPCLCD16_SHIFT 2
Kojto 90:cb3d968589d8 3113 #define LCD_WF8B_BPCLCD14_MASK 0x4u
Kojto 90:cb3d968589d8 3114 #define LCD_WF8B_BPCLCD14_SHIFT 2
Kojto 90:cb3d968589d8 3115 #define LCD_WF8B_BPCLCD32_MASK 0x4u
Kojto 90:cb3d968589d8 3116 #define LCD_WF8B_BPCLCD32_SHIFT 2
Kojto 90:cb3d968589d8 3117 #define LCD_WF8B_BPCLCD28_MASK 0x4u
Kojto 90:cb3d968589d8 3118 #define LCD_WF8B_BPCLCD28_SHIFT 2
Kojto 90:cb3d968589d8 3119 #define LCD_WF8B_BPCLCD53_MASK 0x4u
Kojto 90:cb3d968589d8 3120 #define LCD_WF8B_BPCLCD53_SHIFT 2
Kojto 90:cb3d968589d8 3121 #define LCD_WF8B_BPCLCD33_MASK 0x4u
Kojto 90:cb3d968589d8 3122 #define LCD_WF8B_BPCLCD33_SHIFT 2
Kojto 90:cb3d968589d8 3123 #define LCD_WF8B_BPCLCD0_MASK 0x4u
Kojto 90:cb3d968589d8 3124 #define LCD_WF8B_BPCLCD0_SHIFT 2
Kojto 90:cb3d968589d8 3125 #define LCD_WF8B_BPCLCD43_MASK 0x4u
Kojto 90:cb3d968589d8 3126 #define LCD_WF8B_BPCLCD43_SHIFT 2
Kojto 90:cb3d968589d8 3127 #define LCD_WF8B_BPCLCD7_MASK 0x4u
Kojto 90:cb3d968589d8 3128 #define LCD_WF8B_BPCLCD7_SHIFT 2
Kojto 90:cb3d968589d8 3129 #define LCD_WF8B_BPCLCD4_MASK 0x4u
Kojto 90:cb3d968589d8 3130 #define LCD_WF8B_BPCLCD4_SHIFT 2
Kojto 90:cb3d968589d8 3131 #define LCD_WF8B_BPCLCD34_MASK 0x4u
Kojto 90:cb3d968589d8 3132 #define LCD_WF8B_BPCLCD34_SHIFT 2
Kojto 90:cb3d968589d8 3133 #define LCD_WF8B_BPCLCD29_MASK 0x4u
Kojto 90:cb3d968589d8 3134 #define LCD_WF8B_BPCLCD29_SHIFT 2
Kojto 90:cb3d968589d8 3135 #define LCD_WF8B_BPCLCD45_MASK 0x4u
Kojto 90:cb3d968589d8 3136 #define LCD_WF8B_BPCLCD45_SHIFT 2
Kojto 90:cb3d968589d8 3137 #define LCD_WF8B_BPCLCD57_MASK 0x4u
Kojto 90:cb3d968589d8 3138 #define LCD_WF8B_BPCLCD57_SHIFT 2
Kojto 90:cb3d968589d8 3139 #define LCD_WF8B_BPCLCD42_MASK 0x4u
Kojto 90:cb3d968589d8 3140 #define LCD_WF8B_BPCLCD42_SHIFT 2
Kojto 90:cb3d968589d8 3141 #define LCD_WF8B_BPCLCD35_MASK 0x4u
Kojto 90:cb3d968589d8 3142 #define LCD_WF8B_BPCLCD35_SHIFT 2
Kojto 90:cb3d968589d8 3143 #define LCD_WF8B_BPCLCD13_MASK 0x4u
Kojto 90:cb3d968589d8 3144 #define LCD_WF8B_BPCLCD13_SHIFT 2
Kojto 90:cb3d968589d8 3145 #define LCD_WF8B_BPCLCD36_MASK 0x4u
Kojto 90:cb3d968589d8 3146 #define LCD_WF8B_BPCLCD36_SHIFT 2
Kojto 90:cb3d968589d8 3147 #define LCD_WF8B_BPCLCD30_MASK 0x4u
Kojto 90:cb3d968589d8 3148 #define LCD_WF8B_BPCLCD30_SHIFT 2
Kojto 90:cb3d968589d8 3149 #define LCD_WF8B_BPCLCD52_MASK 0x4u
Kojto 90:cb3d968589d8 3150 #define LCD_WF8B_BPCLCD52_SHIFT 2
Kojto 90:cb3d968589d8 3151 #define LCD_WF8B_BPCLCD58_MASK 0x4u
Kojto 90:cb3d968589d8 3152 #define LCD_WF8B_BPCLCD58_SHIFT 2
Kojto 90:cb3d968589d8 3153 #define LCD_WF8B_BPCLCD41_MASK 0x4u
Kojto 90:cb3d968589d8 3154 #define LCD_WF8B_BPCLCD41_SHIFT 2
Kojto 90:cb3d968589d8 3155 #define LCD_WF8B_BPCLCD37_MASK 0x4u
Kojto 90:cb3d968589d8 3156 #define LCD_WF8B_BPCLCD37_SHIFT 2
Kojto 90:cb3d968589d8 3157 #define LCD_WF8B_BPCLCD3_MASK 0x4u
Kojto 90:cb3d968589d8 3158 #define LCD_WF8B_BPCLCD3_SHIFT 2
Kojto 90:cb3d968589d8 3159 #define LCD_WF8B_BPCLCD12_MASK 0x4u
Kojto 90:cb3d968589d8 3160 #define LCD_WF8B_BPCLCD12_SHIFT 2
Kojto 90:cb3d968589d8 3161 #define LCD_WF8B_BPCLCD11_MASK 0x4u
Kojto 90:cb3d968589d8 3162 #define LCD_WF8B_BPCLCD11_SHIFT 2
Kojto 90:cb3d968589d8 3163 #define LCD_WF8B_BPCLCD38_MASK 0x4u
Kojto 90:cb3d968589d8 3164 #define LCD_WF8B_BPCLCD38_SHIFT 2
Kojto 90:cb3d968589d8 3165 #define LCD_WF8B_BPCLCD44_MASK 0x4u
Kojto 90:cb3d968589d8 3166 #define LCD_WF8B_BPCLCD44_SHIFT 2
Kojto 90:cb3d968589d8 3167 #define LCD_WF8B_BPCLCD31_MASK 0x4u
Kojto 90:cb3d968589d8 3168 #define LCD_WF8B_BPCLCD31_SHIFT 2
Kojto 90:cb3d968589d8 3169 #define LCD_WF8B_BPCLCD40_MASK 0x4u
Kojto 90:cb3d968589d8 3170 #define LCD_WF8B_BPCLCD40_SHIFT 2
Kojto 90:cb3d968589d8 3171 #define LCD_WF8B_BPCLCD62_MASK 0x4u
Kojto 90:cb3d968589d8 3172 #define LCD_WF8B_BPCLCD62_SHIFT 2
Kojto 90:cb3d968589d8 3173 #define LCD_WF8B_BPCLCD56_MASK 0x4u
Kojto 90:cb3d968589d8 3174 #define LCD_WF8B_BPCLCD56_SHIFT 2
Kojto 90:cb3d968589d8 3175 #define LCD_WF8B_BPCLCD39_MASK 0x4u
Kojto 90:cb3d968589d8 3176 #define LCD_WF8B_BPCLCD39_SHIFT 2
Kojto 90:cb3d968589d8 3177 #define LCD_WF8B_BPCLCD6_MASK 0x4u
Kojto 90:cb3d968589d8 3178 #define LCD_WF8B_BPCLCD6_SHIFT 2
Kojto 90:cb3d968589d8 3179 #define LCD_WF8B_BPDLCD47_MASK 0x8u
Kojto 90:cb3d968589d8 3180 #define LCD_WF8B_BPDLCD47_SHIFT 3
Kojto 90:cb3d968589d8 3181 #define LCD_WF8B_BPDLCD23_MASK 0x8u
Kojto 90:cb3d968589d8 3182 #define LCD_WF8B_BPDLCD23_SHIFT 3
Kojto 90:cb3d968589d8 3183 #define LCD_WF8B_BPDLCD48_MASK 0x8u
Kojto 90:cb3d968589d8 3184 #define LCD_WF8B_BPDLCD48_SHIFT 3
Kojto 90:cb3d968589d8 3185 #define LCD_WF8B_BPDLCD24_MASK 0x8u
Kojto 90:cb3d968589d8 3186 #define LCD_WF8B_BPDLCD24_SHIFT 3
Kojto 90:cb3d968589d8 3187 #define LCD_WF8B_BPDLCD15_MASK 0x8u
Kojto 90:cb3d968589d8 3188 #define LCD_WF8B_BPDLCD15_SHIFT 3
Kojto 90:cb3d968589d8 3189 #define LCD_WF8B_BPDLCD22_MASK 0x8u
Kojto 90:cb3d968589d8 3190 #define LCD_WF8B_BPDLCD22_SHIFT 3
Kojto 90:cb3d968589d8 3191 #define LCD_WF8B_BPDLCD60_MASK 0x8u
Kojto 90:cb3d968589d8 3192 #define LCD_WF8B_BPDLCD60_SHIFT 3
Kojto 90:cb3d968589d8 3193 #define LCD_WF8B_BPDLCD10_MASK 0x8u
Kojto 90:cb3d968589d8 3194 #define LCD_WF8B_BPDLCD10_SHIFT 3
Kojto 90:cb3d968589d8 3195 #define LCD_WF8B_BPDLCD21_MASK 0x8u
Kojto 90:cb3d968589d8 3196 #define LCD_WF8B_BPDLCD21_SHIFT 3
Kojto 90:cb3d968589d8 3197 #define LCD_WF8B_BPDLCD49_MASK 0x8u
Kojto 90:cb3d968589d8 3198 #define LCD_WF8B_BPDLCD49_SHIFT 3
Kojto 90:cb3d968589d8 3199 #define LCD_WF8B_BPDLCD1_MASK 0x8u
Kojto 90:cb3d968589d8 3200 #define LCD_WF8B_BPDLCD1_SHIFT 3
Kojto 90:cb3d968589d8 3201 #define LCD_WF8B_BPDLCD25_MASK 0x8u
Kojto 90:cb3d968589d8 3202 #define LCD_WF8B_BPDLCD25_SHIFT 3
Kojto 90:cb3d968589d8 3203 #define LCD_WF8B_BPDLCD20_MASK 0x8u
Kojto 90:cb3d968589d8 3204 #define LCD_WF8B_BPDLCD20_SHIFT 3
Kojto 90:cb3d968589d8 3205 #define LCD_WF8B_BPDLCD2_MASK 0x8u
Kojto 90:cb3d968589d8 3206 #define LCD_WF8B_BPDLCD2_SHIFT 3
Kojto 90:cb3d968589d8 3207 #define LCD_WF8B_BPDLCD55_MASK 0x8u
Kojto 90:cb3d968589d8 3208 #define LCD_WF8B_BPDLCD55_SHIFT 3
Kojto 90:cb3d968589d8 3209 #define LCD_WF8B_BPDLCD59_MASK 0x8u
Kojto 90:cb3d968589d8 3210 #define LCD_WF8B_BPDLCD59_SHIFT 3
Kojto 90:cb3d968589d8 3211 #define LCD_WF8B_BPDLCD5_MASK 0x8u
Kojto 90:cb3d968589d8 3212 #define LCD_WF8B_BPDLCD5_SHIFT 3
Kojto 90:cb3d968589d8 3213 #define LCD_WF8B_BPDLCD19_MASK 0x8u
Kojto 90:cb3d968589d8 3214 #define LCD_WF8B_BPDLCD19_SHIFT 3
Kojto 90:cb3d968589d8 3215 #define LCD_WF8B_BPDLCD6_MASK 0x8u
Kojto 90:cb3d968589d8 3216 #define LCD_WF8B_BPDLCD6_SHIFT 3
Kojto 90:cb3d968589d8 3217 #define LCD_WF8B_BPDLCD26_MASK 0x8u
Kojto 90:cb3d968589d8 3218 #define LCD_WF8B_BPDLCD26_SHIFT 3
Kojto 90:cb3d968589d8 3219 #define LCD_WF8B_BPDLCD0_MASK 0x8u
Kojto 90:cb3d968589d8 3220 #define LCD_WF8B_BPDLCD0_SHIFT 3
Kojto 90:cb3d968589d8 3221 #define LCD_WF8B_BPDLCD50_MASK 0x8u
Kojto 90:cb3d968589d8 3222 #define LCD_WF8B_BPDLCD50_SHIFT 3
Kojto 90:cb3d968589d8 3223 #define LCD_WF8B_BPDLCD46_MASK 0x8u
Kojto 90:cb3d968589d8 3224 #define LCD_WF8B_BPDLCD46_SHIFT 3
Kojto 90:cb3d968589d8 3225 #define LCD_WF8B_BPDLCD18_MASK 0x8u
Kojto 90:cb3d968589d8 3226 #define LCD_WF8B_BPDLCD18_SHIFT 3
Kojto 90:cb3d968589d8 3227 #define LCD_WF8B_BPDLCD61_MASK 0x8u
Kojto 90:cb3d968589d8 3228 #define LCD_WF8B_BPDLCD61_SHIFT 3
Kojto 90:cb3d968589d8 3229 #define LCD_WF8B_BPDLCD9_MASK 0x8u
Kojto 90:cb3d968589d8 3230 #define LCD_WF8B_BPDLCD9_SHIFT 3
Kojto 90:cb3d968589d8 3231 #define LCD_WF8B_BPDLCD17_MASK 0x8u
Kojto 90:cb3d968589d8 3232 #define LCD_WF8B_BPDLCD17_SHIFT 3
Kojto 90:cb3d968589d8 3233 #define LCD_WF8B_BPDLCD27_MASK 0x8u
Kojto 90:cb3d968589d8 3234 #define LCD_WF8B_BPDLCD27_SHIFT 3
Kojto 90:cb3d968589d8 3235 #define LCD_WF8B_BPDLCD53_MASK 0x8u
Kojto 90:cb3d968589d8 3236 #define LCD_WF8B_BPDLCD53_SHIFT 3
Kojto 90:cb3d968589d8 3237 #define LCD_WF8B_BPDLCD51_MASK 0x8u
Kojto 90:cb3d968589d8 3238 #define LCD_WF8B_BPDLCD51_SHIFT 3
Kojto 90:cb3d968589d8 3239 #define LCD_WF8B_BPDLCD54_MASK 0x8u
Kojto 90:cb3d968589d8 3240 #define LCD_WF8B_BPDLCD54_SHIFT 3
Kojto 90:cb3d968589d8 3241 #define LCD_WF8B_BPDLCD13_MASK 0x8u
Kojto 90:cb3d968589d8 3242 #define LCD_WF8B_BPDLCD13_SHIFT 3
Kojto 90:cb3d968589d8 3243 #define LCD_WF8B_BPDLCD16_MASK 0x8u
Kojto 90:cb3d968589d8 3244 #define LCD_WF8B_BPDLCD16_SHIFT 3
Kojto 90:cb3d968589d8 3245 #define LCD_WF8B_BPDLCD32_MASK 0x8u
Kojto 90:cb3d968589d8 3246 #define LCD_WF8B_BPDLCD32_SHIFT 3
Kojto 90:cb3d968589d8 3247 #define LCD_WF8B_BPDLCD14_MASK 0x8u
Kojto 90:cb3d968589d8 3248 #define LCD_WF8B_BPDLCD14_SHIFT 3
Kojto 90:cb3d968589d8 3249 #define LCD_WF8B_BPDLCD28_MASK 0x8u
Kojto 90:cb3d968589d8 3250 #define LCD_WF8B_BPDLCD28_SHIFT 3
Kojto 90:cb3d968589d8 3251 #define LCD_WF8B_BPDLCD43_MASK 0x8u
Kojto 90:cb3d968589d8 3252 #define LCD_WF8B_BPDLCD43_SHIFT 3
Kojto 90:cb3d968589d8 3253 #define LCD_WF8B_BPDLCD4_MASK 0x8u
Kojto 90:cb3d968589d8 3254 #define LCD_WF8B_BPDLCD4_SHIFT 3
Kojto 90:cb3d968589d8 3255 #define LCD_WF8B_BPDLCD45_MASK 0x8u
Kojto 90:cb3d968589d8 3256 #define LCD_WF8B_BPDLCD45_SHIFT 3
Kojto 90:cb3d968589d8 3257 #define LCD_WF8B_BPDLCD8_MASK 0x8u
Kojto 90:cb3d968589d8 3258 #define LCD_WF8B_BPDLCD8_SHIFT 3
Kojto 90:cb3d968589d8 3259 #define LCD_WF8B_BPDLCD62_MASK 0x8u
Kojto 90:cb3d968589d8 3260 #define LCD_WF8B_BPDLCD62_SHIFT 3
Kojto 90:cb3d968589d8 3261 #define LCD_WF8B_BPDLCD33_MASK 0x8u
Kojto 90:cb3d968589d8 3262 #define LCD_WF8B_BPDLCD33_SHIFT 3
Kojto 90:cb3d968589d8 3263 #define LCD_WF8B_BPDLCD34_MASK 0x8u
Kojto 90:cb3d968589d8 3264 #define LCD_WF8B_BPDLCD34_SHIFT 3
Kojto 90:cb3d968589d8 3265 #define LCD_WF8B_BPDLCD29_MASK 0x8u
Kojto 90:cb3d968589d8 3266 #define LCD_WF8B_BPDLCD29_SHIFT 3
Kojto 90:cb3d968589d8 3267 #define LCD_WF8B_BPDLCD58_MASK 0x8u
Kojto 90:cb3d968589d8 3268 #define LCD_WF8B_BPDLCD58_SHIFT 3
Kojto 90:cb3d968589d8 3269 #define LCD_WF8B_BPDLCD57_MASK 0x8u
Kojto 90:cb3d968589d8 3270 #define LCD_WF8B_BPDLCD57_SHIFT 3
Kojto 90:cb3d968589d8 3271 #define LCD_WF8B_BPDLCD42_MASK 0x8u
Kojto 90:cb3d968589d8 3272 #define LCD_WF8B_BPDLCD42_SHIFT 3
Kojto 90:cb3d968589d8 3273 #define LCD_WF8B_BPDLCD35_MASK 0x8u
Kojto 90:cb3d968589d8 3274 #define LCD_WF8B_BPDLCD35_SHIFT 3
Kojto 90:cb3d968589d8 3275 #define LCD_WF8B_BPDLCD52_MASK 0x8u
Kojto 90:cb3d968589d8 3276 #define LCD_WF8B_BPDLCD52_SHIFT 3
Kojto 90:cb3d968589d8 3277 #define LCD_WF8B_BPDLCD7_MASK 0x8u
Kojto 90:cb3d968589d8 3278 #define LCD_WF8B_BPDLCD7_SHIFT 3
Kojto 90:cb3d968589d8 3279 #define LCD_WF8B_BPDLCD36_MASK 0x8u
Kojto 90:cb3d968589d8 3280 #define LCD_WF8B_BPDLCD36_SHIFT 3
Kojto 90:cb3d968589d8 3281 #define LCD_WF8B_BPDLCD30_MASK 0x8u
Kojto 90:cb3d968589d8 3282 #define LCD_WF8B_BPDLCD30_SHIFT 3
Kojto 90:cb3d968589d8 3283 #define LCD_WF8B_BPDLCD41_MASK 0x8u
Kojto 90:cb3d968589d8 3284 #define LCD_WF8B_BPDLCD41_SHIFT 3
Kojto 90:cb3d968589d8 3285 #define LCD_WF8B_BPDLCD37_MASK 0x8u
Kojto 90:cb3d968589d8 3286 #define LCD_WF8B_BPDLCD37_SHIFT 3
Kojto 90:cb3d968589d8 3287 #define LCD_WF8B_BPDLCD44_MASK 0x8u
Kojto 90:cb3d968589d8 3288 #define LCD_WF8B_BPDLCD44_SHIFT 3
Kojto 90:cb3d968589d8 3289 #define LCD_WF8B_BPDLCD63_MASK 0x8u
Kojto 90:cb3d968589d8 3290 #define LCD_WF8B_BPDLCD63_SHIFT 3
Kojto 90:cb3d968589d8 3291 #define LCD_WF8B_BPDLCD38_MASK 0x8u
Kojto 90:cb3d968589d8 3292 #define LCD_WF8B_BPDLCD38_SHIFT 3
Kojto 90:cb3d968589d8 3293 #define LCD_WF8B_BPDLCD56_MASK 0x8u
Kojto 90:cb3d968589d8 3294 #define LCD_WF8B_BPDLCD56_SHIFT 3
Kojto 90:cb3d968589d8 3295 #define LCD_WF8B_BPDLCD40_MASK 0x8u
Kojto 90:cb3d968589d8 3296 #define LCD_WF8B_BPDLCD40_SHIFT 3
Kojto 90:cb3d968589d8 3297 #define LCD_WF8B_BPDLCD31_MASK 0x8u
Kojto 90:cb3d968589d8 3298 #define LCD_WF8B_BPDLCD31_SHIFT 3
Kojto 90:cb3d968589d8 3299 #define LCD_WF8B_BPDLCD12_MASK 0x8u
Kojto 90:cb3d968589d8 3300 #define LCD_WF8B_BPDLCD12_SHIFT 3
Kojto 90:cb3d968589d8 3301 #define LCD_WF8B_BPDLCD39_MASK 0x8u
Kojto 90:cb3d968589d8 3302 #define LCD_WF8B_BPDLCD39_SHIFT 3
Kojto 90:cb3d968589d8 3303 #define LCD_WF8B_BPDLCD3_MASK 0x8u
Kojto 90:cb3d968589d8 3304 #define LCD_WF8B_BPDLCD3_SHIFT 3
Kojto 90:cb3d968589d8 3305 #define LCD_WF8B_BPDLCD11_MASK 0x8u
Kojto 90:cb3d968589d8 3306 #define LCD_WF8B_BPDLCD11_SHIFT 3
Kojto 90:cb3d968589d8 3307 #define LCD_WF8B_BPELCD12_MASK 0x10u
Kojto 90:cb3d968589d8 3308 #define LCD_WF8B_BPELCD12_SHIFT 4
Kojto 90:cb3d968589d8 3309 #define LCD_WF8B_BPELCD39_MASK 0x10u
Kojto 90:cb3d968589d8 3310 #define LCD_WF8B_BPELCD39_SHIFT 4
Kojto 90:cb3d968589d8 3311 #define LCD_WF8B_BPELCD3_MASK 0x10u
Kojto 90:cb3d968589d8 3312 #define LCD_WF8B_BPELCD3_SHIFT 4
Kojto 90:cb3d968589d8 3313 #define LCD_WF8B_BPELCD38_MASK 0x10u
Kojto 90:cb3d968589d8 3314 #define LCD_WF8B_BPELCD38_SHIFT 4
Kojto 90:cb3d968589d8 3315 #define LCD_WF8B_BPELCD40_MASK 0x10u
Kojto 90:cb3d968589d8 3316 #define LCD_WF8B_BPELCD40_SHIFT 4
Kojto 90:cb3d968589d8 3317 #define LCD_WF8B_BPELCD37_MASK 0x10u
Kojto 90:cb3d968589d8 3318 #define LCD_WF8B_BPELCD37_SHIFT 4
Kojto 90:cb3d968589d8 3319 #define LCD_WF8B_BPELCD41_MASK 0x10u
Kojto 90:cb3d968589d8 3320 #define LCD_WF8B_BPELCD41_SHIFT 4
Kojto 90:cb3d968589d8 3321 #define LCD_WF8B_BPELCD36_MASK 0x10u
Kojto 90:cb3d968589d8 3322 #define LCD_WF8B_BPELCD36_SHIFT 4
Kojto 90:cb3d968589d8 3323 #define LCD_WF8B_BPELCD8_MASK 0x10u
Kojto 90:cb3d968589d8 3324 #define LCD_WF8B_BPELCD8_SHIFT 4
Kojto 90:cb3d968589d8 3325 #define LCD_WF8B_BPELCD35_MASK 0x10u
Kojto 90:cb3d968589d8 3326 #define LCD_WF8B_BPELCD35_SHIFT 4
Kojto 90:cb3d968589d8 3327 #define LCD_WF8B_BPELCD42_MASK 0x10u
Kojto 90:cb3d968589d8 3328 #define LCD_WF8B_BPELCD42_SHIFT 4
Kojto 90:cb3d968589d8 3329 #define LCD_WF8B_BPELCD34_MASK 0x10u
Kojto 90:cb3d968589d8 3330 #define LCD_WF8B_BPELCD34_SHIFT 4
Kojto 90:cb3d968589d8 3331 #define LCD_WF8B_BPELCD33_MASK 0x10u
Kojto 90:cb3d968589d8 3332 #define LCD_WF8B_BPELCD33_SHIFT 4
Kojto 90:cb3d968589d8 3333 #define LCD_WF8B_BPELCD11_MASK 0x10u
Kojto 90:cb3d968589d8 3334 #define LCD_WF8B_BPELCD11_SHIFT 4
Kojto 90:cb3d968589d8 3335 #define LCD_WF8B_BPELCD43_MASK 0x10u
Kojto 90:cb3d968589d8 3336 #define LCD_WF8B_BPELCD43_SHIFT 4
Kojto 90:cb3d968589d8 3337 #define LCD_WF8B_BPELCD32_MASK 0x10u
Kojto 90:cb3d968589d8 3338 #define LCD_WF8B_BPELCD32_SHIFT 4
Kojto 90:cb3d968589d8 3339 #define LCD_WF8B_BPELCD31_MASK 0x10u
Kojto 90:cb3d968589d8 3340 #define LCD_WF8B_BPELCD31_SHIFT 4
Kojto 90:cb3d968589d8 3341 #define LCD_WF8B_BPELCD44_MASK 0x10u
Kojto 90:cb3d968589d8 3342 #define LCD_WF8B_BPELCD44_SHIFT 4
Kojto 90:cb3d968589d8 3343 #define LCD_WF8B_BPELCD30_MASK 0x10u
Kojto 90:cb3d968589d8 3344 #define LCD_WF8B_BPELCD30_SHIFT 4
Kojto 90:cb3d968589d8 3345 #define LCD_WF8B_BPELCD29_MASK 0x10u
Kojto 90:cb3d968589d8 3346 #define LCD_WF8B_BPELCD29_SHIFT 4
Kojto 90:cb3d968589d8 3347 #define LCD_WF8B_BPELCD7_MASK 0x10u
Kojto 90:cb3d968589d8 3348 #define LCD_WF8B_BPELCD7_SHIFT 4
Kojto 90:cb3d968589d8 3349 #define LCD_WF8B_BPELCD45_MASK 0x10u
Kojto 90:cb3d968589d8 3350 #define LCD_WF8B_BPELCD45_SHIFT 4
Kojto 90:cb3d968589d8 3351 #define LCD_WF8B_BPELCD28_MASK 0x10u
Kojto 90:cb3d968589d8 3352 #define LCD_WF8B_BPELCD28_SHIFT 4
Kojto 90:cb3d968589d8 3353 #define LCD_WF8B_BPELCD2_MASK 0x10u
Kojto 90:cb3d968589d8 3354 #define LCD_WF8B_BPELCD2_SHIFT 4
Kojto 90:cb3d968589d8 3355 #define LCD_WF8B_BPELCD27_MASK 0x10u
Kojto 90:cb3d968589d8 3356 #define LCD_WF8B_BPELCD27_SHIFT 4
Kojto 90:cb3d968589d8 3357 #define LCD_WF8B_BPELCD46_MASK 0x10u
Kojto 90:cb3d968589d8 3358 #define LCD_WF8B_BPELCD46_SHIFT 4
Kojto 90:cb3d968589d8 3359 #define LCD_WF8B_BPELCD26_MASK 0x10u
Kojto 90:cb3d968589d8 3360 #define LCD_WF8B_BPELCD26_SHIFT 4
Kojto 90:cb3d968589d8 3361 #define LCD_WF8B_BPELCD10_MASK 0x10u
Kojto 90:cb3d968589d8 3362 #define LCD_WF8B_BPELCD10_SHIFT 4
Kojto 90:cb3d968589d8 3363 #define LCD_WF8B_BPELCD13_MASK 0x10u
Kojto 90:cb3d968589d8 3364 #define LCD_WF8B_BPELCD13_SHIFT 4
Kojto 90:cb3d968589d8 3365 #define LCD_WF8B_BPELCD25_MASK 0x10u
Kojto 90:cb3d968589d8 3366 #define LCD_WF8B_BPELCD25_SHIFT 4
Kojto 90:cb3d968589d8 3367 #define LCD_WF8B_BPELCD5_MASK 0x10u
Kojto 90:cb3d968589d8 3368 #define LCD_WF8B_BPELCD5_SHIFT 4
Kojto 90:cb3d968589d8 3369 #define LCD_WF8B_BPELCD24_MASK 0x10u
Kojto 90:cb3d968589d8 3370 #define LCD_WF8B_BPELCD24_SHIFT 4
Kojto 90:cb3d968589d8 3371 #define LCD_WF8B_BPELCD47_MASK 0x10u
Kojto 90:cb3d968589d8 3372 #define LCD_WF8B_BPELCD47_SHIFT 4
Kojto 90:cb3d968589d8 3373 #define LCD_WF8B_BPELCD23_MASK 0x10u
Kojto 90:cb3d968589d8 3374 #define LCD_WF8B_BPELCD23_SHIFT 4
Kojto 90:cb3d968589d8 3375 #define LCD_WF8B_BPELCD22_MASK 0x10u
Kojto 90:cb3d968589d8 3376 #define LCD_WF8B_BPELCD22_SHIFT 4
Kojto 90:cb3d968589d8 3377 #define LCD_WF8B_BPELCD48_MASK 0x10u
Kojto 90:cb3d968589d8 3378 #define LCD_WF8B_BPELCD48_SHIFT 4
Kojto 90:cb3d968589d8 3379 #define LCD_WF8B_BPELCD21_MASK 0x10u
Kojto 90:cb3d968589d8 3380 #define LCD_WF8B_BPELCD21_SHIFT 4
Kojto 90:cb3d968589d8 3381 #define LCD_WF8B_BPELCD49_MASK 0x10u
Kojto 90:cb3d968589d8 3382 #define LCD_WF8B_BPELCD49_SHIFT 4
Kojto 90:cb3d968589d8 3383 #define LCD_WF8B_BPELCD20_MASK 0x10u
Kojto 90:cb3d968589d8 3384 #define LCD_WF8B_BPELCD20_SHIFT 4
Kojto 90:cb3d968589d8 3385 #define LCD_WF8B_BPELCD19_MASK 0x10u
Kojto 90:cb3d968589d8 3386 #define LCD_WF8B_BPELCD19_SHIFT 4
Kojto 90:cb3d968589d8 3387 #define LCD_WF8B_BPELCD9_MASK 0x10u
Kojto 90:cb3d968589d8 3388 #define LCD_WF8B_BPELCD9_SHIFT 4
Kojto 90:cb3d968589d8 3389 #define LCD_WF8B_BPELCD50_MASK 0x10u
Kojto 90:cb3d968589d8 3390 #define LCD_WF8B_BPELCD50_SHIFT 4
Kojto 90:cb3d968589d8 3391 #define LCD_WF8B_BPELCD18_MASK 0x10u
Kojto 90:cb3d968589d8 3392 #define LCD_WF8B_BPELCD18_SHIFT 4
Kojto 90:cb3d968589d8 3393 #define LCD_WF8B_BPELCD6_MASK 0x10u
Kojto 90:cb3d968589d8 3394 #define LCD_WF8B_BPELCD6_SHIFT 4
Kojto 90:cb3d968589d8 3395 #define LCD_WF8B_BPELCD17_MASK 0x10u
Kojto 90:cb3d968589d8 3396 #define LCD_WF8B_BPELCD17_SHIFT 4
Kojto 90:cb3d968589d8 3397 #define LCD_WF8B_BPELCD51_MASK 0x10u
Kojto 90:cb3d968589d8 3398 #define LCD_WF8B_BPELCD51_SHIFT 4
Kojto 90:cb3d968589d8 3399 #define LCD_WF8B_BPELCD16_MASK 0x10u
Kojto 90:cb3d968589d8 3400 #define LCD_WF8B_BPELCD16_SHIFT 4
Kojto 90:cb3d968589d8 3401 #define LCD_WF8B_BPELCD56_MASK 0x10u
Kojto 90:cb3d968589d8 3402 #define LCD_WF8B_BPELCD56_SHIFT 4
Kojto 90:cb3d968589d8 3403 #define LCD_WF8B_BPELCD57_MASK 0x10u
Kojto 90:cb3d968589d8 3404 #define LCD_WF8B_BPELCD57_SHIFT 4
Kojto 90:cb3d968589d8 3405 #define LCD_WF8B_BPELCD52_MASK 0x10u
Kojto 90:cb3d968589d8 3406 #define LCD_WF8B_BPELCD52_SHIFT 4
Kojto 90:cb3d968589d8 3407 #define LCD_WF8B_BPELCD1_MASK 0x10u
Kojto 90:cb3d968589d8 3408 #define LCD_WF8B_BPELCD1_SHIFT 4
Kojto 90:cb3d968589d8 3409 #define LCD_WF8B_BPELCD58_MASK 0x10u
Kojto 90:cb3d968589d8 3410 #define LCD_WF8B_BPELCD58_SHIFT 4
Kojto 90:cb3d968589d8 3411 #define LCD_WF8B_BPELCD59_MASK 0x10u
Kojto 90:cb3d968589d8 3412 #define LCD_WF8B_BPELCD59_SHIFT 4
Kojto 90:cb3d968589d8 3413 #define LCD_WF8B_BPELCD53_MASK 0x10u
Kojto 90:cb3d968589d8 3414 #define LCD_WF8B_BPELCD53_SHIFT 4
Kojto 90:cb3d968589d8 3415 #define LCD_WF8B_BPELCD14_MASK 0x10u
Kojto 90:cb3d968589d8 3416 #define LCD_WF8B_BPELCD14_SHIFT 4
Kojto 90:cb3d968589d8 3417 #define LCD_WF8B_BPELCD0_MASK 0x10u
Kojto 90:cb3d968589d8 3418 #define LCD_WF8B_BPELCD0_SHIFT 4
Kojto 90:cb3d968589d8 3419 #define LCD_WF8B_BPELCD60_MASK 0x10u
Kojto 90:cb3d968589d8 3420 #define LCD_WF8B_BPELCD60_SHIFT 4
Kojto 90:cb3d968589d8 3421 #define LCD_WF8B_BPELCD15_MASK 0x10u
Kojto 90:cb3d968589d8 3422 #define LCD_WF8B_BPELCD15_SHIFT 4
Kojto 90:cb3d968589d8 3423 #define LCD_WF8B_BPELCD61_MASK 0x10u
Kojto 90:cb3d968589d8 3424 #define LCD_WF8B_BPELCD61_SHIFT 4
Kojto 90:cb3d968589d8 3425 #define LCD_WF8B_BPELCD54_MASK 0x10u
Kojto 90:cb3d968589d8 3426 #define LCD_WF8B_BPELCD54_SHIFT 4
Kojto 90:cb3d968589d8 3427 #define LCD_WF8B_BPELCD62_MASK 0x10u
Kojto 90:cb3d968589d8 3428 #define LCD_WF8B_BPELCD62_SHIFT 4
Kojto 90:cb3d968589d8 3429 #define LCD_WF8B_BPELCD63_MASK 0x10u
Kojto 90:cb3d968589d8 3430 #define LCD_WF8B_BPELCD63_SHIFT 4
Kojto 90:cb3d968589d8 3431 #define LCD_WF8B_BPELCD55_MASK 0x10u
Kojto 90:cb3d968589d8 3432 #define LCD_WF8B_BPELCD55_SHIFT 4
Kojto 90:cb3d968589d8 3433 #define LCD_WF8B_BPELCD4_MASK 0x10u
Kojto 90:cb3d968589d8 3434 #define LCD_WF8B_BPELCD4_SHIFT 4
Kojto 90:cb3d968589d8 3435 #define LCD_WF8B_BPFLCD13_MASK 0x20u
Kojto 90:cb3d968589d8 3436 #define LCD_WF8B_BPFLCD13_SHIFT 5
Kojto 90:cb3d968589d8 3437 #define LCD_WF8B_BPFLCD39_MASK 0x20u
Kojto 90:cb3d968589d8 3438 #define LCD_WF8B_BPFLCD39_SHIFT 5
Kojto 90:cb3d968589d8 3439 #define LCD_WF8B_BPFLCD55_MASK 0x20u
Kojto 90:cb3d968589d8 3440 #define LCD_WF8B_BPFLCD55_SHIFT 5
Kojto 90:cb3d968589d8 3441 #define LCD_WF8B_BPFLCD47_MASK 0x20u
Kojto 90:cb3d968589d8 3442 #define LCD_WF8B_BPFLCD47_SHIFT 5
Kojto 90:cb3d968589d8 3443 #define LCD_WF8B_BPFLCD63_MASK 0x20u
Kojto 90:cb3d968589d8 3444 #define LCD_WF8B_BPFLCD63_SHIFT 5
Kojto 90:cb3d968589d8 3445 #define LCD_WF8B_BPFLCD43_MASK 0x20u
Kojto 90:cb3d968589d8 3446 #define LCD_WF8B_BPFLCD43_SHIFT 5
Kojto 90:cb3d968589d8 3447 #define LCD_WF8B_BPFLCD5_MASK 0x20u
Kojto 90:cb3d968589d8 3448 #define LCD_WF8B_BPFLCD5_SHIFT 5
Kojto 90:cb3d968589d8 3449 #define LCD_WF8B_BPFLCD62_MASK 0x20u
Kojto 90:cb3d968589d8 3450 #define LCD_WF8B_BPFLCD62_SHIFT 5
Kojto 90:cb3d968589d8 3451 #define LCD_WF8B_BPFLCD14_MASK 0x20u
Kojto 90:cb3d968589d8 3452 #define LCD_WF8B_BPFLCD14_SHIFT 5
Kojto 90:cb3d968589d8 3453 #define LCD_WF8B_BPFLCD24_MASK 0x20u
Kojto 90:cb3d968589d8 3454 #define LCD_WF8B_BPFLCD24_SHIFT 5
Kojto 90:cb3d968589d8 3455 #define LCD_WF8B_BPFLCD54_MASK 0x20u
Kojto 90:cb3d968589d8 3456 #define LCD_WF8B_BPFLCD54_SHIFT 5
Kojto 90:cb3d968589d8 3457 #define LCD_WF8B_BPFLCD15_MASK 0x20u
Kojto 90:cb3d968589d8 3458 #define LCD_WF8B_BPFLCD15_SHIFT 5
Kojto 90:cb3d968589d8 3459 #define LCD_WF8B_BPFLCD32_MASK 0x20u
Kojto 90:cb3d968589d8 3460 #define LCD_WF8B_BPFLCD32_SHIFT 5
Kojto 90:cb3d968589d8 3461 #define LCD_WF8B_BPFLCD61_MASK 0x20u
Kojto 90:cb3d968589d8 3462 #define LCD_WF8B_BPFLCD61_SHIFT 5
Kojto 90:cb3d968589d8 3463 #define LCD_WF8B_BPFLCD25_MASK 0x20u
Kojto 90:cb3d968589d8 3464 #define LCD_WF8B_BPFLCD25_SHIFT 5
Kojto 90:cb3d968589d8 3465 #define LCD_WF8B_BPFLCD60_MASK 0x20u
Kojto 90:cb3d968589d8 3466 #define LCD_WF8B_BPFLCD60_SHIFT 5
Kojto 90:cb3d968589d8 3467 #define LCD_WF8B_BPFLCD41_MASK 0x20u
Kojto 90:cb3d968589d8 3468 #define LCD_WF8B_BPFLCD41_SHIFT 5
Kojto 90:cb3d968589d8 3469 #define LCD_WF8B_BPFLCD33_MASK 0x20u
Kojto 90:cb3d968589d8 3470 #define LCD_WF8B_BPFLCD33_SHIFT 5
Kojto 90:cb3d968589d8 3471 #define LCD_WF8B_BPFLCD53_MASK 0x20u
Kojto 90:cb3d968589d8 3472 #define LCD_WF8B_BPFLCD53_SHIFT 5
Kojto 90:cb3d968589d8 3473 #define LCD_WF8B_BPFLCD59_MASK 0x20u
Kojto 90:cb3d968589d8 3474 #define LCD_WF8B_BPFLCD59_SHIFT 5
Kojto 90:cb3d968589d8 3475 #define LCD_WF8B_BPFLCD0_MASK 0x20u
Kojto 90:cb3d968589d8 3476 #define LCD_WF8B_BPFLCD0_SHIFT 5
Kojto 90:cb3d968589d8 3477 #define LCD_WF8B_BPFLCD46_MASK 0x20u
Kojto 90:cb3d968589d8 3478 #define LCD_WF8B_BPFLCD46_SHIFT 5
Kojto 90:cb3d968589d8 3479 #define LCD_WF8B_BPFLCD58_MASK 0x20u
Kojto 90:cb3d968589d8 3480 #define LCD_WF8B_BPFLCD58_SHIFT 5
Kojto 90:cb3d968589d8 3481 #define LCD_WF8B_BPFLCD26_MASK 0x20u
Kojto 90:cb3d968589d8 3482 #define LCD_WF8B_BPFLCD26_SHIFT 5
Kojto 90:cb3d968589d8 3483 #define LCD_WF8B_BPFLCD36_MASK 0x20u
Kojto 90:cb3d968589d8 3484 #define LCD_WF8B_BPFLCD36_SHIFT 5
Kojto 90:cb3d968589d8 3485 #define LCD_WF8B_BPFLCD10_MASK 0x20u
Kojto 90:cb3d968589d8 3486 #define LCD_WF8B_BPFLCD10_SHIFT 5
Kojto 90:cb3d968589d8 3487 #define LCD_WF8B_BPFLCD52_MASK 0x20u
Kojto 90:cb3d968589d8 3488 #define LCD_WF8B_BPFLCD52_SHIFT 5
Kojto 90:cb3d968589d8 3489 #define LCD_WF8B_BPFLCD57_MASK 0x20u
Kojto 90:cb3d968589d8 3490 #define LCD_WF8B_BPFLCD57_SHIFT 5
Kojto 90:cb3d968589d8 3491 #define LCD_WF8B_BPFLCD27_MASK 0x20u
Kojto 90:cb3d968589d8 3492 #define LCD_WF8B_BPFLCD27_SHIFT 5
Kojto 90:cb3d968589d8 3493 #define LCD_WF8B_BPFLCD11_MASK 0x20u
Kojto 90:cb3d968589d8 3494 #define LCD_WF8B_BPFLCD11_SHIFT 5
Kojto 90:cb3d968589d8 3495 #define LCD_WF8B_BPFLCD56_MASK 0x20u
Kojto 90:cb3d968589d8 3496 #define LCD_WF8B_BPFLCD56_SHIFT 5
Kojto 90:cb3d968589d8 3497 #define LCD_WF8B_BPFLCD1_MASK 0x20u
Kojto 90:cb3d968589d8 3498 #define LCD_WF8B_BPFLCD1_SHIFT 5
Kojto 90:cb3d968589d8 3499 #define LCD_WF8B_BPFLCD8_MASK 0x20u
Kojto 90:cb3d968589d8 3500 #define LCD_WF8B_BPFLCD8_SHIFT 5
Kojto 90:cb3d968589d8 3501 #define LCD_WF8B_BPFLCD40_MASK 0x20u
Kojto 90:cb3d968589d8 3502 #define LCD_WF8B_BPFLCD40_SHIFT 5
Kojto 90:cb3d968589d8 3503 #define LCD_WF8B_BPFLCD51_MASK 0x20u
Kojto 90:cb3d968589d8 3504 #define LCD_WF8B_BPFLCD51_SHIFT 5
Kojto 90:cb3d968589d8 3505 #define LCD_WF8B_BPFLCD16_MASK 0x20u
Kojto 90:cb3d968589d8 3506 #define LCD_WF8B_BPFLCD16_SHIFT 5
Kojto 90:cb3d968589d8 3507 #define LCD_WF8B_BPFLCD45_MASK 0x20u
Kojto 90:cb3d968589d8 3508 #define LCD_WF8B_BPFLCD45_SHIFT 5
Kojto 90:cb3d968589d8 3509 #define LCD_WF8B_BPFLCD6_MASK 0x20u
Kojto 90:cb3d968589d8 3510 #define LCD_WF8B_BPFLCD6_SHIFT 5
Kojto 90:cb3d968589d8 3511 #define LCD_WF8B_BPFLCD17_MASK 0x20u
Kojto 90:cb3d968589d8 3512 #define LCD_WF8B_BPFLCD17_SHIFT 5
Kojto 90:cb3d968589d8 3513 #define LCD_WF8B_BPFLCD28_MASK 0x20u
Kojto 90:cb3d968589d8 3514 #define LCD_WF8B_BPFLCD28_SHIFT 5
Kojto 90:cb3d968589d8 3515 #define LCD_WF8B_BPFLCD42_MASK 0x20u
Kojto 90:cb3d968589d8 3516 #define LCD_WF8B_BPFLCD42_SHIFT 5
Kojto 90:cb3d968589d8 3517 #define LCD_WF8B_BPFLCD29_MASK 0x20u
Kojto 90:cb3d968589d8 3518 #define LCD_WF8B_BPFLCD29_SHIFT 5
Kojto 90:cb3d968589d8 3519 #define LCD_WF8B_BPFLCD50_MASK 0x20u
Kojto 90:cb3d968589d8 3520 #define LCD_WF8B_BPFLCD50_SHIFT 5
Kojto 90:cb3d968589d8 3521 #define LCD_WF8B_BPFLCD18_MASK 0x20u
Kojto 90:cb3d968589d8 3522 #define LCD_WF8B_BPFLCD18_SHIFT 5
Kojto 90:cb3d968589d8 3523 #define LCD_WF8B_BPFLCD34_MASK 0x20u
Kojto 90:cb3d968589d8 3524 #define LCD_WF8B_BPFLCD34_SHIFT 5
Kojto 90:cb3d968589d8 3525 #define LCD_WF8B_BPFLCD19_MASK 0x20u
Kojto 90:cb3d968589d8 3526 #define LCD_WF8B_BPFLCD19_SHIFT 5
Kojto 90:cb3d968589d8 3527 #define LCD_WF8B_BPFLCD2_MASK 0x20u
Kojto 90:cb3d968589d8 3528 #define LCD_WF8B_BPFLCD2_SHIFT 5
Kojto 90:cb3d968589d8 3529 #define LCD_WF8B_BPFLCD9_MASK 0x20u
Kojto 90:cb3d968589d8 3530 #define LCD_WF8B_BPFLCD9_SHIFT 5
Kojto 90:cb3d968589d8 3531 #define LCD_WF8B_BPFLCD3_MASK 0x20u
Kojto 90:cb3d968589d8 3532 #define LCD_WF8B_BPFLCD3_SHIFT 5
Kojto 90:cb3d968589d8 3533 #define LCD_WF8B_BPFLCD37_MASK 0x20u
Kojto 90:cb3d968589d8 3534 #define LCD_WF8B_BPFLCD37_SHIFT 5
Kojto 90:cb3d968589d8 3535 #define LCD_WF8B_BPFLCD49_MASK 0x20u
Kojto 90:cb3d968589d8 3536 #define LCD_WF8B_BPFLCD49_SHIFT 5
Kojto 90:cb3d968589d8 3537 #define LCD_WF8B_BPFLCD20_MASK 0x20u
Kojto 90:cb3d968589d8 3538 #define LCD_WF8B_BPFLCD20_SHIFT 5
Kojto 90:cb3d968589d8 3539 #define LCD_WF8B_BPFLCD44_MASK 0x20u
Kojto 90:cb3d968589d8 3540 #define LCD_WF8B_BPFLCD44_SHIFT 5
Kojto 90:cb3d968589d8 3541 #define LCD_WF8B_BPFLCD30_MASK 0x20u
Kojto 90:cb3d968589d8 3542 #define LCD_WF8B_BPFLCD30_SHIFT 5
Kojto 90:cb3d968589d8 3543 #define LCD_WF8B_BPFLCD21_MASK 0x20u
Kojto 90:cb3d968589d8 3544 #define LCD_WF8B_BPFLCD21_SHIFT 5
Kojto 90:cb3d968589d8 3545 #define LCD_WF8B_BPFLCD35_MASK 0x20u
Kojto 90:cb3d968589d8 3546 #define LCD_WF8B_BPFLCD35_SHIFT 5
Kojto 90:cb3d968589d8 3547 #define LCD_WF8B_BPFLCD4_MASK 0x20u
Kojto 90:cb3d968589d8 3548 #define LCD_WF8B_BPFLCD4_SHIFT 5
Kojto 90:cb3d968589d8 3549 #define LCD_WF8B_BPFLCD31_MASK 0x20u
Kojto 90:cb3d968589d8 3550 #define LCD_WF8B_BPFLCD31_SHIFT 5
Kojto 90:cb3d968589d8 3551 #define LCD_WF8B_BPFLCD48_MASK 0x20u
Kojto 90:cb3d968589d8 3552 #define LCD_WF8B_BPFLCD48_SHIFT 5
Kojto 90:cb3d968589d8 3553 #define LCD_WF8B_BPFLCD7_MASK 0x20u
Kojto 90:cb3d968589d8 3554 #define LCD_WF8B_BPFLCD7_SHIFT 5
Kojto 90:cb3d968589d8 3555 #define LCD_WF8B_BPFLCD22_MASK 0x20u
Kojto 90:cb3d968589d8 3556 #define LCD_WF8B_BPFLCD22_SHIFT 5
Kojto 90:cb3d968589d8 3557 #define LCD_WF8B_BPFLCD38_MASK 0x20u
Kojto 90:cb3d968589d8 3558 #define LCD_WF8B_BPFLCD38_SHIFT 5
Kojto 90:cb3d968589d8 3559 #define LCD_WF8B_BPFLCD12_MASK 0x20u
Kojto 90:cb3d968589d8 3560 #define LCD_WF8B_BPFLCD12_SHIFT 5
Kojto 90:cb3d968589d8 3561 #define LCD_WF8B_BPFLCD23_MASK 0x20u
Kojto 90:cb3d968589d8 3562 #define LCD_WF8B_BPFLCD23_SHIFT 5
Kojto 90:cb3d968589d8 3563 #define LCD_WF8B_BPGLCD14_MASK 0x40u
Kojto 90:cb3d968589d8 3564 #define LCD_WF8B_BPGLCD14_SHIFT 6
Kojto 90:cb3d968589d8 3565 #define LCD_WF8B_BPGLCD55_MASK 0x40u
Kojto 90:cb3d968589d8 3566 #define LCD_WF8B_BPGLCD55_SHIFT 6
Kojto 90:cb3d968589d8 3567 #define LCD_WF8B_BPGLCD63_MASK 0x40u
Kojto 90:cb3d968589d8 3568 #define LCD_WF8B_BPGLCD63_SHIFT 6
Kojto 90:cb3d968589d8 3569 #define LCD_WF8B_BPGLCD15_MASK 0x40u
Kojto 90:cb3d968589d8 3570 #define LCD_WF8B_BPGLCD15_SHIFT 6
Kojto 90:cb3d968589d8 3571 #define LCD_WF8B_BPGLCD62_MASK 0x40u
Kojto 90:cb3d968589d8 3572 #define LCD_WF8B_BPGLCD62_SHIFT 6
Kojto 90:cb3d968589d8 3573 #define LCD_WF8B_BPGLCD54_MASK 0x40u
Kojto 90:cb3d968589d8 3574 #define LCD_WF8B_BPGLCD54_SHIFT 6
Kojto 90:cb3d968589d8 3575 #define LCD_WF8B_BPGLCD61_MASK 0x40u
Kojto 90:cb3d968589d8 3576 #define LCD_WF8B_BPGLCD61_SHIFT 6
Kojto 90:cb3d968589d8 3577 #define LCD_WF8B_BPGLCD60_MASK 0x40u
Kojto 90:cb3d968589d8 3578 #define LCD_WF8B_BPGLCD60_SHIFT 6
Kojto 90:cb3d968589d8 3579 #define LCD_WF8B_BPGLCD59_MASK 0x40u
Kojto 90:cb3d968589d8 3580 #define LCD_WF8B_BPGLCD59_SHIFT 6
Kojto 90:cb3d968589d8 3581 #define LCD_WF8B_BPGLCD53_MASK 0x40u
Kojto 90:cb3d968589d8 3582 #define LCD_WF8B_BPGLCD53_SHIFT 6
Kojto 90:cb3d968589d8 3583 #define LCD_WF8B_BPGLCD58_MASK 0x40u
Kojto 90:cb3d968589d8 3584 #define LCD_WF8B_BPGLCD58_SHIFT 6
Kojto 90:cb3d968589d8 3585 #define LCD_WF8B_BPGLCD0_MASK 0x40u
Kojto 90:cb3d968589d8 3586 #define LCD_WF8B_BPGLCD0_SHIFT 6
Kojto 90:cb3d968589d8 3587 #define LCD_WF8B_BPGLCD57_MASK 0x40u
Kojto 90:cb3d968589d8 3588 #define LCD_WF8B_BPGLCD57_SHIFT 6
Kojto 90:cb3d968589d8 3589 #define LCD_WF8B_BPGLCD52_MASK 0x40u
Kojto 90:cb3d968589d8 3590 #define LCD_WF8B_BPGLCD52_SHIFT 6
Kojto 90:cb3d968589d8 3591 #define LCD_WF8B_BPGLCD7_MASK 0x40u
Kojto 90:cb3d968589d8 3592 #define LCD_WF8B_BPGLCD7_SHIFT 6
Kojto 90:cb3d968589d8 3593 #define LCD_WF8B_BPGLCD56_MASK 0x40u
Kojto 90:cb3d968589d8 3594 #define LCD_WF8B_BPGLCD56_SHIFT 6
Kojto 90:cb3d968589d8 3595 #define LCD_WF8B_BPGLCD6_MASK 0x40u
Kojto 90:cb3d968589d8 3596 #define LCD_WF8B_BPGLCD6_SHIFT 6
Kojto 90:cb3d968589d8 3597 #define LCD_WF8B_BPGLCD51_MASK 0x40u
Kojto 90:cb3d968589d8 3598 #define LCD_WF8B_BPGLCD51_SHIFT 6
Kojto 90:cb3d968589d8 3599 #define LCD_WF8B_BPGLCD16_MASK 0x40u
Kojto 90:cb3d968589d8 3600 #define LCD_WF8B_BPGLCD16_SHIFT 6
Kojto 90:cb3d968589d8 3601 #define LCD_WF8B_BPGLCD1_MASK 0x40u
Kojto 90:cb3d968589d8 3602 #define LCD_WF8B_BPGLCD1_SHIFT 6
Kojto 90:cb3d968589d8 3603 #define LCD_WF8B_BPGLCD17_MASK 0x40u
Kojto 90:cb3d968589d8 3604 #define LCD_WF8B_BPGLCD17_SHIFT 6
Kojto 90:cb3d968589d8 3605 #define LCD_WF8B_BPGLCD50_MASK 0x40u
Kojto 90:cb3d968589d8 3606 #define LCD_WF8B_BPGLCD50_SHIFT 6
Kojto 90:cb3d968589d8 3607 #define LCD_WF8B_BPGLCD18_MASK 0x40u
Kojto 90:cb3d968589d8 3608 #define LCD_WF8B_BPGLCD18_SHIFT 6
Kojto 90:cb3d968589d8 3609 #define LCD_WF8B_BPGLCD19_MASK 0x40u
Kojto 90:cb3d968589d8 3610 #define LCD_WF8B_BPGLCD19_SHIFT 6
Kojto 90:cb3d968589d8 3611 #define LCD_WF8B_BPGLCD8_MASK 0x40u
Kojto 90:cb3d968589d8 3612 #define LCD_WF8B_BPGLCD8_SHIFT 6
Kojto 90:cb3d968589d8 3613 #define LCD_WF8B_BPGLCD49_MASK 0x40u
Kojto 90:cb3d968589d8 3614 #define LCD_WF8B_BPGLCD49_SHIFT 6
Kojto 90:cb3d968589d8 3615 #define LCD_WF8B_BPGLCD20_MASK 0x40u
Kojto 90:cb3d968589d8 3616 #define LCD_WF8B_BPGLCD20_SHIFT 6
Kojto 90:cb3d968589d8 3617 #define LCD_WF8B_BPGLCD9_MASK 0x40u
Kojto 90:cb3d968589d8 3618 #define LCD_WF8B_BPGLCD9_SHIFT 6
Kojto 90:cb3d968589d8 3619 #define LCD_WF8B_BPGLCD21_MASK 0x40u
Kojto 90:cb3d968589d8 3620 #define LCD_WF8B_BPGLCD21_SHIFT 6
Kojto 90:cb3d968589d8 3621 #define LCD_WF8B_BPGLCD13_MASK 0x40u
Kojto 90:cb3d968589d8 3622 #define LCD_WF8B_BPGLCD13_SHIFT 6
Kojto 90:cb3d968589d8 3623 #define LCD_WF8B_BPGLCD48_MASK 0x40u
Kojto 90:cb3d968589d8 3624 #define LCD_WF8B_BPGLCD48_SHIFT 6
Kojto 90:cb3d968589d8 3625 #define LCD_WF8B_BPGLCD22_MASK 0x40u
Kojto 90:cb3d968589d8 3626 #define LCD_WF8B_BPGLCD22_SHIFT 6
Kojto 90:cb3d968589d8 3627 #define LCD_WF8B_BPGLCD5_MASK 0x40u
Kojto 90:cb3d968589d8 3628 #define LCD_WF8B_BPGLCD5_SHIFT 6
Kojto 90:cb3d968589d8 3629 #define LCD_WF8B_BPGLCD47_MASK 0x40u
Kojto 90:cb3d968589d8 3630 #define LCD_WF8B_BPGLCD47_SHIFT 6
Kojto 90:cb3d968589d8 3631 #define LCD_WF8B_BPGLCD23_MASK 0x40u
Kojto 90:cb3d968589d8 3632 #define LCD_WF8B_BPGLCD23_SHIFT 6
Kojto 90:cb3d968589d8 3633 #define LCD_WF8B_BPGLCD24_MASK 0x40u
Kojto 90:cb3d968589d8 3634 #define LCD_WF8B_BPGLCD24_SHIFT 6
Kojto 90:cb3d968589d8 3635 #define LCD_WF8B_BPGLCD25_MASK 0x40u
Kojto 90:cb3d968589d8 3636 #define LCD_WF8B_BPGLCD25_SHIFT 6
Kojto 90:cb3d968589d8 3637 #define LCD_WF8B_BPGLCD46_MASK 0x40u
Kojto 90:cb3d968589d8 3638 #define LCD_WF8B_BPGLCD46_SHIFT 6
Kojto 90:cb3d968589d8 3639 #define LCD_WF8B_BPGLCD26_MASK 0x40u
Kojto 90:cb3d968589d8 3640 #define LCD_WF8B_BPGLCD26_SHIFT 6
Kojto 90:cb3d968589d8 3641 #define LCD_WF8B_BPGLCD27_MASK 0x40u
Kojto 90:cb3d968589d8 3642 #define LCD_WF8B_BPGLCD27_SHIFT 6
Kojto 90:cb3d968589d8 3643 #define LCD_WF8B_BPGLCD10_MASK 0x40u
Kojto 90:cb3d968589d8 3644 #define LCD_WF8B_BPGLCD10_SHIFT 6
Kojto 90:cb3d968589d8 3645 #define LCD_WF8B_BPGLCD45_MASK 0x40u
Kojto 90:cb3d968589d8 3646 #define LCD_WF8B_BPGLCD45_SHIFT 6
Kojto 90:cb3d968589d8 3647 #define LCD_WF8B_BPGLCD28_MASK 0x40u
Kojto 90:cb3d968589d8 3648 #define LCD_WF8B_BPGLCD28_SHIFT 6
Kojto 90:cb3d968589d8 3649 #define LCD_WF8B_BPGLCD29_MASK 0x40u
Kojto 90:cb3d968589d8 3650 #define LCD_WF8B_BPGLCD29_SHIFT 6
Kojto 90:cb3d968589d8 3651 #define LCD_WF8B_BPGLCD4_MASK 0x40u
Kojto 90:cb3d968589d8 3652 #define LCD_WF8B_BPGLCD4_SHIFT 6
Kojto 90:cb3d968589d8 3653 #define LCD_WF8B_BPGLCD44_MASK 0x40u
Kojto 90:cb3d968589d8 3654 #define LCD_WF8B_BPGLCD44_SHIFT 6
Kojto 90:cb3d968589d8 3655 #define LCD_WF8B_BPGLCD30_MASK 0x40u
Kojto 90:cb3d968589d8 3656 #define LCD_WF8B_BPGLCD30_SHIFT 6
Kojto 90:cb3d968589d8 3657 #define LCD_WF8B_BPGLCD2_MASK 0x40u
Kojto 90:cb3d968589d8 3658 #define LCD_WF8B_BPGLCD2_SHIFT 6
Kojto 90:cb3d968589d8 3659 #define LCD_WF8B_BPGLCD31_MASK 0x40u
Kojto 90:cb3d968589d8 3660 #define LCD_WF8B_BPGLCD31_SHIFT 6
Kojto 90:cb3d968589d8 3661 #define LCD_WF8B_BPGLCD43_MASK 0x40u
Kojto 90:cb3d968589d8 3662 #define LCD_WF8B_BPGLCD43_SHIFT 6
Kojto 90:cb3d968589d8 3663 #define LCD_WF8B_BPGLCD32_MASK 0x40u
Kojto 90:cb3d968589d8 3664 #define LCD_WF8B_BPGLCD32_SHIFT 6
Kojto 90:cb3d968589d8 3665 #define LCD_WF8B_BPGLCD33_MASK 0x40u
Kojto 90:cb3d968589d8 3666 #define LCD_WF8B_BPGLCD33_SHIFT 6
Kojto 90:cb3d968589d8 3667 #define LCD_WF8B_BPGLCD42_MASK 0x40u
Kojto 90:cb3d968589d8 3668 #define LCD_WF8B_BPGLCD42_SHIFT 6
Kojto 90:cb3d968589d8 3669 #define LCD_WF8B_BPGLCD34_MASK 0x40u
Kojto 90:cb3d968589d8 3670 #define LCD_WF8B_BPGLCD34_SHIFT 6
Kojto 90:cb3d968589d8 3671 #define LCD_WF8B_BPGLCD11_MASK 0x40u
Kojto 90:cb3d968589d8 3672 #define LCD_WF8B_BPGLCD11_SHIFT 6
Kojto 90:cb3d968589d8 3673 #define LCD_WF8B_BPGLCD35_MASK 0x40u
Kojto 90:cb3d968589d8 3674 #define LCD_WF8B_BPGLCD35_SHIFT 6
Kojto 90:cb3d968589d8 3675 #define LCD_WF8B_BPGLCD12_MASK 0x40u
Kojto 90:cb3d968589d8 3676 #define LCD_WF8B_BPGLCD12_SHIFT 6
Kojto 90:cb3d968589d8 3677 #define LCD_WF8B_BPGLCD41_MASK 0x40u
Kojto 90:cb3d968589d8 3678 #define LCD_WF8B_BPGLCD41_SHIFT 6
Kojto 90:cb3d968589d8 3679 #define LCD_WF8B_BPGLCD36_MASK 0x40u
Kojto 90:cb3d968589d8 3680 #define LCD_WF8B_BPGLCD36_SHIFT 6
Kojto 90:cb3d968589d8 3681 #define LCD_WF8B_BPGLCD3_MASK 0x40u
Kojto 90:cb3d968589d8 3682 #define LCD_WF8B_BPGLCD3_SHIFT 6
Kojto 90:cb3d968589d8 3683 #define LCD_WF8B_BPGLCD37_MASK 0x40u
Kojto 90:cb3d968589d8 3684 #define LCD_WF8B_BPGLCD37_SHIFT 6
Kojto 90:cb3d968589d8 3685 #define LCD_WF8B_BPGLCD40_MASK 0x40u
Kojto 90:cb3d968589d8 3686 #define LCD_WF8B_BPGLCD40_SHIFT 6
Kojto 90:cb3d968589d8 3687 #define LCD_WF8B_BPGLCD38_MASK 0x40u
Kojto 90:cb3d968589d8 3688 #define LCD_WF8B_BPGLCD38_SHIFT 6
Kojto 90:cb3d968589d8 3689 #define LCD_WF8B_BPGLCD39_MASK 0x40u
Kojto 90:cb3d968589d8 3690 #define LCD_WF8B_BPGLCD39_SHIFT 6
Kojto 90:cb3d968589d8 3691 #define LCD_WF8B_BPHLCD63_MASK 0x80u
Kojto 90:cb3d968589d8 3692 #define LCD_WF8B_BPHLCD63_SHIFT 7
Kojto 90:cb3d968589d8 3693 #define LCD_WF8B_BPHLCD62_MASK 0x80u
Kojto 90:cb3d968589d8 3694 #define LCD_WF8B_BPHLCD62_SHIFT 7
Kojto 90:cb3d968589d8 3695 #define LCD_WF8B_BPHLCD61_MASK 0x80u
Kojto 90:cb3d968589d8 3696 #define LCD_WF8B_BPHLCD61_SHIFT 7
Kojto 90:cb3d968589d8 3697 #define LCD_WF8B_BPHLCD60_MASK 0x80u
Kojto 90:cb3d968589d8 3698 #define LCD_WF8B_BPHLCD60_SHIFT 7
Kojto 90:cb3d968589d8 3699 #define LCD_WF8B_BPHLCD59_MASK 0x80u
Kojto 90:cb3d968589d8 3700 #define LCD_WF8B_BPHLCD59_SHIFT 7
Kojto 90:cb3d968589d8 3701 #define LCD_WF8B_BPHLCD58_MASK 0x80u
Kojto 90:cb3d968589d8 3702 #define LCD_WF8B_BPHLCD58_SHIFT 7
Kojto 90:cb3d968589d8 3703 #define LCD_WF8B_BPHLCD57_MASK 0x80u
Kojto 90:cb3d968589d8 3704 #define LCD_WF8B_BPHLCD57_SHIFT 7
Kojto 90:cb3d968589d8 3705 #define LCD_WF8B_BPHLCD0_MASK 0x80u
Kojto 90:cb3d968589d8 3706 #define LCD_WF8B_BPHLCD0_SHIFT 7
Kojto 90:cb3d968589d8 3707 #define LCD_WF8B_BPHLCD56_MASK 0x80u
Kojto 90:cb3d968589d8 3708 #define LCD_WF8B_BPHLCD56_SHIFT 7
Kojto 90:cb3d968589d8 3709 #define LCD_WF8B_BPHLCD55_MASK 0x80u
Kojto 90:cb3d968589d8 3710 #define LCD_WF8B_BPHLCD55_SHIFT 7
Kojto 90:cb3d968589d8 3711 #define LCD_WF8B_BPHLCD54_MASK 0x80u
Kojto 90:cb3d968589d8 3712 #define LCD_WF8B_BPHLCD54_SHIFT 7
Kojto 90:cb3d968589d8 3713 #define LCD_WF8B_BPHLCD53_MASK 0x80u
Kojto 90:cb3d968589d8 3714 #define LCD_WF8B_BPHLCD53_SHIFT 7
Kojto 90:cb3d968589d8 3715 #define LCD_WF8B_BPHLCD52_MASK 0x80u
Kojto 90:cb3d968589d8 3716 #define LCD_WF8B_BPHLCD52_SHIFT 7
Kojto 90:cb3d968589d8 3717 #define LCD_WF8B_BPHLCD51_MASK 0x80u
Kojto 90:cb3d968589d8 3718 #define LCD_WF8B_BPHLCD51_SHIFT 7
Kojto 90:cb3d968589d8 3719 #define LCD_WF8B_BPHLCD50_MASK 0x80u
Kojto 90:cb3d968589d8 3720 #define LCD_WF8B_BPHLCD50_SHIFT 7
Kojto 90:cb3d968589d8 3721 #define LCD_WF8B_BPHLCD1_MASK 0x80u
Kojto 90:cb3d968589d8 3722 #define LCD_WF8B_BPHLCD1_SHIFT 7
Kojto 90:cb3d968589d8 3723 #define LCD_WF8B_BPHLCD49_MASK 0x80u
Kojto 90:cb3d968589d8 3724 #define LCD_WF8B_BPHLCD49_SHIFT 7
Kojto 90:cb3d968589d8 3725 #define LCD_WF8B_BPHLCD48_MASK 0x80u
Kojto 90:cb3d968589d8 3726 #define LCD_WF8B_BPHLCD48_SHIFT 7
Kojto 90:cb3d968589d8 3727 #define LCD_WF8B_BPHLCD47_MASK 0x80u
Kojto 90:cb3d968589d8 3728 #define LCD_WF8B_BPHLCD47_SHIFT 7
Kojto 90:cb3d968589d8 3729 #define LCD_WF8B_BPHLCD46_MASK 0x80u
Kojto 90:cb3d968589d8 3730 #define LCD_WF8B_BPHLCD46_SHIFT 7
Kojto 90:cb3d968589d8 3731 #define LCD_WF8B_BPHLCD45_MASK 0x80u
Kojto 90:cb3d968589d8 3732 #define LCD_WF8B_BPHLCD45_SHIFT 7
Kojto 90:cb3d968589d8 3733 #define LCD_WF8B_BPHLCD44_MASK 0x80u
Kojto 90:cb3d968589d8 3734 #define LCD_WF8B_BPHLCD44_SHIFT 7
Kojto 90:cb3d968589d8 3735 #define LCD_WF8B_BPHLCD43_MASK 0x80u
Kojto 90:cb3d968589d8 3736 #define LCD_WF8B_BPHLCD43_SHIFT 7
Kojto 90:cb3d968589d8 3737 #define LCD_WF8B_BPHLCD2_MASK 0x80u
Kojto 90:cb3d968589d8 3738 #define LCD_WF8B_BPHLCD2_SHIFT 7
Kojto 90:cb3d968589d8 3739 #define LCD_WF8B_BPHLCD42_MASK 0x80u
Kojto 90:cb3d968589d8 3740 #define LCD_WF8B_BPHLCD42_SHIFT 7
Kojto 90:cb3d968589d8 3741 #define LCD_WF8B_BPHLCD41_MASK 0x80u
Kojto 90:cb3d968589d8 3742 #define LCD_WF8B_BPHLCD41_SHIFT 7
Kojto 90:cb3d968589d8 3743 #define LCD_WF8B_BPHLCD40_MASK 0x80u
Kojto 90:cb3d968589d8 3744 #define LCD_WF8B_BPHLCD40_SHIFT 7
Kojto 90:cb3d968589d8 3745 #define LCD_WF8B_BPHLCD39_MASK 0x80u
Kojto 90:cb3d968589d8 3746 #define LCD_WF8B_BPHLCD39_SHIFT 7
Kojto 90:cb3d968589d8 3747 #define LCD_WF8B_BPHLCD38_MASK 0x80u
Kojto 90:cb3d968589d8 3748 #define LCD_WF8B_BPHLCD38_SHIFT 7
Kojto 90:cb3d968589d8 3749 #define LCD_WF8B_BPHLCD37_MASK 0x80u
Kojto 90:cb3d968589d8 3750 #define LCD_WF8B_BPHLCD37_SHIFT 7
Kojto 90:cb3d968589d8 3751 #define LCD_WF8B_BPHLCD36_MASK 0x80u
Kojto 90:cb3d968589d8 3752 #define LCD_WF8B_BPHLCD36_SHIFT 7
Kojto 90:cb3d968589d8 3753 #define LCD_WF8B_BPHLCD3_MASK 0x80u
Kojto 90:cb3d968589d8 3754 #define LCD_WF8B_BPHLCD3_SHIFT 7
Kojto 90:cb3d968589d8 3755 #define LCD_WF8B_BPHLCD35_MASK 0x80u
Kojto 90:cb3d968589d8 3756 #define LCD_WF8B_BPHLCD35_SHIFT 7
Kojto 90:cb3d968589d8 3757 #define LCD_WF8B_BPHLCD34_MASK 0x80u
Kojto 90:cb3d968589d8 3758 #define LCD_WF8B_BPHLCD34_SHIFT 7
Kojto 90:cb3d968589d8 3759 #define LCD_WF8B_BPHLCD33_MASK 0x80u
Kojto 90:cb3d968589d8 3760 #define LCD_WF8B_BPHLCD33_SHIFT 7
Kojto 90:cb3d968589d8 3761 #define LCD_WF8B_BPHLCD32_MASK 0x80u
Kojto 90:cb3d968589d8 3762 #define LCD_WF8B_BPHLCD32_SHIFT 7
Kojto 90:cb3d968589d8 3763 #define LCD_WF8B_BPHLCD31_MASK 0x80u
Kojto 90:cb3d968589d8 3764 #define LCD_WF8B_BPHLCD31_SHIFT 7
Kojto 90:cb3d968589d8 3765 #define LCD_WF8B_BPHLCD30_MASK 0x80u
Kojto 90:cb3d968589d8 3766 #define LCD_WF8B_BPHLCD30_SHIFT 7
Kojto 90:cb3d968589d8 3767 #define LCD_WF8B_BPHLCD29_MASK 0x80u
Kojto 90:cb3d968589d8 3768 #define LCD_WF8B_BPHLCD29_SHIFT 7
Kojto 90:cb3d968589d8 3769 #define LCD_WF8B_BPHLCD4_MASK 0x80u
Kojto 90:cb3d968589d8 3770 #define LCD_WF8B_BPHLCD4_SHIFT 7
Kojto 90:cb3d968589d8 3771 #define LCD_WF8B_BPHLCD28_MASK 0x80u
Kojto 90:cb3d968589d8 3772 #define LCD_WF8B_BPHLCD28_SHIFT 7
Kojto 90:cb3d968589d8 3773 #define LCD_WF8B_BPHLCD27_MASK 0x80u
Kojto 90:cb3d968589d8 3774 #define LCD_WF8B_BPHLCD27_SHIFT 7
Kojto 90:cb3d968589d8 3775 #define LCD_WF8B_BPHLCD26_MASK 0x80u
Kojto 90:cb3d968589d8 3776 #define LCD_WF8B_BPHLCD26_SHIFT 7
Kojto 90:cb3d968589d8 3777 #define LCD_WF8B_BPHLCD25_MASK 0x80u
Kojto 90:cb3d968589d8 3778 #define LCD_WF8B_BPHLCD25_SHIFT 7
Kojto 90:cb3d968589d8 3779 #define LCD_WF8B_BPHLCD24_MASK 0x80u
Kojto 90:cb3d968589d8 3780 #define LCD_WF8B_BPHLCD24_SHIFT 7
Kojto 90:cb3d968589d8 3781 #define LCD_WF8B_BPHLCD23_MASK 0x80u
Kojto 90:cb3d968589d8 3782 #define LCD_WF8B_BPHLCD23_SHIFT 7
Kojto 90:cb3d968589d8 3783 #define LCD_WF8B_BPHLCD22_MASK 0x80u
Kojto 90:cb3d968589d8 3784 #define LCD_WF8B_BPHLCD22_SHIFT 7
Kojto 90:cb3d968589d8 3785 #define LCD_WF8B_BPHLCD5_MASK 0x80u
Kojto 90:cb3d968589d8 3786 #define LCD_WF8B_BPHLCD5_SHIFT 7
Kojto 90:cb3d968589d8 3787 #define LCD_WF8B_BPHLCD21_MASK 0x80u
Kojto 90:cb3d968589d8 3788 #define LCD_WF8B_BPHLCD21_SHIFT 7
Kojto 90:cb3d968589d8 3789 #define LCD_WF8B_BPHLCD20_MASK 0x80u
Kojto 90:cb3d968589d8 3790 #define LCD_WF8B_BPHLCD20_SHIFT 7
Kojto 90:cb3d968589d8 3791 #define LCD_WF8B_BPHLCD19_MASK 0x80u
Kojto 90:cb3d968589d8 3792 #define LCD_WF8B_BPHLCD19_SHIFT 7
Kojto 90:cb3d968589d8 3793 #define LCD_WF8B_BPHLCD18_MASK 0x80u
Kojto 90:cb3d968589d8 3794 #define LCD_WF8B_BPHLCD18_SHIFT 7
Kojto 90:cb3d968589d8 3795 #define LCD_WF8B_BPHLCD17_MASK 0x80u
Kojto 90:cb3d968589d8 3796 #define LCD_WF8B_BPHLCD17_SHIFT 7
Kojto 90:cb3d968589d8 3797 #define LCD_WF8B_BPHLCD16_MASK 0x80u
Kojto 90:cb3d968589d8 3798 #define LCD_WF8B_BPHLCD16_SHIFT 7
Kojto 90:cb3d968589d8 3799 #define LCD_WF8B_BPHLCD15_MASK 0x80u
Kojto 90:cb3d968589d8 3800 #define LCD_WF8B_BPHLCD15_SHIFT 7
Kojto 90:cb3d968589d8 3801 #define LCD_WF8B_BPHLCD6_MASK 0x80u
Kojto 90:cb3d968589d8 3802 #define LCD_WF8B_BPHLCD6_SHIFT 7
Kojto 90:cb3d968589d8 3803 #define LCD_WF8B_BPHLCD14_MASK 0x80u
Kojto 90:cb3d968589d8 3804 #define LCD_WF8B_BPHLCD14_SHIFT 7
Kojto 90:cb3d968589d8 3805 #define LCD_WF8B_BPHLCD13_MASK 0x80u
Kojto 90:cb3d968589d8 3806 #define LCD_WF8B_BPHLCD13_SHIFT 7
Kojto 90:cb3d968589d8 3807 #define LCD_WF8B_BPHLCD12_MASK 0x80u
Kojto 90:cb3d968589d8 3808 #define LCD_WF8B_BPHLCD12_SHIFT 7
Kojto 90:cb3d968589d8 3809 #define LCD_WF8B_BPHLCD11_MASK 0x80u
Kojto 90:cb3d968589d8 3810 #define LCD_WF8B_BPHLCD11_SHIFT 7
Kojto 90:cb3d968589d8 3811 #define LCD_WF8B_BPHLCD10_MASK 0x80u
Kojto 90:cb3d968589d8 3812 #define LCD_WF8B_BPHLCD10_SHIFT 7
Kojto 90:cb3d968589d8 3813 #define LCD_WF8B_BPHLCD9_MASK 0x80u
Kojto 90:cb3d968589d8 3814 #define LCD_WF8B_BPHLCD9_SHIFT 7
Kojto 90:cb3d968589d8 3815 #define LCD_WF8B_BPHLCD8_MASK 0x80u
Kojto 90:cb3d968589d8 3816 #define LCD_WF8B_BPHLCD8_SHIFT 7
Kojto 90:cb3d968589d8 3817 #define LCD_WF8B_BPHLCD7_MASK 0x80u
Kojto 90:cb3d968589d8 3818 #define LCD_WF8B_BPHLCD7_SHIFT 7
Kojto 90:cb3d968589d8 3819
Kojto 90:cb3d968589d8 3820 /*!
Kojto 90:cb3d968589d8 3821 * @}
Kojto 90:cb3d968589d8 3822 */ /* end of group LCD_Register_Masks */
Kojto 90:cb3d968589d8 3823
Kojto 90:cb3d968589d8 3824
Kojto 90:cb3d968589d8 3825 /* LCD - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 3826 /** Peripheral LCD base address */
Kojto 90:cb3d968589d8 3827 #define LCD_BASE (0x40053000u)
Kojto 90:cb3d968589d8 3828 /** Peripheral LCD base pointer */
Kojto 90:cb3d968589d8 3829 #define LCD ((LCD_Type *)LCD_BASE)
Kojto 90:cb3d968589d8 3830 #define LCD_BASE_PTR (LCD)
Kojto 90:cb3d968589d8 3831 /** Array initializer of LCD peripheral base addresses */
Kojto 90:cb3d968589d8 3832 #define LCD_BASE_ADDRS { LCD_BASE }
Kojto 90:cb3d968589d8 3833 /** Array initializer of LCD peripheral base pointers */
Kojto 90:cb3d968589d8 3834 #define LCD_BASE_PTRS { LCD }
Kojto 90:cb3d968589d8 3835 /** Interrupt vectors for the LCD peripheral type */
Kojto 90:cb3d968589d8 3836 #define LCD_LCD_IRQS { LCD_IRQn }
Kojto 90:cb3d968589d8 3837
Kojto 90:cb3d968589d8 3838 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3839 -- LCD - Register accessor macros
Kojto 90:cb3d968589d8 3840 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3841
Kojto 90:cb3d968589d8 3842 /*!
Kojto 90:cb3d968589d8 3843 * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
Kojto 90:cb3d968589d8 3844 * @{
Kojto 90:cb3d968589d8 3845 */
Kojto 90:cb3d968589d8 3846
Kojto 90:cb3d968589d8 3847
Kojto 90:cb3d968589d8 3848 /* LCD - Register instance definitions */
Kojto 90:cb3d968589d8 3849 /* LCD */
Kojto 90:cb3d968589d8 3850 #define LCD_GCR LCD_GCR_REG(LCD)
Kojto 90:cb3d968589d8 3851 #define LCD_AR LCD_AR_REG(LCD)
Kojto 90:cb3d968589d8 3852 #define LCD_FDCR LCD_FDCR_REG(LCD)
Kojto 90:cb3d968589d8 3853 #define LCD_FDSR LCD_FDSR_REG(LCD)
Kojto 90:cb3d968589d8 3854 #define LCD_PENL LCD_PEN_REG(LCD,0)
Kojto 90:cb3d968589d8 3855 #define LCD_PENH LCD_PEN_REG(LCD,1)
Kojto 90:cb3d968589d8 3856 #define LCD_BPENL LCD_BPEN_REG(LCD,0)
Kojto 90:cb3d968589d8 3857 #define LCD_BPENH LCD_BPEN_REG(LCD,1)
Kojto 90:cb3d968589d8 3858 #define LCD_WF0 LCD_WF8B_REG(LCD,0)
Kojto 90:cb3d968589d8 3859 #define LCD_WF3TO0 LCD_WF_REG(LCD,0)
Kojto 90:cb3d968589d8 3860 #define LCD_WF1 LCD_WF8B_REG(LCD,1)
Kojto 90:cb3d968589d8 3861 #define LCD_WF2 LCD_WF8B_REG(LCD,2)
Kojto 90:cb3d968589d8 3862 #define LCD_WF3 LCD_WF8B_REG(LCD,3)
Kojto 90:cb3d968589d8 3863 #define LCD_WF4 LCD_WF8B_REG(LCD,4)
Kojto 90:cb3d968589d8 3864 #define LCD_WF7TO4 LCD_WF_REG(LCD,1)
Kojto 90:cb3d968589d8 3865 #define LCD_WF5 LCD_WF8B_REG(LCD,5)
Kojto 90:cb3d968589d8 3866 #define LCD_WF6 LCD_WF8B_REG(LCD,6)
Kojto 90:cb3d968589d8 3867 #define LCD_WF7 LCD_WF8B_REG(LCD,7)
Kojto 90:cb3d968589d8 3868 #define LCD_WF11TO8 LCD_WF_REG(LCD,2)
Kojto 90:cb3d968589d8 3869 #define LCD_WF8 LCD_WF8B_REG(LCD,8)
Kojto 90:cb3d968589d8 3870 #define LCD_WF9 LCD_WF8B_REG(LCD,9)
Kojto 90:cb3d968589d8 3871 #define LCD_WF10 LCD_WF8B_REG(LCD,10)
Kojto 90:cb3d968589d8 3872 #define LCD_WF11 LCD_WF8B_REG(LCD,11)
Kojto 90:cb3d968589d8 3873 #define LCD_WF12 LCD_WF8B_REG(LCD,12)
Kojto 90:cb3d968589d8 3874 #define LCD_WF15TO12 LCD_WF_REG(LCD,3)
Kojto 90:cb3d968589d8 3875 #define LCD_WF13 LCD_WF8B_REG(LCD,13)
Kojto 90:cb3d968589d8 3876 #define LCD_WF14 LCD_WF8B_REG(LCD,14)
Kojto 90:cb3d968589d8 3877 #define LCD_WF15 LCD_WF8B_REG(LCD,15)
Kojto 90:cb3d968589d8 3878 #define LCD_WF16 LCD_WF8B_REG(LCD,16)
Kojto 90:cb3d968589d8 3879 #define LCD_WF19TO16 LCD_WF_REG(LCD,4)
Kojto 90:cb3d968589d8 3880 #define LCD_WF17 LCD_WF8B_REG(LCD,17)
Kojto 90:cb3d968589d8 3881 #define LCD_WF18 LCD_WF8B_REG(LCD,18)
Kojto 90:cb3d968589d8 3882 #define LCD_WF19 LCD_WF8B_REG(LCD,19)
Kojto 90:cb3d968589d8 3883 #define LCD_WF20 LCD_WF8B_REG(LCD,20)
Kojto 90:cb3d968589d8 3884 #define LCD_WF23TO20 LCD_WF_REG(LCD,5)
Kojto 90:cb3d968589d8 3885 #define LCD_WF21 LCD_WF8B_REG(LCD,21)
Kojto 90:cb3d968589d8 3886 #define LCD_WF22 LCD_WF8B_REG(LCD,22)
Kojto 90:cb3d968589d8 3887 #define LCD_WF23 LCD_WF8B_REG(LCD,23)
Kojto 90:cb3d968589d8 3888 #define LCD_WF24 LCD_WF8B_REG(LCD,24)
Kojto 90:cb3d968589d8 3889 #define LCD_WF27TO24 LCD_WF_REG(LCD,6)
Kojto 90:cb3d968589d8 3890 #define LCD_WF25 LCD_WF8B_REG(LCD,25)
Kojto 90:cb3d968589d8 3891 #define LCD_WF26 LCD_WF8B_REG(LCD,26)
Kojto 90:cb3d968589d8 3892 #define LCD_WF27 LCD_WF8B_REG(LCD,27)
Kojto 90:cb3d968589d8 3893 #define LCD_WF28 LCD_WF8B_REG(LCD,28)
Kojto 90:cb3d968589d8 3894 #define LCD_WF31TO28 LCD_WF_REG(LCD,7)
Kojto 90:cb3d968589d8 3895 #define LCD_WF29 LCD_WF8B_REG(LCD,29)
Kojto 90:cb3d968589d8 3896 #define LCD_WF30 LCD_WF8B_REG(LCD,30)
Kojto 90:cb3d968589d8 3897 #define LCD_WF31 LCD_WF8B_REG(LCD,31)
Kojto 90:cb3d968589d8 3898 #define LCD_WF32 LCD_WF8B_REG(LCD,32)
Kojto 90:cb3d968589d8 3899 #define LCD_WF35TO32 LCD_WF_REG(LCD,8)
Kojto 90:cb3d968589d8 3900 #define LCD_WF33 LCD_WF8B_REG(LCD,33)
Kojto 90:cb3d968589d8 3901 #define LCD_WF34 LCD_WF8B_REG(LCD,34)
Kojto 90:cb3d968589d8 3902 #define LCD_WF35 LCD_WF8B_REG(LCD,35)
Kojto 90:cb3d968589d8 3903 #define LCD_WF36 LCD_WF8B_REG(LCD,36)
Kojto 90:cb3d968589d8 3904 #define LCD_WF39TO36 LCD_WF_REG(LCD,9)
Kojto 90:cb3d968589d8 3905 #define LCD_WF37 LCD_WF8B_REG(LCD,37)
Kojto 90:cb3d968589d8 3906 #define LCD_WF38 LCD_WF8B_REG(LCD,38)
Kojto 90:cb3d968589d8 3907 #define LCD_WF39 LCD_WF8B_REG(LCD,39)
Kojto 90:cb3d968589d8 3908 #define LCD_WF40 LCD_WF8B_REG(LCD,40)
Kojto 90:cb3d968589d8 3909 #define LCD_WF43TO40 LCD_WF_REG(LCD,10)
Kojto 90:cb3d968589d8 3910 #define LCD_WF41 LCD_WF8B_REG(LCD,41)
Kojto 90:cb3d968589d8 3911 #define LCD_WF42 LCD_WF8B_REG(LCD,42)
Kojto 90:cb3d968589d8 3912 #define LCD_WF43 LCD_WF8B_REG(LCD,43)
Kojto 90:cb3d968589d8 3913 #define LCD_WF44 LCD_WF8B_REG(LCD,44)
Kojto 90:cb3d968589d8 3914 #define LCD_WF47TO44 LCD_WF_REG(LCD,11)
Kojto 90:cb3d968589d8 3915 #define LCD_WF45 LCD_WF8B_REG(LCD,45)
Kojto 90:cb3d968589d8 3916 #define LCD_WF46 LCD_WF8B_REG(LCD,46)
Kojto 90:cb3d968589d8 3917 #define LCD_WF47 LCD_WF8B_REG(LCD,47)
Kojto 90:cb3d968589d8 3918 #define LCD_WF48 LCD_WF8B_REG(LCD,48)
Kojto 90:cb3d968589d8 3919 #define LCD_WF51TO48 LCD_WF_REG(LCD,12)
Kojto 90:cb3d968589d8 3920 #define LCD_WF49 LCD_WF8B_REG(LCD,49)
Kojto 90:cb3d968589d8 3921 #define LCD_WF50 LCD_WF8B_REG(LCD,50)
Kojto 90:cb3d968589d8 3922 #define LCD_WF51 LCD_WF8B_REG(LCD,51)
Kojto 90:cb3d968589d8 3923 #define LCD_WF52 LCD_WF8B_REG(LCD,52)
Kojto 90:cb3d968589d8 3924 #define LCD_WF55TO52 LCD_WF_REG(LCD,13)
Kojto 90:cb3d968589d8 3925 #define LCD_WF53 LCD_WF8B_REG(LCD,53)
Kojto 90:cb3d968589d8 3926 #define LCD_WF54 LCD_WF8B_REG(LCD,54)
Kojto 90:cb3d968589d8 3927 #define LCD_WF55 LCD_WF8B_REG(LCD,55)
Kojto 90:cb3d968589d8 3928 #define LCD_WF56 LCD_WF8B_REG(LCD,56)
Kojto 90:cb3d968589d8 3929 #define LCD_WF59TO56 LCD_WF_REG(LCD,14)
Kojto 90:cb3d968589d8 3930 #define LCD_WF57 LCD_WF8B_REG(LCD,57)
Kojto 90:cb3d968589d8 3931 #define LCD_WF58 LCD_WF8B_REG(LCD,58)
Kojto 90:cb3d968589d8 3932 #define LCD_WF59 LCD_WF8B_REG(LCD,59)
Kojto 90:cb3d968589d8 3933 #define LCD_WF60 LCD_WF8B_REG(LCD,60)
Kojto 90:cb3d968589d8 3934 #define LCD_WF63TO60 LCD_WF_REG(LCD,15)
Kojto 90:cb3d968589d8 3935 #define LCD_WF61 LCD_WF8B_REG(LCD,61)
Kojto 90:cb3d968589d8 3936 #define LCD_WF62 LCD_WF8B_REG(LCD,62)
Kojto 90:cb3d968589d8 3937 #define LCD_WF63 LCD_WF8B_REG(LCD,63)
Kojto 90:cb3d968589d8 3938
Kojto 90:cb3d968589d8 3939 /* LCD - Register array accessors */
Kojto 90:cb3d968589d8 3940 #define LCD_PEN(index) LCD_PEN_REG(LCD,index)
Kojto 90:cb3d968589d8 3941 #define LCD_BPEN(index) LCD_BPEN_REG(LCD,index)
Kojto 90:cb3d968589d8 3942 #define LCD_WF(index2) LCD_WF_REG(LCD,index2)
Kojto 90:cb3d968589d8 3943 #define LCD_WF8B(index2) LCD_WF8B_REG(LCD,index2)
Kojto 90:cb3d968589d8 3944
Kojto 90:cb3d968589d8 3945 /*!
Kojto 90:cb3d968589d8 3946 * @}
Kojto 90:cb3d968589d8 3947 */ /* end of group LCD_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 3948
Kojto 90:cb3d968589d8 3949
Kojto 90:cb3d968589d8 3950 /*!
Kojto 90:cb3d968589d8 3951 * @}
Kojto 90:cb3d968589d8 3952 */ /* end of group LCD_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 3953
Kojto 90:cb3d968589d8 3954
Kojto 90:cb3d968589d8 3955 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3956 -- LLWU Peripheral Access Layer
Kojto 90:cb3d968589d8 3957 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3958
Kojto 90:cb3d968589d8 3959 /*!
Kojto 90:cb3d968589d8 3960 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
Kojto 90:cb3d968589d8 3961 * @{
Kojto 90:cb3d968589d8 3962 */
Kojto 90:cb3d968589d8 3963
Kojto 90:cb3d968589d8 3964 /** LLWU - Register Layout Typedef */
Kojto 90:cb3d968589d8 3965 typedef struct {
Kojto 90:cb3d968589d8 3966 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
Kojto 90:cb3d968589d8 3967 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
Kojto 90:cb3d968589d8 3968 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
Kojto 90:cb3d968589d8 3969 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
Kojto 90:cb3d968589d8 3970 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
Kojto 90:cb3d968589d8 3971 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
Kojto 90:cb3d968589d8 3972 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
Kojto 90:cb3d968589d8 3973 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
Kojto 90:cb3d968589d8 3974 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
Kojto 90:cb3d968589d8 3975 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
Kojto 90:cb3d968589d8 3976 } LLWU_Type, *LLWU_MemMapPtr;
Kojto 90:cb3d968589d8 3977
Kojto 90:cb3d968589d8 3978 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 3979 -- LLWU - Register accessor macros
Kojto 90:cb3d968589d8 3980 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 3981
Kojto 90:cb3d968589d8 3982 /*!
Kojto 90:cb3d968589d8 3983 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
Kojto 90:cb3d968589d8 3984 * @{
Kojto 90:cb3d968589d8 3985 */
Kojto 90:cb3d968589d8 3986
Kojto 90:cb3d968589d8 3987
Kojto 90:cb3d968589d8 3988 /* LLWU - Register accessors */
Kojto 90:cb3d968589d8 3989 #define LLWU_PE1_REG(base) ((base)->PE1)
Kojto 90:cb3d968589d8 3990 #define LLWU_PE2_REG(base) ((base)->PE2)
Kojto 90:cb3d968589d8 3991 #define LLWU_PE3_REG(base) ((base)->PE3)
Kojto 90:cb3d968589d8 3992 #define LLWU_PE4_REG(base) ((base)->PE4)
Kojto 90:cb3d968589d8 3993 #define LLWU_ME_REG(base) ((base)->ME)
Kojto 90:cb3d968589d8 3994 #define LLWU_F1_REG(base) ((base)->F1)
Kojto 90:cb3d968589d8 3995 #define LLWU_F2_REG(base) ((base)->F2)
Kojto 90:cb3d968589d8 3996 #define LLWU_F3_REG(base) ((base)->F3)
Kojto 90:cb3d968589d8 3997 #define LLWU_FILT1_REG(base) ((base)->FILT1)
Kojto 90:cb3d968589d8 3998 #define LLWU_FILT2_REG(base) ((base)->FILT2)
Kojto 90:cb3d968589d8 3999
Kojto 90:cb3d968589d8 4000 /*!
Kojto 90:cb3d968589d8 4001 * @}
Kojto 90:cb3d968589d8 4002 */ /* end of group LLWU_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4003
Kojto 90:cb3d968589d8 4004
Kojto 90:cb3d968589d8 4005 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4006 -- LLWU Register Masks
Kojto 90:cb3d968589d8 4007 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4008
Kojto 90:cb3d968589d8 4009 /*!
Kojto 90:cb3d968589d8 4010 * @addtogroup LLWU_Register_Masks LLWU Register Masks
Kojto 90:cb3d968589d8 4011 * @{
Kojto 90:cb3d968589d8 4012 */
Kojto 90:cb3d968589d8 4013
Kojto 90:cb3d968589d8 4014 /* PE1 Bit Fields */
Kojto 90:cb3d968589d8 4015 #define LLWU_PE1_WUPE0_MASK 0x3u
Kojto 90:cb3d968589d8 4016 #define LLWU_PE1_WUPE0_SHIFT 0
Kojto 90:cb3d968589d8 4017 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
Kojto 90:cb3d968589d8 4018 #define LLWU_PE1_WUPE1_MASK 0xCu
Kojto 90:cb3d968589d8 4019 #define LLWU_PE1_WUPE1_SHIFT 2
Kojto 90:cb3d968589d8 4020 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
Kojto 90:cb3d968589d8 4021 #define LLWU_PE1_WUPE2_MASK 0x30u
Kojto 90:cb3d968589d8 4022 #define LLWU_PE1_WUPE2_SHIFT 4
Kojto 90:cb3d968589d8 4023 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
Kojto 90:cb3d968589d8 4024 #define LLWU_PE1_WUPE3_MASK 0xC0u
Kojto 90:cb3d968589d8 4025 #define LLWU_PE1_WUPE3_SHIFT 6
Kojto 90:cb3d968589d8 4026 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
Kojto 90:cb3d968589d8 4027 /* PE2 Bit Fields */
Kojto 90:cb3d968589d8 4028 #define LLWU_PE2_WUPE4_MASK 0x3u
Kojto 90:cb3d968589d8 4029 #define LLWU_PE2_WUPE4_SHIFT 0
Kojto 90:cb3d968589d8 4030 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
Kojto 90:cb3d968589d8 4031 #define LLWU_PE2_WUPE5_MASK 0xCu
Kojto 90:cb3d968589d8 4032 #define LLWU_PE2_WUPE5_SHIFT 2
Kojto 90:cb3d968589d8 4033 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
Kojto 90:cb3d968589d8 4034 #define LLWU_PE2_WUPE6_MASK 0x30u
Kojto 90:cb3d968589d8 4035 #define LLWU_PE2_WUPE6_SHIFT 4
Kojto 90:cb3d968589d8 4036 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
Kojto 90:cb3d968589d8 4037 #define LLWU_PE2_WUPE7_MASK 0xC0u
Kojto 90:cb3d968589d8 4038 #define LLWU_PE2_WUPE7_SHIFT 6
Kojto 90:cb3d968589d8 4039 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
Kojto 90:cb3d968589d8 4040 /* PE3 Bit Fields */
Kojto 90:cb3d968589d8 4041 #define LLWU_PE3_WUPE8_MASK 0x3u
Kojto 90:cb3d968589d8 4042 #define LLWU_PE3_WUPE8_SHIFT 0
Kojto 90:cb3d968589d8 4043 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
Kojto 90:cb3d968589d8 4044 #define LLWU_PE3_WUPE9_MASK 0xCu
Kojto 90:cb3d968589d8 4045 #define LLWU_PE3_WUPE9_SHIFT 2
Kojto 90:cb3d968589d8 4046 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
Kojto 90:cb3d968589d8 4047 #define LLWU_PE3_WUPE10_MASK 0x30u
Kojto 90:cb3d968589d8 4048 #define LLWU_PE3_WUPE10_SHIFT 4
Kojto 90:cb3d968589d8 4049 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
Kojto 90:cb3d968589d8 4050 #define LLWU_PE3_WUPE11_MASK 0xC0u
Kojto 90:cb3d968589d8 4051 #define LLWU_PE3_WUPE11_SHIFT 6
Kojto 90:cb3d968589d8 4052 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
Kojto 90:cb3d968589d8 4053 /* PE4 Bit Fields */
Kojto 90:cb3d968589d8 4054 #define LLWU_PE4_WUPE12_MASK 0x3u
Kojto 90:cb3d968589d8 4055 #define LLWU_PE4_WUPE12_SHIFT 0
Kojto 90:cb3d968589d8 4056 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
Kojto 90:cb3d968589d8 4057 #define LLWU_PE4_WUPE13_MASK 0xCu
Kojto 90:cb3d968589d8 4058 #define LLWU_PE4_WUPE13_SHIFT 2
Kojto 90:cb3d968589d8 4059 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
Kojto 90:cb3d968589d8 4060 #define LLWU_PE4_WUPE14_MASK 0x30u
Kojto 90:cb3d968589d8 4061 #define LLWU_PE4_WUPE14_SHIFT 4
Kojto 90:cb3d968589d8 4062 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
Kojto 90:cb3d968589d8 4063 #define LLWU_PE4_WUPE15_MASK 0xC0u
Kojto 90:cb3d968589d8 4064 #define LLWU_PE4_WUPE15_SHIFT 6
Kojto 90:cb3d968589d8 4065 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
Kojto 90:cb3d968589d8 4066 /* ME Bit Fields */
Kojto 90:cb3d968589d8 4067 #define LLWU_ME_WUME0_MASK 0x1u
Kojto 90:cb3d968589d8 4068 #define LLWU_ME_WUME0_SHIFT 0
Kojto 90:cb3d968589d8 4069 #define LLWU_ME_WUME1_MASK 0x2u
Kojto 90:cb3d968589d8 4070 #define LLWU_ME_WUME1_SHIFT 1
Kojto 90:cb3d968589d8 4071 #define LLWU_ME_WUME2_MASK 0x4u
Kojto 90:cb3d968589d8 4072 #define LLWU_ME_WUME2_SHIFT 2
Kojto 90:cb3d968589d8 4073 #define LLWU_ME_WUME3_MASK 0x8u
Kojto 90:cb3d968589d8 4074 #define LLWU_ME_WUME3_SHIFT 3
Kojto 90:cb3d968589d8 4075 #define LLWU_ME_WUME4_MASK 0x10u
Kojto 90:cb3d968589d8 4076 #define LLWU_ME_WUME4_SHIFT 4
Kojto 90:cb3d968589d8 4077 #define LLWU_ME_WUME5_MASK 0x20u
Kojto 90:cb3d968589d8 4078 #define LLWU_ME_WUME5_SHIFT 5
Kojto 90:cb3d968589d8 4079 #define LLWU_ME_WUME6_MASK 0x40u
Kojto 90:cb3d968589d8 4080 #define LLWU_ME_WUME6_SHIFT 6
Kojto 90:cb3d968589d8 4081 #define LLWU_ME_WUME7_MASK 0x80u
Kojto 90:cb3d968589d8 4082 #define LLWU_ME_WUME7_SHIFT 7
Kojto 90:cb3d968589d8 4083 /* F1 Bit Fields */
Kojto 90:cb3d968589d8 4084 #define LLWU_F1_WUF0_MASK 0x1u
Kojto 90:cb3d968589d8 4085 #define LLWU_F1_WUF0_SHIFT 0
Kojto 90:cb3d968589d8 4086 #define LLWU_F1_WUF1_MASK 0x2u
Kojto 90:cb3d968589d8 4087 #define LLWU_F1_WUF1_SHIFT 1
Kojto 90:cb3d968589d8 4088 #define LLWU_F1_WUF2_MASK 0x4u
Kojto 90:cb3d968589d8 4089 #define LLWU_F1_WUF2_SHIFT 2
Kojto 90:cb3d968589d8 4090 #define LLWU_F1_WUF3_MASK 0x8u
Kojto 90:cb3d968589d8 4091 #define LLWU_F1_WUF3_SHIFT 3
Kojto 90:cb3d968589d8 4092 #define LLWU_F1_WUF4_MASK 0x10u
Kojto 90:cb3d968589d8 4093 #define LLWU_F1_WUF4_SHIFT 4
Kojto 90:cb3d968589d8 4094 #define LLWU_F1_WUF5_MASK 0x20u
Kojto 90:cb3d968589d8 4095 #define LLWU_F1_WUF5_SHIFT 5
Kojto 90:cb3d968589d8 4096 #define LLWU_F1_WUF6_MASK 0x40u
Kojto 90:cb3d968589d8 4097 #define LLWU_F1_WUF6_SHIFT 6
Kojto 90:cb3d968589d8 4098 #define LLWU_F1_WUF7_MASK 0x80u
Kojto 90:cb3d968589d8 4099 #define LLWU_F1_WUF7_SHIFT 7
Kojto 90:cb3d968589d8 4100 /* F2 Bit Fields */
Kojto 90:cb3d968589d8 4101 #define LLWU_F2_WUF8_MASK 0x1u
Kojto 90:cb3d968589d8 4102 #define LLWU_F2_WUF8_SHIFT 0
Kojto 90:cb3d968589d8 4103 #define LLWU_F2_WUF9_MASK 0x2u
Kojto 90:cb3d968589d8 4104 #define LLWU_F2_WUF9_SHIFT 1
Kojto 90:cb3d968589d8 4105 #define LLWU_F2_WUF10_MASK 0x4u
Kojto 90:cb3d968589d8 4106 #define LLWU_F2_WUF10_SHIFT 2
Kojto 90:cb3d968589d8 4107 #define LLWU_F2_WUF11_MASK 0x8u
Kojto 90:cb3d968589d8 4108 #define LLWU_F2_WUF11_SHIFT 3
Kojto 90:cb3d968589d8 4109 #define LLWU_F2_WUF12_MASK 0x10u
Kojto 90:cb3d968589d8 4110 #define LLWU_F2_WUF12_SHIFT 4
Kojto 90:cb3d968589d8 4111 #define LLWU_F2_WUF13_MASK 0x20u
Kojto 90:cb3d968589d8 4112 #define LLWU_F2_WUF13_SHIFT 5
Kojto 90:cb3d968589d8 4113 #define LLWU_F2_WUF14_MASK 0x40u
Kojto 90:cb3d968589d8 4114 #define LLWU_F2_WUF14_SHIFT 6
Kojto 90:cb3d968589d8 4115 #define LLWU_F2_WUF15_MASK 0x80u
Kojto 90:cb3d968589d8 4116 #define LLWU_F2_WUF15_SHIFT 7
Kojto 90:cb3d968589d8 4117 /* F3 Bit Fields */
Kojto 90:cb3d968589d8 4118 #define LLWU_F3_MWUF0_MASK 0x1u
Kojto 90:cb3d968589d8 4119 #define LLWU_F3_MWUF0_SHIFT 0
Kojto 90:cb3d968589d8 4120 #define LLWU_F3_MWUF1_MASK 0x2u
Kojto 90:cb3d968589d8 4121 #define LLWU_F3_MWUF1_SHIFT 1
Kojto 90:cb3d968589d8 4122 #define LLWU_F3_MWUF2_MASK 0x4u
Kojto 90:cb3d968589d8 4123 #define LLWU_F3_MWUF2_SHIFT 2
Kojto 90:cb3d968589d8 4124 #define LLWU_F3_MWUF3_MASK 0x8u
Kojto 90:cb3d968589d8 4125 #define LLWU_F3_MWUF3_SHIFT 3
Kojto 90:cb3d968589d8 4126 #define LLWU_F3_MWUF4_MASK 0x10u
Kojto 90:cb3d968589d8 4127 #define LLWU_F3_MWUF4_SHIFT 4
Kojto 90:cb3d968589d8 4128 #define LLWU_F3_MWUF5_MASK 0x20u
Kojto 90:cb3d968589d8 4129 #define LLWU_F3_MWUF5_SHIFT 5
Kojto 90:cb3d968589d8 4130 #define LLWU_F3_MWUF6_MASK 0x40u
Kojto 90:cb3d968589d8 4131 #define LLWU_F3_MWUF6_SHIFT 6
Kojto 90:cb3d968589d8 4132 #define LLWU_F3_MWUF7_MASK 0x80u
Kojto 90:cb3d968589d8 4133 #define LLWU_F3_MWUF7_SHIFT 7
Kojto 90:cb3d968589d8 4134 /* FILT1 Bit Fields */
Kojto 90:cb3d968589d8 4135 #define LLWU_FILT1_FILTSEL_MASK 0xFu
Kojto 90:cb3d968589d8 4136 #define LLWU_FILT1_FILTSEL_SHIFT 0
Kojto 90:cb3d968589d8 4137 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
Kojto 90:cb3d968589d8 4138 #define LLWU_FILT1_FILTE_MASK 0x60u
Kojto 90:cb3d968589d8 4139 #define LLWU_FILT1_FILTE_SHIFT 5
Kojto 90:cb3d968589d8 4140 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
Kojto 90:cb3d968589d8 4141 #define LLWU_FILT1_FILTF_MASK 0x80u
Kojto 90:cb3d968589d8 4142 #define LLWU_FILT1_FILTF_SHIFT 7
Kojto 90:cb3d968589d8 4143 /* FILT2 Bit Fields */
Kojto 90:cb3d968589d8 4144 #define LLWU_FILT2_FILTSEL_MASK 0xFu
Kojto 90:cb3d968589d8 4145 #define LLWU_FILT2_FILTSEL_SHIFT 0
Kojto 90:cb3d968589d8 4146 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
Kojto 90:cb3d968589d8 4147 #define LLWU_FILT2_FILTE_MASK 0x60u
Kojto 90:cb3d968589d8 4148 #define LLWU_FILT2_FILTE_SHIFT 5
Kojto 90:cb3d968589d8 4149 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
Kojto 90:cb3d968589d8 4150 #define LLWU_FILT2_FILTF_MASK 0x80u
Kojto 90:cb3d968589d8 4151 #define LLWU_FILT2_FILTF_SHIFT 7
Kojto 90:cb3d968589d8 4152
Kojto 90:cb3d968589d8 4153 /*!
Kojto 90:cb3d968589d8 4154 * @}
Kojto 90:cb3d968589d8 4155 */ /* end of group LLWU_Register_Masks */
Kojto 90:cb3d968589d8 4156
Kojto 90:cb3d968589d8 4157
Kojto 90:cb3d968589d8 4158 /* LLWU - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 4159 /** Peripheral LLWU base address */
Kojto 90:cb3d968589d8 4160 #define LLWU_BASE (0x4007C000u)
Kojto 90:cb3d968589d8 4161 /** Peripheral LLWU base pointer */
Kojto 90:cb3d968589d8 4162 #define LLWU ((LLWU_Type *)LLWU_BASE)
Kojto 90:cb3d968589d8 4163 #define LLWU_BASE_PTR (LLWU)
Kojto 90:cb3d968589d8 4164 /** Array initializer of LLWU peripheral base addresses */
Kojto 90:cb3d968589d8 4165 #define LLWU_BASE_ADDRS { LLWU_BASE }
Kojto 90:cb3d968589d8 4166 /** Array initializer of LLWU peripheral base pointers */
Kojto 90:cb3d968589d8 4167 #define LLWU_BASE_PTRS { LLWU }
Kojto 90:cb3d968589d8 4168 /** Interrupt vectors for the LLWU peripheral type */
Kojto 90:cb3d968589d8 4169 #define LLWU_IRQS { LLWU_IRQn }
Kojto 90:cb3d968589d8 4170
Kojto 90:cb3d968589d8 4171 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4172 -- LLWU - Register accessor macros
Kojto 90:cb3d968589d8 4173 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4174
Kojto 90:cb3d968589d8 4175 /*!
Kojto 90:cb3d968589d8 4176 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
Kojto 90:cb3d968589d8 4177 * @{
Kojto 90:cb3d968589d8 4178 */
Kojto 90:cb3d968589d8 4179
Kojto 90:cb3d968589d8 4180
Kojto 90:cb3d968589d8 4181 /* LLWU - Register instance definitions */
Kojto 90:cb3d968589d8 4182 /* LLWU */
Kojto 90:cb3d968589d8 4183 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
Kojto 90:cb3d968589d8 4184 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
Kojto 90:cb3d968589d8 4185 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
Kojto 90:cb3d968589d8 4186 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
Kojto 90:cb3d968589d8 4187 #define LLWU_ME LLWU_ME_REG(LLWU)
Kojto 90:cb3d968589d8 4188 #define LLWU_F1 LLWU_F1_REG(LLWU)
Kojto 90:cb3d968589d8 4189 #define LLWU_F2 LLWU_F2_REG(LLWU)
Kojto 90:cb3d968589d8 4190 #define LLWU_F3 LLWU_F3_REG(LLWU)
Kojto 90:cb3d968589d8 4191 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
Kojto 90:cb3d968589d8 4192 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
Kojto 90:cb3d968589d8 4193
Kojto 90:cb3d968589d8 4194 /*!
Kojto 90:cb3d968589d8 4195 * @}
Kojto 90:cb3d968589d8 4196 */ /* end of group LLWU_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4197
Kojto 90:cb3d968589d8 4198
Kojto 90:cb3d968589d8 4199 /*!
Kojto 90:cb3d968589d8 4200 * @}
Kojto 90:cb3d968589d8 4201 */ /* end of group LLWU_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 4202
Kojto 90:cb3d968589d8 4203
Kojto 90:cb3d968589d8 4204 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4205 -- LPTMR Peripheral Access Layer
Kojto 90:cb3d968589d8 4206 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4207
Kojto 90:cb3d968589d8 4208 /*!
Kojto 90:cb3d968589d8 4209 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
Kojto 90:cb3d968589d8 4210 * @{
Kojto 90:cb3d968589d8 4211 */
Kojto 90:cb3d968589d8 4212
Kojto 90:cb3d968589d8 4213 /** LPTMR - Register Layout Typedef */
Kojto 90:cb3d968589d8 4214 typedef struct {
Kojto 90:cb3d968589d8 4215 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
Kojto 90:cb3d968589d8 4216 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
Kojto 90:cb3d968589d8 4217 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
Kojto 90:cb3d968589d8 4218 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
Kojto 90:cb3d968589d8 4219 } LPTMR_Type, *LPTMR_MemMapPtr;
Kojto 90:cb3d968589d8 4220
Kojto 90:cb3d968589d8 4221 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4222 -- LPTMR - Register accessor macros
Kojto 90:cb3d968589d8 4223 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4224
Kojto 90:cb3d968589d8 4225 /*!
Kojto 90:cb3d968589d8 4226 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
Kojto 90:cb3d968589d8 4227 * @{
Kojto 90:cb3d968589d8 4228 */
Kojto 90:cb3d968589d8 4229
Kojto 90:cb3d968589d8 4230
Kojto 90:cb3d968589d8 4231 /* LPTMR - Register accessors */
Kojto 90:cb3d968589d8 4232 #define LPTMR_CSR_REG(base) ((base)->CSR)
Kojto 90:cb3d968589d8 4233 #define LPTMR_PSR_REG(base) ((base)->PSR)
Kojto 90:cb3d968589d8 4234 #define LPTMR_CMR_REG(base) ((base)->CMR)
Kojto 90:cb3d968589d8 4235 #define LPTMR_CNR_REG(base) ((base)->CNR)
Kojto 90:cb3d968589d8 4236
Kojto 90:cb3d968589d8 4237 /*!
Kojto 90:cb3d968589d8 4238 * @}
Kojto 90:cb3d968589d8 4239 */ /* end of group LPTMR_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4240
Kojto 90:cb3d968589d8 4241
Kojto 90:cb3d968589d8 4242 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4243 -- LPTMR Register Masks
Kojto 90:cb3d968589d8 4244 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4245
Kojto 90:cb3d968589d8 4246 /*!
Kojto 90:cb3d968589d8 4247 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
Kojto 90:cb3d968589d8 4248 * @{
Kojto 90:cb3d968589d8 4249 */
Kojto 90:cb3d968589d8 4250
Kojto 90:cb3d968589d8 4251 /* CSR Bit Fields */
Kojto 90:cb3d968589d8 4252 #define LPTMR_CSR_TEN_MASK 0x1u
Kojto 90:cb3d968589d8 4253 #define LPTMR_CSR_TEN_SHIFT 0
Kojto 90:cb3d968589d8 4254 #define LPTMR_CSR_TMS_MASK 0x2u
Kojto 90:cb3d968589d8 4255 #define LPTMR_CSR_TMS_SHIFT 1
Kojto 90:cb3d968589d8 4256 #define LPTMR_CSR_TFC_MASK 0x4u
Kojto 90:cb3d968589d8 4257 #define LPTMR_CSR_TFC_SHIFT 2
Kojto 90:cb3d968589d8 4258 #define LPTMR_CSR_TPP_MASK 0x8u
Kojto 90:cb3d968589d8 4259 #define LPTMR_CSR_TPP_SHIFT 3
Kojto 90:cb3d968589d8 4260 #define LPTMR_CSR_TPS_MASK 0x30u
Kojto 90:cb3d968589d8 4261 #define LPTMR_CSR_TPS_SHIFT 4
Kojto 90:cb3d968589d8 4262 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
Kojto 90:cb3d968589d8 4263 #define LPTMR_CSR_TIE_MASK 0x40u
Kojto 90:cb3d968589d8 4264 #define LPTMR_CSR_TIE_SHIFT 6
Kojto 90:cb3d968589d8 4265 #define LPTMR_CSR_TCF_MASK 0x80u
Kojto 90:cb3d968589d8 4266 #define LPTMR_CSR_TCF_SHIFT 7
Kojto 90:cb3d968589d8 4267 /* PSR Bit Fields */
Kojto 90:cb3d968589d8 4268 #define LPTMR_PSR_PCS_MASK 0x3u
Kojto 90:cb3d968589d8 4269 #define LPTMR_PSR_PCS_SHIFT 0
Kojto 90:cb3d968589d8 4270 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
Kojto 90:cb3d968589d8 4271 #define LPTMR_PSR_PBYP_MASK 0x4u
Kojto 90:cb3d968589d8 4272 #define LPTMR_PSR_PBYP_SHIFT 2
Kojto 90:cb3d968589d8 4273 #define LPTMR_PSR_PRESCALE_MASK 0x78u
Kojto 90:cb3d968589d8 4274 #define LPTMR_PSR_PRESCALE_SHIFT 3
Kojto 90:cb3d968589d8 4275 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
Kojto 90:cb3d968589d8 4276 /* CMR Bit Fields */
Kojto 90:cb3d968589d8 4277 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
Kojto 90:cb3d968589d8 4278 #define LPTMR_CMR_COMPARE_SHIFT 0
Kojto 90:cb3d968589d8 4279 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
Kojto 90:cb3d968589d8 4280 /* CNR Bit Fields */
Kojto 90:cb3d968589d8 4281 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
Kojto 90:cb3d968589d8 4282 #define LPTMR_CNR_COUNTER_SHIFT 0
Kojto 90:cb3d968589d8 4283 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
Kojto 90:cb3d968589d8 4284
Kojto 90:cb3d968589d8 4285 /*!
Kojto 90:cb3d968589d8 4286 * @}
Kojto 90:cb3d968589d8 4287 */ /* end of group LPTMR_Register_Masks */
Kojto 90:cb3d968589d8 4288
Kojto 90:cb3d968589d8 4289
Kojto 90:cb3d968589d8 4290 /* LPTMR - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 4291 /** Peripheral LPTMR0 base address */
Kojto 90:cb3d968589d8 4292 #define LPTMR0_BASE (0x40040000u)
Kojto 90:cb3d968589d8 4293 /** Peripheral LPTMR0 base pointer */
Kojto 90:cb3d968589d8 4294 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
Kojto 90:cb3d968589d8 4295 #define LPTMR0_BASE_PTR (LPTMR0)
Kojto 90:cb3d968589d8 4296 /** Array initializer of LPTMR peripheral base addresses */
Kojto 90:cb3d968589d8 4297 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
Kojto 90:cb3d968589d8 4298 /** Array initializer of LPTMR peripheral base pointers */
Kojto 90:cb3d968589d8 4299 #define LPTMR_BASE_PTRS { LPTMR0 }
Kojto 90:cb3d968589d8 4300 /** Interrupt vectors for the LPTMR peripheral type */
Kojto 90:cb3d968589d8 4301 #define LPTMR_IRQS { LPTMR0_IRQn }
Kojto 90:cb3d968589d8 4302
Kojto 90:cb3d968589d8 4303 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4304 -- LPTMR - Register accessor macros
Kojto 90:cb3d968589d8 4305 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4306
Kojto 90:cb3d968589d8 4307 /*!
Kojto 90:cb3d968589d8 4308 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
Kojto 90:cb3d968589d8 4309 * @{
Kojto 90:cb3d968589d8 4310 */
Kojto 90:cb3d968589d8 4311
Kojto 90:cb3d968589d8 4312
Kojto 90:cb3d968589d8 4313 /* LPTMR - Register instance definitions */
Kojto 90:cb3d968589d8 4314 /* LPTMR0 */
Kojto 90:cb3d968589d8 4315 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
Kojto 90:cb3d968589d8 4316 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
Kojto 90:cb3d968589d8 4317 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
Kojto 90:cb3d968589d8 4318 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
Kojto 90:cb3d968589d8 4319
Kojto 90:cb3d968589d8 4320 /*!
Kojto 90:cb3d968589d8 4321 * @}
Kojto 90:cb3d968589d8 4322 */ /* end of group LPTMR_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4323
Kojto 90:cb3d968589d8 4324
Kojto 90:cb3d968589d8 4325 /*!
Kojto 90:cb3d968589d8 4326 * @}
Kojto 90:cb3d968589d8 4327 */ /* end of group LPTMR_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 4328
Kojto 90:cb3d968589d8 4329
Kojto 90:cb3d968589d8 4330 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4331 -- LPUART Peripheral Access Layer
Kojto 90:cb3d968589d8 4332 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4333
Kojto 90:cb3d968589d8 4334 /*!
Kojto 90:cb3d968589d8 4335 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
Kojto 90:cb3d968589d8 4336 * @{
Kojto 90:cb3d968589d8 4337 */
Kojto 90:cb3d968589d8 4338
Kojto 90:cb3d968589d8 4339 /** LPUART - Register Layout Typedef */
Kojto 90:cb3d968589d8 4340 typedef struct {
Kojto 90:cb3d968589d8 4341 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
Kojto 90:cb3d968589d8 4342 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
Kojto 90:cb3d968589d8 4343 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
Kojto 90:cb3d968589d8 4344 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
Kojto 90:cb3d968589d8 4345 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
Kojto 90:cb3d968589d8 4346 } LPUART_Type, *LPUART_MemMapPtr;
Kojto 90:cb3d968589d8 4347
Kojto 90:cb3d968589d8 4348 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4349 -- LPUART - Register accessor macros
Kojto 90:cb3d968589d8 4350 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4351
Kojto 90:cb3d968589d8 4352 /*!
Kojto 90:cb3d968589d8 4353 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
Kojto 90:cb3d968589d8 4354 * @{
Kojto 90:cb3d968589d8 4355 */
Kojto 90:cb3d968589d8 4356
Kojto 90:cb3d968589d8 4357
Kojto 90:cb3d968589d8 4358 /* LPUART - Register accessors */
Kojto 90:cb3d968589d8 4359 #define LPUART_BAUD_REG(base) ((base)->BAUD)
Kojto 90:cb3d968589d8 4360 #define LPUART_STAT_REG(base) ((base)->STAT)
Kojto 90:cb3d968589d8 4361 #define LPUART_CTRL_REG(base) ((base)->CTRL)
Kojto 90:cb3d968589d8 4362 #define LPUART_DATA_REG(base) ((base)->DATA)
Kojto 90:cb3d968589d8 4363 #define LPUART_MATCH_REG(base) ((base)->MATCH)
Kojto 90:cb3d968589d8 4364
Kojto 90:cb3d968589d8 4365 /*!
Kojto 90:cb3d968589d8 4366 * @}
Kojto 90:cb3d968589d8 4367 */ /* end of group LPUART_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4368
Kojto 90:cb3d968589d8 4369
Kojto 90:cb3d968589d8 4370 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4371 -- LPUART Register Masks
Kojto 90:cb3d968589d8 4372 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4373
Kojto 90:cb3d968589d8 4374 /*!
Kojto 90:cb3d968589d8 4375 * @addtogroup LPUART_Register_Masks LPUART Register Masks
Kojto 90:cb3d968589d8 4376 * @{
Kojto 90:cb3d968589d8 4377 */
Kojto 90:cb3d968589d8 4378
Kojto 90:cb3d968589d8 4379 /* BAUD Bit Fields */
Kojto 90:cb3d968589d8 4380 #define LPUART_BAUD_SBR_MASK 0x1FFFu
Kojto 90:cb3d968589d8 4381 #define LPUART_BAUD_SBR_SHIFT 0
Kojto 90:cb3d968589d8 4382 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
Kojto 90:cb3d968589d8 4383 #define LPUART_BAUD_SBNS_MASK 0x2000u
Kojto 90:cb3d968589d8 4384 #define LPUART_BAUD_SBNS_SHIFT 13
Kojto 90:cb3d968589d8 4385 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u
Kojto 90:cb3d968589d8 4386 #define LPUART_BAUD_RXEDGIE_SHIFT 14
Kojto 90:cb3d968589d8 4387 #define LPUART_BAUD_LBKDIE_MASK 0x8000u
Kojto 90:cb3d968589d8 4388 #define LPUART_BAUD_LBKDIE_SHIFT 15
Kojto 90:cb3d968589d8 4389 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
Kojto 90:cb3d968589d8 4390 #define LPUART_BAUD_RESYNCDIS_SHIFT 16
Kojto 90:cb3d968589d8 4391 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
Kojto 90:cb3d968589d8 4392 #define LPUART_BAUD_BOTHEDGE_SHIFT 17
Kojto 90:cb3d968589d8 4393 #define LPUART_BAUD_MATCFG_MASK 0xC0000u
Kojto 90:cb3d968589d8 4394 #define LPUART_BAUD_MATCFG_SHIFT 18
Kojto 90:cb3d968589d8 4395 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
Kojto 90:cb3d968589d8 4396 #define LPUART_BAUD_RDMAE_MASK 0x200000u
Kojto 90:cb3d968589d8 4397 #define LPUART_BAUD_RDMAE_SHIFT 21
Kojto 90:cb3d968589d8 4398 #define LPUART_BAUD_TDMAE_MASK 0x800000u
Kojto 90:cb3d968589d8 4399 #define LPUART_BAUD_TDMAE_SHIFT 23
Kojto 90:cb3d968589d8 4400 #define LPUART_BAUD_OSR_MASK 0x1F000000u
Kojto 90:cb3d968589d8 4401 #define LPUART_BAUD_OSR_SHIFT 24
Kojto 90:cb3d968589d8 4402 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
Kojto 90:cb3d968589d8 4403 #define LPUART_BAUD_M10_MASK 0x20000000u
Kojto 90:cb3d968589d8 4404 #define LPUART_BAUD_M10_SHIFT 29
Kojto 90:cb3d968589d8 4405 #define LPUART_BAUD_MAEN2_MASK 0x40000000u
Kojto 90:cb3d968589d8 4406 #define LPUART_BAUD_MAEN2_SHIFT 30
Kojto 90:cb3d968589d8 4407 #define LPUART_BAUD_MAEN1_MASK 0x80000000u
Kojto 90:cb3d968589d8 4408 #define LPUART_BAUD_MAEN1_SHIFT 31
Kojto 90:cb3d968589d8 4409 /* STAT Bit Fields */
Kojto 90:cb3d968589d8 4410 #define LPUART_STAT_MA2F_MASK 0x4000u
Kojto 90:cb3d968589d8 4411 #define LPUART_STAT_MA2F_SHIFT 14
Kojto 90:cb3d968589d8 4412 #define LPUART_STAT_MA1F_MASK 0x8000u
Kojto 90:cb3d968589d8 4413 #define LPUART_STAT_MA1F_SHIFT 15
Kojto 90:cb3d968589d8 4414 #define LPUART_STAT_PF_MASK 0x10000u
Kojto 90:cb3d968589d8 4415 #define LPUART_STAT_PF_SHIFT 16
Kojto 90:cb3d968589d8 4416 #define LPUART_STAT_FE_MASK 0x20000u
Kojto 90:cb3d968589d8 4417 #define LPUART_STAT_FE_SHIFT 17
Kojto 90:cb3d968589d8 4418 #define LPUART_STAT_NF_MASK 0x40000u
Kojto 90:cb3d968589d8 4419 #define LPUART_STAT_NF_SHIFT 18
Kojto 90:cb3d968589d8 4420 #define LPUART_STAT_OR_MASK 0x80000u
Kojto 90:cb3d968589d8 4421 #define LPUART_STAT_OR_SHIFT 19
Kojto 90:cb3d968589d8 4422 #define LPUART_STAT_IDLE_MASK 0x100000u
Kojto 90:cb3d968589d8 4423 #define LPUART_STAT_IDLE_SHIFT 20
Kojto 90:cb3d968589d8 4424 #define LPUART_STAT_RDRF_MASK 0x200000u
Kojto 90:cb3d968589d8 4425 #define LPUART_STAT_RDRF_SHIFT 21
Kojto 90:cb3d968589d8 4426 #define LPUART_STAT_TC_MASK 0x400000u
Kojto 90:cb3d968589d8 4427 #define LPUART_STAT_TC_SHIFT 22
Kojto 90:cb3d968589d8 4428 #define LPUART_STAT_TDRE_MASK 0x800000u
Kojto 90:cb3d968589d8 4429 #define LPUART_STAT_TDRE_SHIFT 23
Kojto 90:cb3d968589d8 4430 #define LPUART_STAT_RAF_MASK 0x1000000u
Kojto 90:cb3d968589d8 4431 #define LPUART_STAT_RAF_SHIFT 24
Kojto 90:cb3d968589d8 4432 #define LPUART_STAT_LBKDE_MASK 0x2000000u
Kojto 90:cb3d968589d8 4433 #define LPUART_STAT_LBKDE_SHIFT 25
Kojto 90:cb3d968589d8 4434 #define LPUART_STAT_BRK13_MASK 0x4000000u
Kojto 90:cb3d968589d8 4435 #define LPUART_STAT_BRK13_SHIFT 26
Kojto 90:cb3d968589d8 4436 #define LPUART_STAT_RWUID_MASK 0x8000000u
Kojto 90:cb3d968589d8 4437 #define LPUART_STAT_RWUID_SHIFT 27
Kojto 90:cb3d968589d8 4438 #define LPUART_STAT_RXINV_MASK 0x10000000u
Kojto 90:cb3d968589d8 4439 #define LPUART_STAT_RXINV_SHIFT 28
Kojto 90:cb3d968589d8 4440 #define LPUART_STAT_MSBF_MASK 0x20000000u
Kojto 90:cb3d968589d8 4441 #define LPUART_STAT_MSBF_SHIFT 29
Kojto 90:cb3d968589d8 4442 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u
Kojto 90:cb3d968589d8 4443 #define LPUART_STAT_RXEDGIF_SHIFT 30
Kojto 90:cb3d968589d8 4444 #define LPUART_STAT_LBKDIF_MASK 0x80000000u
Kojto 90:cb3d968589d8 4445 #define LPUART_STAT_LBKDIF_SHIFT 31
Kojto 90:cb3d968589d8 4446 /* CTRL Bit Fields */
Kojto 90:cb3d968589d8 4447 #define LPUART_CTRL_PT_MASK 0x1u
Kojto 90:cb3d968589d8 4448 #define LPUART_CTRL_PT_SHIFT 0
Kojto 90:cb3d968589d8 4449 #define LPUART_CTRL_PE_MASK 0x2u
Kojto 90:cb3d968589d8 4450 #define LPUART_CTRL_PE_SHIFT 1
Kojto 90:cb3d968589d8 4451 #define LPUART_CTRL_ILT_MASK 0x4u
Kojto 90:cb3d968589d8 4452 #define LPUART_CTRL_ILT_SHIFT 2
Kojto 90:cb3d968589d8 4453 #define LPUART_CTRL_WAKE_MASK 0x8u
Kojto 90:cb3d968589d8 4454 #define LPUART_CTRL_WAKE_SHIFT 3
Kojto 90:cb3d968589d8 4455 #define LPUART_CTRL_M_MASK 0x10u
Kojto 90:cb3d968589d8 4456 #define LPUART_CTRL_M_SHIFT 4
Kojto 90:cb3d968589d8 4457 #define LPUART_CTRL_RSRC_MASK 0x20u
Kojto 90:cb3d968589d8 4458 #define LPUART_CTRL_RSRC_SHIFT 5
Kojto 90:cb3d968589d8 4459 #define LPUART_CTRL_DOZEEN_MASK 0x40u
Kojto 90:cb3d968589d8 4460 #define LPUART_CTRL_DOZEEN_SHIFT 6
Kojto 90:cb3d968589d8 4461 #define LPUART_CTRL_LOOPS_MASK 0x80u
Kojto 90:cb3d968589d8 4462 #define LPUART_CTRL_LOOPS_SHIFT 7
Kojto 90:cb3d968589d8 4463 #define LPUART_CTRL_IDLECFG_MASK 0x700u
Kojto 90:cb3d968589d8 4464 #define LPUART_CTRL_IDLECFG_SHIFT 8
Kojto 90:cb3d968589d8 4465 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
Kojto 90:cb3d968589d8 4466 #define LPUART_CTRL_MA2IE_MASK 0x4000u
Kojto 90:cb3d968589d8 4467 #define LPUART_CTRL_MA2IE_SHIFT 14
Kojto 90:cb3d968589d8 4468 #define LPUART_CTRL_MA1IE_MASK 0x8000u
Kojto 90:cb3d968589d8 4469 #define LPUART_CTRL_MA1IE_SHIFT 15
Kojto 90:cb3d968589d8 4470 #define LPUART_CTRL_SBK_MASK 0x10000u
Kojto 90:cb3d968589d8 4471 #define LPUART_CTRL_SBK_SHIFT 16
Kojto 90:cb3d968589d8 4472 #define LPUART_CTRL_RWU_MASK 0x20000u
Kojto 90:cb3d968589d8 4473 #define LPUART_CTRL_RWU_SHIFT 17
Kojto 90:cb3d968589d8 4474 #define LPUART_CTRL_RE_MASK 0x40000u
Kojto 90:cb3d968589d8 4475 #define LPUART_CTRL_RE_SHIFT 18
Kojto 90:cb3d968589d8 4476 #define LPUART_CTRL_TE_MASK 0x80000u
Kojto 90:cb3d968589d8 4477 #define LPUART_CTRL_TE_SHIFT 19
Kojto 90:cb3d968589d8 4478 #define LPUART_CTRL_ILIE_MASK 0x100000u
Kojto 90:cb3d968589d8 4479 #define LPUART_CTRL_ILIE_SHIFT 20
Kojto 90:cb3d968589d8 4480 #define LPUART_CTRL_RIE_MASK 0x200000u
Kojto 90:cb3d968589d8 4481 #define LPUART_CTRL_RIE_SHIFT 21
Kojto 90:cb3d968589d8 4482 #define LPUART_CTRL_TCIE_MASK 0x400000u
Kojto 90:cb3d968589d8 4483 #define LPUART_CTRL_TCIE_SHIFT 22
Kojto 90:cb3d968589d8 4484 #define LPUART_CTRL_TIE_MASK 0x800000u
Kojto 90:cb3d968589d8 4485 #define LPUART_CTRL_TIE_SHIFT 23
Kojto 90:cb3d968589d8 4486 #define LPUART_CTRL_PEIE_MASK 0x1000000u
Kojto 90:cb3d968589d8 4487 #define LPUART_CTRL_PEIE_SHIFT 24
Kojto 90:cb3d968589d8 4488 #define LPUART_CTRL_FEIE_MASK 0x2000000u
Kojto 90:cb3d968589d8 4489 #define LPUART_CTRL_FEIE_SHIFT 25
Kojto 90:cb3d968589d8 4490 #define LPUART_CTRL_NEIE_MASK 0x4000000u
Kojto 90:cb3d968589d8 4491 #define LPUART_CTRL_NEIE_SHIFT 26
Kojto 90:cb3d968589d8 4492 #define LPUART_CTRL_ORIE_MASK 0x8000000u
Kojto 90:cb3d968589d8 4493 #define LPUART_CTRL_ORIE_SHIFT 27
Kojto 90:cb3d968589d8 4494 #define LPUART_CTRL_TXINV_MASK 0x10000000u
Kojto 90:cb3d968589d8 4495 #define LPUART_CTRL_TXINV_SHIFT 28
Kojto 90:cb3d968589d8 4496 #define LPUART_CTRL_TXDIR_MASK 0x20000000u
Kojto 90:cb3d968589d8 4497 #define LPUART_CTRL_TXDIR_SHIFT 29
Kojto 90:cb3d968589d8 4498 #define LPUART_CTRL_R9T8_MASK 0x40000000u
Kojto 90:cb3d968589d8 4499 #define LPUART_CTRL_R9T8_SHIFT 30
Kojto 90:cb3d968589d8 4500 #define LPUART_CTRL_R8T9_MASK 0x80000000u
Kojto 90:cb3d968589d8 4501 #define LPUART_CTRL_R8T9_SHIFT 31
Kojto 90:cb3d968589d8 4502 /* DATA Bit Fields */
Kojto 90:cb3d968589d8 4503 #define LPUART_DATA_R0T0_MASK 0x1u
Kojto 90:cb3d968589d8 4504 #define LPUART_DATA_R0T0_SHIFT 0
Kojto 90:cb3d968589d8 4505 #define LPUART_DATA_R1T1_MASK 0x2u
Kojto 90:cb3d968589d8 4506 #define LPUART_DATA_R1T1_SHIFT 1
Kojto 90:cb3d968589d8 4507 #define LPUART_DATA_R2T2_MASK 0x4u
Kojto 90:cb3d968589d8 4508 #define LPUART_DATA_R2T2_SHIFT 2
Kojto 90:cb3d968589d8 4509 #define LPUART_DATA_R3T3_MASK 0x8u
Kojto 90:cb3d968589d8 4510 #define LPUART_DATA_R3T3_SHIFT 3
Kojto 90:cb3d968589d8 4511 #define LPUART_DATA_R4T4_MASK 0x10u
Kojto 90:cb3d968589d8 4512 #define LPUART_DATA_R4T4_SHIFT 4
Kojto 90:cb3d968589d8 4513 #define LPUART_DATA_R5T5_MASK 0x20u
Kojto 90:cb3d968589d8 4514 #define LPUART_DATA_R5T5_SHIFT 5
Kojto 90:cb3d968589d8 4515 #define LPUART_DATA_R6T6_MASK 0x40u
Kojto 90:cb3d968589d8 4516 #define LPUART_DATA_R6T6_SHIFT 6
Kojto 90:cb3d968589d8 4517 #define LPUART_DATA_R7T7_MASK 0x80u
Kojto 90:cb3d968589d8 4518 #define LPUART_DATA_R7T7_SHIFT 7
Kojto 90:cb3d968589d8 4519 #define LPUART_DATA_R8T8_MASK 0x100u
Kojto 90:cb3d968589d8 4520 #define LPUART_DATA_R8T8_SHIFT 8
Kojto 90:cb3d968589d8 4521 #define LPUART_DATA_R9T9_MASK 0x200u
Kojto 90:cb3d968589d8 4522 #define LPUART_DATA_R9T9_SHIFT 9
Kojto 90:cb3d968589d8 4523 #define LPUART_DATA_IDLINE_MASK 0x800u
Kojto 90:cb3d968589d8 4524 #define LPUART_DATA_IDLINE_SHIFT 11
Kojto 90:cb3d968589d8 4525 #define LPUART_DATA_RXEMPT_MASK 0x1000u
Kojto 90:cb3d968589d8 4526 #define LPUART_DATA_RXEMPT_SHIFT 12
Kojto 90:cb3d968589d8 4527 #define LPUART_DATA_FRETSC_MASK 0x2000u
Kojto 90:cb3d968589d8 4528 #define LPUART_DATA_FRETSC_SHIFT 13
Kojto 90:cb3d968589d8 4529 #define LPUART_DATA_PARITYE_MASK 0x4000u
Kojto 90:cb3d968589d8 4530 #define LPUART_DATA_PARITYE_SHIFT 14
Kojto 90:cb3d968589d8 4531 #define LPUART_DATA_NOISY_MASK 0x8000u
Kojto 90:cb3d968589d8 4532 #define LPUART_DATA_NOISY_SHIFT 15
Kojto 90:cb3d968589d8 4533 /* MATCH Bit Fields */
Kojto 90:cb3d968589d8 4534 #define LPUART_MATCH_MA1_MASK 0x3FFu
Kojto 90:cb3d968589d8 4535 #define LPUART_MATCH_MA1_SHIFT 0
Kojto 90:cb3d968589d8 4536 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
Kojto 90:cb3d968589d8 4537 #define LPUART_MATCH_MA2_MASK 0x3FF0000u
Kojto 90:cb3d968589d8 4538 #define LPUART_MATCH_MA2_SHIFT 16
Kojto 90:cb3d968589d8 4539 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
Kojto 90:cb3d968589d8 4540
Kojto 90:cb3d968589d8 4541 /*!
Kojto 90:cb3d968589d8 4542 * @}
Kojto 90:cb3d968589d8 4543 */ /* end of group LPUART_Register_Masks */
Kojto 90:cb3d968589d8 4544
Kojto 90:cb3d968589d8 4545
Kojto 90:cb3d968589d8 4546 /* LPUART - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 4547 /** Peripheral LPUART0 base address */
Kojto 90:cb3d968589d8 4548 #define LPUART0_BASE (0x40054000u)
Kojto 90:cb3d968589d8 4549 /** Peripheral LPUART0 base pointer */
Kojto 90:cb3d968589d8 4550 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
Kojto 90:cb3d968589d8 4551 #define LPUART0_BASE_PTR (LPUART0)
Kojto 90:cb3d968589d8 4552 /** Peripheral LPUART1 base address */
Kojto 90:cb3d968589d8 4553 #define LPUART1_BASE (0x40055000u)
Kojto 90:cb3d968589d8 4554 /** Peripheral LPUART1 base pointer */
Kojto 90:cb3d968589d8 4555 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
Kojto 90:cb3d968589d8 4556 #define LPUART1_BASE_PTR (LPUART1)
Kojto 90:cb3d968589d8 4557 /** Array initializer of LPUART peripheral base addresses */
Kojto 90:cb3d968589d8 4558 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE }
Kojto 90:cb3d968589d8 4559 /** Array initializer of LPUART peripheral base pointers */
Kojto 90:cb3d968589d8 4560 #define LPUART_BASE_PTRS { LPUART0, LPUART1 }
Kojto 90:cb3d968589d8 4561 /** Interrupt vectors for the LPUART peripheral type */
Kojto 90:cb3d968589d8 4562 #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn }
Kojto 90:cb3d968589d8 4563 #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn }
Kojto 90:cb3d968589d8 4564
Kojto 90:cb3d968589d8 4565 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4566 -- LPUART - Register accessor macros
Kojto 90:cb3d968589d8 4567 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4568
Kojto 90:cb3d968589d8 4569 /*!
Kojto 90:cb3d968589d8 4570 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
Kojto 90:cb3d968589d8 4571 * @{
Kojto 90:cb3d968589d8 4572 */
Kojto 90:cb3d968589d8 4573
Kojto 90:cb3d968589d8 4574
Kojto 90:cb3d968589d8 4575 /* LPUART - Register instance definitions */
Kojto 90:cb3d968589d8 4576 /* LPUART0 */
Kojto 90:cb3d968589d8 4577 #define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
Kojto 90:cb3d968589d8 4578 #define LPUART0_STAT LPUART_STAT_REG(LPUART0)
Kojto 90:cb3d968589d8 4579 #define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
Kojto 90:cb3d968589d8 4580 #define LPUART0_DATA LPUART_DATA_REG(LPUART0)
Kojto 90:cb3d968589d8 4581 #define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
Kojto 90:cb3d968589d8 4582 /* LPUART1 */
Kojto 90:cb3d968589d8 4583 #define LPUART1_BAUD LPUART_BAUD_REG(LPUART1)
Kojto 90:cb3d968589d8 4584 #define LPUART1_STAT LPUART_STAT_REG(LPUART1)
Kojto 90:cb3d968589d8 4585 #define LPUART1_CTRL LPUART_CTRL_REG(LPUART1)
Kojto 90:cb3d968589d8 4586 #define LPUART1_DATA LPUART_DATA_REG(LPUART1)
Kojto 90:cb3d968589d8 4587 #define LPUART1_MATCH LPUART_MATCH_REG(LPUART1)
Kojto 90:cb3d968589d8 4588
Kojto 90:cb3d968589d8 4589 /*!
Kojto 90:cb3d968589d8 4590 * @}
Kojto 90:cb3d968589d8 4591 */ /* end of group LPUART_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4592
Kojto 90:cb3d968589d8 4593
Kojto 90:cb3d968589d8 4594 /*!
Kojto 90:cb3d968589d8 4595 * @}
Kojto 90:cb3d968589d8 4596 */ /* end of group LPUART_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 4597
Kojto 90:cb3d968589d8 4598
Kojto 90:cb3d968589d8 4599 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4600 -- MCG Peripheral Access Layer
Kojto 90:cb3d968589d8 4601 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4602
Kojto 90:cb3d968589d8 4603 /*!
Kojto 90:cb3d968589d8 4604 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
Kojto 90:cb3d968589d8 4605 * @{
Kojto 90:cb3d968589d8 4606 */
Kojto 90:cb3d968589d8 4607
Kojto 90:cb3d968589d8 4608 /** MCG - Register Layout Typedef */
Kojto 90:cb3d968589d8 4609 typedef struct {
Kojto 90:cb3d968589d8 4610 __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */
Kojto 90:cb3d968589d8 4611 __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */
Kojto 90:cb3d968589d8 4612 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 4613 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
Kojto 90:cb3d968589d8 4614 uint8_t RESERVED_1[1];
Kojto 90:cb3d968589d8 4615 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
Kojto 90:cb3d968589d8 4616 uint8_t RESERVED_2[11];
Kojto 90:cb3d968589d8 4617 __I uint8_t HCTRIM; /**< MCG High-frequency IRC Coarse Trim Register, offset: 0x14 */
Kojto 90:cb3d968589d8 4618 __I uint8_t HTTRIM; /**< MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register, offset: 0x15 */
Kojto 90:cb3d968589d8 4619 __I uint8_t HFTRIM; /**< MCG High-frequency IRC Fine Trim Register, offset: 0x16 */
Kojto 90:cb3d968589d8 4620 uint8_t RESERVED_3[1];
Kojto 90:cb3d968589d8 4621 __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */
Kojto 90:cb3d968589d8 4622 __I uint8_t LTRIMRNG; /**< MCG Low-frequency IRC Trim Range Register, offset: 0x19 */
Kojto 90:cb3d968589d8 4623 __I uint8_t LFTRIM; /**< MCG Low-frequency IRC8M Trim Register, offset: 0x1A */
Kojto 90:cb3d968589d8 4624 __I uint8_t LSTRIM; /**< MCG Low-frequency IRC2M Trim Register, offset: 0x1B */
Kojto 90:cb3d968589d8 4625 } MCG_Type, *MCG_MemMapPtr;
Kojto 90:cb3d968589d8 4626
Kojto 90:cb3d968589d8 4627 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4628 -- MCG - Register accessor macros
Kojto 90:cb3d968589d8 4629 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4630
Kojto 90:cb3d968589d8 4631 /*!
Kojto 90:cb3d968589d8 4632 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
Kojto 90:cb3d968589d8 4633 * @{
Kojto 90:cb3d968589d8 4634 */
Kojto 90:cb3d968589d8 4635
Kojto 90:cb3d968589d8 4636
Kojto 90:cb3d968589d8 4637 /* MCG - Register accessors */
Kojto 90:cb3d968589d8 4638 #define MCG_C1_REG(base) ((base)->C1)
Kojto 90:cb3d968589d8 4639 #define MCG_C2_REG(base) ((base)->C2)
Kojto 90:cb3d968589d8 4640 #define MCG_S_REG(base) ((base)->S)
Kojto 90:cb3d968589d8 4641 #define MCG_SC_REG(base) ((base)->SC)
Kojto 90:cb3d968589d8 4642 #define MCG_HCTRIM_REG(base) ((base)->HCTRIM)
Kojto 90:cb3d968589d8 4643 #define MCG_HTTRIM_REG(base) ((base)->HTTRIM)
Kojto 90:cb3d968589d8 4644 #define MCG_HFTRIM_REG(base) ((base)->HFTRIM)
Kojto 90:cb3d968589d8 4645 #define MCG_MC_REG(base) ((base)->MC)
Kojto 90:cb3d968589d8 4646 #define MCG_LTRIMRNG_REG(base) ((base)->LTRIMRNG)
Kojto 90:cb3d968589d8 4647 #define MCG_LFTRIM_REG(base) ((base)->LFTRIM)
Kojto 90:cb3d968589d8 4648 #define MCG_LSTRIM_REG(base) ((base)->LSTRIM)
Kojto 90:cb3d968589d8 4649
Kojto 90:cb3d968589d8 4650 /*!
Kojto 90:cb3d968589d8 4651 * @}
Kojto 90:cb3d968589d8 4652 */ /* end of group MCG_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4653
Kojto 90:cb3d968589d8 4654
Kojto 90:cb3d968589d8 4655 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4656 -- MCG Register Masks
Kojto 90:cb3d968589d8 4657 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4658
Kojto 90:cb3d968589d8 4659 /*!
Kojto 90:cb3d968589d8 4660 * @addtogroup MCG_Register_Masks MCG Register Masks
Kojto 90:cb3d968589d8 4661 * @{
Kojto 90:cb3d968589d8 4662 */
Kojto 90:cb3d968589d8 4663
Kojto 90:cb3d968589d8 4664 /* C1 Bit Fields */
Kojto 90:cb3d968589d8 4665 #define MCG_C1_IREFSTEN_MASK 0x1u
Kojto 90:cb3d968589d8 4666 #define MCG_C1_IREFSTEN_SHIFT 0
Kojto 90:cb3d968589d8 4667 #define MCG_C1_IRCLKEN_MASK 0x2u
Kojto 90:cb3d968589d8 4668 #define MCG_C1_IRCLKEN_SHIFT 1
Kojto 90:cb3d968589d8 4669 #define MCG_C1_CLKS_MASK 0xC0u
Kojto 90:cb3d968589d8 4670 #define MCG_C1_CLKS_SHIFT 6
Kojto 90:cb3d968589d8 4671 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
Kojto 90:cb3d968589d8 4672 /* C2 Bit Fields */
Kojto 90:cb3d968589d8 4673 #define MCG_C2_IRCS_MASK 0x1u
Kojto 90:cb3d968589d8 4674 #define MCG_C2_IRCS_SHIFT 0
Kojto 90:cb3d968589d8 4675 #define MCG_C2_EREFS0_MASK 0x4u
Kojto 90:cb3d968589d8 4676 #define MCG_C2_EREFS0_SHIFT 2
Kojto 90:cb3d968589d8 4677 #define MCG_C2_HGO0_MASK 0x8u
Kojto 90:cb3d968589d8 4678 #define MCG_C2_HGO0_SHIFT 3
Kojto 90:cb3d968589d8 4679 #define MCG_C2_RANGE0_MASK 0x30u
Kojto 90:cb3d968589d8 4680 #define MCG_C2_RANGE0_SHIFT 4
Kojto 90:cb3d968589d8 4681 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
Kojto 90:cb3d968589d8 4682 /* S Bit Fields */
Kojto 90:cb3d968589d8 4683 #define MCG_S_OSCINIT0_MASK 0x2u
Kojto 90:cb3d968589d8 4684 #define MCG_S_OSCINIT0_SHIFT 1
Kojto 90:cb3d968589d8 4685 #define MCG_S_CLKST_MASK 0xCu
Kojto 90:cb3d968589d8 4686 #define MCG_S_CLKST_SHIFT 2
Kojto 90:cb3d968589d8 4687 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
Kojto 90:cb3d968589d8 4688 /* SC Bit Fields */
Kojto 90:cb3d968589d8 4689 #define MCG_SC_FCRDIV_MASK 0xEu
Kojto 90:cb3d968589d8 4690 #define MCG_SC_FCRDIV_SHIFT 1
Kojto 90:cb3d968589d8 4691 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
Kojto 90:cb3d968589d8 4692 /* HCTRIM Bit Fields */
Kojto 90:cb3d968589d8 4693 #define MCG_HCTRIM_COARSE_TRIM_MASK 0x3Fu
Kojto 90:cb3d968589d8 4694 #define MCG_HCTRIM_COARSE_TRIM_SHIFT 0
Kojto 90:cb3d968589d8 4695 #define MCG_HCTRIM_COARSE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HCTRIM_COARSE_TRIM_SHIFT))&MCG_HCTRIM_COARSE_TRIM_MASK)
Kojto 90:cb3d968589d8 4696 /* HTTRIM Bit Fields */
Kojto 90:cb3d968589d8 4697 #define MCG_HTTRIM_TEMPCO_TRIM_MASK 0x1Fu
Kojto 90:cb3d968589d8 4698 #define MCG_HTTRIM_TEMPCO_TRIM_SHIFT 0
Kojto 90:cb3d968589d8 4699 #define MCG_HTTRIM_TEMPCO_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HTTRIM_TEMPCO_TRIM_SHIFT))&MCG_HTTRIM_TEMPCO_TRIM_MASK)
Kojto 90:cb3d968589d8 4700 /* HFTRIM Bit Fields */
Kojto 90:cb3d968589d8 4701 #define MCG_HFTRIM_FINE_TRIM_MASK 0x7Fu
Kojto 90:cb3d968589d8 4702 #define MCG_HFTRIM_FINE_TRIM_SHIFT 0
Kojto 90:cb3d968589d8 4703 #define MCG_HFTRIM_FINE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HFTRIM_FINE_TRIM_SHIFT))&MCG_HFTRIM_FINE_TRIM_MASK)
Kojto 90:cb3d968589d8 4704 /* MC Bit Fields */
Kojto 90:cb3d968589d8 4705 #define MCG_MC_LIRC_DIV2_MASK 0x7u
Kojto 90:cb3d968589d8 4706 #define MCG_MC_LIRC_DIV2_SHIFT 0
Kojto 90:cb3d968589d8 4707 #define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x))<<MCG_MC_LIRC_DIV2_SHIFT))&MCG_MC_LIRC_DIV2_MASK)
Kojto 90:cb3d968589d8 4708 #define MCG_MC_HIRCEN_MASK 0x80u
Kojto 90:cb3d968589d8 4709 #define MCG_MC_HIRCEN_SHIFT 7
Kojto 90:cb3d968589d8 4710 /* LTRIMRNG Bit Fields */
Kojto 90:cb3d968589d8 4711 #define MCG_LTRIMRNG_STRIMRNG_MASK 0x3u
Kojto 90:cb3d968589d8 4712 #define MCG_LTRIMRNG_STRIMRNG_SHIFT 0
Kojto 90:cb3d968589d8 4713 #define MCG_LTRIMRNG_STRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_STRIMRNG_SHIFT))&MCG_LTRIMRNG_STRIMRNG_MASK)
Kojto 90:cb3d968589d8 4714 #define MCG_LTRIMRNG_FTRIMRNG_MASK 0xCu
Kojto 90:cb3d968589d8 4715 #define MCG_LTRIMRNG_FTRIMRNG_SHIFT 2
Kojto 90:cb3d968589d8 4716 #define MCG_LTRIMRNG_FTRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_FTRIMRNG_SHIFT))&MCG_LTRIMRNG_FTRIMRNG_MASK)
Kojto 90:cb3d968589d8 4717 /* LFTRIM Bit Fields */
Kojto 90:cb3d968589d8 4718 #define MCG_LFTRIM_LIRC_FTRIM_MASK 0x7Fu
Kojto 90:cb3d968589d8 4719 #define MCG_LFTRIM_LIRC_FTRIM_SHIFT 0
Kojto 90:cb3d968589d8 4720 #define MCG_LFTRIM_LIRC_FTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LFTRIM_LIRC_FTRIM_SHIFT))&MCG_LFTRIM_LIRC_FTRIM_MASK)
Kojto 90:cb3d968589d8 4721 /* LSTRIM Bit Fields */
Kojto 90:cb3d968589d8 4722 #define MCG_LSTRIM_LIRC_STRIM_MASK 0x7Fu
Kojto 90:cb3d968589d8 4723 #define MCG_LSTRIM_LIRC_STRIM_SHIFT 0
Kojto 90:cb3d968589d8 4724 #define MCG_LSTRIM_LIRC_STRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LSTRIM_LIRC_STRIM_SHIFT))&MCG_LSTRIM_LIRC_STRIM_MASK)
Kojto 90:cb3d968589d8 4725
Kojto 90:cb3d968589d8 4726 /*!
Kojto 90:cb3d968589d8 4727 * @}
Kojto 90:cb3d968589d8 4728 */ /* end of group MCG_Register_Masks */
Kojto 90:cb3d968589d8 4729
Kojto 90:cb3d968589d8 4730
Kojto 90:cb3d968589d8 4731 /* MCG - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 4732 /** Peripheral MCG base address */
Kojto 90:cb3d968589d8 4733 #define MCG_BASE (0x40064000u)
Kojto 90:cb3d968589d8 4734 /** Peripheral MCG base pointer */
Kojto 90:cb3d968589d8 4735 #define MCG ((MCG_Type *)MCG_BASE)
Kojto 90:cb3d968589d8 4736 #define MCG_BASE_PTR (MCG)
Kojto 90:cb3d968589d8 4737 /** Array initializer of MCG peripheral base addresses */
Kojto 90:cb3d968589d8 4738 #define MCG_BASE_ADDRS { MCG_BASE }
Kojto 90:cb3d968589d8 4739 /** Array initializer of MCG peripheral base pointers */
Kojto 90:cb3d968589d8 4740 #define MCG_BASE_PTRS { MCG }
Kojto 90:cb3d968589d8 4741
Kojto 90:cb3d968589d8 4742 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4743 -- MCG - Register accessor macros
Kojto 90:cb3d968589d8 4744 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4745
Kojto 90:cb3d968589d8 4746 /*!
Kojto 90:cb3d968589d8 4747 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
Kojto 90:cb3d968589d8 4748 * @{
Kojto 90:cb3d968589d8 4749 */
Kojto 90:cb3d968589d8 4750
Kojto 90:cb3d968589d8 4751
Kojto 90:cb3d968589d8 4752 /* MCG - Register instance definitions */
Kojto 90:cb3d968589d8 4753 /* MCG */
Kojto 90:cb3d968589d8 4754 #define MCG_C1 MCG_C1_REG(MCG)
Kojto 90:cb3d968589d8 4755 #define MCG_C2 MCG_C2_REG(MCG)
Kojto 90:cb3d968589d8 4756 #define MCG_S MCG_S_REG(MCG)
Kojto 90:cb3d968589d8 4757 #define MCG_SC MCG_SC_REG(MCG)
Kojto 90:cb3d968589d8 4758 #define MCG_HCTRIM MCG_HCTRIM_REG(MCG)
Kojto 90:cb3d968589d8 4759 #define MCG_HTTRIM MCG_HTTRIM_REG(MCG)
Kojto 90:cb3d968589d8 4760 #define MCG_HFTRIM MCG_HFTRIM_REG(MCG)
Kojto 90:cb3d968589d8 4761 #define MCG_MC MCG_MC_REG(MCG)
Kojto 90:cb3d968589d8 4762 #define MCG_LTRIMRNG MCG_LTRIMRNG_REG(MCG)
Kojto 90:cb3d968589d8 4763 #define MCG_LFTRIM MCG_LFTRIM_REG(MCG)
Kojto 90:cb3d968589d8 4764 #define MCG_LSTRIM MCG_LSTRIM_REG(MCG)
Kojto 90:cb3d968589d8 4765
Kojto 90:cb3d968589d8 4766 /*!
Kojto 90:cb3d968589d8 4767 * @}
Kojto 90:cb3d968589d8 4768 */ /* end of group MCG_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4769
Kojto 90:cb3d968589d8 4770
Kojto 90:cb3d968589d8 4771 /*!
Kojto 90:cb3d968589d8 4772 * @}
Kojto 90:cb3d968589d8 4773 */ /* end of group MCG_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 4774
Kojto 90:cb3d968589d8 4775
Kojto 90:cb3d968589d8 4776 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4777 -- MCM Peripheral Access Layer
Kojto 90:cb3d968589d8 4778 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4779
Kojto 90:cb3d968589d8 4780 /*!
Kojto 90:cb3d968589d8 4781 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
Kojto 90:cb3d968589d8 4782 * @{
Kojto 90:cb3d968589d8 4783 */
Kojto 90:cb3d968589d8 4784
Kojto 90:cb3d968589d8 4785 /** MCM - Register Layout Typedef */
Kojto 90:cb3d968589d8 4786 typedef struct {
Kojto 90:cb3d968589d8 4787 uint8_t RESERVED_0[8];
Kojto 90:cb3d968589d8 4788 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
Kojto 90:cb3d968589d8 4789 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
Kojto 90:cb3d968589d8 4790 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
Kojto 90:cb3d968589d8 4791 uint8_t RESERVED_1[48];
Kojto 90:cb3d968589d8 4792 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
Kojto 90:cb3d968589d8 4793 } MCM_Type, *MCM_MemMapPtr;
Kojto 90:cb3d968589d8 4794
Kojto 90:cb3d968589d8 4795 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4796 -- MCM - Register accessor macros
Kojto 90:cb3d968589d8 4797 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4798
Kojto 90:cb3d968589d8 4799 /*!
Kojto 90:cb3d968589d8 4800 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
Kojto 90:cb3d968589d8 4801 * @{
Kojto 90:cb3d968589d8 4802 */
Kojto 90:cb3d968589d8 4803
Kojto 90:cb3d968589d8 4804
Kojto 90:cb3d968589d8 4805 /* MCM - Register accessors */
Kojto 90:cb3d968589d8 4806 #define MCM_PLASC_REG(base) ((base)->PLASC)
Kojto 90:cb3d968589d8 4807 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
Kojto 90:cb3d968589d8 4808 #define MCM_PLACR_REG(base) ((base)->PLACR)
Kojto 90:cb3d968589d8 4809 #define MCM_CPO_REG(base) ((base)->CPO)
Kojto 90:cb3d968589d8 4810
Kojto 90:cb3d968589d8 4811 /*!
Kojto 90:cb3d968589d8 4812 * @}
Kojto 90:cb3d968589d8 4813 */ /* end of group MCM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4814
Kojto 90:cb3d968589d8 4815
Kojto 90:cb3d968589d8 4816 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4817 -- MCM Register Masks
Kojto 90:cb3d968589d8 4818 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4819
Kojto 90:cb3d968589d8 4820 /*!
Kojto 90:cb3d968589d8 4821 * @addtogroup MCM_Register_Masks MCM Register Masks
Kojto 90:cb3d968589d8 4822 * @{
Kojto 90:cb3d968589d8 4823 */
Kojto 90:cb3d968589d8 4824
Kojto 90:cb3d968589d8 4825 /* PLASC Bit Fields */
Kojto 90:cb3d968589d8 4826 #define MCM_PLASC_ASC_MASK 0xFFu
Kojto 90:cb3d968589d8 4827 #define MCM_PLASC_ASC_SHIFT 0
Kojto 90:cb3d968589d8 4828 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
Kojto 90:cb3d968589d8 4829 /* PLAMC Bit Fields */
Kojto 90:cb3d968589d8 4830 #define MCM_PLAMC_AMC_MASK 0xFFu
Kojto 90:cb3d968589d8 4831 #define MCM_PLAMC_AMC_SHIFT 0
Kojto 90:cb3d968589d8 4832 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
Kojto 90:cb3d968589d8 4833 /* PLACR Bit Fields */
Kojto 90:cb3d968589d8 4834 #define MCM_PLACR_ARB_MASK 0x200u
Kojto 90:cb3d968589d8 4835 #define MCM_PLACR_ARB_SHIFT 9
Kojto 90:cb3d968589d8 4836 #define MCM_PLACR_CFCC_MASK 0x400u
Kojto 90:cb3d968589d8 4837 #define MCM_PLACR_CFCC_SHIFT 10
Kojto 90:cb3d968589d8 4838 #define MCM_PLACR_DFCDA_MASK 0x800u
Kojto 90:cb3d968589d8 4839 #define MCM_PLACR_DFCDA_SHIFT 11
Kojto 90:cb3d968589d8 4840 #define MCM_PLACR_DFCIC_MASK 0x1000u
Kojto 90:cb3d968589d8 4841 #define MCM_PLACR_DFCIC_SHIFT 12
Kojto 90:cb3d968589d8 4842 #define MCM_PLACR_DFCC_MASK 0x2000u
Kojto 90:cb3d968589d8 4843 #define MCM_PLACR_DFCC_SHIFT 13
Kojto 90:cb3d968589d8 4844 #define MCM_PLACR_EFDS_MASK 0x4000u
Kojto 90:cb3d968589d8 4845 #define MCM_PLACR_EFDS_SHIFT 14
Kojto 90:cb3d968589d8 4846 #define MCM_PLACR_DFCS_MASK 0x8000u
Kojto 90:cb3d968589d8 4847 #define MCM_PLACR_DFCS_SHIFT 15
Kojto 90:cb3d968589d8 4848 #define MCM_PLACR_ESFC_MASK 0x10000u
Kojto 90:cb3d968589d8 4849 #define MCM_PLACR_ESFC_SHIFT 16
Kojto 90:cb3d968589d8 4850 /* CPO Bit Fields */
Kojto 90:cb3d968589d8 4851 #define MCM_CPO_CPOREQ_MASK 0x1u
Kojto 90:cb3d968589d8 4852 #define MCM_CPO_CPOREQ_SHIFT 0
Kojto 90:cb3d968589d8 4853 #define MCM_CPO_CPOACK_MASK 0x2u
Kojto 90:cb3d968589d8 4854 #define MCM_CPO_CPOACK_SHIFT 1
Kojto 90:cb3d968589d8 4855 #define MCM_CPO_CPOWOI_MASK 0x4u
Kojto 90:cb3d968589d8 4856 #define MCM_CPO_CPOWOI_SHIFT 2
Kojto 90:cb3d968589d8 4857
Kojto 90:cb3d968589d8 4858 /*!
Kojto 90:cb3d968589d8 4859 * @}
Kojto 90:cb3d968589d8 4860 */ /* end of group MCM_Register_Masks */
Kojto 90:cb3d968589d8 4861
Kojto 90:cb3d968589d8 4862
Kojto 90:cb3d968589d8 4863 /* MCM - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 4864 /** Peripheral MCM base address */
Kojto 90:cb3d968589d8 4865 #define MCM_BASE (0xF0003000u)
Kojto 90:cb3d968589d8 4866 /** Peripheral MCM base pointer */
Kojto 90:cb3d968589d8 4867 #define MCM ((MCM_Type *)MCM_BASE)
Kojto 90:cb3d968589d8 4868 #define MCM_BASE_PTR (MCM)
Kojto 90:cb3d968589d8 4869 /** Array initializer of MCM peripheral base addresses */
Kojto 90:cb3d968589d8 4870 #define MCM_BASE_ADDRS { MCM_BASE }
Kojto 90:cb3d968589d8 4871 /** Array initializer of MCM peripheral base pointers */
Kojto 90:cb3d968589d8 4872 #define MCM_BASE_PTRS { MCM }
Kojto 90:cb3d968589d8 4873
Kojto 90:cb3d968589d8 4874 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4875 -- MCM - Register accessor macros
Kojto 90:cb3d968589d8 4876 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4877
Kojto 90:cb3d968589d8 4878 /*!
Kojto 90:cb3d968589d8 4879 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
Kojto 90:cb3d968589d8 4880 * @{
Kojto 90:cb3d968589d8 4881 */
Kojto 90:cb3d968589d8 4882
Kojto 90:cb3d968589d8 4883
Kojto 90:cb3d968589d8 4884 /* MCM - Register instance definitions */
Kojto 90:cb3d968589d8 4885 /* MCM */
Kojto 90:cb3d968589d8 4886 #define MCM_PLASC MCM_PLASC_REG(MCM)
Kojto 90:cb3d968589d8 4887 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
Kojto 90:cb3d968589d8 4888 #define MCM_PLACR MCM_PLACR_REG(MCM)
Kojto 90:cb3d968589d8 4889 #define MCM_CPO MCM_CPO_REG(MCM)
Kojto 90:cb3d968589d8 4890
Kojto 90:cb3d968589d8 4891 /*!
Kojto 90:cb3d968589d8 4892 * @}
Kojto 90:cb3d968589d8 4893 */ /* end of group MCM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4894
Kojto 90:cb3d968589d8 4895
Kojto 90:cb3d968589d8 4896 /*!
Kojto 90:cb3d968589d8 4897 * @}
Kojto 90:cb3d968589d8 4898 */ /* end of group MCM_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 4899
Kojto 90:cb3d968589d8 4900
Kojto 90:cb3d968589d8 4901 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4902 -- MTB Peripheral Access Layer
Kojto 90:cb3d968589d8 4903 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4904
Kojto 90:cb3d968589d8 4905 /*!
Kojto 90:cb3d968589d8 4906 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
Kojto 90:cb3d968589d8 4907 * @{
Kojto 90:cb3d968589d8 4908 */
Kojto 90:cb3d968589d8 4909
Kojto 90:cb3d968589d8 4910 /** MTB - Register Layout Typedef */
Kojto 90:cb3d968589d8 4911 typedef struct {
Kojto 90:cb3d968589d8 4912 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
Kojto 90:cb3d968589d8 4913 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
Kojto 90:cb3d968589d8 4914 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
Kojto 90:cb3d968589d8 4915 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
Kojto 90:cb3d968589d8 4916 uint8_t RESERVED_0[3824];
Kojto 90:cb3d968589d8 4917 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
Kojto 90:cb3d968589d8 4918 uint8_t RESERVED_1[156];
Kojto 90:cb3d968589d8 4919 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
Kojto 90:cb3d968589d8 4920 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
Kojto 90:cb3d968589d8 4921 uint8_t RESERVED_2[8];
Kojto 90:cb3d968589d8 4922 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
Kojto 90:cb3d968589d8 4923 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
Kojto 90:cb3d968589d8 4924 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
Kojto 90:cb3d968589d8 4925 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
Kojto 90:cb3d968589d8 4926 uint8_t RESERVED_3[8];
Kojto 90:cb3d968589d8 4927 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
Kojto 90:cb3d968589d8 4928 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
Kojto 90:cb3d968589d8 4929 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
Kojto 90:cb3d968589d8 4930 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
Kojto 90:cb3d968589d8 4931 } MTB_Type, *MTB_MemMapPtr;
Kojto 90:cb3d968589d8 4932
Kojto 90:cb3d968589d8 4933 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4934 -- MTB - Register accessor macros
Kojto 90:cb3d968589d8 4935 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4936
Kojto 90:cb3d968589d8 4937 /*!
Kojto 90:cb3d968589d8 4938 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
Kojto 90:cb3d968589d8 4939 * @{
Kojto 90:cb3d968589d8 4940 */
Kojto 90:cb3d968589d8 4941
Kojto 90:cb3d968589d8 4942
Kojto 90:cb3d968589d8 4943 /* MTB - Register accessors */
Kojto 90:cb3d968589d8 4944 #define MTB_POSITION_REG(base) ((base)->POSITION)
Kojto 90:cb3d968589d8 4945 #define MTB_MASTER_REG(base) ((base)->MASTER)
Kojto 90:cb3d968589d8 4946 #define MTB_FLOW_REG(base) ((base)->FLOW)
Kojto 90:cb3d968589d8 4947 #define MTB_BASE_REG(base) ((base)->BASE)
Kojto 90:cb3d968589d8 4948 #define MTB_MODECTRL_REG(base) ((base)->MODECTRL)
Kojto 90:cb3d968589d8 4949 #define MTB_TAGSET_REG(base) ((base)->TAGSET)
Kojto 90:cb3d968589d8 4950 #define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR)
Kojto 90:cb3d968589d8 4951 #define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS)
Kojto 90:cb3d968589d8 4952 #define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT)
Kojto 90:cb3d968589d8 4953 #define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT)
Kojto 90:cb3d968589d8 4954 #define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH)
Kojto 90:cb3d968589d8 4955 #define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG)
Kojto 90:cb3d968589d8 4956 #define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
Kojto 90:cb3d968589d8 4957 #define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
Kojto 90:cb3d968589d8 4958 #define MTB_COMPID_REG(base,index) ((base)->COMPID[index])
Kojto 90:cb3d968589d8 4959
Kojto 90:cb3d968589d8 4960 /*!
Kojto 90:cb3d968589d8 4961 * @}
Kojto 90:cb3d968589d8 4962 */ /* end of group MTB_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 4963
Kojto 90:cb3d968589d8 4964
Kojto 90:cb3d968589d8 4965 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 4966 -- MTB Register Masks
Kojto 90:cb3d968589d8 4967 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 4968
Kojto 90:cb3d968589d8 4969 /*!
Kojto 90:cb3d968589d8 4970 * @addtogroup MTB_Register_Masks MTB Register Masks
Kojto 90:cb3d968589d8 4971 * @{
Kojto 90:cb3d968589d8 4972 */
Kojto 90:cb3d968589d8 4973
Kojto 90:cb3d968589d8 4974 /* POSITION Bit Fields */
Kojto 90:cb3d968589d8 4975 #define MTB_POSITION_WRAP_MASK 0x4u
Kojto 90:cb3d968589d8 4976 #define MTB_POSITION_WRAP_SHIFT 2
Kojto 90:cb3d968589d8 4977 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
Kojto 90:cb3d968589d8 4978 #define MTB_POSITION_POINTER_SHIFT 3
Kojto 90:cb3d968589d8 4979 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
Kojto 90:cb3d968589d8 4980 /* MASTER Bit Fields */
Kojto 90:cb3d968589d8 4981 #define MTB_MASTER_MASK_MASK 0x1Fu
Kojto 90:cb3d968589d8 4982 #define MTB_MASTER_MASK_SHIFT 0
Kojto 90:cb3d968589d8 4983 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
Kojto 90:cb3d968589d8 4984 #define MTB_MASTER_TSTARTEN_MASK 0x20u
Kojto 90:cb3d968589d8 4985 #define MTB_MASTER_TSTARTEN_SHIFT 5
Kojto 90:cb3d968589d8 4986 #define MTB_MASTER_TSTOPEN_MASK 0x40u
Kojto 90:cb3d968589d8 4987 #define MTB_MASTER_TSTOPEN_SHIFT 6
Kojto 90:cb3d968589d8 4988 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
Kojto 90:cb3d968589d8 4989 #define MTB_MASTER_SFRWPRIV_SHIFT 7
Kojto 90:cb3d968589d8 4990 #define MTB_MASTER_RAMPRIV_MASK 0x100u
Kojto 90:cb3d968589d8 4991 #define MTB_MASTER_RAMPRIV_SHIFT 8
Kojto 90:cb3d968589d8 4992 #define MTB_MASTER_HALTREQ_MASK 0x200u
Kojto 90:cb3d968589d8 4993 #define MTB_MASTER_HALTREQ_SHIFT 9
Kojto 90:cb3d968589d8 4994 #define MTB_MASTER_EN_MASK 0x80000000u
Kojto 90:cb3d968589d8 4995 #define MTB_MASTER_EN_SHIFT 31
Kojto 90:cb3d968589d8 4996 /* FLOW Bit Fields */
Kojto 90:cb3d968589d8 4997 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
Kojto 90:cb3d968589d8 4998 #define MTB_FLOW_AUTOSTOP_SHIFT 0
Kojto 90:cb3d968589d8 4999 #define MTB_FLOW_AUTOHALT_MASK 0x2u
Kojto 90:cb3d968589d8 5000 #define MTB_FLOW_AUTOHALT_SHIFT 1
Kojto 90:cb3d968589d8 5001 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
Kojto 90:cb3d968589d8 5002 #define MTB_FLOW_WATERMARK_SHIFT 3
Kojto 90:cb3d968589d8 5003 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
Kojto 90:cb3d968589d8 5004 /* BASE Bit Fields */
Kojto 90:cb3d968589d8 5005 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5006 #define MTB_BASE_BASEADDR_SHIFT 0
Kojto 90:cb3d968589d8 5007 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
Kojto 90:cb3d968589d8 5008 /* MODECTRL Bit Fields */
Kojto 90:cb3d968589d8 5009 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5010 #define MTB_MODECTRL_MODECTRL_SHIFT 0
Kojto 90:cb3d968589d8 5011 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
Kojto 90:cb3d968589d8 5012 /* TAGSET Bit Fields */
Kojto 90:cb3d968589d8 5013 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5014 #define MTB_TAGSET_TAGSET_SHIFT 0
Kojto 90:cb3d968589d8 5015 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
Kojto 90:cb3d968589d8 5016 /* TAGCLEAR Bit Fields */
Kojto 90:cb3d968589d8 5017 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5018 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
Kojto 90:cb3d968589d8 5019 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
Kojto 90:cb3d968589d8 5020 /* LOCKACCESS Bit Fields */
Kojto 90:cb3d968589d8 5021 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5022 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
Kojto 90:cb3d968589d8 5023 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
Kojto 90:cb3d968589d8 5024 /* LOCKSTAT Bit Fields */
Kojto 90:cb3d968589d8 5025 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5026 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
Kojto 90:cb3d968589d8 5027 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
Kojto 90:cb3d968589d8 5028 /* AUTHSTAT Bit Fields */
Kojto 90:cb3d968589d8 5029 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
Kojto 90:cb3d968589d8 5030 #define MTB_AUTHSTAT_BIT0_SHIFT 0
Kojto 90:cb3d968589d8 5031 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
Kojto 90:cb3d968589d8 5032 #define MTB_AUTHSTAT_BIT1_SHIFT 1
Kojto 90:cb3d968589d8 5033 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
Kojto 90:cb3d968589d8 5034 #define MTB_AUTHSTAT_BIT2_SHIFT 2
Kojto 90:cb3d968589d8 5035 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
Kojto 90:cb3d968589d8 5036 #define MTB_AUTHSTAT_BIT3_SHIFT 3
Kojto 90:cb3d968589d8 5037 /* DEVICEARCH Bit Fields */
Kojto 90:cb3d968589d8 5038 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5039 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
Kojto 90:cb3d968589d8 5040 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
Kojto 90:cb3d968589d8 5041 /* DEVICECFG Bit Fields */
Kojto 90:cb3d968589d8 5042 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5043 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
Kojto 90:cb3d968589d8 5044 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
Kojto 90:cb3d968589d8 5045 /* DEVICETYPID Bit Fields */
Kojto 90:cb3d968589d8 5046 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5047 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
Kojto 90:cb3d968589d8 5048 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
Kojto 90:cb3d968589d8 5049 /* PERIPHID Bit Fields */
Kojto 90:cb3d968589d8 5050 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5051 #define MTB_PERIPHID_PERIPHID_SHIFT 0
Kojto 90:cb3d968589d8 5052 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
Kojto 90:cb3d968589d8 5053 /* COMPID Bit Fields */
Kojto 90:cb3d968589d8 5054 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5055 #define MTB_COMPID_COMPID_SHIFT 0
Kojto 90:cb3d968589d8 5056 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
Kojto 90:cb3d968589d8 5057
Kojto 90:cb3d968589d8 5058 /*!
Kojto 90:cb3d968589d8 5059 * @}
Kojto 90:cb3d968589d8 5060 */ /* end of group MTB_Register_Masks */
Kojto 90:cb3d968589d8 5061
Kojto 90:cb3d968589d8 5062
Kojto 90:cb3d968589d8 5063 /* MTB - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 5064 /** Peripheral MTB base address */
Kojto 90:cb3d968589d8 5065 #define MTB_BASE (0xF0000000u)
Kojto 90:cb3d968589d8 5066 /** Peripheral MTB base pointer */
Kojto 90:cb3d968589d8 5067 #define MTB ((MTB_Type *)MTB_BASE)
Kojto 90:cb3d968589d8 5068 #define MTB_BASE_PTR (MTB)
Kojto 90:cb3d968589d8 5069 /** Array initializer of MTB peripheral base addresses */
Kojto 90:cb3d968589d8 5070 #define MTB_BASE_ADDRS { MTB_BASE }
Kojto 90:cb3d968589d8 5071 /** Array initializer of MTB peripheral base pointers */
Kojto 90:cb3d968589d8 5072 #define MTB_BASE_PTRS { MTB }
Kojto 90:cb3d968589d8 5073
Kojto 90:cb3d968589d8 5074 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5075 -- MTB - Register accessor macros
Kojto 90:cb3d968589d8 5076 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5077
Kojto 90:cb3d968589d8 5078 /*!
Kojto 90:cb3d968589d8 5079 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
Kojto 90:cb3d968589d8 5080 * @{
Kojto 90:cb3d968589d8 5081 */
Kojto 90:cb3d968589d8 5082
Kojto 90:cb3d968589d8 5083
Kojto 90:cb3d968589d8 5084 /* MTB - Register instance definitions */
Kojto 90:cb3d968589d8 5085 /* MTB */
Kojto 90:cb3d968589d8 5086 #define MTB_POSITION MTB_POSITION_REG(MTB)
Kojto 90:cb3d968589d8 5087 #define MTB_MASTER MTB_MASTER_REG(MTB)
Kojto 90:cb3d968589d8 5088 #define MTB_FLOW MTB_FLOW_REG(MTB)
Kojto 90:cb3d968589d8 5089 #define MTB_BASEr MTB_BASE_REG(MTB)
Kojto 90:cb3d968589d8 5090 #define MTB_MODECTRL MTB_MODECTRL_REG(MTB)
Kojto 90:cb3d968589d8 5091 #define MTB_TAGSET MTB_TAGSET_REG(MTB)
Kojto 90:cb3d968589d8 5092 #define MTB_TAGCLEAR MTB_TAGCLEAR_REG(MTB)
Kojto 90:cb3d968589d8 5093 #define MTB_LOCKACCESS MTB_LOCKACCESS_REG(MTB)
Kojto 90:cb3d968589d8 5094 #define MTB_LOCKSTAT MTB_LOCKSTAT_REG(MTB)
Kojto 90:cb3d968589d8 5095 #define MTB_AUTHSTAT MTB_AUTHSTAT_REG(MTB)
Kojto 90:cb3d968589d8 5096 #define MTB_DEVICEARCH MTB_DEVICEARCH_REG(MTB)
Kojto 90:cb3d968589d8 5097 #define MTB_DEVICECFG MTB_DEVICECFG_REG(MTB)
Kojto 90:cb3d968589d8 5098 #define MTB_DEVICETYPID MTB_DEVICETYPID_REG(MTB)
Kojto 90:cb3d968589d8 5099 #define MTB_PERIPHID4 MTB_PERIPHID_REG(MTB,0)
Kojto 90:cb3d968589d8 5100 #define MTB_PERIPHID5 MTB_PERIPHID_REG(MTB,1)
Kojto 90:cb3d968589d8 5101 #define MTB_PERIPHID6 MTB_PERIPHID_REG(MTB,2)
Kojto 90:cb3d968589d8 5102 #define MTB_PERIPHID7 MTB_PERIPHID_REG(MTB,3)
Kojto 90:cb3d968589d8 5103 #define MTB_PERIPHID0 MTB_PERIPHID_REG(MTB,4)
Kojto 90:cb3d968589d8 5104 #define MTB_PERIPHID1 MTB_PERIPHID_REG(MTB,5)
Kojto 90:cb3d968589d8 5105 #define MTB_PERIPHID2 MTB_PERIPHID_REG(MTB,6)
Kojto 90:cb3d968589d8 5106 #define MTB_PERIPHID3 MTB_PERIPHID_REG(MTB,7)
Kojto 90:cb3d968589d8 5107 #define MTB_COMPID0 MTB_COMPID_REG(MTB,0)
Kojto 90:cb3d968589d8 5108 #define MTB_COMPID1 MTB_COMPID_REG(MTB,1)
Kojto 90:cb3d968589d8 5109 #define MTB_COMPID2 MTB_COMPID_REG(MTB,2)
Kojto 90:cb3d968589d8 5110 #define MTB_COMPID3 MTB_COMPID_REG(MTB,3)
Kojto 90:cb3d968589d8 5111
Kojto 90:cb3d968589d8 5112 /* MTB - Register array accessors */
Kojto 90:cb3d968589d8 5113 #define MTB_PERIPHID(index) MTB_PERIPHID_REG(MTB,index)
Kojto 90:cb3d968589d8 5114 #define MTB_COMPID(index) MTB_COMPID_REG(MTB,index)
Kojto 90:cb3d968589d8 5115
Kojto 90:cb3d968589d8 5116 /*!
Kojto 90:cb3d968589d8 5117 * @}
Kojto 90:cb3d968589d8 5118 */ /* end of group MTB_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5119
Kojto 90:cb3d968589d8 5120
Kojto 90:cb3d968589d8 5121 /*!
Kojto 90:cb3d968589d8 5122 * @}
Kojto 90:cb3d968589d8 5123 */ /* end of group MTB_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 5124
Kojto 90:cb3d968589d8 5125
Kojto 90:cb3d968589d8 5126 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5127 -- MTBDWT Peripheral Access Layer
Kojto 90:cb3d968589d8 5128 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5129
Kojto 90:cb3d968589d8 5130 /*!
Kojto 90:cb3d968589d8 5131 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
Kojto 90:cb3d968589d8 5132 * @{
Kojto 90:cb3d968589d8 5133 */
Kojto 90:cb3d968589d8 5134
Kojto 90:cb3d968589d8 5135 /** MTBDWT - Register Layout Typedef */
Kojto 90:cb3d968589d8 5136 typedef struct {
Kojto 90:cb3d968589d8 5137 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 5138 uint8_t RESERVED_0[28];
Kojto 90:cb3d968589d8 5139 struct { /* offset: 0x20, array step: 0x10 */
Kojto 90:cb3d968589d8 5140 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
Kojto 90:cb3d968589d8 5141 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
Kojto 90:cb3d968589d8 5142 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
Kojto 90:cb3d968589d8 5143 uint8_t RESERVED_0[4];
Kojto 90:cb3d968589d8 5144 } COMPARATOR[2];
Kojto 90:cb3d968589d8 5145 uint8_t RESERVED_1[448];
Kojto 90:cb3d968589d8 5146 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
Kojto 90:cb3d968589d8 5147 uint8_t RESERVED_2[3524];
Kojto 90:cb3d968589d8 5148 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
Kojto 90:cb3d968589d8 5149 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
Kojto 90:cb3d968589d8 5150 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
Kojto 90:cb3d968589d8 5151 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
Kojto 90:cb3d968589d8 5152 } MTBDWT_Type, *MTBDWT_MemMapPtr;
Kojto 90:cb3d968589d8 5153
Kojto 90:cb3d968589d8 5154 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5155 -- MTBDWT - Register accessor macros
Kojto 90:cb3d968589d8 5156 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5157
Kojto 90:cb3d968589d8 5158 /*!
Kojto 90:cb3d968589d8 5159 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
Kojto 90:cb3d968589d8 5160 * @{
Kojto 90:cb3d968589d8 5161 */
Kojto 90:cb3d968589d8 5162
Kojto 90:cb3d968589d8 5163
Kojto 90:cb3d968589d8 5164 /* MTBDWT - Register accessors */
Kojto 90:cb3d968589d8 5165 #define MTBDWT_CTRL_REG(base) ((base)->CTRL)
Kojto 90:cb3d968589d8 5166 #define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
Kojto 90:cb3d968589d8 5167 #define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
Kojto 90:cb3d968589d8 5168 #define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT)
Kojto 90:cb3d968589d8 5169 #define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL)
Kojto 90:cb3d968589d8 5170 #define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG)
Kojto 90:cb3d968589d8 5171 #define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
Kojto 90:cb3d968589d8 5172 #define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
Kojto 90:cb3d968589d8 5173 #define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index])
Kojto 90:cb3d968589d8 5174
Kojto 90:cb3d968589d8 5175 /*!
Kojto 90:cb3d968589d8 5176 * @}
Kojto 90:cb3d968589d8 5177 */ /* end of group MTBDWT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5178
Kojto 90:cb3d968589d8 5179
Kojto 90:cb3d968589d8 5180 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5181 -- MTBDWT Register Masks
Kojto 90:cb3d968589d8 5182 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5183
Kojto 90:cb3d968589d8 5184 /*!
Kojto 90:cb3d968589d8 5185 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
Kojto 90:cb3d968589d8 5186 * @{
Kojto 90:cb3d968589d8 5187 */
Kojto 90:cb3d968589d8 5188
Kojto 90:cb3d968589d8 5189 /* CTRL Bit Fields */
Kojto 90:cb3d968589d8 5190 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
Kojto 90:cb3d968589d8 5191 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
Kojto 90:cb3d968589d8 5192 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
Kojto 90:cb3d968589d8 5193 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
Kojto 90:cb3d968589d8 5194 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
Kojto 90:cb3d968589d8 5195 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
Kojto 90:cb3d968589d8 5196 /* COMP Bit Fields */
Kojto 90:cb3d968589d8 5197 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5198 #define MTBDWT_COMP_COMP_SHIFT 0
Kojto 90:cb3d968589d8 5199 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
Kojto 90:cb3d968589d8 5200 /* MASK Bit Fields */
Kojto 90:cb3d968589d8 5201 #define MTBDWT_MASK_MASK_MASK 0x1Fu
Kojto 90:cb3d968589d8 5202 #define MTBDWT_MASK_MASK_SHIFT 0
Kojto 90:cb3d968589d8 5203 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
Kojto 90:cb3d968589d8 5204 /* FCT Bit Fields */
Kojto 90:cb3d968589d8 5205 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
Kojto 90:cb3d968589d8 5206 #define MTBDWT_FCT_FUNCTION_SHIFT 0
Kojto 90:cb3d968589d8 5207 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
Kojto 90:cb3d968589d8 5208 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
Kojto 90:cb3d968589d8 5209 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
Kojto 90:cb3d968589d8 5210 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
Kojto 90:cb3d968589d8 5211 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
Kojto 90:cb3d968589d8 5212 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
Kojto 90:cb3d968589d8 5213 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
Kojto 90:cb3d968589d8 5214 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
Kojto 90:cb3d968589d8 5215 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
Kojto 90:cb3d968589d8 5216 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
Kojto 90:cb3d968589d8 5217 #define MTBDWT_FCT_MATCHED_SHIFT 24
Kojto 90:cb3d968589d8 5218 /* TBCTRL Bit Fields */
Kojto 90:cb3d968589d8 5219 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
Kojto 90:cb3d968589d8 5220 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
Kojto 90:cb3d968589d8 5221 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
Kojto 90:cb3d968589d8 5222 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
Kojto 90:cb3d968589d8 5223 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
Kojto 90:cb3d968589d8 5224 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
Kojto 90:cb3d968589d8 5225 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
Kojto 90:cb3d968589d8 5226 /* DEVICECFG Bit Fields */
Kojto 90:cb3d968589d8 5227 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5228 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
Kojto 90:cb3d968589d8 5229 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
Kojto 90:cb3d968589d8 5230 /* DEVICETYPID Bit Fields */
Kojto 90:cb3d968589d8 5231 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5232 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
Kojto 90:cb3d968589d8 5233 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
Kojto 90:cb3d968589d8 5234 /* PERIPHID Bit Fields */
Kojto 90:cb3d968589d8 5235 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5236 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
Kojto 90:cb3d968589d8 5237 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
Kojto 90:cb3d968589d8 5238 /* COMPID Bit Fields */
Kojto 90:cb3d968589d8 5239 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5240 #define MTBDWT_COMPID_COMPID_SHIFT 0
Kojto 90:cb3d968589d8 5241 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
Kojto 90:cb3d968589d8 5242
Kojto 90:cb3d968589d8 5243 /*!
Kojto 90:cb3d968589d8 5244 * @}
Kojto 90:cb3d968589d8 5245 */ /* end of group MTBDWT_Register_Masks */
Kojto 90:cb3d968589d8 5246
Kojto 90:cb3d968589d8 5247
Kojto 90:cb3d968589d8 5248 /* MTBDWT - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 5249 /** Peripheral MTBDWT base address */
Kojto 90:cb3d968589d8 5250 #define MTBDWT_BASE (0xF0001000u)
Kojto 90:cb3d968589d8 5251 /** Peripheral MTBDWT base pointer */
Kojto 90:cb3d968589d8 5252 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
Kojto 90:cb3d968589d8 5253 #define MTBDWT_BASE_PTR (MTBDWT)
Kojto 90:cb3d968589d8 5254 /** Array initializer of MTBDWT peripheral base addresses */
Kojto 90:cb3d968589d8 5255 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
Kojto 90:cb3d968589d8 5256 /** Array initializer of MTBDWT peripheral base pointers */
Kojto 90:cb3d968589d8 5257 #define MTBDWT_BASE_PTRS { MTBDWT }
Kojto 90:cb3d968589d8 5258
Kojto 90:cb3d968589d8 5259 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5260 -- MTBDWT - Register accessor macros
Kojto 90:cb3d968589d8 5261 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5262
Kojto 90:cb3d968589d8 5263 /*!
Kojto 90:cb3d968589d8 5264 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
Kojto 90:cb3d968589d8 5265 * @{
Kojto 90:cb3d968589d8 5266 */
Kojto 90:cb3d968589d8 5267
Kojto 90:cb3d968589d8 5268
Kojto 90:cb3d968589d8 5269 /* MTBDWT - Register instance definitions */
Kojto 90:cb3d968589d8 5270 /* MTBDWT */
Kojto 90:cb3d968589d8 5271 #define MTBDWT_CTRL MTBDWT_CTRL_REG(MTBDWT)
Kojto 90:cb3d968589d8 5272 #define MTBDWT_COMP0 MTBDWT_COMP_REG(MTBDWT,0)
Kojto 90:cb3d968589d8 5273 #define MTBDWT_MASK0 MTBDWT_MASK_REG(MTBDWT,0)
Kojto 90:cb3d968589d8 5274 #define MTBDWT_FCT0 MTBDWT_FCT_REG(MTBDWT,0)
Kojto 90:cb3d968589d8 5275 #define MTBDWT_COMP1 MTBDWT_COMP_REG(MTBDWT,1)
Kojto 90:cb3d968589d8 5276 #define MTBDWT_MASK1 MTBDWT_MASK_REG(MTBDWT,1)
Kojto 90:cb3d968589d8 5277 #define MTBDWT_FCT1 MTBDWT_FCT_REG(MTBDWT,1)
Kojto 90:cb3d968589d8 5278 #define MTBDWT_TBCTRL MTBDWT_TBCTRL_REG(MTBDWT)
Kojto 90:cb3d968589d8 5279 #define MTBDWT_DEVICECFG MTBDWT_DEVICECFG_REG(MTBDWT)
Kojto 90:cb3d968589d8 5280 #define MTBDWT_DEVICETYPID MTBDWT_DEVICETYPID_REG(MTBDWT)
Kojto 90:cb3d968589d8 5281 #define MTBDWT_PERIPHID4 MTBDWT_PERIPHID_REG(MTBDWT,0)
Kojto 90:cb3d968589d8 5282 #define MTBDWT_PERIPHID5 MTBDWT_PERIPHID_REG(MTBDWT,1)
Kojto 90:cb3d968589d8 5283 #define MTBDWT_PERIPHID6 MTBDWT_PERIPHID_REG(MTBDWT,2)
Kojto 90:cb3d968589d8 5284 #define MTBDWT_PERIPHID7 MTBDWT_PERIPHID_REG(MTBDWT,3)
Kojto 90:cb3d968589d8 5285 #define MTBDWT_PERIPHID0 MTBDWT_PERIPHID_REG(MTBDWT,4)
Kojto 90:cb3d968589d8 5286 #define MTBDWT_PERIPHID1 MTBDWT_PERIPHID_REG(MTBDWT,5)
Kojto 90:cb3d968589d8 5287 #define MTBDWT_PERIPHID2 MTBDWT_PERIPHID_REG(MTBDWT,6)
Kojto 90:cb3d968589d8 5288 #define MTBDWT_PERIPHID3 MTBDWT_PERIPHID_REG(MTBDWT,7)
Kojto 90:cb3d968589d8 5289 #define MTBDWT_COMPID0 MTBDWT_COMPID_REG(MTBDWT,0)
Kojto 90:cb3d968589d8 5290 #define MTBDWT_COMPID1 MTBDWT_COMPID_REG(MTBDWT,1)
Kojto 90:cb3d968589d8 5291 #define MTBDWT_COMPID2 MTBDWT_COMPID_REG(MTBDWT,2)
Kojto 90:cb3d968589d8 5292 #define MTBDWT_COMPID3 MTBDWT_COMPID_REG(MTBDWT,3)
Kojto 90:cb3d968589d8 5293
Kojto 90:cb3d968589d8 5294 /* MTBDWT - Register array accessors */
Kojto 90:cb3d968589d8 5295 #define MTBDWT_COMP(index) MTBDWT_COMP_REG(MTBDWT,index)
Kojto 90:cb3d968589d8 5296 #define MTBDWT_MASK(index) MTBDWT_MASK_REG(MTBDWT,index)
Kojto 90:cb3d968589d8 5297 #define MTBDWT_FCT(index) MTBDWT_FCT_REG(MTBDWT,index)
Kojto 90:cb3d968589d8 5298 #define MTBDWT_PERIPHID(index) MTBDWT_PERIPHID_REG(MTBDWT,index)
Kojto 90:cb3d968589d8 5299 #define MTBDWT_COMPID(index) MTBDWT_COMPID_REG(MTBDWT,index)
Kojto 90:cb3d968589d8 5300
Kojto 90:cb3d968589d8 5301 /*!
Kojto 90:cb3d968589d8 5302 * @}
Kojto 90:cb3d968589d8 5303 */ /* end of group MTBDWT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5304
Kojto 90:cb3d968589d8 5305
Kojto 90:cb3d968589d8 5306 /*!
Kojto 90:cb3d968589d8 5307 * @}
Kojto 90:cb3d968589d8 5308 */ /* end of group MTBDWT_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 5309
Kojto 90:cb3d968589d8 5310
Kojto 90:cb3d968589d8 5311 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5312 -- NV Peripheral Access Layer
Kojto 90:cb3d968589d8 5313 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5314
Kojto 90:cb3d968589d8 5315 /*!
Kojto 90:cb3d968589d8 5316 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
Kojto 90:cb3d968589d8 5317 * @{
Kojto 90:cb3d968589d8 5318 */
Kojto 90:cb3d968589d8 5319
Kojto 90:cb3d968589d8 5320 /** NV - Register Layout Typedef */
Kojto 90:cb3d968589d8 5321 typedef struct {
Kojto 90:cb3d968589d8 5322 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
Kojto 90:cb3d968589d8 5323 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
Kojto 90:cb3d968589d8 5324 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
Kojto 90:cb3d968589d8 5325 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
Kojto 90:cb3d968589d8 5326 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
Kojto 90:cb3d968589d8 5327 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
Kojto 90:cb3d968589d8 5328 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
Kojto 90:cb3d968589d8 5329 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
Kojto 90:cb3d968589d8 5330 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
Kojto 90:cb3d968589d8 5331 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
Kojto 90:cb3d968589d8 5332 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
Kojto 90:cb3d968589d8 5333 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
Kojto 90:cb3d968589d8 5334 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
Kojto 90:cb3d968589d8 5335 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
Kojto 90:cb3d968589d8 5336 } NV_Type, *NV_MemMapPtr;
Kojto 90:cb3d968589d8 5337
Kojto 90:cb3d968589d8 5338 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5339 -- NV - Register accessor macros
Kojto 90:cb3d968589d8 5340 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5341
Kojto 90:cb3d968589d8 5342 /*!
Kojto 90:cb3d968589d8 5343 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
Kojto 90:cb3d968589d8 5344 * @{
Kojto 90:cb3d968589d8 5345 */
Kojto 90:cb3d968589d8 5346
Kojto 90:cb3d968589d8 5347
Kojto 90:cb3d968589d8 5348 /* NV - Register accessors */
Kojto 90:cb3d968589d8 5349 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
Kojto 90:cb3d968589d8 5350 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
Kojto 90:cb3d968589d8 5351 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
Kojto 90:cb3d968589d8 5352 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
Kojto 90:cb3d968589d8 5353 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
Kojto 90:cb3d968589d8 5354 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
Kojto 90:cb3d968589d8 5355 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
Kojto 90:cb3d968589d8 5356 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
Kojto 90:cb3d968589d8 5357 #define NV_FPROT3_REG(base) ((base)->FPROT3)
Kojto 90:cb3d968589d8 5358 #define NV_FPROT2_REG(base) ((base)->FPROT2)
Kojto 90:cb3d968589d8 5359 #define NV_FPROT1_REG(base) ((base)->FPROT1)
Kojto 90:cb3d968589d8 5360 #define NV_FPROT0_REG(base) ((base)->FPROT0)
Kojto 90:cb3d968589d8 5361 #define NV_FSEC_REG(base) ((base)->FSEC)
Kojto 90:cb3d968589d8 5362 #define NV_FOPT_REG(base) ((base)->FOPT)
Kojto 90:cb3d968589d8 5363
Kojto 90:cb3d968589d8 5364 /*!
Kojto 90:cb3d968589d8 5365 * @}
Kojto 90:cb3d968589d8 5366 */ /* end of group NV_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5367
Kojto 90:cb3d968589d8 5368
Kojto 90:cb3d968589d8 5369 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5370 -- NV Register Masks
Kojto 90:cb3d968589d8 5371 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5372
Kojto 90:cb3d968589d8 5373 /*!
Kojto 90:cb3d968589d8 5374 * @addtogroup NV_Register_Masks NV Register Masks
Kojto 90:cb3d968589d8 5375 * @{
Kojto 90:cb3d968589d8 5376 */
Kojto 90:cb3d968589d8 5377
Kojto 90:cb3d968589d8 5378 /* BACKKEY3 Bit Fields */
Kojto 90:cb3d968589d8 5379 #define NV_BACKKEY3_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 5380 #define NV_BACKKEY3_KEY_SHIFT 0
Kojto 90:cb3d968589d8 5381 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
Kojto 90:cb3d968589d8 5382 /* BACKKEY2 Bit Fields */
Kojto 90:cb3d968589d8 5383 #define NV_BACKKEY2_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 5384 #define NV_BACKKEY2_KEY_SHIFT 0
Kojto 90:cb3d968589d8 5385 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
Kojto 90:cb3d968589d8 5386 /* BACKKEY1 Bit Fields */
Kojto 90:cb3d968589d8 5387 #define NV_BACKKEY1_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 5388 #define NV_BACKKEY1_KEY_SHIFT 0
Kojto 90:cb3d968589d8 5389 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
Kojto 90:cb3d968589d8 5390 /* BACKKEY0 Bit Fields */
Kojto 90:cb3d968589d8 5391 #define NV_BACKKEY0_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 5392 #define NV_BACKKEY0_KEY_SHIFT 0
Kojto 90:cb3d968589d8 5393 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
Kojto 90:cb3d968589d8 5394 /* BACKKEY7 Bit Fields */
Kojto 90:cb3d968589d8 5395 #define NV_BACKKEY7_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 5396 #define NV_BACKKEY7_KEY_SHIFT 0
Kojto 90:cb3d968589d8 5397 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
Kojto 90:cb3d968589d8 5398 /* BACKKEY6 Bit Fields */
Kojto 90:cb3d968589d8 5399 #define NV_BACKKEY6_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 5400 #define NV_BACKKEY6_KEY_SHIFT 0
Kojto 90:cb3d968589d8 5401 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
Kojto 90:cb3d968589d8 5402 /* BACKKEY5 Bit Fields */
Kojto 90:cb3d968589d8 5403 #define NV_BACKKEY5_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 5404 #define NV_BACKKEY5_KEY_SHIFT 0
Kojto 90:cb3d968589d8 5405 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
Kojto 90:cb3d968589d8 5406 /* BACKKEY4 Bit Fields */
Kojto 90:cb3d968589d8 5407 #define NV_BACKKEY4_KEY_MASK 0xFFu
Kojto 90:cb3d968589d8 5408 #define NV_BACKKEY4_KEY_SHIFT 0
Kojto 90:cb3d968589d8 5409 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
Kojto 90:cb3d968589d8 5410 /* FPROT3 Bit Fields */
Kojto 90:cb3d968589d8 5411 #define NV_FPROT3_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 5412 #define NV_FPROT3_PROT_SHIFT 0
Kojto 90:cb3d968589d8 5413 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
Kojto 90:cb3d968589d8 5414 /* FPROT2 Bit Fields */
Kojto 90:cb3d968589d8 5415 #define NV_FPROT2_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 5416 #define NV_FPROT2_PROT_SHIFT 0
Kojto 90:cb3d968589d8 5417 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
Kojto 90:cb3d968589d8 5418 /* FPROT1 Bit Fields */
Kojto 90:cb3d968589d8 5419 #define NV_FPROT1_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 5420 #define NV_FPROT1_PROT_SHIFT 0
Kojto 90:cb3d968589d8 5421 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
Kojto 90:cb3d968589d8 5422 /* FPROT0 Bit Fields */
Kojto 90:cb3d968589d8 5423 #define NV_FPROT0_PROT_MASK 0xFFu
Kojto 90:cb3d968589d8 5424 #define NV_FPROT0_PROT_SHIFT 0
Kojto 90:cb3d968589d8 5425 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
Kojto 90:cb3d968589d8 5426 /* FSEC Bit Fields */
Kojto 90:cb3d968589d8 5427 #define NV_FSEC_SEC_MASK 0x3u
Kojto 90:cb3d968589d8 5428 #define NV_FSEC_SEC_SHIFT 0
Kojto 90:cb3d968589d8 5429 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
Kojto 90:cb3d968589d8 5430 #define NV_FSEC_FSLACC_MASK 0xCu
Kojto 90:cb3d968589d8 5431 #define NV_FSEC_FSLACC_SHIFT 2
Kojto 90:cb3d968589d8 5432 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
Kojto 90:cb3d968589d8 5433 #define NV_FSEC_MEEN_MASK 0x30u
Kojto 90:cb3d968589d8 5434 #define NV_FSEC_MEEN_SHIFT 4
Kojto 90:cb3d968589d8 5435 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
Kojto 90:cb3d968589d8 5436 #define NV_FSEC_KEYEN_MASK 0xC0u
Kojto 90:cb3d968589d8 5437 #define NV_FSEC_KEYEN_SHIFT 6
Kojto 90:cb3d968589d8 5438 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
Kojto 90:cb3d968589d8 5439 /* FOPT Bit Fields */
Kojto 90:cb3d968589d8 5440 #define NV_FOPT_LPBOOT0_MASK 0x1u
Kojto 90:cb3d968589d8 5441 #define NV_FOPT_LPBOOT0_SHIFT 0
Kojto 90:cb3d968589d8 5442 #define NV_FOPT_BOOTPIN_OPT_MASK 0x2u
Kojto 90:cb3d968589d8 5443 #define NV_FOPT_BOOTPIN_OPT_SHIFT 1
Kojto 90:cb3d968589d8 5444 #define NV_FOPT_NMI_DIS_MASK 0x4u
Kojto 90:cb3d968589d8 5445 #define NV_FOPT_NMI_DIS_SHIFT 2
Kojto 90:cb3d968589d8 5446 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
Kojto 90:cb3d968589d8 5447 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
Kojto 90:cb3d968589d8 5448 #define NV_FOPT_LPBOOT1_MASK 0x10u
Kojto 90:cb3d968589d8 5449 #define NV_FOPT_LPBOOT1_SHIFT 4
Kojto 90:cb3d968589d8 5450 #define NV_FOPT_FAST_INIT_MASK 0x20u
Kojto 90:cb3d968589d8 5451 #define NV_FOPT_FAST_INIT_SHIFT 5
Kojto 90:cb3d968589d8 5452 #define NV_FOPT_BOOTSRC_SEL_MASK 0xC0u
Kojto 90:cb3d968589d8 5453 #define NV_FOPT_BOOTSRC_SEL_SHIFT 6
Kojto 90:cb3d968589d8 5454 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTSRC_SEL_SHIFT))&NV_FOPT_BOOTSRC_SEL_MASK)
Kojto 90:cb3d968589d8 5455
Kojto 90:cb3d968589d8 5456 /*!
Kojto 90:cb3d968589d8 5457 * @}
Kojto 90:cb3d968589d8 5458 */ /* end of group NV_Register_Masks */
Kojto 90:cb3d968589d8 5459
Kojto 90:cb3d968589d8 5460
Kojto 90:cb3d968589d8 5461 /* NV - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 5462 /** Peripheral FTFA_FlashConfig base address */
Kojto 90:cb3d968589d8 5463 #define FTFA_FlashConfig_BASE (0x400u)
Kojto 90:cb3d968589d8 5464 /** Peripheral FTFA_FlashConfig base pointer */
Kojto 90:cb3d968589d8 5465 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
Kojto 90:cb3d968589d8 5466 #define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5467 /** Array initializer of NV peripheral base addresses */
Kojto 90:cb3d968589d8 5468 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
Kojto 90:cb3d968589d8 5469 /** Array initializer of NV peripheral base pointers */
Kojto 90:cb3d968589d8 5470 #define NV_BASE_PTRS { FTFA_FlashConfig }
Kojto 90:cb3d968589d8 5471
Kojto 90:cb3d968589d8 5472 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5473 -- NV - Register accessor macros
Kojto 90:cb3d968589d8 5474 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5475
Kojto 90:cb3d968589d8 5476 /*!
Kojto 90:cb3d968589d8 5477 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
Kojto 90:cb3d968589d8 5478 * @{
Kojto 90:cb3d968589d8 5479 */
Kojto 90:cb3d968589d8 5480
Kojto 90:cb3d968589d8 5481
Kojto 90:cb3d968589d8 5482 /* NV - Register instance definitions */
Kojto 90:cb3d968589d8 5483 /* FTFA_FlashConfig */
Kojto 90:cb3d968589d8 5484 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5485 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5486 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5487 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5488 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5489 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5490 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5491 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5492 #define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5493 #define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5494 #define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5495 #define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5496 #define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5497 #define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
Kojto 90:cb3d968589d8 5498
Kojto 90:cb3d968589d8 5499 /*!
Kojto 90:cb3d968589d8 5500 * @}
Kojto 90:cb3d968589d8 5501 */ /* end of group NV_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5502
Kojto 90:cb3d968589d8 5503
Kojto 90:cb3d968589d8 5504 /*!
Kojto 90:cb3d968589d8 5505 * @}
Kojto 90:cb3d968589d8 5506 */ /* end of group NV_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 5507
Kojto 90:cb3d968589d8 5508
Kojto 90:cb3d968589d8 5509 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5510 -- OSC Peripheral Access Layer
Kojto 90:cb3d968589d8 5511 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5512
Kojto 90:cb3d968589d8 5513 /*!
Kojto 90:cb3d968589d8 5514 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
Kojto 90:cb3d968589d8 5515 * @{
Kojto 90:cb3d968589d8 5516 */
Kojto 90:cb3d968589d8 5517
Kojto 90:cb3d968589d8 5518 /** OSC - Register Layout Typedef */
Kojto 90:cb3d968589d8 5519 typedef struct {
Kojto 90:cb3d968589d8 5520 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 5521 } OSC_Type, *OSC_MemMapPtr;
Kojto 90:cb3d968589d8 5522
Kojto 90:cb3d968589d8 5523 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5524 -- OSC - Register accessor macros
Kojto 90:cb3d968589d8 5525 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5526
Kojto 90:cb3d968589d8 5527 /*!
Kojto 90:cb3d968589d8 5528 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
Kojto 90:cb3d968589d8 5529 * @{
Kojto 90:cb3d968589d8 5530 */
Kojto 90:cb3d968589d8 5531
Kojto 90:cb3d968589d8 5532
Kojto 90:cb3d968589d8 5533 /* OSC - Register accessors */
Kojto 90:cb3d968589d8 5534 #define OSC_CR_REG(base) ((base)->CR)
Kojto 90:cb3d968589d8 5535
Kojto 90:cb3d968589d8 5536 /*!
Kojto 90:cb3d968589d8 5537 * @}
Kojto 90:cb3d968589d8 5538 */ /* end of group OSC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5539
Kojto 90:cb3d968589d8 5540
Kojto 90:cb3d968589d8 5541 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5542 -- OSC Register Masks
Kojto 90:cb3d968589d8 5543 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5544
Kojto 90:cb3d968589d8 5545 /*!
Kojto 90:cb3d968589d8 5546 * @addtogroup OSC_Register_Masks OSC Register Masks
Kojto 90:cb3d968589d8 5547 * @{
Kojto 90:cb3d968589d8 5548 */
Kojto 90:cb3d968589d8 5549
Kojto 90:cb3d968589d8 5550 /* CR Bit Fields */
Kojto 90:cb3d968589d8 5551 #define OSC_CR_SC16P_MASK 0x1u
Kojto 90:cb3d968589d8 5552 #define OSC_CR_SC16P_SHIFT 0
Kojto 90:cb3d968589d8 5553 #define OSC_CR_SC8P_MASK 0x2u
Kojto 90:cb3d968589d8 5554 #define OSC_CR_SC8P_SHIFT 1
Kojto 90:cb3d968589d8 5555 #define OSC_CR_SC4P_MASK 0x4u
Kojto 90:cb3d968589d8 5556 #define OSC_CR_SC4P_SHIFT 2
Kojto 90:cb3d968589d8 5557 #define OSC_CR_SC2P_MASK 0x8u
Kojto 90:cb3d968589d8 5558 #define OSC_CR_SC2P_SHIFT 3
Kojto 90:cb3d968589d8 5559 #define OSC_CR_EREFSTEN_MASK 0x20u
Kojto 90:cb3d968589d8 5560 #define OSC_CR_EREFSTEN_SHIFT 5
Kojto 90:cb3d968589d8 5561 #define OSC_CR_ERCLKEN_MASK 0x80u
Kojto 90:cb3d968589d8 5562 #define OSC_CR_ERCLKEN_SHIFT 7
Kojto 90:cb3d968589d8 5563
Kojto 90:cb3d968589d8 5564 /*!
Kojto 90:cb3d968589d8 5565 * @}
Kojto 90:cb3d968589d8 5566 */ /* end of group OSC_Register_Masks */
Kojto 90:cb3d968589d8 5567
Kojto 90:cb3d968589d8 5568
Kojto 90:cb3d968589d8 5569 /* OSC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 5570 /** Peripheral OSC0 base address */
Kojto 90:cb3d968589d8 5571 #define OSC0_BASE (0x40065000u)
Kojto 90:cb3d968589d8 5572 /** Peripheral OSC0 base pointer */
Kojto 90:cb3d968589d8 5573 #define OSC0 ((OSC_Type *)OSC0_BASE)
Kojto 90:cb3d968589d8 5574 #define OSC0_BASE_PTR (OSC0)
Kojto 90:cb3d968589d8 5575 /** Array initializer of OSC peripheral base addresses */
Kojto 90:cb3d968589d8 5576 #define OSC_BASE_ADDRS { OSC0_BASE }
Kojto 90:cb3d968589d8 5577 /** Array initializer of OSC peripheral base pointers */
Kojto 90:cb3d968589d8 5578 #define OSC_BASE_PTRS { OSC0 }
Kojto 90:cb3d968589d8 5579
Kojto 90:cb3d968589d8 5580 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5581 -- OSC - Register accessor macros
Kojto 90:cb3d968589d8 5582 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5583
Kojto 90:cb3d968589d8 5584 /*!
Kojto 90:cb3d968589d8 5585 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
Kojto 90:cb3d968589d8 5586 * @{
Kojto 90:cb3d968589d8 5587 */
Kojto 90:cb3d968589d8 5588
Kojto 90:cb3d968589d8 5589
Kojto 90:cb3d968589d8 5590 /* OSC - Register instance definitions */
Kojto 90:cb3d968589d8 5591 /* OSC0 */
Kojto 90:cb3d968589d8 5592 #define OSC0_CR OSC_CR_REG(OSC0)
Kojto 90:cb3d968589d8 5593
Kojto 90:cb3d968589d8 5594 /*!
Kojto 90:cb3d968589d8 5595 * @}
Kojto 90:cb3d968589d8 5596 */ /* end of group OSC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5597
Kojto 90:cb3d968589d8 5598
Kojto 90:cb3d968589d8 5599 /*!
Kojto 90:cb3d968589d8 5600 * @}
Kojto 90:cb3d968589d8 5601 */ /* end of group OSC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 5602
Kojto 90:cb3d968589d8 5603
Kojto 90:cb3d968589d8 5604 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5605 -- PIT Peripheral Access Layer
Kojto 90:cb3d968589d8 5606 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5607
Kojto 90:cb3d968589d8 5608 /*!
Kojto 90:cb3d968589d8 5609 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
Kojto 90:cb3d968589d8 5610 * @{
Kojto 90:cb3d968589d8 5611 */
Kojto 90:cb3d968589d8 5612
Kojto 90:cb3d968589d8 5613 /** PIT - Register Layout Typedef */
Kojto 90:cb3d968589d8 5614 typedef struct {
Kojto 90:cb3d968589d8 5615 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
Kojto 90:cb3d968589d8 5616 uint8_t RESERVED_0[220];
Kojto 90:cb3d968589d8 5617 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
Kojto 90:cb3d968589d8 5618 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
Kojto 90:cb3d968589d8 5619 uint8_t RESERVED_1[24];
Kojto 90:cb3d968589d8 5620 struct { /* offset: 0x100, array step: 0x10 */
Kojto 90:cb3d968589d8 5621 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
Kojto 90:cb3d968589d8 5622 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
Kojto 90:cb3d968589d8 5623 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
Kojto 90:cb3d968589d8 5624 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
Kojto 90:cb3d968589d8 5625 } CHANNEL[2];
Kojto 90:cb3d968589d8 5626 } PIT_Type, *PIT_MemMapPtr;
Kojto 90:cb3d968589d8 5627
Kojto 90:cb3d968589d8 5628 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5629 -- PIT - Register accessor macros
Kojto 90:cb3d968589d8 5630 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5631
Kojto 90:cb3d968589d8 5632 /*!
Kojto 90:cb3d968589d8 5633 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
Kojto 90:cb3d968589d8 5634 * @{
Kojto 90:cb3d968589d8 5635 */
Kojto 90:cb3d968589d8 5636
Kojto 90:cb3d968589d8 5637
Kojto 90:cb3d968589d8 5638 /* PIT - Register accessors */
Kojto 90:cb3d968589d8 5639 #define PIT_MCR_REG(base) ((base)->MCR)
Kojto 90:cb3d968589d8 5640 #define PIT_LTMR64H_REG(base) ((base)->LTMR64H)
Kojto 90:cb3d968589d8 5641 #define PIT_LTMR64L_REG(base) ((base)->LTMR64L)
Kojto 90:cb3d968589d8 5642 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
Kojto 90:cb3d968589d8 5643 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
Kojto 90:cb3d968589d8 5644 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
Kojto 90:cb3d968589d8 5645 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
Kojto 90:cb3d968589d8 5646
Kojto 90:cb3d968589d8 5647 /*!
Kojto 90:cb3d968589d8 5648 * @}
Kojto 90:cb3d968589d8 5649 */ /* end of group PIT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5650
Kojto 90:cb3d968589d8 5651
Kojto 90:cb3d968589d8 5652 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5653 -- PIT Register Masks
Kojto 90:cb3d968589d8 5654 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5655
Kojto 90:cb3d968589d8 5656 /*!
Kojto 90:cb3d968589d8 5657 * @addtogroup PIT_Register_Masks PIT Register Masks
Kojto 90:cb3d968589d8 5658 * @{
Kojto 90:cb3d968589d8 5659 */
Kojto 90:cb3d968589d8 5660
Kojto 90:cb3d968589d8 5661 /* MCR Bit Fields */
Kojto 90:cb3d968589d8 5662 #define PIT_MCR_FRZ_MASK 0x1u
Kojto 90:cb3d968589d8 5663 #define PIT_MCR_FRZ_SHIFT 0
Kojto 90:cb3d968589d8 5664 #define PIT_MCR_MDIS_MASK 0x2u
Kojto 90:cb3d968589d8 5665 #define PIT_MCR_MDIS_SHIFT 1
Kojto 90:cb3d968589d8 5666 /* LTMR64H Bit Fields */
Kojto 90:cb3d968589d8 5667 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5668 #define PIT_LTMR64H_LTH_SHIFT 0
Kojto 90:cb3d968589d8 5669 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
Kojto 90:cb3d968589d8 5670 /* LTMR64L Bit Fields */
Kojto 90:cb3d968589d8 5671 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5672 #define PIT_LTMR64L_LTL_SHIFT 0
Kojto 90:cb3d968589d8 5673 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
Kojto 90:cb3d968589d8 5674 /* LDVAL Bit Fields */
Kojto 90:cb3d968589d8 5675 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5676 #define PIT_LDVAL_TSV_SHIFT 0
Kojto 90:cb3d968589d8 5677 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
Kojto 90:cb3d968589d8 5678 /* CVAL Bit Fields */
Kojto 90:cb3d968589d8 5679 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5680 #define PIT_CVAL_TVL_SHIFT 0
Kojto 90:cb3d968589d8 5681 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
Kojto 90:cb3d968589d8 5682 /* TCTRL Bit Fields */
Kojto 90:cb3d968589d8 5683 #define PIT_TCTRL_TEN_MASK 0x1u
Kojto 90:cb3d968589d8 5684 #define PIT_TCTRL_TEN_SHIFT 0
Kojto 90:cb3d968589d8 5685 #define PIT_TCTRL_TIE_MASK 0x2u
Kojto 90:cb3d968589d8 5686 #define PIT_TCTRL_TIE_SHIFT 1
Kojto 90:cb3d968589d8 5687 #define PIT_TCTRL_CHN_MASK 0x4u
Kojto 90:cb3d968589d8 5688 #define PIT_TCTRL_CHN_SHIFT 2
Kojto 90:cb3d968589d8 5689 /* TFLG Bit Fields */
Kojto 90:cb3d968589d8 5690 #define PIT_TFLG_TIF_MASK 0x1u
Kojto 90:cb3d968589d8 5691 #define PIT_TFLG_TIF_SHIFT 0
Kojto 90:cb3d968589d8 5692
Kojto 90:cb3d968589d8 5693 /*!
Kojto 90:cb3d968589d8 5694 * @}
Kojto 90:cb3d968589d8 5695 */ /* end of group PIT_Register_Masks */
Kojto 90:cb3d968589d8 5696
Kojto 90:cb3d968589d8 5697
Kojto 90:cb3d968589d8 5698 /* PIT - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 5699 /** Peripheral PIT base address */
Kojto 90:cb3d968589d8 5700 #define PIT_BASE (0x40037000u)
Kojto 90:cb3d968589d8 5701 /** Peripheral PIT base pointer */
Kojto 90:cb3d968589d8 5702 #define PIT ((PIT_Type *)PIT_BASE)
Kojto 90:cb3d968589d8 5703 #define PIT_BASE_PTR (PIT)
Kojto 90:cb3d968589d8 5704 /** Array initializer of PIT peripheral base addresses */
Kojto 90:cb3d968589d8 5705 #define PIT_BASE_ADDRS { PIT_BASE }
Kojto 90:cb3d968589d8 5706 /** Array initializer of PIT peripheral base pointers */
Kojto 90:cb3d968589d8 5707 #define PIT_BASE_PTRS { PIT }
Kojto 90:cb3d968589d8 5708 /** Interrupt vectors for the PIT peripheral type */
Kojto 90:cb3d968589d8 5709 #define PIT_IRQS { PIT_IRQn, PIT_IRQn }
Kojto 90:cb3d968589d8 5710
Kojto 90:cb3d968589d8 5711 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5712 -- PIT - Register accessor macros
Kojto 90:cb3d968589d8 5713 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5714
Kojto 90:cb3d968589d8 5715 /*!
Kojto 90:cb3d968589d8 5716 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
Kojto 90:cb3d968589d8 5717 * @{
Kojto 90:cb3d968589d8 5718 */
Kojto 90:cb3d968589d8 5719
Kojto 90:cb3d968589d8 5720
Kojto 90:cb3d968589d8 5721 /* PIT - Register instance definitions */
Kojto 90:cb3d968589d8 5722 /* PIT */
Kojto 90:cb3d968589d8 5723 #define PIT_MCR PIT_MCR_REG(PIT)
Kojto 90:cb3d968589d8 5724 #define PIT_LTMR64H PIT_LTMR64H_REG(PIT)
Kojto 90:cb3d968589d8 5725 #define PIT_LTMR64L PIT_LTMR64L_REG(PIT)
Kojto 90:cb3d968589d8 5726 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
Kojto 90:cb3d968589d8 5727 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
Kojto 90:cb3d968589d8 5728 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
Kojto 90:cb3d968589d8 5729 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
Kojto 90:cb3d968589d8 5730 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
Kojto 90:cb3d968589d8 5731 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
Kojto 90:cb3d968589d8 5732 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
Kojto 90:cb3d968589d8 5733 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
Kojto 90:cb3d968589d8 5734
Kojto 90:cb3d968589d8 5735 /* PIT - Register array accessors */
Kojto 90:cb3d968589d8 5736 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
Kojto 90:cb3d968589d8 5737 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
Kojto 90:cb3d968589d8 5738 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
Kojto 90:cb3d968589d8 5739 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
Kojto 90:cb3d968589d8 5740
Kojto 90:cb3d968589d8 5741 /*!
Kojto 90:cb3d968589d8 5742 * @}
Kojto 90:cb3d968589d8 5743 */ /* end of group PIT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5744
Kojto 90:cb3d968589d8 5745
Kojto 90:cb3d968589d8 5746 /*!
Kojto 90:cb3d968589d8 5747 * @}
Kojto 90:cb3d968589d8 5748 */ /* end of group PIT_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 5749
Kojto 90:cb3d968589d8 5750
Kojto 90:cb3d968589d8 5751 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5752 -- PMC Peripheral Access Layer
Kojto 90:cb3d968589d8 5753 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5754
Kojto 90:cb3d968589d8 5755 /*!
Kojto 90:cb3d968589d8 5756 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
Kojto 90:cb3d968589d8 5757 * @{
Kojto 90:cb3d968589d8 5758 */
Kojto 90:cb3d968589d8 5759
Kojto 90:cb3d968589d8 5760 /** PMC - Register Layout Typedef */
Kojto 90:cb3d968589d8 5761 typedef struct {
Kojto 90:cb3d968589d8 5762 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
Kojto 90:cb3d968589d8 5763 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
Kojto 90:cb3d968589d8 5764 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
Kojto 90:cb3d968589d8 5765 } PMC_Type, *PMC_MemMapPtr;
Kojto 90:cb3d968589d8 5766
Kojto 90:cb3d968589d8 5767 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5768 -- PMC - Register accessor macros
Kojto 90:cb3d968589d8 5769 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5770
Kojto 90:cb3d968589d8 5771 /*!
Kojto 90:cb3d968589d8 5772 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
Kojto 90:cb3d968589d8 5773 * @{
Kojto 90:cb3d968589d8 5774 */
Kojto 90:cb3d968589d8 5775
Kojto 90:cb3d968589d8 5776
Kojto 90:cb3d968589d8 5777 /* PMC - Register accessors */
Kojto 90:cb3d968589d8 5778 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
Kojto 90:cb3d968589d8 5779 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
Kojto 90:cb3d968589d8 5780 #define PMC_REGSC_REG(base) ((base)->REGSC)
Kojto 90:cb3d968589d8 5781
Kojto 90:cb3d968589d8 5782 /*!
Kojto 90:cb3d968589d8 5783 * @}
Kojto 90:cb3d968589d8 5784 */ /* end of group PMC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5785
Kojto 90:cb3d968589d8 5786
Kojto 90:cb3d968589d8 5787 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5788 -- PMC Register Masks
Kojto 90:cb3d968589d8 5789 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5790
Kojto 90:cb3d968589d8 5791 /*!
Kojto 90:cb3d968589d8 5792 * @addtogroup PMC_Register_Masks PMC Register Masks
Kojto 90:cb3d968589d8 5793 * @{
Kojto 90:cb3d968589d8 5794 */
Kojto 90:cb3d968589d8 5795
Kojto 90:cb3d968589d8 5796 /* LVDSC1 Bit Fields */
Kojto 90:cb3d968589d8 5797 #define PMC_LVDSC1_LVDV_MASK 0x3u
Kojto 90:cb3d968589d8 5798 #define PMC_LVDSC1_LVDV_SHIFT 0
Kojto 90:cb3d968589d8 5799 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
Kojto 90:cb3d968589d8 5800 #define PMC_LVDSC1_LVDRE_MASK 0x10u
Kojto 90:cb3d968589d8 5801 #define PMC_LVDSC1_LVDRE_SHIFT 4
Kojto 90:cb3d968589d8 5802 #define PMC_LVDSC1_LVDIE_MASK 0x20u
Kojto 90:cb3d968589d8 5803 #define PMC_LVDSC1_LVDIE_SHIFT 5
Kojto 90:cb3d968589d8 5804 #define PMC_LVDSC1_LVDACK_MASK 0x40u
Kojto 90:cb3d968589d8 5805 #define PMC_LVDSC1_LVDACK_SHIFT 6
Kojto 90:cb3d968589d8 5806 #define PMC_LVDSC1_LVDF_MASK 0x80u
Kojto 90:cb3d968589d8 5807 #define PMC_LVDSC1_LVDF_SHIFT 7
Kojto 90:cb3d968589d8 5808 /* LVDSC2 Bit Fields */
Kojto 90:cb3d968589d8 5809 #define PMC_LVDSC2_LVWV_MASK 0x3u
Kojto 90:cb3d968589d8 5810 #define PMC_LVDSC2_LVWV_SHIFT 0
Kojto 90:cb3d968589d8 5811 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
Kojto 90:cb3d968589d8 5812 #define PMC_LVDSC2_LVWIE_MASK 0x20u
Kojto 90:cb3d968589d8 5813 #define PMC_LVDSC2_LVWIE_SHIFT 5
Kojto 90:cb3d968589d8 5814 #define PMC_LVDSC2_LVWACK_MASK 0x40u
Kojto 90:cb3d968589d8 5815 #define PMC_LVDSC2_LVWACK_SHIFT 6
Kojto 90:cb3d968589d8 5816 #define PMC_LVDSC2_LVWF_MASK 0x80u
Kojto 90:cb3d968589d8 5817 #define PMC_LVDSC2_LVWF_SHIFT 7
Kojto 90:cb3d968589d8 5818 /* REGSC Bit Fields */
Kojto 90:cb3d968589d8 5819 #define PMC_REGSC_BGBE_MASK 0x1u
Kojto 90:cb3d968589d8 5820 #define PMC_REGSC_BGBE_SHIFT 0
Kojto 90:cb3d968589d8 5821 #define PMC_REGSC_REGONS_MASK 0x4u
Kojto 90:cb3d968589d8 5822 #define PMC_REGSC_REGONS_SHIFT 2
Kojto 90:cb3d968589d8 5823 #define PMC_REGSC_ACKISO_MASK 0x8u
Kojto 90:cb3d968589d8 5824 #define PMC_REGSC_ACKISO_SHIFT 3
Kojto 90:cb3d968589d8 5825 #define PMC_REGSC_BGEN_MASK 0x10u
Kojto 90:cb3d968589d8 5826 #define PMC_REGSC_BGEN_SHIFT 4
Kojto 90:cb3d968589d8 5827
Kojto 90:cb3d968589d8 5828 /*!
Kojto 90:cb3d968589d8 5829 * @}
Kojto 90:cb3d968589d8 5830 */ /* end of group PMC_Register_Masks */
Kojto 90:cb3d968589d8 5831
Kojto 90:cb3d968589d8 5832
Kojto 90:cb3d968589d8 5833 /* PMC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 5834 /** Peripheral PMC base address */
Kojto 90:cb3d968589d8 5835 #define PMC_BASE (0x4007D000u)
Kojto 90:cb3d968589d8 5836 /** Peripheral PMC base pointer */
Kojto 90:cb3d968589d8 5837 #define PMC ((PMC_Type *)PMC_BASE)
Kojto 90:cb3d968589d8 5838 #define PMC_BASE_PTR (PMC)
Kojto 90:cb3d968589d8 5839 /** Array initializer of PMC peripheral base addresses */
Kojto 90:cb3d968589d8 5840 #define PMC_BASE_ADDRS { PMC_BASE }
Kojto 90:cb3d968589d8 5841 /** Array initializer of PMC peripheral base pointers */
Kojto 90:cb3d968589d8 5842 #define PMC_BASE_PTRS { PMC }
Kojto 90:cb3d968589d8 5843 /** Interrupt vectors for the PMC peripheral type */
Kojto 90:cb3d968589d8 5844 #define PMC_IRQS { PMC_IRQn }
Kojto 90:cb3d968589d8 5845
Kojto 90:cb3d968589d8 5846 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5847 -- PMC - Register accessor macros
Kojto 90:cb3d968589d8 5848 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5849
Kojto 90:cb3d968589d8 5850 /*!
Kojto 90:cb3d968589d8 5851 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
Kojto 90:cb3d968589d8 5852 * @{
Kojto 90:cb3d968589d8 5853 */
Kojto 90:cb3d968589d8 5854
Kojto 90:cb3d968589d8 5855
Kojto 90:cb3d968589d8 5856 /* PMC - Register instance definitions */
Kojto 90:cb3d968589d8 5857 /* PMC */
Kojto 90:cb3d968589d8 5858 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
Kojto 90:cb3d968589d8 5859 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
Kojto 90:cb3d968589d8 5860 #define PMC_REGSC PMC_REGSC_REG(PMC)
Kojto 90:cb3d968589d8 5861
Kojto 90:cb3d968589d8 5862 /*!
Kojto 90:cb3d968589d8 5863 * @}
Kojto 90:cb3d968589d8 5864 */ /* end of group PMC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5865
Kojto 90:cb3d968589d8 5866
Kojto 90:cb3d968589d8 5867 /*!
Kojto 90:cb3d968589d8 5868 * @}
Kojto 90:cb3d968589d8 5869 */ /* end of group PMC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 5870
Kojto 90:cb3d968589d8 5871
Kojto 90:cb3d968589d8 5872 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5873 -- PORT Peripheral Access Layer
Kojto 90:cb3d968589d8 5874 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5875
Kojto 90:cb3d968589d8 5876 /*!
Kojto 90:cb3d968589d8 5877 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
Kojto 90:cb3d968589d8 5878 * @{
Kojto 90:cb3d968589d8 5879 */
Kojto 90:cb3d968589d8 5880
Kojto 90:cb3d968589d8 5881 /** PORT - Register Layout Typedef */
Kojto 90:cb3d968589d8 5882 typedef struct {
Kojto 90:cb3d968589d8 5883 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
Kojto 90:cb3d968589d8 5884 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
Kojto 90:cb3d968589d8 5885 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
Kojto 90:cb3d968589d8 5886 uint8_t RESERVED_0[24];
Kojto 90:cb3d968589d8 5887 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
Kojto 90:cb3d968589d8 5888 } PORT_Type, *PORT_MemMapPtr;
Kojto 90:cb3d968589d8 5889
Kojto 90:cb3d968589d8 5890 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5891 -- PORT - Register accessor macros
Kojto 90:cb3d968589d8 5892 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5893
Kojto 90:cb3d968589d8 5894 /*!
Kojto 90:cb3d968589d8 5895 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
Kojto 90:cb3d968589d8 5896 * @{
Kojto 90:cb3d968589d8 5897 */
Kojto 90:cb3d968589d8 5898
Kojto 90:cb3d968589d8 5899
Kojto 90:cb3d968589d8 5900 /* PORT - Register accessors */
Kojto 90:cb3d968589d8 5901 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
Kojto 90:cb3d968589d8 5902 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
Kojto 90:cb3d968589d8 5903 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
Kojto 90:cb3d968589d8 5904 #define PORT_ISFR_REG(base) ((base)->ISFR)
Kojto 90:cb3d968589d8 5905
Kojto 90:cb3d968589d8 5906 /*!
Kojto 90:cb3d968589d8 5907 * @}
Kojto 90:cb3d968589d8 5908 */ /* end of group PORT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 5909
Kojto 90:cb3d968589d8 5910
Kojto 90:cb3d968589d8 5911 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5912 -- PORT Register Masks
Kojto 90:cb3d968589d8 5913 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5914
Kojto 90:cb3d968589d8 5915 /*!
Kojto 90:cb3d968589d8 5916 * @addtogroup PORT_Register_Masks PORT Register Masks
Kojto 90:cb3d968589d8 5917 * @{
Kojto 90:cb3d968589d8 5918 */
Kojto 90:cb3d968589d8 5919
Kojto 90:cb3d968589d8 5920 /* PCR Bit Fields */
Kojto 90:cb3d968589d8 5921 #define PORT_PCR_PS_MASK 0x1u
Kojto 90:cb3d968589d8 5922 #define PORT_PCR_PS_SHIFT 0
Kojto 90:cb3d968589d8 5923 #define PORT_PCR_PE_MASK 0x2u
Kojto 90:cb3d968589d8 5924 #define PORT_PCR_PE_SHIFT 1
Kojto 90:cb3d968589d8 5925 #define PORT_PCR_SRE_MASK 0x4u
Kojto 90:cb3d968589d8 5926 #define PORT_PCR_SRE_SHIFT 2
Kojto 90:cb3d968589d8 5927 #define PORT_PCR_PFE_MASK 0x10u
Kojto 90:cb3d968589d8 5928 #define PORT_PCR_PFE_SHIFT 4
Kojto 90:cb3d968589d8 5929 #define PORT_PCR_DSE_MASK 0x40u
Kojto 90:cb3d968589d8 5930 #define PORT_PCR_DSE_SHIFT 6
Kojto 90:cb3d968589d8 5931 #define PORT_PCR_MUX_MASK 0x700u
Kojto 90:cb3d968589d8 5932 #define PORT_PCR_MUX_SHIFT 8
Kojto 90:cb3d968589d8 5933 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
Kojto 90:cb3d968589d8 5934 #define PORT_PCR_IRQC_MASK 0xF0000u
Kojto 90:cb3d968589d8 5935 #define PORT_PCR_IRQC_SHIFT 16
Kojto 90:cb3d968589d8 5936 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
Kojto 90:cb3d968589d8 5937 #define PORT_PCR_ISF_MASK 0x1000000u
Kojto 90:cb3d968589d8 5938 #define PORT_PCR_ISF_SHIFT 24
Kojto 90:cb3d968589d8 5939 /* GPCLR Bit Fields */
Kojto 90:cb3d968589d8 5940 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5941 #define PORT_GPCLR_GPWD_SHIFT 0
Kojto 90:cb3d968589d8 5942 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
Kojto 90:cb3d968589d8 5943 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 5944 #define PORT_GPCLR_GPWE_SHIFT 16
Kojto 90:cb3d968589d8 5945 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
Kojto 90:cb3d968589d8 5946 /* GPCHR Bit Fields */
Kojto 90:cb3d968589d8 5947 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
Kojto 90:cb3d968589d8 5948 #define PORT_GPCHR_GPWD_SHIFT 0
Kojto 90:cb3d968589d8 5949 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
Kojto 90:cb3d968589d8 5950 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
Kojto 90:cb3d968589d8 5951 #define PORT_GPCHR_GPWE_SHIFT 16
Kojto 90:cb3d968589d8 5952 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
Kojto 90:cb3d968589d8 5953 /* ISFR Bit Fields */
Kojto 90:cb3d968589d8 5954 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 5955 #define PORT_ISFR_ISF_SHIFT 0
Kojto 90:cb3d968589d8 5956 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
Kojto 90:cb3d968589d8 5957
Kojto 90:cb3d968589d8 5958 /*!
Kojto 90:cb3d968589d8 5959 * @}
Kojto 90:cb3d968589d8 5960 */ /* end of group PORT_Register_Masks */
Kojto 90:cb3d968589d8 5961
Kojto 90:cb3d968589d8 5962
Kojto 90:cb3d968589d8 5963 /* PORT - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 5964 /** Peripheral PORTA base address */
Kojto 90:cb3d968589d8 5965 #define PORTA_BASE (0x40049000u)
Kojto 90:cb3d968589d8 5966 /** Peripheral PORTA base pointer */
Kojto 90:cb3d968589d8 5967 #define PORTA ((PORT_Type *)PORTA_BASE)
Kojto 90:cb3d968589d8 5968 #define PORTA_BASE_PTR (PORTA)
Kojto 90:cb3d968589d8 5969 /** Peripheral PORTB base address */
Kojto 90:cb3d968589d8 5970 #define PORTB_BASE (0x4004A000u)
Kojto 90:cb3d968589d8 5971 /** Peripheral PORTB base pointer */
Kojto 90:cb3d968589d8 5972 #define PORTB ((PORT_Type *)PORTB_BASE)
Kojto 90:cb3d968589d8 5973 #define PORTB_BASE_PTR (PORTB)
Kojto 90:cb3d968589d8 5974 /** Peripheral PORTC base address */
Kojto 90:cb3d968589d8 5975 #define PORTC_BASE (0x4004B000u)
Kojto 90:cb3d968589d8 5976 /** Peripheral PORTC base pointer */
Kojto 90:cb3d968589d8 5977 #define PORTC ((PORT_Type *)PORTC_BASE)
Kojto 90:cb3d968589d8 5978 #define PORTC_BASE_PTR (PORTC)
Kojto 90:cb3d968589d8 5979 /** Peripheral PORTD base address */
Kojto 90:cb3d968589d8 5980 #define PORTD_BASE (0x4004C000u)
Kojto 90:cb3d968589d8 5981 /** Peripheral PORTD base pointer */
Kojto 90:cb3d968589d8 5982 #define PORTD ((PORT_Type *)PORTD_BASE)
Kojto 90:cb3d968589d8 5983 #define PORTD_BASE_PTR (PORTD)
Kojto 90:cb3d968589d8 5984 /** Peripheral PORTE base address */
Kojto 90:cb3d968589d8 5985 #define PORTE_BASE (0x4004D000u)
Kojto 90:cb3d968589d8 5986 /** Peripheral PORTE base pointer */
Kojto 90:cb3d968589d8 5987 #define PORTE ((PORT_Type *)PORTE_BASE)
Kojto 90:cb3d968589d8 5988 #define PORTE_BASE_PTR (PORTE)
Kojto 90:cb3d968589d8 5989 /** Array initializer of PORT peripheral base addresses */
Kojto 90:cb3d968589d8 5990 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
Kojto 90:cb3d968589d8 5991 /** Array initializer of PORT peripheral base pointers */
Kojto 90:cb3d968589d8 5992 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
Kojto 90:cb3d968589d8 5993 /** Interrupt vectors for the PORT peripheral type */
Kojto 90:cb3d968589d8 5994 #define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTCD_IRQn, PORTCD_IRQn, NotAvail_IRQn }
Kojto 90:cb3d968589d8 5995
Kojto 90:cb3d968589d8 5996 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 5997 -- PORT - Register accessor macros
Kojto 90:cb3d968589d8 5998 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 5999
Kojto 90:cb3d968589d8 6000 /*!
Kojto 90:cb3d968589d8 6001 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
Kojto 90:cb3d968589d8 6002 * @{
Kojto 90:cb3d968589d8 6003 */
Kojto 90:cb3d968589d8 6004
Kojto 90:cb3d968589d8 6005
Kojto 90:cb3d968589d8 6006 /* PORT - Register instance definitions */
Kojto 90:cb3d968589d8 6007 /* PORTA */
Kojto 90:cb3d968589d8 6008 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
Kojto 90:cb3d968589d8 6009 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
Kojto 90:cb3d968589d8 6010 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
Kojto 90:cb3d968589d8 6011 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
Kojto 90:cb3d968589d8 6012 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
Kojto 90:cb3d968589d8 6013 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
Kojto 90:cb3d968589d8 6014 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
Kojto 90:cb3d968589d8 6015 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
Kojto 90:cb3d968589d8 6016 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
Kojto 90:cb3d968589d8 6017 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
Kojto 90:cb3d968589d8 6018 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
Kojto 90:cb3d968589d8 6019 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
Kojto 90:cb3d968589d8 6020 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
Kojto 90:cb3d968589d8 6021 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
Kojto 90:cb3d968589d8 6022 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
Kojto 90:cb3d968589d8 6023 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
Kojto 90:cb3d968589d8 6024 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
Kojto 90:cb3d968589d8 6025 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
Kojto 90:cb3d968589d8 6026 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
Kojto 90:cb3d968589d8 6027 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
Kojto 90:cb3d968589d8 6028 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
Kojto 90:cb3d968589d8 6029 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
Kojto 90:cb3d968589d8 6030 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
Kojto 90:cb3d968589d8 6031 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
Kojto 90:cb3d968589d8 6032 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
Kojto 90:cb3d968589d8 6033 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
Kojto 90:cb3d968589d8 6034 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
Kojto 90:cb3d968589d8 6035 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
Kojto 90:cb3d968589d8 6036 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
Kojto 90:cb3d968589d8 6037 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
Kojto 90:cb3d968589d8 6038 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
Kojto 90:cb3d968589d8 6039 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
Kojto 90:cb3d968589d8 6040 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
Kojto 90:cb3d968589d8 6041 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
Kojto 90:cb3d968589d8 6042 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
Kojto 90:cb3d968589d8 6043 /* PORTB */
Kojto 90:cb3d968589d8 6044 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
Kojto 90:cb3d968589d8 6045 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
Kojto 90:cb3d968589d8 6046 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
Kojto 90:cb3d968589d8 6047 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
Kojto 90:cb3d968589d8 6048 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
Kojto 90:cb3d968589d8 6049 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
Kojto 90:cb3d968589d8 6050 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
Kojto 90:cb3d968589d8 6051 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
Kojto 90:cb3d968589d8 6052 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
Kojto 90:cb3d968589d8 6053 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
Kojto 90:cb3d968589d8 6054 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
Kojto 90:cb3d968589d8 6055 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
Kojto 90:cb3d968589d8 6056 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
Kojto 90:cb3d968589d8 6057 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
Kojto 90:cb3d968589d8 6058 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
Kojto 90:cb3d968589d8 6059 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
Kojto 90:cb3d968589d8 6060 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
Kojto 90:cb3d968589d8 6061 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
Kojto 90:cb3d968589d8 6062 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
Kojto 90:cb3d968589d8 6063 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
Kojto 90:cb3d968589d8 6064 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
Kojto 90:cb3d968589d8 6065 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
Kojto 90:cb3d968589d8 6066 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
Kojto 90:cb3d968589d8 6067 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
Kojto 90:cb3d968589d8 6068 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
Kojto 90:cb3d968589d8 6069 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
Kojto 90:cb3d968589d8 6070 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
Kojto 90:cb3d968589d8 6071 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
Kojto 90:cb3d968589d8 6072 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
Kojto 90:cb3d968589d8 6073 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
Kojto 90:cb3d968589d8 6074 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
Kojto 90:cb3d968589d8 6075 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
Kojto 90:cb3d968589d8 6076 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
Kojto 90:cb3d968589d8 6077 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
Kojto 90:cb3d968589d8 6078 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
Kojto 90:cb3d968589d8 6079 /* PORTC */
Kojto 90:cb3d968589d8 6080 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
Kojto 90:cb3d968589d8 6081 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
Kojto 90:cb3d968589d8 6082 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
Kojto 90:cb3d968589d8 6083 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
Kojto 90:cb3d968589d8 6084 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
Kojto 90:cb3d968589d8 6085 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
Kojto 90:cb3d968589d8 6086 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
Kojto 90:cb3d968589d8 6087 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
Kojto 90:cb3d968589d8 6088 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
Kojto 90:cb3d968589d8 6089 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
Kojto 90:cb3d968589d8 6090 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
Kojto 90:cb3d968589d8 6091 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
Kojto 90:cb3d968589d8 6092 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
Kojto 90:cb3d968589d8 6093 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
Kojto 90:cb3d968589d8 6094 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
Kojto 90:cb3d968589d8 6095 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
Kojto 90:cb3d968589d8 6096 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
Kojto 90:cb3d968589d8 6097 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
Kojto 90:cb3d968589d8 6098 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
Kojto 90:cb3d968589d8 6099 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
Kojto 90:cb3d968589d8 6100 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
Kojto 90:cb3d968589d8 6101 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
Kojto 90:cb3d968589d8 6102 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
Kojto 90:cb3d968589d8 6103 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
Kojto 90:cb3d968589d8 6104 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
Kojto 90:cb3d968589d8 6105 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
Kojto 90:cb3d968589d8 6106 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
Kojto 90:cb3d968589d8 6107 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
Kojto 90:cb3d968589d8 6108 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
Kojto 90:cb3d968589d8 6109 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
Kojto 90:cb3d968589d8 6110 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
Kojto 90:cb3d968589d8 6111 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
Kojto 90:cb3d968589d8 6112 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
Kojto 90:cb3d968589d8 6113 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
Kojto 90:cb3d968589d8 6114 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
Kojto 90:cb3d968589d8 6115 /* PORTD */
Kojto 90:cb3d968589d8 6116 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
Kojto 90:cb3d968589d8 6117 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
Kojto 90:cb3d968589d8 6118 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
Kojto 90:cb3d968589d8 6119 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
Kojto 90:cb3d968589d8 6120 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
Kojto 90:cb3d968589d8 6121 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
Kojto 90:cb3d968589d8 6122 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
Kojto 90:cb3d968589d8 6123 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
Kojto 90:cb3d968589d8 6124 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
Kojto 90:cb3d968589d8 6125 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
Kojto 90:cb3d968589d8 6126 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
Kojto 90:cb3d968589d8 6127 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
Kojto 90:cb3d968589d8 6128 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
Kojto 90:cb3d968589d8 6129 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
Kojto 90:cb3d968589d8 6130 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
Kojto 90:cb3d968589d8 6131 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
Kojto 90:cb3d968589d8 6132 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
Kojto 90:cb3d968589d8 6133 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
Kojto 90:cb3d968589d8 6134 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
Kojto 90:cb3d968589d8 6135 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
Kojto 90:cb3d968589d8 6136 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
Kojto 90:cb3d968589d8 6137 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
Kojto 90:cb3d968589d8 6138 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
Kojto 90:cb3d968589d8 6139 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
Kojto 90:cb3d968589d8 6140 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
Kojto 90:cb3d968589d8 6141 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
Kojto 90:cb3d968589d8 6142 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
Kojto 90:cb3d968589d8 6143 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
Kojto 90:cb3d968589d8 6144 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
Kojto 90:cb3d968589d8 6145 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
Kojto 90:cb3d968589d8 6146 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
Kojto 90:cb3d968589d8 6147 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
Kojto 90:cb3d968589d8 6148 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
Kojto 90:cb3d968589d8 6149 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
Kojto 90:cb3d968589d8 6150 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
Kojto 90:cb3d968589d8 6151 /* PORTE */
Kojto 90:cb3d968589d8 6152 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
Kojto 90:cb3d968589d8 6153 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
Kojto 90:cb3d968589d8 6154 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
Kojto 90:cb3d968589d8 6155 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
Kojto 90:cb3d968589d8 6156 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
Kojto 90:cb3d968589d8 6157 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
Kojto 90:cb3d968589d8 6158 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
Kojto 90:cb3d968589d8 6159 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
Kojto 90:cb3d968589d8 6160 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
Kojto 90:cb3d968589d8 6161 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
Kojto 90:cb3d968589d8 6162 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
Kojto 90:cb3d968589d8 6163 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
Kojto 90:cb3d968589d8 6164 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
Kojto 90:cb3d968589d8 6165 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
Kojto 90:cb3d968589d8 6166 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
Kojto 90:cb3d968589d8 6167 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
Kojto 90:cb3d968589d8 6168 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
Kojto 90:cb3d968589d8 6169 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
Kojto 90:cb3d968589d8 6170 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
Kojto 90:cb3d968589d8 6171 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
Kojto 90:cb3d968589d8 6172 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
Kojto 90:cb3d968589d8 6173 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
Kojto 90:cb3d968589d8 6174 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
Kojto 90:cb3d968589d8 6175 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
Kojto 90:cb3d968589d8 6176 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
Kojto 90:cb3d968589d8 6177 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
Kojto 90:cb3d968589d8 6178 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
Kojto 90:cb3d968589d8 6179 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
Kojto 90:cb3d968589d8 6180 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
Kojto 90:cb3d968589d8 6181 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
Kojto 90:cb3d968589d8 6182 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
Kojto 90:cb3d968589d8 6183 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
Kojto 90:cb3d968589d8 6184 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
Kojto 90:cb3d968589d8 6185 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
Kojto 90:cb3d968589d8 6186 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
Kojto 90:cb3d968589d8 6187
Kojto 90:cb3d968589d8 6188 /* PORT - Register array accessors */
Kojto 90:cb3d968589d8 6189 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
Kojto 90:cb3d968589d8 6190 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
Kojto 90:cb3d968589d8 6191 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
Kojto 90:cb3d968589d8 6192 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
Kojto 90:cb3d968589d8 6193 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
Kojto 90:cb3d968589d8 6194
Kojto 90:cb3d968589d8 6195 /*!
Kojto 90:cb3d968589d8 6196 * @}
Kojto 90:cb3d968589d8 6197 */ /* end of group PORT_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6198
Kojto 90:cb3d968589d8 6199
Kojto 90:cb3d968589d8 6200 /*!
Kojto 90:cb3d968589d8 6201 * @}
Kojto 90:cb3d968589d8 6202 */ /* end of group PORT_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 6203
Kojto 90:cb3d968589d8 6204
Kojto 90:cb3d968589d8 6205 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6206 -- RCM Peripheral Access Layer
Kojto 90:cb3d968589d8 6207 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6208
Kojto 90:cb3d968589d8 6209 /*!
Kojto 90:cb3d968589d8 6210 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
Kojto 90:cb3d968589d8 6211 * @{
Kojto 90:cb3d968589d8 6212 */
Kojto 90:cb3d968589d8 6213
Kojto 90:cb3d968589d8 6214 /** RCM - Register Layout Typedef */
Kojto 90:cb3d968589d8 6215 typedef struct {
Kojto 90:cb3d968589d8 6216 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
Kojto 90:cb3d968589d8 6217 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
Kojto 90:cb3d968589d8 6218 uint8_t RESERVED_0[2];
Kojto 90:cb3d968589d8 6219 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
Kojto 90:cb3d968589d8 6220 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
Kojto 90:cb3d968589d8 6221 __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
Kojto 90:cb3d968589d8 6222 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */
Kojto 90:cb3d968589d8 6223 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
Kojto 90:cb3d968589d8 6224 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
Kojto 90:cb3d968589d8 6225 } RCM_Type, *RCM_MemMapPtr;
Kojto 90:cb3d968589d8 6226
Kojto 90:cb3d968589d8 6227 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6228 -- RCM - Register accessor macros
Kojto 90:cb3d968589d8 6229 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6230
Kojto 90:cb3d968589d8 6231 /*!
Kojto 90:cb3d968589d8 6232 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
Kojto 90:cb3d968589d8 6233 * @{
Kojto 90:cb3d968589d8 6234 */
Kojto 90:cb3d968589d8 6235
Kojto 90:cb3d968589d8 6236
Kojto 90:cb3d968589d8 6237 /* RCM - Register accessors */
Kojto 90:cb3d968589d8 6238 #define RCM_SRS0_REG(base) ((base)->SRS0)
Kojto 90:cb3d968589d8 6239 #define RCM_SRS1_REG(base) ((base)->SRS1)
Kojto 90:cb3d968589d8 6240 #define RCM_RPFC_REG(base) ((base)->RPFC)
Kojto 90:cb3d968589d8 6241 #define RCM_RPFW_REG(base) ((base)->RPFW)
Kojto 90:cb3d968589d8 6242 #define RCM_FM_REG(base) ((base)->FM)
Kojto 90:cb3d968589d8 6243 #define RCM_MR_REG(base) ((base)->MR)
Kojto 90:cb3d968589d8 6244 #define RCM_SSRS0_REG(base) ((base)->SSRS0)
Kojto 90:cb3d968589d8 6245 #define RCM_SSRS1_REG(base) ((base)->SSRS1)
Kojto 90:cb3d968589d8 6246
Kojto 90:cb3d968589d8 6247 /*!
Kojto 90:cb3d968589d8 6248 * @}
Kojto 90:cb3d968589d8 6249 */ /* end of group RCM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6250
Kojto 90:cb3d968589d8 6251
Kojto 90:cb3d968589d8 6252 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6253 -- RCM Register Masks
Kojto 90:cb3d968589d8 6254 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6255
Kojto 90:cb3d968589d8 6256 /*!
Kojto 90:cb3d968589d8 6257 * @addtogroup RCM_Register_Masks RCM Register Masks
Kojto 90:cb3d968589d8 6258 * @{
Kojto 90:cb3d968589d8 6259 */
Kojto 90:cb3d968589d8 6260
Kojto 90:cb3d968589d8 6261 /* SRS0 Bit Fields */
Kojto 90:cb3d968589d8 6262 #define RCM_SRS0_WAKEUP_MASK 0x1u
Kojto 90:cb3d968589d8 6263 #define RCM_SRS0_WAKEUP_SHIFT 0
Kojto 90:cb3d968589d8 6264 #define RCM_SRS0_LVD_MASK 0x2u
Kojto 90:cb3d968589d8 6265 #define RCM_SRS0_LVD_SHIFT 1
Kojto 90:cb3d968589d8 6266 #define RCM_SRS0_WDOG_MASK 0x20u
Kojto 90:cb3d968589d8 6267 #define RCM_SRS0_WDOG_SHIFT 5
Kojto 90:cb3d968589d8 6268 #define RCM_SRS0_PIN_MASK 0x40u
Kojto 90:cb3d968589d8 6269 #define RCM_SRS0_PIN_SHIFT 6
Kojto 90:cb3d968589d8 6270 #define RCM_SRS0_POR_MASK 0x80u
Kojto 90:cb3d968589d8 6271 #define RCM_SRS0_POR_SHIFT 7
Kojto 90:cb3d968589d8 6272 /* SRS1 Bit Fields */
Kojto 90:cb3d968589d8 6273 #define RCM_SRS1_LOCKUP_MASK 0x2u
Kojto 90:cb3d968589d8 6274 #define RCM_SRS1_LOCKUP_SHIFT 1
Kojto 90:cb3d968589d8 6275 #define RCM_SRS1_SW_MASK 0x4u
Kojto 90:cb3d968589d8 6276 #define RCM_SRS1_SW_SHIFT 2
Kojto 90:cb3d968589d8 6277 #define RCM_SRS1_MDM_AP_MASK 0x8u
Kojto 90:cb3d968589d8 6278 #define RCM_SRS1_MDM_AP_SHIFT 3
Kojto 90:cb3d968589d8 6279 #define RCM_SRS1_SACKERR_MASK 0x20u
Kojto 90:cb3d968589d8 6280 #define RCM_SRS1_SACKERR_SHIFT 5
Kojto 90:cb3d968589d8 6281 /* RPFC Bit Fields */
Kojto 90:cb3d968589d8 6282 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
Kojto 90:cb3d968589d8 6283 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
Kojto 90:cb3d968589d8 6284 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
Kojto 90:cb3d968589d8 6285 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
Kojto 90:cb3d968589d8 6286 #define RCM_RPFC_RSTFLTSS_SHIFT 2
Kojto 90:cb3d968589d8 6287 /* RPFW Bit Fields */
Kojto 90:cb3d968589d8 6288 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
Kojto 90:cb3d968589d8 6289 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
Kojto 90:cb3d968589d8 6290 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
Kojto 90:cb3d968589d8 6291 /* FM Bit Fields */
Kojto 90:cb3d968589d8 6292 #define RCM_FM_FORCEROM_MASK 0x6u
Kojto 90:cb3d968589d8 6293 #define RCM_FM_FORCEROM_SHIFT 1
Kojto 90:cb3d968589d8 6294 #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_FM_FORCEROM_SHIFT))&RCM_FM_FORCEROM_MASK)
Kojto 90:cb3d968589d8 6295 /* MR Bit Fields */
Kojto 90:cb3d968589d8 6296 #define RCM_MR_BOOTROM_MASK 0x6u
Kojto 90:cb3d968589d8 6297 #define RCM_MR_BOOTROM_SHIFT 1
Kojto 90:cb3d968589d8 6298 #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_MR_BOOTROM_SHIFT))&RCM_MR_BOOTROM_MASK)
Kojto 90:cb3d968589d8 6299 /* SSRS0 Bit Fields */
Kojto 90:cb3d968589d8 6300 #define RCM_SSRS0_SWAKEUP_MASK 0x1u
Kojto 90:cb3d968589d8 6301 #define RCM_SSRS0_SWAKEUP_SHIFT 0
Kojto 90:cb3d968589d8 6302 #define RCM_SSRS0_SLVD_MASK 0x2u
Kojto 90:cb3d968589d8 6303 #define RCM_SSRS0_SLVD_SHIFT 1
Kojto 90:cb3d968589d8 6304 #define RCM_SSRS0_SWDOG_MASK 0x20u
Kojto 90:cb3d968589d8 6305 #define RCM_SSRS0_SWDOG_SHIFT 5
Kojto 90:cb3d968589d8 6306 #define RCM_SSRS0_SPIN_MASK 0x40u
Kojto 90:cb3d968589d8 6307 #define RCM_SSRS0_SPIN_SHIFT 6
Kojto 90:cb3d968589d8 6308 #define RCM_SSRS0_SPOR_MASK 0x80u
Kojto 90:cb3d968589d8 6309 #define RCM_SSRS0_SPOR_SHIFT 7
Kojto 90:cb3d968589d8 6310 /* SSRS1 Bit Fields */
Kojto 90:cb3d968589d8 6311 #define RCM_SSRS1_SLOCKUP_MASK 0x2u
Kojto 90:cb3d968589d8 6312 #define RCM_SSRS1_SLOCKUP_SHIFT 1
Kojto 90:cb3d968589d8 6313 #define RCM_SSRS1_SSW_MASK 0x4u
Kojto 90:cb3d968589d8 6314 #define RCM_SSRS1_SSW_SHIFT 2
Kojto 90:cb3d968589d8 6315 #define RCM_SSRS1_SMDM_AP_MASK 0x8u
Kojto 90:cb3d968589d8 6316 #define RCM_SSRS1_SMDM_AP_SHIFT 3
Kojto 90:cb3d968589d8 6317 #define RCM_SSRS1_SSACKERR_MASK 0x20u
Kojto 90:cb3d968589d8 6318 #define RCM_SSRS1_SSACKERR_SHIFT 5
Kojto 90:cb3d968589d8 6319
Kojto 90:cb3d968589d8 6320 /*!
Kojto 90:cb3d968589d8 6321 * @}
Kojto 90:cb3d968589d8 6322 */ /* end of group RCM_Register_Masks */
Kojto 90:cb3d968589d8 6323
Kojto 90:cb3d968589d8 6324
Kojto 90:cb3d968589d8 6325 /* RCM - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 6326 /** Peripheral RCM base address */
Kojto 90:cb3d968589d8 6327 #define RCM_BASE (0x4007F000u)
Kojto 90:cb3d968589d8 6328 /** Peripheral RCM base pointer */
Kojto 90:cb3d968589d8 6329 #define RCM ((RCM_Type *)RCM_BASE)
Kojto 90:cb3d968589d8 6330 #define RCM_BASE_PTR (RCM)
Kojto 90:cb3d968589d8 6331 /** Array initializer of RCM peripheral base addresses */
Kojto 90:cb3d968589d8 6332 #define RCM_BASE_ADDRS { RCM_BASE }
Kojto 90:cb3d968589d8 6333 /** Array initializer of RCM peripheral base pointers */
Kojto 90:cb3d968589d8 6334 #define RCM_BASE_PTRS { RCM }
Kojto 90:cb3d968589d8 6335
Kojto 90:cb3d968589d8 6336 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6337 -- RCM - Register accessor macros
Kojto 90:cb3d968589d8 6338 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6339
Kojto 90:cb3d968589d8 6340 /*!
Kojto 90:cb3d968589d8 6341 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
Kojto 90:cb3d968589d8 6342 * @{
Kojto 90:cb3d968589d8 6343 */
Kojto 90:cb3d968589d8 6344
Kojto 90:cb3d968589d8 6345
Kojto 90:cb3d968589d8 6346 /* RCM - Register instance definitions */
Kojto 90:cb3d968589d8 6347 /* RCM */
Kojto 90:cb3d968589d8 6348 #define RCM_SRS0 RCM_SRS0_REG(RCM)
Kojto 90:cb3d968589d8 6349 #define RCM_SRS1 RCM_SRS1_REG(RCM)
Kojto 90:cb3d968589d8 6350 #define RCM_RPFC RCM_RPFC_REG(RCM)
Kojto 90:cb3d968589d8 6351 #define RCM_RPFW RCM_RPFW_REG(RCM)
Kojto 90:cb3d968589d8 6352 #define RCM_FM RCM_FM_REG(RCM)
Kojto 90:cb3d968589d8 6353 #define RCM_MR RCM_MR_REG(RCM)
Kojto 90:cb3d968589d8 6354 #define RCM_SSRS0 RCM_SSRS0_REG(RCM)
Kojto 90:cb3d968589d8 6355 #define RCM_SSRS1 RCM_SSRS1_REG(RCM)
Kojto 90:cb3d968589d8 6356
Kojto 90:cb3d968589d8 6357 /*!
Kojto 90:cb3d968589d8 6358 * @}
Kojto 90:cb3d968589d8 6359 */ /* end of group RCM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6360
Kojto 90:cb3d968589d8 6361
Kojto 90:cb3d968589d8 6362 /*!
Kojto 90:cb3d968589d8 6363 * @}
Kojto 90:cb3d968589d8 6364 */ /* end of group RCM_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 6365
Kojto 90:cb3d968589d8 6366
Kojto 90:cb3d968589d8 6367 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6368 -- RFSYS Peripheral Access Layer
Kojto 90:cb3d968589d8 6369 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6370
Kojto 90:cb3d968589d8 6371 /*!
Kojto 90:cb3d968589d8 6372 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
Kojto 90:cb3d968589d8 6373 * @{
Kojto 90:cb3d968589d8 6374 */
Kojto 90:cb3d968589d8 6375
Kojto 90:cb3d968589d8 6376 /** RFSYS - Register Layout Typedef */
Kojto 90:cb3d968589d8 6377 typedef struct {
Kojto 90:cb3d968589d8 6378 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
Kojto 90:cb3d968589d8 6379 } RFSYS_Type, *RFSYS_MemMapPtr;
Kojto 90:cb3d968589d8 6380
Kojto 90:cb3d968589d8 6381 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6382 -- RFSYS - Register accessor macros
Kojto 90:cb3d968589d8 6383 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6384
Kojto 90:cb3d968589d8 6385 /*!
Kojto 90:cb3d968589d8 6386 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
Kojto 90:cb3d968589d8 6387 * @{
Kojto 90:cb3d968589d8 6388 */
Kojto 90:cb3d968589d8 6389
Kojto 90:cb3d968589d8 6390
Kojto 90:cb3d968589d8 6391 /* RFSYS - Register accessors */
Kojto 90:cb3d968589d8 6392 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
Kojto 90:cb3d968589d8 6393
Kojto 90:cb3d968589d8 6394 /*!
Kojto 90:cb3d968589d8 6395 * @}
Kojto 90:cb3d968589d8 6396 */ /* end of group RFSYS_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6397
Kojto 90:cb3d968589d8 6398
Kojto 90:cb3d968589d8 6399 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6400 -- RFSYS Register Masks
Kojto 90:cb3d968589d8 6401 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6402
Kojto 90:cb3d968589d8 6403 /*!
Kojto 90:cb3d968589d8 6404 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
Kojto 90:cb3d968589d8 6405 * @{
Kojto 90:cb3d968589d8 6406 */
Kojto 90:cb3d968589d8 6407
Kojto 90:cb3d968589d8 6408 /* REG Bit Fields */
Kojto 90:cb3d968589d8 6409 #define RFSYS_REG_LL_MASK 0xFFu
Kojto 90:cb3d968589d8 6410 #define RFSYS_REG_LL_SHIFT 0
Kojto 90:cb3d968589d8 6411 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
Kojto 90:cb3d968589d8 6412 #define RFSYS_REG_LH_MASK 0xFF00u
Kojto 90:cb3d968589d8 6413 #define RFSYS_REG_LH_SHIFT 8
Kojto 90:cb3d968589d8 6414 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
Kojto 90:cb3d968589d8 6415 #define RFSYS_REG_HL_MASK 0xFF0000u
Kojto 90:cb3d968589d8 6416 #define RFSYS_REG_HL_SHIFT 16
Kojto 90:cb3d968589d8 6417 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
Kojto 90:cb3d968589d8 6418 #define RFSYS_REG_HH_MASK 0xFF000000u
Kojto 90:cb3d968589d8 6419 #define RFSYS_REG_HH_SHIFT 24
Kojto 90:cb3d968589d8 6420 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
Kojto 90:cb3d968589d8 6421
Kojto 90:cb3d968589d8 6422 /*!
Kojto 90:cb3d968589d8 6423 * @}
Kojto 90:cb3d968589d8 6424 */ /* end of group RFSYS_Register_Masks */
Kojto 90:cb3d968589d8 6425
Kojto 90:cb3d968589d8 6426
Kojto 90:cb3d968589d8 6427 /* RFSYS - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 6428 /** Peripheral RFSYS base address */
Kojto 90:cb3d968589d8 6429 #define RFSYS_BASE (0x40041000u)
Kojto 90:cb3d968589d8 6430 /** Peripheral RFSYS base pointer */
Kojto 90:cb3d968589d8 6431 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
Kojto 90:cb3d968589d8 6432 #define RFSYS_BASE_PTR (RFSYS)
Kojto 90:cb3d968589d8 6433 /** Array initializer of RFSYS peripheral base addresses */
Kojto 90:cb3d968589d8 6434 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
Kojto 90:cb3d968589d8 6435 /** Array initializer of RFSYS peripheral base pointers */
Kojto 90:cb3d968589d8 6436 #define RFSYS_BASE_PTRS { RFSYS }
Kojto 90:cb3d968589d8 6437
Kojto 90:cb3d968589d8 6438 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6439 -- RFSYS - Register accessor macros
Kojto 90:cb3d968589d8 6440 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6441
Kojto 90:cb3d968589d8 6442 /*!
Kojto 90:cb3d968589d8 6443 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
Kojto 90:cb3d968589d8 6444 * @{
Kojto 90:cb3d968589d8 6445 */
Kojto 90:cb3d968589d8 6446
Kojto 90:cb3d968589d8 6447
Kojto 90:cb3d968589d8 6448 /* RFSYS - Register instance definitions */
Kojto 90:cb3d968589d8 6449 /* RFSYS */
Kojto 90:cb3d968589d8 6450 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
Kojto 90:cb3d968589d8 6451 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
Kojto 90:cb3d968589d8 6452 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
Kojto 90:cb3d968589d8 6453 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
Kojto 90:cb3d968589d8 6454 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
Kojto 90:cb3d968589d8 6455 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
Kojto 90:cb3d968589d8 6456 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
Kojto 90:cb3d968589d8 6457 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
Kojto 90:cb3d968589d8 6458
Kojto 90:cb3d968589d8 6459 /* RFSYS - Register array accessors */
Kojto 90:cb3d968589d8 6460 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
Kojto 90:cb3d968589d8 6461
Kojto 90:cb3d968589d8 6462 /*!
Kojto 90:cb3d968589d8 6463 * @}
Kojto 90:cb3d968589d8 6464 */ /* end of group RFSYS_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6465
Kojto 90:cb3d968589d8 6466
Kojto 90:cb3d968589d8 6467 /*!
Kojto 90:cb3d968589d8 6468 * @}
Kojto 90:cb3d968589d8 6469 */ /* end of group RFSYS_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 6470
Kojto 90:cb3d968589d8 6471
Kojto 90:cb3d968589d8 6472 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6473 -- ROM Peripheral Access Layer
Kojto 90:cb3d968589d8 6474 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6475
Kojto 90:cb3d968589d8 6476 /*!
Kojto 90:cb3d968589d8 6477 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
Kojto 90:cb3d968589d8 6478 * @{
Kojto 90:cb3d968589d8 6479 */
Kojto 90:cb3d968589d8 6480
Kojto 90:cb3d968589d8 6481 /** ROM - Register Layout Typedef */
Kojto 90:cb3d968589d8 6482 typedef struct {
Kojto 90:cb3d968589d8 6483 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
Kojto 90:cb3d968589d8 6484 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
Kojto 90:cb3d968589d8 6485 uint8_t RESERVED_0[4028];
Kojto 90:cb3d968589d8 6486 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
Kojto 90:cb3d968589d8 6487 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
Kojto 90:cb3d968589d8 6488 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
Kojto 90:cb3d968589d8 6489 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
Kojto 90:cb3d968589d8 6490 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
Kojto 90:cb3d968589d8 6491 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
Kojto 90:cb3d968589d8 6492 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
Kojto 90:cb3d968589d8 6493 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
Kojto 90:cb3d968589d8 6494 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
Kojto 90:cb3d968589d8 6495 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
Kojto 90:cb3d968589d8 6496 } ROM_Type, *ROM_MemMapPtr;
Kojto 90:cb3d968589d8 6497
Kojto 90:cb3d968589d8 6498 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6499 -- ROM - Register accessor macros
Kojto 90:cb3d968589d8 6500 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6501
Kojto 90:cb3d968589d8 6502 /*!
Kojto 90:cb3d968589d8 6503 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
Kojto 90:cb3d968589d8 6504 * @{
Kojto 90:cb3d968589d8 6505 */
Kojto 90:cb3d968589d8 6506
Kojto 90:cb3d968589d8 6507
Kojto 90:cb3d968589d8 6508 /* ROM - Register accessors */
Kojto 90:cb3d968589d8 6509 #define ROM_ENTRY_REG(base,index) ((base)->ENTRY[index])
Kojto 90:cb3d968589d8 6510 #define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK)
Kojto 90:cb3d968589d8 6511 #define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS)
Kojto 90:cb3d968589d8 6512 #define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4)
Kojto 90:cb3d968589d8 6513 #define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5)
Kojto 90:cb3d968589d8 6514 #define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6)
Kojto 90:cb3d968589d8 6515 #define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7)
Kojto 90:cb3d968589d8 6516 #define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0)
Kojto 90:cb3d968589d8 6517 #define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1)
Kojto 90:cb3d968589d8 6518 #define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2)
Kojto 90:cb3d968589d8 6519 #define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3)
Kojto 90:cb3d968589d8 6520 #define ROM_COMPID_REG(base,index) ((base)->COMPID[index])
Kojto 90:cb3d968589d8 6521
Kojto 90:cb3d968589d8 6522 /*!
Kojto 90:cb3d968589d8 6523 * @}
Kojto 90:cb3d968589d8 6524 */ /* end of group ROM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6525
Kojto 90:cb3d968589d8 6526
Kojto 90:cb3d968589d8 6527 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6528 -- ROM Register Masks
Kojto 90:cb3d968589d8 6529 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6530
Kojto 90:cb3d968589d8 6531 /*!
Kojto 90:cb3d968589d8 6532 * @addtogroup ROM_Register_Masks ROM Register Masks
Kojto 90:cb3d968589d8 6533 * @{
Kojto 90:cb3d968589d8 6534 */
Kojto 90:cb3d968589d8 6535
Kojto 90:cb3d968589d8 6536 /* ENTRY Bit Fields */
Kojto 90:cb3d968589d8 6537 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6538 #define ROM_ENTRY_ENTRY_SHIFT 0
Kojto 90:cb3d968589d8 6539 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
Kojto 90:cb3d968589d8 6540 /* TABLEMARK Bit Fields */
Kojto 90:cb3d968589d8 6541 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6542 #define ROM_TABLEMARK_MARK_SHIFT 0
Kojto 90:cb3d968589d8 6543 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
Kojto 90:cb3d968589d8 6544 /* SYSACCESS Bit Fields */
Kojto 90:cb3d968589d8 6545 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6546 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
Kojto 90:cb3d968589d8 6547 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
Kojto 90:cb3d968589d8 6548 /* PERIPHID4 Bit Fields */
Kojto 90:cb3d968589d8 6549 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6550 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
Kojto 90:cb3d968589d8 6551 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
Kojto 90:cb3d968589d8 6552 /* PERIPHID5 Bit Fields */
Kojto 90:cb3d968589d8 6553 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6554 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
Kojto 90:cb3d968589d8 6555 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
Kojto 90:cb3d968589d8 6556 /* PERIPHID6 Bit Fields */
Kojto 90:cb3d968589d8 6557 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6558 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
Kojto 90:cb3d968589d8 6559 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
Kojto 90:cb3d968589d8 6560 /* PERIPHID7 Bit Fields */
Kojto 90:cb3d968589d8 6561 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6562 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
Kojto 90:cb3d968589d8 6563 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
Kojto 90:cb3d968589d8 6564 /* PERIPHID0 Bit Fields */
Kojto 90:cb3d968589d8 6565 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6566 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
Kojto 90:cb3d968589d8 6567 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
Kojto 90:cb3d968589d8 6568 /* PERIPHID1 Bit Fields */
Kojto 90:cb3d968589d8 6569 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6570 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
Kojto 90:cb3d968589d8 6571 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
Kojto 90:cb3d968589d8 6572 /* PERIPHID2 Bit Fields */
Kojto 90:cb3d968589d8 6573 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6574 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
Kojto 90:cb3d968589d8 6575 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
Kojto 90:cb3d968589d8 6576 /* PERIPHID3 Bit Fields */
Kojto 90:cb3d968589d8 6577 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6578 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
Kojto 90:cb3d968589d8 6579 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
Kojto 90:cb3d968589d8 6580 /* COMPID Bit Fields */
Kojto 90:cb3d968589d8 6581 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6582 #define ROM_COMPID_COMPID_SHIFT 0
Kojto 90:cb3d968589d8 6583 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
Kojto 90:cb3d968589d8 6584
Kojto 90:cb3d968589d8 6585 /*!
Kojto 90:cb3d968589d8 6586 * @}
Kojto 90:cb3d968589d8 6587 */ /* end of group ROM_Register_Masks */
Kojto 90:cb3d968589d8 6588
Kojto 90:cb3d968589d8 6589
Kojto 90:cb3d968589d8 6590 /* ROM - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 6591 /** Peripheral ROM base address */
Kojto 90:cb3d968589d8 6592 #define ROM_BASE (0xF0002000u)
Kojto 90:cb3d968589d8 6593 /** Peripheral ROM base pointer */
Kojto 90:cb3d968589d8 6594 #define ROM ((ROM_Type *)ROM_BASE)
Kojto 90:cb3d968589d8 6595 #define ROM_BASE_PTR (ROM)
Kojto 90:cb3d968589d8 6596 /** Array initializer of ROM peripheral base addresses */
Kojto 90:cb3d968589d8 6597 #define ROM_BASE_ADDRS { ROM_BASE }
Kojto 90:cb3d968589d8 6598 /** Array initializer of ROM peripheral base pointers */
Kojto 90:cb3d968589d8 6599 #define ROM_BASE_PTRS { ROM }
Kojto 90:cb3d968589d8 6600
Kojto 90:cb3d968589d8 6601 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6602 -- ROM - Register accessor macros
Kojto 90:cb3d968589d8 6603 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6604
Kojto 90:cb3d968589d8 6605 /*!
Kojto 90:cb3d968589d8 6606 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
Kojto 90:cb3d968589d8 6607 * @{
Kojto 90:cb3d968589d8 6608 */
Kojto 90:cb3d968589d8 6609
Kojto 90:cb3d968589d8 6610
Kojto 90:cb3d968589d8 6611 /* ROM - Register instance definitions */
Kojto 90:cb3d968589d8 6612 /* ROM */
Kojto 90:cb3d968589d8 6613 #define ROM_ENTRY0 ROM_ENTRY_REG(ROM,0)
Kojto 90:cb3d968589d8 6614 #define ROM_ENTRY1 ROM_ENTRY_REG(ROM,1)
Kojto 90:cb3d968589d8 6615 #define ROM_ENTRY2 ROM_ENTRY_REG(ROM,2)
Kojto 90:cb3d968589d8 6616 #define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM)
Kojto 90:cb3d968589d8 6617 #define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM)
Kojto 90:cb3d968589d8 6618 #define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM)
Kojto 90:cb3d968589d8 6619 #define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM)
Kojto 90:cb3d968589d8 6620 #define ROM_PERIPHID6 ROM_PERIPHID6_REG(ROM)
Kojto 90:cb3d968589d8 6621 #define ROM_PERIPHID7 ROM_PERIPHID7_REG(ROM)
Kojto 90:cb3d968589d8 6622 #define ROM_PERIPHID0 ROM_PERIPHID0_REG(ROM)
Kojto 90:cb3d968589d8 6623 #define ROM_PERIPHID1 ROM_PERIPHID1_REG(ROM)
Kojto 90:cb3d968589d8 6624 #define ROM_PERIPHID2 ROM_PERIPHID2_REG(ROM)
Kojto 90:cb3d968589d8 6625 #define ROM_PERIPHID3 ROM_PERIPHID3_REG(ROM)
Kojto 90:cb3d968589d8 6626 #define ROM_COMPID0 ROM_COMPID_REG(ROM,0)
Kojto 90:cb3d968589d8 6627 #define ROM_COMPID1 ROM_COMPID_REG(ROM,1)
Kojto 90:cb3d968589d8 6628 #define ROM_COMPID2 ROM_COMPID_REG(ROM,2)
Kojto 90:cb3d968589d8 6629 #define ROM_COMPID3 ROM_COMPID_REG(ROM,3)
Kojto 90:cb3d968589d8 6630
Kojto 90:cb3d968589d8 6631 /* ROM - Register array accessors */
Kojto 90:cb3d968589d8 6632 #define ROM_ENTRY(index) ROM_ENTRY_REG(ROM,index)
Kojto 90:cb3d968589d8 6633 #define ROM_COMPID(index) ROM_COMPID_REG(ROM,index)
Kojto 90:cb3d968589d8 6634
Kojto 90:cb3d968589d8 6635 /*!
Kojto 90:cb3d968589d8 6636 * @}
Kojto 90:cb3d968589d8 6637 */ /* end of group ROM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6638
Kojto 90:cb3d968589d8 6639
Kojto 90:cb3d968589d8 6640 /*!
Kojto 90:cb3d968589d8 6641 * @}
Kojto 90:cb3d968589d8 6642 */ /* end of group ROM_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 6643
Kojto 90:cb3d968589d8 6644
Kojto 90:cb3d968589d8 6645 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6646 -- RTC Peripheral Access Layer
Kojto 90:cb3d968589d8 6647 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6648
Kojto 90:cb3d968589d8 6649 /*!
Kojto 90:cb3d968589d8 6650 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
Kojto 90:cb3d968589d8 6651 * @{
Kojto 90:cb3d968589d8 6652 */
Kojto 90:cb3d968589d8 6653
Kojto 90:cb3d968589d8 6654 /** RTC - Register Layout Typedef */
Kojto 90:cb3d968589d8 6655 typedef struct {
Kojto 90:cb3d968589d8 6656 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
Kojto 90:cb3d968589d8 6657 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
Kojto 90:cb3d968589d8 6658 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
Kojto 90:cb3d968589d8 6659 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
Kojto 90:cb3d968589d8 6660 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
Kojto 90:cb3d968589d8 6661 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
Kojto 90:cb3d968589d8 6662 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
Kojto 90:cb3d968589d8 6663 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
Kojto 90:cb3d968589d8 6664 } RTC_Type, *RTC_MemMapPtr;
Kojto 90:cb3d968589d8 6665
Kojto 90:cb3d968589d8 6666 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6667 -- RTC - Register accessor macros
Kojto 90:cb3d968589d8 6668 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6669
Kojto 90:cb3d968589d8 6670 /*!
Kojto 90:cb3d968589d8 6671 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
Kojto 90:cb3d968589d8 6672 * @{
Kojto 90:cb3d968589d8 6673 */
Kojto 90:cb3d968589d8 6674
Kojto 90:cb3d968589d8 6675
Kojto 90:cb3d968589d8 6676 /* RTC - Register accessors */
Kojto 90:cb3d968589d8 6677 #define RTC_TSR_REG(base) ((base)->TSR)
Kojto 90:cb3d968589d8 6678 #define RTC_TPR_REG(base) ((base)->TPR)
Kojto 90:cb3d968589d8 6679 #define RTC_TAR_REG(base) ((base)->TAR)
Kojto 90:cb3d968589d8 6680 #define RTC_TCR_REG(base) ((base)->TCR)
Kojto 90:cb3d968589d8 6681 #define RTC_CR_REG(base) ((base)->CR)
Kojto 90:cb3d968589d8 6682 #define RTC_SR_REG(base) ((base)->SR)
Kojto 90:cb3d968589d8 6683 #define RTC_LR_REG(base) ((base)->LR)
Kojto 90:cb3d968589d8 6684 #define RTC_IER_REG(base) ((base)->IER)
Kojto 90:cb3d968589d8 6685
Kojto 90:cb3d968589d8 6686 /*!
Kojto 90:cb3d968589d8 6687 * @}
Kojto 90:cb3d968589d8 6688 */ /* end of group RTC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6689
Kojto 90:cb3d968589d8 6690
Kojto 90:cb3d968589d8 6691 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6692 -- RTC Register Masks
Kojto 90:cb3d968589d8 6693 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6694
Kojto 90:cb3d968589d8 6695 /*!
Kojto 90:cb3d968589d8 6696 * @addtogroup RTC_Register_Masks RTC Register Masks
Kojto 90:cb3d968589d8 6697 * @{
Kojto 90:cb3d968589d8 6698 */
Kojto 90:cb3d968589d8 6699
Kojto 90:cb3d968589d8 6700 /* TSR Bit Fields */
Kojto 90:cb3d968589d8 6701 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6702 #define RTC_TSR_TSR_SHIFT 0
Kojto 90:cb3d968589d8 6703 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
Kojto 90:cb3d968589d8 6704 /* TPR Bit Fields */
Kojto 90:cb3d968589d8 6705 #define RTC_TPR_TPR_MASK 0xFFFFu
Kojto 90:cb3d968589d8 6706 #define RTC_TPR_TPR_SHIFT 0
Kojto 90:cb3d968589d8 6707 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
Kojto 90:cb3d968589d8 6708 /* TAR Bit Fields */
Kojto 90:cb3d968589d8 6709 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 6710 #define RTC_TAR_TAR_SHIFT 0
Kojto 90:cb3d968589d8 6711 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
Kojto 90:cb3d968589d8 6712 /* TCR Bit Fields */
Kojto 90:cb3d968589d8 6713 #define RTC_TCR_TCR_MASK 0xFFu
Kojto 90:cb3d968589d8 6714 #define RTC_TCR_TCR_SHIFT 0
Kojto 90:cb3d968589d8 6715 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
Kojto 90:cb3d968589d8 6716 #define RTC_TCR_CIR_MASK 0xFF00u
Kojto 90:cb3d968589d8 6717 #define RTC_TCR_CIR_SHIFT 8
Kojto 90:cb3d968589d8 6718 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
Kojto 90:cb3d968589d8 6719 #define RTC_TCR_TCV_MASK 0xFF0000u
Kojto 90:cb3d968589d8 6720 #define RTC_TCR_TCV_SHIFT 16
Kojto 90:cb3d968589d8 6721 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
Kojto 90:cb3d968589d8 6722 #define RTC_TCR_CIC_MASK 0xFF000000u
Kojto 90:cb3d968589d8 6723 #define RTC_TCR_CIC_SHIFT 24
Kojto 90:cb3d968589d8 6724 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
Kojto 90:cb3d968589d8 6725 /* CR Bit Fields */
Kojto 90:cb3d968589d8 6726 #define RTC_CR_SWR_MASK 0x1u
Kojto 90:cb3d968589d8 6727 #define RTC_CR_SWR_SHIFT 0
Kojto 90:cb3d968589d8 6728 #define RTC_CR_WPE_MASK 0x2u
Kojto 90:cb3d968589d8 6729 #define RTC_CR_WPE_SHIFT 1
Kojto 90:cb3d968589d8 6730 #define RTC_CR_SUP_MASK 0x4u
Kojto 90:cb3d968589d8 6731 #define RTC_CR_SUP_SHIFT 2
Kojto 90:cb3d968589d8 6732 #define RTC_CR_UM_MASK 0x8u
Kojto 90:cb3d968589d8 6733 #define RTC_CR_UM_SHIFT 3
Kojto 90:cb3d968589d8 6734 #define RTC_CR_WPS_MASK 0x10u
Kojto 90:cb3d968589d8 6735 #define RTC_CR_WPS_SHIFT 4
Kojto 90:cb3d968589d8 6736 #define RTC_CR_OSCE_MASK 0x100u
Kojto 90:cb3d968589d8 6737 #define RTC_CR_OSCE_SHIFT 8
Kojto 90:cb3d968589d8 6738 #define RTC_CR_CLKO_MASK 0x200u
Kojto 90:cb3d968589d8 6739 #define RTC_CR_CLKO_SHIFT 9
Kojto 90:cb3d968589d8 6740 #define RTC_CR_SC16P_MASK 0x400u
Kojto 90:cb3d968589d8 6741 #define RTC_CR_SC16P_SHIFT 10
Kojto 90:cb3d968589d8 6742 #define RTC_CR_SC8P_MASK 0x800u
Kojto 90:cb3d968589d8 6743 #define RTC_CR_SC8P_SHIFT 11
Kojto 90:cb3d968589d8 6744 #define RTC_CR_SC4P_MASK 0x1000u
Kojto 90:cb3d968589d8 6745 #define RTC_CR_SC4P_SHIFT 12
Kojto 90:cb3d968589d8 6746 #define RTC_CR_SC2P_MASK 0x2000u
Kojto 90:cb3d968589d8 6747 #define RTC_CR_SC2P_SHIFT 13
Kojto 90:cb3d968589d8 6748 /* SR Bit Fields */
Kojto 90:cb3d968589d8 6749 #define RTC_SR_TIF_MASK 0x1u
Kojto 90:cb3d968589d8 6750 #define RTC_SR_TIF_SHIFT 0
Kojto 90:cb3d968589d8 6751 #define RTC_SR_TOF_MASK 0x2u
Kojto 90:cb3d968589d8 6752 #define RTC_SR_TOF_SHIFT 1
Kojto 90:cb3d968589d8 6753 #define RTC_SR_TAF_MASK 0x4u
Kojto 90:cb3d968589d8 6754 #define RTC_SR_TAF_SHIFT 2
Kojto 90:cb3d968589d8 6755 #define RTC_SR_TCE_MASK 0x10u
Kojto 90:cb3d968589d8 6756 #define RTC_SR_TCE_SHIFT 4
Kojto 90:cb3d968589d8 6757 /* LR Bit Fields */
Kojto 90:cb3d968589d8 6758 #define RTC_LR_TCL_MASK 0x8u
Kojto 90:cb3d968589d8 6759 #define RTC_LR_TCL_SHIFT 3
Kojto 90:cb3d968589d8 6760 #define RTC_LR_CRL_MASK 0x10u
Kojto 90:cb3d968589d8 6761 #define RTC_LR_CRL_SHIFT 4
Kojto 90:cb3d968589d8 6762 #define RTC_LR_SRL_MASK 0x20u
Kojto 90:cb3d968589d8 6763 #define RTC_LR_SRL_SHIFT 5
Kojto 90:cb3d968589d8 6764 #define RTC_LR_LRL_MASK 0x40u
Kojto 90:cb3d968589d8 6765 #define RTC_LR_LRL_SHIFT 6
Kojto 90:cb3d968589d8 6766 /* IER Bit Fields */
Kojto 90:cb3d968589d8 6767 #define RTC_IER_TIIE_MASK 0x1u
Kojto 90:cb3d968589d8 6768 #define RTC_IER_TIIE_SHIFT 0
Kojto 90:cb3d968589d8 6769 #define RTC_IER_TOIE_MASK 0x2u
Kojto 90:cb3d968589d8 6770 #define RTC_IER_TOIE_SHIFT 1
Kojto 90:cb3d968589d8 6771 #define RTC_IER_TAIE_MASK 0x4u
Kojto 90:cb3d968589d8 6772 #define RTC_IER_TAIE_SHIFT 2
Kojto 90:cb3d968589d8 6773 #define RTC_IER_TSIE_MASK 0x10u
Kojto 90:cb3d968589d8 6774 #define RTC_IER_TSIE_SHIFT 4
Kojto 90:cb3d968589d8 6775 #define RTC_IER_WPON_MASK 0x80u
Kojto 90:cb3d968589d8 6776 #define RTC_IER_WPON_SHIFT 7
Kojto 90:cb3d968589d8 6777
Kojto 90:cb3d968589d8 6778 /*!
Kojto 90:cb3d968589d8 6779 * @}
Kojto 90:cb3d968589d8 6780 */ /* end of group RTC_Register_Masks */
Kojto 90:cb3d968589d8 6781
Kojto 90:cb3d968589d8 6782
Kojto 90:cb3d968589d8 6783 /* RTC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 6784 /** Peripheral RTC base address */
Kojto 90:cb3d968589d8 6785 #define RTC_BASE (0x4003D000u)
Kojto 90:cb3d968589d8 6786 /** Peripheral RTC base pointer */
Kojto 90:cb3d968589d8 6787 #define RTC ((RTC_Type *)RTC_BASE)
Kojto 90:cb3d968589d8 6788 #define RTC_BASE_PTR (RTC)
Kojto 90:cb3d968589d8 6789 /** Array initializer of RTC peripheral base addresses */
Kojto 90:cb3d968589d8 6790 #define RTC_BASE_ADDRS { RTC_BASE }
Kojto 90:cb3d968589d8 6791 /** Array initializer of RTC peripheral base pointers */
Kojto 90:cb3d968589d8 6792 #define RTC_BASE_PTRS { RTC }
Kojto 90:cb3d968589d8 6793 /** Interrupt vectors for the RTC peripheral type */
Kojto 90:cb3d968589d8 6794 #define RTC_IRQS { RTC_IRQn }
Kojto 90:cb3d968589d8 6795 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
Kojto 90:cb3d968589d8 6796
Kojto 90:cb3d968589d8 6797 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6798 -- RTC - Register accessor macros
Kojto 90:cb3d968589d8 6799 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6800
Kojto 90:cb3d968589d8 6801 /*!
Kojto 90:cb3d968589d8 6802 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
Kojto 90:cb3d968589d8 6803 * @{
Kojto 90:cb3d968589d8 6804 */
Kojto 90:cb3d968589d8 6805
Kojto 90:cb3d968589d8 6806
Kojto 90:cb3d968589d8 6807 /* RTC - Register instance definitions */
Kojto 90:cb3d968589d8 6808 /* RTC */
Kojto 90:cb3d968589d8 6809 #define RTC_TSR RTC_TSR_REG(RTC)
Kojto 90:cb3d968589d8 6810 #define RTC_TPR RTC_TPR_REG(RTC)
Kojto 90:cb3d968589d8 6811 #define RTC_TAR RTC_TAR_REG(RTC)
Kojto 90:cb3d968589d8 6812 #define RTC_TCR RTC_TCR_REG(RTC)
Kojto 90:cb3d968589d8 6813 #define RTC_CR RTC_CR_REG(RTC)
Kojto 90:cb3d968589d8 6814 #define RTC_SR RTC_SR_REG(RTC)
Kojto 90:cb3d968589d8 6815 #define RTC_LR RTC_LR_REG(RTC)
Kojto 90:cb3d968589d8 6816 #define RTC_IER RTC_IER_REG(RTC)
Kojto 90:cb3d968589d8 6817
Kojto 90:cb3d968589d8 6818 /*!
Kojto 90:cb3d968589d8 6819 * @}
Kojto 90:cb3d968589d8 6820 */ /* end of group RTC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6821
Kojto 90:cb3d968589d8 6822
Kojto 90:cb3d968589d8 6823 /*!
Kojto 90:cb3d968589d8 6824 * @}
Kojto 90:cb3d968589d8 6825 */ /* end of group RTC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 6826
Kojto 90:cb3d968589d8 6827
Kojto 90:cb3d968589d8 6828 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6829 -- SIM Peripheral Access Layer
Kojto 90:cb3d968589d8 6830 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6831
Kojto 90:cb3d968589d8 6832 /*!
Kojto 90:cb3d968589d8 6833 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
Kojto 90:cb3d968589d8 6834 * @{
Kojto 90:cb3d968589d8 6835 */
Kojto 90:cb3d968589d8 6836
Kojto 90:cb3d968589d8 6837 /** SIM - Register Layout Typedef */
Kojto 90:cb3d968589d8 6838 typedef struct {
Kojto 90:cb3d968589d8 6839 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
Kojto 90:cb3d968589d8 6840 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
Kojto 90:cb3d968589d8 6841 uint8_t RESERVED_0[4092];
Kojto 90:cb3d968589d8 6842 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
Kojto 90:cb3d968589d8 6843 uint8_t RESERVED_1[4];
Kojto 90:cb3d968589d8 6844 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
Kojto 90:cb3d968589d8 6845 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
Kojto 90:cb3d968589d8 6846 uint8_t RESERVED_2[4];
Kojto 90:cb3d968589d8 6847 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
Kojto 90:cb3d968589d8 6848 uint8_t RESERVED_3[8];
Kojto 90:cb3d968589d8 6849 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
Kojto 90:cb3d968589d8 6850 uint8_t RESERVED_4[12];
Kojto 90:cb3d968589d8 6851 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
Kojto 90:cb3d968589d8 6852 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
Kojto 90:cb3d968589d8 6853 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
Kojto 90:cb3d968589d8 6854 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
Kojto 90:cb3d968589d8 6855 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
Kojto 90:cb3d968589d8 6856 uint8_t RESERVED_5[4];
Kojto 90:cb3d968589d8 6857 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
Kojto 90:cb3d968589d8 6858 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
Kojto 90:cb3d968589d8 6859 uint8_t RESERVED_6[4];
Kojto 90:cb3d968589d8 6860 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
Kojto 90:cb3d968589d8 6861 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
Kojto 90:cb3d968589d8 6862 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
Kojto 90:cb3d968589d8 6863 uint8_t RESERVED_7[156];
Kojto 90:cb3d968589d8 6864 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
Kojto 90:cb3d968589d8 6865 __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
Kojto 90:cb3d968589d8 6866 } SIM_Type, *SIM_MemMapPtr;
Kojto 90:cb3d968589d8 6867
Kojto 90:cb3d968589d8 6868 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6869 -- SIM - Register accessor macros
Kojto 90:cb3d968589d8 6870 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6871
Kojto 90:cb3d968589d8 6872 /*!
Kojto 90:cb3d968589d8 6873 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
Kojto 90:cb3d968589d8 6874 * @{
Kojto 90:cb3d968589d8 6875 */
Kojto 90:cb3d968589d8 6876
Kojto 90:cb3d968589d8 6877
Kojto 90:cb3d968589d8 6878 /* SIM - Register accessors */
Kojto 90:cb3d968589d8 6879 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
Kojto 90:cb3d968589d8 6880 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
Kojto 90:cb3d968589d8 6881 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
Kojto 90:cb3d968589d8 6882 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
Kojto 90:cb3d968589d8 6883 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
Kojto 90:cb3d968589d8 6884 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
Kojto 90:cb3d968589d8 6885 #define SIM_SDID_REG(base) ((base)->SDID)
Kojto 90:cb3d968589d8 6886 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
Kojto 90:cb3d968589d8 6887 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
Kojto 90:cb3d968589d8 6888 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
Kojto 90:cb3d968589d8 6889 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
Kojto 90:cb3d968589d8 6890 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
Kojto 90:cb3d968589d8 6891 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
Kojto 90:cb3d968589d8 6892 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
Kojto 90:cb3d968589d8 6893 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
Kojto 90:cb3d968589d8 6894 #define SIM_UIDML_REG(base) ((base)->UIDML)
Kojto 90:cb3d968589d8 6895 #define SIM_UIDL_REG(base) ((base)->UIDL)
Kojto 90:cb3d968589d8 6896 #define SIM_COPC_REG(base) ((base)->COPC)
Kojto 90:cb3d968589d8 6897 #define SIM_SRVCOP_REG(base) ((base)->SRVCOP)
Kojto 90:cb3d968589d8 6898
Kojto 90:cb3d968589d8 6899 /*!
Kojto 90:cb3d968589d8 6900 * @}
Kojto 90:cb3d968589d8 6901 */ /* end of group SIM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 6902
Kojto 90:cb3d968589d8 6903
Kojto 90:cb3d968589d8 6904 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 6905 -- SIM Register Masks
Kojto 90:cb3d968589d8 6906 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 6907
Kojto 90:cb3d968589d8 6908 /*!
Kojto 90:cb3d968589d8 6909 * @addtogroup SIM_Register_Masks SIM Register Masks
Kojto 90:cb3d968589d8 6910 * @{
Kojto 90:cb3d968589d8 6911 */
Kojto 90:cb3d968589d8 6912
Kojto 90:cb3d968589d8 6913 /* SOPT1 Bit Fields */
Kojto 90:cb3d968589d8 6914 #define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
Kojto 90:cb3d968589d8 6915 #define SIM_SOPT1_OSC32KOUT_SHIFT 16
Kojto 90:cb3d968589d8 6916 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
Kojto 90:cb3d968589d8 6917 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
Kojto 90:cb3d968589d8 6918 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
Kojto 90:cb3d968589d8 6919 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
Kojto 90:cb3d968589d8 6920 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
Kojto 90:cb3d968589d8 6921 #define SIM_SOPT1_USBVSTBY_SHIFT 29
Kojto 90:cb3d968589d8 6922 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
Kojto 90:cb3d968589d8 6923 #define SIM_SOPT1_USBSSTBY_SHIFT 30
Kojto 90:cb3d968589d8 6924 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
Kojto 90:cb3d968589d8 6925 #define SIM_SOPT1_USBREGEN_SHIFT 31
Kojto 90:cb3d968589d8 6926 /* SOPT1CFG Bit Fields */
Kojto 90:cb3d968589d8 6927 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
Kojto 90:cb3d968589d8 6928 #define SIM_SOPT1CFG_URWE_SHIFT 24
Kojto 90:cb3d968589d8 6929 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
Kojto 90:cb3d968589d8 6930 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
Kojto 90:cb3d968589d8 6931 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
Kojto 90:cb3d968589d8 6932 #define SIM_SOPT1CFG_USSWE_SHIFT 26
Kojto 90:cb3d968589d8 6933 /* SOPT2 Bit Fields */
Kojto 90:cb3d968589d8 6934 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
Kojto 90:cb3d968589d8 6935 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
Kojto 90:cb3d968589d8 6936 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
Kojto 90:cb3d968589d8 6937 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
Kojto 90:cb3d968589d8 6938 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
Kojto 90:cb3d968589d8 6939 #define SIM_SOPT2_USBSRC_MASK 0x40000u
Kojto 90:cb3d968589d8 6940 #define SIM_SOPT2_USBSRC_SHIFT 18
Kojto 90:cb3d968589d8 6941 #define SIM_SOPT2_FLEXIOSRC_MASK 0xC00000u
Kojto 90:cb3d968589d8 6942 #define SIM_SOPT2_FLEXIOSRC_SHIFT 22
Kojto 90:cb3d968589d8 6943 #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FLEXIOSRC_SHIFT))&SIM_SOPT2_FLEXIOSRC_MASK)
Kojto 90:cb3d968589d8 6944 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
Kojto 90:cb3d968589d8 6945 #define SIM_SOPT2_TPMSRC_SHIFT 24
Kojto 90:cb3d968589d8 6946 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
Kojto 90:cb3d968589d8 6947 #define SIM_SOPT2_LPUART0SRC_MASK 0xC000000u
Kojto 90:cb3d968589d8 6948 #define SIM_SOPT2_LPUART0SRC_SHIFT 26
Kojto 90:cb3d968589d8 6949 #define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART0SRC_SHIFT))&SIM_SOPT2_LPUART0SRC_MASK)
Kojto 90:cb3d968589d8 6950 #define SIM_SOPT2_LPUART1SRC_MASK 0x30000000u
Kojto 90:cb3d968589d8 6951 #define SIM_SOPT2_LPUART1SRC_SHIFT 28
Kojto 90:cb3d968589d8 6952 #define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART1SRC_SHIFT))&SIM_SOPT2_LPUART1SRC_MASK)
Kojto 90:cb3d968589d8 6953 /* SOPT4 Bit Fields */
Kojto 90:cb3d968589d8 6954 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
Kojto 90:cb3d968589d8 6955 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
Kojto 90:cb3d968589d8 6956 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
Kojto 90:cb3d968589d8 6957 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
Kojto 90:cb3d968589d8 6958 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
Kojto 90:cb3d968589d8 6959 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
Kojto 90:cb3d968589d8 6960 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
Kojto 90:cb3d968589d8 6961 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
Kojto 90:cb3d968589d8 6962 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
Kojto 90:cb3d968589d8 6963 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
Kojto 90:cb3d968589d8 6964 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
Kojto 90:cb3d968589d8 6965 /* SOPT5 Bit Fields */
Kojto 90:cb3d968589d8 6966 #define SIM_SOPT5_LPUART0TXSRC_MASK 0x3u
Kojto 90:cb3d968589d8 6967 #define SIM_SOPT5_LPUART0TXSRC_SHIFT 0
Kojto 90:cb3d968589d8 6968 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0TXSRC_SHIFT))&SIM_SOPT5_LPUART0TXSRC_MASK)
Kojto 90:cb3d968589d8 6969 #define SIM_SOPT5_LPUART0RXSRC_MASK 0x4u
Kojto 90:cb3d968589d8 6970 #define SIM_SOPT5_LPUART0RXSRC_SHIFT 2
Kojto 90:cb3d968589d8 6971 #define SIM_SOPT5_LPUART1TXSRC_MASK 0x30u
Kojto 90:cb3d968589d8 6972 #define SIM_SOPT5_LPUART1TXSRC_SHIFT 4
Kojto 90:cb3d968589d8 6973 #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART1TXSRC_SHIFT))&SIM_SOPT5_LPUART1TXSRC_MASK)
Kojto 90:cb3d968589d8 6974 #define SIM_SOPT5_LPUART1RXSRC_MASK 0x40u
Kojto 90:cb3d968589d8 6975 #define SIM_SOPT5_LPUART1RXSRC_SHIFT 6
Kojto 90:cb3d968589d8 6976 #define SIM_SOPT5_LPUART0ODE_MASK 0x10000u
Kojto 90:cb3d968589d8 6977 #define SIM_SOPT5_LPUART0ODE_SHIFT 16
Kojto 90:cb3d968589d8 6978 #define SIM_SOPT5_LPUART1ODE_MASK 0x20000u
Kojto 90:cb3d968589d8 6979 #define SIM_SOPT5_LPUART1ODE_SHIFT 17
Kojto 90:cb3d968589d8 6980 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
Kojto 90:cb3d968589d8 6981 #define SIM_SOPT5_UART2ODE_SHIFT 18
Kojto 90:cb3d968589d8 6982 /* SOPT7 Bit Fields */
Kojto 90:cb3d968589d8 6983 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
Kojto 90:cb3d968589d8 6984 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
Kojto 90:cb3d968589d8 6985 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
Kojto 90:cb3d968589d8 6986 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
Kojto 90:cb3d968589d8 6987 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
Kojto 90:cb3d968589d8 6988 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
Kojto 90:cb3d968589d8 6989 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
Kojto 90:cb3d968589d8 6990 /* SDID Bit Fields */
Kojto 90:cb3d968589d8 6991 #define SIM_SDID_PINID_MASK 0xFu
Kojto 90:cb3d968589d8 6992 #define SIM_SDID_PINID_SHIFT 0
Kojto 90:cb3d968589d8 6993 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
Kojto 90:cb3d968589d8 6994 #define SIM_SDID_REVID_MASK 0xF000u
Kojto 90:cb3d968589d8 6995 #define SIM_SDID_REVID_SHIFT 12
Kojto 90:cb3d968589d8 6996 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
Kojto 90:cb3d968589d8 6997 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
Kojto 90:cb3d968589d8 6998 #define SIM_SDID_SRAMSIZE_SHIFT 16
Kojto 90:cb3d968589d8 6999 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
Kojto 90:cb3d968589d8 7000 #define SIM_SDID_SERIESID_MASK 0xF00000u
Kojto 90:cb3d968589d8 7001 #define SIM_SDID_SERIESID_SHIFT 20
Kojto 90:cb3d968589d8 7002 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
Kojto 90:cb3d968589d8 7003 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
Kojto 90:cb3d968589d8 7004 #define SIM_SDID_SUBFAMID_SHIFT 24
Kojto 90:cb3d968589d8 7005 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
Kojto 90:cb3d968589d8 7006 #define SIM_SDID_FAMID_MASK 0xF0000000u
Kojto 90:cb3d968589d8 7007 #define SIM_SDID_FAMID_SHIFT 28
Kojto 90:cb3d968589d8 7008 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
Kojto 90:cb3d968589d8 7009 /* SCGC4 Bit Fields */
Kojto 90:cb3d968589d8 7010 #define SIM_SCGC4_I2C0_MASK 0x40u
Kojto 90:cb3d968589d8 7011 #define SIM_SCGC4_I2C0_SHIFT 6
Kojto 90:cb3d968589d8 7012 #define SIM_SCGC4_I2C1_MASK 0x80u
Kojto 90:cb3d968589d8 7013 #define SIM_SCGC4_I2C1_SHIFT 7
Kojto 90:cb3d968589d8 7014 #define SIM_SCGC4_UART2_MASK 0x1000u
Kojto 90:cb3d968589d8 7015 #define SIM_SCGC4_UART2_SHIFT 12
Kojto 90:cb3d968589d8 7016 #define SIM_SCGC4_USBFS_MASK 0x40000u
Kojto 90:cb3d968589d8 7017 #define SIM_SCGC4_USBFS_SHIFT 18
Kojto 90:cb3d968589d8 7018 #define SIM_SCGC4_CMP0_MASK 0x80000u
Kojto 90:cb3d968589d8 7019 #define SIM_SCGC4_CMP0_SHIFT 19
Kojto 90:cb3d968589d8 7020 #define SIM_SCGC4_VREF_MASK 0x100000u
Kojto 90:cb3d968589d8 7021 #define SIM_SCGC4_VREF_SHIFT 20
Kojto 90:cb3d968589d8 7022 #define SIM_SCGC4_SPI0_MASK 0x400000u
Kojto 90:cb3d968589d8 7023 #define SIM_SCGC4_SPI0_SHIFT 22
Kojto 90:cb3d968589d8 7024 #define SIM_SCGC4_SPI1_MASK 0x800000u
Kojto 90:cb3d968589d8 7025 #define SIM_SCGC4_SPI1_SHIFT 23
Kojto 90:cb3d968589d8 7026 /* SCGC5 Bit Fields */
Kojto 90:cb3d968589d8 7027 #define SIM_SCGC5_LPTMR_MASK 0x1u
Kojto 90:cb3d968589d8 7028 #define SIM_SCGC5_LPTMR_SHIFT 0
Kojto 90:cb3d968589d8 7029 #define SIM_SCGC5_PORTA_MASK 0x200u
Kojto 90:cb3d968589d8 7030 #define SIM_SCGC5_PORTA_SHIFT 9
Kojto 90:cb3d968589d8 7031 #define SIM_SCGC5_PORTB_MASK 0x400u
Kojto 90:cb3d968589d8 7032 #define SIM_SCGC5_PORTB_SHIFT 10
Kojto 90:cb3d968589d8 7033 #define SIM_SCGC5_PORTC_MASK 0x800u
Kojto 90:cb3d968589d8 7034 #define SIM_SCGC5_PORTC_SHIFT 11
Kojto 90:cb3d968589d8 7035 #define SIM_SCGC5_PORTD_MASK 0x1000u
Kojto 90:cb3d968589d8 7036 #define SIM_SCGC5_PORTD_SHIFT 12
Kojto 90:cb3d968589d8 7037 #define SIM_SCGC5_PORTE_MASK 0x2000u
Kojto 90:cb3d968589d8 7038 #define SIM_SCGC5_PORTE_SHIFT 13
Kojto 90:cb3d968589d8 7039 #define SIM_SCGC5_SLCD_MASK 0x80000u
Kojto 90:cb3d968589d8 7040 #define SIM_SCGC5_SLCD_SHIFT 19
Kojto 90:cb3d968589d8 7041 #define SIM_SCGC5_LPUART0_MASK 0x100000u
Kojto 90:cb3d968589d8 7042 #define SIM_SCGC5_LPUART0_SHIFT 20
Kojto 90:cb3d968589d8 7043 #define SIM_SCGC5_LPUART1_MASK 0x200000u
Kojto 90:cb3d968589d8 7044 #define SIM_SCGC5_LPUART1_SHIFT 21
Kojto 90:cb3d968589d8 7045 #define SIM_SCGC5_FLEXIO_MASK 0x80000000u
Kojto 90:cb3d968589d8 7046 #define SIM_SCGC5_FLEXIO_SHIFT 31
Kojto 90:cb3d968589d8 7047 /* SCGC6 Bit Fields */
Kojto 90:cb3d968589d8 7048 #define SIM_SCGC6_FTF_MASK 0x1u
Kojto 90:cb3d968589d8 7049 #define SIM_SCGC6_FTF_SHIFT 0
Kojto 90:cb3d968589d8 7050 #define SIM_SCGC6_DMAMUX_MASK 0x2u
Kojto 90:cb3d968589d8 7051 #define SIM_SCGC6_DMAMUX_SHIFT 1
Kojto 90:cb3d968589d8 7052 #define SIM_SCGC6_I2S_MASK 0x8000u
Kojto 90:cb3d968589d8 7053 #define SIM_SCGC6_I2S_SHIFT 15
Kojto 90:cb3d968589d8 7054 #define SIM_SCGC6_PIT_MASK 0x800000u
Kojto 90:cb3d968589d8 7055 #define SIM_SCGC6_PIT_SHIFT 23
Kojto 90:cb3d968589d8 7056 #define SIM_SCGC6_TPM0_MASK 0x1000000u
Kojto 90:cb3d968589d8 7057 #define SIM_SCGC6_TPM0_SHIFT 24
Kojto 90:cb3d968589d8 7058 #define SIM_SCGC6_TPM1_MASK 0x2000000u
Kojto 90:cb3d968589d8 7059 #define SIM_SCGC6_TPM1_SHIFT 25
Kojto 90:cb3d968589d8 7060 #define SIM_SCGC6_TPM2_MASK 0x4000000u
Kojto 90:cb3d968589d8 7061 #define SIM_SCGC6_TPM2_SHIFT 26
Kojto 90:cb3d968589d8 7062 #define SIM_SCGC6_ADC0_MASK 0x8000000u
Kojto 90:cb3d968589d8 7063 #define SIM_SCGC6_ADC0_SHIFT 27
Kojto 90:cb3d968589d8 7064 #define SIM_SCGC6_RTC_MASK 0x20000000u
Kojto 90:cb3d968589d8 7065 #define SIM_SCGC6_RTC_SHIFT 29
Kojto 90:cb3d968589d8 7066 #define SIM_SCGC6_DAC0_MASK 0x80000000u
Kojto 90:cb3d968589d8 7067 #define SIM_SCGC6_DAC0_SHIFT 31
Kojto 90:cb3d968589d8 7068 /* SCGC7 Bit Fields */
Kojto 90:cb3d968589d8 7069 #define SIM_SCGC7_DMA_MASK 0x100u
Kojto 90:cb3d968589d8 7070 #define SIM_SCGC7_DMA_SHIFT 8
Kojto 90:cb3d968589d8 7071 /* CLKDIV1 Bit Fields */
Kojto 90:cb3d968589d8 7072 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
Kojto 90:cb3d968589d8 7073 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
Kojto 90:cb3d968589d8 7074 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
Kojto 90:cb3d968589d8 7075 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
Kojto 90:cb3d968589d8 7076 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
Kojto 90:cb3d968589d8 7077 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
Kojto 90:cb3d968589d8 7078 /* FCFG1 Bit Fields */
Kojto 90:cb3d968589d8 7079 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
Kojto 90:cb3d968589d8 7080 #define SIM_FCFG1_FLASHDIS_SHIFT 0
Kojto 90:cb3d968589d8 7081 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
Kojto 90:cb3d968589d8 7082 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
Kojto 90:cb3d968589d8 7083 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
Kojto 90:cb3d968589d8 7084 #define SIM_FCFG1_PFSIZE_SHIFT 24
Kojto 90:cb3d968589d8 7085 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
Kojto 90:cb3d968589d8 7086 /* FCFG2 Bit Fields */
Kojto 90:cb3d968589d8 7087 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
Kojto 90:cb3d968589d8 7088 #define SIM_FCFG2_MAXADDR1_SHIFT 16
Kojto 90:cb3d968589d8 7089 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
Kojto 90:cb3d968589d8 7090 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
Kojto 90:cb3d968589d8 7091 #define SIM_FCFG2_MAXADDR0_SHIFT 24
Kojto 90:cb3d968589d8 7092 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
Kojto 90:cb3d968589d8 7093 /* UIDMH Bit Fields */
Kojto 90:cb3d968589d8 7094 #define SIM_UIDMH_UID_MASK 0xFFFFu
Kojto 90:cb3d968589d8 7095 #define SIM_UIDMH_UID_SHIFT 0
Kojto 90:cb3d968589d8 7096 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
Kojto 90:cb3d968589d8 7097 /* UIDML Bit Fields */
Kojto 90:cb3d968589d8 7098 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 7099 #define SIM_UIDML_UID_SHIFT 0
Kojto 90:cb3d968589d8 7100 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
Kojto 90:cb3d968589d8 7101 /* UIDL Bit Fields */
Kojto 90:cb3d968589d8 7102 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
Kojto 90:cb3d968589d8 7103 #define SIM_UIDL_UID_SHIFT 0
Kojto 90:cb3d968589d8 7104 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
Kojto 90:cb3d968589d8 7105 /* COPC Bit Fields */
Kojto 90:cb3d968589d8 7106 #define SIM_COPC_COPW_MASK 0x1u
Kojto 90:cb3d968589d8 7107 #define SIM_COPC_COPW_SHIFT 0
Kojto 90:cb3d968589d8 7108 #define SIM_COPC_COPCLKS_MASK 0x2u
Kojto 90:cb3d968589d8 7109 #define SIM_COPC_COPCLKS_SHIFT 1
Kojto 90:cb3d968589d8 7110 #define SIM_COPC_COPT_MASK 0xCu
Kojto 90:cb3d968589d8 7111 #define SIM_COPC_COPT_SHIFT 2
Kojto 90:cb3d968589d8 7112 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
Kojto 90:cb3d968589d8 7113 #define SIM_COPC_COPSTPEN_MASK 0x10u
Kojto 90:cb3d968589d8 7114 #define SIM_COPC_COPSTPEN_SHIFT 4
Kojto 90:cb3d968589d8 7115 #define SIM_COPC_COPDBGEN_MASK 0x20u
Kojto 90:cb3d968589d8 7116 #define SIM_COPC_COPDBGEN_SHIFT 5
Kojto 90:cb3d968589d8 7117 #define SIM_COPC_COPCLKSEL_MASK 0xC0u
Kojto 90:cb3d968589d8 7118 #define SIM_COPC_COPCLKSEL_SHIFT 6
Kojto 90:cb3d968589d8 7119 #define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPCLKSEL_SHIFT))&SIM_COPC_COPCLKSEL_MASK)
Kojto 90:cb3d968589d8 7120 /* SRVCOP Bit Fields */
Kojto 90:cb3d968589d8 7121 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
Kojto 90:cb3d968589d8 7122 #define SIM_SRVCOP_SRVCOP_SHIFT 0
Kojto 90:cb3d968589d8 7123 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
Kojto 90:cb3d968589d8 7124
Kojto 90:cb3d968589d8 7125 /*!
Kojto 90:cb3d968589d8 7126 * @}
Kojto 90:cb3d968589d8 7127 */ /* end of group SIM_Register_Masks */
Kojto 90:cb3d968589d8 7128
Kojto 90:cb3d968589d8 7129
Kojto 90:cb3d968589d8 7130 /* SIM - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 7131 /** Peripheral SIM base address */
Kojto 90:cb3d968589d8 7132 #define SIM_BASE (0x40047000u)
Kojto 90:cb3d968589d8 7133 /** Peripheral SIM base pointer */
Kojto 90:cb3d968589d8 7134 #define SIM ((SIM_Type *)SIM_BASE)
Kojto 90:cb3d968589d8 7135 #define SIM_BASE_PTR (SIM)
Kojto 90:cb3d968589d8 7136 /** Array initializer of SIM peripheral base addresses */
Kojto 90:cb3d968589d8 7137 #define SIM_BASE_ADDRS { SIM_BASE }
Kojto 90:cb3d968589d8 7138 /** Array initializer of SIM peripheral base pointers */
Kojto 90:cb3d968589d8 7139 #define SIM_BASE_PTRS { SIM }
Kojto 90:cb3d968589d8 7140
Kojto 90:cb3d968589d8 7141 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7142 -- SIM - Register accessor macros
Kojto 90:cb3d968589d8 7143 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7144
Kojto 90:cb3d968589d8 7145 /*!
Kojto 90:cb3d968589d8 7146 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
Kojto 90:cb3d968589d8 7147 * @{
Kojto 90:cb3d968589d8 7148 */
Kojto 90:cb3d968589d8 7149
Kojto 90:cb3d968589d8 7150
Kojto 90:cb3d968589d8 7151 /* SIM - Register instance definitions */
Kojto 90:cb3d968589d8 7152 /* SIM */
Kojto 90:cb3d968589d8 7153 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
Kojto 90:cb3d968589d8 7154 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
Kojto 90:cb3d968589d8 7155 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
Kojto 90:cb3d968589d8 7156 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
Kojto 90:cb3d968589d8 7157 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
Kojto 90:cb3d968589d8 7158 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
Kojto 90:cb3d968589d8 7159 #define SIM_SDID SIM_SDID_REG(SIM)
Kojto 90:cb3d968589d8 7160 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
Kojto 90:cb3d968589d8 7161 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
Kojto 90:cb3d968589d8 7162 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
Kojto 90:cb3d968589d8 7163 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
Kojto 90:cb3d968589d8 7164 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
Kojto 90:cb3d968589d8 7165 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
Kojto 90:cb3d968589d8 7166 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
Kojto 90:cb3d968589d8 7167 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
Kojto 90:cb3d968589d8 7168 #define SIM_UIDML SIM_UIDML_REG(SIM)
Kojto 90:cb3d968589d8 7169 #define SIM_UIDL SIM_UIDL_REG(SIM)
Kojto 90:cb3d968589d8 7170 #define SIM_COPC SIM_COPC_REG(SIM)
Kojto 90:cb3d968589d8 7171 #define SIM_SRVCOP SIM_SRVCOP_REG(SIM)
Kojto 90:cb3d968589d8 7172
Kojto 90:cb3d968589d8 7173 /*!
Kojto 90:cb3d968589d8 7174 * @}
Kojto 90:cb3d968589d8 7175 */ /* end of group SIM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7176
Kojto 90:cb3d968589d8 7177
Kojto 90:cb3d968589d8 7178 /*!
Kojto 90:cb3d968589d8 7179 * @}
Kojto 90:cb3d968589d8 7180 */ /* end of group SIM_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 7181
Kojto 90:cb3d968589d8 7182
Kojto 90:cb3d968589d8 7183 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7184 -- SMC Peripheral Access Layer
Kojto 90:cb3d968589d8 7185 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7186
Kojto 90:cb3d968589d8 7187 /*!
Kojto 90:cb3d968589d8 7188 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
Kojto 90:cb3d968589d8 7189 * @{
Kojto 90:cb3d968589d8 7190 */
Kojto 90:cb3d968589d8 7191
Kojto 90:cb3d968589d8 7192 /** SMC - Register Layout Typedef */
Kojto 90:cb3d968589d8 7193 typedef struct {
Kojto 90:cb3d968589d8 7194 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
Kojto 90:cb3d968589d8 7195 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
Kojto 90:cb3d968589d8 7196 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
Kojto 90:cb3d968589d8 7197 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
Kojto 90:cb3d968589d8 7198 } SMC_Type, *SMC_MemMapPtr;
Kojto 90:cb3d968589d8 7199
Kojto 90:cb3d968589d8 7200 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7201 -- SMC - Register accessor macros
Kojto 90:cb3d968589d8 7202 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7203
Kojto 90:cb3d968589d8 7204 /*!
Kojto 90:cb3d968589d8 7205 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
Kojto 90:cb3d968589d8 7206 * @{
Kojto 90:cb3d968589d8 7207 */
Kojto 90:cb3d968589d8 7208
Kojto 90:cb3d968589d8 7209
Kojto 90:cb3d968589d8 7210 /* SMC - Register accessors */
Kojto 90:cb3d968589d8 7211 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
Kojto 90:cb3d968589d8 7212 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
Kojto 90:cb3d968589d8 7213 #define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
Kojto 90:cb3d968589d8 7214 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
Kojto 90:cb3d968589d8 7215
Kojto 90:cb3d968589d8 7216 /*!
Kojto 90:cb3d968589d8 7217 * @}
Kojto 90:cb3d968589d8 7218 */ /* end of group SMC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7219
Kojto 90:cb3d968589d8 7220
Kojto 90:cb3d968589d8 7221 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7222 -- SMC Register Masks
Kojto 90:cb3d968589d8 7223 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7224
Kojto 90:cb3d968589d8 7225 /*!
Kojto 90:cb3d968589d8 7226 * @addtogroup SMC_Register_Masks SMC Register Masks
Kojto 90:cb3d968589d8 7227 * @{
Kojto 90:cb3d968589d8 7228 */
Kojto 90:cb3d968589d8 7229
Kojto 90:cb3d968589d8 7230 /* PMPROT Bit Fields */
Kojto 90:cb3d968589d8 7231 #define SMC_PMPROT_AVLLS_MASK 0x2u
Kojto 90:cb3d968589d8 7232 #define SMC_PMPROT_AVLLS_SHIFT 1
Kojto 90:cb3d968589d8 7233 #define SMC_PMPROT_ALLS_MASK 0x8u
Kojto 90:cb3d968589d8 7234 #define SMC_PMPROT_ALLS_SHIFT 3
Kojto 90:cb3d968589d8 7235 #define SMC_PMPROT_AVLP_MASK 0x20u
Kojto 90:cb3d968589d8 7236 #define SMC_PMPROT_AVLP_SHIFT 5
Kojto 90:cb3d968589d8 7237 /* PMCTRL Bit Fields */
Kojto 90:cb3d968589d8 7238 #define SMC_PMCTRL_STOPM_MASK 0x7u
Kojto 90:cb3d968589d8 7239 #define SMC_PMCTRL_STOPM_SHIFT 0
Kojto 90:cb3d968589d8 7240 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
Kojto 90:cb3d968589d8 7241 #define SMC_PMCTRL_STOPA_MASK 0x8u
Kojto 90:cb3d968589d8 7242 #define SMC_PMCTRL_STOPA_SHIFT 3
Kojto 90:cb3d968589d8 7243 #define SMC_PMCTRL_RUNM_MASK 0x60u
Kojto 90:cb3d968589d8 7244 #define SMC_PMCTRL_RUNM_SHIFT 5
Kojto 90:cb3d968589d8 7245 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
Kojto 90:cb3d968589d8 7246 /* STOPCTRL Bit Fields */
Kojto 90:cb3d968589d8 7247 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
Kojto 90:cb3d968589d8 7248 #define SMC_STOPCTRL_VLLSM_SHIFT 0
Kojto 90:cb3d968589d8 7249 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
Kojto 90:cb3d968589d8 7250 #define SMC_STOPCTRL_PORPO_MASK 0x20u
Kojto 90:cb3d968589d8 7251 #define SMC_STOPCTRL_PORPO_SHIFT 5
Kojto 90:cb3d968589d8 7252 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
Kojto 90:cb3d968589d8 7253 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
Kojto 90:cb3d968589d8 7254 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
Kojto 90:cb3d968589d8 7255 /* PMSTAT Bit Fields */
Kojto 90:cb3d968589d8 7256 #define SMC_PMSTAT_PMSTAT_MASK 0xFFu
Kojto 90:cb3d968589d8 7257 #define SMC_PMSTAT_PMSTAT_SHIFT 0
Kojto 90:cb3d968589d8 7258 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
Kojto 90:cb3d968589d8 7259
Kojto 90:cb3d968589d8 7260 /*!
Kojto 90:cb3d968589d8 7261 * @}
Kojto 90:cb3d968589d8 7262 */ /* end of group SMC_Register_Masks */
Kojto 90:cb3d968589d8 7263
Kojto 90:cb3d968589d8 7264
Kojto 90:cb3d968589d8 7265 /* SMC - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 7266 /** Peripheral SMC base address */
Kojto 90:cb3d968589d8 7267 #define SMC_BASE (0x4007E000u)
Kojto 90:cb3d968589d8 7268 /** Peripheral SMC base pointer */
Kojto 90:cb3d968589d8 7269 #define SMC ((SMC_Type *)SMC_BASE)
Kojto 90:cb3d968589d8 7270 #define SMC_BASE_PTR (SMC)
Kojto 90:cb3d968589d8 7271 /** Array initializer of SMC peripheral base addresses */
Kojto 90:cb3d968589d8 7272 #define SMC_BASE_ADDRS { SMC_BASE }
Kojto 90:cb3d968589d8 7273 /** Array initializer of SMC peripheral base pointers */
Kojto 90:cb3d968589d8 7274 #define SMC_BASE_PTRS { SMC }
Kojto 90:cb3d968589d8 7275
Kojto 90:cb3d968589d8 7276 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7277 -- SMC - Register accessor macros
Kojto 90:cb3d968589d8 7278 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7279
Kojto 90:cb3d968589d8 7280 /*!
Kojto 90:cb3d968589d8 7281 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
Kojto 90:cb3d968589d8 7282 * @{
Kojto 90:cb3d968589d8 7283 */
Kojto 90:cb3d968589d8 7284
Kojto 90:cb3d968589d8 7285
Kojto 90:cb3d968589d8 7286 /* SMC - Register instance definitions */
Kojto 90:cb3d968589d8 7287 /* SMC */
Kojto 90:cb3d968589d8 7288 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
Kojto 90:cb3d968589d8 7289 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
Kojto 90:cb3d968589d8 7290 #define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
Kojto 90:cb3d968589d8 7291 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
Kojto 90:cb3d968589d8 7292
Kojto 90:cb3d968589d8 7293 /*!
Kojto 90:cb3d968589d8 7294 * @}
Kojto 90:cb3d968589d8 7295 */ /* end of group SMC_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7296
Kojto 90:cb3d968589d8 7297
Kojto 90:cb3d968589d8 7298 /*!
Kojto 90:cb3d968589d8 7299 * @}
Kojto 90:cb3d968589d8 7300 */ /* end of group SMC_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 7301
Kojto 90:cb3d968589d8 7302
Kojto 90:cb3d968589d8 7303 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7304 -- SPI Peripheral Access Layer
Kojto 90:cb3d968589d8 7305 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7306
Kojto 90:cb3d968589d8 7307 /*!
Kojto 90:cb3d968589d8 7308 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
Kojto 90:cb3d968589d8 7309 * @{
Kojto 90:cb3d968589d8 7310 */
Kojto 90:cb3d968589d8 7311
Kojto 90:cb3d968589d8 7312 /** SPI - Register Layout Typedef */
Kojto 90:cb3d968589d8 7313 typedef struct {
Kojto 90:cb3d968589d8 7314 __I uint8_t S; /**< SPI Status Register, offset: 0x0 */
Kojto 90:cb3d968589d8 7315 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
Kojto 90:cb3d968589d8 7316 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
Kojto 90:cb3d968589d8 7317 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
Kojto 90:cb3d968589d8 7318 __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
Kojto 90:cb3d968589d8 7319 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
Kojto 90:cb3d968589d8 7320 __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
Kojto 90:cb3d968589d8 7321 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
Kojto 90:cb3d968589d8 7322 uint8_t RESERVED_0[2];
Kojto 90:cb3d968589d8 7323 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
Kojto 90:cb3d968589d8 7324 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
Kojto 90:cb3d968589d8 7325 } SPI_Type, *SPI_MemMapPtr;
Kojto 90:cb3d968589d8 7326
Kojto 90:cb3d968589d8 7327 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7328 -- SPI - Register accessor macros
Kojto 90:cb3d968589d8 7329 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7330
Kojto 90:cb3d968589d8 7331 /*!
Kojto 90:cb3d968589d8 7332 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
Kojto 90:cb3d968589d8 7333 * @{
Kojto 90:cb3d968589d8 7334 */
Kojto 90:cb3d968589d8 7335
Kojto 90:cb3d968589d8 7336
Kojto 90:cb3d968589d8 7337 /* SPI - Register accessors */
Kojto 90:cb3d968589d8 7338 #define SPI_S_REG(base) ((base)->S)
Kojto 90:cb3d968589d8 7339 #define SPI_BR_REG(base) ((base)->BR)
Kojto 90:cb3d968589d8 7340 #define SPI_C2_REG(base) ((base)->C2)
Kojto 90:cb3d968589d8 7341 #define SPI_C1_REG(base) ((base)->C1)
Kojto 90:cb3d968589d8 7342 #define SPI_ML_REG(base) ((base)->ML)
Kojto 90:cb3d968589d8 7343 #define SPI_MH_REG(base) ((base)->MH)
Kojto 90:cb3d968589d8 7344 #define SPI_DL_REG(base) ((base)->DL)
Kojto 90:cb3d968589d8 7345 #define SPI_DH_REG(base) ((base)->DH)
Kojto 90:cb3d968589d8 7346 #define SPI_CI_REG(base) ((base)->CI)
Kojto 90:cb3d968589d8 7347 #define SPI_C3_REG(base) ((base)->C3)
Kojto 90:cb3d968589d8 7348
Kojto 90:cb3d968589d8 7349 /*!
Kojto 90:cb3d968589d8 7350 * @}
Kojto 90:cb3d968589d8 7351 */ /* end of group SPI_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7352
Kojto 90:cb3d968589d8 7353
Kojto 90:cb3d968589d8 7354 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7355 -- SPI Register Masks
Kojto 90:cb3d968589d8 7356 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7357
Kojto 90:cb3d968589d8 7358 /*!
Kojto 90:cb3d968589d8 7359 * @addtogroup SPI_Register_Masks SPI Register Masks
Kojto 90:cb3d968589d8 7360 * @{
Kojto 90:cb3d968589d8 7361 */
Kojto 90:cb3d968589d8 7362
Kojto 90:cb3d968589d8 7363 /* S Bit Fields */
Kojto 90:cb3d968589d8 7364 #define SPI_S_RFIFOEF_MASK 0x1u
Kojto 90:cb3d968589d8 7365 #define SPI_S_RFIFOEF_SHIFT 0
Kojto 90:cb3d968589d8 7366 #define SPI_S_TXFULLF_MASK 0x2u
Kojto 90:cb3d968589d8 7367 #define SPI_S_TXFULLF_SHIFT 1
Kojto 90:cb3d968589d8 7368 #define SPI_S_TNEAREF_MASK 0x4u
Kojto 90:cb3d968589d8 7369 #define SPI_S_TNEAREF_SHIFT 2
Kojto 90:cb3d968589d8 7370 #define SPI_S_RNFULLF_MASK 0x8u
Kojto 90:cb3d968589d8 7371 #define SPI_S_RNFULLF_SHIFT 3
Kojto 90:cb3d968589d8 7372 #define SPI_S_MODF_MASK 0x10u
Kojto 90:cb3d968589d8 7373 #define SPI_S_MODF_SHIFT 4
Kojto 90:cb3d968589d8 7374 #define SPI_S_SPTEF_MASK 0x20u
Kojto 90:cb3d968589d8 7375 #define SPI_S_SPTEF_SHIFT 5
Kojto 90:cb3d968589d8 7376 #define SPI_S_SPMF_MASK 0x40u
Kojto 90:cb3d968589d8 7377 #define SPI_S_SPMF_SHIFT 6
Kojto 90:cb3d968589d8 7378 #define SPI_S_SPRF_MASK 0x80u
Kojto 90:cb3d968589d8 7379 #define SPI_S_SPRF_SHIFT 7
Kojto 90:cb3d968589d8 7380 /* BR Bit Fields */
Kojto 90:cb3d968589d8 7381 #define SPI_BR_SPR_MASK 0xFu
Kojto 90:cb3d968589d8 7382 #define SPI_BR_SPR_SHIFT 0
Kojto 90:cb3d968589d8 7383 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
Kojto 90:cb3d968589d8 7384 #define SPI_BR_SPPR_MASK 0x70u
Kojto 90:cb3d968589d8 7385 #define SPI_BR_SPPR_SHIFT 4
Kojto 90:cb3d968589d8 7386 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
Kojto 90:cb3d968589d8 7387 /* C2 Bit Fields */
Kojto 90:cb3d968589d8 7388 #define SPI_C2_SPC0_MASK 0x1u
Kojto 90:cb3d968589d8 7389 #define SPI_C2_SPC0_SHIFT 0
Kojto 90:cb3d968589d8 7390 #define SPI_C2_SPISWAI_MASK 0x2u
Kojto 90:cb3d968589d8 7391 #define SPI_C2_SPISWAI_SHIFT 1
Kojto 90:cb3d968589d8 7392 #define SPI_C2_RXDMAE_MASK 0x4u
Kojto 90:cb3d968589d8 7393 #define SPI_C2_RXDMAE_SHIFT 2
Kojto 90:cb3d968589d8 7394 #define SPI_C2_BIDIROE_MASK 0x8u
Kojto 90:cb3d968589d8 7395 #define SPI_C2_BIDIROE_SHIFT 3
Kojto 90:cb3d968589d8 7396 #define SPI_C2_MODFEN_MASK 0x10u
Kojto 90:cb3d968589d8 7397 #define SPI_C2_MODFEN_SHIFT 4
Kojto 90:cb3d968589d8 7398 #define SPI_C2_TXDMAE_MASK 0x20u
Kojto 90:cb3d968589d8 7399 #define SPI_C2_TXDMAE_SHIFT 5
Kojto 90:cb3d968589d8 7400 #define SPI_C2_SPIMODE_MASK 0x40u
Kojto 90:cb3d968589d8 7401 #define SPI_C2_SPIMODE_SHIFT 6
Kojto 90:cb3d968589d8 7402 #define SPI_C2_SPMIE_MASK 0x80u
Kojto 90:cb3d968589d8 7403 #define SPI_C2_SPMIE_SHIFT 7
Kojto 90:cb3d968589d8 7404 /* C1 Bit Fields */
Kojto 90:cb3d968589d8 7405 #define SPI_C1_LSBFE_MASK 0x1u
Kojto 90:cb3d968589d8 7406 #define SPI_C1_LSBFE_SHIFT 0
Kojto 90:cb3d968589d8 7407 #define SPI_C1_SSOE_MASK 0x2u
Kojto 90:cb3d968589d8 7408 #define SPI_C1_SSOE_SHIFT 1
Kojto 90:cb3d968589d8 7409 #define SPI_C1_CPHA_MASK 0x4u
Kojto 90:cb3d968589d8 7410 #define SPI_C1_CPHA_SHIFT 2
Kojto 90:cb3d968589d8 7411 #define SPI_C1_CPOL_MASK 0x8u
Kojto 90:cb3d968589d8 7412 #define SPI_C1_CPOL_SHIFT 3
Kojto 90:cb3d968589d8 7413 #define SPI_C1_MSTR_MASK 0x10u
Kojto 90:cb3d968589d8 7414 #define SPI_C1_MSTR_SHIFT 4
Kojto 90:cb3d968589d8 7415 #define SPI_C1_SPTIE_MASK 0x20u
Kojto 90:cb3d968589d8 7416 #define SPI_C1_SPTIE_SHIFT 5
Kojto 90:cb3d968589d8 7417 #define SPI_C1_SPE_MASK 0x40u
Kojto 90:cb3d968589d8 7418 #define SPI_C1_SPE_SHIFT 6
Kojto 90:cb3d968589d8 7419 #define SPI_C1_SPIE_MASK 0x80u
Kojto 90:cb3d968589d8 7420 #define SPI_C1_SPIE_SHIFT 7
Kojto 90:cb3d968589d8 7421 /* ML Bit Fields */
Kojto 90:cb3d968589d8 7422 #define SPI_ML_Bits_MASK 0xFFu
Kojto 90:cb3d968589d8 7423 #define SPI_ML_Bits_SHIFT 0
Kojto 90:cb3d968589d8 7424 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
Kojto 90:cb3d968589d8 7425 /* MH Bit Fields */
Kojto 90:cb3d968589d8 7426 #define SPI_MH_Bits_MASK 0xFFu
Kojto 90:cb3d968589d8 7427 #define SPI_MH_Bits_SHIFT 0
Kojto 90:cb3d968589d8 7428 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
Kojto 90:cb3d968589d8 7429 /* DL Bit Fields */
Kojto 90:cb3d968589d8 7430 #define SPI_DL_Bits_MASK 0xFFu
Kojto 90:cb3d968589d8 7431 #define SPI_DL_Bits_SHIFT 0
Kojto 90:cb3d968589d8 7432 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
Kojto 90:cb3d968589d8 7433 /* DH Bit Fields */
Kojto 90:cb3d968589d8 7434 #define SPI_DH_Bits_MASK 0xFFu
Kojto 90:cb3d968589d8 7435 #define SPI_DH_Bits_SHIFT 0
Kojto 90:cb3d968589d8 7436 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
Kojto 90:cb3d968589d8 7437 /* CI Bit Fields */
Kojto 90:cb3d968589d8 7438 #define SPI_CI_SPRFCI_MASK 0x1u
Kojto 90:cb3d968589d8 7439 #define SPI_CI_SPRFCI_SHIFT 0
Kojto 90:cb3d968589d8 7440 #define SPI_CI_SPTEFCI_MASK 0x2u
Kojto 90:cb3d968589d8 7441 #define SPI_CI_SPTEFCI_SHIFT 1
Kojto 90:cb3d968589d8 7442 #define SPI_CI_RNFULLFCI_MASK 0x4u
Kojto 90:cb3d968589d8 7443 #define SPI_CI_RNFULLFCI_SHIFT 2
Kojto 90:cb3d968589d8 7444 #define SPI_CI_TNEAREFCI_MASK 0x8u
Kojto 90:cb3d968589d8 7445 #define SPI_CI_TNEAREFCI_SHIFT 3
Kojto 90:cb3d968589d8 7446 #define SPI_CI_RXFOF_MASK 0x10u
Kojto 90:cb3d968589d8 7447 #define SPI_CI_RXFOF_SHIFT 4
Kojto 90:cb3d968589d8 7448 #define SPI_CI_TXFOF_MASK 0x20u
Kojto 90:cb3d968589d8 7449 #define SPI_CI_TXFOF_SHIFT 5
Kojto 90:cb3d968589d8 7450 #define SPI_CI_RXFERR_MASK 0x40u
Kojto 90:cb3d968589d8 7451 #define SPI_CI_RXFERR_SHIFT 6
Kojto 90:cb3d968589d8 7452 #define SPI_CI_TXFERR_MASK 0x80u
Kojto 90:cb3d968589d8 7453 #define SPI_CI_TXFERR_SHIFT 7
Kojto 90:cb3d968589d8 7454 /* C3 Bit Fields */
Kojto 90:cb3d968589d8 7455 #define SPI_C3_FIFOMODE_MASK 0x1u
Kojto 90:cb3d968589d8 7456 #define SPI_C3_FIFOMODE_SHIFT 0
Kojto 90:cb3d968589d8 7457 #define SPI_C3_RNFULLIEN_MASK 0x2u
Kojto 90:cb3d968589d8 7458 #define SPI_C3_RNFULLIEN_SHIFT 1
Kojto 90:cb3d968589d8 7459 #define SPI_C3_TNEARIEN_MASK 0x4u
Kojto 90:cb3d968589d8 7460 #define SPI_C3_TNEARIEN_SHIFT 2
Kojto 90:cb3d968589d8 7461 #define SPI_C3_INTCLR_MASK 0x8u
Kojto 90:cb3d968589d8 7462 #define SPI_C3_INTCLR_SHIFT 3
Kojto 90:cb3d968589d8 7463 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
Kojto 90:cb3d968589d8 7464 #define SPI_C3_RNFULLF_MARK_SHIFT 4
Kojto 90:cb3d968589d8 7465 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
Kojto 90:cb3d968589d8 7466 #define SPI_C3_TNEAREF_MARK_SHIFT 5
Kojto 90:cb3d968589d8 7467
Kojto 90:cb3d968589d8 7468 /*!
Kojto 90:cb3d968589d8 7469 * @}
Kojto 90:cb3d968589d8 7470 */ /* end of group SPI_Register_Masks */
Kojto 90:cb3d968589d8 7471
Kojto 90:cb3d968589d8 7472
Kojto 90:cb3d968589d8 7473 /* SPI - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 7474 /** Peripheral SPI0 base address */
Kojto 90:cb3d968589d8 7475 #define SPI0_BASE (0x40076000u)
Kojto 90:cb3d968589d8 7476 /** Peripheral SPI0 base pointer */
Kojto 90:cb3d968589d8 7477 #define SPI0 ((SPI_Type *)SPI0_BASE)
Kojto 90:cb3d968589d8 7478 #define SPI0_BASE_PTR (SPI0)
Kojto 90:cb3d968589d8 7479 /** Peripheral SPI1 base address */
Kojto 90:cb3d968589d8 7480 #define SPI1_BASE (0x40077000u)
Kojto 90:cb3d968589d8 7481 /** Peripheral SPI1 base pointer */
Kojto 90:cb3d968589d8 7482 #define SPI1 ((SPI_Type *)SPI1_BASE)
Kojto 90:cb3d968589d8 7483 #define SPI1_BASE_PTR (SPI1)
Kojto 90:cb3d968589d8 7484 /** Array initializer of SPI peripheral base addresses */
Kojto 90:cb3d968589d8 7485 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
Kojto 90:cb3d968589d8 7486 /** Array initializer of SPI peripheral base pointers */
Kojto 90:cb3d968589d8 7487 #define SPI_BASE_PTRS { SPI0, SPI1 }
Kojto 90:cb3d968589d8 7488 /** Interrupt vectors for the SPI peripheral type */
Kojto 90:cb3d968589d8 7489 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
Kojto 90:cb3d968589d8 7490
Kojto 90:cb3d968589d8 7491 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7492 -- SPI - Register accessor macros
Kojto 90:cb3d968589d8 7493 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7494
Kojto 90:cb3d968589d8 7495 /*!
Kojto 90:cb3d968589d8 7496 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
Kojto 90:cb3d968589d8 7497 * @{
Kojto 90:cb3d968589d8 7498 */
Kojto 90:cb3d968589d8 7499
Kojto 90:cb3d968589d8 7500
Kojto 90:cb3d968589d8 7501 /* SPI - Register instance definitions */
Kojto 90:cb3d968589d8 7502 /* SPI0 */
Kojto 90:cb3d968589d8 7503 #define SPI0_S SPI_S_REG(SPI0)
Kojto 90:cb3d968589d8 7504 #define SPI0_BR SPI_BR_REG(SPI0)
Kojto 90:cb3d968589d8 7505 #define SPI0_C2 SPI_C2_REG(SPI0)
Kojto 90:cb3d968589d8 7506 #define SPI0_C1 SPI_C1_REG(SPI0)
Kojto 90:cb3d968589d8 7507 #define SPI0_ML SPI_ML_REG(SPI0)
Kojto 90:cb3d968589d8 7508 #define SPI0_MH SPI_MH_REG(SPI0)
Kojto 90:cb3d968589d8 7509 #define SPI0_DL SPI_DL_REG(SPI0)
Kojto 90:cb3d968589d8 7510 #define SPI0_DH SPI_DH_REG(SPI0)
Kojto 90:cb3d968589d8 7511 /* SPI1 */
Kojto 90:cb3d968589d8 7512 #define SPI1_S SPI_S_REG(SPI1)
Kojto 90:cb3d968589d8 7513 #define SPI1_BR SPI_BR_REG(SPI1)
Kojto 90:cb3d968589d8 7514 #define SPI1_C2 SPI_C2_REG(SPI1)
Kojto 90:cb3d968589d8 7515 #define SPI1_C1 SPI_C1_REG(SPI1)
Kojto 90:cb3d968589d8 7516 #define SPI1_ML SPI_ML_REG(SPI1)
Kojto 90:cb3d968589d8 7517 #define SPI1_MH SPI_MH_REG(SPI1)
Kojto 90:cb3d968589d8 7518 #define SPI1_DL SPI_DL_REG(SPI1)
Kojto 90:cb3d968589d8 7519 #define SPI1_DH SPI_DH_REG(SPI1)
Kojto 90:cb3d968589d8 7520 #define SPI1_CI SPI_CI_REG(SPI1)
Kojto 90:cb3d968589d8 7521 #define SPI1_C3 SPI_C3_REG(SPI1)
Kojto 90:cb3d968589d8 7522
Kojto 90:cb3d968589d8 7523 /*!
Kojto 90:cb3d968589d8 7524 * @}
Kojto 90:cb3d968589d8 7525 */ /* end of group SPI_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7526
Kojto 90:cb3d968589d8 7527
Kojto 90:cb3d968589d8 7528 /*!
Kojto 90:cb3d968589d8 7529 * @}
Kojto 90:cb3d968589d8 7530 */ /* end of group SPI_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 7531
Kojto 90:cb3d968589d8 7532
Kojto 90:cb3d968589d8 7533 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7534 -- TPM Peripheral Access Layer
Kojto 90:cb3d968589d8 7535 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7536
Kojto 90:cb3d968589d8 7537 /*!
Kojto 90:cb3d968589d8 7538 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
Kojto 90:cb3d968589d8 7539 * @{
Kojto 90:cb3d968589d8 7540 */
Kojto 90:cb3d968589d8 7541
Kojto 90:cb3d968589d8 7542 /** TPM - Register Layout Typedef */
Kojto 90:cb3d968589d8 7543 typedef struct {
Kojto 90:cb3d968589d8 7544 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
Kojto 90:cb3d968589d8 7545 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
Kojto 90:cb3d968589d8 7546 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
Kojto 90:cb3d968589d8 7547 struct { /* offset: 0xC, array step: 0x8 */
Kojto 90:cb3d968589d8 7548 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
Kojto 90:cb3d968589d8 7549 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
Kojto 90:cb3d968589d8 7550 } CONTROLS[6];
Kojto 90:cb3d968589d8 7551 uint8_t RESERVED_0[20];
Kojto 90:cb3d968589d8 7552 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
Kojto 90:cb3d968589d8 7553 uint8_t RESERVED_1[28];
Kojto 90:cb3d968589d8 7554 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
Kojto 90:cb3d968589d8 7555 uint8_t RESERVED_2[16];
Kojto 90:cb3d968589d8 7556 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
Kojto 90:cb3d968589d8 7557 } TPM_Type, *TPM_MemMapPtr;
Kojto 90:cb3d968589d8 7558
Kojto 90:cb3d968589d8 7559 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7560 -- TPM - Register accessor macros
Kojto 90:cb3d968589d8 7561 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7562
Kojto 90:cb3d968589d8 7563 /*!
Kojto 90:cb3d968589d8 7564 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
Kojto 90:cb3d968589d8 7565 * @{
Kojto 90:cb3d968589d8 7566 */
Kojto 90:cb3d968589d8 7567
Kojto 90:cb3d968589d8 7568
Kojto 90:cb3d968589d8 7569 /* TPM - Register accessors */
Kojto 90:cb3d968589d8 7570 #define TPM_SC_REG(base) ((base)->SC)
Kojto 90:cb3d968589d8 7571 #define TPM_CNT_REG(base) ((base)->CNT)
Kojto 90:cb3d968589d8 7572 #define TPM_MOD_REG(base) ((base)->MOD)
Kojto 90:cb3d968589d8 7573 #define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
Kojto 90:cb3d968589d8 7574 #define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
Kojto 90:cb3d968589d8 7575 #define TPM_STATUS_REG(base) ((base)->STATUS)
Kojto 90:cb3d968589d8 7576 #define TPM_POL_REG(base) ((base)->POL)
Kojto 90:cb3d968589d8 7577 #define TPM_CONF_REG(base) ((base)->CONF)
Kojto 90:cb3d968589d8 7578
Kojto 90:cb3d968589d8 7579 /*!
Kojto 90:cb3d968589d8 7580 * @}
Kojto 90:cb3d968589d8 7581 */ /* end of group TPM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7582
Kojto 90:cb3d968589d8 7583
Kojto 90:cb3d968589d8 7584 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7585 -- TPM Register Masks
Kojto 90:cb3d968589d8 7586 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7587
Kojto 90:cb3d968589d8 7588 /*!
Kojto 90:cb3d968589d8 7589 * @addtogroup TPM_Register_Masks TPM Register Masks
Kojto 90:cb3d968589d8 7590 * @{
Kojto 90:cb3d968589d8 7591 */
Kojto 90:cb3d968589d8 7592
Kojto 90:cb3d968589d8 7593 /* SC Bit Fields */
Kojto 90:cb3d968589d8 7594 #define TPM_SC_PS_MASK 0x7u
Kojto 90:cb3d968589d8 7595 #define TPM_SC_PS_SHIFT 0
Kojto 90:cb3d968589d8 7596 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
Kojto 90:cb3d968589d8 7597 #define TPM_SC_CMOD_MASK 0x18u
Kojto 90:cb3d968589d8 7598 #define TPM_SC_CMOD_SHIFT 3
Kojto 90:cb3d968589d8 7599 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
Kojto 90:cb3d968589d8 7600 #define TPM_SC_CPWMS_MASK 0x20u
Kojto 90:cb3d968589d8 7601 #define TPM_SC_CPWMS_SHIFT 5
Kojto 90:cb3d968589d8 7602 #define TPM_SC_TOIE_MASK 0x40u
Kojto 90:cb3d968589d8 7603 #define TPM_SC_TOIE_SHIFT 6
Kojto 90:cb3d968589d8 7604 #define TPM_SC_TOF_MASK 0x80u
Kojto 90:cb3d968589d8 7605 #define TPM_SC_TOF_SHIFT 7
Kojto 90:cb3d968589d8 7606 #define TPM_SC_DMA_MASK 0x100u
Kojto 90:cb3d968589d8 7607 #define TPM_SC_DMA_SHIFT 8
Kojto 90:cb3d968589d8 7608 /* CNT Bit Fields */
Kojto 90:cb3d968589d8 7609 #define TPM_CNT_COUNT_MASK 0xFFFFu
Kojto 90:cb3d968589d8 7610 #define TPM_CNT_COUNT_SHIFT 0
Kojto 90:cb3d968589d8 7611 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
Kojto 90:cb3d968589d8 7612 /* MOD Bit Fields */
Kojto 90:cb3d968589d8 7613 #define TPM_MOD_MOD_MASK 0xFFFFu
Kojto 90:cb3d968589d8 7614 #define TPM_MOD_MOD_SHIFT 0
Kojto 90:cb3d968589d8 7615 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
Kojto 90:cb3d968589d8 7616 /* CnSC Bit Fields */
Kojto 90:cb3d968589d8 7617 #define TPM_CnSC_DMA_MASK 0x1u
Kojto 90:cb3d968589d8 7618 #define TPM_CnSC_DMA_SHIFT 0
Kojto 90:cb3d968589d8 7619 #define TPM_CnSC_ELSA_MASK 0x4u
Kojto 90:cb3d968589d8 7620 #define TPM_CnSC_ELSA_SHIFT 2
Kojto 90:cb3d968589d8 7621 #define TPM_CnSC_ELSB_MASK 0x8u
Kojto 90:cb3d968589d8 7622 #define TPM_CnSC_ELSB_SHIFT 3
Kojto 90:cb3d968589d8 7623 #define TPM_CnSC_MSA_MASK 0x10u
Kojto 90:cb3d968589d8 7624 #define TPM_CnSC_MSA_SHIFT 4
Kojto 90:cb3d968589d8 7625 #define TPM_CnSC_MSB_MASK 0x20u
Kojto 90:cb3d968589d8 7626 #define TPM_CnSC_MSB_SHIFT 5
Kojto 90:cb3d968589d8 7627 #define TPM_CnSC_CHIE_MASK 0x40u
Kojto 90:cb3d968589d8 7628 #define TPM_CnSC_CHIE_SHIFT 6
Kojto 90:cb3d968589d8 7629 #define TPM_CnSC_CHF_MASK 0x80u
Kojto 90:cb3d968589d8 7630 #define TPM_CnSC_CHF_SHIFT 7
Kojto 90:cb3d968589d8 7631 /* CnV Bit Fields */
Kojto 90:cb3d968589d8 7632 #define TPM_CnV_VAL_MASK 0xFFFFu
Kojto 90:cb3d968589d8 7633 #define TPM_CnV_VAL_SHIFT 0
Kojto 90:cb3d968589d8 7634 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
Kojto 90:cb3d968589d8 7635 /* STATUS Bit Fields */
Kojto 90:cb3d968589d8 7636 #define TPM_STATUS_CH0F_MASK 0x1u
Kojto 90:cb3d968589d8 7637 #define TPM_STATUS_CH0F_SHIFT 0
Kojto 90:cb3d968589d8 7638 #define TPM_STATUS_CH1F_MASK 0x2u
Kojto 90:cb3d968589d8 7639 #define TPM_STATUS_CH1F_SHIFT 1
Kojto 90:cb3d968589d8 7640 #define TPM_STATUS_CH2F_MASK 0x4u
Kojto 90:cb3d968589d8 7641 #define TPM_STATUS_CH2F_SHIFT 2
Kojto 90:cb3d968589d8 7642 #define TPM_STATUS_CH3F_MASK 0x8u
Kojto 90:cb3d968589d8 7643 #define TPM_STATUS_CH3F_SHIFT 3
Kojto 90:cb3d968589d8 7644 #define TPM_STATUS_CH4F_MASK 0x10u
Kojto 90:cb3d968589d8 7645 #define TPM_STATUS_CH4F_SHIFT 4
Kojto 90:cb3d968589d8 7646 #define TPM_STATUS_CH5F_MASK 0x20u
Kojto 90:cb3d968589d8 7647 #define TPM_STATUS_CH5F_SHIFT 5
Kojto 90:cb3d968589d8 7648 #define TPM_STATUS_TOF_MASK 0x100u
Kojto 90:cb3d968589d8 7649 #define TPM_STATUS_TOF_SHIFT 8
Kojto 90:cb3d968589d8 7650 /* POL Bit Fields */
Kojto 90:cb3d968589d8 7651 #define TPM_POL_POL0_MASK 0x1u
Kojto 90:cb3d968589d8 7652 #define TPM_POL_POL0_SHIFT 0
Kojto 90:cb3d968589d8 7653 #define TPM_POL_POL1_MASK 0x2u
Kojto 90:cb3d968589d8 7654 #define TPM_POL_POL1_SHIFT 1
Kojto 90:cb3d968589d8 7655 #define TPM_POL_POL2_MASK 0x4u
Kojto 90:cb3d968589d8 7656 #define TPM_POL_POL2_SHIFT 2
Kojto 90:cb3d968589d8 7657 #define TPM_POL_POL3_MASK 0x8u
Kojto 90:cb3d968589d8 7658 #define TPM_POL_POL3_SHIFT 3
Kojto 90:cb3d968589d8 7659 #define TPM_POL_POL4_MASK 0x10u
Kojto 90:cb3d968589d8 7660 #define TPM_POL_POL4_SHIFT 4
Kojto 90:cb3d968589d8 7661 #define TPM_POL_POL5_MASK 0x20u
Kojto 90:cb3d968589d8 7662 #define TPM_POL_POL5_SHIFT 5
Kojto 90:cb3d968589d8 7663 /* CONF Bit Fields */
Kojto 90:cb3d968589d8 7664 #define TPM_CONF_DOZEEN_MASK 0x20u
Kojto 90:cb3d968589d8 7665 #define TPM_CONF_DOZEEN_SHIFT 5
Kojto 90:cb3d968589d8 7666 #define TPM_CONF_DBGMODE_MASK 0xC0u
Kojto 90:cb3d968589d8 7667 #define TPM_CONF_DBGMODE_SHIFT 6
Kojto 90:cb3d968589d8 7668 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
Kojto 90:cb3d968589d8 7669 #define TPM_CONF_GTBSYNC_MASK 0x100u
Kojto 90:cb3d968589d8 7670 #define TPM_CONF_GTBSYNC_SHIFT 8
Kojto 90:cb3d968589d8 7671 #define TPM_CONF_GTBEEN_MASK 0x200u
Kojto 90:cb3d968589d8 7672 #define TPM_CONF_GTBEEN_SHIFT 9
Kojto 90:cb3d968589d8 7673 #define TPM_CONF_CSOT_MASK 0x10000u
Kojto 90:cb3d968589d8 7674 #define TPM_CONF_CSOT_SHIFT 16
Kojto 90:cb3d968589d8 7675 #define TPM_CONF_CSOO_MASK 0x20000u
Kojto 90:cb3d968589d8 7676 #define TPM_CONF_CSOO_SHIFT 17
Kojto 90:cb3d968589d8 7677 #define TPM_CONF_CROT_MASK 0x40000u
Kojto 90:cb3d968589d8 7678 #define TPM_CONF_CROT_SHIFT 18
Kojto 90:cb3d968589d8 7679 #define TPM_CONF_CPOT_MASK 0x80000u
Kojto 90:cb3d968589d8 7680 #define TPM_CONF_CPOT_SHIFT 19
Kojto 90:cb3d968589d8 7681 #define TPM_CONF_TRGPOL_MASK 0x400000u
Kojto 90:cb3d968589d8 7682 #define TPM_CONF_TRGPOL_SHIFT 22
Kojto 90:cb3d968589d8 7683 #define TPM_CONF_TRGSRC_MASK 0x800000u
Kojto 90:cb3d968589d8 7684 #define TPM_CONF_TRGSRC_SHIFT 23
Kojto 90:cb3d968589d8 7685 #define TPM_CONF_TRGSEL_MASK 0xF000000u
Kojto 90:cb3d968589d8 7686 #define TPM_CONF_TRGSEL_SHIFT 24
Kojto 90:cb3d968589d8 7687 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
Kojto 90:cb3d968589d8 7688
Kojto 90:cb3d968589d8 7689 /*!
Kojto 90:cb3d968589d8 7690 * @}
Kojto 90:cb3d968589d8 7691 */ /* end of group TPM_Register_Masks */
Kojto 90:cb3d968589d8 7692
Kojto 90:cb3d968589d8 7693
Kojto 90:cb3d968589d8 7694 /* TPM - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 7695 /** Peripheral TPM0 base address */
Kojto 90:cb3d968589d8 7696 #define TPM0_BASE (0x40038000u)
Kojto 90:cb3d968589d8 7697 /** Peripheral TPM0 base pointer */
Kojto 90:cb3d968589d8 7698 #define TPM0 ((TPM_Type *)TPM0_BASE)
Kojto 90:cb3d968589d8 7699 #define TPM0_BASE_PTR (TPM0)
Kojto 90:cb3d968589d8 7700 /** Peripheral TPM1 base address */
Kojto 90:cb3d968589d8 7701 #define TPM1_BASE (0x40039000u)
Kojto 90:cb3d968589d8 7702 /** Peripheral TPM1 base pointer */
Kojto 90:cb3d968589d8 7703 #define TPM1 ((TPM_Type *)TPM1_BASE)
Kojto 90:cb3d968589d8 7704 #define TPM1_BASE_PTR (TPM1)
Kojto 90:cb3d968589d8 7705 /** Peripheral TPM2 base address */
Kojto 90:cb3d968589d8 7706 #define TPM2_BASE (0x4003A000u)
Kojto 90:cb3d968589d8 7707 /** Peripheral TPM2 base pointer */
Kojto 90:cb3d968589d8 7708 #define TPM2 ((TPM_Type *)TPM2_BASE)
Kojto 90:cb3d968589d8 7709 #define TPM2_BASE_PTR (TPM2)
Kojto 90:cb3d968589d8 7710 /** Array initializer of TPM peripheral base addresses */
Kojto 90:cb3d968589d8 7711 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
Kojto 90:cb3d968589d8 7712 /** Array initializer of TPM peripheral base pointers */
Kojto 90:cb3d968589d8 7713 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
Kojto 90:cb3d968589d8 7714 /** Interrupt vectors for the TPM peripheral type */
Kojto 90:cb3d968589d8 7715 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
Kojto 90:cb3d968589d8 7716
Kojto 90:cb3d968589d8 7717 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7718 -- TPM - Register accessor macros
Kojto 90:cb3d968589d8 7719 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7720
Kojto 90:cb3d968589d8 7721 /*!
Kojto 90:cb3d968589d8 7722 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
Kojto 90:cb3d968589d8 7723 * @{
Kojto 90:cb3d968589d8 7724 */
Kojto 90:cb3d968589d8 7725
Kojto 90:cb3d968589d8 7726
Kojto 90:cb3d968589d8 7727 /* TPM - Register instance definitions */
Kojto 90:cb3d968589d8 7728 /* TPM0 */
Kojto 90:cb3d968589d8 7729 #define TPM0_SC TPM_SC_REG(TPM0)
Kojto 90:cb3d968589d8 7730 #define TPM0_CNT TPM_CNT_REG(TPM0)
Kojto 90:cb3d968589d8 7731 #define TPM0_MOD TPM_MOD_REG(TPM0)
Kojto 90:cb3d968589d8 7732 #define TPM0_C0SC TPM_CnSC_REG(TPM0,0)
Kojto 90:cb3d968589d8 7733 #define TPM0_C0V TPM_CnV_REG(TPM0,0)
Kojto 90:cb3d968589d8 7734 #define TPM0_C1SC TPM_CnSC_REG(TPM0,1)
Kojto 90:cb3d968589d8 7735 #define TPM0_C1V TPM_CnV_REG(TPM0,1)
Kojto 90:cb3d968589d8 7736 #define TPM0_C2SC TPM_CnSC_REG(TPM0,2)
Kojto 90:cb3d968589d8 7737 #define TPM0_C2V TPM_CnV_REG(TPM0,2)
Kojto 90:cb3d968589d8 7738 #define TPM0_C3SC TPM_CnSC_REG(TPM0,3)
Kojto 90:cb3d968589d8 7739 #define TPM0_C3V TPM_CnV_REG(TPM0,3)
Kojto 90:cb3d968589d8 7740 #define TPM0_C4SC TPM_CnSC_REG(TPM0,4)
Kojto 90:cb3d968589d8 7741 #define TPM0_C4V TPM_CnV_REG(TPM0,4)
Kojto 90:cb3d968589d8 7742 #define TPM0_C5SC TPM_CnSC_REG(TPM0,5)
Kojto 90:cb3d968589d8 7743 #define TPM0_C5V TPM_CnV_REG(TPM0,5)
Kojto 90:cb3d968589d8 7744 #define TPM0_STATUS TPM_STATUS_REG(TPM0)
Kojto 90:cb3d968589d8 7745 #define TPM0_POL TPM_POL_REG(TPM0)
Kojto 90:cb3d968589d8 7746 #define TPM0_CONF TPM_CONF_REG(TPM0)
Kojto 90:cb3d968589d8 7747 /* TPM1 */
Kojto 90:cb3d968589d8 7748 #define TPM1_SC TPM_SC_REG(TPM1)
Kojto 90:cb3d968589d8 7749 #define TPM1_CNT TPM_CNT_REG(TPM1)
Kojto 90:cb3d968589d8 7750 #define TPM1_MOD TPM_MOD_REG(TPM1)
Kojto 90:cb3d968589d8 7751 #define TPM1_C0SC TPM_CnSC_REG(TPM1,0)
Kojto 90:cb3d968589d8 7752 #define TPM1_C0V TPM_CnV_REG(TPM1,0)
Kojto 90:cb3d968589d8 7753 #define TPM1_C1SC TPM_CnSC_REG(TPM1,1)
Kojto 90:cb3d968589d8 7754 #define TPM1_C1V TPM_CnV_REG(TPM1,1)
Kojto 90:cb3d968589d8 7755 #define TPM1_STATUS TPM_STATUS_REG(TPM1)
Kojto 90:cb3d968589d8 7756 #define TPM1_POL TPM_POL_REG(TPM1)
Kojto 90:cb3d968589d8 7757 #define TPM1_CONF TPM_CONF_REG(TPM1)
Kojto 90:cb3d968589d8 7758 /* TPM2 */
Kojto 90:cb3d968589d8 7759 #define TPM2_SC TPM_SC_REG(TPM2)
Kojto 90:cb3d968589d8 7760 #define TPM2_CNT TPM_CNT_REG(TPM2)
Kojto 90:cb3d968589d8 7761 #define TPM2_MOD TPM_MOD_REG(TPM2)
Kojto 90:cb3d968589d8 7762 #define TPM2_C0SC TPM_CnSC_REG(TPM2,0)
Kojto 90:cb3d968589d8 7763 #define TPM2_C0V TPM_CnV_REG(TPM2,0)
Kojto 90:cb3d968589d8 7764 #define TPM2_C1SC TPM_CnSC_REG(TPM2,1)
Kojto 90:cb3d968589d8 7765 #define TPM2_C1V TPM_CnV_REG(TPM2,1)
Kojto 90:cb3d968589d8 7766 #define TPM2_STATUS TPM_STATUS_REG(TPM2)
Kojto 90:cb3d968589d8 7767 #define TPM2_POL TPM_POL_REG(TPM2)
Kojto 90:cb3d968589d8 7768 #define TPM2_CONF TPM_CONF_REG(TPM2)
Kojto 90:cb3d968589d8 7769
Kojto 90:cb3d968589d8 7770 /* TPM - Register array accessors */
Kojto 90:cb3d968589d8 7771 #define TPM0_CnSC(index) TPM_CnSC_REG(TPM0,index)
Kojto 90:cb3d968589d8 7772 #define TPM1_CnSC(index) TPM_CnSC_REG(TPM1,index)
Kojto 90:cb3d968589d8 7773 #define TPM2_CnSC(index) TPM_CnSC_REG(TPM2,index)
Kojto 90:cb3d968589d8 7774 #define TPM0_CnV(index) TPM_CnV_REG(TPM0,index)
Kojto 90:cb3d968589d8 7775 #define TPM1_CnV(index) TPM_CnV_REG(TPM1,index)
Kojto 90:cb3d968589d8 7776 #define TPM2_CnV(index) TPM_CnV_REG(TPM2,index)
Kojto 90:cb3d968589d8 7777
Kojto 90:cb3d968589d8 7778 /*!
Kojto 90:cb3d968589d8 7779 * @}
Kojto 90:cb3d968589d8 7780 */ /* end of group TPM_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7781
Kojto 90:cb3d968589d8 7782
Kojto 90:cb3d968589d8 7783 /*!
Kojto 90:cb3d968589d8 7784 * @}
Kojto 90:cb3d968589d8 7785 */ /* end of group TPM_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 7786
Kojto 90:cb3d968589d8 7787
Kojto 90:cb3d968589d8 7788 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7789 -- UART Peripheral Access Layer
Kojto 90:cb3d968589d8 7790 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7791
Kojto 90:cb3d968589d8 7792 /*!
Kojto 90:cb3d968589d8 7793 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
Kojto 90:cb3d968589d8 7794 * @{
Kojto 90:cb3d968589d8 7795 */
Kojto 90:cb3d968589d8 7796
Kojto 90:cb3d968589d8 7797 /** UART - Register Layout Typedef */
Kojto 90:cb3d968589d8 7798 typedef struct {
Kojto 90:cb3d968589d8 7799 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
Kojto 90:cb3d968589d8 7800 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
Kojto 90:cb3d968589d8 7801 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
Kojto 90:cb3d968589d8 7802 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
Kojto 90:cb3d968589d8 7803 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
Kojto 90:cb3d968589d8 7804 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
Kojto 90:cb3d968589d8 7805 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
Kojto 90:cb3d968589d8 7806 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
Kojto 90:cb3d968589d8 7807 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
Kojto 90:cb3d968589d8 7808 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
Kojto 90:cb3d968589d8 7809 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
Kojto 90:cb3d968589d8 7810 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
Kojto 90:cb3d968589d8 7811 uint8_t RESERVED_0[12];
Kojto 90:cb3d968589d8 7812 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
Kojto 90:cb3d968589d8 7813 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
Kojto 90:cb3d968589d8 7814 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
Kojto 90:cb3d968589d8 7815 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
Kojto 90:cb3d968589d8 7816 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
Kojto 90:cb3d968589d8 7817 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
Kojto 90:cb3d968589d8 7818 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
Kojto 90:cb3d968589d8 7819 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
Kojto 90:cb3d968589d8 7820 uint8_t RESERVED_1[26];
Kojto 90:cb3d968589d8 7821 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
Kojto 90:cb3d968589d8 7822 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
Kojto 90:cb3d968589d8 7823 union { /* offset: 0x3C */
Kojto 90:cb3d968589d8 7824 struct { /* offset: 0x3C */
Kojto 90:cb3d968589d8 7825 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
Kojto 90:cb3d968589d8 7826 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
Kojto 90:cb3d968589d8 7827 } TYPE0;
Kojto 90:cb3d968589d8 7828 struct { /* offset: 0x3C */
Kojto 90:cb3d968589d8 7829 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
Kojto 90:cb3d968589d8 7830 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
Kojto 90:cb3d968589d8 7831 } TYPE1;
Kojto 90:cb3d968589d8 7832 };
Kojto 90:cb3d968589d8 7833 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
Kojto 90:cb3d968589d8 7834 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
Kojto 90:cb3d968589d8 7835 } UART_Type, *UART_MemMapPtr;
Kojto 90:cb3d968589d8 7836
Kojto 90:cb3d968589d8 7837 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7838 -- UART - Register accessor macros
Kojto 90:cb3d968589d8 7839 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7840
Kojto 90:cb3d968589d8 7841 /*!
Kojto 90:cb3d968589d8 7842 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
Kojto 90:cb3d968589d8 7843 * @{
Kojto 90:cb3d968589d8 7844 */
Kojto 90:cb3d968589d8 7845
Kojto 90:cb3d968589d8 7846
Kojto 90:cb3d968589d8 7847 /* UART - Register accessors */
Kojto 90:cb3d968589d8 7848 #define UART_BDH_REG(base) ((base)->BDH)
Kojto 90:cb3d968589d8 7849 #define UART_BDL_REG(base) ((base)->BDL)
Kojto 90:cb3d968589d8 7850 #define UART_C1_REG(base) ((base)->C1)
Kojto 90:cb3d968589d8 7851 #define UART_C2_REG(base) ((base)->C2)
Kojto 90:cb3d968589d8 7852 #define UART_S1_REG(base) ((base)->S1)
Kojto 90:cb3d968589d8 7853 #define UART_S2_REG(base) ((base)->S2)
Kojto 90:cb3d968589d8 7854 #define UART_C3_REG(base) ((base)->C3)
Kojto 90:cb3d968589d8 7855 #define UART_D_REG(base) ((base)->D)
Kojto 90:cb3d968589d8 7856 #define UART_MA1_REG(base) ((base)->MA1)
Kojto 90:cb3d968589d8 7857 #define UART_MA2_REG(base) ((base)->MA2)
Kojto 90:cb3d968589d8 7858 #define UART_C4_REG(base) ((base)->C4)
Kojto 90:cb3d968589d8 7859 #define UART_C5_REG(base) ((base)->C5)
Kojto 90:cb3d968589d8 7860 #define UART_C7816_REG(base) ((base)->C7816)
Kojto 90:cb3d968589d8 7861 #define UART_IE7816_REG(base) ((base)->IE7816)
Kojto 90:cb3d968589d8 7862 #define UART_IS7816_REG(base) ((base)->IS7816)
Kojto 90:cb3d968589d8 7863 #define UART_WP7816_REG(base) ((base)->WP7816)
Kojto 90:cb3d968589d8 7864 #define UART_WN7816_REG(base) ((base)->WN7816)
Kojto 90:cb3d968589d8 7865 #define UART_WF7816_REG(base) ((base)->WF7816)
Kojto 90:cb3d968589d8 7866 #define UART_ET7816_REG(base) ((base)->ET7816)
Kojto 90:cb3d968589d8 7867 #define UART_TL7816_REG(base) ((base)->TL7816)
Kojto 90:cb3d968589d8 7868 #define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
Kojto 90:cb3d968589d8 7869 #define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
Kojto 90:cb3d968589d8 7870 #define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
Kojto 90:cb3d968589d8 7871 #define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
Kojto 90:cb3d968589d8 7872 #define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
Kojto 90:cb3d968589d8 7873 #define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
Kojto 90:cb3d968589d8 7874 #define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
Kojto 90:cb3d968589d8 7875 #define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
Kojto 90:cb3d968589d8 7876
Kojto 90:cb3d968589d8 7877 /*!
Kojto 90:cb3d968589d8 7878 * @}
Kojto 90:cb3d968589d8 7879 */ /* end of group UART_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 7880
Kojto 90:cb3d968589d8 7881
Kojto 90:cb3d968589d8 7882 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 7883 -- UART Register Masks
Kojto 90:cb3d968589d8 7884 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 7885
Kojto 90:cb3d968589d8 7886 /*!
Kojto 90:cb3d968589d8 7887 * @addtogroup UART_Register_Masks UART Register Masks
Kojto 90:cb3d968589d8 7888 * @{
Kojto 90:cb3d968589d8 7889 */
Kojto 90:cb3d968589d8 7890
Kojto 90:cb3d968589d8 7891 /* BDH Bit Fields */
Kojto 90:cb3d968589d8 7892 #define UART_BDH_SBR_MASK 0x1Fu
Kojto 90:cb3d968589d8 7893 #define UART_BDH_SBR_SHIFT 0
Kojto 90:cb3d968589d8 7894 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
Kojto 90:cb3d968589d8 7895 #define UART_BDH_RXEDGIE_MASK 0x40u
Kojto 90:cb3d968589d8 7896 #define UART_BDH_RXEDGIE_SHIFT 6
Kojto 90:cb3d968589d8 7897 /* BDL Bit Fields */
Kojto 90:cb3d968589d8 7898 #define UART_BDL_SBR_MASK 0xFFu
Kojto 90:cb3d968589d8 7899 #define UART_BDL_SBR_SHIFT 0
Kojto 90:cb3d968589d8 7900 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
Kojto 90:cb3d968589d8 7901 /* C1 Bit Fields */
Kojto 90:cb3d968589d8 7902 #define UART_C1_PT_MASK 0x1u
Kojto 90:cb3d968589d8 7903 #define UART_C1_PT_SHIFT 0
Kojto 90:cb3d968589d8 7904 #define UART_C1_PE_MASK 0x2u
Kojto 90:cb3d968589d8 7905 #define UART_C1_PE_SHIFT 1
Kojto 90:cb3d968589d8 7906 #define UART_C1_ILT_MASK 0x4u
Kojto 90:cb3d968589d8 7907 #define UART_C1_ILT_SHIFT 2
Kojto 90:cb3d968589d8 7908 #define UART_C1_WAKE_MASK 0x8u
Kojto 90:cb3d968589d8 7909 #define UART_C1_WAKE_SHIFT 3
Kojto 90:cb3d968589d8 7910 #define UART_C1_M_MASK 0x10u
Kojto 90:cb3d968589d8 7911 #define UART_C1_M_SHIFT 4
Kojto 90:cb3d968589d8 7912 #define UART_C1_RSRC_MASK 0x20u
Kojto 90:cb3d968589d8 7913 #define UART_C1_RSRC_SHIFT 5
Kojto 90:cb3d968589d8 7914 #define UART_C1_LOOPS_MASK 0x80u
Kojto 90:cb3d968589d8 7915 #define UART_C1_LOOPS_SHIFT 7
Kojto 90:cb3d968589d8 7916 /* C2 Bit Fields */
Kojto 90:cb3d968589d8 7917 #define UART_C2_SBK_MASK 0x1u
Kojto 90:cb3d968589d8 7918 #define UART_C2_SBK_SHIFT 0
Kojto 90:cb3d968589d8 7919 #define UART_C2_RWU_MASK 0x2u
Kojto 90:cb3d968589d8 7920 #define UART_C2_RWU_SHIFT 1
Kojto 90:cb3d968589d8 7921 #define UART_C2_RE_MASK 0x4u
Kojto 90:cb3d968589d8 7922 #define UART_C2_RE_SHIFT 2
Kojto 90:cb3d968589d8 7923 #define UART_C2_TE_MASK 0x8u
Kojto 90:cb3d968589d8 7924 #define UART_C2_TE_SHIFT 3
Kojto 90:cb3d968589d8 7925 #define UART_C2_ILIE_MASK 0x10u
Kojto 90:cb3d968589d8 7926 #define UART_C2_ILIE_SHIFT 4
Kojto 90:cb3d968589d8 7927 #define UART_C2_RIE_MASK 0x20u
Kojto 90:cb3d968589d8 7928 #define UART_C2_RIE_SHIFT 5
Kojto 90:cb3d968589d8 7929 #define UART_C2_TCIE_MASK 0x40u
Kojto 90:cb3d968589d8 7930 #define UART_C2_TCIE_SHIFT 6
Kojto 90:cb3d968589d8 7931 #define UART_C2_TIE_MASK 0x80u
Kojto 90:cb3d968589d8 7932 #define UART_C2_TIE_SHIFT 7
Kojto 90:cb3d968589d8 7933 /* S1 Bit Fields */
Kojto 90:cb3d968589d8 7934 #define UART_S1_PF_MASK 0x1u
Kojto 90:cb3d968589d8 7935 #define UART_S1_PF_SHIFT 0
Kojto 90:cb3d968589d8 7936 #define UART_S1_FE_MASK 0x2u
Kojto 90:cb3d968589d8 7937 #define UART_S1_FE_SHIFT 1
Kojto 90:cb3d968589d8 7938 #define UART_S1_NF_MASK 0x4u
Kojto 90:cb3d968589d8 7939 #define UART_S1_NF_SHIFT 2
Kojto 90:cb3d968589d8 7940 #define UART_S1_OR_MASK 0x8u
Kojto 90:cb3d968589d8 7941 #define UART_S1_OR_SHIFT 3
Kojto 90:cb3d968589d8 7942 #define UART_S1_IDLE_MASK 0x10u
Kojto 90:cb3d968589d8 7943 #define UART_S1_IDLE_SHIFT 4
Kojto 90:cb3d968589d8 7944 #define UART_S1_RDRF_MASK 0x20u
Kojto 90:cb3d968589d8 7945 #define UART_S1_RDRF_SHIFT 5
Kojto 90:cb3d968589d8 7946 #define UART_S1_TC_MASK 0x40u
Kojto 90:cb3d968589d8 7947 #define UART_S1_TC_SHIFT 6
Kojto 90:cb3d968589d8 7948 #define UART_S1_TDRE_MASK 0x80u
Kojto 90:cb3d968589d8 7949 #define UART_S1_TDRE_SHIFT 7
Kojto 90:cb3d968589d8 7950 /* S2 Bit Fields */
Kojto 90:cb3d968589d8 7951 #define UART_S2_RAF_MASK 0x1u
Kojto 90:cb3d968589d8 7952 #define UART_S2_RAF_SHIFT 0
Kojto 90:cb3d968589d8 7953 #define UART_S2_BRK13_MASK 0x4u
Kojto 90:cb3d968589d8 7954 #define UART_S2_BRK13_SHIFT 2
Kojto 90:cb3d968589d8 7955 #define UART_S2_RWUID_MASK 0x8u
Kojto 90:cb3d968589d8 7956 #define UART_S2_RWUID_SHIFT 3
Kojto 90:cb3d968589d8 7957 #define UART_S2_RXINV_MASK 0x10u
Kojto 90:cb3d968589d8 7958 #define UART_S2_RXINV_SHIFT 4
Kojto 90:cb3d968589d8 7959 #define UART_S2_MSBF_MASK 0x20u
Kojto 90:cb3d968589d8 7960 #define UART_S2_MSBF_SHIFT 5
Kojto 90:cb3d968589d8 7961 #define UART_S2_RXEDGIF_MASK 0x40u
Kojto 90:cb3d968589d8 7962 #define UART_S2_RXEDGIF_SHIFT 6
Kojto 90:cb3d968589d8 7963 /* C3 Bit Fields */
Kojto 90:cb3d968589d8 7964 #define UART_C3_PEIE_MASK 0x1u
Kojto 90:cb3d968589d8 7965 #define UART_C3_PEIE_SHIFT 0
Kojto 90:cb3d968589d8 7966 #define UART_C3_FEIE_MASK 0x2u
Kojto 90:cb3d968589d8 7967 #define UART_C3_FEIE_SHIFT 1
Kojto 90:cb3d968589d8 7968 #define UART_C3_NEIE_MASK 0x4u
Kojto 90:cb3d968589d8 7969 #define UART_C3_NEIE_SHIFT 2
Kojto 90:cb3d968589d8 7970 #define UART_C3_ORIE_MASK 0x8u
Kojto 90:cb3d968589d8 7971 #define UART_C3_ORIE_SHIFT 3
Kojto 90:cb3d968589d8 7972 #define UART_C3_TXINV_MASK 0x10u
Kojto 90:cb3d968589d8 7973 #define UART_C3_TXINV_SHIFT 4
Kojto 90:cb3d968589d8 7974 #define UART_C3_TXDIR_MASK 0x20u
Kojto 90:cb3d968589d8 7975 #define UART_C3_TXDIR_SHIFT 5
Kojto 90:cb3d968589d8 7976 #define UART_C3_T8_MASK 0x40u
Kojto 90:cb3d968589d8 7977 #define UART_C3_T8_SHIFT 6
Kojto 90:cb3d968589d8 7978 #define UART_C3_R8_MASK 0x80u
Kojto 90:cb3d968589d8 7979 #define UART_C3_R8_SHIFT 7
Kojto 90:cb3d968589d8 7980 /* D Bit Fields */
Kojto 90:cb3d968589d8 7981 #define UART_D_RT_MASK 0xFFu
Kojto 90:cb3d968589d8 7982 #define UART_D_RT_SHIFT 0
Kojto 90:cb3d968589d8 7983 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
Kojto 90:cb3d968589d8 7984 /* MA1 Bit Fields */
Kojto 90:cb3d968589d8 7985 #define UART_MA1_MA_MASK 0xFFu
Kojto 90:cb3d968589d8 7986 #define UART_MA1_MA_SHIFT 0
Kojto 90:cb3d968589d8 7987 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
Kojto 90:cb3d968589d8 7988 /* MA2 Bit Fields */
Kojto 90:cb3d968589d8 7989 #define UART_MA2_MA_MASK 0xFFu
Kojto 90:cb3d968589d8 7990 #define UART_MA2_MA_SHIFT 0
Kojto 90:cb3d968589d8 7991 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
Kojto 90:cb3d968589d8 7992 /* C4 Bit Fields */
Kojto 90:cb3d968589d8 7993 #define UART_C4_BRFA_MASK 0x1Fu
Kojto 90:cb3d968589d8 7994 #define UART_C4_BRFA_SHIFT 0
Kojto 90:cb3d968589d8 7995 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
Kojto 90:cb3d968589d8 7996 #define UART_C4_M10_MASK 0x20u
Kojto 90:cb3d968589d8 7997 #define UART_C4_M10_SHIFT 5
Kojto 90:cb3d968589d8 7998 #define UART_C4_MAEN2_MASK 0x40u
Kojto 90:cb3d968589d8 7999 #define UART_C4_MAEN2_SHIFT 6
Kojto 90:cb3d968589d8 8000 #define UART_C4_MAEN1_MASK 0x80u
Kojto 90:cb3d968589d8 8001 #define UART_C4_MAEN1_SHIFT 7
Kojto 90:cb3d968589d8 8002 /* C5 Bit Fields */
Kojto 90:cb3d968589d8 8003 #define UART_C5_RDMAS_MASK 0x20u
Kojto 90:cb3d968589d8 8004 #define UART_C5_RDMAS_SHIFT 5
Kojto 90:cb3d968589d8 8005 #define UART_C5_TDMAS_MASK 0x80u
Kojto 90:cb3d968589d8 8006 #define UART_C5_TDMAS_SHIFT 7
Kojto 90:cb3d968589d8 8007 /* C7816 Bit Fields */
Kojto 90:cb3d968589d8 8008 #define UART_C7816_ISO_7816E_MASK 0x1u
Kojto 90:cb3d968589d8 8009 #define UART_C7816_ISO_7816E_SHIFT 0
Kojto 90:cb3d968589d8 8010 #define UART_C7816_TTYPE_MASK 0x2u
Kojto 90:cb3d968589d8 8011 #define UART_C7816_TTYPE_SHIFT 1
Kojto 90:cb3d968589d8 8012 #define UART_C7816_INIT_MASK 0x4u
Kojto 90:cb3d968589d8 8013 #define UART_C7816_INIT_SHIFT 2
Kojto 90:cb3d968589d8 8014 #define UART_C7816_ANACK_MASK 0x8u
Kojto 90:cb3d968589d8 8015 #define UART_C7816_ANACK_SHIFT 3
Kojto 90:cb3d968589d8 8016 #define UART_C7816_ONACK_MASK 0x10u
Kojto 90:cb3d968589d8 8017 #define UART_C7816_ONACK_SHIFT 4
Kojto 90:cb3d968589d8 8018 /* IE7816 Bit Fields */
Kojto 90:cb3d968589d8 8019 #define UART_IE7816_RXTE_MASK 0x1u
Kojto 90:cb3d968589d8 8020 #define UART_IE7816_RXTE_SHIFT 0
Kojto 90:cb3d968589d8 8021 #define UART_IE7816_TXTE_MASK 0x2u
Kojto 90:cb3d968589d8 8022 #define UART_IE7816_TXTE_SHIFT 1
Kojto 90:cb3d968589d8 8023 #define UART_IE7816_GTVE_MASK 0x4u
Kojto 90:cb3d968589d8 8024 #define UART_IE7816_GTVE_SHIFT 2
Kojto 90:cb3d968589d8 8025 #define UART_IE7816_ADTE_MASK 0x8u
Kojto 90:cb3d968589d8 8026 #define UART_IE7816_ADTE_SHIFT 3
Kojto 90:cb3d968589d8 8027 #define UART_IE7816_INITDE_MASK 0x10u
Kojto 90:cb3d968589d8 8028 #define UART_IE7816_INITDE_SHIFT 4
Kojto 90:cb3d968589d8 8029 #define UART_IE7816_BWTE_MASK 0x20u
Kojto 90:cb3d968589d8 8030 #define UART_IE7816_BWTE_SHIFT 5
Kojto 90:cb3d968589d8 8031 #define UART_IE7816_CWTE_MASK 0x40u
Kojto 90:cb3d968589d8 8032 #define UART_IE7816_CWTE_SHIFT 6
Kojto 90:cb3d968589d8 8033 #define UART_IE7816_WTE_MASK 0x80u
Kojto 90:cb3d968589d8 8034 #define UART_IE7816_WTE_SHIFT 7
Kojto 90:cb3d968589d8 8035 /* IS7816 Bit Fields */
Kojto 90:cb3d968589d8 8036 #define UART_IS7816_RXT_MASK 0x1u
Kojto 90:cb3d968589d8 8037 #define UART_IS7816_RXT_SHIFT 0
Kojto 90:cb3d968589d8 8038 #define UART_IS7816_TXT_MASK 0x2u
Kojto 90:cb3d968589d8 8039 #define UART_IS7816_TXT_SHIFT 1
Kojto 90:cb3d968589d8 8040 #define UART_IS7816_GTV_MASK 0x4u
Kojto 90:cb3d968589d8 8041 #define UART_IS7816_GTV_SHIFT 2
Kojto 90:cb3d968589d8 8042 #define UART_IS7816_ADT_MASK 0x8u
Kojto 90:cb3d968589d8 8043 #define UART_IS7816_ADT_SHIFT 3
Kojto 90:cb3d968589d8 8044 #define UART_IS7816_INITD_MASK 0x10u
Kojto 90:cb3d968589d8 8045 #define UART_IS7816_INITD_SHIFT 4
Kojto 90:cb3d968589d8 8046 #define UART_IS7816_BWT_MASK 0x20u
Kojto 90:cb3d968589d8 8047 #define UART_IS7816_BWT_SHIFT 5
Kojto 90:cb3d968589d8 8048 #define UART_IS7816_CWT_MASK 0x40u
Kojto 90:cb3d968589d8 8049 #define UART_IS7816_CWT_SHIFT 6
Kojto 90:cb3d968589d8 8050 #define UART_IS7816_WT_MASK 0x80u
Kojto 90:cb3d968589d8 8051 #define UART_IS7816_WT_SHIFT 7
Kojto 90:cb3d968589d8 8052 /* WP7816 Bit Fields */
Kojto 90:cb3d968589d8 8053 #define UART_WP7816_WTX_MASK 0xFFu
Kojto 90:cb3d968589d8 8054 #define UART_WP7816_WTX_SHIFT 0
Kojto 90:cb3d968589d8 8055 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
Kojto 90:cb3d968589d8 8056 /* WN7816 Bit Fields */
Kojto 90:cb3d968589d8 8057 #define UART_WN7816_GTN_MASK 0xFFu
Kojto 90:cb3d968589d8 8058 #define UART_WN7816_GTN_SHIFT 0
Kojto 90:cb3d968589d8 8059 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
Kojto 90:cb3d968589d8 8060 /* WF7816 Bit Fields */
Kojto 90:cb3d968589d8 8061 #define UART_WF7816_GTFD_MASK 0xFFu
Kojto 90:cb3d968589d8 8062 #define UART_WF7816_GTFD_SHIFT 0
Kojto 90:cb3d968589d8 8063 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
Kojto 90:cb3d968589d8 8064 /* ET7816 Bit Fields */
Kojto 90:cb3d968589d8 8065 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
Kojto 90:cb3d968589d8 8066 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
Kojto 90:cb3d968589d8 8067 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
Kojto 90:cb3d968589d8 8068 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
Kojto 90:cb3d968589d8 8069 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
Kojto 90:cb3d968589d8 8070 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
Kojto 90:cb3d968589d8 8071 /* TL7816 Bit Fields */
Kojto 90:cb3d968589d8 8072 #define UART_TL7816_TLEN_MASK 0xFFu
Kojto 90:cb3d968589d8 8073 #define UART_TL7816_TLEN_SHIFT 0
Kojto 90:cb3d968589d8 8074 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
Kojto 90:cb3d968589d8 8075 /* AP7816A_T0 Bit Fields */
Kojto 90:cb3d968589d8 8076 #define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
Kojto 90:cb3d968589d8 8077 #define UART_AP7816A_T0_ADTI_H_SHIFT 0
Kojto 90:cb3d968589d8 8078 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
Kojto 90:cb3d968589d8 8079 /* AP7816B_T0 Bit Fields */
Kojto 90:cb3d968589d8 8080 #define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
Kojto 90:cb3d968589d8 8081 #define UART_AP7816B_T0_ADTI_L_SHIFT 0
Kojto 90:cb3d968589d8 8082 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
Kojto 90:cb3d968589d8 8083 /* WP7816A_T0 Bit Fields */
Kojto 90:cb3d968589d8 8084 #define UART_WP7816A_T0_WI_H_MASK 0xFFu
Kojto 90:cb3d968589d8 8085 #define UART_WP7816A_T0_WI_H_SHIFT 0
Kojto 90:cb3d968589d8 8086 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
Kojto 90:cb3d968589d8 8087 /* WP7816B_T0 Bit Fields */
Kojto 90:cb3d968589d8 8088 #define UART_WP7816B_T0_WI_L_MASK 0xFFu
Kojto 90:cb3d968589d8 8089 #define UART_WP7816B_T0_WI_L_SHIFT 0
Kojto 90:cb3d968589d8 8090 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
Kojto 90:cb3d968589d8 8091 /* WP7816A_T1 Bit Fields */
Kojto 90:cb3d968589d8 8092 #define UART_WP7816A_T1_BWI_H_MASK 0xFFu
Kojto 90:cb3d968589d8 8093 #define UART_WP7816A_T1_BWI_H_SHIFT 0
Kojto 90:cb3d968589d8 8094 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
Kojto 90:cb3d968589d8 8095 /* WP7816B_T1 Bit Fields */
Kojto 90:cb3d968589d8 8096 #define UART_WP7816B_T1_BWI_L_MASK 0xFFu
Kojto 90:cb3d968589d8 8097 #define UART_WP7816B_T1_BWI_L_SHIFT 0
Kojto 90:cb3d968589d8 8098 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
Kojto 90:cb3d968589d8 8099 /* WGP7816_T1 Bit Fields */
Kojto 90:cb3d968589d8 8100 #define UART_WGP7816_T1_BGI_MASK 0xFu
Kojto 90:cb3d968589d8 8101 #define UART_WGP7816_T1_BGI_SHIFT 0
Kojto 90:cb3d968589d8 8102 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
Kojto 90:cb3d968589d8 8103 #define UART_WGP7816_T1_CWI1_MASK 0xF0u
Kojto 90:cb3d968589d8 8104 #define UART_WGP7816_T1_CWI1_SHIFT 4
Kojto 90:cb3d968589d8 8105 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
Kojto 90:cb3d968589d8 8106 /* WP7816C_T1 Bit Fields */
Kojto 90:cb3d968589d8 8107 #define UART_WP7816C_T1_CWI2_MASK 0x1Fu
Kojto 90:cb3d968589d8 8108 #define UART_WP7816C_T1_CWI2_SHIFT 0
Kojto 90:cb3d968589d8 8109 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
Kojto 90:cb3d968589d8 8110
Kojto 90:cb3d968589d8 8111 /*!
Kojto 90:cb3d968589d8 8112 * @}
Kojto 90:cb3d968589d8 8113 */ /* end of group UART_Register_Masks */
Kojto 90:cb3d968589d8 8114
Kojto 90:cb3d968589d8 8115
Kojto 90:cb3d968589d8 8116 /* UART - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 8117 /** Peripheral UART2 base address */
Kojto 90:cb3d968589d8 8118 #define UART2_BASE (0x4006C000u)
Kojto 90:cb3d968589d8 8119 /** Peripheral UART2 base pointer */
Kojto 90:cb3d968589d8 8120 #define UART2 ((UART_Type *)UART2_BASE)
Kojto 90:cb3d968589d8 8121 #define UART2_BASE_PTR (UART2)
Kojto 90:cb3d968589d8 8122 /** Array initializer of UART peripheral base addresses */
Kojto 90:cb3d968589d8 8123 #define UART_BASE_ADDRS { UART2_BASE }
Kojto 90:cb3d968589d8 8124 /** Array initializer of UART peripheral base pointers */
Kojto 90:cb3d968589d8 8125 #define UART_BASE_PTRS { UART2 }
Kojto 90:cb3d968589d8 8126 /** Interrupt vectors for the UART peripheral type */
Kojto 90:cb3d968589d8 8127 #define UART_RX_TX_IRQS { UART2_FLEXIO_IRQn }
Kojto 90:cb3d968589d8 8128 #define UART_ERR_IRQS { UART2_FLEXIO_IRQn }
Kojto 90:cb3d968589d8 8129
Kojto 90:cb3d968589d8 8130 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8131 -- UART - Register accessor macros
Kojto 90:cb3d968589d8 8132 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8133
Kojto 90:cb3d968589d8 8134 /*!
Kojto 90:cb3d968589d8 8135 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
Kojto 90:cb3d968589d8 8136 * @{
Kojto 90:cb3d968589d8 8137 */
Kojto 90:cb3d968589d8 8138
Kojto 90:cb3d968589d8 8139
Kojto 90:cb3d968589d8 8140 /* UART - Register instance definitions */
Kojto 90:cb3d968589d8 8141 /* UART2 */
Kojto 90:cb3d968589d8 8142 #define UART2_BDH UART_BDH_REG(UART2)
Kojto 90:cb3d968589d8 8143 #define UART2_BDL UART_BDL_REG(UART2)
Kojto 90:cb3d968589d8 8144 #define UART2_C1 UART_C1_REG(UART2)
Kojto 90:cb3d968589d8 8145 #define UART2_C2 UART_C2_REG(UART2)
Kojto 90:cb3d968589d8 8146 #define UART2_S1 UART_S1_REG(UART2)
Kojto 90:cb3d968589d8 8147 #define UART2_S2 UART_S2_REG(UART2)
Kojto 90:cb3d968589d8 8148 #define UART2_C3 UART_C3_REG(UART2)
Kojto 90:cb3d968589d8 8149 #define UART2_D UART_D_REG(UART2)
Kojto 90:cb3d968589d8 8150 #define UART2_MA1 UART_MA1_REG(UART2)
Kojto 90:cb3d968589d8 8151 #define UART2_MA2 UART_MA2_REG(UART2)
Kojto 90:cb3d968589d8 8152 #define UART2_C4 UART_C4_REG(UART2)
Kojto 90:cb3d968589d8 8153 #define UART2_C5 UART_C5_REG(UART2)
Kojto 90:cb3d968589d8 8154 #define UART2_C7816 UART_C7816_REG(UART2)
Kojto 90:cb3d968589d8 8155 #define UART2_IE7816 UART_IE7816_REG(UART2)
Kojto 90:cb3d968589d8 8156 #define UART2_IS7816 UART_IS7816_REG(UART2)
Kojto 90:cb3d968589d8 8157 #define UART2_WP7816 UART_WP7816_REG(UART2)
Kojto 90:cb3d968589d8 8158 #define UART2_WN7816 UART_WN7816_REG(UART2)
Kojto 90:cb3d968589d8 8159 #define UART2_WF7816 UART_WF7816_REG(UART2)
Kojto 90:cb3d968589d8 8160 #define UART2_ET7816 UART_ET7816_REG(UART2)
Kojto 90:cb3d968589d8 8161 #define UART2_TL7816 UART_TL7816_REG(UART2)
Kojto 90:cb3d968589d8 8162 #define UART2_AP7816A_T0 UART_AP7816A_T0_REG(UART2)
Kojto 90:cb3d968589d8 8163 #define UART2_AP7816B_T0 UART_AP7816B_T0_REG(UART2)
Kojto 90:cb3d968589d8 8164 #define UART2_WP7816A_T0 UART_WP7816A_T0_REG(UART2)
Kojto 90:cb3d968589d8 8165 #define UART2_WP7816A_T1 UART_WP7816A_T1_REG(UART2)
Kojto 90:cb3d968589d8 8166 #define UART2_WP7816B_T0 UART_WP7816B_T0_REG(UART2)
Kojto 90:cb3d968589d8 8167 #define UART2_WP7816B_T1 UART_WP7816B_T1_REG(UART2)
Kojto 90:cb3d968589d8 8168 #define UART2_WGP7816_T1 UART_WGP7816_T1_REG(UART2)
Kojto 90:cb3d968589d8 8169 #define UART2_WP7816C_T1 UART_WP7816C_T1_REG(UART2)
Kojto 90:cb3d968589d8 8170
Kojto 90:cb3d968589d8 8171 /*!
Kojto 90:cb3d968589d8 8172 * @}
Kojto 90:cb3d968589d8 8173 */ /* end of group UART_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8174
Kojto 90:cb3d968589d8 8175
Kojto 90:cb3d968589d8 8176 /*!
Kojto 90:cb3d968589d8 8177 * @}
Kojto 90:cb3d968589d8 8178 */ /* end of group UART_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 8179
Kojto 90:cb3d968589d8 8180
Kojto 90:cb3d968589d8 8181 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8182 -- USB Peripheral Access Layer
Kojto 90:cb3d968589d8 8183 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8184
Kojto 90:cb3d968589d8 8185 /*!
Kojto 90:cb3d968589d8 8186 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
Kojto 90:cb3d968589d8 8187 * @{
Kojto 90:cb3d968589d8 8188 */
Kojto 90:cb3d968589d8 8189
Kojto 90:cb3d968589d8 8190 /** USB - Register Layout Typedef */
Kojto 90:cb3d968589d8 8191 typedef struct {
Kojto 90:cb3d968589d8 8192 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
Kojto 90:cb3d968589d8 8193 uint8_t RESERVED_0[3];
Kojto 90:cb3d968589d8 8194 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
Kojto 90:cb3d968589d8 8195 uint8_t RESERVED_1[3];
Kojto 90:cb3d968589d8 8196 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
Kojto 90:cb3d968589d8 8197 uint8_t RESERVED_2[3];
Kojto 90:cb3d968589d8 8198 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
Kojto 90:cb3d968589d8 8199 uint8_t RESERVED_3[15];
Kojto 90:cb3d968589d8 8200 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
Kojto 90:cb3d968589d8 8201 uint8_t RESERVED_4[99];
Kojto 90:cb3d968589d8 8202 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
Kojto 90:cb3d968589d8 8203 uint8_t RESERVED_5[3];
Kojto 90:cb3d968589d8 8204 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
Kojto 90:cb3d968589d8 8205 uint8_t RESERVED_6[3];
Kojto 90:cb3d968589d8 8206 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
Kojto 90:cb3d968589d8 8207 uint8_t RESERVED_7[3];
Kojto 90:cb3d968589d8 8208 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
Kojto 90:cb3d968589d8 8209 uint8_t RESERVED_8[3];
Kojto 90:cb3d968589d8 8210 __I uint8_t STAT; /**< Status register, offset: 0x90 */
Kojto 90:cb3d968589d8 8211 uint8_t RESERVED_9[3];
Kojto 90:cb3d968589d8 8212 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
Kojto 90:cb3d968589d8 8213 uint8_t RESERVED_10[3];
Kojto 90:cb3d968589d8 8214 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
Kojto 90:cb3d968589d8 8215 uint8_t RESERVED_11[3];
Kojto 90:cb3d968589d8 8216 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
Kojto 90:cb3d968589d8 8217 uint8_t RESERVED_12[3];
Kojto 90:cb3d968589d8 8218 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
Kojto 90:cb3d968589d8 8219 uint8_t RESERVED_13[3];
Kojto 90:cb3d968589d8 8220 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
Kojto 90:cb3d968589d8 8221 uint8_t RESERVED_14[11];
Kojto 90:cb3d968589d8 8222 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
Kojto 90:cb3d968589d8 8223 uint8_t RESERVED_15[3];
Kojto 90:cb3d968589d8 8224 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
Kojto 90:cb3d968589d8 8225 uint8_t RESERVED_16[11];
Kojto 90:cb3d968589d8 8226 struct { /* offset: 0xC0, array step: 0x4 */
Kojto 90:cb3d968589d8 8227 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
Kojto 90:cb3d968589d8 8228 uint8_t RESERVED_0[3];
Kojto 90:cb3d968589d8 8229 } ENDPOINT[16];
Kojto 90:cb3d968589d8 8230 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
Kojto 90:cb3d968589d8 8231 uint8_t RESERVED_17[3];
Kojto 90:cb3d968589d8 8232 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
Kojto 90:cb3d968589d8 8233 uint8_t RESERVED_18[3];
Kojto 90:cb3d968589d8 8234 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
Kojto 90:cb3d968589d8 8235 uint8_t RESERVED_19[3];
Kojto 90:cb3d968589d8 8236 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
Kojto 90:cb3d968589d8 8237 uint8_t RESERVED_20[7];
Kojto 90:cb3d968589d8 8238 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
Kojto 90:cb3d968589d8 8239 uint8_t RESERVED_21[43];
Kojto 90:cb3d968589d8 8240 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
Kojto 90:cb3d968589d8 8241 uint8_t RESERVED_22[3];
Kojto 90:cb3d968589d8 8242 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
Kojto 90:cb3d968589d8 8243 uint8_t RESERVED_23[15];
Kojto 90:cb3d968589d8 8244 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
Kojto 90:cb3d968589d8 8245 uint8_t RESERVED_24[7];
Kojto 90:cb3d968589d8 8246 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
Kojto 90:cb3d968589d8 8247 } USB_Type, *USB_MemMapPtr;
Kojto 90:cb3d968589d8 8248
Kojto 90:cb3d968589d8 8249 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8250 -- USB - Register accessor macros
Kojto 90:cb3d968589d8 8251 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8252
Kojto 90:cb3d968589d8 8253 /*!
Kojto 90:cb3d968589d8 8254 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
Kojto 90:cb3d968589d8 8255 * @{
Kojto 90:cb3d968589d8 8256 */
Kojto 90:cb3d968589d8 8257
Kojto 90:cb3d968589d8 8258
Kojto 90:cb3d968589d8 8259 /* USB - Register accessors */
Kojto 90:cb3d968589d8 8260 #define USB_PERID_REG(base) ((base)->PERID)
Kojto 90:cb3d968589d8 8261 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
Kojto 90:cb3d968589d8 8262 #define USB_REV_REG(base) ((base)->REV)
Kojto 90:cb3d968589d8 8263 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
Kojto 90:cb3d968589d8 8264 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
Kojto 90:cb3d968589d8 8265 #define USB_ISTAT_REG(base) ((base)->ISTAT)
Kojto 90:cb3d968589d8 8266 #define USB_INTEN_REG(base) ((base)->INTEN)
Kojto 90:cb3d968589d8 8267 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
Kojto 90:cb3d968589d8 8268 #define USB_ERREN_REG(base) ((base)->ERREN)
Kojto 90:cb3d968589d8 8269 #define USB_STAT_REG(base) ((base)->STAT)
Kojto 90:cb3d968589d8 8270 #define USB_CTL_REG(base) ((base)->CTL)
Kojto 90:cb3d968589d8 8271 #define USB_ADDR_REG(base) ((base)->ADDR)
Kojto 90:cb3d968589d8 8272 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
Kojto 90:cb3d968589d8 8273 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
Kojto 90:cb3d968589d8 8274 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
Kojto 90:cb3d968589d8 8275 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
Kojto 90:cb3d968589d8 8276 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
Kojto 90:cb3d968589d8 8277 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
Kojto 90:cb3d968589d8 8278 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
Kojto 90:cb3d968589d8 8279 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
Kojto 90:cb3d968589d8 8280 #define USB_CONTROL_REG(base) ((base)->CONTROL)
Kojto 90:cb3d968589d8 8281 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
Kojto 90:cb3d968589d8 8282 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
Kojto 90:cb3d968589d8 8283 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
Kojto 90:cb3d968589d8 8284 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
Kojto 90:cb3d968589d8 8285 #define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN)
Kojto 90:cb3d968589d8 8286 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
Kojto 90:cb3d968589d8 8287
Kojto 90:cb3d968589d8 8288 /*!
Kojto 90:cb3d968589d8 8289 * @}
Kojto 90:cb3d968589d8 8290 */ /* end of group USB_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8291
Kojto 90:cb3d968589d8 8292
Kojto 90:cb3d968589d8 8293 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8294 -- USB Register Masks
Kojto 90:cb3d968589d8 8295 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8296
Kojto 90:cb3d968589d8 8297 /*!
Kojto 90:cb3d968589d8 8298 * @addtogroup USB_Register_Masks USB Register Masks
Kojto 90:cb3d968589d8 8299 * @{
Kojto 90:cb3d968589d8 8300 */
Kojto 90:cb3d968589d8 8301
Kojto 90:cb3d968589d8 8302 /* PERID Bit Fields */
Kojto 90:cb3d968589d8 8303 #define USB_PERID_ID_MASK 0x3Fu
Kojto 90:cb3d968589d8 8304 #define USB_PERID_ID_SHIFT 0
Kojto 90:cb3d968589d8 8305 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
Kojto 90:cb3d968589d8 8306 /* IDCOMP Bit Fields */
Kojto 90:cb3d968589d8 8307 #define USB_IDCOMP_NID_MASK 0x3Fu
Kojto 90:cb3d968589d8 8308 #define USB_IDCOMP_NID_SHIFT 0
Kojto 90:cb3d968589d8 8309 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
Kojto 90:cb3d968589d8 8310 /* REV Bit Fields */
Kojto 90:cb3d968589d8 8311 #define USB_REV_REV_MASK 0xFFu
Kojto 90:cb3d968589d8 8312 #define USB_REV_REV_SHIFT 0
Kojto 90:cb3d968589d8 8313 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
Kojto 90:cb3d968589d8 8314 /* ADDINFO Bit Fields */
Kojto 90:cb3d968589d8 8315 #define USB_ADDINFO_IEHOST_MASK 0x1u
Kojto 90:cb3d968589d8 8316 #define USB_ADDINFO_IEHOST_SHIFT 0
Kojto 90:cb3d968589d8 8317 /* OTGCTL Bit Fields */
Kojto 90:cb3d968589d8 8318 #define USB_OTGCTL_DPHIGH_MASK 0x80u
Kojto 90:cb3d968589d8 8319 #define USB_OTGCTL_DPHIGH_SHIFT 7
Kojto 90:cb3d968589d8 8320 /* ISTAT Bit Fields */
Kojto 90:cb3d968589d8 8321 #define USB_ISTAT_USBRST_MASK 0x1u
Kojto 90:cb3d968589d8 8322 #define USB_ISTAT_USBRST_SHIFT 0
Kojto 90:cb3d968589d8 8323 #define USB_ISTAT_ERROR_MASK 0x2u
Kojto 90:cb3d968589d8 8324 #define USB_ISTAT_ERROR_SHIFT 1
Kojto 90:cb3d968589d8 8325 #define USB_ISTAT_SOFTOK_MASK 0x4u
Kojto 90:cb3d968589d8 8326 #define USB_ISTAT_SOFTOK_SHIFT 2
Kojto 90:cb3d968589d8 8327 #define USB_ISTAT_TOKDNE_MASK 0x8u
Kojto 90:cb3d968589d8 8328 #define USB_ISTAT_TOKDNE_SHIFT 3
Kojto 90:cb3d968589d8 8329 #define USB_ISTAT_SLEEP_MASK 0x10u
Kojto 90:cb3d968589d8 8330 #define USB_ISTAT_SLEEP_SHIFT 4
Kojto 90:cb3d968589d8 8331 #define USB_ISTAT_RESUME_MASK 0x20u
Kojto 90:cb3d968589d8 8332 #define USB_ISTAT_RESUME_SHIFT 5
Kojto 90:cb3d968589d8 8333 #define USB_ISTAT_STALL_MASK 0x80u
Kojto 90:cb3d968589d8 8334 #define USB_ISTAT_STALL_SHIFT 7
Kojto 90:cb3d968589d8 8335 /* INTEN Bit Fields */
Kojto 90:cb3d968589d8 8336 #define USB_INTEN_USBRSTEN_MASK 0x1u
Kojto 90:cb3d968589d8 8337 #define USB_INTEN_USBRSTEN_SHIFT 0
Kojto 90:cb3d968589d8 8338 #define USB_INTEN_ERROREN_MASK 0x2u
Kojto 90:cb3d968589d8 8339 #define USB_INTEN_ERROREN_SHIFT 1
Kojto 90:cb3d968589d8 8340 #define USB_INTEN_SOFTOKEN_MASK 0x4u
Kojto 90:cb3d968589d8 8341 #define USB_INTEN_SOFTOKEN_SHIFT 2
Kojto 90:cb3d968589d8 8342 #define USB_INTEN_TOKDNEEN_MASK 0x8u
Kojto 90:cb3d968589d8 8343 #define USB_INTEN_TOKDNEEN_SHIFT 3
Kojto 90:cb3d968589d8 8344 #define USB_INTEN_SLEEPEN_MASK 0x10u
Kojto 90:cb3d968589d8 8345 #define USB_INTEN_SLEEPEN_SHIFT 4
Kojto 90:cb3d968589d8 8346 #define USB_INTEN_RESUMEEN_MASK 0x20u
Kojto 90:cb3d968589d8 8347 #define USB_INTEN_RESUMEEN_SHIFT 5
Kojto 90:cb3d968589d8 8348 #define USB_INTEN_STALLEN_MASK 0x80u
Kojto 90:cb3d968589d8 8349 #define USB_INTEN_STALLEN_SHIFT 7
Kojto 90:cb3d968589d8 8350 /* ERRSTAT Bit Fields */
Kojto 90:cb3d968589d8 8351 #define USB_ERRSTAT_PIDERR_MASK 0x1u
Kojto 90:cb3d968589d8 8352 #define USB_ERRSTAT_PIDERR_SHIFT 0
Kojto 90:cb3d968589d8 8353 #define USB_ERRSTAT_CRC5_MASK 0x2u
Kojto 90:cb3d968589d8 8354 #define USB_ERRSTAT_CRC5_SHIFT 1
Kojto 90:cb3d968589d8 8355 #define USB_ERRSTAT_CRC16_MASK 0x4u
Kojto 90:cb3d968589d8 8356 #define USB_ERRSTAT_CRC16_SHIFT 2
Kojto 90:cb3d968589d8 8357 #define USB_ERRSTAT_DFN8_MASK 0x8u
Kojto 90:cb3d968589d8 8358 #define USB_ERRSTAT_DFN8_SHIFT 3
Kojto 90:cb3d968589d8 8359 #define USB_ERRSTAT_BTOERR_MASK 0x10u
Kojto 90:cb3d968589d8 8360 #define USB_ERRSTAT_BTOERR_SHIFT 4
Kojto 90:cb3d968589d8 8361 #define USB_ERRSTAT_DMAERR_MASK 0x20u
Kojto 90:cb3d968589d8 8362 #define USB_ERRSTAT_DMAERR_SHIFT 5
Kojto 90:cb3d968589d8 8363 #define USB_ERRSTAT_BTSERR_MASK 0x80u
Kojto 90:cb3d968589d8 8364 #define USB_ERRSTAT_BTSERR_SHIFT 7
Kojto 90:cb3d968589d8 8365 /* ERREN Bit Fields */
Kojto 90:cb3d968589d8 8366 #define USB_ERREN_PIDERREN_MASK 0x1u
Kojto 90:cb3d968589d8 8367 #define USB_ERREN_PIDERREN_SHIFT 0
Kojto 90:cb3d968589d8 8368 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
Kojto 90:cb3d968589d8 8369 #define USB_ERREN_CRC5EOFEN_SHIFT 1
Kojto 90:cb3d968589d8 8370 #define USB_ERREN_CRC16EN_MASK 0x4u
Kojto 90:cb3d968589d8 8371 #define USB_ERREN_CRC16EN_SHIFT 2
Kojto 90:cb3d968589d8 8372 #define USB_ERREN_DFN8EN_MASK 0x8u
Kojto 90:cb3d968589d8 8373 #define USB_ERREN_DFN8EN_SHIFT 3
Kojto 90:cb3d968589d8 8374 #define USB_ERREN_BTOERREN_MASK 0x10u
Kojto 90:cb3d968589d8 8375 #define USB_ERREN_BTOERREN_SHIFT 4
Kojto 90:cb3d968589d8 8376 #define USB_ERREN_DMAERREN_MASK 0x20u
Kojto 90:cb3d968589d8 8377 #define USB_ERREN_DMAERREN_SHIFT 5
Kojto 90:cb3d968589d8 8378 #define USB_ERREN_BTSERREN_MASK 0x80u
Kojto 90:cb3d968589d8 8379 #define USB_ERREN_BTSERREN_SHIFT 7
Kojto 90:cb3d968589d8 8380 /* STAT Bit Fields */
Kojto 90:cb3d968589d8 8381 #define USB_STAT_ODD_MASK 0x4u
Kojto 90:cb3d968589d8 8382 #define USB_STAT_ODD_SHIFT 2
Kojto 90:cb3d968589d8 8383 #define USB_STAT_TX_MASK 0x8u
Kojto 90:cb3d968589d8 8384 #define USB_STAT_TX_SHIFT 3
Kojto 90:cb3d968589d8 8385 #define USB_STAT_ENDP_MASK 0xF0u
Kojto 90:cb3d968589d8 8386 #define USB_STAT_ENDP_SHIFT 4
Kojto 90:cb3d968589d8 8387 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
Kojto 90:cb3d968589d8 8388 /* CTL Bit Fields */
Kojto 90:cb3d968589d8 8389 #define USB_CTL_USBENSOFEN_MASK 0x1u
Kojto 90:cb3d968589d8 8390 #define USB_CTL_USBENSOFEN_SHIFT 0
Kojto 90:cb3d968589d8 8391 #define USB_CTL_ODDRST_MASK 0x2u
Kojto 90:cb3d968589d8 8392 #define USB_CTL_ODDRST_SHIFT 1
Kojto 90:cb3d968589d8 8393 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
Kojto 90:cb3d968589d8 8394 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
Kojto 90:cb3d968589d8 8395 #define USB_CTL_SE0_MASK 0x40u
Kojto 90:cb3d968589d8 8396 #define USB_CTL_SE0_SHIFT 6
Kojto 90:cb3d968589d8 8397 #define USB_CTL_JSTATE_MASK 0x80u
Kojto 90:cb3d968589d8 8398 #define USB_CTL_JSTATE_SHIFT 7
Kojto 90:cb3d968589d8 8399 /* ADDR Bit Fields */
Kojto 90:cb3d968589d8 8400 #define USB_ADDR_ADDR_MASK 0x7Fu
Kojto 90:cb3d968589d8 8401 #define USB_ADDR_ADDR_SHIFT 0
Kojto 90:cb3d968589d8 8402 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
Kojto 90:cb3d968589d8 8403 /* BDTPAGE1 Bit Fields */
Kojto 90:cb3d968589d8 8404 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
Kojto 90:cb3d968589d8 8405 #define USB_BDTPAGE1_BDTBA_SHIFT 1
Kojto 90:cb3d968589d8 8406 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
Kojto 90:cb3d968589d8 8407 /* FRMNUML Bit Fields */
Kojto 90:cb3d968589d8 8408 #define USB_FRMNUML_FRM_MASK 0xFFu
Kojto 90:cb3d968589d8 8409 #define USB_FRMNUML_FRM_SHIFT 0
Kojto 90:cb3d968589d8 8410 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
Kojto 90:cb3d968589d8 8411 /* FRMNUMH Bit Fields */
Kojto 90:cb3d968589d8 8412 #define USB_FRMNUMH_FRM_MASK 0x7u
Kojto 90:cb3d968589d8 8413 #define USB_FRMNUMH_FRM_SHIFT 0
Kojto 90:cb3d968589d8 8414 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
Kojto 90:cb3d968589d8 8415 /* BDTPAGE2 Bit Fields */
Kojto 90:cb3d968589d8 8416 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
Kojto 90:cb3d968589d8 8417 #define USB_BDTPAGE2_BDTBA_SHIFT 0
Kojto 90:cb3d968589d8 8418 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
Kojto 90:cb3d968589d8 8419 /* BDTPAGE3 Bit Fields */
Kojto 90:cb3d968589d8 8420 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
Kojto 90:cb3d968589d8 8421 #define USB_BDTPAGE3_BDTBA_SHIFT 0
Kojto 90:cb3d968589d8 8422 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
Kojto 90:cb3d968589d8 8423 /* ENDPT Bit Fields */
Kojto 90:cb3d968589d8 8424 #define USB_ENDPT_EPHSHK_MASK 0x1u
Kojto 90:cb3d968589d8 8425 #define USB_ENDPT_EPHSHK_SHIFT 0
Kojto 90:cb3d968589d8 8426 #define USB_ENDPT_EPSTALL_MASK 0x2u
Kojto 90:cb3d968589d8 8427 #define USB_ENDPT_EPSTALL_SHIFT 1
Kojto 90:cb3d968589d8 8428 #define USB_ENDPT_EPTXEN_MASK 0x4u
Kojto 90:cb3d968589d8 8429 #define USB_ENDPT_EPTXEN_SHIFT 2
Kojto 90:cb3d968589d8 8430 #define USB_ENDPT_EPRXEN_MASK 0x8u
Kojto 90:cb3d968589d8 8431 #define USB_ENDPT_EPRXEN_SHIFT 3
Kojto 90:cb3d968589d8 8432 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
Kojto 90:cb3d968589d8 8433 #define USB_ENDPT_EPCTLDIS_SHIFT 4
Kojto 90:cb3d968589d8 8434 /* USBCTRL Bit Fields */
Kojto 90:cb3d968589d8 8435 #define USB_USBCTRL_PDE_MASK 0x40u
Kojto 90:cb3d968589d8 8436 #define USB_USBCTRL_PDE_SHIFT 6
Kojto 90:cb3d968589d8 8437 #define USB_USBCTRL_SUSP_MASK 0x80u
Kojto 90:cb3d968589d8 8438 #define USB_USBCTRL_SUSP_SHIFT 7
Kojto 90:cb3d968589d8 8439 /* OBSERVE Bit Fields */
Kojto 90:cb3d968589d8 8440 #define USB_OBSERVE_DMPD_MASK 0x10u
Kojto 90:cb3d968589d8 8441 #define USB_OBSERVE_DMPD_SHIFT 4
Kojto 90:cb3d968589d8 8442 #define USB_OBSERVE_DPPD_MASK 0x40u
Kojto 90:cb3d968589d8 8443 #define USB_OBSERVE_DPPD_SHIFT 6
Kojto 90:cb3d968589d8 8444 #define USB_OBSERVE_DPPU_MASK 0x80u
Kojto 90:cb3d968589d8 8445 #define USB_OBSERVE_DPPU_SHIFT 7
Kojto 90:cb3d968589d8 8446 /* CONTROL Bit Fields */
Kojto 90:cb3d968589d8 8447 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
Kojto 90:cb3d968589d8 8448 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
Kojto 90:cb3d968589d8 8449 /* USBTRC0 Bit Fields */
Kojto 90:cb3d968589d8 8450 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
Kojto 90:cb3d968589d8 8451 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
Kojto 90:cb3d968589d8 8452 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
Kojto 90:cb3d968589d8 8453 #define USB_USBTRC0_SYNC_DET_SHIFT 1
Kojto 90:cb3d968589d8 8454 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
Kojto 90:cb3d968589d8 8455 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
Kojto 90:cb3d968589d8 8456 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
Kojto 90:cb3d968589d8 8457 #define USB_USBTRC0_USBRESMEN_SHIFT 5
Kojto 90:cb3d968589d8 8458 #define USB_USBTRC0_USBRESET_MASK 0x80u
Kojto 90:cb3d968589d8 8459 #define USB_USBTRC0_USBRESET_SHIFT 7
Kojto 90:cb3d968589d8 8460 /* USBFRMADJUST Bit Fields */
Kojto 90:cb3d968589d8 8461 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
Kojto 90:cb3d968589d8 8462 #define USB_USBFRMADJUST_ADJ_SHIFT 0
Kojto 90:cb3d968589d8 8463 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
Kojto 90:cb3d968589d8 8464 /* CLK_RECOVER_CTRL Bit Fields */
Kojto 90:cb3d968589d8 8465 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
Kojto 90:cb3d968589d8 8466 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
Kojto 90:cb3d968589d8 8467 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
Kojto 90:cb3d968589d8 8468 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
Kojto 90:cb3d968589d8 8469 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
Kojto 90:cb3d968589d8 8470 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
Kojto 90:cb3d968589d8 8471 /* CLK_RECOVER_IRC_EN Bit Fields */
Kojto 90:cb3d968589d8 8472 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
Kojto 90:cb3d968589d8 8473 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
Kojto 90:cb3d968589d8 8474 /* CLK_RECOVER_INT_EN Bit Fields */
Kojto 90:cb3d968589d8 8475 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
Kojto 90:cb3d968589d8 8476 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
Kojto 90:cb3d968589d8 8477 /* CLK_RECOVER_INT_STATUS Bit Fields */
Kojto 90:cb3d968589d8 8478 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
Kojto 90:cb3d968589d8 8479 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
Kojto 90:cb3d968589d8 8480
Kojto 90:cb3d968589d8 8481 /*!
Kojto 90:cb3d968589d8 8482 * @}
Kojto 90:cb3d968589d8 8483 */ /* end of group USB_Register_Masks */
Kojto 90:cb3d968589d8 8484
Kojto 90:cb3d968589d8 8485
Kojto 90:cb3d968589d8 8486 /* USB - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 8487 /** Peripheral USB0 base address */
Kojto 90:cb3d968589d8 8488 #define USB0_BASE (0x40072000u)
Kojto 90:cb3d968589d8 8489 /** Peripheral USB0 base pointer */
Kojto 90:cb3d968589d8 8490 #define USB0 ((USB_Type *)USB0_BASE)
Kojto 90:cb3d968589d8 8491 #define USB0_BASE_PTR (USB0)
Kojto 90:cb3d968589d8 8492 /** Array initializer of USB peripheral base addresses */
Kojto 90:cb3d968589d8 8493 #define USB_BASE_ADDRS { USB0_BASE }
Kojto 90:cb3d968589d8 8494 /** Array initializer of USB peripheral base pointers */
Kojto 90:cb3d968589d8 8495 #define USB_BASE_PTRS { USB0 }
Kojto 90:cb3d968589d8 8496 /** Interrupt vectors for the USB peripheral type */
Kojto 90:cb3d968589d8 8497 #define USB_IRQS { USB0_IRQn }
Kojto 90:cb3d968589d8 8498
Kojto 90:cb3d968589d8 8499 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8500 -- USB - Register accessor macros
Kojto 90:cb3d968589d8 8501 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8502
Kojto 90:cb3d968589d8 8503 /*!
Kojto 90:cb3d968589d8 8504 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
Kojto 90:cb3d968589d8 8505 * @{
Kojto 90:cb3d968589d8 8506 */
Kojto 90:cb3d968589d8 8507
Kojto 90:cb3d968589d8 8508
Kojto 90:cb3d968589d8 8509 /* USB - Register instance definitions */
Kojto 90:cb3d968589d8 8510 /* USB0 */
Kojto 90:cb3d968589d8 8511 #define USB0_PERID USB_PERID_REG(USB0)
Kojto 90:cb3d968589d8 8512 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
Kojto 90:cb3d968589d8 8513 #define USB0_REV USB_REV_REG(USB0)
Kojto 90:cb3d968589d8 8514 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
Kojto 90:cb3d968589d8 8515 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
Kojto 90:cb3d968589d8 8516 #define USB0_ISTAT USB_ISTAT_REG(USB0)
Kojto 90:cb3d968589d8 8517 #define USB0_INTEN USB_INTEN_REG(USB0)
Kojto 90:cb3d968589d8 8518 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
Kojto 90:cb3d968589d8 8519 #define USB0_ERREN USB_ERREN_REG(USB0)
Kojto 90:cb3d968589d8 8520 #define USB0_STAT USB_STAT_REG(USB0)
Kojto 90:cb3d968589d8 8521 #define USB0_CTL USB_CTL_REG(USB0)
Kojto 90:cb3d968589d8 8522 #define USB0_ADDR USB_ADDR_REG(USB0)
Kojto 90:cb3d968589d8 8523 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
Kojto 90:cb3d968589d8 8524 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
Kojto 90:cb3d968589d8 8525 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
Kojto 90:cb3d968589d8 8526 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
Kojto 90:cb3d968589d8 8527 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
Kojto 90:cb3d968589d8 8528 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
Kojto 90:cb3d968589d8 8529 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
Kojto 90:cb3d968589d8 8530 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
Kojto 90:cb3d968589d8 8531 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
Kojto 90:cb3d968589d8 8532 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
Kojto 90:cb3d968589d8 8533 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
Kojto 90:cb3d968589d8 8534 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
Kojto 90:cb3d968589d8 8535 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
Kojto 90:cb3d968589d8 8536 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
Kojto 90:cb3d968589d8 8537 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
Kojto 90:cb3d968589d8 8538 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
Kojto 90:cb3d968589d8 8539 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
Kojto 90:cb3d968589d8 8540 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
Kojto 90:cb3d968589d8 8541 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
Kojto 90:cb3d968589d8 8542 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
Kojto 90:cb3d968589d8 8543 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
Kojto 90:cb3d968589d8 8544 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
Kojto 90:cb3d968589d8 8545 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
Kojto 90:cb3d968589d8 8546 #define USB0_CONTROL USB_CONTROL_REG(USB0)
Kojto 90:cb3d968589d8 8547 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
Kojto 90:cb3d968589d8 8548 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
Kojto 90:cb3d968589d8 8549 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
Kojto 90:cb3d968589d8 8550 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
Kojto 90:cb3d968589d8 8551 #define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0)
Kojto 90:cb3d968589d8 8552 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
Kojto 90:cb3d968589d8 8553
Kojto 90:cb3d968589d8 8554 /* USB - Register array accessors */
Kojto 90:cb3d968589d8 8555 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
Kojto 90:cb3d968589d8 8556
Kojto 90:cb3d968589d8 8557 /*!
Kojto 90:cb3d968589d8 8558 * @}
Kojto 90:cb3d968589d8 8559 */ /* end of group USB_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8560
Kojto 90:cb3d968589d8 8561
Kojto 90:cb3d968589d8 8562 /*!
Kojto 90:cb3d968589d8 8563 * @}
Kojto 90:cb3d968589d8 8564 */ /* end of group USB_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 8565
Kojto 90:cb3d968589d8 8566
Kojto 90:cb3d968589d8 8567 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8568 -- VREF Peripheral Access Layer
Kojto 90:cb3d968589d8 8569 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8570
Kojto 90:cb3d968589d8 8571 /*!
Kojto 90:cb3d968589d8 8572 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
Kojto 90:cb3d968589d8 8573 * @{
Kojto 90:cb3d968589d8 8574 */
Kojto 90:cb3d968589d8 8575
Kojto 90:cb3d968589d8 8576 /** VREF - Register Layout Typedef */
Kojto 90:cb3d968589d8 8577 typedef struct {
Kojto 90:cb3d968589d8 8578 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
Kojto 90:cb3d968589d8 8579 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
Kojto 90:cb3d968589d8 8580 } VREF_Type, *VREF_MemMapPtr;
Kojto 90:cb3d968589d8 8581
Kojto 90:cb3d968589d8 8582 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8583 -- VREF - Register accessor macros
Kojto 90:cb3d968589d8 8584 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8585
Kojto 90:cb3d968589d8 8586 /*!
Kojto 90:cb3d968589d8 8587 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
Kojto 90:cb3d968589d8 8588 * @{
Kojto 90:cb3d968589d8 8589 */
Kojto 90:cb3d968589d8 8590
Kojto 90:cb3d968589d8 8591
Kojto 90:cb3d968589d8 8592 /* VREF - Register accessors */
Kojto 90:cb3d968589d8 8593 #define VREF_TRM_REG(base) ((base)->TRM)
Kojto 90:cb3d968589d8 8594 #define VREF_SC_REG(base) ((base)->SC)
Kojto 90:cb3d968589d8 8595
Kojto 90:cb3d968589d8 8596 /*!
Kojto 90:cb3d968589d8 8597 * @}
Kojto 90:cb3d968589d8 8598 */ /* end of group VREF_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8599
Kojto 90:cb3d968589d8 8600
Kojto 90:cb3d968589d8 8601 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8602 -- VREF Register Masks
Kojto 90:cb3d968589d8 8603 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8604
Kojto 90:cb3d968589d8 8605 /*!
Kojto 90:cb3d968589d8 8606 * @addtogroup VREF_Register_Masks VREF Register Masks
Kojto 90:cb3d968589d8 8607 * @{
Kojto 90:cb3d968589d8 8608 */
Kojto 90:cb3d968589d8 8609
Kojto 90:cb3d968589d8 8610 /* TRM Bit Fields */
Kojto 90:cb3d968589d8 8611 #define VREF_TRM_TRIM_MASK 0x3Fu
Kojto 90:cb3d968589d8 8612 #define VREF_TRM_TRIM_SHIFT 0
Kojto 90:cb3d968589d8 8613 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
Kojto 90:cb3d968589d8 8614 #define VREF_TRM_CHOPEN_MASK 0x40u
Kojto 90:cb3d968589d8 8615 #define VREF_TRM_CHOPEN_SHIFT 6
Kojto 90:cb3d968589d8 8616 /* SC Bit Fields */
Kojto 90:cb3d968589d8 8617 #define VREF_SC_MODE_LV_MASK 0x3u
Kojto 90:cb3d968589d8 8618 #define VREF_SC_MODE_LV_SHIFT 0
Kojto 90:cb3d968589d8 8619 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
Kojto 90:cb3d968589d8 8620 #define VREF_SC_VREFST_MASK 0x4u
Kojto 90:cb3d968589d8 8621 #define VREF_SC_VREFST_SHIFT 2
Kojto 90:cb3d968589d8 8622 #define VREF_SC_ICOMPEN_MASK 0x20u
Kojto 90:cb3d968589d8 8623 #define VREF_SC_ICOMPEN_SHIFT 5
Kojto 90:cb3d968589d8 8624 #define VREF_SC_REGEN_MASK 0x40u
Kojto 90:cb3d968589d8 8625 #define VREF_SC_REGEN_SHIFT 6
Kojto 90:cb3d968589d8 8626 #define VREF_SC_VREFEN_MASK 0x80u
Kojto 90:cb3d968589d8 8627 #define VREF_SC_VREFEN_SHIFT 7
Kojto 90:cb3d968589d8 8628
Kojto 90:cb3d968589d8 8629 /*!
Kojto 90:cb3d968589d8 8630 * @}
Kojto 90:cb3d968589d8 8631 */ /* end of group VREF_Register_Masks */
Kojto 90:cb3d968589d8 8632
Kojto 90:cb3d968589d8 8633
Kojto 90:cb3d968589d8 8634 /* VREF - Peripheral instance base addresses */
Kojto 90:cb3d968589d8 8635 /** Peripheral VREF base address */
Kojto 90:cb3d968589d8 8636 #define VREF_BASE (0x40074000u)
Kojto 90:cb3d968589d8 8637 /** Peripheral VREF base pointer */
Kojto 90:cb3d968589d8 8638 #define VREF ((VREF_Type *)VREF_BASE)
Kojto 90:cb3d968589d8 8639 #define VREF_BASE_PTR (VREF)
Kojto 90:cb3d968589d8 8640 /** Array initializer of VREF peripheral base addresses */
Kojto 90:cb3d968589d8 8641 #define VREF_BASE_ADDRS { VREF_BASE }
Kojto 90:cb3d968589d8 8642 /** Array initializer of VREF peripheral base pointers */
Kojto 90:cb3d968589d8 8643 #define VREF_BASE_PTRS { VREF }
Kojto 90:cb3d968589d8 8644
Kojto 90:cb3d968589d8 8645 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8646 -- VREF - Register accessor macros
Kojto 90:cb3d968589d8 8647 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8648
Kojto 90:cb3d968589d8 8649 /*!
Kojto 90:cb3d968589d8 8650 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
Kojto 90:cb3d968589d8 8651 * @{
Kojto 90:cb3d968589d8 8652 */
Kojto 90:cb3d968589d8 8653
Kojto 90:cb3d968589d8 8654
Kojto 90:cb3d968589d8 8655 /* VREF - Register instance definitions */
Kojto 90:cb3d968589d8 8656 /* VREF */
Kojto 90:cb3d968589d8 8657 #define VREF_TRM VREF_TRM_REG(VREF)
Kojto 90:cb3d968589d8 8658 #define VREF_SC VREF_SC_REG(VREF)
Kojto 90:cb3d968589d8 8659
Kojto 90:cb3d968589d8 8660 /*!
Kojto 90:cb3d968589d8 8661 * @}
Kojto 90:cb3d968589d8 8662 */ /* end of group VREF_Register_Accessor_Macros */
Kojto 90:cb3d968589d8 8663
Kojto 90:cb3d968589d8 8664
Kojto 90:cb3d968589d8 8665 /*!
Kojto 90:cb3d968589d8 8666 * @}
Kojto 90:cb3d968589d8 8667 */ /* end of group VREF_Peripheral_Access_Layer */
Kojto 90:cb3d968589d8 8668
Kojto 90:cb3d968589d8 8669
Kojto 90:cb3d968589d8 8670 /*
Kojto 90:cb3d968589d8 8671 ** End of section using anonymous unions
Kojto 90:cb3d968589d8 8672 */
Kojto 90:cb3d968589d8 8673
Kojto 90:cb3d968589d8 8674 #if defined(__ARMCC_VERSION)
Kojto 90:cb3d968589d8 8675 #pragma pop
Kojto 90:cb3d968589d8 8676 #elif defined(__CWCC__)
Kojto 90:cb3d968589d8 8677 #pragma pop
Kojto 90:cb3d968589d8 8678 #elif defined(__GNUC__)
Kojto 90:cb3d968589d8 8679 /* leave anonymous unions enabled */
Kojto 90:cb3d968589d8 8680 #elif defined(__IAR_SYSTEMS_ICC__)
Kojto 90:cb3d968589d8 8681 #pragma language=default
Kojto 90:cb3d968589d8 8682 #else
Kojto 90:cb3d968589d8 8683 #error Not supported compiler type
Kojto 90:cb3d968589d8 8684 #endif
Kojto 90:cb3d968589d8 8685
Kojto 90:cb3d968589d8 8686 /*!
Kojto 90:cb3d968589d8 8687 * @}
Kojto 90:cb3d968589d8 8688 */ /* end of group Peripheral_access_layer */
Kojto 90:cb3d968589d8 8689
Kojto 90:cb3d968589d8 8690
Kojto 90:cb3d968589d8 8691 /* ----------------------------------------------------------------------------
Kojto 90:cb3d968589d8 8692 -- Backward Compatibility
Kojto 90:cb3d968589d8 8693 ---------------------------------------------------------------------------- */
Kojto 90:cb3d968589d8 8694
Kojto 90:cb3d968589d8 8695 /*!
Kojto 90:cb3d968589d8 8696 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
Kojto 90:cb3d968589d8 8697 * @{
Kojto 90:cb3d968589d8 8698 */
Kojto 90:cb3d968589d8 8699
Kojto 90:cb3d968589d8 8700 #define I2C_S1_RXAK_MASK I2C_S_RXAK_MASK
Kojto 90:cb3d968589d8 8701 #define I2C_S1_RXAK_SHIFT I2C_S_RXAK_SHIFT
Kojto 90:cb3d968589d8 8702 #define I2C_S1_IICIF_MASK I2C_S_IICIF_MASK
Kojto 90:cb3d968589d8 8703 #define I2C_S1_IICIF_SHIFT I2C_S_IICIF_SHIFTFT
Kojto 90:cb3d968589d8 8704 #define I2C_S1_SRW_MASK I2C_S_SRW_MASK
Kojto 90:cb3d968589d8 8705 #define I2C_S1_SRW_SHIFT I2C_S_SRW_SHIFT
Kojto 90:cb3d968589d8 8706 #define I2C_S1_RAM_MASK I2C_S_RAM_MASK
Kojto 90:cb3d968589d8 8707 #define I2C_S1_RAM_SHIFT I2C_S_RAM_SHIFT
Kojto 90:cb3d968589d8 8708 #define I2C_S1_ARBL_MASK I2C_S_ARBL_MASK
Kojto 90:cb3d968589d8 8709 #define I2C_S1_ARBL_SHIFT I2C_S_ARBL_SHIFT
Kojto 90:cb3d968589d8 8710 #define I2C_S1_BUSY_MASK I2C_S_BUSY_MASK
Kojto 90:cb3d968589d8 8711 #define I2C_S1_BUSY_SHIFT I2C_S_BUSY_SHIFT
Kojto 90:cb3d968589d8 8712 #define I2C_S1_IAAS_MASK I2C_S_IAAS_MASK
Kojto 90:cb3d968589d8 8713 #define I2C_S1_IAAS_SHIFT I2C_S_IAAS_SHIFT
Kojto 90:cb3d968589d8 8714 #define I2C_S1_TCF_MASK I2C_S_TCF_MASK
Kojto 90:cb3d968589d8 8715 #define I2C_S1_TCF_SHIFT I2C_S_TCF_SHIFT
Kojto 90:cb3d968589d8 8716 #define I2C_S1_REG(base) I2C_S_REG(base)
Kojto 90:cb3d968589d8 8717 #define I2C0_S1 I2C0_S
Kojto 90:cb3d968589d8 8718 #define I2C1_S1 I2C1_S
Kojto 90:cb3d968589d8 8719 #define ADC_BASES ADC_BASE_PTRS
Kojto 90:cb3d968589d8 8720 #define CMP_BASES CMP_BASE_PTRS
Kojto 90:cb3d968589d8 8721 #define DAC_BASES DAC_BASE_PTRS
Kojto 90:cb3d968589d8 8722 #define DMA_BASES DMA_BASE_PTRS
Kojto 90:cb3d968589d8 8723 #define DMAMUX_BASES DMAMUX_BASE_PTRS
Kojto 90:cb3d968589d8 8724 #define FLEXIO_BASES FLEXIO_BASE_PTRS
Kojto 90:cb3d968589d8 8725 #define FTFA_BASES FTFA_BASE_PTRS
Kojto 90:cb3d968589d8 8726 #define GPIO_BASES GPIO_BASE_PTRS
Kojto 90:cb3d968589d8 8727 #define I2C_BASES I2C_BASE_PTRS
Kojto 90:cb3d968589d8 8728 #define I2S_BASES I2S_BASE_PTRS
Kojto 90:cb3d968589d8 8729 #define LCD_BASES LCD_BASE_PTRS
Kojto 90:cb3d968589d8 8730 #define LLWU_BASES LLWU_BASE_PTRS
Kojto 90:cb3d968589d8 8731 #define LPTMR_BASES LPTMR_BASE_PTRS
Kojto 90:cb3d968589d8 8732 #define LPUART_BASES LPUART_BASE_PTRS
Kojto 90:cb3d968589d8 8733 #define MCG_BASES MCG_BASE_PTRS
Kojto 90:cb3d968589d8 8734 #define MCM_BASES MCM_BASE_PTRS
Kojto 90:cb3d968589d8 8735 #define MTB_BASES MTB_BASE_PTRS
Kojto 90:cb3d968589d8 8736 #define MTBDWT_BASES MTBDWT_BASE_PTRS
Kojto 90:cb3d968589d8 8737 #define NV_BASES NV_BASE_PTRS
Kojto 90:cb3d968589d8 8738 #define OSC_BASES OSC_BASE_PTRS
Kojto 90:cb3d968589d8 8739 #define PIT_BASES PIT_BASE_PTRS
Kojto 90:cb3d968589d8 8740 #define PMC_BASES PMC_BASE_PTRS
Kojto 90:cb3d968589d8 8741 #define PORT_BASES PORT_BASE_PTRS
Kojto 90:cb3d968589d8 8742 #define RCM_BASES RCM_BASE_PTRS
Kojto 90:cb3d968589d8 8743 #define ROM_BASES ROM_BASE_PTRS
Kojto 90:cb3d968589d8 8744 #define RTC_BASES RTC_BASE_PTRS
Kojto 90:cb3d968589d8 8745 #define SIM_BASES SIM_BASE_PTRS
Kojto 90:cb3d968589d8 8746 #define SMC_BASES SMC_BASE_PTRS
Kojto 90:cb3d968589d8 8747 #define SPI_BASES SPI_BASE_PTRS
Kojto 90:cb3d968589d8 8748 #define TPM_BASES TPM_BASE_PTRS
Kojto 90:cb3d968589d8 8749 #define UART_BASES UART_BASE_PTRS
Kojto 90:cb3d968589d8 8750 #define USB_BASES USB_BASE_PTRS
Kojto 90:cb3d968589d8 8751 #define VREF_BASES VREF_BASE_PTRS
Kojto 90:cb3d968589d8 8752 #define PTA_BASE_PTR GPIOA_BASE_PTR
Kojto 90:cb3d968589d8 8753 #define PTB_BASE_PTR GPIOB_BASE_PTR
Kojto 90:cb3d968589d8 8754 #define PTC_BASE_PTR GPIOC_BASE_PTR
Kojto 90:cb3d968589d8 8755 #define PTD_BASE_PTR GPIOD_BASE_PTR
Kojto 90:cb3d968589d8 8756 #define PTE_BASE_PTR GPIOE_BASE_PTR
Kojto 90:cb3d968589d8 8757 #define PTA_BASE GPIOA_BASE
Kojto 90:cb3d968589d8 8758 #define PTB_BASE GPIOB_BASE
Kojto 90:cb3d968589d8 8759 #define PTC_BASE GPIOC_BASE
Kojto 90:cb3d968589d8 8760 #define PTD_BASE GPIOD_BASE
Kojto 90:cb3d968589d8 8761 #define PTE_BASE GPIOE_BASE
Kojto 90:cb3d968589d8 8762 #define PTA GPIOA
Kojto 90:cb3d968589d8 8763 #define PTB GPIOB
Kojto 90:cb3d968589d8 8764 #define PTC GPIOC
Kojto 90:cb3d968589d8 8765 #define PTD GPIOD
Kojto 90:cb3d968589d8 8766 #define PTE GPIOE
Kojto 90:cb3d968589d8 8767 #define UART0_FLEXIO_IRQn UART2_FLEXIO_IRQn
Kojto 90:cb3d968589d8 8768 #define SIM_SOPT5_UART0ODE_MASK SIM_SOPT5_UART2ODE_MASK
Kojto 90:cb3d968589d8 8769 #define SIM_SOPT5_UART0ODE_SHIFT SIM_SOPT5_UART2ODE_SHIFT
Kojto 90:cb3d968589d8 8770 #define SIM_SCGC4_UART0_MASK SIM_SCGC4_UART2_MASK
Kojto 90:cb3d968589d8 8771 #define SIM_SCGC4_UART0_SHIFT SIM_SCGC4_UART2_SHIFT
Kojto 90:cb3d968589d8 8772 #define UART0_BASE UART2_BASE
Kojto 90:cb3d968589d8 8773 #define UART0 UART2
Kojto 90:cb3d968589d8 8774 #define UART0_BASE_PTR UART2_BASE_PTR
Kojto 90:cb3d968589d8 8775 #define UART0_BDH UART2_BDH
Kojto 90:cb3d968589d8 8776 #define UART0_BDL UART2_BDL
Kojto 90:cb3d968589d8 8777 #define UART0_C1 UART2_C1
Kojto 90:cb3d968589d8 8778 #define UART0_C2 UART2_C2
Kojto 90:cb3d968589d8 8779 #define UART0_S1 UART2_S1
Kojto 90:cb3d968589d8 8780 #define UART0_S2 UART2_S2
Kojto 90:cb3d968589d8 8781 #define UART0_C3 UART2_C3
Kojto 90:cb3d968589d8 8782 #define UART0_D UART2_D
Kojto 90:cb3d968589d8 8783 #define UART0_MA1 UART2_MA1
Kojto 90:cb3d968589d8 8784 #define UART0_MA2 UART2_MA2
Kojto 90:cb3d968589d8 8785 #define UART0_C4 UART2_C4
Kojto 90:cb3d968589d8 8786 #define UART0_C5 UART2_C5
Kojto 90:cb3d968589d8 8787 #define UART0_ED UART2_ED
Kojto 90:cb3d968589d8 8788 #define UART0_MODEM UART2_MODEM
Kojto 90:cb3d968589d8 8789 #define UART0_IR UART2_IR
Kojto 90:cb3d968589d8 8790 #define UART0_PFIFO UART2_PFIFO
Kojto 90:cb3d968589d8 8791 #define UART0_CFIFO UART2_CFIFO
Kojto 90:cb3d968589d8 8792 #define UART0_SFIFO UART2_SFIFO
Kojto 90:cb3d968589d8 8793 #define UART0_TWFIFO UART2_TWFIFO
Kojto 90:cb3d968589d8 8794 #define UART0_TCFIFO UART2_TCFIFO
Kojto 90:cb3d968589d8 8795 #define UART0_RWFIFO UART2_RWFIFO
Kojto 90:cb3d968589d8 8796 #define UART0_RCFIFO UART2_RCFIFO
Kojto 90:cb3d968589d8 8797 #define UART0_C7816 UART2_C7816
Kojto 90:cb3d968589d8 8798 #define UART0_IE7816 UART2_IE7816
Kojto 90:cb3d968589d8 8799 #define UART0_IS7816 UART2_IS7816
Kojto 90:cb3d968589d8 8800 #define UART0_WP7816 UART2_WP7816
Kojto 90:cb3d968589d8 8801 #define UART0_WN7816 UART2_WN7816
Kojto 90:cb3d968589d8 8802 #define UART0_WF7816 UART2_WF7816
Kojto 90:cb3d968589d8 8803 #define UART0_ET7816 UART2_ET7816
Kojto 90:cb3d968589d8 8804 #define UART0_TL7816 UART2_TL7816
Kojto 90:cb3d968589d8 8805 #define UART0_AP7816A_T0 UART2_AP7816A_T0
Kojto 90:cb3d968589d8 8806 #define UART0_AP7816B_T0 UART2_AP7816B_T0
Kojto 90:cb3d968589d8 8807 #define UART0_WP7816A_T0 UART2_WP7816A_T0
Kojto 90:cb3d968589d8 8808 #define UART0_WP7816A_T1 UART2_WP7816A_T1
Kojto 90:cb3d968589d8 8809 #define UART0_WP7816B_T0 UART2_WP7816B_T0
Kojto 90:cb3d968589d8 8810 #define UART0_WP7816B_T1 UART2_WP7816B_T1
Kojto 90:cb3d968589d8 8811 #define UART0_WGP7816_T1 UART2_WGP7816_T1
Kojto 90:cb3d968589d8 8812 #define UART0_WP7816C_T1 UART2_WP7816C_T1
Kojto 90:cb3d968589d8 8813 #define I2S0_MDR This_symb_has_been_deprecated
Kojto 90:cb3d968589d8 8814 #define I2S_MDR_DIVIDE_MASK This_symb_has_been_deprecated
Kojto 90:cb3d968589d8 8815 #define I2S_MDR_DIVIDE_SHIFT This_symb_has_been_deprecated
Kojto 90:cb3d968589d8 8816 #define I2S_MDR_DIVIDE(x) This_symb_has_been_deprecated
Kojto 90:cb3d968589d8 8817 #define I2S_MDR_FRACT_MASK This_symb_has_been_deprecated
Kojto 90:cb3d968589d8 8818 #define I2S_MDR_FRACT_SHIFT This_symb_has_been_deprecated
Kojto 90:cb3d968589d8 8819 #define I2S_MDR_FRACT(x) This_symb_has_been_deprecated
Kojto 90:cb3d968589d8 8820 #define I2S_MDR_REG(base) This_symb_has_been_deprecated
Kojto 90:cb3d968589d8 8821 #define CTL0 OTGCTL
Kojto 90:cb3d968589d8 8822 #define USB0_CTL0 USB0_OTGCTL
Kojto 90:cb3d968589d8 8823 #define USB_CTL0_REG(base) USB_OTGCTL_REG(base)
Kojto 90:cb3d968589d8 8824 #define USB_CTL0_DPHIGH_MASK USB_OTGCTL_DPHIGH_MASK
Kojto 90:cb3d968589d8 8825 #define USB_CTL0_DPHIGH_SHIFT USB_OTGCTL_DPHIGH_SHIFT
Kojto 90:cb3d968589d8 8826 #define CTL1 CTL
Kojto 90:cb3d968589d8 8827 #define USB0_CTL1 USB0_CTL
Kojto 90:cb3d968589d8 8828 #define USB_CTL1_REG(base) USB_CTL_REG(base)
Kojto 90:cb3d968589d8 8829 #define USB_CTL1_USBEN_MASK USB_CTL_USBEN_MASK
Kojto 90:cb3d968589d8 8830 #define USB_CTL1_USBEN_SHIFT USB_CTL_USBEN_SHIFT
Kojto 90:cb3d968589d8 8831 #define USB_CTL1_ODDRST_MASK USB_CTL_ODDRST_MASK
Kojto 90:cb3d968589d8 8832 #define USB_CTL1_ODDRST_SHIFT USB_CTL_ODDRST_SHIFT
Kojto 90:cb3d968589d8 8833 #define USB_CTL1_TXSUSPENDTOKENBUSY_MASK USB_CTL_TXSUSPENDTOKENBUSY_MASK
Kojto 90:cb3d968589d8 8834 #define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT USB_CTL_TXSUSPENDTOKENBUSY_SHIFT
Kojto 90:cb3d968589d8 8835 #define USB_CTL1_SE0_MASK USB_CTL_SE0_MASK
Kojto 90:cb3d968589d8 8836 #define USB_CTL1_SE0_SHIFT USB_CTL_SE0_SHIFT
Kojto 90:cb3d968589d8 8837 #define USB_CTL1_JSTATE_MASK USB_CTL_JSTATE_MASK
Kojto 90:cb3d968589d8 8838 #define USB_CTL1_JSTATE_SHIFT USB_CTL_JSTATE_SHIFT
Kojto 90:cb3d968589d8 8839 #define USB_CTL_USBEN_MASK USB_CTL_USBENSOFEN_MASK
Kojto 90:cb3d968589d8 8840 #define USB_CTL_USBEN_SHIFT USB_CTL_USBENSOFEN_SHIFT
Kojto 90:cb3d968589d8 8841
Kojto 90:cb3d968589d8 8842 /*!
Kojto 90:cb3d968589d8 8843 * @}
Kojto 90:cb3d968589d8 8844 */ /* end of group Backward_Compatibility_Symbols */
Kojto 90:cb3d968589d8 8845
Kojto 90:cb3d968589d8 8846
Kojto 90:cb3d968589d8 8847 #else /* #if !defined(MKL43Z4_H_) */
Kojto 90:cb3d968589d8 8848 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
Kojto 90:cb3d968589d8 8849 #if (MCU_MEM_MAP_VERSION != 0x0100u)
Kojto 90:cb3d968589d8 8850 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
Kojto 90:cb3d968589d8 8851 #warning There are included two not compatible versions of memory maps. Please check possible differences.
Kojto 90:cb3d968589d8 8852 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
Kojto 90:cb3d968589d8 8853 #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
Kojto 90:cb3d968589d8 8854 #endif /* #if !defined(MKL43Z4_H_) */
Kojto 90:cb3d968589d8 8855
Kojto 90:cb3d968589d8 8856 /* MKL43Z4.h, eof. */