Wim Huiskamp / Mbed 2 deprecated mbed_bus

Libraries and Example of mbed parallel bus using I2C port expanders

Dependencies:   HDSP253X mbed PCF8574_Bus

HDSP253X_Display.h@1:e180256ba6fb, 2011-09-17 (annotated)

Committer:
wim
Date:
Sat Sep 17 15:35:39 2011 +0000
Revision:
1:e180256ba6fb
Example of using the parallel bus to control a smart alphanumeric display

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wim 1:e180256ba6fb 1 /* HDSP253X_Display - Intelligent 8 digit 5x7 LED matrix display
wim 1:e180256ba6fb 2 *
wim 1:e180256ba6fb 3 * Copyright (c) 2011 Wim Huiskamp
wim 1:e180256ba6fb 4 * Modified software based on sourcecode by RAC 06/08/2008
wim 1:e180256ba6fb 5 *
wim 1:e180256ba6fb 6 * Released under the MIT License: http://mbed.org/license/mit
wim 1:e180256ba6fb 7 *
wim 1:e180256ba6fb 8 * version 0.2 Initial Release
wim 1:e180256ba6fb 9 */
wim 1:e180256ba6fb 10 #ifndef _HDSP253X_DISPLAY_H
wim 1:e180256ba6fb 11 #define _HDSP253X_DISPLAY_H
wim 1:e180256ba6fb 12 /*---------------------------------------------------------------------------*\
wim 1:e180256ba6fb 13 | Original text by RAC 06/08/2008 has been modified to fix those parts of
wim 1:e180256ba6fb 14 | the description which explain hardware or software that has been removed or
wim 1:e180256ba6fb 15 | adapted in the new version.
wim 1:e180256ba6fb 16 |
wim 1:e180256ba6fb 17 | Description: Display driver and demonstrator for HDSP253X series intelligent
wim 1:e180256ba6fb 18 | 8 character LED display modules. Options include adjusting
wim 1:e180256ba6fb 19 | brightness and message blinking.
wim 1:e180256ba6fb 20 | This software drives a single display module using 8 bit databus,
wim 1:e180256ba6fb 21 | 5 bit addressbus and controlsignals. Note that this software
wim 1:e180256ba6fb 22 | will drive all display devices in the series, including HDSP2530 Orange,
wim 1:e180256ba6fb 23 | HDSP2531 Yellow, HDSP2532 red and HDSP2533 green devices. It will also
wim 1:e180256ba6fb 24 | drive the smaller HDSP21XX series.
wim 1:e180256ba6fb 25 |
wim 1:e180256ba6fb 26 | The peripheral is connected to the following pins:
wim 1:e180256ba6fb 27 | HDSP253X
wim 1:e180256ba6fb 28 | - Reset (pin 1) to EnableBus.RESET
wim 1:e180256ba6fb 29 | - Flash (pin 2) to AddressBus.A5
wim 1:e180256ba6fb 30 | - Addr A0 (pin 3) to AddressBus.A0
wim 1:e180256ba6fb 31 | - Addr A1 (pin 4) to AddressBus.A1
wim 1:e180256ba6fb 32 | - Addr A2 (pin 5) to AddressBus.A2
wim 1:e180256ba6fb 33 | - Addr A3 (pin 6) to AddressBus.A3
wim 1:e180256ba6fb 34 | - Addr A4 (pin 10) to AddressBus.A4
wim 1:e180256ba6fb 35 | - Clock select (pin 11) to VCC (Pull Up)
wim 1:e180256ba6fb 36 | - Clock in/out (pin 12) to Not Connected
wim 1:e180256ba6fb 37 | - Write (pin 13) to ControlBus.WR
wim 1:e180256ba6fb 38 | - CE (Pin 14) to EnableBus.CSDISP
wim 1:e180256ba6fb 39 | - VDD 5V (Pin 15)
wim 1:e180256ba6fb 40 | - GND (supply) (Pin 16)
wim 1:e180256ba6fb 41 | - TST (Pin 16) NC
wim 1:e180256ba6fb 42 | - GND (logic) (Pin 18)
wim 1:e180256ba6fb 43 | - Read (pin 19) to ControlBus.RD
wim 1:e180256ba6fb 44 | - Data D0 (pin 20) to Databus.D0
wim 1:e180256ba6fb 45 | - Data D1 (pin 21) to Databus.D1
wim 1:e180256ba6fb 46 | - Data D2 (pin 25) to Databus.D2
wim 1:e180256ba6fb 47 | - Data D3 (pin 26) to Databus.D3
wim 1:e180256ba6fb 48 | - Data D4 (pin 27) to Databus.D4
wim 1:e180256ba6fb 49 | - Data D5 (pin 28) to Databus.D5
wim 1:e180256ba6fb 50 | - Data D6 (pin 29) to Databus.D6
wim 1:e180256ba6fb 51 | - Data D7 (pin 30) to Databus.D7
wim 1:e180256ba6fb 52 |
wim 1:e180256ba6fb 53 | The peripheral is connected to the following pins:
wim 1:e180256ba6fb 54 | HDSP211X
wim 1:e180256ba6fb 55 | - Reset (pin 1) to EnableBus.RESET
wim 1:e180256ba6fb 56 | - Flash (pin 2) to AddressBus.A5
wim 1:e180256ba6fb 57 | - Addr A0 (pin 3) to AddressBus.A0
wim 1:e180256ba6fb 58 | - Addr A1 (pin 4) to AddressBus.A1
wim 1:e180256ba6fb 59 | - Addr A2 (pin 5) to AddressBus.A2
wim 1:e180256ba6fb 60 | - Addr A3 (pin 6) to AddressBus.A3
wim 1:e180256ba6fb 61 | - Addr A4 (pin 10) to AddressBus.A4
wim 1:e180256ba6fb 62 | - Clock select (pin 11) to VCC (Pull Up)
wim 1:e180256ba6fb 63 | - Clock in/out (pin 12) to Not Connected
wim 1:e180256ba6fb 64 | - Write (pin 13) to ControlBus.WR
wim 1:e180256ba6fb 65 | - VDD 5V (Pin 14)
wim 1:e180256ba6fb 66 | - GND (supply) (Pin 15)
wim 1:e180256ba6fb 67 | - GND (logic) (Pin 16)
wim 1:e180256ba6fb 68 | - CE (Pin 17) to EnableBus.CSDISP
wim 1:e180256ba6fb 69 | - Read (pin 18) to ControlBus.RD
wim 1:e180256ba6fb 70 | - Data D0 (pin 19) to Databus.D0
wim 1:e180256ba6fb 71 | - Data D1 (pin 20) to Databus.D1
wim 1:e180256ba6fb 72 | - Data D2 (pin 23) to Databus.D2
wim 1:e180256ba6fb 73 | - Data D3 (pin 24) to Databus.D3
wim 1:e180256ba6fb 74 | - Data D4 (pin 25) to Databus.D4
wim 1:e180256ba6fb 75 | - Data D5 (pin 26) to Databus.D5
wim 1:e180256ba6fb 76 | - Data D6 (pin 27) to Databus.D6
wim 1:e180256ba6fb 77 | - Data D7 (pin 28) to Databus.D7
wim 1:e180256ba6fb 78 |
wim 1:e180256ba6fb 79 | Details: All signals to the HDSP253X are pulled up by 10K resistors.
wim 1:e180256ba6fb 80 | The device must be reset by pulsing Reset low with Chip Enable
wim 1:e180256ba6fb 81 | set high. Other signals are don't cares during a reset. This
wim 1:e180256ba6fb 82 | firmware meets these conditions, as long as the pullups are
wim 1:e180256ba6fb 83 | correctly installed.
wim 1:e180256ba6fb 84 |
wim 1:e180256ba6fb 85 | Connecting the clock select and in/out lines to the CPU is optional,
wim 1:e180256ba6fb 86 | and may be used for experimentation.
wim 1:e180256ba6fb 87 | If using one display, the clock select should normally be pulled
wim 1:e180256ba6fb 88 | up high, which results in the clock signal being an output.
wim 1:e180256ba6fb 89 | This driver software does not currently control these signals.
wim 1:e180256ba6fb 90 |
wim 1:e180256ba6fb 91 | If using more than one display, the driver software will
wim 1:e180256ba6fb 92 | require modification and extension. Multiple displays should
wim 1:e180256ba6fb 93 | have reset, data, address, flash and read/write lines paralleled.
wim 1:e180256ba6fb 94 | Each display requires a unique Chip Enable input, and the
wim 1:e180256ba6fb 95 | driver software will need to select which display to access.
wim 1:e180256ba6fb 96 | The first display should have clock select high, and its clock
wim 1:e180256ba6fb 97 | output connected to the clock inputs on all the other displays;
wim 1:e180256ba6fb 98 | these should have clock select low to input the clock signal.
wim 1:e180256ba6fb 99 |
wim 1:e180256ba6fb 100 | Calls to wait_ms() are used to meet the display timing specs
wim 1:e180256ba6fb 101 | may need to be modified at higher CPU speeds.
wim 1:e180256ba6fb 102 |
wim 1:e180256ba6fb 103 |
wim 1:e180256ba6fb 104 | Legalese: This software is FREEWARE, and you can adapt it for any
wim 1:e180256ba6fb 105 | purpose whatsoever. I cannot be held responsible for any
wim 1:e180256ba6fb 106 | loss, injury, damage or death caused by the use of this
wim 1:e180256ba6fb 107 | software.
wim 1:e180256ba6fb 108 |
wim 1:e180256ba6fb 109 \*---------------------------------------------------------------------------*/
wim 1:e180256ba6fb 110
wim 1:e180256ba6fb 111 //Useful stuff to simplify porting of some third party software
wim 1:e180256ba6fb 112 #include <stdarg.h>
wim 1:e180256ba6fb 113 //#include "Utils.h"
wim 1:e180256ba6fb 114
wim 1:e180256ba6fb 115
wim 1:e180256ba6fb 116 /*****************************************************************************/
wim 1:e180256ba6fb 117 /********************* DEFINITIONS FOR HDSP253X DISPLAY ********************/
wim 1:e180256ba6fb 118 /*****************************************************************************/
wim 1:e180256ba6fb 119
wim 1:e180256ba6fb 120 // Specific delays for display operation, assuming internal clocking
wim 1:e180256ba6fb 121 // This may need to be lengthened if a significantly slower external clock is used
wim 1:e180256ba6fb 122 #define HDSP253X_1TCY_WAIT_MS 1
wim 1:e180256ba6fb 123 //#define HDSP253X_1TCY_WAIT_MS 10
wim 1:e180256ba6fb 124 #define HDSP253X_RST_CLR_DELAY_MS 2 // delay AFTER issuing reset or clear
wim 1:e180256ba6fb 125 #define HDSP253X_SELFTEST_WAIT_MS 6000 // duration of self test operation
wim 1:e180256ba6fb 126
wim 1:e180256ba6fb 127 // address values and masks for HDSP253X display access
wim 1:e180256ba6fb 128 #define HDSP253X_ADDR_FLASH_BASE 0x00
wim 1:e180256ba6fb 129 #define HDSP253X_ADDR_UDC_ADDRESS 0x20
wim 1:e180256ba6fb 130 #define HDSP253X_ADDR_UDC_ROW_BASE 0x28
wim 1:e180256ba6fb 131 #define HDSP253X_ADDR_CTRL_WORD 0x30
wim 1:e180256ba6fb 132 #define HDSP253X_ADDR_CHAR_BASE 0x38
wim 1:e180256ba6fb 133 // minimises address line power consumption through pullups
wim 1:e180256ba6fb 134 #define HDSP253X_ADDR_LOW_POWER 0x3F
wim 1:e180256ba6fb 135
wim 1:e180256ba6fb 136 // control word masks for HDSP253X display
wim 1:e180256ba6fb 137 #define HDSP253X_CTRL_BRIGHT_MASK 0x07
wim 1:e180256ba6fb 138 #define HDSP253X_CTRL_FLASH_MASK 0x08
wim 1:e180256ba6fb 139 #define HDSP253X_CTRL_BLINK_MASK 0x10
wim 1:e180256ba6fb 140 #define HDSP253X_CTRL_STRESULT_MASK 0x20
wim 1:e180256ba6fb 141 #define HDSP253X_CTRL_SELFTEST_MASK 0x40
wim 1:e180256ba6fb 142 #define HDSP253X_CTRL_CLEAR_MASK 0x80
wim 1:e180256ba6fb 143
wim 1:e180256ba6fb 144 // Masks for register read, Bit 7 not readable in the target hardware
wim 1:e180256ba6fb 145 #define HDSP253X_CTRL_MASK 0x7F
wim 1:e180256ba6fb 146
wim 1:e180256ba6fb 147
wim 1:e180256ba6fb 148 // display brightness definitions, indicating percentage brightness
wim 1:e180256ba6fb 149 #define HDSP253X_BRIGHT_100 0x00
wim 1:e180256ba6fb 150 #define HDSP253X_BRIGHT_80 0x01
wim 1:e180256ba6fb 151 #define HDSP253X_BRIGHT_53 0x02
wim 1:e180256ba6fb 152 #define HDSP253X_BRIGHT_40 0x03
wim 1:e180256ba6fb 153 #define HDSP253X_BRIGHT_27 0x04
wim 1:e180256ba6fb 154 #define HDSP253X_BRIGHT_20 0x05
wim 1:e180256ba6fb 155 #define HDSP253X_BRIGHT_13 0x06
wim 1:e180256ba6fb 156 #define HDSP253X_BRIGHT_0 0x07
wim 1:e180256ba6fb 157
wim 1:e180256ba6fb 158 // miscellaneous definitions for HDSP253X display
wim 1:e180256ba6fb 159 #define HDSP253X_NUM_CHARS 8
wim 1:e180256ba6fb 160 #define HDSP253X_CHAR_MASK 0x7F
wim 1:e180256ba6fb 161 #define HDSP253X_UDC_SEL 0x80
wim 1:e180256ba6fb 162 #define HDSP253X_UDC_MASK 0x0F
wim 1:e180256ba6fb 163 #define HDSP253X_ASCII_UDC_CHARS 0x80
wim 1:e180256ba6fb 164
wim 1:e180256ba6fb 165 // default display brightness
wim 1:e180256ba6fb 166 #define HDSP253X_DEF_DISPLAY_BRIGHT HDSP253X_BRIGHT_100
wim 1:e180256ba6fb 167
wim 1:e180256ba6fb 168
wim 1:e180256ba6fb 169 /** Create an HDSP253X_Display object connected to the proper busses
wim 1:e180256ba6fb 170 *
wim 1:e180256ba6fb 171 * @param PCF8574_DataBus data databus to connect to
wim 1:e180256ba6fb 172 * @param PCF8574_AddressBus address addressbus to connect to
wim 1:e180256ba6fb 173 * @param PCF8574_EnableBus enable enablebus to connect to
wim 1:e180256ba6fb 174 * @param MBED_ControlBus control controlbus to connect to
wim 1:e180256ba6fb 175 */
wim 1:e180256ba6fb 176 class HDSP253X_Display {
wim 1:e180256ba6fb 177 public:
wim 1:e180256ba6fb 178 HDSP253X_Display(PCF8574_DataBus &databus, PCF8574_AddressBus &addressbus,
wim 1:e180256ba6fb 179 PCF8574_EnableBus &enablebus, MBED_ControlBus &controlbus);
wim 1:e180256ba6fb 180 void cls();
wim 1:e180256ba6fb 181 void putc(char disp_char);
wim 1:e180256ba6fb 182 // char getc();
wim 1:e180256ba6fb 183
wim 1:e180256ba6fb 184 void printf (char * format, ...);
wim 1:e180256ba6fb 185 void locate(uint8_t column);
wim 1:e180256ba6fb 186 void define_user_char(uint8_t udc_char_num, uint8_t row_data_1, uint8_t row_data_2,
wim 1:e180256ba6fb 187 uint8_t row_data_3, uint8_t row_data_4, uint8_t row_data_5,
wim 1:e180256ba6fb 188 uint8_t row_data_6, uint8_t row_data_7);
wim 1:e180256ba6fb 189 void putudc(char udc_char_num);
wim 1:e180256ba6fb 190
wim 1:e180256ba6fb 191 void set_char_flash_state(bool flash_state, uint8_t char_pos);
wim 1:e180256ba6fb 192 void set_all_flash_states(uint8_t flash_bits);
wim 1:e180256ba6fb 193 void set_brightness(uint8_t brightness);
wim 1:e180256ba6fb 194 void set_blink_mode(bool enable);
wim 1:e180256ba6fb 195 void set_flash_mode(bool enable);
wim 1:e180256ba6fb 196 void reset();
wim 1:e180256ba6fb 197 void start_self_test();
wim 1:e180256ba6fb 198 bool finish_self_test();
wim 1:e180256ba6fb 199
wim 1:e180256ba6fb 200 protected:
wim 1:e180256ba6fb 201 PCF8574_DataBus &_databus;
wim 1:e180256ba6fb 202 PCF8574_AddressBus &_addressbus;
wim 1:e180256ba6fb 203 PCF8574_EnableBus &_enablebus;
wim 1:e180256ba6fb 204 MBED_ControlBus &_controlbus;
wim 1:e180256ba6fb 205
wim 1:e180256ba6fb 206 // int _row;
wim 1:e180256ba6fb 207 int _column;
wim 1:e180256ba6fb 208 void _write(uint8_t address, uint8_t data);
wim 1:e180256ba6fb 209 uint8_t _read(uint8_t address);
wim 1:e180256ba6fb 210 void _init();
wim 1:e180256ba6fb 211 // void _display_ascii_char(char ascii_char, uint8_t char_pos);
wim 1:e180256ba6fb 212 // void _display_udc_char(char udc_char, uint8_t char_pos);
wim 1:e180256ba6fb 213 // void _display_part_string(const char *disp_string, uint8_t start_pos, uint8_t end_pos);
wim 1:e180256ba6fb 214 // void _display_fixed_string(const char *disp_string, uint8_t start_pos);
wim 1:e180256ba6fb 215
wim 1:e180256ba6fb 216 };
wim 1:e180256ba6fb 217
wim 1:e180256ba6fb 218
wim 1:e180256ba6fb 219 #endif
wim 1:e180256ba6fb 220 /*****************************************************************************/
wim 1:e180256ba6fb 221 /****************************** END OF FILE ********************************/
wim 1:e180256ba6fb 222 /*****************************************************************************/
wim 1:e180256ba6fb 223