wimbeaumont Project / AD5384

control for DAC AD5384 for the SOLID SM1 Slow Control

Dependents:   SPItest sscm

AD5384.h@5:477603ce54a0, 2015-01-29 (annotated)

Committer:
wbeaumont
Date:
Thu Jan 29 11:03:56 2015 +0000
Revision:
5:477603ce54a0
Parent:
4:bc9ab300ab26 
i n calculation corrected gain+1  to gain+2

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wbeaumont 0:33bb5081488a 1 #ifndef AD5384_H
wbeaumont 0:33bb5081488a 2 #define AD5384_H
wbeaumont 0:33bb5081488a 3
wbeaumont 0:33bb5081488a 4 #include "solid_sctrl_def.h"
wbeaumont 0:33bb5081488a 5 #include "SWSPI.h"
wbeaumont 1:d2d6341d3e97 6 #include "getVersion.h"
wbeaumont 0:33bb5081488a 7
wbeaumont 4:bc9ab300ab26 8 #define VERSION_AD5384_HDR "1.30"
wbeaumont 0:33bb5081488a 9
wbeaumont 0:33bb5081488a 10
wbeaumont 0:33bb5081488a 11 /*
wbeaumont 0:33bb5081488a 12 * class to set and readback the AD5384
wbeaumont 0:33bb5081488a 13 * to minimize the access to the device there is a shadow of the DAC, GAIN and OFFSET values
wbeaumont 0:33bb5081488a 14
wbeaumont 1:d2d6341d3e97 15 * v0.10 initial development to see if reading / writing is possible
wbeaumont 1:d2d6341d3e97 16 * v1.10 initial release versioni
wbeaumont 1:d2d6341d3e97 17 * v1.11 added init1 init2
wbeaumont 3:7ca85ed310e0 18 * v1.20 added rst pin
wbeaumont 4:bc9ab300ab26 19 * v1.24 added update shadow registers
wbeaumont 4:bc9ab300ab26 20 * v1.30 added get volt
wbeaumont 0:33bb5081488a 21 */
wbeaumont 0:33bb5081488a 22 class SWSPI;
wbeaumont 0:33bb5081488a 23 #include "mbed.h"
wbeaumont 0:33bb5081488a 24 //class DigitalOut;
wbeaumont 0:33bb5081488a 25
wbeaumont 1:d2d6341d3e97 26 class AD5384 : public getVersion {
wbeaumont 0:33bb5081488a 27 SWSPI *spi ;
wbeaumont 0:33bb5081488a 28 DigitalOut* cs;
wbeaumont 3:7ca85ed310e0 29 DigitalOut* rst;
wbeaumont 0:33bb5081488a 30 float vref;
wbeaumont 0:33bb5081488a 31
wbeaumont 0:33bb5081488a 32 void set_spi_mode();
wbeaumont 0:33bb5081488a 33 u16 calculate_dac_setting(u8 nr, float vout );
wbeaumont 0:33bb5081488a 34 u32 format_word(u8 mode,u8 ch,u8 rw,u16 data) ;
wbeaumont 0:33bb5081488a 35 u16 get_reg(u8 mode, u8 ch );
wbeaumont 0:33bb5081488a 36 u32 set_reg(u8 mode,u8 ch, u16 value );
wbeaumont 4:bc9ab300ab26 37
wbeaumont 4:bc9ab300ab26 38 void update_gain_shadow(u8 ch ) ;
wbeaumont 4:bc9ab300ab26 39 void update_offset_shadow(u8 ch ) ;
wbeaumont 4:bc9ab300ab26 40 void update_dac_shadow(u8 ch );
wbeaumont 4:bc9ab300ab26 41
wbeaumont 0:33bb5081488a 42 public:
wbeaumont 3:7ca85ed310e0 43 AD5384(SWSPI *spiinterface ,DigitalOut* chipselect,DigitalOut* reset );
wbeaumont 4:bc9ab300ab26 44 // channel shadow registers
wbeaumont 4:bc9ab300ab26 45 u16 dacr[40];
wbeaumont 0:33bb5081488a 46 u16 gain[40];
wbeaumont 0:33bb5081488a 47 u16 offset[40];
wbeaumont 0:33bb5081488a 48 float volt[40];
wbeaumont 0:33bb5081488a 49 u16 get_dac(u8 ch);
wbeaumont 0:33bb5081488a 50 u16 set_dac( u8 ch, u16 dac);
wbeaumont 0:33bb5081488a 51 u16 get_ch_out_reg(u8 ch) ;
wbeaumont 0:33bb5081488a 52 u16 set_volt(u8 nr, float vout );
wbeaumont 4:bc9ab300ab26 53 // if read all reg the gain and offset register is read
wbeaumont 4:bc9ab300ab26 54 // otherwise the shadow register offset and gain are used
wbeaumont 4:bc9ab300ab26 55 float get_volt(u8 nr, bool readallreg=false );
wbeaumont 0:33bb5081488a 56 u16 set_gain(u8 ch, u16 gain );
wbeaumont 0:33bb5081488a 57 u16 get_gain(u8 ch );
wbeaumont 0:33bb5081488a 58 u16 set_offset(u8 ch, u16 gain);
wbeaumont 0:33bb5081488a 59 u16 get_offset(u8 ch );
wbeaumont 3:7ca85ed310e0 60 void hw_rst();
wbeaumont 0:33bb5081488a 61 // ctnrls
wbeaumont 0:33bb5081488a 62 u32 get_ctrl();
wbeaumont 0:33bb5081488a 63 u32 soft_clr();
wbeaumont 0:33bb5081488a 64 u32 soft_rst();
wbeaumont 0:33bb5081488a 65 u32 clear_code();
wbeaumont 1:d2d6341d3e97 66 void init1();
wbeaumont 1:d2d6341d3e97 67 void init2();
wbeaumont 1:d2d6341d3e97 68
wbeaumont 1:d2d6341d3e97 69
wbeaumont 0:33bb5081488a 70
wbeaumont 0:33bb5081488a 71 };
wbeaumont 0:33bb5081488a 72
wbeaumont 0:33bb5081488a 73 #endif