Vipin Ranka / MGAS_GR_Peach

This is the final version of Mini Gateway for Automation and Security desgined for Renesas GR Peach Design Contest

Dependencies:   GR-PEACH_video GraphicsFramework HTTPServer R_BSP mbed-rpc mbed-rtos Socket lwip-eth lwip-sys lwip FATFileSystem

Fork of mbed-os-example-mbed5-blinky by mbed-os-examples

RF24/RF24.cpp@12:9a20164dcc47, 2017-01-11 (annotated)

Committer:
vipinranka
Date:
Wed Jan 11 11:41:30 2017 +0000
Revision:
12:9a20164dcc47
This is the final version MGAS Project for Renesas GR Peach Design Contest

Who changed what in which revision?

UserRevisionLine numberNew contents of line
vipinranka 12:9a20164dcc47 1 /*
vipinranka 12:9a20164dcc47 2 Copyright (C) 2011 J. Coliz <maniacbug@ymail.com>
vipinranka 12:9a20164dcc47 3
vipinranka 12:9a20164dcc47 4 This program is free software; you can redistribute it and/or
vipinranka 12:9a20164dcc47 5 modify it under the terms of the GNU General Public License
vipinranka 12:9a20164dcc47 6 version 2 as published by the Free Software Foundation.
vipinranka 12:9a20164dcc47 7 */
vipinranka 12:9a20164dcc47 8
vipinranka 12:9a20164dcc47 9 /*
vipinranka 12:9a20164dcc47 10 * Mbed support added by Akash Vibhute <akash.roboticist@gmail.com>
vipinranka 12:9a20164dcc47 11 * Porting completed on Nov/05/2015
vipinranka 12:9a20164dcc47 12 *
vipinranka 12:9a20164dcc47 13 * Updated 1: Synced with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20
vipinranka 12:9a20164dcc47 14 * Updated 2: Synced with TMRh20's RF24 library on Apr/18/2015 from https://github.com/TMRh20
vipinranka 12:9a20164dcc47 15 *
vipinranka 12:9a20164dcc47 16 */
vipinranka 12:9a20164dcc47 17
vipinranka 12:9a20164dcc47 18 #include "nRF24L01.h"
vipinranka 12:9a20164dcc47 19 #include "RF24_config.h"
vipinranka 12:9a20164dcc47 20 #include "RF24.h"
vipinranka 12:9a20164dcc47 21
vipinranka 12:9a20164dcc47 22 /****************************************************************************/
vipinranka 12:9a20164dcc47 23
vipinranka 12:9a20164dcc47 24 void RF24::csn(bool mode)
vipinranka 12:9a20164dcc47 25 {
vipinranka 12:9a20164dcc47 26
vipinranka 12:9a20164dcc47 27 csn_pin = mode;
vipinranka 12:9a20164dcc47 28
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vipinranka 12:9a20164dcc47 65 }
vipinranka 12:9a20164dcc47 66
vipinranka 12:9a20164dcc47 67 /****************************************************************************/
vipinranka 12:9a20164dcc47 68
vipinranka 12:9a20164dcc47 69 void RF24::ce(bool level)
vipinranka 12:9a20164dcc47 70 {
vipinranka 12:9a20164dcc47 71 ce_pin = level;
vipinranka 12:9a20164dcc47 72
vipinranka 12:9a20164dcc47 73 }
vipinranka 12:9a20164dcc47 74
vipinranka 12:9a20164dcc47 75 /****************************************************************************/
vipinranka 12:9a20164dcc47 76
vipinranka 12:9a20164dcc47 77 inline void RF24::beginTransaction()
vipinranka 12:9a20164dcc47 78 {
vipinranka 12:9a20164dcc47 79
vipinranka 12:9a20164dcc47 80
vipinranka 12:9a20164dcc47 81 csn(LOW);
vipinranka 12:9a20164dcc47 82 }
vipinranka 12:9a20164dcc47 83
vipinranka 12:9a20164dcc47 84 /****************************************************************************/
vipinranka 12:9a20164dcc47 85
vipinranka 12:9a20164dcc47 86 inline void RF24::endTransaction()
vipinranka 12:9a20164dcc47 87 {
vipinranka 12:9a20164dcc47 88 csn(HIGH);
vipinranka 12:9a20164dcc47 89
vipinranka 12:9a20164dcc47 90
vipinranka 12:9a20164dcc47 91
vipinranka 12:9a20164dcc47 92 }
vipinranka 12:9a20164dcc47 93
vipinranka 12:9a20164dcc47 94 /****************************************************************************/
vipinranka 12:9a20164dcc47 95
vipinranka 12:9a20164dcc47 96 uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
vipinranka 12:9a20164dcc47 97 {
vipinranka 12:9a20164dcc47 98 uint8_t status;
vipinranka 12:9a20164dcc47 99
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vipinranka 12:9a20164dcc47 121 beginTransaction();
vipinranka 12:9a20164dcc47 122 status = spi.write( R_REGISTER | ( REGISTER_MASK & reg ) );
vipinranka 12:9a20164dcc47 123 while ( len-- ) {
vipinranka 12:9a20164dcc47 124 *buf++ = spi.write(0xff);
vipinranka 12:9a20164dcc47 125 }
vipinranka 12:9a20164dcc47 126 endTransaction();
vipinranka 12:9a20164dcc47 127
vipinranka 12:9a20164dcc47 128
vipinranka 12:9a20164dcc47 129
vipinranka 12:9a20164dcc47 130 return status;
vipinranka 12:9a20164dcc47 131 }
vipinranka 12:9a20164dcc47 132
vipinranka 12:9a20164dcc47 133 /****************************************************************************/
vipinranka 12:9a20164dcc47 134
vipinranka 12:9a20164dcc47 135 uint8_t RF24::read_register(uint8_t reg)
vipinranka 12:9a20164dcc47 136 {
vipinranka 12:9a20164dcc47 137 uint8_t result;
vipinranka 12:9a20164dcc47 138
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vipinranka 12:9a20164dcc47 154 beginTransaction();
vipinranka 12:9a20164dcc47 155 spi.write( R_REGISTER | ( REGISTER_MASK & reg ) );
vipinranka 12:9a20164dcc47 156 result = spi.write(0xff);
vipinranka 12:9a20164dcc47 157 endTransaction();
vipinranka 12:9a20164dcc47 158
vipinranka 12:9a20164dcc47 159
vipinranka 12:9a20164dcc47 160
vipinranka 12:9a20164dcc47 161 return result;
vipinranka 12:9a20164dcc47 162 }
vipinranka 12:9a20164dcc47 163
vipinranka 12:9a20164dcc47 164 /****************************************************************************/
vipinranka 12:9a20164dcc47 165
vipinranka 12:9a20164dcc47 166 uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
vipinranka 12:9a20164dcc47 167 {
vipinranka 12:9a20164dcc47 168 uint8_t status;
vipinranka 12:9a20164dcc47 169 beginTransaction();
vipinranka 12:9a20164dcc47 170 status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) );
vipinranka 12:9a20164dcc47 171 while ( len-- )
vipinranka 12:9a20164dcc47 172 spi.write(*buf++);
vipinranka 12:9a20164dcc47 173 endTransaction();
vipinranka 12:9a20164dcc47 174
vipinranka 12:9a20164dcc47 175
vipinranka 12:9a20164dcc47 176
vipinranka 12:9a20164dcc47 177 return status;
vipinranka 12:9a20164dcc47 178 }
vipinranka 12:9a20164dcc47 179
vipinranka 12:9a20164dcc47 180 /****************************************************************************/
vipinranka 12:9a20164dcc47 181
vipinranka 12:9a20164dcc47 182 uint8_t RF24::write_register(uint8_t reg, uint8_t value)
vipinranka 12:9a20164dcc47 183 {
vipinranka 12:9a20164dcc47 184 uint8_t status;
vipinranka 12:9a20164dcc47 185
vipinranka 12:9a20164dcc47 186 IF_SERIAL_DEBUG(printf(PSTR("write_register(%02x,%02x)\r\n"),reg,value));
vipinranka 12:9a20164dcc47 187 beginTransaction();
vipinranka 12:9a20164dcc47 188 status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) );
vipinranka 12:9a20164dcc47 189 spi.write(value);
vipinranka 12:9a20164dcc47 190 endTransaction();
vipinranka 12:9a20164dcc47 191 return status;
vipinranka 12:9a20164dcc47 192 }
vipinranka 12:9a20164dcc47 193
vipinranka 12:9a20164dcc47 194 /****************************************************************************/
vipinranka 12:9a20164dcc47 195
vipinranka 12:9a20164dcc47 196 uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t writeType)
vipinranka 12:9a20164dcc47 197 {
vipinranka 12:9a20164dcc47 198 uint8_t status;
vipinranka 12:9a20164dcc47 199 const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
vipinranka 12:9a20164dcc47 200
vipinranka 12:9a20164dcc47 201 data_len = rf24_min(data_len, payload_size);
vipinranka 12:9a20164dcc47 202 uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
vipinranka 12:9a20164dcc47 203
vipinranka 12:9a20164dcc47 204 //printf("[Writing %u bytes %u blanks]",data_len,blank_len);
vipinranka 12:9a20164dcc47 205 IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); );
vipinranka 12:9a20164dcc47 206 beginTransaction();
vipinranka 12:9a20164dcc47 207 status = spi.write( writeType );
vipinranka 12:9a20164dcc47 208 while ( data_len-- ) {
vipinranka 12:9a20164dcc47 209 spi.write(*current++);
vipinranka 12:9a20164dcc47 210 }
vipinranka 12:9a20164dcc47 211 while ( blank_len-- ) {
vipinranka 12:9a20164dcc47 212 spi.write(0);
vipinranka 12:9a20164dcc47 213 }
vipinranka 12:9a20164dcc47 214 endTransaction();
vipinranka 12:9a20164dcc47 215
vipinranka 12:9a20164dcc47 216
vipinranka 12:9a20164dcc47 217
vipinranka 12:9a20164dcc47 218 return status;
vipinranka 12:9a20164dcc47 219 }
vipinranka 12:9a20164dcc47 220
vipinranka 12:9a20164dcc47 221 /****************************************************************************/
vipinranka 12:9a20164dcc47 222
vipinranka 12:9a20164dcc47 223 uint8_t RF24::read_payload(void* buf, uint8_t data_len)
vipinranka 12:9a20164dcc47 224 {
vipinranka 12:9a20164dcc47 225 uint8_t status;
vipinranka 12:9a20164dcc47 226 uint8_t* current = reinterpret_cast<uint8_t*>(buf);
vipinranka 12:9a20164dcc47 227
vipinranka 12:9a20164dcc47 228 if(data_len > payload_size) data_len = payload_size;
vipinranka 12:9a20164dcc47 229 uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len;
vipinranka 12:9a20164dcc47 230
vipinranka 12:9a20164dcc47 231 //printf("[Reading %u bytes %u blanks]",data_len,blank_len);
vipinranka 12:9a20164dcc47 232
vipinranka 12:9a20164dcc47 233 IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); );
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vipinranka 12:9a20164dcc47 261 beginTransaction();
vipinranka 12:9a20164dcc47 262 status = spi.write( R_RX_PAYLOAD );
vipinranka 12:9a20164dcc47 263 while ( data_len-- ) {
vipinranka 12:9a20164dcc47 264 *current++ = spi.write(0xFF);
vipinranka 12:9a20164dcc47 265 }
vipinranka 12:9a20164dcc47 266 while ( blank_len-- ) {
vipinranka 12:9a20164dcc47 267 spi.write(0xff);
vipinranka 12:9a20164dcc47 268 }
vipinranka 12:9a20164dcc47 269 endTransaction();
vipinranka 12:9a20164dcc47 270
vipinranka 12:9a20164dcc47 271
vipinranka 12:9a20164dcc47 272
vipinranka 12:9a20164dcc47 273 return status;
vipinranka 12:9a20164dcc47 274 }
vipinranka 12:9a20164dcc47 275
vipinranka 12:9a20164dcc47 276 /****************************************************************************/
vipinranka 12:9a20164dcc47 277
vipinranka 12:9a20164dcc47 278 uint8_t RF24::flush_rx(void)
vipinranka 12:9a20164dcc47 279 {
vipinranka 12:9a20164dcc47 280 return spiTrans( FLUSH_RX );
vipinranka 12:9a20164dcc47 281 }
vipinranka 12:9a20164dcc47 282
vipinranka 12:9a20164dcc47 283 /****************************************************************************/
vipinranka 12:9a20164dcc47 284
vipinranka 12:9a20164dcc47 285 uint8_t RF24::flush_tx(void)
vipinranka 12:9a20164dcc47 286 {
vipinranka 12:9a20164dcc47 287 return spiTrans( FLUSH_TX );
vipinranka 12:9a20164dcc47 288 }
vipinranka 12:9a20164dcc47 289
vipinranka 12:9a20164dcc47 290 /****************************************************************************/
vipinranka 12:9a20164dcc47 291
vipinranka 12:9a20164dcc47 292 uint8_t RF24::spiTrans(uint8_t cmd)
vipinranka 12:9a20164dcc47 293 {
vipinranka 12:9a20164dcc47 294
vipinranka 12:9a20164dcc47 295 uint8_t status;
vipinranka 12:9a20164dcc47 296
vipinranka 12:9a20164dcc47 297 beginTransaction();
vipinranka 12:9a20164dcc47 298 status = spi.write( cmd );
vipinranka 12:9a20164dcc47 299 endTransaction();
vipinranka 12:9a20164dcc47 300
vipinranka 12:9a20164dcc47 301 return status;
vipinranka 12:9a20164dcc47 302 }
vipinranka 12:9a20164dcc47 303
vipinranka 12:9a20164dcc47 304 /****************************************************************************/
vipinranka 12:9a20164dcc47 305
vipinranka 12:9a20164dcc47 306 uint8_t RF24::get_status(void)
vipinranka 12:9a20164dcc47 307 {
vipinranka 12:9a20164dcc47 308 return spiTrans(NOP);
vipinranka 12:9a20164dcc47 309 }
vipinranka 12:9a20164dcc47 310
vipinranka 12:9a20164dcc47 311 /****************************************************************************/
vipinranka 12:9a20164dcc47 312 #if !defined (MINIMAL)
vipinranka 12:9a20164dcc47 313 void RF24::print_status(uint8_t status)
vipinranka 12:9a20164dcc47 314 {
vipinranka 12:9a20164dcc47 315 printf(PSTR("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"),
vipinranka 12:9a20164dcc47 316 status,
vipinranka 12:9a20164dcc47 317 (status & _BV(RX_DR))?1:0,
vipinranka 12:9a20164dcc47 318 (status & _BV(TX_DS))?1:0,
vipinranka 12:9a20164dcc47 319 (status & _BV(MAX_RT))?1:0,
vipinranka 12:9a20164dcc47 320 ((status >> RX_P_NO) & 0b111),
vipinranka 12:9a20164dcc47 321 (status & _BV(TX_FULL))?1:0
vipinranka 12:9a20164dcc47 322 );
vipinranka 12:9a20164dcc47 323 }
vipinranka 12:9a20164dcc47 324
vipinranka 12:9a20164dcc47 325 /****************************************************************************/
vipinranka 12:9a20164dcc47 326
vipinranka 12:9a20164dcc47 327 void RF24::print_observe_tx(uint8_t value)
vipinranka 12:9a20164dcc47 328 {
vipinranka 12:9a20164dcc47 329 printf(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
vipinranka 12:9a20164dcc47 330 value,
vipinranka 12:9a20164dcc47 331 (value >> PLOS_CNT) & 0b1111,
vipinranka 12:9a20164dcc47 332 (value >> ARC_CNT) & 0b1111
vipinranka 12:9a20164dcc47 333 );
vipinranka 12:9a20164dcc47 334 }
vipinranka 12:9a20164dcc47 335
vipinranka 12:9a20164dcc47 336 /****************************************************************************/
vipinranka 12:9a20164dcc47 337
vipinranka 12:9a20164dcc47 338 void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty)
vipinranka 12:9a20164dcc47 339 {
vipinranka 12:9a20164dcc47 340 //char extra_tab = strlen_P(name) < 8 ? '\t' : 0;
vipinranka 12:9a20164dcc47 341 //printf(PSTR(PRIPSTR"\t%c ="),name,extra_tab);
vipinranka 12:9a20164dcc47 342
vipinranka 12:9a20164dcc47 343
vipinranka 12:9a20164dcc47 344
vipinranka 12:9a20164dcc47 345 printf(PSTR(PRIPSTR"\t ="),name);
vipinranka 12:9a20164dcc47 346
vipinranka 12:9a20164dcc47 347 while (qty--)
vipinranka 12:9a20164dcc47 348 printf(PSTR(" 0x%02x"),read_register(reg++));
vipinranka 12:9a20164dcc47 349 printf(PSTR("\r\n"));
vipinranka 12:9a20164dcc47 350 }
vipinranka 12:9a20164dcc47 351
vipinranka 12:9a20164dcc47 352 /****************************************************************************/
vipinranka 12:9a20164dcc47 353
vipinranka 12:9a20164dcc47 354 void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
vipinranka 12:9a20164dcc47 355 {
vipinranka 12:9a20164dcc47 356
vipinranka 12:9a20164dcc47 357
vipinranka 12:9a20164dcc47 358
vipinranka 12:9a20164dcc47 359
vipinranka 12:9a20164dcc47 360 printf(PSTR(PRIPSTR"\t ="),name);
vipinranka 12:9a20164dcc47 361
vipinranka 12:9a20164dcc47 362 while (qty--) {
vipinranka 12:9a20164dcc47 363 uint8_t buffer[addr_width];
vipinranka 12:9a20164dcc47 364 read_register(reg++,buffer,sizeof buffer);
vipinranka 12:9a20164dcc47 365
vipinranka 12:9a20164dcc47 366 printf(PSTR(" 0x"));
vipinranka 12:9a20164dcc47 367 uint8_t* bufptr = buffer + sizeof buffer;
vipinranka 12:9a20164dcc47 368 while( --bufptr >= buffer )
vipinranka 12:9a20164dcc47 369 printf(PSTR("%02x"),*bufptr);
vipinranka 12:9a20164dcc47 370 }
vipinranka 12:9a20164dcc47 371
vipinranka 12:9a20164dcc47 372 printf(PSTR("\r\n"));
vipinranka 12:9a20164dcc47 373 }
vipinranka 12:9a20164dcc47 374 #endif
vipinranka 12:9a20164dcc47 375 /****************************************************************************/
vipinranka 12:9a20164dcc47 376 RF24::RF24(PinName mosi, PinName miso, PinName sck, PinName _cepin, PinName _csnpin):
vipinranka 12:9a20164dcc47 377 spi(mosi, miso, sck), ce_pin(_cepin), csn_pin(_csnpin), p_variant(true),
vipinranka 12:9a20164dcc47 378 payload_size(32), dynamic_payloads_enabled(false), addr_width(5)
vipinranka 12:9a20164dcc47 379 {
vipinranka 12:9a20164dcc47 380 pipe0_reading_address[0]=0;
vipinranka 12:9a20164dcc47 381
vipinranka 12:9a20164dcc47 382 //spi.frequency(10000000/5); // 2Mbit, 1/5th the maximum transfer rate for the spi bus
vipinranka 12:9a20164dcc47 383 spi.frequency(10000000/5);
vipinranka 12:9a20164dcc47 384 //spi.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0
vipinranka 12:9a20164dcc47 385 spi.format(8,0);
vipinranka 12:9a20164dcc47 386 wait_ms(10);
vipinranka 12:9a20164dcc47 387 }
vipinranka 12:9a20164dcc47 388
vipinranka 12:9a20164dcc47 389
vipinranka 12:9a20164dcc47 390
vipinranka 12:9a20164dcc47 391
vipinranka 12:9a20164dcc47 392
vipinranka 12:9a20164dcc47 393
vipinranka 12:9a20164dcc47 394
vipinranka 12:9a20164dcc47 395
vipinranka 12:9a20164dcc47 396 /****************************************************************************/
vipinranka 12:9a20164dcc47 397
vipinranka 12:9a20164dcc47 398 void RF24::setChannel(uint8_t channel)
vipinranka 12:9a20164dcc47 399 {
vipinranka 12:9a20164dcc47 400 const uint8_t max_channel = 125;
vipinranka 12:9a20164dcc47 401 write_register(RF_CH,rf24_min(channel,max_channel));
vipinranka 12:9a20164dcc47 402 }
vipinranka 12:9a20164dcc47 403
vipinranka 12:9a20164dcc47 404 uint8_t RF24::getChannel()
vipinranka 12:9a20164dcc47 405 {
vipinranka 12:9a20164dcc47 406
vipinranka 12:9a20164dcc47 407 return read_register(RF_CH);
vipinranka 12:9a20164dcc47 408 }
vipinranka 12:9a20164dcc47 409 /****************************************************************************/
vipinranka 12:9a20164dcc47 410
vipinranka 12:9a20164dcc47 411 void RF24::setPayloadSize(uint8_t size)
vipinranka 12:9a20164dcc47 412 {
vipinranka 12:9a20164dcc47 413 payload_size = rf24_min(size,32);
vipinranka 12:9a20164dcc47 414 }
vipinranka 12:9a20164dcc47 415
vipinranka 12:9a20164dcc47 416 /****************************************************************************/
vipinranka 12:9a20164dcc47 417
vipinranka 12:9a20164dcc47 418 uint8_t RF24::getPayloadSize(void)
vipinranka 12:9a20164dcc47 419 {
vipinranka 12:9a20164dcc47 420 return payload_size;
vipinranka 12:9a20164dcc47 421 }
vipinranka 12:9a20164dcc47 422
vipinranka 12:9a20164dcc47 423 /****************************************************************************/
vipinranka 12:9a20164dcc47 424
vipinranka 12:9a20164dcc47 425 #if !defined (MINIMAL)
vipinranka 12:9a20164dcc47 426
vipinranka 12:9a20164dcc47 427 static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS";
vipinranka 12:9a20164dcc47 428 static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS";
vipinranka 12:9a20164dcc47 429 static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS";
vipinranka 12:9a20164dcc47 430 static const char * const rf24_datarate_e_str_P[] PROGMEM = {
vipinranka 12:9a20164dcc47 431 rf24_datarate_e_str_0,
vipinranka 12:9a20164dcc47 432 rf24_datarate_e_str_1,
vipinranka 12:9a20164dcc47 433 rf24_datarate_e_str_2,
vipinranka 12:9a20164dcc47 434 };
vipinranka 12:9a20164dcc47 435 static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01";
vipinranka 12:9a20164dcc47 436 static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+";
vipinranka 12:9a20164dcc47 437 static const char * const rf24_model_e_str_P[] PROGMEM = {
vipinranka 12:9a20164dcc47 438 rf24_model_e_str_0,
vipinranka 12:9a20164dcc47 439 rf24_model_e_str_1,
vipinranka 12:9a20164dcc47 440 };
vipinranka 12:9a20164dcc47 441 static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled";
vipinranka 12:9a20164dcc47 442 static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits";
vipinranka 12:9a20164dcc47 443 static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ;
vipinranka 12:9a20164dcc47 444 static const char * const rf24_crclength_e_str_P[] PROGMEM = {
vipinranka 12:9a20164dcc47 445 rf24_crclength_e_str_0,
vipinranka 12:9a20164dcc47 446 rf24_crclength_e_str_1,
vipinranka 12:9a20164dcc47 447 rf24_crclength_e_str_2,
vipinranka 12:9a20164dcc47 448 };
vipinranka 12:9a20164dcc47 449 static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN";
vipinranka 12:9a20164dcc47 450 static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW";
vipinranka 12:9a20164dcc47 451 static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH";
vipinranka 12:9a20164dcc47 452 static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX";
vipinranka 12:9a20164dcc47 453 static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = {
vipinranka 12:9a20164dcc47 454 rf24_pa_dbm_e_str_0,
vipinranka 12:9a20164dcc47 455 rf24_pa_dbm_e_str_1,
vipinranka 12:9a20164dcc47 456 rf24_pa_dbm_e_str_2,
vipinranka 12:9a20164dcc47 457 rf24_pa_dbm_e_str_3,
vipinranka 12:9a20164dcc47 458 };
vipinranka 12:9a20164dcc47 459
vipinranka 12:9a20164dcc47 460
vipinranka 12:9a20164dcc47 461
vipinranka 12:9a20164dcc47 462
vipinranka 12:9a20164dcc47 463
vipinranka 12:9a20164dcc47 464
vipinranka 12:9a20164dcc47 465
vipinranka 12:9a20164dcc47 466
vipinranka 12:9a20164dcc47 467
vipinranka 12:9a20164dcc47 468
vipinranka 12:9a20164dcc47 469
vipinranka 12:9a20164dcc47 470
vipinranka 12:9a20164dcc47 471
vipinranka 12:9a20164dcc47 472
vipinranka 12:9a20164dcc47 473 void RF24::printDetails(void)
vipinranka 12:9a20164dcc47 474 {
vipinranka 12:9a20164dcc47 475
vipinranka 12:9a20164dcc47 476 print_status(get_status());
vipinranka 12:9a20164dcc47 477
vipinranka 12:9a20164dcc47 478 print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2);
vipinranka 12:9a20164dcc47 479 print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4);
vipinranka 12:9a20164dcc47 480 print_address_register(PSTR("TX_ADDR\t"),TX_ADDR);
vipinranka 12:9a20164dcc47 481
vipinranka 12:9a20164dcc47 482 print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6);
vipinranka 12:9a20164dcc47 483 print_byte_register(PSTR("EN_AA\t"),EN_AA);
vipinranka 12:9a20164dcc47 484 print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR);
vipinranka 12:9a20164dcc47 485 print_byte_register(PSTR("RF_CH\t"),RF_CH);
vipinranka 12:9a20164dcc47 486 print_byte_register(PSTR("RF_SETUP"),RF_SETUP);
vipinranka 12:9a20164dcc47 487 print_byte_register(PSTR("CONFIG\t"),NRF_CONFIG);
vipinranka 12:9a20164dcc47 488 print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2);
vipinranka 12:9a20164dcc47 489
vipinranka 12:9a20164dcc47 490 printf(PSTR("Data Rate\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()]));
vipinranka 12:9a20164dcc47 491 printf(PSTR("Model\t\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()]));
vipinranka 12:9a20164dcc47 492 printf(PSTR("CRC Length\t = " PRIPSTR "\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()]));
vipinranka 12:9a20164dcc47 493 printf(PSTR("PA Power\t = " PRIPSTR "\r\n"), pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()]));
vipinranka 12:9a20164dcc47 494
vipinranka 12:9a20164dcc47 495 }
vipinranka 12:9a20164dcc47 496
vipinranka 12:9a20164dcc47 497 #endif
vipinranka 12:9a20164dcc47 498 /****************************************************************************/
vipinranka 12:9a20164dcc47 499
vipinranka 12:9a20164dcc47 500 bool RF24::begin(void)
vipinranka 12:9a20164dcc47 501 {
vipinranka 12:9a20164dcc47 502
vipinranka 12:9a20164dcc47 503 uint8_t setup=0;
vipinranka 12:9a20164dcc47 504
vipinranka 12:9a20164dcc47 505 mainTimer.start();
vipinranka 12:9a20164dcc47 506
vipinranka 12:9a20164dcc47 507 ce(LOW);
vipinranka 12:9a20164dcc47 508 csn(HIGH);
vipinranka 12:9a20164dcc47 509
vipinranka 12:9a20164dcc47 510 wait_ms(100);
vipinranka 12:9a20164dcc47 511
vipinranka 12:9a20164dcc47 512
vipinranka 12:9a20164dcc47 513
vipinranka 12:9a20164dcc47 514
vipinranka 12:9a20164dcc47 515
vipinranka 12:9a20164dcc47 516
vipinranka 12:9a20164dcc47 517
vipinranka 12:9a20164dcc47 518
vipinranka 12:9a20164dcc47 519
vipinranka 12:9a20164dcc47 520
vipinranka 12:9a20164dcc47 521
vipinranka 12:9a20164dcc47 522
vipinranka 12:9a20164dcc47 523
vipinranka 12:9a20164dcc47 524
vipinranka 12:9a20164dcc47 525
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vipinranka 12:9a20164dcc47 527
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vipinranka 12:9a20164dcc47 530
vipinranka 12:9a20164dcc47 531
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vipinranka 12:9a20164dcc47 533
vipinranka 12:9a20164dcc47 534
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vipinranka 12:9a20164dcc47 536
vipinranka 12:9a20164dcc47 537
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vipinranka 12:9a20164dcc47 541
vipinranka 12:9a20164dcc47 542
vipinranka 12:9a20164dcc47 543
vipinranka 12:9a20164dcc47 544
vipinranka 12:9a20164dcc47 545
vipinranka 12:9a20164dcc47 546
vipinranka 12:9a20164dcc47 547
vipinranka 12:9a20164dcc47 548
vipinranka 12:9a20164dcc47 549
vipinranka 12:9a20164dcc47 550
vipinranka 12:9a20164dcc47 551 // Must allow the radio time to settle else configuration bits will not necessarily stick.
vipinranka 12:9a20164dcc47 552 // This is actually only required following power up but some settling time also appears to
vipinranka 12:9a20164dcc47 553 // be required after resets too. For full coverage, we'll always assume the worst.
vipinranka 12:9a20164dcc47 554 // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped.
vipinranka 12:9a20164dcc47 555 // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure.
vipinranka 12:9a20164dcc47 556 // WARNING: Delay is based on P-variant whereby non-P *may* require different timing.
vipinranka 12:9a20164dcc47 557 wait_ms( 5 ) ;
vipinranka 12:9a20164dcc47 558
vipinranka 12:9a20164dcc47 559 // Reset NRF_CONFIG and enable 16-bit CRC.
vipinranka 12:9a20164dcc47 560 write_register( NRF_CONFIG, 0b00001100 ) ;
vipinranka 12:9a20164dcc47 561
vipinranka 12:9a20164dcc47 562 // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
vipinranka 12:9a20164dcc47 563 // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
vipinranka 12:9a20164dcc47 564 // sizes must never be used. See documentation for a more complete explanation.
vipinranka 12:9a20164dcc47 565 setRetries(5,15);
vipinranka 12:9a20164dcc47 566
vipinranka 12:9a20164dcc47 567 // Reset value is MAX
vipinranka 12:9a20164dcc47 568 //setPALevel( RF24_PA_MAX ) ;
vipinranka 12:9a20164dcc47 569
vipinranka 12:9a20164dcc47 570 // check for connected module and if this is a p nRF24l01 variant
vipinranka 12:9a20164dcc47 571 //
vipinranka 12:9a20164dcc47 572 if( setDataRate( RF24_250KBPS ) ) {
vipinranka 12:9a20164dcc47 573 p_variant = true ;
vipinranka 12:9a20164dcc47 574 }
vipinranka 12:9a20164dcc47 575 setup = read_register(RF_SETUP);
vipinranka 12:9a20164dcc47 576 /*if( setup == 0b00001110 ) // register default for nRF24L01P
vipinranka 12:9a20164dcc47 577 {
vipinranka 12:9a20164dcc47 578 p_variant = true ;
vipinranka 12:9a20164dcc47 579 }*/
vipinranka 12:9a20164dcc47 580
vipinranka 12:9a20164dcc47 581 // Then set the data rate to the slowest (and most reliable) speed supported by all
vipinranka 12:9a20164dcc47 582 // hardware.
vipinranka 12:9a20164dcc47 583 //setDataRate( RF24_1MBPS ) ;
vipinranka 12:9a20164dcc47 584 setDataRate( RF24_2MBPS ) ;
vipinranka 12:9a20164dcc47 585
vipinranka 12:9a20164dcc47 586 // Initialize CRC and request 2-byte (16bit) CRC
vipinranka 12:9a20164dcc47 587 //setCRCLength( RF24_CRC_16 ) ;
vipinranka 12:9a20164dcc47 588
vipinranka 12:9a20164dcc47 589 // Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0
vipinranka 12:9a20164dcc47 590 toggle_features();
vipinranka 12:9a20164dcc47 591 write_register(FEATURE,0 );
vipinranka 12:9a20164dcc47 592 write_register(DYNPD,0);
vipinranka 12:9a20164dcc47 593
vipinranka 12:9a20164dcc47 594 // Reset current status
vipinranka 12:9a20164dcc47 595 // Notice reset and flush is the last thing we do
vipinranka 12:9a20164dcc47 596 write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
vipinranka 12:9a20164dcc47 597
vipinranka 12:9a20164dcc47 598 // Set up default configuration. Callers can always change it later.
vipinranka 12:9a20164dcc47 599 // This channel should be universally safe and not bleed over into adjacent
vipinranka 12:9a20164dcc47 600 // spectrum.
vipinranka 12:9a20164dcc47 601 setChannel(76);
vipinranka 12:9a20164dcc47 602
vipinranka 12:9a20164dcc47 603 // Flush buffers
vipinranka 12:9a20164dcc47 604 flush_rx();
vipinranka 12:9a20164dcc47 605 flush_tx();
vipinranka 12:9a20164dcc47 606
vipinranka 12:9a20164dcc47 607 powerUp(); //Power up by default when begin() is called
vipinranka 12:9a20164dcc47 608
vipinranka 12:9a20164dcc47 609 // Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp )
vipinranka 12:9a20164dcc47 610 // PTX should use only 22uA of power
vipinranka 12:9a20164dcc47 611 write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
vipinranka 12:9a20164dcc47 612 //printDetails();
vipinranka 12:9a20164dcc47 613 // if setup is 0 or ff then there was no response from module
vipinranka 12:9a20164dcc47 614 return ( setup != 0 && setup != 0xff );
vipinranka 12:9a20164dcc47 615 }
vipinranka 12:9a20164dcc47 616
vipinranka 12:9a20164dcc47 617 /****************************************************************************/
vipinranka 12:9a20164dcc47 618
vipinranka 12:9a20164dcc47 619 void RF24::startListening(void)
vipinranka 12:9a20164dcc47 620 {
vipinranka 12:9a20164dcc47 621
vipinranka 12:9a20164dcc47 622
vipinranka 12:9a20164dcc47 623
vipinranka 12:9a20164dcc47 624 write_register(NRF_CONFIG, read_register(NRF_CONFIG) | _BV(PRIM_RX));
vipinranka 12:9a20164dcc47 625 write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
vipinranka 12:9a20164dcc47 626 ce(HIGH);
vipinranka 12:9a20164dcc47 627 // Restore the pipe0 adddress, if exists
vipinranka 12:9a20164dcc47 628 if (pipe0_reading_address[0] > 0) {
vipinranka 12:9a20164dcc47 629 write_register(RX_ADDR_P0, pipe0_reading_address, addr_width);
vipinranka 12:9a20164dcc47 630 } else {
vipinranka 12:9a20164dcc47 631 closeReadingPipe(0);
vipinranka 12:9a20164dcc47 632 }
vipinranka 12:9a20164dcc47 633
vipinranka 12:9a20164dcc47 634 // Flush buffers
vipinranka 12:9a20164dcc47 635 //flush_rx();
vipinranka 12:9a20164dcc47 636 if(read_register(FEATURE) & _BV(EN_ACK_PAY)) {
vipinranka 12:9a20164dcc47 637 flush_tx();
vipinranka 12:9a20164dcc47 638 }
vipinranka 12:9a20164dcc47 639
vipinranka 12:9a20164dcc47 640 // Go!
vipinranka 12:9a20164dcc47 641 //delayMicroseconds(100);
vipinranka 12:9a20164dcc47 642 }
vipinranka 12:9a20164dcc47 643
vipinranka 12:9a20164dcc47 644 /****************************************************************************/
vipinranka 12:9a20164dcc47 645 static const uint8_t child_pipe_enable[] PROGMEM = {
vipinranka 12:9a20164dcc47 646 ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5
vipinranka 12:9a20164dcc47 647 };
vipinranka 12:9a20164dcc47 648
vipinranka 12:9a20164dcc47 649 void RF24::stopListening(void)
vipinranka 12:9a20164dcc47 650 {
vipinranka 12:9a20164dcc47 651 ce(LOW);
vipinranka 12:9a20164dcc47 652
vipinranka 12:9a20164dcc47 653 wait_us(txRxDelay);
vipinranka 12:9a20164dcc47 654
vipinranka 12:9a20164dcc47 655 if(read_register(FEATURE) & _BV(EN_ACK_PAY)) {
vipinranka 12:9a20164dcc47 656 wait_us(txRxDelay); //200
vipinranka 12:9a20164dcc47 657 flush_tx();
vipinranka 12:9a20164dcc47 658 }
vipinranka 12:9a20164dcc47 659 //flush_rx();
vipinranka 12:9a20164dcc47 660 write_register(NRF_CONFIG, ( read_register(NRF_CONFIG) ) & ~_BV(PRIM_RX) );
vipinranka 12:9a20164dcc47 661
vipinranka 12:9a20164dcc47 662
vipinranka 12:9a20164dcc47 663
vipinranka 12:9a20164dcc47 664
vipinranka 12:9a20164dcc47 665
vipinranka 12:9a20164dcc47 666
vipinranka 12:9a20164dcc47 667
vipinranka 12:9a20164dcc47 668
vipinranka 12:9a20164dcc47 669 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0
vipinranka 12:9a20164dcc47 670
vipinranka 12:9a20164dcc47 671 //delayMicroseconds(100);
vipinranka 12:9a20164dcc47 672
vipinranka 12:9a20164dcc47 673 }
vipinranka 12:9a20164dcc47 674
vipinranka 12:9a20164dcc47 675 /****************************************************************************/
vipinranka 12:9a20164dcc47 676
vipinranka 12:9a20164dcc47 677 void RF24::powerDown(void)
vipinranka 12:9a20164dcc47 678 {
vipinranka 12:9a20164dcc47 679 ce(LOW); // Guarantee CE is low on powerDown
vipinranka 12:9a20164dcc47 680 write_register(NRF_CONFIG,read_register(NRF_CONFIG) & ~_BV(PWR_UP));
vipinranka 12:9a20164dcc47 681 }
vipinranka 12:9a20164dcc47 682
vipinranka 12:9a20164dcc47 683 /****************************************************************************/
vipinranka 12:9a20164dcc47 684
vipinranka 12:9a20164dcc47 685 //Power up now. Radio will not power down unless instructed by MCU for config changes etc.
vipinranka 12:9a20164dcc47 686 void RF24::powerUp(void)
vipinranka 12:9a20164dcc47 687 {
vipinranka 12:9a20164dcc47 688 uint8_t cfg = read_register(NRF_CONFIG);
vipinranka 12:9a20164dcc47 689
vipinranka 12:9a20164dcc47 690 // if not powered up then power up and wait for the radio to initialize
vipinranka 12:9a20164dcc47 691 if (!(cfg & _BV(PWR_UP))) {
vipinranka 12:9a20164dcc47 692 write_register(NRF_CONFIG, cfg | _BV(PWR_UP));
vipinranka 12:9a20164dcc47 693
vipinranka 12:9a20164dcc47 694 // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode.
vipinranka 12:9a20164dcc47 695 // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before
vipinranka 12:9a20164dcc47 696 // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet
vipinranka 12:9a20164dcc47 697 wait_ms(5);
vipinranka 12:9a20164dcc47 698 }
vipinranka 12:9a20164dcc47 699 }
vipinranka 12:9a20164dcc47 700
vipinranka 12:9a20164dcc47 701 /******************************************************************/
vipinranka 12:9a20164dcc47 702 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
vipinranka 12:9a20164dcc47 703 void RF24::errNotify()
vipinranka 12:9a20164dcc47 704 {
vipinranka 12:9a20164dcc47 705 #if defined (SERIAL_DEBUG) || defined (RF24_LINUX)
vipinranka 12:9a20164dcc47 706 printf(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n"));
vipinranka 12:9a20164dcc47 707 #endif
vipinranka 12:9a20164dcc47 708 #if defined (FAILURE_HANDLING)
vipinranka 12:9a20164dcc47 709 failureDetected = 1;
vipinranka 12:9a20164dcc47 710 #else
vipinranka 12:9a20164dcc47 711 wait_ms(5000);
vipinranka 12:9a20164dcc47 712 #endif
vipinranka 12:9a20164dcc47 713 }
vipinranka 12:9a20164dcc47 714 #endif
vipinranka 12:9a20164dcc47 715 /******************************************************************/
vipinranka 12:9a20164dcc47 716
vipinranka 12:9a20164dcc47 717 //Similar to the previous write, clears the interrupt flags
vipinranka 12:9a20164dcc47 718 bool RF24::write( const void* buf, uint8_t len, const bool multicast )
vipinranka 12:9a20164dcc47 719 {
vipinranka 12:9a20164dcc47 720 //Start Writing
vipinranka 12:9a20164dcc47 721 startFastWrite(buf,len,multicast);
vipinranka 12:9a20164dcc47 722
vipinranka 12:9a20164dcc47 723 //Wait until complete or failed
vipinranka 12:9a20164dcc47 724 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
vipinranka 12:9a20164dcc47 725 uint32_t timer = mainTimer.read_ms();
vipinranka 12:9a20164dcc47 726 #endif
vipinranka 12:9a20164dcc47 727
vipinranka 12:9a20164dcc47 728 while( ! ( get_status() & ( _BV(TX_DS) | _BV(MAX_RT) ))) {
vipinranka 12:9a20164dcc47 729 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
vipinranka 12:9a20164dcc47 730 if(mainTimer.read_ms() - timer > 95) {
vipinranka 12:9a20164dcc47 731 errNotify();
vipinranka 12:9a20164dcc47 732 #if defined (FAILURE_HANDLING)
vipinranka 12:9a20164dcc47 733 return 0;
vipinranka 12:9a20164dcc47 734 #else
vipinranka 12:9a20164dcc47 735 wait_ms(100);
vipinranka 12:9a20164dcc47 736 #endif
vipinranka 12:9a20164dcc47 737 }
vipinranka 12:9a20164dcc47 738 #endif
vipinranka 12:9a20164dcc47 739 }
vipinranka 12:9a20164dcc47 740
vipinranka 12:9a20164dcc47 741 ce(LOW);
vipinranka 12:9a20164dcc47 742
vipinranka 12:9a20164dcc47 743 uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
vipinranka 12:9a20164dcc47 744
vipinranka 12:9a20164dcc47 745 //Max retries exceeded
vipinranka 12:9a20164dcc47 746 if( status & _BV(MAX_RT)) {
vipinranka 12:9a20164dcc47 747 flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush
vipinranka 12:9a20164dcc47 748 return 0;
vipinranka 12:9a20164dcc47 749 }
vipinranka 12:9a20164dcc47 750 //TX OK 1 or 0
vipinranka 12:9a20164dcc47 751 return 1;
vipinranka 12:9a20164dcc47 752 }
vipinranka 12:9a20164dcc47 753
vipinranka 12:9a20164dcc47 754 bool RF24::write( const void* buf, uint8_t len )
vipinranka 12:9a20164dcc47 755 {
vipinranka 12:9a20164dcc47 756 return write(buf,len,0);
vipinranka 12:9a20164dcc47 757 }
vipinranka 12:9a20164dcc47 758 /****************************************************************************/
vipinranka 12:9a20164dcc47 759
vipinranka 12:9a20164dcc47 760 //For general use, the interrupt flags are not important to clear
vipinranka 12:9a20164dcc47 761 bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout )
vipinranka 12:9a20164dcc47 762 {
vipinranka 12:9a20164dcc47 763 //Block until the FIFO is NOT full.
vipinranka 12:9a20164dcc47 764 //Keep track of the MAX retries and set auto-retry if seeing failures
vipinranka 12:9a20164dcc47 765 //This way the FIFO will fill up and allow blocking until packets go through
vipinranka 12:9a20164dcc47 766 //The radio will auto-clear everything in the FIFO as long as CE remains high
vipinranka 12:9a20164dcc47 767
vipinranka 12:9a20164dcc47 768 uint32_t timer = mainTimer.read_ms(); //Get the time that the payload transmission started
vipinranka 12:9a20164dcc47 769
vipinranka 12:9a20164dcc47 770 while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout
vipinranka 12:9a20164dcc47 771
vipinranka 12:9a20164dcc47 772 if( get_status() & _BV(MAX_RT)) { //If MAX Retries have been reached
vipinranka 12:9a20164dcc47 773 reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag
vipinranka 12:9a20164dcc47 774 if(mainTimer.read_ms() - timer > timeout) {
vipinranka 12:9a20164dcc47 775 return 0; //If this payload has exceeded the user-defined timeout, exit and return 0
vipinranka 12:9a20164dcc47 776 }
vipinranka 12:9a20164dcc47 777 }
vipinranka 12:9a20164dcc47 778 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
vipinranka 12:9a20164dcc47 779 if(mainTimer.read_ms() - timer > (timeout+95) ) {
vipinranka 12:9a20164dcc47 780 errNotify();
vipinranka 12:9a20164dcc47 781 #if defined (FAILURE_HANDLING)
vipinranka 12:9a20164dcc47 782 return 0;
vipinranka 12:9a20164dcc47 783 #endif
vipinranka 12:9a20164dcc47 784 }
vipinranka 12:9a20164dcc47 785 #endif
vipinranka 12:9a20164dcc47 786
vipinranka 12:9a20164dcc47 787 }
vipinranka 12:9a20164dcc47 788
vipinranka 12:9a20164dcc47 789 //Start Writing
vipinranka 12:9a20164dcc47 790 startFastWrite(buf,len,0); //Write the payload if a buffer is clear
vipinranka 12:9a20164dcc47 791
vipinranka 12:9a20164dcc47 792 return 1; //Return 1 to indicate successful transmission
vipinranka 12:9a20164dcc47 793 }
vipinranka 12:9a20164dcc47 794
vipinranka 12:9a20164dcc47 795 /****************************************************************************/
vipinranka 12:9a20164dcc47 796
vipinranka 12:9a20164dcc47 797 void RF24::reUseTX()
vipinranka 12:9a20164dcc47 798 {
vipinranka 12:9a20164dcc47 799 write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
vipinranka 12:9a20164dcc47 800 spiTrans( REUSE_TX_PL );
vipinranka 12:9a20164dcc47 801 ce(LOW); //Re-Transfer packet
vipinranka 12:9a20164dcc47 802 ce(HIGH);
vipinranka 12:9a20164dcc47 803 }
vipinranka 12:9a20164dcc47 804
vipinranka 12:9a20164dcc47 805 /****************************************************************************/
vipinranka 12:9a20164dcc47 806
vipinranka 12:9a20164dcc47 807 bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast )
vipinranka 12:9a20164dcc47 808 {
vipinranka 12:9a20164dcc47 809 //Block until the FIFO is NOT full.
vipinranka 12:9a20164dcc47 810 //Keep track of the MAX retries and set auto-retry if seeing failures
vipinranka 12:9a20164dcc47 811 //Return 0 so the user can control the retrys and set a timer or failure counter if required
vipinranka 12:9a20164dcc47 812 //The radio will auto-clear everything in the FIFO as long as CE remains high
vipinranka 12:9a20164dcc47 813
vipinranka 12:9a20164dcc47 814 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
vipinranka 12:9a20164dcc47 815 uint32_t timer = mainTimer.read_ms();
vipinranka 12:9a20164dcc47 816 #endif
vipinranka 12:9a20164dcc47 817
vipinranka 12:9a20164dcc47 818 while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail
vipinranka 12:9a20164dcc47 819
vipinranka 12:9a20164dcc47 820 if( get_status() & _BV(MAX_RT)) {
vipinranka 12:9a20164dcc47 821 //reUseTX(); //Set re-transmit
vipinranka 12:9a20164dcc47 822 write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag
vipinranka 12:9a20164dcc47 823 return 0; //Return 0. The previous payload has been retransmitted
vipinranka 12:9a20164dcc47 824 //From the user perspective, if you get a 0, just keep trying to send the same payload
vipinranka 12:9a20164dcc47 825 }
vipinranka 12:9a20164dcc47 826 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
vipinranka 12:9a20164dcc47 827 if(mainTimer.read_ms() - timer > 95 ) {
vipinranka 12:9a20164dcc47 828 errNotify();
vipinranka 12:9a20164dcc47 829 #if defined (FAILURE_HANDLING)
vipinranka 12:9a20164dcc47 830 return 0;
vipinranka 12:9a20164dcc47 831 #endif
vipinranka 12:9a20164dcc47 832 }
vipinranka 12:9a20164dcc47 833 #endif
vipinranka 12:9a20164dcc47 834 }
vipinranka 12:9a20164dcc47 835 //Start Writing
vipinranka 12:9a20164dcc47 836 startFastWrite(buf,len,multicast);
vipinranka 12:9a20164dcc47 837
vipinranka 12:9a20164dcc47 838 return 1;
vipinranka 12:9a20164dcc47 839 }
vipinranka 12:9a20164dcc47 840
vipinranka 12:9a20164dcc47 841 bool RF24::writeFast( const void* buf, uint8_t len )
vipinranka 12:9a20164dcc47 842 {
vipinranka 12:9a20164dcc47 843 return writeFast(buf,len,0);
vipinranka 12:9a20164dcc47 844 }
vipinranka 12:9a20164dcc47 845
vipinranka 12:9a20164dcc47 846 /****************************************************************************/
vipinranka 12:9a20164dcc47 847
vipinranka 12:9a20164dcc47 848 //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high
vipinranka 12:9a20164dcc47 849 //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay)
vipinranka 12:9a20164dcc47 850 //Otherwise we enter Standby-II mode, which is still faster than standby mode
vipinranka 12:9a20164dcc47 851 //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data
vipinranka 12:9a20164dcc47 852
vipinranka 12:9a20164dcc47 853 void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx) //TMRh20
vipinranka 12:9a20164dcc47 854 {
vipinranka 12:9a20164dcc47 855
vipinranka 12:9a20164dcc47 856 //write_payload( buf,len);
vipinranka 12:9a20164dcc47 857 write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
vipinranka 12:9a20164dcc47 858 if(startTx) {
vipinranka 12:9a20164dcc47 859 ce(HIGH);
vipinranka 12:9a20164dcc47 860 }
vipinranka 12:9a20164dcc47 861
vipinranka 12:9a20164dcc47 862 }
vipinranka 12:9a20164dcc47 863
vipinranka 12:9a20164dcc47 864 /****************************************************************************/
vipinranka 12:9a20164dcc47 865
vipinranka 12:9a20164dcc47 866 //Added the original startWrite back in so users can still use interrupts, ack payloads, etc
vipinranka 12:9a20164dcc47 867 //Allows the library to pass all tests
vipinranka 12:9a20164dcc47 868 void RF24::startWrite( const void* buf, uint8_t len, const bool multicast )
vipinranka 12:9a20164dcc47 869 {
vipinranka 12:9a20164dcc47 870
vipinranka 12:9a20164dcc47 871 // Send the payload
vipinranka 12:9a20164dcc47 872
vipinranka 12:9a20164dcc47 873 //write_payload( buf, len );
vipinranka 12:9a20164dcc47 874 write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ;
vipinranka 12:9a20164dcc47 875 ce(HIGH);
vipinranka 12:9a20164dcc47 876
vipinranka 12:9a20164dcc47 877 wait_us(10);
vipinranka 12:9a20164dcc47 878
vipinranka 12:9a20164dcc47 879 ce(LOW);
vipinranka 12:9a20164dcc47 880
vipinranka 12:9a20164dcc47 881
vipinranka 12:9a20164dcc47 882 }
vipinranka 12:9a20164dcc47 883
vipinranka 12:9a20164dcc47 884 /****************************************************************************/
vipinranka 12:9a20164dcc47 885
vipinranka 12:9a20164dcc47 886 bool RF24::rxFifoFull()
vipinranka 12:9a20164dcc47 887 {
vipinranka 12:9a20164dcc47 888 return read_register(FIFO_STATUS) & _BV(RX_FULL);
vipinranka 12:9a20164dcc47 889 }
vipinranka 12:9a20164dcc47 890 /****************************************************************************/
vipinranka 12:9a20164dcc47 891
vipinranka 12:9a20164dcc47 892 bool RF24::txStandBy()
vipinranka 12:9a20164dcc47 893 {
vipinranka 12:9a20164dcc47 894
vipinranka 12:9a20164dcc47 895 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
vipinranka 12:9a20164dcc47 896 uint32_t timeout = mainTimer.read_ms();
vipinranka 12:9a20164dcc47 897 #endif
vipinranka 12:9a20164dcc47 898 while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ) {
vipinranka 12:9a20164dcc47 899 if( get_status() & _BV(MAX_RT)) {
vipinranka 12:9a20164dcc47 900 write_register(NRF_STATUS,_BV(MAX_RT) );
vipinranka 12:9a20164dcc47 901 ce(LOW);
vipinranka 12:9a20164dcc47 902 flush_tx(); //Non blocking, flush the data
vipinranka 12:9a20164dcc47 903 return 0;
vipinranka 12:9a20164dcc47 904 }
vipinranka 12:9a20164dcc47 905 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
vipinranka 12:9a20164dcc47 906 if( mainTimer.read_ms() - timeout > 95) {
vipinranka 12:9a20164dcc47 907 errNotify();
vipinranka 12:9a20164dcc47 908 #if defined (FAILURE_HANDLING)
vipinranka 12:9a20164dcc47 909 return 0;
vipinranka 12:9a20164dcc47 910 #endif
vipinranka 12:9a20164dcc47 911 }
vipinranka 12:9a20164dcc47 912 #endif
vipinranka 12:9a20164dcc47 913 }
vipinranka 12:9a20164dcc47 914
vipinranka 12:9a20164dcc47 915 ce(LOW); //Set STANDBY-I mode
vipinranka 12:9a20164dcc47 916 return 1;
vipinranka 12:9a20164dcc47 917 }
vipinranka 12:9a20164dcc47 918
vipinranka 12:9a20164dcc47 919 /****************************************************************************/
vipinranka 12:9a20164dcc47 920
vipinranka 12:9a20164dcc47 921 bool RF24::txStandBy(uint32_t timeout, bool startTx)
vipinranka 12:9a20164dcc47 922 {
vipinranka 12:9a20164dcc47 923
vipinranka 12:9a20164dcc47 924 if(startTx) {
vipinranka 12:9a20164dcc47 925 stopListening();
vipinranka 12:9a20164dcc47 926 ce(HIGH);
vipinranka 12:9a20164dcc47 927 }
vipinranka 12:9a20164dcc47 928 uint32_t start = mainTimer.read_ms();
vipinranka 12:9a20164dcc47 929
vipinranka 12:9a20164dcc47 930 while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ) {
vipinranka 12:9a20164dcc47 931 if( get_status() & _BV(MAX_RT)) {
vipinranka 12:9a20164dcc47 932 write_register(NRF_STATUS,_BV(MAX_RT) );
vipinranka 12:9a20164dcc47 933 ce(LOW); //Set re-transmit
vipinranka 12:9a20164dcc47 934 ce(HIGH);
vipinranka 12:9a20164dcc47 935 if(mainTimer.read_ms() - start >= timeout) {
vipinranka 12:9a20164dcc47 936 ce(LOW);
vipinranka 12:9a20164dcc47 937 flush_tx();
vipinranka 12:9a20164dcc47 938 return 0;
vipinranka 12:9a20164dcc47 939 }
vipinranka 12:9a20164dcc47 940 }
vipinranka 12:9a20164dcc47 941 #if defined (FAILURE_HANDLING) || defined (RF24_LINUX)
vipinranka 12:9a20164dcc47 942 if( mainTimer.read_ms() - start > (timeout+95)) {
vipinranka 12:9a20164dcc47 943 errNotify();
vipinranka 12:9a20164dcc47 944 #if defined (FAILURE_HANDLING)
vipinranka 12:9a20164dcc47 945 return 0;
vipinranka 12:9a20164dcc47 946 #endif
vipinranka 12:9a20164dcc47 947 }
vipinranka 12:9a20164dcc47 948 #endif
vipinranka 12:9a20164dcc47 949 }
vipinranka 12:9a20164dcc47 950
vipinranka 12:9a20164dcc47 951
vipinranka 12:9a20164dcc47 952 ce(LOW); //Set STANDBY-I mode
vipinranka 12:9a20164dcc47 953 return 1;
vipinranka 12:9a20164dcc47 954
vipinranka 12:9a20164dcc47 955 }
vipinranka 12:9a20164dcc47 956
vipinranka 12:9a20164dcc47 957 /****************************************************************************/
vipinranka 12:9a20164dcc47 958
vipinranka 12:9a20164dcc47 959 void RF24::maskIRQ(bool tx, bool fail, bool rx)
vipinranka 12:9a20164dcc47 960 {
vipinranka 12:9a20164dcc47 961
vipinranka 12:9a20164dcc47 962 uint8_t config = read_register(NRF_CONFIG);
vipinranka 12:9a20164dcc47 963 /* clear the interrupt flags */
vipinranka 12:9a20164dcc47 964 config &= ~(1 << MASK_MAX_RT | 1 << MASK_TX_DS | 1 << MASK_RX_DR);
vipinranka 12:9a20164dcc47 965 /* set the specified interrupt flags */
vipinranka 12:9a20164dcc47 966 config |= fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR;
vipinranka 12:9a20164dcc47 967 write_register(NRF_CONFIG, config);
vipinranka 12:9a20164dcc47 968 }
vipinranka 12:9a20164dcc47 969
vipinranka 12:9a20164dcc47 970 /****************************************************************************/
vipinranka 12:9a20164dcc47 971
vipinranka 12:9a20164dcc47 972 uint8_t RF24::getDynamicPayloadSize(void)
vipinranka 12:9a20164dcc47 973 {
vipinranka 12:9a20164dcc47 974 uint8_t result = 0;
vipinranka 12:9a20164dcc47 975
vipinranka 12:9a20164dcc47 976
vipinranka 12:9a20164dcc47 977
vipinranka 12:9a20164dcc47 978
vipinranka 12:9a20164dcc47 979
vipinranka 12:9a20164dcc47 980
vipinranka 12:9a20164dcc47 981
vipinranka 12:9a20164dcc47 982
vipinranka 12:9a20164dcc47 983
vipinranka 12:9a20164dcc47 984 beginTransaction();
vipinranka 12:9a20164dcc47 985 spi.write( R_RX_PL_WID );
vipinranka 12:9a20164dcc47 986 result = spi.write(0xff);
vipinranka 12:9a20164dcc47 987 endTransaction();
vipinranka 12:9a20164dcc47 988
vipinranka 12:9a20164dcc47 989
vipinranka 12:9a20164dcc47 990 if(result > 32) {
vipinranka 12:9a20164dcc47 991 flush_rx();
vipinranka 12:9a20164dcc47 992 wait_ms(2);
vipinranka 12:9a20164dcc47 993 return 0;
vipinranka 12:9a20164dcc47 994 }
vipinranka 12:9a20164dcc47 995 return result;
vipinranka 12:9a20164dcc47 996 }
vipinranka 12:9a20164dcc47 997
vipinranka 12:9a20164dcc47 998 /****************************************************************************/
vipinranka 12:9a20164dcc47 999
vipinranka 12:9a20164dcc47 1000 bool RF24::available(void)
vipinranka 12:9a20164dcc47 1001 {
vipinranka 12:9a20164dcc47 1002 return available(NULL);
vipinranka 12:9a20164dcc47 1003 }
vipinranka 12:9a20164dcc47 1004
vipinranka 12:9a20164dcc47 1005 /****************************************************************************/
vipinranka 12:9a20164dcc47 1006
vipinranka 12:9a20164dcc47 1007 bool RF24::available(uint8_t* pipe_num)
vipinranka 12:9a20164dcc47 1008 {
vipinranka 12:9a20164dcc47 1009 if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )) {
vipinranka 12:9a20164dcc47 1010
vipinranka 12:9a20164dcc47 1011 // If the caller wants the pipe number, include that
vipinranka 12:9a20164dcc47 1012 if ( pipe_num ) {
vipinranka 12:9a20164dcc47 1013 uint8_t status = get_status();
vipinranka 12:9a20164dcc47 1014 *pipe_num = ( status >> RX_P_NO ) & 0b111;
vipinranka 12:9a20164dcc47 1015 }
vipinranka 12:9a20164dcc47 1016 return 1;
vipinranka 12:9a20164dcc47 1017 }
vipinranka 12:9a20164dcc47 1018
vipinranka 12:9a20164dcc47 1019
vipinranka 12:9a20164dcc47 1020 return 0;
vipinranka 12:9a20164dcc47 1021
vipinranka 12:9a20164dcc47 1022
vipinranka 12:9a20164dcc47 1023 }
vipinranka 12:9a20164dcc47 1024
vipinranka 12:9a20164dcc47 1025 /****************************************************************************/
vipinranka 12:9a20164dcc47 1026
vipinranka 12:9a20164dcc47 1027 void RF24::read( void* buf, uint8_t len )
vipinranka 12:9a20164dcc47 1028 {
vipinranka 12:9a20164dcc47 1029
vipinranka 12:9a20164dcc47 1030 // Fetch the payload
vipinranka 12:9a20164dcc47 1031 read_payload( buf, len );
vipinranka 12:9a20164dcc47 1032
vipinranka 12:9a20164dcc47 1033 //Clear the two possible interrupt flags with one command
vipinranka 12:9a20164dcc47 1034 write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) );
vipinranka 12:9a20164dcc47 1035
vipinranka 12:9a20164dcc47 1036 }
vipinranka 12:9a20164dcc47 1037
vipinranka 12:9a20164dcc47 1038 /****************************************************************************/
vipinranka 12:9a20164dcc47 1039
vipinranka 12:9a20164dcc47 1040 void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready)
vipinranka 12:9a20164dcc47 1041 {
vipinranka 12:9a20164dcc47 1042 // Read the status & reset the status in one easy call
vipinranka 12:9a20164dcc47 1043 // Or is that such a good idea?
vipinranka 12:9a20164dcc47 1044 uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
vipinranka 12:9a20164dcc47 1045
vipinranka 12:9a20164dcc47 1046 // Report to the user what happened
vipinranka 12:9a20164dcc47 1047 tx_ok = status & _BV(TX_DS);
vipinranka 12:9a20164dcc47 1048 tx_fail = status & _BV(MAX_RT);
vipinranka 12:9a20164dcc47 1049 rx_ready = status & _BV(RX_DR);
vipinranka 12:9a20164dcc47 1050 }
vipinranka 12:9a20164dcc47 1051
vipinranka 12:9a20164dcc47 1052 /****************************************************************************/
vipinranka 12:9a20164dcc47 1053
vipinranka 12:9a20164dcc47 1054 void RF24::openWritingPipe(uint64_t value)
vipinranka 12:9a20164dcc47 1055 {
vipinranka 12:9a20164dcc47 1056 // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
vipinranka 12:9a20164dcc47 1057 // expects it LSB first too, so we're good.
vipinranka 12:9a20164dcc47 1058
vipinranka 12:9a20164dcc47 1059 write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width);
vipinranka 12:9a20164dcc47 1060 write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width);
vipinranka 12:9a20164dcc47 1061
vipinranka 12:9a20164dcc47 1062
vipinranka 12:9a20164dcc47 1063 //const uint8_t max_payload_size = 32;
vipinranka 12:9a20164dcc47 1064 //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
vipinranka 12:9a20164dcc47 1065 write_register(RX_PW_P0,payload_size);
vipinranka 12:9a20164dcc47 1066 }
vipinranka 12:9a20164dcc47 1067
vipinranka 12:9a20164dcc47 1068 /****************************************************************************/
vipinranka 12:9a20164dcc47 1069 void RF24::openWritingPipe(const uint8_t *address)
vipinranka 12:9a20164dcc47 1070 {
vipinranka 12:9a20164dcc47 1071 // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+)
vipinranka 12:9a20164dcc47 1072 // expects it LSB first too, so we're good.
vipinranka 12:9a20164dcc47 1073
vipinranka 12:9a20164dcc47 1074 write_register(RX_ADDR_P0,address, addr_width);
vipinranka 12:9a20164dcc47 1075 write_register(TX_ADDR, address, addr_width);
vipinranka 12:9a20164dcc47 1076
vipinranka 12:9a20164dcc47 1077 //const uint8_t max_payload_size = 32;
vipinranka 12:9a20164dcc47 1078 //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size));
vipinranka 12:9a20164dcc47 1079 write_register(RX_PW_P0,payload_size);
vipinranka 12:9a20164dcc47 1080 }
vipinranka 12:9a20164dcc47 1081
vipinranka 12:9a20164dcc47 1082 /****************************************************************************/
vipinranka 12:9a20164dcc47 1083 static const uint8_t child_pipe[] PROGMEM = {
vipinranka 12:9a20164dcc47 1084 RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5
vipinranka 12:9a20164dcc47 1085 };
vipinranka 12:9a20164dcc47 1086 static const uint8_t child_payload_size[] PROGMEM = {
vipinranka 12:9a20164dcc47 1087 RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5
vipinranka 12:9a20164dcc47 1088 };
vipinranka 12:9a20164dcc47 1089
vipinranka 12:9a20164dcc47 1090
vipinranka 12:9a20164dcc47 1091 void RF24::openReadingPipe(uint8_t child, uint64_t address)
vipinranka 12:9a20164dcc47 1092 {
vipinranka 12:9a20164dcc47 1093 // If this is pipe 0, cache the address. This is needed because
vipinranka 12:9a20164dcc47 1094 // openWritingPipe() will overwrite the pipe 0 address, so
vipinranka 12:9a20164dcc47 1095 // startListening() will have to restore it.
vipinranka 12:9a20164dcc47 1096 if (child == 0) {
vipinranka 12:9a20164dcc47 1097 memcpy(pipe0_reading_address,&address,addr_width);
vipinranka 12:9a20164dcc47 1098 }
vipinranka 12:9a20164dcc47 1099
vipinranka 12:9a20164dcc47 1100 if (child <= 6) {
vipinranka 12:9a20164dcc47 1101 // For pipes 2-5, only write the LSB
vipinranka 12:9a20164dcc47 1102 if ( child < 2 )
vipinranka 12:9a20164dcc47 1103 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width);
vipinranka 12:9a20164dcc47 1104 else
vipinranka 12:9a20164dcc47 1105 write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1);
vipinranka 12:9a20164dcc47 1106
vipinranka 12:9a20164dcc47 1107 write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
vipinranka 12:9a20164dcc47 1108
vipinranka 12:9a20164dcc47 1109 // Note it would be more efficient to set all of the bits for all open
vipinranka 12:9a20164dcc47 1110 // pipes at once. However, I thought it would make the calling code
vipinranka 12:9a20164dcc47 1111 // more simple to do it this way.
vipinranka 12:9a20164dcc47 1112 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
vipinranka 12:9a20164dcc47 1113 }
vipinranka 12:9a20164dcc47 1114 }
vipinranka 12:9a20164dcc47 1115
vipinranka 12:9a20164dcc47 1116 /****************************************************************************/
vipinranka 12:9a20164dcc47 1117 void RF24::setAddressWidth(uint8_t a_width)
vipinranka 12:9a20164dcc47 1118 {
vipinranka 12:9a20164dcc47 1119
vipinranka 12:9a20164dcc47 1120 if(a_width -= 2) {
vipinranka 12:9a20164dcc47 1121 write_register(SETUP_AW,a_width%4);
vipinranka 12:9a20164dcc47 1122 addr_width = (a_width%4) + 2;
vipinranka 12:9a20164dcc47 1123 }
vipinranka 12:9a20164dcc47 1124
vipinranka 12:9a20164dcc47 1125 }
vipinranka 12:9a20164dcc47 1126
vipinranka 12:9a20164dcc47 1127 /****************************************************************************/
vipinranka 12:9a20164dcc47 1128
vipinranka 12:9a20164dcc47 1129 void RF24::openReadingPipe(uint8_t child, const uint8_t *address)
vipinranka 12:9a20164dcc47 1130 {
vipinranka 12:9a20164dcc47 1131 // If this is pipe 0, cache the address. This is needed because
vipinranka 12:9a20164dcc47 1132 // openWritingPipe() will overwrite the pipe 0 address, so
vipinranka 12:9a20164dcc47 1133 // startListening() will have to restore it.
vipinranka 12:9a20164dcc47 1134 if (child == 0) {
vipinranka 12:9a20164dcc47 1135 memcpy(pipe0_reading_address,address,addr_width);
vipinranka 12:9a20164dcc47 1136 }
vipinranka 12:9a20164dcc47 1137 if (child <= 6) {
vipinranka 12:9a20164dcc47 1138 // For pipes 2-5, only write the LSB
vipinranka 12:9a20164dcc47 1139 if ( child < 2 ) {
vipinranka 12:9a20164dcc47 1140 write_register(pgm_read_byte(&child_pipe[child]), address, addr_width);
vipinranka 12:9a20164dcc47 1141 } else {
vipinranka 12:9a20164dcc47 1142 write_register(pgm_read_byte(&child_pipe[child]), address, 1);
vipinranka 12:9a20164dcc47 1143 }
vipinranka 12:9a20164dcc47 1144 write_register(pgm_read_byte(&child_payload_size[child]),payload_size);
vipinranka 12:9a20164dcc47 1145
vipinranka 12:9a20164dcc47 1146 // Note it would be more efficient to set all of the bits for all open
vipinranka 12:9a20164dcc47 1147 // pipes at once. However, I thought it would make the calling code
vipinranka 12:9a20164dcc47 1148 // more simple to do it this way.
vipinranka 12:9a20164dcc47 1149 write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child])));
vipinranka 12:9a20164dcc47 1150
vipinranka 12:9a20164dcc47 1151 }
vipinranka 12:9a20164dcc47 1152 }
vipinranka 12:9a20164dcc47 1153
vipinranka 12:9a20164dcc47 1154 /****************************************************************************/
vipinranka 12:9a20164dcc47 1155
vipinranka 12:9a20164dcc47 1156 void RF24::closeReadingPipe( uint8_t pipe )
vipinranka 12:9a20164dcc47 1157 {
vipinranka 12:9a20164dcc47 1158 write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe])));
vipinranka 12:9a20164dcc47 1159 }
vipinranka 12:9a20164dcc47 1160
vipinranka 12:9a20164dcc47 1161 /****************************************************************************/
vipinranka 12:9a20164dcc47 1162
vipinranka 12:9a20164dcc47 1163 void RF24::toggle_features(void)
vipinranka 12:9a20164dcc47 1164 {
vipinranka 12:9a20164dcc47 1165 beginTransaction();
vipinranka 12:9a20164dcc47 1166 spi.write( ACTIVATE );
vipinranka 12:9a20164dcc47 1167 spi.write( 0x73 );
vipinranka 12:9a20164dcc47 1168 endTransaction();
vipinranka 12:9a20164dcc47 1169 }
vipinranka 12:9a20164dcc47 1170
vipinranka 12:9a20164dcc47 1171 /****************************************************************************/
vipinranka 12:9a20164dcc47 1172
vipinranka 12:9a20164dcc47 1173 void RF24::enableDynamicPayloads(void)
vipinranka 12:9a20164dcc47 1174 {
vipinranka 12:9a20164dcc47 1175 // Enable dynamic payload throughout the system
vipinranka 12:9a20164dcc47 1176
vipinranka 12:9a20164dcc47 1177 //toggle_features();
vipinranka 12:9a20164dcc47 1178 write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) );
vipinranka 12:9a20164dcc47 1179
vipinranka 12:9a20164dcc47 1180
vipinranka 12:9a20164dcc47 1181 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
vipinranka 12:9a20164dcc47 1182
vipinranka 12:9a20164dcc47 1183 // Enable dynamic payload on all pipes
vipinranka 12:9a20164dcc47 1184 //
vipinranka 12:9a20164dcc47 1185 // Not sure the use case of only having dynamic payload on certain
vipinranka 12:9a20164dcc47 1186 // pipes, so the library does not support it.
vipinranka 12:9a20164dcc47 1187 write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0));
vipinranka 12:9a20164dcc47 1188
vipinranka 12:9a20164dcc47 1189 dynamic_payloads_enabled = true;
vipinranka 12:9a20164dcc47 1190 }
vipinranka 12:9a20164dcc47 1191
vipinranka 12:9a20164dcc47 1192 /****************************************************************************/
vipinranka 12:9a20164dcc47 1193
vipinranka 12:9a20164dcc47 1194 void RF24::enableAckPayload(void)
vipinranka 12:9a20164dcc47 1195 {
vipinranka 12:9a20164dcc47 1196 //
vipinranka 12:9a20164dcc47 1197 // enable ack payload and dynamic payload features
vipinranka 12:9a20164dcc47 1198 //
vipinranka 12:9a20164dcc47 1199
vipinranka 12:9a20164dcc47 1200 //toggle_features();
vipinranka 12:9a20164dcc47 1201 write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) );
vipinranka 12:9a20164dcc47 1202
vipinranka 12:9a20164dcc47 1203 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
vipinranka 12:9a20164dcc47 1204
vipinranka 12:9a20164dcc47 1205 //
vipinranka 12:9a20164dcc47 1206 // Enable dynamic payload on pipes 0 & 1
vipinranka 12:9a20164dcc47 1207 //
vipinranka 12:9a20164dcc47 1208
vipinranka 12:9a20164dcc47 1209 write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0));
vipinranka 12:9a20164dcc47 1210 dynamic_payloads_enabled = true;
vipinranka 12:9a20164dcc47 1211 }
vipinranka 12:9a20164dcc47 1212
vipinranka 12:9a20164dcc47 1213 /****************************************************************************/
vipinranka 12:9a20164dcc47 1214
vipinranka 12:9a20164dcc47 1215 void RF24::enableDynamicAck(void)
vipinranka 12:9a20164dcc47 1216 {
vipinranka 12:9a20164dcc47 1217 //
vipinranka 12:9a20164dcc47 1218 // enable dynamic ack features
vipinranka 12:9a20164dcc47 1219 //
vipinranka 12:9a20164dcc47 1220 //toggle_features();
vipinranka 12:9a20164dcc47 1221 write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) );
vipinranka 12:9a20164dcc47 1222
vipinranka 12:9a20164dcc47 1223 IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE)));
vipinranka 12:9a20164dcc47 1224
vipinranka 12:9a20164dcc47 1225
vipinranka 12:9a20164dcc47 1226 }
vipinranka 12:9a20164dcc47 1227
vipinranka 12:9a20164dcc47 1228 /****************************************************************************/
vipinranka 12:9a20164dcc47 1229
vipinranka 12:9a20164dcc47 1230 void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
vipinranka 12:9a20164dcc47 1231 {
vipinranka 12:9a20164dcc47 1232 const uint8_t* current = reinterpret_cast<const uint8_t*>(buf);
vipinranka 12:9a20164dcc47 1233
vipinranka 12:9a20164dcc47 1234 uint8_t data_len = rf24_min(len,32);
vipinranka 12:9a20164dcc47 1235
vipinranka 12:9a20164dcc47 1236
vipinranka 12:9a20164dcc47 1237
vipinranka 12:9a20164dcc47 1238
vipinranka 12:9a20164dcc47 1239
vipinranka 12:9a20164dcc47 1240
vipinranka 12:9a20164dcc47 1241
vipinranka 12:9a20164dcc47 1242
vipinranka 12:9a20164dcc47 1243
vipinranka 12:9a20164dcc47 1244
vipinranka 12:9a20164dcc47 1245
vipinranka 12:9a20164dcc47 1246
vipinranka 12:9a20164dcc47 1247
vipinranka 12:9a20164dcc47 1248 beginTransaction();
vipinranka 12:9a20164dcc47 1249 spi.write(W_ACK_PAYLOAD | ( pipe & 0b111 ) );
vipinranka 12:9a20164dcc47 1250
vipinranka 12:9a20164dcc47 1251 while ( data_len-- )
vipinranka 12:9a20164dcc47 1252 spi.write(*current++);
vipinranka 12:9a20164dcc47 1253 endTransaction();
vipinranka 12:9a20164dcc47 1254
vipinranka 12:9a20164dcc47 1255
vipinranka 12:9a20164dcc47 1256
vipinranka 12:9a20164dcc47 1257 }
vipinranka 12:9a20164dcc47 1258
vipinranka 12:9a20164dcc47 1259 /****************************************************************************/
vipinranka 12:9a20164dcc47 1260
vipinranka 12:9a20164dcc47 1261 bool RF24::isAckPayloadAvailable(void)
vipinranka 12:9a20164dcc47 1262 {
vipinranka 12:9a20164dcc47 1263 return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY));
vipinranka 12:9a20164dcc47 1264 }
vipinranka 12:9a20164dcc47 1265
vipinranka 12:9a20164dcc47 1266 /****************************************************************************/
vipinranka 12:9a20164dcc47 1267
vipinranka 12:9a20164dcc47 1268 bool RF24::isPVariant(void)
vipinranka 12:9a20164dcc47 1269 {
vipinranka 12:9a20164dcc47 1270 return p_variant ;
vipinranka 12:9a20164dcc47 1271 }
vipinranka 12:9a20164dcc47 1272
vipinranka 12:9a20164dcc47 1273 /****************************************************************************/
vipinranka 12:9a20164dcc47 1274
vipinranka 12:9a20164dcc47 1275 void RF24::setAutoAck(bool enable)
vipinranka 12:9a20164dcc47 1276 {
vipinranka 12:9a20164dcc47 1277 if ( enable )
vipinranka 12:9a20164dcc47 1278 write_register(EN_AA, 0b111111);
vipinranka 12:9a20164dcc47 1279 else
vipinranka 12:9a20164dcc47 1280 write_register(EN_AA, 0);
vipinranka 12:9a20164dcc47 1281 }
vipinranka 12:9a20164dcc47 1282
vipinranka 12:9a20164dcc47 1283 /****************************************************************************/
vipinranka 12:9a20164dcc47 1284
vipinranka 12:9a20164dcc47 1285 void RF24::setAutoAck( uint8_t pipe, bool enable )
vipinranka 12:9a20164dcc47 1286 {
vipinranka 12:9a20164dcc47 1287 if ( pipe <= 6 ) {
vipinranka 12:9a20164dcc47 1288 uint8_t en_aa = read_register( EN_AA ) ;
vipinranka 12:9a20164dcc47 1289 if( enable ) {
vipinranka 12:9a20164dcc47 1290 en_aa |= _BV(pipe) ;
vipinranka 12:9a20164dcc47 1291 } else {
vipinranka 12:9a20164dcc47 1292 en_aa &= ~_BV(pipe) ;
vipinranka 12:9a20164dcc47 1293 }
vipinranka 12:9a20164dcc47 1294 write_register( EN_AA, en_aa ) ;
vipinranka 12:9a20164dcc47 1295 }
vipinranka 12:9a20164dcc47 1296 }
vipinranka 12:9a20164dcc47 1297
vipinranka 12:9a20164dcc47 1298 /****************************************************************************/
vipinranka 12:9a20164dcc47 1299
vipinranka 12:9a20164dcc47 1300 bool RF24::testCarrier(void)
vipinranka 12:9a20164dcc47 1301 {
vipinranka 12:9a20164dcc47 1302 return ( read_register(CD) & 1 );
vipinranka 12:9a20164dcc47 1303 }
vipinranka 12:9a20164dcc47 1304
vipinranka 12:9a20164dcc47 1305 /****************************************************************************/
vipinranka 12:9a20164dcc47 1306
vipinranka 12:9a20164dcc47 1307 bool RF24::testRPD(void)
vipinranka 12:9a20164dcc47 1308 {
vipinranka 12:9a20164dcc47 1309 return ( read_register(RPD) & 1 ) ;
vipinranka 12:9a20164dcc47 1310 }
vipinranka 12:9a20164dcc47 1311
vipinranka 12:9a20164dcc47 1312 /****************************************************************************/
vipinranka 12:9a20164dcc47 1313
vipinranka 12:9a20164dcc47 1314 void RF24::setPALevel(uint8_t level)
vipinranka 12:9a20164dcc47 1315 {
vipinranka 12:9a20164dcc47 1316
vipinranka 12:9a20164dcc47 1317 uint8_t setup = read_register(RF_SETUP) & 0b11111000;
vipinranka 12:9a20164dcc47 1318
vipinranka 12:9a20164dcc47 1319 if(level > 3) { // If invalid level, go to max PA
vipinranka 12:9a20164dcc47 1320 level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit
vipinranka 12:9a20164dcc47 1321 } else {
vipinranka 12:9a20164dcc47 1322 level = (level << 1) + 1; // Else set level as requested
vipinranka 12:9a20164dcc47 1323 }
vipinranka 12:9a20164dcc47 1324
vipinranka 12:9a20164dcc47 1325
vipinranka 12:9a20164dcc47 1326 write_register( RF_SETUP, setup |= level ) ; // Write it to the chip
vipinranka 12:9a20164dcc47 1327 }
vipinranka 12:9a20164dcc47 1328
vipinranka 12:9a20164dcc47 1329 /****************************************************************************/
vipinranka 12:9a20164dcc47 1330
vipinranka 12:9a20164dcc47 1331 uint8_t RF24::getPALevel(void)
vipinranka 12:9a20164dcc47 1332 {
vipinranka 12:9a20164dcc47 1333
vipinranka 12:9a20164dcc47 1334 return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ;
vipinranka 12:9a20164dcc47 1335 }
vipinranka 12:9a20164dcc47 1336
vipinranka 12:9a20164dcc47 1337 /****************************************************************************/
vipinranka 12:9a20164dcc47 1338
vipinranka 12:9a20164dcc47 1339 bool RF24::setDataRate(rf24_datarate_e speed)
vipinranka 12:9a20164dcc47 1340 {
vipinranka 12:9a20164dcc47 1341 bool result = false;
vipinranka 12:9a20164dcc47 1342 uint8_t setup = read_register(RF_SETUP) ;
vipinranka 12:9a20164dcc47 1343
vipinranka 12:9a20164dcc47 1344 // HIGH and LOW '00' is 1Mbs - our default
vipinranka 12:9a20164dcc47 1345 setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ;
vipinranka 12:9a20164dcc47 1346
vipinranka 12:9a20164dcc47 1347
vipinranka 12:9a20164dcc47 1348
vipinranka 12:9a20164dcc47 1349
vipinranka 12:9a20164dcc47 1350 txRxDelay=85;
vipinranka 12:9a20164dcc47 1351
vipinranka 12:9a20164dcc47 1352 if( speed == RF24_250KBPS ) {
vipinranka 12:9a20164dcc47 1353 // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0
vipinranka 12:9a20164dcc47 1354 // Making it '10'.
vipinranka 12:9a20164dcc47 1355 setup |= _BV( RF_DR_LOW ) ;
vipinranka 12:9a20164dcc47 1356
vipinranka 12:9a20164dcc47 1357
vipinranka 12:9a20164dcc47 1358
vipinranka 12:9a20164dcc47 1359 txRxDelay=155;
vipinranka 12:9a20164dcc47 1360
vipinranka 12:9a20164dcc47 1361 } else {
vipinranka 12:9a20164dcc47 1362 // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1
vipinranka 12:9a20164dcc47 1363 // Making it '01'
vipinranka 12:9a20164dcc47 1364 if ( speed == RF24_2MBPS ) {
vipinranka 12:9a20164dcc47 1365 setup |= _BV(RF_DR_HIGH);
vipinranka 12:9a20164dcc47 1366
vipinranka 12:9a20164dcc47 1367
vipinranka 12:9a20164dcc47 1368 //txRxDelay=65;
vipinranka 12:9a20164dcc47 1369 txRxDelay=15; //mbed works fine with this latency
vipinranka 12:9a20164dcc47 1370
vipinranka 12:9a20164dcc47 1371 }
vipinranka 12:9a20164dcc47 1372 }
vipinranka 12:9a20164dcc47 1373 write_register(RF_SETUP,setup);
vipinranka 12:9a20164dcc47 1374
vipinranka 12:9a20164dcc47 1375 // Verify our result
vipinranka 12:9a20164dcc47 1376 if ( read_register(RF_SETUP) == setup ) {
vipinranka 12:9a20164dcc47 1377 result = true;
vipinranka 12:9a20164dcc47 1378 }
vipinranka 12:9a20164dcc47 1379 return result;
vipinranka 12:9a20164dcc47 1380 }
vipinranka 12:9a20164dcc47 1381
vipinranka 12:9a20164dcc47 1382 /****************************************************************************/
vipinranka 12:9a20164dcc47 1383
vipinranka 12:9a20164dcc47 1384 rf24_datarate_e RF24::getDataRate( void )
vipinranka 12:9a20164dcc47 1385 {
vipinranka 12:9a20164dcc47 1386 rf24_datarate_e result ;
vipinranka 12:9a20164dcc47 1387 uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH));
vipinranka 12:9a20164dcc47 1388
vipinranka 12:9a20164dcc47 1389 // switch uses RAM (evil!)
vipinranka 12:9a20164dcc47 1390 // Order matters in our case below
vipinranka 12:9a20164dcc47 1391 if ( dr == _BV(RF_DR_LOW) ) {
vipinranka 12:9a20164dcc47 1392 // '10' = 250KBPS
vipinranka 12:9a20164dcc47 1393 result = RF24_250KBPS ;
vipinranka 12:9a20164dcc47 1394 } else if ( dr == _BV(RF_DR_HIGH) ) {
vipinranka 12:9a20164dcc47 1395 // '01' = 2MBPS
vipinranka 12:9a20164dcc47 1396 result = RF24_2MBPS ;
vipinranka 12:9a20164dcc47 1397 } else {
vipinranka 12:9a20164dcc47 1398 // '00' = 1MBPS
vipinranka 12:9a20164dcc47 1399 result = RF24_1MBPS ;
vipinranka 12:9a20164dcc47 1400 }
vipinranka 12:9a20164dcc47 1401 return result ;
vipinranka 12:9a20164dcc47 1402 }
vipinranka 12:9a20164dcc47 1403
vipinranka 12:9a20164dcc47 1404 /****************************************************************************/
vipinranka 12:9a20164dcc47 1405
vipinranka 12:9a20164dcc47 1406 void RF24::setCRCLength(rf24_crclength_e length)
vipinranka 12:9a20164dcc47 1407 {
vipinranka 12:9a20164dcc47 1408 uint8_t config = read_register(NRF_CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ;
vipinranka 12:9a20164dcc47 1409
vipinranka 12:9a20164dcc47 1410 // switch uses RAM (evil!)
vipinranka 12:9a20164dcc47 1411 if ( length == RF24_CRC_DISABLED ) {
vipinranka 12:9a20164dcc47 1412 // Do nothing, we turned it off above.
vipinranka 12:9a20164dcc47 1413 } else if ( length == RF24_CRC_8 ) {
vipinranka 12:9a20164dcc47 1414 config |= _BV(EN_CRC);
vipinranka 12:9a20164dcc47 1415 } else {
vipinranka 12:9a20164dcc47 1416 config |= _BV(EN_CRC);
vipinranka 12:9a20164dcc47 1417 config |= _BV( CRCO );
vipinranka 12:9a20164dcc47 1418 }
vipinranka 12:9a20164dcc47 1419 write_register( NRF_CONFIG, config ) ;
vipinranka 12:9a20164dcc47 1420 }
vipinranka 12:9a20164dcc47 1421
vipinranka 12:9a20164dcc47 1422 /****************************************************************************/
vipinranka 12:9a20164dcc47 1423
vipinranka 12:9a20164dcc47 1424 rf24_crclength_e RF24::getCRCLength(void)
vipinranka 12:9a20164dcc47 1425 {
vipinranka 12:9a20164dcc47 1426 rf24_crclength_e result = RF24_CRC_DISABLED;
vipinranka 12:9a20164dcc47 1427
vipinranka 12:9a20164dcc47 1428 uint8_t config = read_register(NRF_CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ;
vipinranka 12:9a20164dcc47 1429 uint8_t AA = read_register(EN_AA);
vipinranka 12:9a20164dcc47 1430
vipinranka 12:9a20164dcc47 1431 if ( config & _BV(EN_CRC ) || AA) {
vipinranka 12:9a20164dcc47 1432 if ( config & _BV(CRCO) )
vipinranka 12:9a20164dcc47 1433 result = RF24_CRC_16;
vipinranka 12:9a20164dcc47 1434 else
vipinranka 12:9a20164dcc47 1435 result = RF24_CRC_8;
vipinranka 12:9a20164dcc47 1436 }
vipinranka 12:9a20164dcc47 1437
vipinranka 12:9a20164dcc47 1438 return result;
vipinranka 12:9a20164dcc47 1439 }
vipinranka 12:9a20164dcc47 1440
vipinranka 12:9a20164dcc47 1441 /****************************************************************************/
vipinranka 12:9a20164dcc47 1442
vipinranka 12:9a20164dcc47 1443 void RF24::disableCRC( void )
vipinranka 12:9a20164dcc47 1444 {
vipinranka 12:9a20164dcc47 1445 uint8_t disable = read_register(NRF_CONFIG) & ~_BV(EN_CRC) ;
vipinranka 12:9a20164dcc47 1446 write_register( NRF_CONFIG, disable ) ;
vipinranka 12:9a20164dcc47 1447 }
vipinranka 12:9a20164dcc47 1448
vipinranka 12:9a20164dcc47 1449 /****************************************************************************/
vipinranka 12:9a20164dcc47 1450 void RF24::setRetries(uint8_t delay, uint8_t count)
vipinranka 12:9a20164dcc47 1451 {
vipinranka 12:9a20164dcc47 1452 write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC);
vipinranka 12:9a20164dcc47 1453 }
vipinranka 12:9a20164dcc47 1454