Norimasa Okamoto / Mbed 2 deprecated USBLowsCap

USB low speed packet capture

Dependencies:   mbed

lowspeed.s@0:654d7d47e816, 2013-04-29 (annotated)

Committer:
va009039
Date:
Mon Apr 29 08:11:31 2013 +0000
Revision:
0:654d7d47e816
first commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 0:654d7d47e816 1 ; lowspeed.s 2013/4/29
va009039 0:654d7d47e816 2 ;
va009039 0:654d7d47e816 3 AREA LOWSPEED,CODE,READONLY
va009039 0:654d7d47e816 4
va009039 0:654d7d47e816 5 ; Base addresses
va009039 0:654d7d47e816 6 LPC_GPIO_BASE EQU 0x2009c000
va009039 0:654d7d47e816 7
va009039 0:654d7d47e816 8 ; GPIOs */
va009039 0:654d7d47e816 9 LPC_GPIO0_BASE EQU (LPC_GPIO_BASE + 0x00000)
va009039 0:654d7d47e816 10 LPC_GPIO1_BASE EQU (LPC_GPIO_BASE + 0x00020)
va009039 0:654d7d47e816 11 LPC_GPIO2_BASE EQU (LPC_GPIO_BASE + 0x00040)
va009039 0:654d7d47e816 12 LPC_GPIO3_BASE EQU (LPC_GPIO_BASE + 0x00060)
va009039 0:654d7d47e816 13 LPC_GPIO4_BASE EQU (LPC_GPIO_BASE + 0x00080)
va009039 0:654d7d47e816 14
va009039 0:654d7d47e816 15 ; offset
va009039 0:654d7d47e816 16 FIOPIN EQU 0x14
va009039 0:654d7d47e816 17 FIOPIN0 EQU 0x14
va009039 0:654d7d47e816 18 FIOPIN1 EQU 0x15
va009039 0:654d7d47e816 19 FIOPIN2 EQU 0x16
va009039 0:654d7d47e816 20 FIOPIN3 EQU 0x17
va009039 0:654d7d47e816 21 FIOSET EQU 0x18
va009039 0:654d7d47e816 22 FIOSET0 EQU 0x18
va009039 0:654d7d47e816 23 FIOSET1 EQU 0x19
va009039 0:654d7d47e816 24 FIOSET2 EQU 0x1a
va009039 0:654d7d47e816 25 FIOSET3 EQU 0x1b
va009039 0:654d7d47e816 26 FIOCLR EQU 0x1c
va009039 0:654d7d47e816 27 FIOCLR0 EQU 0x1c
va009039 0:654d7d47e816 28 FIOCLR1 EQU 0x1d
va009039 0:654d7d47e816 29 FIOCLR2 EQU 0x1e
va009039 0:654d7d47e816 30 FIOCLR3 EQU 0x1f
va009039 0:654d7d47e816 31
va009039 0:654d7d47e816 32 ; FIOSET2,FIOCLR2
va009039 0:654d7d47e816 33 P1_18 EQU (1<<2)
va009039 0:654d7d47e816 34 P1_20 EQU (1<<4)
va009039 0:654d7d47e816 35 ; FIOPIN0
va009039 0:654d7d47e816 36 P2_4 EQU (1<<4)
va009039 0:654d7d47e816 37 P2_5 EQU (1<<5)
va009039 0:654d7d47e816 38
va009039 0:654d7d47e816 39 LED1 EQU P1_18
va009039 0:654d7d47e816 40 LED2 EQU P1_20
va009039 0:654d7d47e816 41 p21 EQU P2_5
va009039 0:654d7d47e816 42 p22 EQU P2_4
va009039 0:654d7d47e816 43
va009039 0:654d7d47e816 44 USB_MASK EQU (p21+p22)
va009039 0:654d7d47e816 45 USB_SE0 EQU (p21+p22)
va009039 0:654d7d47e816 46 ;
va009039 0:654d7d47e816 47 ; uint8_t* capraw(uint8_t* buf, int size, int count)
va009039 0:654d7d47e816 48 ;
va009039 0:654d7d47e816 49 EXPORT capraw
va009039 0:654d7d47e816 50 capraw
va009039 0:654d7d47e816 51 PUSH {r4-r7}
va009039 0:654d7d47e816 52 LDR r6,=LPC_GPIO1_BASE
va009039 0:654d7d47e816 53 MOV r7,#LED1
va009039 0:654d7d47e816 54 cap10 LDR r4,=LPC_GPIO2_BASE+FIOPIN0 ; D+ p21(P2_5), D- p22(P2_4)
va009039 0:654d7d47e816 55 cap20 LDRB r5,[r4]
va009039 0:654d7d47e816 56 TST r5,#p21
va009039 0:654d7d47e816 57 BEQ cap20
va009039 0:654d7d47e816 58 STRB r7,[r6,#FIOSET2] ; LED1 on
va009039 0:654d7d47e816 59 cap50 LDRB r5,[r4]
va009039 0:654d7d47e816 60 STRB r5,[r0],#+1
va009039 0:654d7d47e816 61 TST r5,#USB_SE0 ; EOP ?
va009039 0:654d7d47e816 62 BNE cap70
va009039 0:654d7d47e816 63 STRB r7,[r6,#FIOCLR2] ; LED1 off
va009039 0:654d7d47e816 64 SUBS r2,r2,#1
va009039 0:654d7d47e816 65 BEQ cap90
va009039 0:654d7d47e816 66 B cap10
va009039 0:654d7d47e816 67 cap70 SUBS r1,r1,#1 ; buffer full ?
va009039 0:654d7d47e816 68 BNE cap50
va009039 0:654d7d47e816 69 cap90 POP {r4-r7}
va009039 0:654d7d47e816 70 BX lr
va009039 0:654d7d47e816 71
va009039 0:654d7d47e816 72 ALIGN
va009039 0:654d7d47e816 73 END
va009039 0:654d7d47e816 74