S K UCI / PowerControlClkPatch

Patched version of the PowerControl library that handles (re)starting clocks such that (ETH) power can be brought up and down repeatedly without stalling the mbed.

Dependents:   AutonomousDAQ AutonomousDAQ

EthernetPowerControl.h@4:e5a50000fcfb, 2013-10-05 (annotated)

Committer:
uci1
Date:
Sat Oct 05 04:31:08 2013 +0000
Revision:
4:e5a50000fcfb
Parent:
0:334c4560cd83 
allow optional use of the rtos wait

Who changed what in which revision?

UserRevisionLine numberNew contents of line
uci1 0:334c4560cd83 1 /* mbed PowerControl Library
uci1 0:334c4560cd83 2 * Copyright (c) 2010 Michael Wei
uci1 0:334c4560cd83 3 */
uci1 0:334c4560cd83 4
uci1 0:334c4560cd83 5 #ifndef MBED_POWERCONTROL_ETH_H
uci1 0:334c4560cd83 6 #define MBED_POWERCONTROL_ETH_H
uci1 0:334c4560cd83 7
uci1 0:334c4560cd83 8 #include "mbed.h"
uci1 0:334c4560cd83 9 #include "PowerControl.h"
uci1 0:334c4560cd83 10
uci1 0:334c4560cd83 11 #define PHY_REG_BMCR_POWERDOWN 0xB
uci1 0:334c4560cd83 12 #define PHY_REG_EDCR_ENABLE 0xF
uci1 0:334c4560cd83 13
uci1 0:334c4560cd83 14
uci1 0:334c4560cd83 15 void EMAC_Init();
uci1 0:334c4560cd83 16 static unsigned short read_PHY (unsigned int PhyReg);
uci1 0:334c4560cd83 17 static void write_PHY (unsigned int PhyReg, unsigned short Value);
uci1 0:334c4560cd83 18
uci1 0:334c4560cd83 19 void PHY_PowerDown(void);
uci1 0:334c4560cd83 20 void PHY_PowerUp(void);
uci1 0:334c4560cd83 21 void PHY_EnergyDetect_Enable(void);
uci1 0:334c4560cd83 22 void PHY_EnergyDetect_Disable(void);
uci1 0:334c4560cd83 23
uci1 0:334c4560cd83 24 //From NXP Sample Code .... Probably from KEIL sample code
uci1 0:334c4560cd83 25 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
uci1 0:334c4560cd83 26 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
uci1 0:334c4560cd83 27 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
uci1 0:334c4560cd83 28 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
uci1 0:334c4560cd83 29
uci1 0:334c4560cd83 30 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
uci1 0:334c4560cd83 31
uci1 0:334c4560cd83 32 /* EMAC variables located in 16K Ethernet SRAM */
uci1 0:334c4560cd83 33 #define RX_DESC_BASE 0x20080000
uci1 0:334c4560cd83 34 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
uci1 0:334c4560cd83 35 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
uci1 0:334c4560cd83 36 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
uci1 0:334c4560cd83 37 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
uci1 0:334c4560cd83 38 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
uci1 0:334c4560cd83 39
uci1 0:334c4560cd83 40 /* RX and TX descriptor and status definitions. */
uci1 0:334c4560cd83 41 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
uci1 0:334c4560cd83 42 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
uci1 0:334c4560cd83 43 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
uci1 0:334c4560cd83 44 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
uci1 0:334c4560cd83 45 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
uci1 0:334c4560cd83 46 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
uci1 0:334c4560cd83 47 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
uci1 0:334c4560cd83 48 #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
uci1 0:334c4560cd83 49 #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
uci1 0:334c4560cd83 50
uci1 0:334c4560cd83 51 /* MAC Configuration Register 1 */
uci1 0:334c4560cd83 52 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
uci1 0:334c4560cd83 53 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
uci1 0:334c4560cd83 54 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
uci1 0:334c4560cd83 55 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
uci1 0:334c4560cd83 56 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
uci1 0:334c4560cd83 57 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
uci1 0:334c4560cd83 58 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
uci1 0:334c4560cd83 59 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
uci1 0:334c4560cd83 60 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
uci1 0:334c4560cd83 61 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
uci1 0:334c4560cd83 62 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
uci1 0:334c4560cd83 63
uci1 0:334c4560cd83 64 /* MAC Configuration Register 2 */
uci1 0:334c4560cd83 65 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
uci1 0:334c4560cd83 66 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
uci1 0:334c4560cd83 67 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
uci1 0:334c4560cd83 68 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
uci1 0:334c4560cd83 69 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
uci1 0:334c4560cd83 70 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
uci1 0:334c4560cd83 71 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
uci1 0:334c4560cd83 72 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
uci1 0:334c4560cd83 73 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
uci1 0:334c4560cd83 74 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
uci1 0:334c4560cd83 75 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
uci1 0:334c4560cd83 76 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
uci1 0:334c4560cd83 77 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
uci1 0:334c4560cd83 78
uci1 0:334c4560cd83 79 /* Back-to-Back Inter-Packet-Gap Register */
uci1 0:334c4560cd83 80 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
uci1 0:334c4560cd83 81 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
uci1 0:334c4560cd83 82
uci1 0:334c4560cd83 83 /* Non Back-to-Back Inter-Packet-Gap Register */
uci1 0:334c4560cd83 84 #define IPGR_DEF 0x00000012 /* Recommended value */
uci1 0:334c4560cd83 85
uci1 0:334c4560cd83 86 /* Collision Window/Retry Register */
uci1 0:334c4560cd83 87 #define CLRT_DEF 0x0000370F /* Default value */
uci1 0:334c4560cd83 88
uci1 0:334c4560cd83 89 /* PHY Support Register */
uci1 0:334c4560cd83 90 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
uci1 0:334c4560cd83 91 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
uci1 0:334c4560cd83 92
uci1 0:334c4560cd83 93 /* Test Register */
uci1 0:334c4560cd83 94 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
uci1 0:334c4560cd83 95 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
uci1 0:334c4560cd83 96 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
uci1 0:334c4560cd83 97
uci1 0:334c4560cd83 98 /* MII Management Configuration Register */
uci1 0:334c4560cd83 99 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
uci1 0:334c4560cd83 100 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
uci1 0:334c4560cd83 101 #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
uci1 0:334c4560cd83 102 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
uci1 0:334c4560cd83 103
uci1 0:334c4560cd83 104 /* MII Management Command Register */
uci1 0:334c4560cd83 105 #define MCMD_READ 0x00000001 /* MII Read */
uci1 0:334c4560cd83 106 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
uci1 0:334c4560cd83 107
uci1 0:334c4560cd83 108 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
uci1 0:334c4560cd83 109 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
uci1 0:334c4560cd83 110
uci1 0:334c4560cd83 111 /* MII Management Address Register */
uci1 0:334c4560cd83 112 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
uci1 0:334c4560cd83 113 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
uci1 0:334c4560cd83 114
uci1 0:334c4560cd83 115 /* MII Management Indicators Register */
uci1 0:334c4560cd83 116 #define MIND_BUSY 0x00000001 /* MII is Busy */
uci1 0:334c4560cd83 117 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
uci1 0:334c4560cd83 118 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
uci1 0:334c4560cd83 119 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
uci1 0:334c4560cd83 120
uci1 0:334c4560cd83 121 /* Command Register */
uci1 0:334c4560cd83 122 #define CR_RX_EN 0x00000001 /* Enable Receive */
uci1 0:334c4560cd83 123 #define CR_TX_EN 0x00000002 /* Enable Transmit */
uci1 0:334c4560cd83 124 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
uci1 0:334c4560cd83 125 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
uci1 0:334c4560cd83 126 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
uci1 0:334c4560cd83 127 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
uci1 0:334c4560cd83 128 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
uci1 0:334c4560cd83 129 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
uci1 0:334c4560cd83 130 #define CR_RMII 0x00000200 /* Reduced MII Interface */
uci1 0:334c4560cd83 131 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
uci1 0:334c4560cd83 132
uci1 0:334c4560cd83 133 /* Status Register */
uci1 0:334c4560cd83 134 #define SR_RX_EN 0x00000001 /* Enable Receive */
uci1 0:334c4560cd83 135 #define SR_TX_EN 0x00000002 /* Enable Transmit */
uci1 0:334c4560cd83 136
uci1 0:334c4560cd83 137 /* Transmit Status Vector 0 Register */
uci1 0:334c4560cd83 138 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
uci1 0:334c4560cd83 139 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
uci1 0:334c4560cd83 140 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
uci1 0:334c4560cd83 141 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
uci1 0:334c4560cd83 142 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
uci1 0:334c4560cd83 143 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
uci1 0:334c4560cd83 144 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
uci1 0:334c4560cd83 145 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
uci1 0:334c4560cd83 146 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
uci1 0:334c4560cd83 147 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
uci1 0:334c4560cd83 148 #define TSV0_GIANT 0x00000400 /* Giant Frame */
uci1 0:334c4560cd83 149 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
uci1 0:334c4560cd83 150 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
uci1 0:334c4560cd83 151 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
uci1 0:334c4560cd83 152 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
uci1 0:334c4560cd83 153 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
uci1 0:334c4560cd83 154 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
uci1 0:334c4560cd83 155
uci1 0:334c4560cd83 156 /* Transmit Status Vector 1 Register */
uci1 0:334c4560cd83 157 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
uci1 0:334c4560cd83 158 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
uci1 0:334c4560cd83 159
uci1 0:334c4560cd83 160 /* Receive Status Vector Register */
uci1 0:334c4560cd83 161 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
uci1 0:334c4560cd83 162 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
uci1 0:334c4560cd83 163 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
uci1 0:334c4560cd83 164 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
uci1 0:334c4560cd83 165 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
uci1 0:334c4560cd83 166 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
uci1 0:334c4560cd83 167 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
uci1 0:334c4560cd83 168 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
uci1 0:334c4560cd83 169 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
uci1 0:334c4560cd83 170 #define RSV_MCAST 0x01000000 /* Multicast Frame */
uci1 0:334c4560cd83 171 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
uci1 0:334c4560cd83 172 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
uci1 0:334c4560cd83 173 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
uci1 0:334c4560cd83 174 #define RSV_PAUSE 0x10000000 /* Pause Frame */
uci1 0:334c4560cd83 175 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
uci1 0:334c4560cd83 176 #define RSV_VLAN 0x40000000 /* VLAN Frame */
uci1 0:334c4560cd83 177
uci1 0:334c4560cd83 178 /* Flow Control Counter Register */
uci1 0:334c4560cd83 179 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
uci1 0:334c4560cd83 180 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
uci1 0:334c4560cd83 181
uci1 0:334c4560cd83 182 /* Flow Control Status Register */
uci1 0:334c4560cd83 183 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
uci1 0:334c4560cd83 184
uci1 0:334c4560cd83 185 /* Receive Filter Control Register */
uci1 0:334c4560cd83 186 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
uci1 0:334c4560cd83 187 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
uci1 0:334c4560cd83 188 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
uci1 0:334c4560cd83 189 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
uci1 0:334c4560cd83 190 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
uci1 0:334c4560cd83 191 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
uci1 0:334c4560cd83 192 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
uci1 0:334c4560cd83 193 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
uci1 0:334c4560cd83 194
uci1 0:334c4560cd83 195 /* Receive Filter WoL Status/Clear Registers */
uci1 0:334c4560cd83 196 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
uci1 0:334c4560cd83 197 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
uci1 0:334c4560cd83 198 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
uci1 0:334c4560cd83 199 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
uci1 0:334c4560cd83 200 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
uci1 0:334c4560cd83 201 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
uci1 0:334c4560cd83 202 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
uci1 0:334c4560cd83 203 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
uci1 0:334c4560cd83 204
uci1 0:334c4560cd83 205 /* Interrupt Status/Enable/Clear/Set Registers */
uci1 0:334c4560cd83 206 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
uci1 0:334c4560cd83 207 #define INT_RX_ERR 0x00000002 /* Receive Error */
uci1 0:334c4560cd83 208 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
uci1 0:334c4560cd83 209 #define INT_RX_DONE 0x00000008 /* Receive Done */
uci1 0:334c4560cd83 210 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
uci1 0:334c4560cd83 211 #define INT_TX_ERR 0x00000020 /* Transmit Error */
uci1 0:334c4560cd83 212 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
uci1 0:334c4560cd83 213 #define INT_TX_DONE 0x00000080 /* Transmit Done */
uci1 0:334c4560cd83 214 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
uci1 0:334c4560cd83 215 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
uci1 0:334c4560cd83 216
uci1 0:334c4560cd83 217 /* Power Down Register */
uci1 0:334c4560cd83 218 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
uci1 0:334c4560cd83 219
uci1 0:334c4560cd83 220 /* RX Descriptor Control Word */
uci1 0:334c4560cd83 221 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
uci1 0:334c4560cd83 222 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
uci1 0:334c4560cd83 223
uci1 0:334c4560cd83 224 /* RX Status Hash CRC Word */
uci1 0:334c4560cd83 225 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
uci1 0:334c4560cd83 226 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
uci1 0:334c4560cd83 227
uci1 0:334c4560cd83 228 /* RX Status Information Word */
uci1 0:334c4560cd83 229 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
uci1 0:334c4560cd83 230 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
uci1 0:334c4560cd83 231 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
uci1 0:334c4560cd83 232 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
uci1 0:334c4560cd83 233 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
uci1 0:334c4560cd83 234 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
uci1 0:334c4560cd83 235 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
uci1 0:334c4560cd83 236 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
uci1 0:334c4560cd83 237 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
uci1 0:334c4560cd83 238 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
uci1 0:334c4560cd83 239 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
uci1 0:334c4560cd83 240 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
uci1 0:334c4560cd83 241 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
uci1 0:334c4560cd83 242 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
uci1 0:334c4560cd83 243 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
uci1 0:334c4560cd83 244
uci1 0:334c4560cd83 245 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
uci1 0:334c4560cd83 246 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
uci1 0:334c4560cd83 247
uci1 0:334c4560cd83 248 /* TX Descriptor Control Word */
uci1 0:334c4560cd83 249 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
uci1 0:334c4560cd83 250 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
uci1 0:334c4560cd83 251 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
uci1 0:334c4560cd83 252 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
uci1 0:334c4560cd83 253 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
uci1 0:334c4560cd83 254 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
uci1 0:334c4560cd83 255 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
uci1 0:334c4560cd83 256
uci1 0:334c4560cd83 257 /* TX Status Information Word */
uci1 0:334c4560cd83 258 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
uci1 0:334c4560cd83 259 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
uci1 0:334c4560cd83 260 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
uci1 0:334c4560cd83 261 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
uci1 0:334c4560cd83 262 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
uci1 0:334c4560cd83 263 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
uci1 0:334c4560cd83 264 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
uci1 0:334c4560cd83 265 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
uci1 0:334c4560cd83 266
uci1 0:334c4560cd83 267 /* DP83848C PHY Registers */
uci1 0:334c4560cd83 268 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
uci1 0:334c4560cd83 269 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
uci1 0:334c4560cd83 270 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
uci1 0:334c4560cd83 271 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
uci1 0:334c4560cd83 272 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
uci1 0:334c4560cd83 273 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
uci1 0:334c4560cd83 274 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
uci1 0:334c4560cd83 275 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
uci1 0:334c4560cd83 276
uci1 0:334c4560cd83 277 /* PHY Extended Registers */
uci1 0:334c4560cd83 278 #define PHY_REG_STS 0x10 /* Status Register */
uci1 0:334c4560cd83 279 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
uci1 0:334c4560cd83 280 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
uci1 0:334c4560cd83 281 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
uci1 0:334c4560cd83 282 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
uci1 0:334c4560cd83 283 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
uci1 0:334c4560cd83 284 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
uci1 0:334c4560cd83 285 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
uci1 0:334c4560cd83 286 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
uci1 0:334c4560cd83 287 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
uci1 0:334c4560cd83 288 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
uci1 0:334c4560cd83 289 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
uci1 0:334c4560cd83 290
uci1 0:334c4560cd83 291 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
uci1 0:334c4560cd83 292 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
uci1 0:334c4560cd83 293 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
uci1 0:334c4560cd83 294 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
uci1 0:334c4560cd83 295 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
uci1 0:334c4560cd83 296
uci1 0:334c4560cd83 297 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
uci1 0:334c4560cd83 298 #define DP83848C_ID 0x20005C90 /* PHY Identifier */
uci1 0:334c4560cd83 299 #endif