hideharu tsunemoto / Mbed 2 deprecated SerialADC_Sample

ADC_3CH_DAC_CDC

Dependencies:   MODDMA mbed

Fork of Serial_interrupts by jim hamblen

main.cpp@2:6fb0d2e32144, 2016-05-18 (annotated)

Committer:
tsunemoto
Date:
Wed May 18 09:18:44 2016 +0000
Revision:
2:6fb0d2e32144
Parent:
0:023c5cda6102 
SerialADC_Sample Ver0100

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tsunemoto 2:6fb0d2e32144 1 /////////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 2 // Dose Meter Test Program //
tsunemoto 2:6fb0d2e32144 3 // for ADC Measurement Timer(0.1mSec)Interrupt & DAC Controll //
tsunemoto 2:6fb0d2e32144 4 // Since 2013.08.01 H.Tsunemoto //
tsunemoto 2:6fb0d2e32144 5 // Sample Program Import (1) Serial_interrupt //
tsunemoto 2:6fb0d2e32144 6 // (2) Timer_Interrupt(100mSec) Sample //
tsunemoto 2:6fb0d2e32144 7 // (3) Internal_ADC_with_interrupt //
tsunemoto 2:6fb0d2e32144 8 /////////////////////////////////////////////////////////////////////
4180_1 0:023c5cda6102 9
4180_1 0:023c5cda6102 10 #include "mbed.h"
tsunemoto 2:6fb0d2e32144 11 #include "stdio.h"
tsunemoto 2:6fb0d2e32144 12 #include "math.h"
tsunemoto 2:6fb0d2e32144 13 #include "LPC17xx.h"
4180_1 0:023c5cda6102 14 // Serial TX & RX interrupt loopback test using formatted IO - sprintf and sscanf
4180_1 0:023c5cda6102 15 // Connect TX to RX (p9 to p10)
4180_1 0:023c5cda6102 16 // or can also use USB and type back in the number printed out in a terminal window
4180_1 0:023c5cda6102 17 // Sends out ASCII numbers in a loop and reads them back
tsunemoto 2:6fb0d2e32144 18 // Since 2013.08.
4180_1 0:023c5cda6102 19 // If not the same number LED4 goes on
tsunemoto 2:6fb0d2e32144 20 // LED1 and LED2 ADC
4180_1 0:023c5cda6102 21 // LED3 changing indicate main loop running
4180_1 0:023c5cda6102 22
tsunemoto 2:6fb0d2e32144 23 //-------------------------------------//
tsunemoto 2:6fb0d2e32144 24 // --- MBED I/O Asign declaration --- //
tsunemoto 2:6fb0d2e32144 25 //-------------------------------------//
tsunemoto 2:6fb0d2e32144 26 // Serial Port Asign P9:TX P10:RX
tsunemoto 2:6fb0d2e32144 27 Serial device(USBTX, USBRX); // tx, rx //Serial device(p9, p10); // tx, rx
tsunemoto 2:6fb0d2e32144 28 // ADC Port Asign P15: ad_ch1 P16 = ad_ch2
tsunemoto 2:6fb0d2e32144 29 AnalogIn ad_ch1(p15); // AD CH1
tsunemoto 2:6fb0d2e32144 30 AnalogIn ad_ch2(p16); //AD CH2
tsunemoto 2:6fb0d2e32144 31 AnalogIn ad_ch3(p17); //AD CH2
tsunemoto 2:6fb0d2e32144 32 AnalogOut dac_output(p18);
tsunemoto 2:6fb0d2e32144 33
tsunemoto 2:6fb0d2e32144 34 // Can also use USB and type back in the number printed out in a terminal window
tsunemoto 2:6fb0d2e32144 35 // Serial monitor_device(USBTX, USBRX);
tsunemoto 2:6fb0d2e32144 36 DigitalOut led1(LED1); // ADC Active
tsunemoto 2:6fb0d2e32144 37 DigitalOut led2(LED2); // ADC Input Cycle
tsunemoto 2:6fb0d2e32144 38 DigitalOut led3(LED3); // Main Loop Cycle
tsunemoto 2:6fb0d2e32144 39 DigitalOut led4(LED4); // DAC Active
tsunemoto 2:6fb0d2e32144 40 BusOut leds(LED4,LED3,LED2,LED1); //LED
tsunemoto 2:6fb0d2e32144 41
tsunemoto 2:6fb0d2e32144 42 //---------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 43 // <<< ADC Sample Parameter & Function declaration >>> //
tsunemoto 2:6fb0d2e32144 44 //---------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 45 //---- ADC Interrupt Timer -----//
tsunemoto 2:6fb0d2e32144 46 int main_loop_count = 0;
tsunemoto 2:6fb0d2e32144 47 Ticker ADC_Timer;
tsunemoto 2:6fb0d2e32144 48 Timer t;
tsunemoto 2:6fb0d2e32144 49 int ADC_Count1=0;
tsunemoto 2:6fb0d2e32144 50 int ADC_Count1Block=0;
tsunemoto 2:6fb0d2e32144 51 #define ADC_BUFF_SIZE 5000
tsunemoto 2:6fb0d2e32144 52 #define ADC_CH1 0
tsunemoto 2:6fb0d2e32144 53 #define ADC_CH2 1
tsunemoto 2:6fb0d2e32144 54 #define ADC_CH3 2
tsunemoto 2:6fb0d2e32144 55 volatile unsigned short Adc_inp_temp[3];
tsunemoto 2:6fb0d2e32144 56 volatile unsigned short Adc_buff[3][ADC_BUFF_SIZE];
tsunemoto 2:6fb0d2e32144 57 volatile int adc_buff_inp = 0;
tsunemoto 2:6fb0d2e32144 58 volatile int adc_buff_out = 0;
tsunemoto 2:6fb0d2e32144 59 // Ative Mode Status Controll
tsunemoto 2:6fb0d2e32144 60 #define ActiveMode_ADC_Sample_Stop 0
tsunemoto 2:6fb0d2e32144 61 #define ActiveMode_ADC_Sample_Ready 1 //
tsunemoto 2:6fb0d2e32144 62 #define ActiveMode_ADC_Sample_Busy 2 //
tsunemoto 2:6fb0d2e32144 63 int i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Stop;
tsunemoto 2:6fb0d2e32144 64 // Trigger Mode Status Control
tsunemoto 2:6fb0d2e32144 65 #define ADC_TRIGGER_READY 0 //Trigger Mode Ready :Trigger Wait & No Data Send
tsunemoto 2:6fb0d2e32144 66 #define ADC_TRIGGER_BUSY 1 //Trigger Mode Busy :Trigger Detected & Sample Data Send
tsunemoto 2:6fb0d2e32144 67 #define ADC_TRIGGER_END 2 //Trigger Mode END :Sample End & Data Send Done Wait
tsunemoto 2:6fb0d2e32144 68 int i_adc_Trigger_Sample_Status = ADC_TRIGGER_READY;
tsunemoto 2:6fb0d2e32144 69 volatile unsigned short adc_CH1_now;
tsunemoto 2:6fb0d2e32144 70 volatile int i_adc_trigger_end_count;
tsunemoto 2:6fb0d2e32144 71 int i_adc_Waveform_count=0;
tsunemoto 2:6fb0d2e32144 72 volatile int i_adc_Sample_Total_Count = 0;
tsunemoto 2:6fb0d2e32144 73 volatile int i_adc_Sample_Total_Time = 0;
tsunemoto 2:6fb0d2e32144 74 #define ADC_TRIGGER_START_ENABLE 1
tsunemoto 2:6fb0d2e32144 75 #define ADC_TRIGGER__START_READY 0
tsunemoto 2:6fb0d2e32144 76 bool b_Trigger_Start_sendFlag = ADC_TRIGGER__START_READY;
tsunemoto 2:6fb0d2e32144 77 #define ADC_PULSE_END_ENABLE 1
tsunemoto 2:6fb0d2e32144 78 #define ADC_PULSE_END_READY 0
tsunemoto 2:6fb0d2e32144 79 bool b_Trigger_EndFlag = ADC_PULSE_END_READY;
tsunemoto 2:6fb0d2e32144 80 #define ADC_SAMPLE_AVE_MAX 4
tsunemoto 2:6fb0d2e32144 81 volatile int adc_Sample_Ave_Count = 4;
tsunemoto 2:6fb0d2e32144 82 typedef struct st_adc_ave{
tsunemoto 2:6fb0d2e32144 83 volatile unsigned short sample_Add;
tsunemoto 2:6fb0d2e32144 84 volatile unsigned short sample_Max;
tsunemoto 2:6fb0d2e32144 85 volatile unsigned short sample_Min;
tsunemoto 2:6fb0d2e32144 86 }ST_ADC_AVE;
tsunemoto 2:6fb0d2e32144 87 volatile ST_ADC_AVE st_adc_sample_ave[3];
tsunemoto 2:6fb0d2e32144 88 const ST_ADC_AVE const_ADC_AVE_Default=
tsunemoto 2:6fb0d2e32144 89 {
tsunemoto 2:6fb0d2e32144 90 0 //unsigned short sample_Add;
tsunemoto 2:6fb0d2e32144 91 ,0 //unsigned short sample_Max;
tsunemoto 2:6fb0d2e32144 92 ,0xfff //unsigned short sample_Min;
tsunemoto 2:6fb0d2e32144 93 };
tsunemoto 2:6fb0d2e32144 94 #define ADC_SAMPLE_RATE_MIN 5
tsunemoto 2:6fb0d2e32144 95 #define ADC_SAMPLE_RATE_MAX 20000
tsunemoto 2:6fb0d2e32144 96 #define ADC_SAMPLE_RATE_MIN_f 0.005f
tsunemoto 2:6fb0d2e32144 97 #define ADC_SAMPLE_RATE_MAX_f 20.000f
tsunemoto 2:6fb0d2e32144 98 #define ADC_PRE_TRIG_MIN 0
tsunemoto 2:6fb0d2e32144 99 #define ADC_PRE_TRIG_MAX 100
tsunemoto 2:6fb0d2e32144 100 #define ADC_PULSE_END_MIN_f 0.1f //0.1Sec
tsunemoto 2:6fb0d2e32144 101 #define ADC_PULSE_END_MAX_f 5.0f //5.0Sec
tsunemoto 2:6fb0d2e32144 102
tsunemoto 2:6fb0d2e32144 103 //-------- ADC Measure Mode Parameter declaration --------//
tsunemoto 2:6fb0d2e32144 104 typedef struct st_adc_param{
tsunemoto 2:6fb0d2e32144 105 int i_sample_interval; // DAC Output Pattern
tsunemoto 2:6fb0d2e32144 106 float f_trigger_level;
tsunemoto 2:6fb0d2e32144 107 unsigned short us_trigger_level; // (3.3f/1023) * f_trigger_level (Image)
tsunemoto 2:6fb0d2e32144 108 int i_pre_trig_point;
tsunemoto 2:6fb0d2e32144 109 int i_pulse_end_time;
tsunemoto 2:6fb0d2e32144 110 }ST_ADC_PARAM;
tsunemoto 2:6fb0d2e32144 111
tsunemoto 2:6fb0d2e32144 112 ST_ADC_PARAM st_adc_mode_param;
tsunemoto 2:6fb0d2e32144 113
tsunemoto 2:6fb0d2e32144 114 //-------- ADC Measure Mode Parameter Default Set --------//
tsunemoto 2:6fb0d2e32144 115 const ST_ADC_PARAM const_ADC_Param_Default=
tsunemoto 2:6fb0d2e32144 116 {
tsunemoto 2:6fb0d2e32144 117 1000 //i_sample_int=1000 microS
tsunemoto 2:6fb0d2e32144 118 ,0.01f //f_trigger_level = 0.01V
tsunemoto 2:6fb0d2e32144 119 ,0x00c // (3.3f/4095) * f_trigger_level
tsunemoto 2:6fb0d2e32144 120 ,5 // i_pre_trig_point = 5 point before
tsunemoto 2:6fb0d2e32144 121 ,12000 //i_pulse_end_time = 1.2 Sec
tsunemoto 2:6fb0d2e32144 122 };
tsunemoto 2:6fb0d2e32144 123 //int adc_sample_interval = 1000; // ADC Sample Rate 5 - 20000(20.0mSec)
tsunemoto 2:6fb0d2e32144 124 void ADC_ave_Init();
tsunemoto 2:6fb0d2e32144 125 void Start_ADC();
tsunemoto 2:6fb0d2e32144 126 int ADC_Inp3CH();
tsunemoto 2:6fb0d2e32144 127 void ADC_Interrupt();
tsunemoto 2:6fb0d2e32144 128 void ADC_Stop();
tsunemoto 2:6fb0d2e32144 129 void ad_sample_send();
tsunemoto 2:6fb0d2e32144 130 void adc_param_init();
tsunemoto 2:6fb0d2e32144 131
4180_1 0:023c5cda6102 132
4180_1 0:023c5cda6102 133
4180_1 0:023c5cda6102 134
tsunemoto 2:6fb0d2e32144 135 //--------------------------------//
tsunemoto 2:6fb0d2e32144 136 // --- Serial Communication --- //
tsunemoto 2:6fb0d2e32144 137 //--------------------------------//
4180_1 0:023c5cda6102 138 void Tx_interrupt();
4180_1 0:023c5cda6102 139 void Rx_interrupt();
4180_1 0:023c5cda6102 140 void send_line();
tsunemoto 2:6fb0d2e32144 141 int read_line(); // Return Rec CHAR Count 2013.08.08 Tsunemoto Append
tsunemoto 2:6fb0d2e32144 142
tsunemoto 2:6fb0d2e32144 143
tsunemoto 2:6fb0d2e32144 144
tsunemoto 2:6fb0d2e32144 145 //---------- H.Tsunemoto Scince 2013.08.08 ---------//
tsunemoto 2:6fb0d2e32144 146 //-----------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 147 //--------- Timer Innterrupt For DAC Control ---------------//
tsunemoto 2:6fb0d2e32144 148 //-----------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 149 int timer_count=0;
tsunemoto 2:6fb0d2e32144 150 int timer_1Sec=0;
tsunemoto 2:6fb0d2e32144 151
tsunemoto 2:6fb0d2e32144 152 //void TIMER0_IRQHandler(void);
tsunemoto 2:6fb0d2e32144 153 void timer0_init(void);
tsunemoto 2:6fb0d2e32144 154 //--------- New Append Function ---------//
4180_1 0:023c5cda6102 155
tsunemoto 2:6fb0d2e32144 156 void dac1_param_init();
tsunemoto 2:6fb0d2e32144 157 void Ser_Command_Input();
tsunemoto 2:6fb0d2e32144 158 //////////////////////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 159 //------------ Command Check & Set Function ---------------------------------//
tsunemoto 2:6fb0d2e32144 160 // ADC No.1 "ARx.xx" ADC Sample Rate
tsunemoto 2:6fb0d2e32144 161 bool com_Check_AR(int i_RecCharCount);
tsunemoto 2:6fb0d2e32144 162 // ADC No.2 "ALx.xxx" ADC Trigger Limit Level 0.00-3.3V
tsunemoto 2:6fb0d2e32144 163 bool com_Check_AL(int i_RecCharCount);
tsunemoto 2:6fb0d2e32144 164 // ADC No.3 "APxx" ADC PreTrigger Send Data Point
tsunemoto 2:6fb0d2e32144 165 bool com_Check_AP(int i_RecCharCount);
tsunemoto 2:6fb0d2e32144 166 // ADC No.4 "AIx.xxx" ADC Pulse End Point Check Time
tsunemoto 2:6fb0d2e32144 167 bool com_Check_AI(int i_RecCharCount);
tsunemoto 2:6fb0d2e32144 168 // ADC No.5
tsunemoto 2:6fb0d2e32144 169 void com_ADC_Table_Param_Send();
tsunemoto 2:6fb0d2e32144 170 // DAC_No.1 "DMn:xx (SINGLE/PULSE/TRIANGLE) //
tsunemoto 2:6fb0d2e32144 171 bool com_Check_DM(int i_RecCharCount);
tsunemoto 2:6fb0d2e32144 172 // DAC_No.2 "DHn:xx.x Pulse High Level Volt Set (0.000 - 3.300[V]) //
tsunemoto 2:6fb0d2e32144 173 bool com_Check_DH(int i_RecCharCount);
tsunemoto 2:6fb0d2e32144 174 // DAC_No.3 "DLn:xx.x Pulse Low Level Volt Set (0.000 - 3.300[V]) //
tsunemoto 2:6fb0d2e32144 175 bool com_Check_DL(int i_RecCharCount);
tsunemoto 2:6fb0d2e32144 176 // DAC_No.4 "DPn:xx.x Pulse Mode Pulse Width Set (0.1 - 2000.0[mSec]) //
tsunemoto 2:6fb0d2e32144 177 bool com_Check_DP(int i_RecCharCount);
tsunemoto 2:6fb0d2e32144 178 // DAC_No.5 "DIn:xx.x Pulse Mode Pulse Interval Set //
tsunemoto 2:6fb0d2e32144 179 bool com_Check_DI(int i_RecCharCount);
tsunemoto 2:6fb0d2e32144 180 // DAC_No.6 "DWn:xx.x Wave Form Total Width Set //
tsunemoto 2:6fb0d2e32144 181 bool com_Check_DW(int i_RecCharCount);
tsunemoto 2:6fb0d2e32144 182 // DAC_No.7 "D?" DAC Parameter RepryWave Form Total Width Set //
tsunemoto 2:6fb0d2e32144 183 void com_Table_Param_Send();
tsunemoto 2:6fb0d2e32144 184 //----------------------------------------------------------------//
4180_1 0:023c5cda6102 185
4180_1 0:023c5cda6102 186 // Circular buffers for serial TX and RX data - used by interrupt routines
tsunemoto 2:6fb0d2e32144 187 const int ser_buffer_size = 255;
4180_1 0:023c5cda6102 188 // might need to increase buffer size for high baud rates
tsunemoto 2:6fb0d2e32144 189 char tx_buffer[ser_buffer_size];
tsunemoto 2:6fb0d2e32144 190 char rx_buffer[ser_buffer_size];
4180_1 0:023c5cda6102 191 // Circular buffer pointers
4180_1 0:023c5cda6102 192 // volatile makes read-modify-write atomic
4180_1 0:023c5cda6102 193 volatile int tx_in=0;
4180_1 0:023c5cda6102 194 volatile int tx_out=0;
4180_1 0:023c5cda6102 195 volatile int rx_in=0;
4180_1 0:023c5cda6102 196 volatile int rx_out=0;
4180_1 0:023c5cda6102 197 // Line buffers for sprintf and sscanf
4180_1 0:023c5cda6102 198 char tx_line[80];
4180_1 0:023c5cda6102 199 char rx_line[80];
tsunemoto 2:6fb0d2e32144 200 //--- 2013.08.08 Tsunemoto ------//
tsunemoto 2:6fb0d2e32144 201 //-- rx Data Cr Rec Counter
tsunemoto 2:6fb0d2e32144 202 volatile int rx_cr_Rec = 0;
tsunemoto 2:6fb0d2e32144 203 //--------------------------------//
4180_1 0:023c5cda6102 204
tsunemoto 2:6fb0d2e32144 205
tsunemoto 2:6fb0d2e32144 206 // ---------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 207 // 2013.08.07 Tsunemoto
tsunemoto 2:6fb0d2e32144 208 // Measurement Grobal Parameter
tsunemoto 2:6fb0d2e32144 209 // ---- DAC 1 Digit Unit ----------//
tsunemoto 2:6fb0d2e32144 210 // 10Bits = 1023 : VREFP = 3.3V
tsunemoto 2:6fb0d2e32144 211 //#define DAC_1_DIGIT_VOLT (0.0032258f)
tsunemoto 2:6fb0d2e32144 212 #define DAC1_FULL_VOLT_f 3.30f
tsunemoto 2:6fb0d2e32144 213 #define DAC1_PULSE_INT_MAX_f 3000.0f
tsunemoto 2:6fb0d2e32144 214 #define DAC1_PULSE_TOTAL_TIME_MAX_f 500.0000f
tsunemoto 2:6fb0d2e32144 215 //unsigned short us_Dac1_volt;
tsunemoto 2:6fb0d2e32144 216 float f_Dac1_volt;
tsunemoto 2:6fb0d2e32144 217 float f_Dac_Triangle_inc;
tsunemoto 2:6fb0d2e32144 218 //--- DAC OutPut Pattern ---//
tsunemoto 2:6fb0d2e32144 219 // --- DAC Active Pattern ---//
tsunemoto 2:6fb0d2e32144 220 #define DAC1_PATERN_0 0
tsunemoto 2:6fb0d2e32144 221 #define DAC1_PATERN_1 1
tsunemoto 2:6fb0d2e32144 222 #define DAC1_PATERN_2 2
tsunemoto 2:6fb0d2e32144 223 int i_dac1_pattern_now = DAC1_PATERN_0; // Active Pattern 0,1,2
tsunemoto 2:6fb0d2e32144 224 //--- DAC Active MODE ---//
tsunemoto 2:6fb0d2e32144 225 #define DAC1_ACT_0_READY 0 // NO Active
tsunemoto 2:6fb0d2e32144 226 #define DAC1_ACT_1_START 1 // START Command Input
tsunemoto 2:6fb0d2e32144 227 #define DAC1_ACT_2_OUTPUT_BUSY 2// PULSE PATTERN ACTIVE
tsunemoto 2:6fb0d2e32144 228 int i_dac1_active_status;
tsunemoto 2:6fb0d2e32144 229 int i_dac1_active_count; //OUTPUT_WAVE TOTAL COUNT 0-500S:0-500000(0x7A120)
tsunemoto 2:6fb0d2e32144 230 int i_dac1_pulse_count; //OUTPUT PULSE COUNT
tsunemoto 2:6fb0d2e32144 231 #define DAC1_PULSE_ACT_INTERVAL 0
tsunemoto 2:6fb0d2e32144 232 #define DAC1_PULSE_ACT_UP 1
tsunemoto 2:6fb0d2e32144 233 #define DAC1_PULSE_ACT_DOWN 2
tsunemoto 2:6fb0d2e32144 234 int i_dac1_pulse_act = DAC1_PULSE_ACT_INTERVAL;
tsunemoto 2:6fb0d2e32144 235 //--- DAC1 Pattern Parameter
tsunemoto 2:6fb0d2e32144 236 #define DAC1_PATTERN_1_SINGLE_PULSE 0
tsunemoto 2:6fb0d2e32144 237 #define DAC1_PATTERN_2_PULSE 1
tsunemoto 2:6fb0d2e32144 238 #define DAC1_PATTERN_3_TRIANGLE 2
tsunemoto 2:6fb0d2e32144 239 #define DAC1_PATTERN_MAX 3
tsunemoto 2:6fb0d2e32144 240 typedef struct st_dac_param{
tsunemoto 2:6fb0d2e32144 241 int i_pattern; // DAC Output Pattern
tsunemoto 2:6fb0d2e32144 242 float f_pulse_high;
tsunemoto 2:6fb0d2e32144 243 float f_pulse_low;
tsunemoto 2:6fb0d2e32144 244
tsunemoto 2:6fb0d2e32144 245 int i_pulse_width;
tsunemoto 2:6fb0d2e32144 246 int i_pulse_interval;
tsunemoto 2:6fb0d2e32144 247 int i_Total_time;
tsunemoto 2:6fb0d2e32144 248 }ST_DAC_PARAM;
tsunemoto 2:6fb0d2e32144 249
tsunemoto 2:6fb0d2e32144 250 ST_DAC_PARAM st_dac1_param[DAC1_PATTERN_MAX];
tsunemoto 2:6fb0d2e32144 251 const ST_DAC_PARAM const_DAC1_Default[DAC1_PATTERN_MAX]=
tsunemoto 2:6fb0d2e32144 252 {
tsunemoto 2:6fb0d2e32144 253 // Pattern 1
tsunemoto 2:6fb0d2e32144 254 DAC1_PATTERN_1_SINGLE_PULSE
tsunemoto 2:6fb0d2e32144 255 ,(3.0f/3.300f)
tsunemoto 2:6fb0d2e32144 256 ,0.0f
tsunemoto 2:6fb0d2e32144 257 ,100 // Not Use
tsunemoto 2:6fb0d2e32144 258 ,3000 //Not Use
tsunemoto 2:6fb0d2e32144 259 ,1000 // 10mSe
tsunemoto 2:6fb0d2e32144 260 // ,50000 // 5Sec
tsunemoto 2:6fb0d2e32144 261 // Pattern 2
tsunemoto 2:6fb0d2e32144 262 ,DAC1_PATTERN_1_SINGLE_PULSE
tsunemoto 2:6fb0d2e32144 263 ,(0.3f/3.300f)
tsunemoto 2:6fb0d2e32144 264 ,0.0f
tsunemoto 2:6fb0d2e32144 265 ,100 // Not Use
tsunemoto 2:6fb0d2e32144 266 ,3000 //Not Use
tsunemoto 2:6fb0d2e32144 267 ,50000 // 5Sec
tsunemoto 2:6fb0d2e32144 268 // Pattern 3
tsunemoto 2:6fb0d2e32144 269 ,DAC1_PATTERN_2_PULSE
tsunemoto 2:6fb0d2e32144 270 ,(3.0f/3.300f)
tsunemoto 2:6fb0d2e32144 271 ,0.0f
tsunemoto 2:6fb0d2e32144 272 ,100 // 10mSec
tsunemoto 2:6fb0d2e32144 273 ,3000 //300mSec
tsunemoto 2:6fb0d2e32144 274 ,50000 // 5Sec
tsunemoto 2:6fb0d2e32144 275
tsunemoto 2:6fb0d2e32144 276
tsunemoto 2:6fb0d2e32144 277 };
tsunemoto 2:6fb0d2e32144 278
tsunemoto 2:6fb0d2e32144 279 /////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 280 // <<<< Main Function >>>> //
tsunemoto 2:6fb0d2e32144 281 /////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 282 // ---------------------------------------------------------------//
4180_1 0:023c5cda6102 283 // main test program
4180_1 0:023c5cda6102 284 int main() {
tsunemoto 2:6fb0d2e32144 285 // Serial Speed Set
tsunemoto 2:6fb0d2e32144 286 device.baud(115200);
4180_1 0:023c5cda6102 287
4180_1 0:023c5cda6102 288 // Setup a serial interrupt function to receive data
4180_1 0:023c5cda6102 289 device.attach(&Rx_interrupt, Serial::RxIrq);
4180_1 0:023c5cda6102 290 // Setup a serial interrupt function to transmit data
4180_1 0:023c5cda6102 291 device.attach(&Tx_interrupt, Serial::TxIrq);
4180_1 0:023c5cda6102 292
4180_1 0:023c5cda6102 293 // Formatted IO test using send and receive serial interrupts
tsunemoto 2:6fb0d2e32144 294 // Timer 0 Interrupt Initial Set //
tsunemoto 2:6fb0d2e32144 295 timer0_init();
tsunemoto 2:6fb0d2e32144 296 timer_count = 0;
tsunemoto 2:6fb0d2e32144 297
tsunemoto 2:6fb0d2e32144 298 //--- ADC Measurement Control Parameter Initial Set ---//
tsunemoto 2:6fb0d2e32144 299 adc_param_init();
tsunemoto 2:6fb0d2e32144 300 //--- DAC Control Parameter Init --- //
tsunemoto 2:6fb0d2e32144 301 dac1_param_init();
tsunemoto 2:6fb0d2e32144 302 // -- Main Loop -- //
4180_1 0:023c5cda6102 303 while (1) {
tsunemoto 2:6fb0d2e32144 304 if (i_adc_ActiveMode_status != ActiveMode_ADC_Sample_Stop){
tsunemoto 2:6fb0d2e32144 305
tsunemoto 2:6fb0d2e32144 306 ad_sample_send();// --- ADC Sample & Serial Data Out --- //
tsunemoto 2:6fb0d2e32144 307 }
tsunemoto 2:6fb0d2e32144 308 if(rx_cr_Rec != 0){
tsunemoto 2:6fb0d2e32144 309 Ser_Command_Input();
tsunemoto 2:6fb0d2e32144 310 }
tsunemoto 2:6fb0d2e32144 311 main_loop_count++;
tsunemoto 2:6fb0d2e32144 312 if(main_loop_count>=100000){
tsunemoto 2:6fb0d2e32144 313 led3 = (led3+1) & 1;
tsunemoto 2:6fb0d2e32144 314 main_loop_count = 0;
tsunemoto 2:6fb0d2e32144 315 }
tsunemoto 2:6fb0d2e32144 316 /////////////////////////////////
tsunemoto 2:6fb0d2e32144 317 }
tsunemoto 2:6fb0d2e32144 318 }
tsunemoto 2:6fb0d2e32144 319
tsunemoto 2:6fb0d2e32144 320 //////////////////////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 321 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 322 //------- A/D Input & Data Send(Serial) -------//
tsunemoto 2:6fb0d2e32144 323 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 324 // int ADC_Count1=0; //
tsunemoto 2:6fb0d2e32144 325 // int ADC_Count1Block=0; //
tsunemoto 2:6fb0d2e32144 326 // #define ADC_BUFF_SIZE 5000 //
tsunemoto 2:6fb0d2e32144 327 // #define ADC_CH1 0 //
tsunemoto 2:6fb0d2e32144 328 // #define ADC_CH2 1 //
tsunemoto 2:6fb0d2e32144 329 // #define ADC_CH3 2 //
tsunemoto 2:6fb0d2e32144 330 // unsigned short Adc_buff[3][ADC_BUFF_SIZE] //
tsunemoto 2:6fb0d2e32144 331 // int adc_buff_inp = 0; //
tsunemoto 2:6fb0d2e32144 332 // int adc_buff_out = 0; //
tsunemoto 2:6fb0d2e32144 333 //
tsunemoto 2:6fb0d2e32144 334 //#define ActiveMode_ADC_Sample_Stop 0
tsunemoto 2:6fb0d2e32144 335 //#define ActiveMode_ADC_Sample_Ready 1 //
tsunemoto 2:6fb0d2e32144 336 //#define ActiveMode_ADC_Sample_Busy 2 //
tsunemoto 2:6fb0d2e32144 337 //int i_adc_ActiveMode_status ;
tsunemoto 2:6fb0d2e32144 338 // //
tsunemoto 2:6fb0d2e32144 339 //#define ADC_TRIGGER_START_ENABLE
tsunemoto 2:6fb0d2e32144 340 //#define ADC_TRIGGER__START_READY
tsunemoto 2:6fb0d2e32144 341 //bool b_Trigger_Start_sendFlag = ADC_TRIGGER__START_READY;
tsunemoto 2:6fb0d2e32144 342 //#define ADC_PULSE_END_ENABLE
tsunemoto 2:6fb0d2e32144 343 //#define ADC_PULSE_END_READY
tsunemoto 2:6fb0d2e32144 344 //bool b_Trigger_EndFlag = ADC_PULSE_END_READY;
tsunemoto 2:6fb0d2e32144 345 //int i_adc_Waveform_count=0
tsunemoto 2:6fb0d2e32144 346 //int i_adc_Sample_Total_Count = 0;
tsunemoto 2:6fb0d2e32144 347 //int i_adc_Sample_Total_Time = 0;
tsunemoto 2:6fb0d2e32144 348 //
tsunemoto 2:6fb0d2e32144 349 //////////////////////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 350 void ad_sample_send(){
tsunemoto 2:6fb0d2e32144 351 float f_num;
tsunemoto 2:6fb0d2e32144 352 // A/D CH1(P15) / CH2(P16) / CH3(P17) => HEX SHORT
tsunemoto 2:6fb0d2e32144 353 if(i_adc_ActiveMode_status == ActiveMode_ADC_Sample_Ready){
tsunemoto 2:6fb0d2e32144 354 if (b_Trigger_Start_sendFlag == ADC_TRIGGER_START_ENABLE){
tsunemoto 2:6fb0d2e32144 355 sprintf(tx_line,"PULSE_START:%05d\r\n",i_adc_Waveform_count);
4180_1 0:023c5cda6102 356 send_line();
tsunemoto 2:6fb0d2e32144 357 b_Trigger_Start_sendFlag = ADC_TRIGGER__START_READY;
tsunemoto 2:6fb0d2e32144 358 }
tsunemoto 2:6fb0d2e32144 359 if(i_adc_Trigger_Sample_Status != ADC_TRIGGER_READY){
tsunemoto 2:6fb0d2e32144 360 if(adc_buff_inp != adc_buff_out){
tsunemoto 2:6fb0d2e32144 361 sprintf(tx_line,"%03x%03x%03x\r\n"
tsunemoto 2:6fb0d2e32144 362 ,Adc_buff[ADC_CH1][adc_buff_out]
tsunemoto 2:6fb0d2e32144 363 ,Adc_buff[ADC_CH2][adc_buff_out]
tsunemoto 2:6fb0d2e32144 364 ,Adc_buff[ADC_CH3][adc_buff_out]
tsunemoto 2:6fb0d2e32144 365 );
tsunemoto 2:6fb0d2e32144 366 adc_buff_out = ((adc_buff_out + 1) % ADC_BUFF_SIZE);
tsunemoto 2:6fb0d2e32144 367 send_line();
tsunemoto 2:6fb0d2e32144 368 }
tsunemoto 2:6fb0d2e32144 369 }
tsunemoto 2:6fb0d2e32144 370 if((adc_buff_inp == adc_buff_out)&& (b_Trigger_EndFlag == ADC_PULSE_END_ENABLE)){
tsunemoto 2:6fb0d2e32144 371 f_num = ((float)i_adc_Sample_Total_Time + 0.5f)/10.0f;
tsunemoto 2:6fb0d2e32144 372 sprintf(tx_line,"PULSE_END:%05d:SAMPLE:%05d,TIME:%06.1f[mSec]\r\n",i_adc_Waveform_count,i_adc_Sample_Total_Count,f_num);
tsunemoto 2:6fb0d2e32144 373 send_line();
tsunemoto 2:6fb0d2e32144 374 b_Trigger_EndFlag = ADC_PULSE_END_READY;
tsunemoto 2:6fb0d2e32144 375 }
tsunemoto 2:6fb0d2e32144 376
tsunemoto 2:6fb0d2e32144 377 }
tsunemoto 2:6fb0d2e32144 378 else if(adc_buff_inp != adc_buff_out){
tsunemoto 2:6fb0d2e32144 379 sprintf(tx_line,"%03x%03x%03x\r\n"
tsunemoto 2:6fb0d2e32144 380 ,Adc_buff[ADC_CH1][adc_buff_out]
tsunemoto 2:6fb0d2e32144 381 ,Adc_buff[ADC_CH2][adc_buff_out]
tsunemoto 2:6fb0d2e32144 382 ,Adc_buff[ADC_CH3][adc_buff_out]
tsunemoto 2:6fb0d2e32144 383 );
tsunemoto 2:6fb0d2e32144 384 adc_buff_out = ((adc_buff_out + 1) % ADC_BUFF_SIZE);
4180_1 0:023c5cda6102 385 send_line();
tsunemoto 2:6fb0d2e32144 386 }
tsunemoto 2:6fb0d2e32144 387 }
tsunemoto 2:6fb0d2e32144 388
tsunemoto 2:6fb0d2e32144 389 void Start_ADC() {
tsunemoto 2:6fb0d2e32144 390 ADC_Count1Block=0;
tsunemoto 2:6fb0d2e32144 391 ADC_Count1=0;
tsunemoto 2:6fb0d2e32144 392
tsunemoto 2:6fb0d2e32144 393 t.reset();
tsunemoto 2:6fb0d2e32144 394 // t.start();
tsunemoto 2:6fb0d2e32144 395 //memset(Samples, 0, AANTAL_SAMPLES);
tsunemoto 2:6fb0d2e32144 396 //ADC_Timer.attach_us(&ADC_Interrupt, 200);
tsunemoto 2:6fb0d2e32144 397 // 2013_0827 Tsunemoto for 1/4Sample Average
tsunemoto 2:6fb0d2e32144 398 ADC_Timer.attach_us(&ADC_Interrupt, (st_adc_mode_param.i_sample_interval>>2));
tsunemoto 2:6fb0d2e32144 399 ADC_ave_Init();
tsunemoto 2:6fb0d2e32144 400 //ADC_Timer.attach_us(&ADC_Interrupt, st_adc_mode_param.i_sample_interval);
tsunemoto 2:6fb0d2e32144 401 i_adc_Waveform_count = 0;
tsunemoto 2:6fb0d2e32144 402 t.start();
tsunemoto 2:6fb0d2e32144 403 led1 = 1;
tsunemoto 2:6fb0d2e32144 404
tsunemoto 2:6fb0d2e32144 405 // wait(0.0005);
tsunemoto 2:6fb0d2e32144 406 }
tsunemoto 2:6fb0d2e32144 407 //*********************************************
tsunemoto 2:6fb0d2e32144 408 //** ADC 1/4 Sample Parameter init **
tsunemoto 2:6fb0d2e32144 409 //** 2013.08.27 Tsunemoto **
tsunemoto 2:6fb0d2e32144 410 //typedef struct st_adc_ave{
tsunemoto 2:6fb0d2e32144 411 // unsigned short sample_Add;
tsunemoto 2:6fb0d2e32144 412 // unsigned short sample_Max;
tsunemoto 2:6fb0d2e32144 413 // unsigned short sample_Min;
tsunemoto 2:6fb0d2e32144 414 //}ST_ADC_AVE;
tsunemoto 2:6fb0d2e32144 415 //ST_ADC_AVE st_adc_sample_ave[3];
tsunemoto 2:6fb0d2e32144 416 //const ST_ADC_AVE const_ADC_AVE_Default=
tsunemoto 2:6fb0d2e32144 417 //#define ADC_SAMPLE_AVE_MAX 4
tsunemoto 2:6fb0d2e32144 418 //int adc_Sample_Ave_Count = 4;
tsunemoto 2:6fb0d2e32144 419 //***************************************
tsunemoto 2:6fb0d2e32144 420 void ADC_ave_Init()
tsunemoto 2:6fb0d2e32144 421 {
tsunemoto 2:6fb0d2e32144 422 int i;
tsunemoto 2:6fb0d2e32144 423 for (i=ADC_CH1;i<=ADC_CH3;i++){
tsunemoto 2:6fb0d2e32144 424 st_adc_sample_ave[i].sample_Add = const_ADC_AVE_Default.sample_Add;
tsunemoto 2:6fb0d2e32144 425 st_adc_sample_ave[i].sample_Max = const_ADC_AVE_Default.sample_Max;
tsunemoto 2:6fb0d2e32144 426 st_adc_sample_ave[i].sample_Min = const_ADC_AVE_Default.sample_Min;
tsunemoto 2:6fb0d2e32144 427 }
tsunemoto 2:6fb0d2e32144 428 adc_Sample_Ave_Count = ADC_SAMPLE_AVE_MAX;
tsunemoto 2:6fb0d2e32144 429 }
tsunemoto 2:6fb0d2e32144 430 //****************************************************
tsunemoto 2:6fb0d2e32144 431 //** ADC Sample Input for 1/4 Ave & MAX/Min Cansel **
tsunemoto 2:6fb0d2e32144 432 //Adc_inp_temp
tsunemoto 2:6fb0d2e32144 433 // return ;0= No Buffer inc
tsunemoto 2:6fb0d2e32144 434 // 1= Buffer Inp & Count INC
tsunemoto 2:6fb0d2e32144 435 //****************************************************
tsunemoto 2:6fb0d2e32144 436 int ADC_Inp3CH()
tsunemoto 2:6fb0d2e32144 437 {
tsunemoto 2:6fb0d2e32144 438 int i_ret=0;
tsunemoto 2:6fb0d2e32144 439 Adc_inp_temp[ADC_CH1] = ((ad_ch1.read_u16()>>4)&0xFFF);
tsunemoto 2:6fb0d2e32144 440 Adc_inp_temp[ADC_CH2] = ((ad_ch2.read_u16()>>4)&0xFFF);
tsunemoto 2:6fb0d2e32144 441 Adc_inp_temp[ADC_CH3] = ((ad_ch3.read_u16()>>4)&0xFFF);
tsunemoto 2:6fb0d2e32144 442 adc_Sample_Ave_Count--;
tsunemoto 2:6fb0d2e32144 443 // CH1 Ave
tsunemoto 2:6fb0d2e32144 444 st_adc_sample_ave[ADC_CH1].sample_Add = st_adc_sample_ave[ADC_CH1].sample_Add+Adc_inp_temp[ADC_CH1];
tsunemoto 2:6fb0d2e32144 445 if(Adc_inp_temp[ADC_CH1] >= st_adc_sample_ave[ADC_CH1].sample_Max){
tsunemoto 2:6fb0d2e32144 446 st_adc_sample_ave[ADC_CH1].sample_Max = Adc_inp_temp[ADC_CH1];
tsunemoto 2:6fb0d2e32144 447 }
tsunemoto 2:6fb0d2e32144 448 if(Adc_inp_temp[ADC_CH1] < st_adc_sample_ave[ADC_CH1].sample_Min){
tsunemoto 2:6fb0d2e32144 449 st_adc_sample_ave[ADC_CH1].sample_Min = Adc_inp_temp[ADC_CH1];
tsunemoto 2:6fb0d2e32144 450 }
tsunemoto 2:6fb0d2e32144 451 // CH2 Ave
tsunemoto 2:6fb0d2e32144 452 st_adc_sample_ave[ADC_CH2].sample_Add = st_adc_sample_ave[ADC_CH2].sample_Add+Adc_inp_temp[ADC_CH2];
tsunemoto 2:6fb0d2e32144 453 if(Adc_inp_temp[ADC_CH2] >= st_adc_sample_ave[ADC_CH2].sample_Max){
tsunemoto 2:6fb0d2e32144 454 st_adc_sample_ave[ADC_CH2].sample_Max = Adc_inp_temp[ADC_CH2];
tsunemoto 2:6fb0d2e32144 455 }
tsunemoto 2:6fb0d2e32144 456 if(Adc_inp_temp[ADC_CH2] < st_adc_sample_ave[ADC_CH2].sample_Min){
tsunemoto 2:6fb0d2e32144 457 st_adc_sample_ave[ADC_CH2].sample_Min = Adc_inp_temp[ADC_CH2];
tsunemoto 2:6fb0d2e32144 458 }
tsunemoto 2:6fb0d2e32144 459 // CH3 Ave
tsunemoto 2:6fb0d2e32144 460 st_adc_sample_ave[ADC_CH3].sample_Add = st_adc_sample_ave[ADC_CH3].sample_Add+Adc_inp_temp[ADC_CH3];
tsunemoto 2:6fb0d2e32144 461 if(Adc_inp_temp[ADC_CH3] >= st_adc_sample_ave[ADC_CH3].sample_Max){
tsunemoto 2:6fb0d2e32144 462 st_adc_sample_ave[ADC_CH3].sample_Max = Adc_inp_temp[ADC_CH3];
tsunemoto 2:6fb0d2e32144 463 }
tsunemoto 2:6fb0d2e32144 464 if(Adc_inp_temp[ADC_CH3] < st_adc_sample_ave[ADC_CH3].sample_Min){
tsunemoto 2:6fb0d2e32144 465 st_adc_sample_ave[ADC_CH3].sample_Min = Adc_inp_temp[ADC_CH3];
tsunemoto 2:6fb0d2e32144 466 }
tsunemoto 2:6fb0d2e32144 467
tsunemoto 2:6fb0d2e32144 468 if(adc_Sample_Ave_Count == 0){
tsunemoto 2:6fb0d2e32144 469 // Adc_buff[ADC_CH1][adc_buff_inp] = adc_CH1_now = ((ad_ch1.read_u16()>>4)&0xFFF);
tsunemoto 2:6fb0d2e32144 470 // Adc_buff[ADC_CH2][adc_buff_inp]= ((ad_ch2.read_u16()>>4)&0xFFF);
tsunemoto 2:6fb0d2e32144 471 // Adc_buff[ADC_CH3][adc_buff_inp]= ((ad_ch3.read_u16()>>4)&0xFFF);
tsunemoto 2:6fb0d2e32144 472 Adc_buff[ADC_CH1][adc_buff_inp] = adc_CH1_now =
tsunemoto 2:6fb0d2e32144 473 (((st_adc_sample_ave[ADC_CH1].sample_Add - st_adc_sample_ave[ADC_CH1].sample_Max - st_adc_sample_ave[ADC_CH1].sample_Min)/2) &0xFFF);
tsunemoto 2:6fb0d2e32144 474 Adc_buff[ADC_CH2][adc_buff_inp] =
tsunemoto 2:6fb0d2e32144 475 (((st_adc_sample_ave[ADC_CH2].sample_Add - st_adc_sample_ave[ADC_CH2].sample_Max - st_adc_sample_ave[ADC_CH2].sample_Min)/2)&0xFFF);
tsunemoto 2:6fb0d2e32144 476 Adc_buff[ADC_CH3][adc_buff_inp] =
tsunemoto 2:6fb0d2e32144 477 (((st_adc_sample_ave[ADC_CH3].sample_Add - st_adc_sample_ave[ADC_CH3].sample_Max - st_adc_sample_ave[ADC_CH3].sample_Min)/2)&0xFFF);
tsunemoto 2:6fb0d2e32144 478 adc_buff_inp = ((adc_buff_inp + 1) % ADC_BUFF_SIZE);
tsunemoto 2:6fb0d2e32144 479 ADC_ave_Init();
tsunemoto 2:6fb0d2e32144 480 i_ret = 1;
tsunemoto 2:6fb0d2e32144 481 }
tsunemoto 2:6fb0d2e32144 482 return(i_ret);
tsunemoto 2:6fb0d2e32144 483 }
tsunemoto 2:6fb0d2e32144 484 void ADC_Interrupt() {
tsunemoto 2:6fb0d2e32144 485 int i_inp_ret;
tsunemoto 2:6fb0d2e32144 486 led2 = 1;
tsunemoto 2:6fb0d2e32144 487 if(adc_buff_inp == (ADC_BUFF_SIZE-1)){
tsunemoto 2:6fb0d2e32144 488 ADC_Count1Block++;
tsunemoto 2:6fb0d2e32144 489 }
tsunemoto 2:6fb0d2e32144 490 ADC_Count1++;
tsunemoto 2:6fb0d2e32144 491 //#define ActiveMode_ADC_Sample_Busy 2 //
tsunemoto 2:6fb0d2e32144 492 //int i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Stop;
tsunemoto 2:6fb0d2e32144 493 if(i_adc_ActiveMode_status == ActiveMode_ADC_Sample_Busy){
tsunemoto 2:6fb0d2e32144 494 if (((adc_buff_inp + 1) % ADC_BUFF_SIZE) == adc_buff_out) {
tsunemoto 2:6fb0d2e32144 495 ADC_Stop();
tsunemoto 2:6fb0d2e32144 496 }
tsunemoto 2:6fb0d2e32144 497 else{
tsunemoto 2:6fb0d2e32144 498 i_inp_ret = ADC_Inp3CH();
tsunemoto 2:6fb0d2e32144 499 }
tsunemoto 2:6fb0d2e32144 500 }
tsunemoto 2:6fb0d2e32144 501 else if (i_adc_ActiveMode_status == ActiveMode_ADC_Sample_Ready){
tsunemoto 2:6fb0d2e32144 502 //#define ADC_TRIGGER_READY 0 //Trigger Mode Ready :Trigger Wait & No Data Send
tsunemoto 2:6fb0d2e32144 503 //#define ADC_TRIGGER_BUSY 1 //Trigger Mode Busy :Trigger Detected & Sample Data Send
tsunemoto 2:6fb0d2e32144 504 //#define ADC_TRIGGER_END 2 //Trigger Mode END :Sample End & Data Send Done Wait
tsunemoto 2:6fb0d2e32144 505 //int i_adc_Trigger_Sample_Status = ADC_TRIGGER_READY;
tsunemoto 2:6fb0d2e32144 506 //int i_adc_Sample_Total_Count = 0;
tsunemoto 2:6fb0d2e32144 507 //#define ADC_TRIGGER_START_ENABLE
tsunemoto 2:6fb0d2e32144 508 //#define ADC_TRIGGER__START_READY
tsunemoto 2:6fb0d2e32144 509 //bool b_Trigger_Start_sendFlag = ADC_TRIGGER__START_READY;
tsunemoto 2:6fb0d2e32144 510 //#define ADC_PULSE_END_ENABLE
tsunemoto 2:6fb0d2e32144 511 //#define ADC_PULSE_END_READY
tsunemoto 2:6fb0d2e32144 512 //bool b_Trigger_EndFlag = ADC_PULSE_END_READY;
tsunemoto 2:6fb0d2e32144 513 //
tsunemoto 2:6fb0d2e32144 514 switch(i_adc_Trigger_Sample_Status){
tsunemoto 2:6fb0d2e32144 515 case ADC_TRIGGER_READY:
tsunemoto 2:6fb0d2e32144 516 adc_buff_out = adc_buff_inp;
tsunemoto 2:6fb0d2e32144 517 if(ADC_Inp3CH()== 1) {
tsunemoto 2:6fb0d2e32144 518 if(adc_CH1_now >= st_adc_mode_param.us_trigger_level){ // Trigger Point Detect
tsunemoto 2:6fb0d2e32144 519 adc_buff_out = (adc_buff_inp + (ADC_BUFF_SIZE - st_adc_mode_param.i_pre_trig_point - 1)) % ADC_BUFF_SIZE;
tsunemoto 2:6fb0d2e32144 520 i_adc_Trigger_Sample_Status = ADC_TRIGGER_BUSY;
tsunemoto 2:6fb0d2e32144 521 i_adc_Sample_Total_Count = st_adc_mode_param.i_pre_trig_point;
tsunemoto 2:6fb0d2e32144 522 i_adc_Sample_Total_Time = 0;
tsunemoto 2:6fb0d2e32144 523 b_Trigger_Start_sendFlag = ADC_TRIGGER_START_ENABLE;
tsunemoto 2:6fb0d2e32144 524 i_adc_Waveform_count++;
tsunemoto 2:6fb0d2e32144 525 i_adc_trigger_end_count = st_adc_mode_param.i_pulse_end_time;
tsunemoto 2:6fb0d2e32144 526 }
tsunemoto 2:6fb0d2e32144 527 }
tsunemoto 2:6fb0d2e32144 528 break;
tsunemoto 2:6fb0d2e32144 529 case ADC_TRIGGER_BUSY:
tsunemoto 2:6fb0d2e32144 530 if (((adc_buff_inp + 1) % ADC_BUFF_SIZE) == adc_buff_out) {
tsunemoto 2:6fb0d2e32144 531 i_adc_Trigger_Sample_Status = ADC_TRIGGER_END;
tsunemoto 2:6fb0d2e32144 532 b_Trigger_EndFlag = ADC_PULSE_END_ENABLE;
tsunemoto 2:6fb0d2e32144 533 }
tsunemoto 2:6fb0d2e32144 534 else{
tsunemoto 2:6fb0d2e32144 535 if(ADC_Inp3CH()== 1){
tsunemoto 2:6fb0d2e32144 536 i_adc_Sample_Total_Count++;
tsunemoto 2:6fb0d2e32144 537 if(adc_CH1_now >= st_adc_mode_param.us_trigger_level){
tsunemoto 2:6fb0d2e32144 538 i_adc_trigger_end_count = st_adc_mode_param.i_pulse_end_time; // Pulse End Detect Reset
tsunemoto 2:6fb0d2e32144 539 }
tsunemoto 2:6fb0d2e32144 540 else{
tsunemoto 2:6fb0d2e32144 541 if(i_adc_trigger_end_count == 0){
tsunemoto 2:6fb0d2e32144 542 i_adc_Trigger_Sample_Status = ADC_TRIGGER_END;
tsunemoto 2:6fb0d2e32144 543 b_Trigger_EndFlag = ADC_PULSE_END_ENABLE;
tsunemoto 2:6fb0d2e32144 544 }
tsunemoto 2:6fb0d2e32144 545 }
tsunemoto 2:6fb0d2e32144 546 }
tsunemoto 2:6fb0d2e32144 547 }
tsunemoto 2:6fb0d2e32144 548 break;
tsunemoto 2:6fb0d2e32144 549 case ADC_TRIGGER_END: // Data Sample Wait for Data Translate Complete
tsunemoto 2:6fb0d2e32144 550 if(adc_buff_out == adc_buff_inp){
tsunemoto 2:6fb0d2e32144 551 i_adc_Trigger_Sample_Status = ADC_TRIGGER_READY;
tsunemoto 2:6fb0d2e32144 552 }
tsunemoto 2:6fb0d2e32144 553 break;
tsunemoto 2:6fb0d2e32144 554 }
tsunemoto 2:6fb0d2e32144 555 }
tsunemoto 2:6fb0d2e32144 556 led2 = 0;
tsunemoto 2:6fb0d2e32144 557
tsunemoto 2:6fb0d2e32144 558 }
tsunemoto 2:6fb0d2e32144 559
tsunemoto 2:6fb0d2e32144 560 void ADC_Stop() {
tsunemoto 2:6fb0d2e32144 561 ADC_Timer.detach();
tsunemoto 2:6fb0d2e32144 562 t.stop();
tsunemoto 2:6fb0d2e32144 563 led1=0;
tsunemoto 2:6fb0d2e32144 564 }
tsunemoto 2:6fb0d2e32144 565 //-------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 566 // ADC Measurement Parameter Initial Set //
tsunemoto 2:6fb0d2e32144 567 // 2013.08.14 H.Tsunemoto
tsunemoto 2:6fb0d2e32144 568 //typedef struct st_adc_param{
tsunemoto 2:6fb0d2e32144 569 // int i_sample_interval; // DAC Output Pattern
tsunemoto 2:6fb0d2e32144 570 // float f_trigger_level;
tsunemoto 2:6fb0d2e32144 571 // unsigned short us_trigger_level; // (3.3f/1023) * f_trigger_level (Image)
tsunemoto 2:6fb0d2e32144 572 // int i_pre_trig_point;
tsunemoto 2:6fb0d2e32144 573 // int i_pulse_end_time;
tsunemoto 2:6fb0d2e32144 574 //}ST_ADC_PARAM;
tsunemoto 2:6fb0d2e32144 575 //
tsunemoto 2:6fb0d2e32144 576 //ST_ADC_PARAM st_adc_mode_param;
tsunemoto 2:6fb0d2e32144 577 //-------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 578 void adc_param_init()
tsunemoto 2:6fb0d2e32144 579 {
tsunemoto 2:6fb0d2e32144 580 st_adc_mode_param.i_sample_interval = const_ADC_Param_Default.i_sample_interval;
tsunemoto 2:6fb0d2e32144 581 st_adc_mode_param.f_trigger_level = const_ADC_Param_Default.f_trigger_level;
tsunemoto 2:6fb0d2e32144 582 st_adc_mode_param.us_trigger_level = const_ADC_Param_Default.us_trigger_level;
tsunemoto 2:6fb0d2e32144 583 st_adc_mode_param.i_pre_trig_point = const_ADC_Param_Default.i_pre_trig_point;
tsunemoto 2:6fb0d2e32144 584 st_adc_mode_param.i_pulse_end_time = const_ADC_Param_Default.i_pulse_end_time;
tsunemoto 2:6fb0d2e32144 585 }
tsunemoto 2:6fb0d2e32144 586 ///////////////////////////////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 587 ///////////////////////////////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 588
tsunemoto 2:6fb0d2e32144 589
tsunemoto 2:6fb0d2e32144 590 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 591 //----- DAC Control Function
tsunemoto 2:6fb0d2e32144 592 // H.Tsunemoto Scince 2013.08.09
tsunemoto 2:6fb0d2e32144 593 // int i_pattern; // DAC Output Pattern
tsunemoto 2:6fb0d2e32144 594 // float f_pulse_high;
tsunemoto 2:6fb0d2e32144 595 // float f_pulse_low;
tsunemoto 2:6fb0d2e32144 596 // int i_pulse_width;
tsunemoto 2:6fb0d2e32144 597 // int i_pulse_interval;
tsunemoto 2:6fb0d2e32144 598 // int i_Total_time;
tsunemoto 2:6fb0d2e32144 599 //
tsunemoto 2:6fb0d2e32144 600 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 601 //-------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 602 // DAC Parameter Initial Set //
tsunemoto 2:6fb0d2e32144 603 // 2013.08.09 H.Tsunemoto
tsunemoto 2:6fb0d2e32144 604 //-------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 605 void dac1_param_init()
tsunemoto 2:6fb0d2e32144 606 {
tsunemoto 2:6fb0d2e32144 607 int i;
tsunemoto 2:6fb0d2e32144 608 for (i=0;i<DAC1_PATTERN_MAX;i++){
tsunemoto 2:6fb0d2e32144 609 st_dac1_param[i].i_pattern = const_DAC1_Default[i].i_pattern;
tsunemoto 2:6fb0d2e32144 610 st_dac1_param[i].f_pulse_high = const_DAC1_Default[i].f_pulse_high;
tsunemoto 2:6fb0d2e32144 611 st_dac1_param[i].f_pulse_low = const_DAC1_Default[i].f_pulse_low;
tsunemoto 2:6fb0d2e32144 612 st_dac1_param[i].i_pulse_width = const_DAC1_Default[i].i_pulse_width;
tsunemoto 2:6fb0d2e32144 613 st_dac1_param[i].i_pulse_interval = const_DAC1_Default[i].i_pulse_interval;
tsunemoto 2:6fb0d2e32144 614 st_dac1_param[i].i_Total_time = const_DAC1_Default[i].i_Total_time;
tsunemoto 2:6fb0d2e32144 615 }
tsunemoto 2:6fb0d2e32144 616
tsunemoto 2:6fb0d2e32144 617 }
tsunemoto 2:6fb0d2e32144 618 //------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 619 // Timer Interrupt Routine
tsunemoto 2:6fb0d2e32144 620 //i_dac1_active_status
tsunemoto 2:6fb0d2e32144 621 //#define DAC1_ACT_0_READY 0 // NO Active
tsunemoto 2:6fb0d2e32144 622 //#define DAC1_ACT_1_START 1 // START Command Input
tsunemoto 2:6fb0d2e32144 623 //#define DAC1_ACT_2_OUTPUT_BUSY // PULSE PATTERN ACTIVE
tsunemoto 2:6fb0d2e32144 624 //
tsunemoto 2:6fb0d2e32144 625 //int i_dac1_pulse_act = DAC1_PULSE_ACT_INTERVAL;
tsunemoto 2:6fb0d2e32144 626 //#define DAC1_PULSE_ACT_INTERVAL 0
tsunemoto 2:6fb0d2e32144 627 //#define DAC1_PULSE_ACT_UP 1
tsunemoto 2:6fb0d2e32144 628 //#define DAC1_PULSE_ACT_DOWN 2
tsunemoto 2:6fb0d2e32144 629 //Global Parameter
tsunemoto 2:6fb0d2e32144 630 // int i_dac1_active_count; //OUTPUT_WAVE TOTAL COUNT 0-500S:0-500000(0x7A120)
tsunemoto 2:6fb0d2e32144 631 // int i_dac1_pulse_count; //OUTPUT PULSE COUNT
tsunemoto 2:6fb0d2e32144 632 //#define DAC1_PATTERN_1_SINGLE_PULSE 0
tsunemoto 2:6fb0d2e32144 633 //#define DAC1_PATTERN_2_PULSE 1
tsunemoto 2:6fb0d2e32144 634 //#define DAC1_PATTERN_3_TRIANGLE 2
tsunemoto 2:6fb0d2e32144 635 //
tsunemoto 2:6fb0d2e32144 636 //------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 637 extern "C" void TIMER0_IRQHandler (void)
tsunemoto 2:6fb0d2e32144 638 {
tsunemoto 2:6fb0d2e32144 639 if((LPC_TIM0->IR & 0x01) == 0x01) // if MR0 interrupt, proceed
tsunemoto 2:6fb0d2e32144 640 {
tsunemoto 2:6fb0d2e32144 641 LPC_TIM0->IR |= 1 << 0; // Clear MR0 interrupt flag
tsunemoto 2:6fb0d2e32144 642 timer_count++; //increment timer_count
tsunemoto 2:6fb0d2e32144 643 if(timer_count >= 10000){
tsunemoto 2:6fb0d2e32144 644 timer_count = 0;
tsunemoto 2:6fb0d2e32144 645 timer_1Sec++;
tsunemoto 2:6fb0d2e32144 646 }
tsunemoto 2:6fb0d2e32144 647 // --- for ADC Sample End Check ----//
tsunemoto 2:6fb0d2e32144 648 if( i_adc_trigger_end_count > 0){
tsunemoto 2:6fb0d2e32144 649 i_adc_trigger_end_count--;
tsunemoto 2:6fb0d2e32144 650 i_adc_Sample_Total_Time++;
tsunemoto 2:6fb0d2e32144 651 }
tsunemoto 2:6fb0d2e32144 652
tsunemoto 2:6fb0d2e32144 653 //-- DAC Control --//
tsunemoto 2:6fb0d2e32144 654 switch(i_dac1_active_status){
tsunemoto 2:6fb0d2e32144 655 case DAC1_ACT_0_READY:
tsunemoto 2:6fb0d2e32144 656 led4=0;
tsunemoto 2:6fb0d2e32144 657 f_Dac1_volt = st_dac1_param[i_dac1_pattern_now].f_pulse_low;
tsunemoto 2:6fb0d2e32144 658 dac_output.write(f_Dac1_volt); //DAC Output
tsunemoto 2:6fb0d2e32144 659 // sprintf(tx_line,"DAC:%1d,%3x\r\n",i_dac1_pattern_now,st_dac1_param[i_dac1_pattern_now].i_pulse_low);
tsunemoto 2:6fb0d2e32144 660 // send_line();
tsunemoto 2:6fb0d2e32144 661 break;
tsunemoto 2:6fb0d2e32144 662 case DAC1_ACT_1_START:
tsunemoto 2:6fb0d2e32144 663 led4=1;
tsunemoto 2:6fb0d2e32144 664 i_dac1_active_count = st_dac1_param[i_dac1_pattern_now].i_Total_time;
tsunemoto 2:6fb0d2e32144 665 i_dac1_pulse_act = DAC1_PULSE_ACT_UP;
tsunemoto 2:6fb0d2e32144 666 if(st_dac1_param[i_dac1_pattern_now].i_pattern == DAC1_PATTERN_3_TRIANGLE){
tsunemoto 2:6fb0d2e32144 667 i_dac1_pulse_count = st_dac1_param[i_dac1_pattern_now].i_pulse_width/2;
tsunemoto 2:6fb0d2e32144 668 f_Dac_Triangle_inc = ( st_dac1_param[i_dac1_pattern_now].f_pulse_high
tsunemoto 2:6fb0d2e32144 669 - st_dac1_param[i_dac1_pattern_now].f_pulse_low)
tsunemoto 2:6fb0d2e32144 670 / (float)(st_dac1_param[i_dac1_pattern_now].i_pulse_width/2);
tsunemoto 2:6fb0d2e32144 671
tsunemoto 2:6fb0d2e32144 672 }
tsunemoto 2:6fb0d2e32144 673 else{
tsunemoto 2:6fb0d2e32144 674 i_dac1_pulse_count = st_dac1_param[i_dac1_pattern_now].i_pulse_width;
tsunemoto 2:6fb0d2e32144 675 f_Dac1_volt = st_dac1_param[i_dac1_pattern_now].f_pulse_high;
tsunemoto 2:6fb0d2e32144 676 dac_output.write(f_Dac1_volt); //DAC Output
tsunemoto 2:6fb0d2e32144 677 // for Debug
tsunemoto 2:6fb0d2e32144 678 //sprintf(tx_line,"DAC:%1d,%f\r\n",i_dac1_pattern_now,f_Dac1_volt*DAC1_FULL_VOLT_f);
tsunemoto 2:6fb0d2e32144 679 //send_line();
tsunemoto 2:6fb0d2e32144 680 }
tsunemoto 2:6fb0d2e32144 681 i_dac1_active_status ++; // = DAC1_ACT_2_OUTPUT_BUSY;
tsunemoto 2:6fb0d2e32144 682 break;
tsunemoto 2:6fb0d2e32144 683 case DAC1_ACT_2_OUTPUT_BUSY:
tsunemoto 2:6fb0d2e32144 684 // Wave Total COunt Check & if 0 Wave OutPut Done
tsunemoto 2:6fb0d2e32144 685 i_dac1_active_count--;
tsunemoto 2:6fb0d2e32144 686 if(i_dac1_active_count <= 0){
tsunemoto 2:6fb0d2e32144 687 i_dac1_active_status = DAC1_ACT_0_READY;
tsunemoto 2:6fb0d2e32144 688 f_Dac1_volt = st_dac1_param[i_dac1_pattern_now].f_pulse_low;
tsunemoto 2:6fb0d2e32144 689 dac_output.write(f_Dac1_volt); //DAC Output
tsunemoto 2:6fb0d2e32144 690 // for Debug
tsunemoto 2:6fb0d2e32144 691 //sprintf(tx_line,"DAC:%1d,%f\r\n",i_dac1_pattern_now,f_Dac1_volt*DAC1_FULL_VOLT_f);
tsunemoto 2:6fb0d2e32144 692 //send_line();
tsunemoto 2:6fb0d2e32144 693 break;
tsunemoto 2:6fb0d2e32144 694 }
tsunemoto 2:6fb0d2e32144 695 // Pulse Count Down
tsunemoto 2:6fb0d2e32144 696 if(st_dac1_param[i_dac1_pattern_now].i_pattern == DAC1_PATTERN_3_TRIANGLE){
tsunemoto 2:6fb0d2e32144 697 if(i_dac1_pulse_act == DAC1_PULSE_ACT_UP){
tsunemoto 2:6fb0d2e32144 698 f_Dac1_volt += f_Dac_Triangle_inc;
tsunemoto 2:6fb0d2e32144 699 dac_output.write(f_Dac1_volt); //DAC Output
tsunemoto 2:6fb0d2e32144 700 }
tsunemoto 2:6fb0d2e32144 701 else if (i_dac1_pulse_act == DAC1_PULSE_ACT_DOWN){
tsunemoto 2:6fb0d2e32144 702 f_Dac1_volt -= f_Dac_Triangle_inc;
tsunemoto 2:6fb0d2e32144 703 dac_output.write(f_Dac1_volt); //DAC Output
tsunemoto 2:6fb0d2e32144 704 }
tsunemoto 2:6fb0d2e32144 705 }
tsunemoto 2:6fb0d2e32144 706 i_dac1_pulse_count--;
tsunemoto 2:6fb0d2e32144 707 if( i_dac1_pulse_count <= 0){
tsunemoto 2:6fb0d2e32144 708 switch(st_dac1_param[i_dac1_pattern_now].i_pattern){
tsunemoto 2:6fb0d2e32144 709 case DAC1_PATTERN_1_SINGLE_PULSE:
tsunemoto 2:6fb0d2e32144 710 break;
tsunemoto 2:6fb0d2e32144 711 case DAC1_PATTERN_2_PULSE:
tsunemoto 2:6fb0d2e32144 712 if(i_dac1_pulse_act == DAC1_PULSE_ACT_UP){
tsunemoto 2:6fb0d2e32144 713 f_Dac1_volt = st_dac1_param[i_dac1_pattern_now].f_pulse_low;
tsunemoto 2:6fb0d2e32144 714 dac_output.write(f_Dac1_volt); //DAC Output
tsunemoto 2:6fb0d2e32144 715 i_dac1_pulse_act = DAC1_PULSE_ACT_INTERVAL;
tsunemoto 2:6fb0d2e32144 716 i_dac1_pulse_count = st_dac1_param[i_dac1_pattern_now].i_pulse_interval;
tsunemoto 2:6fb0d2e32144 717 }
tsunemoto 2:6fb0d2e32144 718 else {
tsunemoto 2:6fb0d2e32144 719 f_Dac1_volt = st_dac1_param[i_dac1_pattern_now].f_pulse_high;
tsunemoto 2:6fb0d2e32144 720 dac_output.write(f_Dac1_volt); //DAC Output
tsunemoto 2:6fb0d2e32144 721 i_dac1_pulse_act = DAC1_PULSE_ACT_UP;
tsunemoto 2:6fb0d2e32144 722 i_dac1_pulse_count = st_dac1_param[i_dac1_pattern_now].i_pulse_width;
tsunemoto 2:6fb0d2e32144 723 }
tsunemoto 2:6fb0d2e32144 724 break;
tsunemoto 2:6fb0d2e32144 725 case DAC1_PATTERN_3_TRIANGLE:
tsunemoto 2:6fb0d2e32144 726 if(i_dac1_pulse_act == DAC1_PULSE_ACT_UP){
tsunemoto 2:6fb0d2e32144 727 f_Dac1_volt = st_dac1_param[i_dac1_pattern_now].f_pulse_high;
tsunemoto 2:6fb0d2e32144 728 dac_output.write(f_Dac1_volt); //DAC Output
tsunemoto 2:6fb0d2e32144 729 i_dac1_pulse_act = DAC1_PULSE_ACT_DOWN;
tsunemoto 2:6fb0d2e32144 730 i_dac1_pulse_count = st_dac1_param[i_dac1_pattern_now].i_pulse_width/2;
tsunemoto 2:6fb0d2e32144 731 }
tsunemoto 2:6fb0d2e32144 732 else if(i_dac1_pulse_act == DAC1_PULSE_ACT_DOWN){
tsunemoto 2:6fb0d2e32144 733 f_Dac1_volt = st_dac1_param[i_dac1_pattern_now].f_pulse_low;
tsunemoto 2:6fb0d2e32144 734 dac_output.write(f_Dac1_volt); //DAC Output
tsunemoto 2:6fb0d2e32144 735 i_dac1_pulse_act = DAC1_PULSE_ACT_INTERVAL;
tsunemoto 2:6fb0d2e32144 736 i_dac1_pulse_count = st_dac1_param[i_dac1_pattern_now].i_pulse_interval;
tsunemoto 2:6fb0d2e32144 737 }
tsunemoto 2:6fb0d2e32144 738 else {
tsunemoto 2:6fb0d2e32144 739 f_Dac1_volt = st_dac1_param[i_dac1_pattern_now].f_pulse_low;
tsunemoto 2:6fb0d2e32144 740 dac_output.write(f_Dac1_volt); //DAC Output
tsunemoto 2:6fb0d2e32144 741 i_dac1_pulse_act = DAC1_PULSE_ACT_UP;
tsunemoto 2:6fb0d2e32144 742 i_dac1_pulse_count = st_dac1_param[i_dac1_pattern_now].i_pulse_width/2;
tsunemoto 2:6fb0d2e32144 743 }
tsunemoto 2:6fb0d2e32144 744 break;
tsunemoto 2:6fb0d2e32144 745 default:
tsunemoto 2:6fb0d2e32144 746 i_dac1_active_status = DAC1_ACT_0_READY;
tsunemoto 2:6fb0d2e32144 747 break;
tsunemoto 2:6fb0d2e32144 748 }
tsunemoto 2:6fb0d2e32144 749 }
tsunemoto 2:6fb0d2e32144 750 break;
tsunemoto 2:6fb0d2e32144 751 default:
tsunemoto 2:6fb0d2e32144 752 break;
4180_1 0:023c5cda6102 753 }
4180_1 0:023c5cda6102 754 }
4180_1 0:023c5cda6102 755 }
tsunemoto 2:6fb0d2e32144 756
tsunemoto 2:6fb0d2e32144 757 void timer0_init(void)
tsunemoto 2:6fb0d2e32144 758 {
tsunemoto 2:6fb0d2e32144 759 LPC_SC->PCONP |=1<1; //timer0 power on
tsunemoto 2:6fb0d2e32144 760 // 2013.08.09 H.Tsunemoto 100mSec => 0.1mSec Change
tsunemoto 2:6fb0d2e32144 761 //LPC_TIM0->MR0 = 2398000; //100 msec
tsunemoto 2:6fb0d2e32144 762 LPC_TIM0->MR0 = 2398; //0.1 msec
4180_1 0:023c5cda6102 763
tsunemoto 2:6fb0d2e32144 764 LPC_TIM0->MCR = 3; //interrupt and reset control
tsunemoto 2:6fb0d2e32144 765 //3 = Interrupt & reset timer0 on match
tsunemoto 2:6fb0d2e32144 766 //1 = Interrupt only, no reset of timer0
tsunemoto 2:6fb0d2e32144 767 NVIC_EnableIRQ(TIMER0_IRQn); //enable timer0 interrupt
tsunemoto 2:6fb0d2e32144 768 LPC_TIM0->TCR = 1; //enable Timer0
tsunemoto 2:6fb0d2e32144 769 // pc.printf("Done timer_init\n\r");
tsunemoto 2:6fb0d2e32144 770 }
tsunemoto 2:6fb0d2e32144 771
tsunemoto 2:6fb0d2e32144 772 //------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 773 //----- Serial rx Commmand Input & Parameter Set Function -----//
tsunemoto 2:6fb0d2e32144 774 // Tsunemoto Scince 2013.08.08 //
tsunemoto 2:6fb0d2e32144 775 //------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 776 void Ser_Command_Input()
tsunemoto 2:6fb0d2e32144 777 {
tsunemoto 2:6fb0d2e32144 778 int i_RecCharCount;
tsunemoto 2:6fb0d2e32144 779 bool b_CommadERR = 0;
tsunemoto 2:6fb0d2e32144 780
tsunemoto 2:6fb0d2e32144 781 while(rx_cr_Rec != 0){
tsunemoto 2:6fb0d2e32144 782 // Read a line from the large rx buffer from rx interrupt routine
tsunemoto 2:6fb0d2e32144 783 i_RecCharCount = read_line();
tsunemoto 2:6fb0d2e32144 784 if(i_RecCharCount < 3){
tsunemoto 2:6fb0d2e32144 785 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 786 }
tsunemoto 2:6fb0d2e32144 787 else{
tsunemoto 2:6fb0d2e32144 788 switch(rx_line[0]){
tsunemoto 2:6fb0d2e32144 789 // Header "A" ADC Control Command
tsunemoto 2:6fb0d2e32144 790 case 'A':
tsunemoto 2:6fb0d2e32144 791 switch(rx_line[1]){
tsunemoto 2:6fb0d2e32144 792 case 'S':
tsunemoto 2:6fb0d2e32144 793 if(rx_line[2] == '0'){
tsunemoto 2:6fb0d2e32144 794 i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Busy;
tsunemoto 2:6fb0d2e32144 795
tsunemoto 2:6fb0d2e32144 796 }
tsunemoto 2:6fb0d2e32144 797 else{
tsunemoto 2:6fb0d2e32144 798 i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Ready;
tsunemoto 2:6fb0d2e32144 799 }
tsunemoto 2:6fb0d2e32144 800 Start_ADC();
tsunemoto 2:6fb0d2e32144 801 break;
tsunemoto 2:6fb0d2e32144 802 case 'E':
tsunemoto 2:6fb0d2e32144 803 ADC_Stop();
tsunemoto 2:6fb0d2e32144 804 break;
tsunemoto 2:6fb0d2e32144 805 case 'R':
tsunemoto 2:6fb0d2e32144 806 b_CommadERR= com_Check_AR(i_RecCharCount);
tsunemoto 2:6fb0d2e32144 807 break;
tsunemoto 2:6fb0d2e32144 808 case 'L':
tsunemoto 2:6fb0d2e32144 809 b_CommadERR= com_Check_AL(i_RecCharCount);
tsunemoto 2:6fb0d2e32144 810 break;
tsunemoto 2:6fb0d2e32144 811 case 'P':
tsunemoto 2:6fb0d2e32144 812 b_CommadERR= com_Check_AP(i_RecCharCount);
tsunemoto 2:6fb0d2e32144 813 break;
tsunemoto 2:6fb0d2e32144 814 case 'I':
tsunemoto 2:6fb0d2e32144 815 b_CommadERR= com_Check_AI(i_RecCharCount);
tsunemoto 2:6fb0d2e32144 816 break;
tsunemoto 2:6fb0d2e32144 817 case '?':
tsunemoto 2:6fb0d2e32144 818 com_ADC_Table_Param_Send();
tsunemoto 2:6fb0d2e32144 819 break;
tsunemoto 2:6fb0d2e32144 820 default:
tsunemoto 2:6fb0d2e32144 821 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 822 break;
tsunemoto 2:6fb0d2e32144 823 }
tsunemoto 2:6fb0d2e32144 824 break;
tsunemoto 2:6fb0d2e32144 825 // Header "D" DAC Control Command
tsunemoto 2:6fb0d2e32144 826 case 'D':
tsunemoto 2:6fb0d2e32144 827 switch(rx_line[1]){
tsunemoto 2:6fb0d2e32144 828 case 'S': // 'DS'Start Command
tsunemoto 2:6fb0d2e32144 829 if(rx_line[2]=='1'){
tsunemoto 2:6fb0d2e32144 830 i_dac1_pattern_now = DAC1_PATERN_1;
tsunemoto 2:6fb0d2e32144 831 }
tsunemoto 2:6fb0d2e32144 832 else if(rx_line[2]=='2'){
tsunemoto 2:6fb0d2e32144 833 i_dac1_pattern_now = DAC1_PATERN_2;
tsunemoto 2:6fb0d2e32144 834 }
tsunemoto 2:6fb0d2e32144 835 else{
tsunemoto 2:6fb0d2e32144 836 i_dac1_pattern_now = DAC1_PATERN_0;
tsunemoto 2:6fb0d2e32144 837 }
tsunemoto 2:6fb0d2e32144 838 i_dac1_active_status = DAC1_ACT_1_START;
tsunemoto 2:6fb0d2e32144 839 break;
tsunemoto 2:6fb0d2e32144 840 case 'E': // 'DE'Active MOde Stop (End)
tsunemoto 2:6fb0d2e32144 841 i_dac1_active_status = DAC1_ACT_0_READY;
tsunemoto 2:6fb0d2e32144 842 break;
tsunemoto 2:6fb0d2e32144 843 case 'M': // 'DM' DAC Mode Set Single/Pulse/Triangle
tsunemoto 2:6fb0d2e32144 844 b_CommadERR= com_Check_DM(i_RecCharCount);
tsunemoto 2:6fb0d2e32144 845 break;
tsunemoto 2:6fb0d2e32144 846 case 'H': // 'DH' Pulse High Level[V] Set
tsunemoto 2:6fb0d2e32144 847 b_CommadERR= com_Check_DH(i_RecCharCount);
tsunemoto 2:6fb0d2e32144 848 break;
tsunemoto 2:6fb0d2e32144 849 case 'L': // 'DL' Pulse Low Level [V]Set
tsunemoto 2:6fb0d2e32144 850 b_CommadERR= com_Check_DL(i_RecCharCount);
tsunemoto 2:6fb0d2e32144 851 break;
tsunemoto 2:6fb0d2e32144 852 case 'P': // 'DP' Pulse Width [mSec]
tsunemoto 2:6fb0d2e32144 853 b_CommadERR= com_Check_DP(i_RecCharCount);
tsunemoto 2:6fb0d2e32144 854 break;
tsunemoto 2:6fb0d2e32144 855 case 'I': // 'DI' Pulse Interval [mSec]
tsunemoto 2:6fb0d2e32144 856 b_CommadERR= com_Check_DI(i_RecCharCount);
tsunemoto 2:6fb0d2e32144 857 break;
tsunemoto 2:6fb0d2e32144 858 case 'W': // 'DW' Total Pattern Width [Sec]
tsunemoto 2:6fb0d2e32144 859 b_CommadERR= com_Check_DW(i_RecCharCount);
tsunemoto 2:6fb0d2e32144 860 break;
tsunemoto 2:6fb0d2e32144 861 case '?': // Parameter Query
tsunemoto 2:6fb0d2e32144 862 com_Table_Param_Send();
tsunemoto 2:6fb0d2e32144 863 break;
tsunemoto 2:6fb0d2e32144 864 default:
tsunemoto 2:6fb0d2e32144 865 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 866 break;
tsunemoto 2:6fb0d2e32144 867 }
tsunemoto 2:6fb0d2e32144 868 break;
tsunemoto 2:6fb0d2e32144 869 case 'T': // "T?" Timer Interrupt Counter Repry
tsunemoto 2:6fb0d2e32144 870 if (rx_line[1]=='?'){
tsunemoto 2:6fb0d2e32144 871 sprintf(tx_line,"Timer=%d[S}+%d[x0.1mSec] \r\n",timer_1Sec,timer_count);
tsunemoto 2:6fb0d2e32144 872 // Copy tx line buffer to large tx buffer for tx interrupt routine
tsunemoto 2:6fb0d2e32144 873 send_line();
tsunemoto 2:6fb0d2e32144 874
tsunemoto 2:6fb0d2e32144 875 }
tsunemoto 2:6fb0d2e32144 876 else if(rx_line[1]=='C'){
tsunemoto 2:6fb0d2e32144 877 timer_1Sec = timer_count = 0;
tsunemoto 2:6fb0d2e32144 878 }
tsunemoto 2:6fb0d2e32144 879 else{
tsunemoto 2:6fb0d2e32144 880 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 881 }
tsunemoto 2:6fb0d2e32144 882 break;
tsunemoto 2:6fb0d2e32144 883
tsunemoto 2:6fb0d2e32144 884
tsunemoto 2:6fb0d2e32144 885 default:
tsunemoto 2:6fb0d2e32144 886 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 887 break;
tsunemoto 2:6fb0d2e32144 888
tsunemoto 2:6fb0d2e32144 889 }
tsunemoto 2:6fb0d2e32144 890 }
tsunemoto 2:6fb0d2e32144 891 if(b_CommadERR == 0){
tsunemoto 2:6fb0d2e32144 892 sprintf(tx_line,"ACK%d \r\n",rx_cr_Rec);
tsunemoto 2:6fb0d2e32144 893 // Copy tx line buffer to large tx buffer for tx interrupt routine
tsunemoto 2:6fb0d2e32144 894 send_line();
tsunemoto 2:6fb0d2e32144 895 }
tsunemoto 2:6fb0d2e32144 896 else{
tsunemoto 2:6fb0d2e32144 897 sprintf(tx_line,"ERR%d \r\n",rx_cr_Rec);
tsunemoto 2:6fb0d2e32144 898 // Copy tx line buffer to large tx buffer for tx interrupt routine
tsunemoto 2:6fb0d2e32144 899 send_line();
tsunemoto 2:6fb0d2e32144 900 }
tsunemoto 2:6fb0d2e32144 901 rx_cr_Rec--;
tsunemoto 2:6fb0d2e32144 902
tsunemoto 2:6fb0d2e32144 903 }
tsunemoto 2:6fb0d2e32144 904 }
tsunemoto 2:6fb0d2e32144 905 //////////////////////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 906 //------------ Command Check & Set Function ---------------------------------//
tsunemoto 2:6fb0d2e32144 907 // Input :i_RecCharCount :Command Stringth Length //
tsunemoto 2:6fb0d2e32144 908 // rx_line[80] :(Global) Rec Data Stringth //
tsunemoto 2:6fb0d2e32144 909 // Return :bool b_CommadERR 0= ACK //
tsunemoto 2:6fb0d2e32144 910 // 1= ERR //
tsunemoto 2:6fb0d2e32144 911 //////////////////////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 912 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 913 // ADC No.1 "ARxx.x Pulse Mode Pulse Interval Set //
tsunemoto 2:6fb0d2e32144 914 //#define ADC_SAMPLE_RATE_MIN 5
tsunemoto 2:6fb0d2e32144 915 //#define ADC_SAMPLE_RATE_MAX 20000
tsunemoto 2:6fb0d2e32144 916 //int st_adc_mode_param.i_sample_interval = 200; // ADC Sample Rate 5 - 20000(20.0mSec)
tsunemoto 2:6fb0d2e32144 917 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 918 bool com_Check_AR(int i_RecCharCount)
tsunemoto 2:6fb0d2e32144 919 {
tsunemoto 2:6fb0d2e32144 920 bool b_CommadERR=0;
tsunemoto 2:6fb0d2e32144 921 float f_num=0.00f;
tsunemoto 2:6fb0d2e32144 922 char *pt_comRec;
tsunemoto 2:6fb0d2e32144 923
tsunemoto 2:6fb0d2e32144 924 if(i_RecCharCount < 3){
tsunemoto 2:6fb0d2e32144 925 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 926 }
tsunemoto 2:6fb0d2e32144 927 else{
tsunemoto 2:6fb0d2e32144 928 pt_comRec = (char *)&rx_line[2];
tsunemoto 2:6fb0d2e32144 929 f_num = atof(pt_comRec);
tsunemoto 2:6fb0d2e32144 930 if((f_num >= ADC_SAMPLE_RATE_MIN_f ) && (f_num <= ADC_SAMPLE_RATE_MAX_f)){
tsunemoto 2:6fb0d2e32144 931 st_adc_mode_param.i_sample_interval = (int)( f_num * 1000.0f + 0.5f) ;
tsunemoto 2:6fb0d2e32144 932 }
tsunemoto 2:6fb0d2e32144 933 else{
tsunemoto 2:6fb0d2e32144 934 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 935 }
tsunemoto 2:6fb0d2e32144 936
tsunemoto 2:6fb0d2e32144 937 }
tsunemoto 2:6fb0d2e32144 938 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 939 }
tsunemoto 2:6fb0d2e32144 940 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 941 // ADC No.2 "ALx.xxx" ADC Trigger Limit Level 0.00-3.3V
tsunemoto 2:6fb0d2e32144 942 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 943 bool com_Check_AL(int i_RecCharCount)
tsunemoto 2:6fb0d2e32144 944 {
tsunemoto 2:6fb0d2e32144 945 bool b_CommadERR=0;
tsunemoto 2:6fb0d2e32144 946 float f_num=0.00f;
tsunemoto 2:6fb0d2e32144 947 char *pt_comRec;
tsunemoto 2:6fb0d2e32144 948
tsunemoto 2:6fb0d2e32144 949 if(i_RecCharCount < 3){
tsunemoto 2:6fb0d2e32144 950 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 951 }
tsunemoto 2:6fb0d2e32144 952 else{
tsunemoto 2:6fb0d2e32144 953 pt_comRec = (char *)&rx_line[2];
tsunemoto 2:6fb0d2e32144 954 f_num = atof(pt_comRec);
tsunemoto 2:6fb0d2e32144 955 if((f_num >= 0) && (f_num <= 3.3000f)){
tsunemoto 2:6fb0d2e32144 956 st_adc_mode_param.f_trigger_level = f_num;
tsunemoto 2:6fb0d2e32144 957 st_adc_mode_param.us_trigger_level =(int)((f_num/(DAC1_FULL_VOLT_f / 4095.0f))+0.5f);
tsunemoto 2:6fb0d2e32144 958 }
tsunemoto 2:6fb0d2e32144 959 else{
tsunemoto 2:6fb0d2e32144 960 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 961 }
tsunemoto 2:6fb0d2e32144 962 }
tsunemoto 2:6fb0d2e32144 963 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 964 }
tsunemoto 2:6fb0d2e32144 965 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 966 // ADC No.3 "APxx" ADC PreTrigger Send Data Point
tsunemoto 2:6fb0d2e32144 967 //#define ADC_PRE_TRIG_MIN 0
tsunemoto 2:6fb0d2e32144 968 //#define ADC_PRE_TRIG_MAX 100
tsunemoto 2:6fb0d2e32144 969 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 970 bool com_Check_AP(int i_RecCharCount)
tsunemoto 2:6fb0d2e32144 971 {
tsunemoto 2:6fb0d2e32144 972 bool b_CommadERR=0;
tsunemoto 2:6fb0d2e32144 973 float f_num=0.00f;
tsunemoto 2:6fb0d2e32144 974 char *pt_comRec;
tsunemoto 2:6fb0d2e32144 975
tsunemoto 2:6fb0d2e32144 976 if(i_RecCharCount < 3){
tsunemoto 2:6fb0d2e32144 977 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 978 }
tsunemoto 2:6fb0d2e32144 979 else{
tsunemoto 2:6fb0d2e32144 980 pt_comRec = (char *)&rx_line[2];
tsunemoto 2:6fb0d2e32144 981 f_num = atof(pt_comRec);
tsunemoto 2:6fb0d2e32144 982 if((f_num >= ADC_PRE_TRIG_MIN ) && (f_num <= ADC_PRE_TRIG_MAX)){
tsunemoto 2:6fb0d2e32144 983 st_adc_mode_param.i_pre_trig_point = (int)( f_num + 0.5f) ;
tsunemoto 2:6fb0d2e32144 984 }
tsunemoto 2:6fb0d2e32144 985 else{
tsunemoto 2:6fb0d2e32144 986 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 987 }
tsunemoto 2:6fb0d2e32144 988
tsunemoto 2:6fb0d2e32144 989 }
tsunemoto 2:6fb0d2e32144 990 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 991
tsunemoto 2:6fb0d2e32144 992 }
tsunemoto 2:6fb0d2e32144 993 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 994 // ADC No.4 "AIx.xxx" ADC Pulse End Point Check Time
tsunemoto 2:6fb0d2e32144 995 //#define ADC_PULSE_END_MIN_f 0.1f //0.1Sec
tsunemoto 2:6fb0d2e32144 996 //#define ADC_PULSE_END_MAX_f 5.0f //5.0Sec
tsunemoto 2:6fb0d2e32144 997 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 998 bool com_Check_AI(int i_RecCharCount)
tsunemoto 2:6fb0d2e32144 999 {
tsunemoto 2:6fb0d2e32144 1000 bool b_CommadERR=0;
tsunemoto 2:6fb0d2e32144 1001 float f_num=0.00f;
tsunemoto 2:6fb0d2e32144 1002 char *pt_comRec;
tsunemoto 2:6fb0d2e32144 1003
tsunemoto 2:6fb0d2e32144 1004 if(i_RecCharCount < 3){
tsunemoto 2:6fb0d2e32144 1005 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1006 }
tsunemoto 2:6fb0d2e32144 1007 else{
tsunemoto 2:6fb0d2e32144 1008 pt_comRec = (char *)&rx_line[2];
tsunemoto 2:6fb0d2e32144 1009 f_num = atof(pt_comRec);
tsunemoto 2:6fb0d2e32144 1010 if((f_num >= ADC_PULSE_END_MIN_f ) && (f_num <= ADC_PULSE_END_MAX_f)){
tsunemoto 2:6fb0d2e32144 1011 st_adc_mode_param.i_pulse_end_time = (int)( f_num * 10000.0f + 0.5f) ;
tsunemoto 2:6fb0d2e32144 1012 }
tsunemoto 2:6fb0d2e32144 1013 else{
tsunemoto 2:6fb0d2e32144 1014 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1015 }
tsunemoto 2:6fb0d2e32144 1016
tsunemoto 2:6fb0d2e32144 1017 }
tsunemoto 2:6fb0d2e32144 1018 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 1019 }
tsunemoto 2:6fb0d2e32144 1020 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1021 // ADC No.5 "A?" DAC Parameter Repry //
tsunemoto 2:6fb0d2e32144 1022 //typedef struct st_adc_param{
tsunemoto 2:6fb0d2e32144 1023 // int i_sample_interval; // DAC Output Pattern
tsunemoto 2:6fb0d2e32144 1024 // float f_trigger_level;
tsunemoto 2:6fb0d2e32144 1025 // us_trigger_level;
tsunemoto 2:6fb0d2e32144 1026 // int i_pre_trig_point;
tsunemoto 2:6fb0d2e32144 1027 // int i_pulse_end_time;
tsunemoto 2:6fb0d2e32144 1028 //}ST_ADC_PARAM;
tsunemoto 2:6fb0d2e32144 1029 //
tsunemoto 2:6fb0d2e32144 1030 //ST_ADC_PARAM st_adc_mode_param;
tsunemoto 2:6fb0d2e32144 1031 //
tsunemoto 2:6fb0d2e32144 1032 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1033 void com_ADC_Table_Param_Send()
tsunemoto 2:6fb0d2e32144 1034 {
tsunemoto 2:6fb0d2e32144 1035 float f_num;
tsunemoto 2:6fb0d2e32144 1036
tsunemoto 2:6fb0d2e32144 1037 f_num = ((float)st_adc_mode_param.i_sample_interval + 0.5f)/1000.0f;
tsunemoto 2:6fb0d2e32144 1038 sprintf(tx_line,"AR%2.3f[mSec]\r\n",f_num);
tsunemoto 2:6fb0d2e32144 1039 send_line();
tsunemoto 2:6fb0d2e32144 1040 f_num = st_adc_mode_param.f_trigger_level;
tsunemoto 2:6fb0d2e32144 1041 sprintf(tx_line,"AL%1.3f[V]:(0x%03x)\r\n",f_num,st_adc_mode_param.us_trigger_level);
tsunemoto 2:6fb0d2e32144 1042 send_line();
tsunemoto 2:6fb0d2e32144 1043 sprintf(tx_line,"AP%d[Sample]\r\n",st_adc_mode_param.i_pre_trig_point);
tsunemoto 2:6fb0d2e32144 1044 send_line();
tsunemoto 2:6fb0d2e32144 1045 f_num = ((float)st_adc_mode_param.i_pulse_end_time + 0.5f)/10000.0f;
tsunemoto 2:6fb0d2e32144 1046 sprintf(tx_line,"AI%1.3f[Sec]\r\n",f_num);
tsunemoto 2:6fb0d2e32144 1047 send_line();
tsunemoto 2:6fb0d2e32144 1048 // for Debug
tsunemoto 2:6fb0d2e32144 1049 sprintf(tx_line,"ADC Sample Count = %d,BuffLoop=%d\r\n",ADC_Count1,ADC_Count1Block);
tsunemoto 2:6fb0d2e32144 1050 send_line();
tsunemoto 2:6fb0d2e32144 1051 //
tsunemoto 2:6fb0d2e32144 1052 // Ative Mode Status Controll
tsunemoto 2:6fb0d2e32144 1053 //#define ActiveMode_ADC_Sample_Stop 0
tsunemoto 2:6fb0d2e32144 1054 //#define ActiveMode_ADC_Sample_Ready 1 //
tsunemoto 2:6fb0d2e32144 1055 //#define ActiveMode_ADC_Sample_Busy 2 //
tsunemoto 2:6fb0d2e32144 1056 //int i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Stop;
tsunemoto 2:6fb0d2e32144 1057 // Trigger Mode Status Control
tsunemoto 2:6fb0d2e32144 1058 //#define ADC_TRIGGER_READY 0 //Trigger Mode Ready :Trigger Wait & No Data Send
tsunemoto 2:6fb0d2e32144 1059 //#define ADC_TRIGGER_BUSY 1 //Trigger Mode Busy :Trigger Detected & Sample Data Send
tsunemoto 2:6fb0d2e32144 1060 //#define ADC_TRIGGER_END 2 //Trigger Mode END :Sample End & Data Send Done Wait
tsunemoto 2:6fb0d2e32144 1061 //int i_adc_Trigger_Sample_Status = ADC_TRIGGER_READY;
tsunemoto 2:6fb0d2e32144 1062 //volatile unsigned short adc_CH1_now;
tsunemoto 2:6fb0d2e32144 1063 //int i_adc_trigger_end_count;
tsunemoto 2:6fb0d2e32144 1064 switch(i_adc_ActiveMode_status){
tsunemoto 2:6fb0d2e32144 1065 case ActiveMode_ADC_Sample_Stop:
tsunemoto 2:6fb0d2e32144 1066 sprintf(tx_line,"ADC i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Stop\r\n");
tsunemoto 2:6fb0d2e32144 1067 break;
tsunemoto 2:6fb0d2e32144 1068 case ActiveMode_ADC_Sample_Ready:
tsunemoto 2:6fb0d2e32144 1069 sprintf(tx_line,"ADC i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Ready\r\n");
tsunemoto 2:6fb0d2e32144 1070 break;
tsunemoto 2:6fb0d2e32144 1071 case ActiveMode_ADC_Sample_Busy:
tsunemoto 2:6fb0d2e32144 1072 sprintf(tx_line,"ADC i_adc_ActiveMode_status = ActiveMode_ADC_Sample_Busy\r\n");
tsunemoto 2:6fb0d2e32144 1073 break;
tsunemoto 2:6fb0d2e32144 1074 }
tsunemoto 2:6fb0d2e32144 1075 send_line();
tsunemoto 2:6fb0d2e32144 1076 switch(i_adc_Trigger_Sample_Status){
tsunemoto 2:6fb0d2e32144 1077 case ADC_TRIGGER_READY:
tsunemoto 2:6fb0d2e32144 1078 sprintf(tx_line,"ADC i_adc_Trigger_Sample_Status = ADC_TRIGGER_READY\r\n");
tsunemoto 2:6fb0d2e32144 1079 break;
tsunemoto 2:6fb0d2e32144 1080 case ADC_TRIGGER_BUSY:
tsunemoto 2:6fb0d2e32144 1081 sprintf(tx_line,"ADC i_adc_Trigger_Sample_Status = ADC_TRIGGER_BUSY\r\n");
tsunemoto 2:6fb0d2e32144 1082 break;
tsunemoto 2:6fb0d2e32144 1083 case ADC_TRIGGER_END:
tsunemoto 2:6fb0d2e32144 1084 sprintf(tx_line,"ADC i_adc_Trigger_Sample_Status = ADC_TRIGGER_END\r\n");
tsunemoto 2:6fb0d2e32144 1085 break;
tsunemoto 2:6fb0d2e32144 1086 }
tsunemoto 2:6fb0d2e32144 1087 send_line();
tsunemoto 2:6fb0d2e32144 1088 sprintf(tx_line,"ADC input level:%03x i_adc_trigger_end_count = %d\r\n",adc_CH1_now,i_adc_trigger_end_count);
tsunemoto 2:6fb0d2e32144 1089 send_line();
tsunemoto 2:6fb0d2e32144 1090
tsunemoto 2:6fb0d2e32144 1091
tsunemoto 2:6fb0d2e32144 1092 }
tsunemoto 2:6fb0d2e32144 1093
tsunemoto 2:6fb0d2e32144 1094
tsunemoto 2:6fb0d2e32144 1095 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1096 // DAC_No.1 "DMn:xx (SINGLE/PULSE/TRIANGLE) //
tsunemoto 2:6fb0d2e32144 1097 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1098 bool com_Check_DM(int i_RecCharCount)
tsunemoto 2:6fb0d2e32144 1099 {
tsunemoto 2:6fb0d2e32144 1100 bool b_CommadERR=0;
tsunemoto 2:6fb0d2e32144 1101 int i_work;
tsunemoto 2:6fb0d2e32144 1102 if(i_RecCharCount < 7){
tsunemoto 2:6fb0d2e32144 1103 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1104 }
tsunemoto 2:6fb0d2e32144 1105 if(rx_line[3]==':'){
tsunemoto 2:6fb0d2e32144 1106 if((rx_line[4]=='S') & (rx_line[5]=='I')){
tsunemoto 2:6fb0d2e32144 1107 i_work = DAC1_PATTERN_1_SINGLE_PULSE;
tsunemoto 2:6fb0d2e32144 1108 }
tsunemoto 2:6fb0d2e32144 1109 else if ((rx_line[4]=='P') & (rx_line[5]=='U')){
tsunemoto 2:6fb0d2e32144 1110 i_work = DAC1_PATTERN_2_PULSE;
tsunemoto 2:6fb0d2e32144 1111 }
tsunemoto 2:6fb0d2e32144 1112 else if((rx_line[4]=='T') & (rx_line[5]=='R')){
tsunemoto 2:6fb0d2e32144 1113 i_work = DAC1_PATTERN_3_TRIANGLE;
tsunemoto 2:6fb0d2e32144 1114 }
tsunemoto 2:6fb0d2e32144 1115 else{
tsunemoto 2:6fb0d2e32144 1116 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1117 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 1118 }
tsunemoto 2:6fb0d2e32144 1119 switch(rx_line[2]){
tsunemoto 2:6fb0d2e32144 1120 case '0':
tsunemoto 2:6fb0d2e32144 1121 st_dac1_param[0].i_pattern = i_work;
tsunemoto 2:6fb0d2e32144 1122 break;
tsunemoto 2:6fb0d2e32144 1123 case '1':
tsunemoto 2:6fb0d2e32144 1124 st_dac1_param[1].i_pattern = i_work;
tsunemoto 2:6fb0d2e32144 1125 break;
tsunemoto 2:6fb0d2e32144 1126 case '2':
tsunemoto 2:6fb0d2e32144 1127 st_dac1_param[2].i_pattern = i_work;
tsunemoto 2:6fb0d2e32144 1128 break;
tsunemoto 2:6fb0d2e32144 1129 default:
tsunemoto 2:6fb0d2e32144 1130 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1131 break;
tsunemoto 2:6fb0d2e32144 1132 }
tsunemoto 2:6fb0d2e32144 1133 }
tsunemoto 2:6fb0d2e32144 1134 else{
tsunemoto 2:6fb0d2e32144 1135 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1136 }
tsunemoto 2:6fb0d2e32144 1137 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 1138 }
tsunemoto 2:6fb0d2e32144 1139 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1140 // DAC_No.2 "DHn:xx.x Pulse High Level Volt Set (0.000 - 3.300[V]) //
tsunemoto 2:6fb0d2e32144 1141 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1142 bool com_Check_DH(int i_RecCharCount)
tsunemoto 2:6fb0d2e32144 1143 {
tsunemoto 2:6fb0d2e32144 1144 bool b_CommadERR=0;
tsunemoto 2:6fb0d2e32144 1145 float f_num=0.00f;
tsunemoto 2:6fb0d2e32144 1146 char *pt_comRec;
tsunemoto 2:6fb0d2e32144 1147
tsunemoto 2:6fb0d2e32144 1148 //sprintf(tx_line,"DH?? \r\n");
tsunemoto 2:6fb0d2e32144 1149 //strcpy((char *)rx_line[4],tx_line);
tsunemoto 2:6fb0d2e32144 1150 //send_line();
tsunemoto 2:6fb0d2e32144 1151 if(i_RecCharCount < 6){
tsunemoto 2:6fb0d2e32144 1152 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1153 }
tsunemoto 2:6fb0d2e32144 1154 else{
tsunemoto 2:6fb0d2e32144 1155 if(rx_line[3]==':'){
tsunemoto 2:6fb0d2e32144 1156 pt_comRec = (char *)&rx_line[4];
tsunemoto 2:6fb0d2e32144 1157 f_num = atof(pt_comRec);
tsunemoto 2:6fb0d2e32144 1158 if((f_num >= 0) && (f_num <= 3.3000f)){
tsunemoto 2:6fb0d2e32144 1159 f_num = f_num/DAC1_FULL_VOLT_f;
tsunemoto 2:6fb0d2e32144 1160 switch(rx_line[2]){
tsunemoto 2:6fb0d2e32144 1161 case '0':
tsunemoto 2:6fb0d2e32144 1162 st_dac1_param[0].f_pulse_high = f_num;
tsunemoto 2:6fb0d2e32144 1163 break;
tsunemoto 2:6fb0d2e32144 1164 case '1':
tsunemoto 2:6fb0d2e32144 1165 st_dac1_param[1].f_pulse_high = f_num;
tsunemoto 2:6fb0d2e32144 1166 break;
tsunemoto 2:6fb0d2e32144 1167 case '2':
tsunemoto 2:6fb0d2e32144 1168 st_dac1_param[2].f_pulse_high = f_num;
tsunemoto 2:6fb0d2e32144 1169 break;
tsunemoto 2:6fb0d2e32144 1170
tsunemoto 2:6fb0d2e32144 1171 default:
tsunemoto 2:6fb0d2e32144 1172 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1173 break;
tsunemoto 2:6fb0d2e32144 1174 }
tsunemoto 2:6fb0d2e32144 1175 }
tsunemoto 2:6fb0d2e32144 1176 else{
tsunemoto 2:6fb0d2e32144 1177 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1178 }
tsunemoto 2:6fb0d2e32144 1179 }
tsunemoto 2:6fb0d2e32144 1180 else{
tsunemoto 2:6fb0d2e32144 1181 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1182 }
tsunemoto 2:6fb0d2e32144 1183 }
tsunemoto 2:6fb0d2e32144 1184 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 1185 }
tsunemoto 2:6fb0d2e32144 1186 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1187 // DAC_No.3 "DLn:xx.x Pulse Low Level Volt Set (0.000 - 3.300[V]) //
tsunemoto 2:6fb0d2e32144 1188 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1189 bool com_Check_DL(int i_RecCharCount)
tsunemoto 2:6fb0d2e32144 1190 {
tsunemoto 2:6fb0d2e32144 1191 bool b_CommadERR=0;
tsunemoto 2:6fb0d2e32144 1192 float f_num=0.00f;
tsunemoto 2:6fb0d2e32144 1193 char *pt_comRec;
tsunemoto 2:6fb0d2e32144 1194
tsunemoto 2:6fb0d2e32144 1195 if(i_RecCharCount < 6){
tsunemoto 2:6fb0d2e32144 1196 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1197 }
tsunemoto 2:6fb0d2e32144 1198 else{
tsunemoto 2:6fb0d2e32144 1199 if(rx_line[3]==':'){
tsunemoto 2:6fb0d2e32144 1200 pt_comRec = (char *)&rx_line[4];
tsunemoto 2:6fb0d2e32144 1201 f_num = atof(pt_comRec);
tsunemoto 2:6fb0d2e32144 1202 if((f_num >= 0) && (f_num <= 3.3000f)){
tsunemoto 2:6fb0d2e32144 1203 f_num = f_num/DAC1_FULL_VOLT_f;
tsunemoto 2:6fb0d2e32144 1204 switch(rx_line[2]){
tsunemoto 2:6fb0d2e32144 1205 case '0':
tsunemoto 2:6fb0d2e32144 1206 st_dac1_param[0].f_pulse_low = f_num;
tsunemoto 2:6fb0d2e32144 1207 break;
tsunemoto 2:6fb0d2e32144 1208 case '1':
tsunemoto 2:6fb0d2e32144 1209 st_dac1_param[1].f_pulse_low = f_num;
tsunemoto 2:6fb0d2e32144 1210 break;
tsunemoto 2:6fb0d2e32144 1211 case '2':
tsunemoto 2:6fb0d2e32144 1212 st_dac1_param[2].f_pulse_low = f_num;
tsunemoto 2:6fb0d2e32144 1213 break;
tsunemoto 2:6fb0d2e32144 1214
tsunemoto 2:6fb0d2e32144 1215 default:
tsunemoto 2:6fb0d2e32144 1216 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1217 break;
tsunemoto 2:6fb0d2e32144 1218 }
tsunemoto 2:6fb0d2e32144 1219 }
tsunemoto 2:6fb0d2e32144 1220 else{
tsunemoto 2:6fb0d2e32144 1221 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1222 }
tsunemoto 2:6fb0d2e32144 1223 }
tsunemoto 2:6fb0d2e32144 1224 else{
tsunemoto 2:6fb0d2e32144 1225 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1226 }
tsunemoto 2:6fb0d2e32144 1227 }
tsunemoto 2:6fb0d2e32144 1228 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 1229 }
tsunemoto 2:6fb0d2e32144 1230 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1231 // DAC_No.4 "DPn:xx.x Pulse Mode Pulse Width Set (0.1 - 2000.0[mSec]) //
tsunemoto 2:6fb0d2e32144 1232 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1233 bool com_Check_DP(int i_RecCharCount)
tsunemoto 2:6fb0d2e32144 1234 {
tsunemoto 2:6fb0d2e32144 1235 bool b_CommadERR=0;
tsunemoto 2:6fb0d2e32144 1236 float f_num=0.00f;
tsunemoto 2:6fb0d2e32144 1237 int i_work;
tsunemoto 2:6fb0d2e32144 1238 char *pt_comRec;
tsunemoto 2:6fb0d2e32144 1239
tsunemoto 2:6fb0d2e32144 1240 if(i_RecCharCount < 6){
tsunemoto 2:6fb0d2e32144 1241 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1242 }
tsunemoto 2:6fb0d2e32144 1243 else{
tsunemoto 2:6fb0d2e32144 1244 if(rx_line[3]==':'){
tsunemoto 2:6fb0d2e32144 1245 pt_comRec = (char *)&rx_line[4];
tsunemoto 2:6fb0d2e32144 1246 f_num = atof(pt_comRec);
tsunemoto 2:6fb0d2e32144 1247 if((f_num >= 0.1f) && (f_num <= DAC1_PULSE_INT_MAX_f)){
tsunemoto 2:6fb0d2e32144 1248 i_work = (int)(f_num*10.0f+0.5f);
tsunemoto 2:6fb0d2e32144 1249 switch(rx_line[2]){
tsunemoto 2:6fb0d2e32144 1250 case '0':
tsunemoto 2:6fb0d2e32144 1251 st_dac1_param[0].i_pulse_width = i_work;
tsunemoto 2:6fb0d2e32144 1252 break;
tsunemoto 2:6fb0d2e32144 1253 case '1':
tsunemoto 2:6fb0d2e32144 1254 st_dac1_param[1].i_pulse_width = i_work;
tsunemoto 2:6fb0d2e32144 1255 break;
tsunemoto 2:6fb0d2e32144 1256 case '2':
tsunemoto 2:6fb0d2e32144 1257 st_dac1_param[2].i_pulse_width = i_work;
tsunemoto 2:6fb0d2e32144 1258 break;
tsunemoto 2:6fb0d2e32144 1259
tsunemoto 2:6fb0d2e32144 1260 default:
tsunemoto 2:6fb0d2e32144 1261 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1262 break;
tsunemoto 2:6fb0d2e32144 1263 }
tsunemoto 2:6fb0d2e32144 1264 }
tsunemoto 2:6fb0d2e32144 1265 else{
tsunemoto 2:6fb0d2e32144 1266 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1267 }
tsunemoto 2:6fb0d2e32144 1268 }
tsunemoto 2:6fb0d2e32144 1269 else{
tsunemoto 2:6fb0d2e32144 1270 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1271 }
tsunemoto 2:6fb0d2e32144 1272 }
tsunemoto 2:6fb0d2e32144 1273 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 1274 }
tsunemoto 2:6fb0d2e32144 1275 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1276 // DAC_No.5 "DIn:xx.x Pulse Mode Pulse Interval Set //
tsunemoto 2:6fb0d2e32144 1277 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1278 bool com_Check_DI(int i_RecCharCount)
tsunemoto 2:6fb0d2e32144 1279 {
tsunemoto 2:6fb0d2e32144 1280 bool b_CommadERR=0;
tsunemoto 2:6fb0d2e32144 1281 float f_num=0.00f;
tsunemoto 2:6fb0d2e32144 1282 int i_work;
tsunemoto 2:6fb0d2e32144 1283 char *pt_comRec;
tsunemoto 2:6fb0d2e32144 1284
tsunemoto 2:6fb0d2e32144 1285 if(i_RecCharCount < 6){
tsunemoto 2:6fb0d2e32144 1286 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1287 }
tsunemoto 2:6fb0d2e32144 1288 else{
tsunemoto 2:6fb0d2e32144 1289 if(rx_line[3]==':'){
tsunemoto 2:6fb0d2e32144 1290 pt_comRec = (char *)&rx_line[4];
tsunemoto 2:6fb0d2e32144 1291 f_num = atof(pt_comRec);
tsunemoto 2:6fb0d2e32144 1292 if((f_num >= 0.1f) && (f_num <= DAC1_PULSE_INT_MAX_f)){
tsunemoto 2:6fb0d2e32144 1293 i_work = (int)(f_num*10.0f+0.5f);
tsunemoto 2:6fb0d2e32144 1294 switch(rx_line[2]){
tsunemoto 2:6fb0d2e32144 1295 case '0':
tsunemoto 2:6fb0d2e32144 1296 st_dac1_param[0].i_pulse_interval = i_work;
tsunemoto 2:6fb0d2e32144 1297 break;
tsunemoto 2:6fb0d2e32144 1298 case '1':
tsunemoto 2:6fb0d2e32144 1299 st_dac1_param[1].i_pulse_interval = i_work;
tsunemoto 2:6fb0d2e32144 1300 break;
tsunemoto 2:6fb0d2e32144 1301 case '2':
tsunemoto 2:6fb0d2e32144 1302 st_dac1_param[2].i_pulse_interval = i_work;
tsunemoto 2:6fb0d2e32144 1303 break;
tsunemoto 2:6fb0d2e32144 1304
tsunemoto 2:6fb0d2e32144 1305 default:
tsunemoto 2:6fb0d2e32144 1306 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1307 break;
tsunemoto 2:6fb0d2e32144 1308 }
tsunemoto 2:6fb0d2e32144 1309 }
tsunemoto 2:6fb0d2e32144 1310 else{
tsunemoto 2:6fb0d2e32144 1311 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1312 }
tsunemoto 2:6fb0d2e32144 1313 }
tsunemoto 2:6fb0d2e32144 1314 else{
tsunemoto 2:6fb0d2e32144 1315 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1316 }
tsunemoto 2:6fb0d2e32144 1317 }
tsunemoto 2:6fb0d2e32144 1318 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 1319 }
tsunemoto 2:6fb0d2e32144 1320 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1321 // DAC_No.6 "DWn:xx.x Wave Form Total Width Set //
tsunemoto 2:6fb0d2e32144 1322 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1323 bool com_Check_DW(int i_RecCharCount)
tsunemoto 2:6fb0d2e32144 1324 {
tsunemoto 2:6fb0d2e32144 1325 bool b_CommadERR=0;
tsunemoto 2:6fb0d2e32144 1326 float f_num=0.00f;
tsunemoto 2:6fb0d2e32144 1327 int i_work;
tsunemoto 2:6fb0d2e32144 1328 char *pt_comRec;
tsunemoto 2:6fb0d2e32144 1329
tsunemoto 2:6fb0d2e32144 1330 if(i_RecCharCount < 6){
tsunemoto 2:6fb0d2e32144 1331 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1332 }
tsunemoto 2:6fb0d2e32144 1333 else{
tsunemoto 2:6fb0d2e32144 1334 if(rx_line[3]==':'){
tsunemoto 2:6fb0d2e32144 1335 pt_comRec = (char *)&rx_line[4];
tsunemoto 2:6fb0d2e32144 1336 f_num = atof(pt_comRec);
tsunemoto 2:6fb0d2e32144 1337 if((f_num >= 0.0001f) && (f_num <= DAC1_PULSE_TOTAL_TIME_MAX_f)){
tsunemoto 2:6fb0d2e32144 1338 i_work = (int)(f_num*10000.0f+0.5f);
tsunemoto 2:6fb0d2e32144 1339 switch(rx_line[2]){
tsunemoto 2:6fb0d2e32144 1340 case '0':
tsunemoto 2:6fb0d2e32144 1341 st_dac1_param[0].i_Total_time = i_work;
tsunemoto 2:6fb0d2e32144 1342 break;
tsunemoto 2:6fb0d2e32144 1343 case '1':
tsunemoto 2:6fb0d2e32144 1344 st_dac1_param[1].i_Total_time = i_work;
tsunemoto 2:6fb0d2e32144 1345 break;
tsunemoto 2:6fb0d2e32144 1346 case '2':
tsunemoto 2:6fb0d2e32144 1347 st_dac1_param[2].i_Total_time = i_work;
tsunemoto 2:6fb0d2e32144 1348 break;
tsunemoto 2:6fb0d2e32144 1349
tsunemoto 2:6fb0d2e32144 1350 default:
tsunemoto 2:6fb0d2e32144 1351 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1352 break;
tsunemoto 2:6fb0d2e32144 1353 }
tsunemoto 2:6fb0d2e32144 1354 }
tsunemoto 2:6fb0d2e32144 1355 else{
tsunemoto 2:6fb0d2e32144 1356 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1357 }
tsunemoto 2:6fb0d2e32144 1358 }
tsunemoto 2:6fb0d2e32144 1359 else{
tsunemoto 2:6fb0d2e32144 1360 b_CommadERR = 1;
tsunemoto 2:6fb0d2e32144 1361 }
tsunemoto 2:6fb0d2e32144 1362 }
tsunemoto 2:6fb0d2e32144 1363 return(b_CommadERR);
tsunemoto 2:6fb0d2e32144 1364 }
tsunemoto 2:6fb0d2e32144 1365 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1366 // DAC_No.7 "D?" DAC Parameter RepryWave Form Total Width Set //
tsunemoto 2:6fb0d2e32144 1367 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1368 void com_Table_Param_Send()
tsunemoto 2:6fb0d2e32144 1369 {
tsunemoto 2:6fb0d2e32144 1370 float f_num;
tsunemoto 2:6fb0d2e32144 1371 int i;
tsunemoto 2:6fb0d2e32144 1372
tsunemoto 2:6fb0d2e32144 1373 for (i=0;i<DAC1_PATTERN_MAX;i++){
tsunemoto 2:6fb0d2e32144 1374 sprintf(tx_line,"DAC Pattern Table:%d\r\n",i);
tsunemoto 2:6fb0d2e32144 1375 send_line();
tsunemoto 2:6fb0d2e32144 1376 if (st_dac1_param[i].i_pattern == DAC1_PATTERN_1_SINGLE_PULSE){
tsunemoto 2:6fb0d2e32144 1377 sprintf(tx_line,"DM%1d:SINGLE\r\n",i);
tsunemoto 2:6fb0d2e32144 1378 }
tsunemoto 2:6fb0d2e32144 1379 else if (st_dac1_param[i].i_pattern == DAC1_PATTERN_2_PULSE){
tsunemoto 2:6fb0d2e32144 1380 sprintf(tx_line,"DM%1d:PULSE\r\n",i);
tsunemoto 2:6fb0d2e32144 1381 }
tsunemoto 2:6fb0d2e32144 1382 else{
tsunemoto 2:6fb0d2e32144 1383 sprintf(tx_line,"DM%1d:TRIANGLE\r\n",i);
tsunemoto 2:6fb0d2e32144 1384 }
tsunemoto 2:6fb0d2e32144 1385 send_line();
tsunemoto 2:6fb0d2e32144 1386 f_num = st_dac1_param[i].f_pulse_high*DAC1_FULL_VOLT_f;
tsunemoto 2:6fb0d2e32144 1387 sprintf(tx_line,"DH%1d:%1.3f[V]\r\n",i,f_num);
tsunemoto 2:6fb0d2e32144 1388 send_line();
tsunemoto 2:6fb0d2e32144 1389 f_num = st_dac1_param[i].f_pulse_low *DAC1_FULL_VOLT_f;
tsunemoto 2:6fb0d2e32144 1390 sprintf(tx_line,"DL%1d:%1.3f[V]\r\n",i,f_num);
tsunemoto 2:6fb0d2e32144 1391 send_line();
tsunemoto 2:6fb0d2e32144 1392 f_num = ((float)st_dac1_param[i].i_pulse_width + 0.005) / 10.0f;;
tsunemoto 2:6fb0d2e32144 1393 sprintf(tx_line,"DP%1d:%4.1f[mSec]\r\n",i,f_num);
tsunemoto 2:6fb0d2e32144 1394 send_line();
tsunemoto 2:6fb0d2e32144 1395 f_num = ((float)st_dac1_param[i].i_pulse_interval + 0.005)/10.0f;
tsunemoto 2:6fb0d2e32144 1396 sprintf(tx_line,"DI%1d:%4.1f[mSec]\r\n",i,f_num);
tsunemoto 2:6fb0d2e32144 1397 send_line();
tsunemoto 2:6fb0d2e32144 1398 f_num = ((float)st_dac1_param[i].i_Total_time + 0.005)/10000.0f;
tsunemoto 2:6fb0d2e32144 1399 sprintf(tx_line,"DW%1d:%1.4f[Sec]\r\n",i,f_num);
tsunemoto 2:6fb0d2e32144 1400 send_line();
tsunemoto 2:6fb0d2e32144 1401 sprintf(tx_line,"\r\n");
tsunemoto 2:6fb0d2e32144 1402 send_line();
tsunemoto 2:6fb0d2e32144 1403 }
tsunemoto 2:6fb0d2e32144 1404 }
tsunemoto 2:6fb0d2e32144 1405
tsunemoto 2:6fb0d2e32144 1406 //////////////////////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 1407 //////////////////////////////////////////////////////////////////////////////////
tsunemoto 2:6fb0d2e32144 1408
tsunemoto 2:6fb0d2e32144 1409
tsunemoto 2:6fb0d2e32144 1410 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1411 //------------------------------------------------------------------------------//
tsunemoto 2:6fb0d2e32144 1412 //----- Serial tx/rx Communication
tsunemoto 2:6fb0d2e32144 1413 //------------------------------------------------------------------------------//
4180_1 0:023c5cda6102 1414 // Copy tx line buffer to large tx buffer for tx interrupt routine
4180_1 0:023c5cda6102 1415 void send_line() {
4180_1 0:023c5cda6102 1416 int i;
4180_1 0:023c5cda6102 1417 char temp_char;
4180_1 0:023c5cda6102 1418 bool empty;
4180_1 0:023c5cda6102 1419 i = 0;
4180_1 0:023c5cda6102 1420 // Start Critical Section - don't interrupt while changing global buffer variables
4180_1 0:023c5cda6102 1421 NVIC_DisableIRQ(UART1_IRQn);
4180_1 0:023c5cda6102 1422 empty = (tx_in == tx_out);
4180_1 0:023c5cda6102 1423 while ((i==0) || (tx_line[i-1] != '\n')) {
4180_1 0:023c5cda6102 1424 // Wait if buffer full
tsunemoto 2:6fb0d2e32144 1425 if (((tx_in + 1) % ser_buffer_size) == tx_out) {
4180_1 0:023c5cda6102 1426 // End Critical Section - need to let interrupt routine empty buffer by sending
4180_1 0:023c5cda6102 1427 NVIC_EnableIRQ(UART1_IRQn);
tsunemoto 2:6fb0d2e32144 1428 while (((tx_in + 1) % ser_buffer_size) == tx_out) {
4180_1 0:023c5cda6102 1429 }
4180_1 0:023c5cda6102 1430 // Start Critical Section - don't interrupt while changing global buffer variables
4180_1 0:023c5cda6102 1431 NVIC_DisableIRQ(UART1_IRQn);
4180_1 0:023c5cda6102 1432 }
4180_1 0:023c5cda6102 1433 tx_buffer[tx_in] = tx_line[i];
4180_1 0:023c5cda6102 1434 i++;
tsunemoto 2:6fb0d2e32144 1435 tx_in = (tx_in + 1) % ser_buffer_size;
4180_1 0:023c5cda6102 1436 }
4180_1 0:023c5cda6102 1437 if (device.writeable() && (empty)) {
4180_1 0:023c5cda6102 1438 temp_char = tx_buffer[tx_out];
tsunemoto 2:6fb0d2e32144 1439 tx_out = (tx_out + 1) % ser_buffer_size;
4180_1 0:023c5cda6102 1440 // Send first character to start tx interrupts, if stopped
4180_1 0:023c5cda6102 1441 device.putc(temp_char);
4180_1 0:023c5cda6102 1442 }
4180_1 0:023c5cda6102 1443 // End Critical Section
4180_1 0:023c5cda6102 1444 NVIC_EnableIRQ(UART1_IRQn);
4180_1 0:023c5cda6102 1445 return;
4180_1 0:023c5cda6102 1446 }
4180_1 0:023c5cda6102 1447
4180_1 0:023c5cda6102 1448 // Read a line from the large rx buffer from rx interrupt routine
tsunemoto 2:6fb0d2e32144 1449 // 2013.08.08 H.Tsunemoto
tsunemoto 2:6fb0d2e32144 1450 // Append Return Chear Number
tsunemoto 2:6fb0d2e32144 1451 int read_line(){
tsunemoto 2:6fb0d2e32144 1452 //void read_line() {
4180_1 0:023c5cda6102 1453 int i;
4180_1 0:023c5cda6102 1454 i = 0;
tsunemoto 2:6fb0d2e32144 1455 // Start Critical Section - don't interrupt while changing global buffer variables
4180_1 0:023c5cda6102 1456 NVIC_DisableIRQ(UART1_IRQn);
tsunemoto 2:6fb0d2e32144 1457 // Loop reading rx buffer characters until end of line character
4180_1 0:023c5cda6102 1458 while ((i==0) || (rx_line[i-1] != '\r')) {
tsunemoto 2:6fb0d2e32144 1459 // Wait if buffer empty
4180_1 0:023c5cda6102 1460 if (rx_in == rx_out) {
tsunemoto 2:6fb0d2e32144 1461 // End Critical Section - need to allow rx interrupt to get new characters for buffer
4180_1 0:023c5cda6102 1462 NVIC_EnableIRQ(UART1_IRQn);
4180_1 0:023c5cda6102 1463 while (rx_in == rx_out) {
4180_1 0:023c5cda6102 1464 }
tsunemoto 2:6fb0d2e32144 1465 // Start Critical Section - don't interrupt while changing global buffer variables
4180_1 0:023c5cda6102 1466 NVIC_DisableIRQ(UART1_IRQn);
4180_1 0:023c5cda6102 1467 }
4180_1 0:023c5cda6102 1468 rx_line[i] = rx_buffer[rx_out];
4180_1 0:023c5cda6102 1469 i++;
tsunemoto 2:6fb0d2e32144 1470 rx_out = (rx_out + 1) % ser_buffer_size;
4180_1 0:023c5cda6102 1471 }
4180_1 0:023c5cda6102 1472 rx_line[i-1] = 0;
4180_1 0:023c5cda6102 1473 // End Critical Section
4180_1 0:023c5cda6102 1474 NVIC_EnableIRQ(UART1_IRQn);
tsunemoto 2:6fb0d2e32144 1475 return(i);
4180_1 0:023c5cda6102 1476 }
4180_1 0:023c5cda6102 1477
4180_1 0:023c5cda6102 1478 // Interupt Routine to read in data from serial port
4180_1 0:023c5cda6102 1479 void Rx_interrupt() {
tsunemoto 2:6fb0d2e32144 1480 //led1=1;
4180_1 0:023c5cda6102 1481 // Loop just in case more than one character is in UART's receive FIFO buffer
4180_1 0:023c5cda6102 1482 // Stop if buffer full
tsunemoto 2:6fb0d2e32144 1483 while ((device.readable()) || (((rx_in + 1) % ser_buffer_size) == rx_out)) {
4180_1 0:023c5cda6102 1484 rx_buffer[rx_in] = device.getc();
4180_1 0:023c5cda6102 1485 // Uncomment to Echo to USB serial to watch data flow
4180_1 0:023c5cda6102 1486 // monitor_device.putc(rx_buffer[rx_in]);
tsunemoto 2:6fb0d2e32144 1487 //------- 2013.08.08 Tsunemoto ------------//
tsunemoto 2:6fb0d2e32144 1488 // -- Char CR Rec Counter ----//
tsunemoto 2:6fb0d2e32144 1489 if(rx_buffer[rx_in]== '\r'){
tsunemoto 2:6fb0d2e32144 1490 //led2 = 1;
tsunemoto 2:6fb0d2e32144 1491 rx_cr_Rec ++;
tsunemoto 2:6fb0d2e32144 1492 }
tsunemoto 2:6fb0d2e32144 1493 //----------------------------//
tsunemoto 2:6fb0d2e32144 1494 rx_in = (rx_in + 1) % ser_buffer_size;
4180_1 0:023c5cda6102 1495 }
tsunemoto 2:6fb0d2e32144 1496 //led1=0;
4180_1 0:023c5cda6102 1497 return;
4180_1 0:023c5cda6102 1498 }
4180_1 0:023c5cda6102 1499
4180_1 0:023c5cda6102 1500 // Interupt Routine to write out data to serial port
4180_1 0:023c5cda6102 1501 void Tx_interrupt() {
tsunemoto 2:6fb0d2e32144 1502 //led2=1;
4180_1 0:023c5cda6102 1503 // Loop to fill more than one character in UART's transmit FIFO buffer
4180_1 0:023c5cda6102 1504 // Stop if buffer empty
4180_1 0:023c5cda6102 1505 while ((device.writeable()) && (tx_in != tx_out)) {
4180_1 0:023c5cda6102 1506 device.putc(tx_buffer[tx_out]);
tsunemoto 2:6fb0d2e32144 1507 tx_out = (tx_out + 1) % ser_buffer_size;
4180_1 0:023c5cda6102 1508 }
tsunemoto 2:6fb0d2e32144 1509 //led2=0;
4180_1 0:023c5cda6102 1510 return;
tsunemoto 2:6fb0d2e32144 1511 }
tsunemoto 2:6fb0d2e32144 1512 //----------------------------------------------------------------------------------//