shinichi nakazawa / mbed-src

mbed library sources

Dependents:   Nucleo_blink_led

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC408X/TARGET_LPC4088_DM/ethernet_api.c@462:e03396e14338, 2015-02-03 (annotated)

Committer:
mbed_official
Date:
Tue Feb 03 13:15:07 2015 +0000
Revision:
462:e03396e14338
Synchronized with git revision ae7e2e76ed57b9ca11dc05f51f097df1de144fe2



Full URL: https://github.com/mbedmicro/mbed/commit/ae7e2e76ed57b9ca11dc05f51f097df1de144fe2/



Add support for EA LPC4088_DM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 462:e03396e14338 1 /* mbed Microcontroller Library
mbed_official 462:e03396e14338 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 462:e03396e14338 3 *
mbed_official 462:e03396e14338 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 462:e03396e14338 5 * you may not use this file except in compliance with the License.
mbed_official 462:e03396e14338 6 * You may obtain a copy of the License at
mbed_official 462:e03396e14338 7 *
mbed_official 462:e03396e14338 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 462:e03396e14338 9 *
mbed_official 462:e03396e14338 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 462:e03396e14338 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 462:e03396e14338 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 462:e03396e14338 13 * See the License for the specific language governing permissions and
mbed_official 462:e03396e14338 14 * limitations under the License.
mbed_official 462:e03396e14338 15 */
mbed_official 462:e03396e14338 16 #include <string.h>
mbed_official 462:e03396e14338 17
mbed_official 462:e03396e14338 18 #include "ethernet_api.h"
mbed_official 462:e03396e14338 19 #include "cmsis.h"
mbed_official 462:e03396e14338 20 #include "mbed_interface.h"
mbed_official 462:e03396e14338 21 #include "toolchain.h"
mbed_official 462:e03396e14338 22 #include "mbed_error.h"
mbed_official 462:e03396e14338 23
mbed_official 462:e03396e14338 24 #define NEW_LOGIC 0
mbed_official 462:e03396e14338 25 #define NEW_ETH_BUFFER 0
mbed_official 462:e03396e14338 26
mbed_official 462:e03396e14338 27 #if NEW_ETH_BUFFER
mbed_official 462:e03396e14338 28
mbed_official 462:e03396e14338 29 #define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
mbed_official 462:e03396e14338 30 #define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
mbed_official 462:e03396e14338 31
mbed_official 462:e03396e14338 32 #define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
mbed_official 462:e03396e14338 33 #define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
mbed_official 462:e03396e14338 34
mbed_official 462:e03396e14338 35 #else
mbed_official 462:e03396e14338 36
mbed_official 462:e03396e14338 37 // Memfree calculation:
mbed_official 462:e03396e14338 38 // (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
mbed_official 462:e03396e14338 39 // (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
mbed_official 462:e03396e14338 40 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
mbed_official 462:e03396e14338 41 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
mbed_official 462:e03396e14338 42 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
mbed_official 462:e03396e14338 43 //#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
mbed_official 462:e03396e14338 44
mbed_official 462:e03396e14338 45 //#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
mbed_official 462:e03396e14338 46 #define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
mbed_official 462:e03396e14338 47 #define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
mbed_official 462:e03396e14338 48
mbed_official 462:e03396e14338 49 const int ethernet_MTU_SIZE = 0x300;
mbed_official 462:e03396e14338 50
mbed_official 462:e03396e14338 51 #endif
mbed_official 462:e03396e14338 52
mbed_official 462:e03396e14338 53 #define ETHERNET_ADDR_SIZE 6
mbed_official 462:e03396e14338 54
mbed_official 462:e03396e14338 55 PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
mbed_official 462:e03396e14338 56 unsigned int Packet;
mbed_official 462:e03396e14338 57 unsigned int Ctrl;
mbed_official 462:e03396e14338 58 };
mbed_official 462:e03396e14338 59 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
mbed_official 462:e03396e14338 60
mbed_official 462:e03396e14338 61 PACKED struct RX_STAT_TypeDef { /* RX Status struct */
mbed_official 462:e03396e14338 62 unsigned int Info;
mbed_official 462:e03396e14338 63 unsigned int HashCRC;
mbed_official 462:e03396e14338 64 };
mbed_official 462:e03396e14338 65 typedef struct RX_STAT_TypeDef RX_STAT_TypeDef;
mbed_official 462:e03396e14338 66
mbed_official 462:e03396e14338 67 PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
mbed_official 462:e03396e14338 68 unsigned int Packet;
mbed_official 462:e03396e14338 69 unsigned int Ctrl;
mbed_official 462:e03396e14338 70 };
mbed_official 462:e03396e14338 71 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
mbed_official 462:e03396e14338 72
mbed_official 462:e03396e14338 73 PACKED struct TX_STAT_TypeDef { /* TX Status struct */
mbed_official 462:e03396e14338 74 unsigned int Info;
mbed_official 462:e03396e14338 75 };
mbed_official 462:e03396e14338 76 typedef struct TX_STAT_TypeDef TX_STAT_TypeDef;
mbed_official 462:e03396e14338 77
mbed_official 462:e03396e14338 78 /* MAC Configuration Register 1 */
mbed_official 462:e03396e14338 79 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
mbed_official 462:e03396e14338 80 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
mbed_official 462:e03396e14338 81 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
mbed_official 462:e03396e14338 82 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
mbed_official 462:e03396e14338 83 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
mbed_official 462:e03396e14338 84 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
mbed_official 462:e03396e14338 85 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
mbed_official 462:e03396e14338 86 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
mbed_official 462:e03396e14338 87 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
mbed_official 462:e03396e14338 88 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
mbed_official 462:e03396e14338 89 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
mbed_official 462:e03396e14338 90
mbed_official 462:e03396e14338 91 /* MAC Configuration Register 2 */
mbed_official 462:e03396e14338 92 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
mbed_official 462:e03396e14338 93 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
mbed_official 462:e03396e14338 94 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
mbed_official 462:e03396e14338 95 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
mbed_official 462:e03396e14338 96 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
mbed_official 462:e03396e14338 97 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
mbed_official 462:e03396e14338 98 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
mbed_official 462:e03396e14338 99 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
mbed_official 462:e03396e14338 100 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
mbed_official 462:e03396e14338 101 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
mbed_official 462:e03396e14338 102 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
mbed_official 462:e03396e14338 103 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
mbed_official 462:e03396e14338 104 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
mbed_official 462:e03396e14338 105
mbed_official 462:e03396e14338 106 /* Back-to-Back Inter-Packet-Gap Register */
mbed_official 462:e03396e14338 107 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
mbed_official 462:e03396e14338 108 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
mbed_official 462:e03396e14338 109
mbed_official 462:e03396e14338 110 /* Non Back-to-Back Inter-Packet-Gap Register */
mbed_official 462:e03396e14338 111 #define IPGR_DEF 0x00000012 /* Recommended value */
mbed_official 462:e03396e14338 112
mbed_official 462:e03396e14338 113 /* Collision Window/Retry Register */
mbed_official 462:e03396e14338 114 #define CLRT_DEF 0x0000370F /* Default value */
mbed_official 462:e03396e14338 115
mbed_official 462:e03396e14338 116 /* PHY Support Register */
mbed_official 462:e03396e14338 117 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
mbed_official 462:e03396e14338 118 //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
mbed_official 462:e03396e14338 119 #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
mbed_official 462:e03396e14338 120
mbed_official 462:e03396e14338 121 /* Test Register */
mbed_official 462:e03396e14338 122 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
mbed_official 462:e03396e14338 123 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
mbed_official 462:e03396e14338 124 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
mbed_official 462:e03396e14338 125
mbed_official 462:e03396e14338 126 /* MII Management Configuration Register */
mbed_official 462:e03396e14338 127 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
mbed_official 462:e03396e14338 128 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
mbed_official 462:e03396e14338 129 #define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */
mbed_official 462:e03396e14338 130 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
mbed_official 462:e03396e14338 131
mbed_official 462:e03396e14338 132 /* MII Management Command Register */
mbed_official 462:e03396e14338 133 #define MCMD_READ 0x00000001 /* MII Read */
mbed_official 462:e03396e14338 134 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
mbed_official 462:e03396e14338 135
mbed_official 462:e03396e14338 136 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
mbed_official 462:e03396e14338 137 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
mbed_official 462:e03396e14338 138
mbed_official 462:e03396e14338 139 /* MII Management Address Register */
mbed_official 462:e03396e14338 140 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
mbed_official 462:e03396e14338 141 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
mbed_official 462:e03396e14338 142
mbed_official 462:e03396e14338 143 /* MII Management Indicators Register */
mbed_official 462:e03396e14338 144 #define MIND_BUSY 0x00000001 /* MII is Busy */
mbed_official 462:e03396e14338 145 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
mbed_official 462:e03396e14338 146 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
mbed_official 462:e03396e14338 147 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
mbed_official 462:e03396e14338 148
mbed_official 462:e03396e14338 149 /* Command Register */
mbed_official 462:e03396e14338 150 #define CR_RX_EN 0x00000001 /* Enable Receive */
mbed_official 462:e03396e14338 151 #define CR_TX_EN 0x00000002 /* Enable Transmit */
mbed_official 462:e03396e14338 152 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
mbed_official 462:e03396e14338 153 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
mbed_official 462:e03396e14338 154 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
mbed_official 462:e03396e14338 155 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
mbed_official 462:e03396e14338 156 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
mbed_official 462:e03396e14338 157 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
mbed_official 462:e03396e14338 158 #define CR_RMII 0x00000200 /* Reduced MII Interface */
mbed_official 462:e03396e14338 159 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
mbed_official 462:e03396e14338 160
mbed_official 462:e03396e14338 161 /* Status Register */
mbed_official 462:e03396e14338 162 #define SR_RX_EN 0x00000001 /* Enable Receive */
mbed_official 462:e03396e14338 163 #define SR_TX_EN 0x00000002 /* Enable Transmit */
mbed_official 462:e03396e14338 164
mbed_official 462:e03396e14338 165 /* Transmit Status Vector 0 Register */
mbed_official 462:e03396e14338 166 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
mbed_official 462:e03396e14338 167 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
mbed_official 462:e03396e14338 168 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
mbed_official 462:e03396e14338 169 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
mbed_official 462:e03396e14338 170 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
mbed_official 462:e03396e14338 171 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
mbed_official 462:e03396e14338 172 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
mbed_official 462:e03396e14338 173 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
mbed_official 462:e03396e14338 174 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
mbed_official 462:e03396e14338 175 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
mbed_official 462:e03396e14338 176 #define TSV0_GIANT 0x00000400 /* Giant Frame */
mbed_official 462:e03396e14338 177 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
mbed_official 462:e03396e14338 178 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
mbed_official 462:e03396e14338 179 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
mbed_official 462:e03396e14338 180 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
mbed_official 462:e03396e14338 181 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
mbed_official 462:e03396e14338 182 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
mbed_official 462:e03396e14338 183
mbed_official 462:e03396e14338 184 /* Transmit Status Vector 1 Register */
mbed_official 462:e03396e14338 185 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
mbed_official 462:e03396e14338 186 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
mbed_official 462:e03396e14338 187
mbed_official 462:e03396e14338 188 /* Receive Status Vector Register */
mbed_official 462:e03396e14338 189 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
mbed_official 462:e03396e14338 190 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
mbed_official 462:e03396e14338 191 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
mbed_official 462:e03396e14338 192 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
mbed_official 462:e03396e14338 193 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
mbed_official 462:e03396e14338 194 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
mbed_official 462:e03396e14338 195 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
mbed_official 462:e03396e14338 196 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
mbed_official 462:e03396e14338 197 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
mbed_official 462:e03396e14338 198 #define RSV_MCAST 0x01000000 /* Multicast Frame */
mbed_official 462:e03396e14338 199 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
mbed_official 462:e03396e14338 200 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
mbed_official 462:e03396e14338 201 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
mbed_official 462:e03396e14338 202 #define RSV_PAUSE 0x10000000 /* Pause Frame */
mbed_official 462:e03396e14338 203 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
mbed_official 462:e03396e14338 204 #define RSV_VLAN 0x40000000 /* VLAN Frame */
mbed_official 462:e03396e14338 205
mbed_official 462:e03396e14338 206 /* Flow Control Counter Register */
mbed_official 462:e03396e14338 207 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
mbed_official 462:e03396e14338 208 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
mbed_official 462:e03396e14338 209
mbed_official 462:e03396e14338 210 /* Flow Control Status Register */
mbed_official 462:e03396e14338 211 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
mbed_official 462:e03396e14338 212
mbed_official 462:e03396e14338 213 /* Receive Filter Control Register */
mbed_official 462:e03396e14338 214 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
mbed_official 462:e03396e14338 215 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
mbed_official 462:e03396e14338 216 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
mbed_official 462:e03396e14338 217 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
mbed_official 462:e03396e14338 218 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
mbed_official 462:e03396e14338 219 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
mbed_official 462:e03396e14338 220 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
mbed_official 462:e03396e14338 221 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
mbed_official 462:e03396e14338 222
mbed_official 462:e03396e14338 223 /* Receive Filter WoL Status/Clear Registers */
mbed_official 462:e03396e14338 224 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
mbed_official 462:e03396e14338 225 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
mbed_official 462:e03396e14338 226 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
mbed_official 462:e03396e14338 227 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
mbed_official 462:e03396e14338 228 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
mbed_official 462:e03396e14338 229 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
mbed_official 462:e03396e14338 230 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
mbed_official 462:e03396e14338 231 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
mbed_official 462:e03396e14338 232
mbed_official 462:e03396e14338 233 /* Interrupt Status/Enable/Clear/Set Registers */
mbed_official 462:e03396e14338 234 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
mbed_official 462:e03396e14338 235 #define INT_RX_ERR 0x00000002 /* Receive Error */
mbed_official 462:e03396e14338 236 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
mbed_official 462:e03396e14338 237 #define INT_RX_DONE 0x00000008 /* Receive Done */
mbed_official 462:e03396e14338 238 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
mbed_official 462:e03396e14338 239 #define INT_TX_ERR 0x00000020 /* Transmit Error */
mbed_official 462:e03396e14338 240 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
mbed_official 462:e03396e14338 241 #define INT_TX_DONE 0x00000080 /* Transmit Done */
mbed_official 462:e03396e14338 242 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
mbed_official 462:e03396e14338 243 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
mbed_official 462:e03396e14338 244
mbed_official 462:e03396e14338 245 /* Power Down Register */
mbed_official 462:e03396e14338 246 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
mbed_official 462:e03396e14338 247
mbed_official 462:e03396e14338 248 /* RX Descriptor Control Word */
mbed_official 462:e03396e14338 249 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
mbed_official 462:e03396e14338 250 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
mbed_official 462:e03396e14338 251
mbed_official 462:e03396e14338 252 /* RX Status Hash CRC Word */
mbed_official 462:e03396e14338 253 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
mbed_official 462:e03396e14338 254 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
mbed_official 462:e03396e14338 255
mbed_official 462:e03396e14338 256 /* RX Status Information Word */
mbed_official 462:e03396e14338 257 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
mbed_official 462:e03396e14338 258 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
mbed_official 462:e03396e14338 259 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
mbed_official 462:e03396e14338 260 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
mbed_official 462:e03396e14338 261 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
mbed_official 462:e03396e14338 262 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
mbed_official 462:e03396e14338 263 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
mbed_official 462:e03396e14338 264 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
mbed_official 462:e03396e14338 265 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
mbed_official 462:e03396e14338 266 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
mbed_official 462:e03396e14338 267 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
mbed_official 462:e03396e14338 268 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
mbed_official 462:e03396e14338 269 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
mbed_official 462:e03396e14338 270 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
mbed_official 462:e03396e14338 271 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
mbed_official 462:e03396e14338 272
mbed_official 462:e03396e14338 273 //#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
mbed_official 462:e03396e14338 274 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_SYM_ERR | \
mbed_official 462:e03396e14338 275 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
mbed_official 462:e03396e14338 276
mbed_official 462:e03396e14338 277
mbed_official 462:e03396e14338 278 /* TX Descriptor Control Word */
mbed_official 462:e03396e14338 279 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
mbed_official 462:e03396e14338 280 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
mbed_official 462:e03396e14338 281 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
mbed_official 462:e03396e14338 282 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
mbed_official 462:e03396e14338 283 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
mbed_official 462:e03396e14338 284 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
mbed_official 462:e03396e14338 285 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
mbed_official 462:e03396e14338 286
mbed_official 462:e03396e14338 287 /* TX Status Information Word */
mbed_official 462:e03396e14338 288 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
mbed_official 462:e03396e14338 289 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
mbed_official 462:e03396e14338 290 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
mbed_official 462:e03396e14338 291 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
mbed_official 462:e03396e14338 292 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
mbed_official 462:e03396e14338 293 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
mbed_official 462:e03396e14338 294 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
mbed_official 462:e03396e14338 295 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
mbed_official 462:e03396e14338 296
mbed_official 462:e03396e14338 297 /* ENET Device Revision ID */
mbed_official 462:e03396e14338 298 #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
mbed_official 462:e03396e14338 299
mbed_official 462:e03396e14338 300 /* DP83848C PHY Registers */
mbed_official 462:e03396e14338 301 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
mbed_official 462:e03396e14338 302 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
mbed_official 462:e03396e14338 303 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
mbed_official 462:e03396e14338 304 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
mbed_official 462:e03396e14338 305 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
mbed_official 462:e03396e14338 306 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
mbed_official 462:e03396e14338 307 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
mbed_official 462:e03396e14338 308 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
mbed_official 462:e03396e14338 309
mbed_official 462:e03396e14338 310 /* PHY Extended Registers */
mbed_official 462:e03396e14338 311 #define PHY_REG_STS 0x10 /* Status Register */
mbed_official 462:e03396e14338 312 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
mbed_official 462:e03396e14338 313 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
mbed_official 462:e03396e14338 314 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
mbed_official 462:e03396e14338 315 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
mbed_official 462:e03396e14338 316 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
mbed_official 462:e03396e14338 317 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
mbed_official 462:e03396e14338 318 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
mbed_official 462:e03396e14338 319 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
mbed_official 462:e03396e14338 320 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
mbed_official 462:e03396e14338 321 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
mbed_official 462:e03396e14338 322 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
mbed_official 462:e03396e14338 323
mbed_official 462:e03396e14338 324 #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
mbed_official 462:e03396e14338 325
mbed_official 462:e03396e14338 326 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
mbed_official 462:e03396e14338 327 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
mbed_official 462:e03396e14338 328 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
mbed_official 462:e03396e14338 329 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
mbed_official 462:e03396e14338 330 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
mbed_official 462:e03396e14338 331
mbed_official 462:e03396e14338 332 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
mbed_official 462:e03396e14338 333 #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
mbed_official 462:e03396e14338 334
mbed_official 462:e03396e14338 335 #define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
mbed_official 462:e03396e14338 336
mbed_official 462:e03396e14338 337 #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
mbed_official 462:e03396e14338 338 #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
mbed_official 462:e03396e14338 339 #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
mbed_official 462:e03396e14338 340
mbed_official 462:e03396e14338 341 #define PHY_BMCR_RESET 0x8000 /* PHY Reset */
mbed_official 462:e03396e14338 342
mbed_official 462:e03396e14338 343 #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
mbed_official 462:e03396e14338 344
mbed_official 462:e03396e14338 345 #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
mbed_official 462:e03396e14338 346 #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
mbed_official 462:e03396e14338 347
mbed_official 462:e03396e14338 348
mbed_official 462:e03396e14338 349 static int phy_read(unsigned int PhyReg);
mbed_official 462:e03396e14338 350 static int phy_write(unsigned int PhyReg, unsigned short Data);
mbed_official 462:e03396e14338 351
mbed_official 462:e03396e14338 352 static void txdscr_init(void);
mbed_official 462:e03396e14338 353 static void rxdscr_init(void);
mbed_official 462:e03396e14338 354
mbed_official 462:e03396e14338 355 #if defined (__ICCARM__)
mbed_official 462:e03396e14338 356 # define AHBSRAM1
mbed_official 462:e03396e14338 357 #elif defined(TOOLCHAIN_GCC_CR)
mbed_official 462:e03396e14338 358 # define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
mbed_official 462:e03396e14338 359 #else
mbed_official 462:e03396e14338 360 # define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
mbed_official 462:e03396e14338 361 #endif
mbed_official 462:e03396e14338 362
mbed_official 462:e03396e14338 363 AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
mbed_official 462:e03396e14338 364 AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
mbed_official 462:e03396e14338 365 AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
mbed_official 462:e03396e14338 366 AHBSRAM1 volatile RX_STAT_TypeDef rxstat[NUM_RX_FRAG];
mbed_official 462:e03396e14338 367 AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
mbed_official 462:e03396e14338 368 AHBSRAM1 volatile TX_STAT_TypeDef txstat[NUM_TX_FRAG];
mbed_official 462:e03396e14338 369
mbed_official 462:e03396e14338 370
mbed_official 462:e03396e14338 371 #if NEW_LOGIC
mbed_official 462:e03396e14338 372 static int rx_consume_offset = -1;
mbed_official 462:e03396e14338 373 static int tx_produce_offset = -1;
mbed_official 462:e03396e14338 374 #else
mbed_official 462:e03396e14338 375 static int send_doff = 0;
mbed_official 462:e03396e14338 376 static int send_idx = -1;
mbed_official 462:e03396e14338 377 static int send_size = 0;
mbed_official 462:e03396e14338 378
mbed_official 462:e03396e14338 379 static int receive_soff = 0;
mbed_official 462:e03396e14338 380 static int receive_idx = -1;
mbed_official 462:e03396e14338 381 #endif
mbed_official 462:e03396e14338 382
mbed_official 462:e03396e14338 383 static uint32_t phy_id = 0;
mbed_official 462:e03396e14338 384
mbed_official 462:e03396e14338 385 static inline int rinc(int idx, int mod) {
mbed_official 462:e03396e14338 386 ++idx;
mbed_official 462:e03396e14338 387 idx %= mod;
mbed_official 462:e03396e14338 388 return idx;
mbed_official 462:e03396e14338 389 }
mbed_official 462:e03396e14338 390
mbed_official 462:e03396e14338 391 //extern unsigned int SystemFrequency;
mbed_official 462:e03396e14338 392 static inline unsigned int clockselect() {
mbed_official 462:e03396e14338 393 if(SystemCoreClock < 10000000) {
mbed_official 462:e03396e14338 394 return 1;
mbed_official 462:e03396e14338 395 } else if(SystemCoreClock < 15000000) {
mbed_official 462:e03396e14338 396 return 2;
mbed_official 462:e03396e14338 397 } else if(SystemCoreClock < 20000000) {
mbed_official 462:e03396e14338 398 return 3;
mbed_official 462:e03396e14338 399 } else if(SystemCoreClock < 25000000) {
mbed_official 462:e03396e14338 400 return 4;
mbed_official 462:e03396e14338 401 } else if(SystemCoreClock < 35000000) {
mbed_official 462:e03396e14338 402 return 5;
mbed_official 462:e03396e14338 403 } else if(SystemCoreClock < 50000000) {
mbed_official 462:e03396e14338 404 return 6;
mbed_official 462:e03396e14338 405 } else if(SystemCoreClock < 70000000) {
mbed_official 462:e03396e14338 406 return 7;
mbed_official 462:e03396e14338 407 } else if(SystemCoreClock < 80000000) {
mbed_official 462:e03396e14338 408 return 8;
mbed_official 462:e03396e14338 409 } else if(SystemCoreClock < 90000000) {
mbed_official 462:e03396e14338 410 return 9;
mbed_official 462:e03396e14338 411 } else if(SystemCoreClock < 100000000) {
mbed_official 462:e03396e14338 412 return 10;
mbed_official 462:e03396e14338 413 } else if(SystemCoreClock < 120000000) {
mbed_official 462:e03396e14338 414 return 11;
mbed_official 462:e03396e14338 415 } else if(SystemCoreClock < 130000000) {
mbed_official 462:e03396e14338 416 return 12;
mbed_official 462:e03396e14338 417 } else if(SystemCoreClock < 140000000) {
mbed_official 462:e03396e14338 418 return 13;
mbed_official 462:e03396e14338 419 } else if(SystemCoreClock < 150000000) {
mbed_official 462:e03396e14338 420 return 15;
mbed_official 462:e03396e14338 421 } else if(SystemCoreClock < 160000000) {
mbed_official 462:e03396e14338 422 return 16;
mbed_official 462:e03396e14338 423 } else {
mbed_official 462:e03396e14338 424 return 0;
mbed_official 462:e03396e14338 425 }
mbed_official 462:e03396e14338 426 }
mbed_official 462:e03396e14338 427
mbed_official 462:e03396e14338 428 #ifndef min
mbed_official 462:e03396e14338 429 #define min(x, y) (((x)<(y))?(x):(y))
mbed_official 462:e03396e14338 430 #endif
mbed_official 462:e03396e14338 431
mbed_official 462:e03396e14338 432 /*----------------------------------------------------------------------------
mbed_official 462:e03396e14338 433 Ethernet Device initialize
mbed_official 462:e03396e14338 434 *----------------------------------------------------------------------------*/
mbed_official 462:e03396e14338 435 int ethernet_init() {
mbed_official 462:e03396e14338 436 int regv, tout;
mbed_official 462:e03396e14338 437 char mac[ETHERNET_ADDR_SIZE];
mbed_official 462:e03396e14338 438 unsigned int clock = clockselect();
mbed_official 462:e03396e14338 439
mbed_official 462:e03396e14338 440 LPC_SC->PCONP |= 0x40000000; /* Power Up the EMAC controller. */
mbed_official 462:e03396e14338 441
mbed_official 462:e03396e14338 442 LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
mbed_official 462:e03396e14338 443 LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */
mbed_official 462:e03396e14338 444 LPC_IOCON->P1_1 &= ~0x07;
mbed_official 462:e03396e14338 445 LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */
mbed_official 462:e03396e14338 446 LPC_IOCON->P1_4 &= ~0x07;
mbed_official 462:e03396e14338 447 LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */
mbed_official 462:e03396e14338 448 LPC_IOCON->P1_8 &= ~0x07;
mbed_official 462:e03396e14338 449 LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */
mbed_official 462:e03396e14338 450 LPC_IOCON->P1_9 &= ~0x07;
mbed_official 462:e03396e14338 451 LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */
mbed_official 462:e03396e14338 452 LPC_IOCON->P1_10 &= ~0x07;
mbed_official 462:e03396e14338 453 LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */
mbed_official 462:e03396e14338 454 LPC_IOCON->P1_14 &= ~0x07;
mbed_official 462:e03396e14338 455 LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */
mbed_official 462:e03396e14338 456 LPC_IOCON->P1_15 &= ~0x07;
mbed_official 462:e03396e14338 457 LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */
mbed_official 462:e03396e14338 458 LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
mbed_official 462:e03396e14338 459 LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */
mbed_official 462:e03396e14338 460 LPC_IOCON->P1_17 &= ~0x07;
mbed_official 462:e03396e14338 461 LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */
mbed_official 462:e03396e14338 462
mbed_official 462:e03396e14338 463 /* Reset all EMAC internal modules. */
mbed_official 462:e03396e14338 464 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX |
mbed_official 462:e03396e14338 465 MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES;
mbed_official 462:e03396e14338 466 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM;
mbed_official 462:e03396e14338 467
mbed_official 462:e03396e14338 468 for(tout = 100; tout; tout--) __NOP(); /* A short delay after reset. */
mbed_official 462:e03396e14338 469
mbed_official 462:e03396e14338 470 LPC_EMAC->MAC1 = MAC1_PASS_ALL; /* Initialize MAC control registers. */
mbed_official 462:e03396e14338 471 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
mbed_official 462:e03396e14338 472 LPC_EMAC->MAXF = ETH_MAX_FLEN;
mbed_official 462:e03396e14338 473 LPC_EMAC->CLRT = CLRT_DEF;
mbed_official 462:e03396e14338 474 LPC_EMAC->IPGR = IPGR_DEF;
mbed_official 462:e03396e14338 475
mbed_official 462:e03396e14338 476 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM; /* Enable Reduced MII interface. */
mbed_official 462:e03396e14338 477
mbed_official 462:e03396e14338 478 LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL; /* Set clock */
mbed_official 462:e03396e14338 479 LPC_EMAC->MCFG |= MCFG_RES_MII; /* and reset */
mbed_official 462:e03396e14338 480
mbed_official 462:e03396e14338 481 for(tout = 100; tout; tout--) __NOP(); /* A short delay */
mbed_official 462:e03396e14338 482
mbed_official 462:e03396e14338 483 LPC_EMAC->MCFG = (clock << 0x2) & MCFG_CLK_SEL;
mbed_official 462:e03396e14338 484 LPC_EMAC->MCMD = 0;
mbed_official 462:e03396e14338 485
mbed_official 462:e03396e14338 486 LPC_EMAC->SUPP = SUPP_RES_RMII; /* Reset Reduced MII Logic. */
mbed_official 462:e03396e14338 487
mbed_official 462:e03396e14338 488 for (tout = 100; tout; tout--) __NOP(); /* A short delay */
mbed_official 462:e03396e14338 489
mbed_official 462:e03396e14338 490 LPC_EMAC->SUPP = 0;
mbed_official 462:e03396e14338 491
mbed_official 462:e03396e14338 492 phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
mbed_official 462:e03396e14338 493 for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
mbed_official 462:e03396e14338 494 regv = phy_read(PHY_REG_BMCR);
mbed_official 462:e03396e14338 495 if(regv < 0 || tout == 0) {
mbed_official 462:e03396e14338 496 return -1; /* Error */
mbed_official 462:e03396e14338 497 }
mbed_official 462:e03396e14338 498 if(!(regv & PHY_BMCR_RESET)) {
mbed_official 462:e03396e14338 499 break; /* Reset complete. */
mbed_official 462:e03396e14338 500 }
mbed_official 462:e03396e14338 501 }
mbed_official 462:e03396e14338 502
mbed_official 462:e03396e14338 503 phy_id = (phy_read(PHY_REG_IDR1) << 16);
mbed_official 462:e03396e14338 504 phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
mbed_official 462:e03396e14338 505
mbed_official 462:e03396e14338 506 if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
mbed_official 462:e03396e14338 507 error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
mbed_official 462:e03396e14338 508 }
mbed_official 462:e03396e14338 509
mbed_official 462:e03396e14338 510 ethernet_set_link(-1, 0);
mbed_official 462:e03396e14338 511
mbed_official 462:e03396e14338 512 /* Set the Ethernet MAC Address registers */
mbed_official 462:e03396e14338 513 ethernet_address(mac);
mbed_official 462:e03396e14338 514 LPC_EMAC->SA0 = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4];
mbed_official 462:e03396e14338 515 LPC_EMAC->SA1 = ((uint32_t)mac[3] << 8) | (uint32_t)mac[2];
mbed_official 462:e03396e14338 516 LPC_EMAC->SA2 = ((uint32_t)mac[1] << 8) | (uint32_t)mac[0];
mbed_official 462:e03396e14338 517
mbed_official 462:e03396e14338 518 txdscr_init(); /* initialize DMA TX Descriptor */
mbed_official 462:e03396e14338 519 rxdscr_init(); /* initialize DMA RX Descriptor */
mbed_official 462:e03396e14338 520
mbed_official 462:e03396e14338 521 LPC_EMAC->RxFilterCtrl = RFC_UCAST_EN | RFC_MCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN;
mbed_official 462:e03396e14338 522 /* Receive Broadcast, Perfect Match Packets */
mbed_official 462:e03396e14338 523
mbed_official 462:e03396e14338 524 LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE; /* Enable EMAC interrupts. */
mbed_official 462:e03396e14338 525 LPC_EMAC->IntClear = 0xFFFF; /* Reset all interrupts */
mbed_official 462:e03396e14338 526
mbed_official 462:e03396e14338 527 LPC_EMAC->Command |= (CR_RX_EN | CR_TX_EN); /* Enable receive and transmit mode of MAC Ethernet core */
mbed_official 462:e03396e14338 528 LPC_EMAC->MAC1 |= MAC1_REC_EN;
mbed_official 462:e03396e14338 529
mbed_official 462:e03396e14338 530 #if NEW_LOGIC
mbed_official 462:e03396e14338 531 rx_consume_offset = -1;
mbed_official 462:e03396e14338 532 tx_produce_offset = -1;
mbed_official 462:e03396e14338 533 #else
mbed_official 462:e03396e14338 534 send_doff = 0;
mbed_official 462:e03396e14338 535 send_idx = -1;
mbed_official 462:e03396e14338 536 send_size = 0;
mbed_official 462:e03396e14338 537
mbed_official 462:e03396e14338 538 receive_soff = 0;
mbed_official 462:e03396e14338 539 receive_idx = -1;
mbed_official 462:e03396e14338 540 #endif
mbed_official 462:e03396e14338 541
mbed_official 462:e03396e14338 542 return 0;
mbed_official 462:e03396e14338 543 }
mbed_official 462:e03396e14338 544
mbed_official 462:e03396e14338 545 /*----------------------------------------------------------------------------
mbed_official 462:e03396e14338 546 Ethernet Device Uninitialize
mbed_official 462:e03396e14338 547 *----------------------------------------------------------------------------*/
mbed_official 462:e03396e14338 548 void ethernet_free() {
mbed_official 462:e03396e14338 549 LPC_EMAC->IntEnable &= ~(INT_RX_DONE | INT_TX_DONE);
mbed_official 462:e03396e14338 550 LPC_EMAC->IntClear = 0xFFFF;
mbed_official 462:e03396e14338 551
mbed_official 462:e03396e14338 552 LPC_SC->PCONP &= ~0x40000000; /* Power down the EMAC controller. */
mbed_official 462:e03396e14338 553
mbed_official 462:e03396e14338 554 LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
mbed_official 462:e03396e14338 555 LPC_IOCON->P1_1 &= ~0x07;
mbed_official 462:e03396e14338 556 LPC_IOCON->P1_4 &= ~0x07;
mbed_official 462:e03396e14338 557 LPC_IOCON->P1_8 &= ~0x07;
mbed_official 462:e03396e14338 558 LPC_IOCON->P1_9 &= ~0x07;
mbed_official 462:e03396e14338 559 LPC_IOCON->P1_10 &= ~0x07;
mbed_official 462:e03396e14338 560 LPC_IOCON->P1_14 &= ~0x07;
mbed_official 462:e03396e14338 561 LPC_IOCON->P1_15 &= ~0x07;
mbed_official 462:e03396e14338 562 LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
mbed_official 462:e03396e14338 563 LPC_IOCON->P1_17 &= ~0x07;
mbed_official 462:e03396e14338 564 }
mbed_official 462:e03396e14338 565
mbed_official 462:e03396e14338 566 // if(TxProduceIndex == TxConsumeIndex) buffer array is empty
mbed_official 462:e03396e14338 567 // if(TxProduceIndex == TxConsumeIndex - 1) buffer is full, should not fill
mbed_official 462:e03396e14338 568 // TxProduceIndex - The buffer that will/is being fileld by driver, s/w increment
mbed_official 462:e03396e14338 569 // TxConsumeIndex - The buffer that will/is beign sent by hardware
mbed_official 462:e03396e14338 570
mbed_official 462:e03396e14338 571 int ethernet_write(const char *data, int slen) {
mbed_official 462:e03396e14338 572
mbed_official 462:e03396e14338 573 #if NEW_LOGIC
mbed_official 462:e03396e14338 574
mbed_official 462:e03396e14338 575 if(tx_produce_offset < 0) { // mark as active if not already
mbed_official 462:e03396e14338 576 tx_produce_offset = 0;
mbed_official 462:e03396e14338 577 }
mbed_official 462:e03396e14338 578
mbed_official 462:e03396e14338 579 int index = LPC_EMAC->TxProduceIndex;
mbed_official 462:e03396e14338 580
mbed_official 462:e03396e14338 581 int remaining = ETH_MAX_FLEN - tx_produce_offset - 4; // bytes written plus checksum
mbed_official 462:e03396e14338 582 int requested = slen;
mbed_official 462:e03396e14338 583 int ncopy = min(remaining, requested);
mbed_official 462:e03396e14338 584
mbed_official 462:e03396e14338 585 void *pdst = (void *)(txdesc[index].Packet + tx_produce_offset);
mbed_official 462:e03396e14338 586 void *psrc = (void *)(data);
mbed_official 462:e03396e14338 587
mbed_official 462:e03396e14338 588 if(ncopy > 0 ){
mbed_official 462:e03396e14338 589 if(data != NULL) {
mbed_official 462:e03396e14338 590 memcpy(pdst, psrc, ncopy);
mbed_official 462:e03396e14338 591 } else {
mbed_official 462:e03396e14338 592 memset(pdst, 0, ncopy);
mbed_official 462:e03396e14338 593 }
mbed_official 462:e03396e14338 594 }
mbed_official 462:e03396e14338 595
mbed_official 462:e03396e14338 596 tx_produce_offset += ncopy;
mbed_official 462:e03396e14338 597
mbed_official 462:e03396e14338 598 return ncopy;
mbed_official 462:e03396e14338 599
mbed_official 462:e03396e14338 600 #else
mbed_official 462:e03396e14338 601 void *pdst, *psrc;
mbed_official 462:e03396e14338 602 const int dlen = ETH_FRAG_SIZE;
mbed_official 462:e03396e14338 603 int copy = 0;
mbed_official 462:e03396e14338 604 int soff = 0;
mbed_official 462:e03396e14338 605
mbed_official 462:e03396e14338 606 if(send_idx == -1) {
mbed_official 462:e03396e14338 607 send_idx = LPC_EMAC->TxProduceIndex;
mbed_official 462:e03396e14338 608 }
mbed_official 462:e03396e14338 609
mbed_official 462:e03396e14338 610 if(slen + send_doff > ethernet_MTU_SIZE) {
mbed_official 462:e03396e14338 611 return -1;
mbed_official 462:e03396e14338 612 }
mbed_official 462:e03396e14338 613
mbed_official 462:e03396e14338 614 do {
mbed_official 462:e03396e14338 615 copy = min(slen - soff, dlen - send_doff);
mbed_official 462:e03396e14338 616 pdst = (void *)(txdesc[send_idx].Packet + send_doff);
mbed_official 462:e03396e14338 617 psrc = (void *)(data + soff);
mbed_official 462:e03396e14338 618 if(send_doff + copy > ETH_FRAG_SIZE) {
mbed_official 462:e03396e14338 619 txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT);
mbed_official 462:e03396e14338 620 send_idx = rinc(send_idx, NUM_TX_FRAG);
mbed_official 462:e03396e14338 621 send_doff = 0;
mbed_official 462:e03396e14338 622 }
mbed_official 462:e03396e14338 623
mbed_official 462:e03396e14338 624 if(data != NULL) {
mbed_official 462:e03396e14338 625 memcpy(pdst, psrc, copy);
mbed_official 462:e03396e14338 626 } else {
mbed_official 462:e03396e14338 627 memset(pdst, 0, copy);
mbed_official 462:e03396e14338 628 }
mbed_official 462:e03396e14338 629
mbed_official 462:e03396e14338 630 soff += copy;
mbed_official 462:e03396e14338 631 send_doff += copy;
mbed_official 462:e03396e14338 632 send_size += copy;
mbed_official 462:e03396e14338 633 } while(soff != slen);
mbed_official 462:e03396e14338 634
mbed_official 462:e03396e14338 635 return soff;
mbed_official 462:e03396e14338 636 #endif
mbed_official 462:e03396e14338 637 }
mbed_official 462:e03396e14338 638
mbed_official 462:e03396e14338 639 int ethernet_send() {
mbed_official 462:e03396e14338 640
mbed_official 462:e03396e14338 641 #if NEW_LOGIC
mbed_official 462:e03396e14338 642 if(tx_produce_offset < 0) { // no buffer active
mbed_official 462:e03396e14338 643 return -1;
mbed_official 462:e03396e14338 644 }
mbed_official 462:e03396e14338 645
mbed_official 462:e03396e14338 646 // ensure there is a link
mbed_official 462:e03396e14338 647 if(!ethernet_link()) {
mbed_official 462:e03396e14338 648 return -2;
mbed_official 462:e03396e14338 649 }
mbed_official 462:e03396e14338 650
mbed_official 462:e03396e14338 651 // we have been writing in to a buffer, so finalise it
mbed_official 462:e03396e14338 652 int size = tx_produce_offset;
mbed_official 462:e03396e14338 653 int index = LPC_EMAC->TxProduceIndex;
mbed_official 462:e03396e14338 654 txdesc[index].Ctrl = (tx_produce_offset-1) | (TCTRL_INT | TCTRL_LAST);
mbed_official 462:e03396e14338 655
mbed_official 462:e03396e14338 656 // Increment ProduceIndex to allow it to be sent
mbed_official 462:e03396e14338 657 // We can only do this if the next slot is free
mbed_official 462:e03396e14338 658 int next = rinc(index, NUM_TX_FRAG);
mbed_official 462:e03396e14338 659 while(next == LPC_EMAC->TxConsumeIndex) {
mbed_official 462:e03396e14338 660 for(int i=0; i<1000; i++) { __NOP(); }
mbed_official 462:e03396e14338 661 }
mbed_official 462:e03396e14338 662
mbed_official 462:e03396e14338 663 LPC_EMAC->TxProduceIndex = next;
mbed_official 462:e03396e14338 664 tx_produce_offset = -1;
mbed_official 462:e03396e14338 665 return size;
mbed_official 462:e03396e14338 666
mbed_official 462:e03396e14338 667 #else
mbed_official 462:e03396e14338 668 int s = send_size;
mbed_official 462:e03396e14338 669 txdesc[send_idx].Ctrl = (send_doff-1) | (TCTRL_INT | TCTRL_LAST);
mbed_official 462:e03396e14338 670 send_idx = rinc(send_idx, NUM_TX_FRAG);
mbed_official 462:e03396e14338 671 LPC_EMAC->TxProduceIndex = send_idx;
mbed_official 462:e03396e14338 672 send_doff = 0;
mbed_official 462:e03396e14338 673 send_idx = -1;
mbed_official 462:e03396e14338 674 send_size = 0;
mbed_official 462:e03396e14338 675 return s;
mbed_official 462:e03396e14338 676 #endif
mbed_official 462:e03396e14338 677 }
mbed_official 462:e03396e14338 678
mbed_official 462:e03396e14338 679 // RxConsmeIndex - The index of buffer the driver will/is reading from. Driver should inc once read
mbed_official 462:e03396e14338 680 // RxProduceIndex - The index of buffer that will/is being filled by MAC. H/w will inc once rxd
mbed_official 462:e03396e14338 681 //
mbed_official 462:e03396e14338 682 // if(RxConsumeIndex == RxProduceIndex) buffer array is empty
mbed_official 462:e03396e14338 683 // if(RxConsumeIndex == RxProduceIndex + 1) buffer array is full
mbed_official 462:e03396e14338 684
mbed_official 462:e03396e14338 685 // Recevies an arrived ethernet packet.
mbed_official 462:e03396e14338 686 // Receiving an ethernet packet will drop the last received ethernet packet
mbed_official 462:e03396e14338 687 // and make a new ethernet packet ready to read.
mbed_official 462:e03396e14338 688 // Returns size of packet, else 0 if nothing to receive
mbed_official 462:e03396e14338 689
mbed_official 462:e03396e14338 690 // We read from RxConsumeIndex from position rx_consume_offset
mbed_official 462:e03396e14338 691 // if rx_consume_offset < 0, then we have not recieved the RxConsumeIndex packet for reading
mbed_official 462:e03396e14338 692 // rx_consume_offset = -1 // no frame
mbed_official 462:e03396e14338 693 // rx_consume_offset = 0 // start of frame
mbed_official 462:e03396e14338 694 // Assumption: A fragment should alway be a whole frame
mbed_official 462:e03396e14338 695
mbed_official 462:e03396e14338 696 int ethernet_receive() {
mbed_official 462:e03396e14338 697 #if NEW_LOGIC
mbed_official 462:e03396e14338 698
mbed_official 462:e03396e14338 699 // if we are currently reading a valid RxConsume buffer, increment to the next one
mbed_official 462:e03396e14338 700 if(rx_consume_offset >= 0) {
mbed_official 462:e03396e14338 701 LPC_EMAC->RxConsumeIndex = rinc(LPC_EMAC->RxConsumeIndex, NUM_RX_FRAG);
mbed_official 462:e03396e14338 702 }
mbed_official 462:e03396e14338 703
mbed_official 462:e03396e14338 704 // if the buffer is empty, mark it as no valid buffer
mbed_official 462:e03396e14338 705 if(LPC_EMAC->RxConsumeIndex == LPC_EMAC->RxProduceIndex) {
mbed_official 462:e03396e14338 706 rx_consume_offset = -1;
mbed_official 462:e03396e14338 707 return 0;
mbed_official 462:e03396e14338 708 }
mbed_official 462:e03396e14338 709
mbed_official 462:e03396e14338 710 uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
mbed_official 462:e03396e14338 711 rx_consume_offset = 0;
mbed_official 462:e03396e14338 712
mbed_official 462:e03396e14338 713 // check if it is not marked as last or for errors
mbed_official 462:e03396e14338 714 if(!(info & RINFO_LAST_FLAG) || (info & RINFO_ERR_MASK)) {
mbed_official 462:e03396e14338 715 return -1;
mbed_official 462:e03396e14338 716 }
mbed_official 462:e03396e14338 717
mbed_official 462:e03396e14338 718 int size = (info & RINFO_SIZE) + 1;
mbed_official 462:e03396e14338 719 return size - 4; // don't include checksum bytes
mbed_official 462:e03396e14338 720
mbed_official 462:e03396e14338 721 #else
mbed_official 462:e03396e14338 722 if(receive_idx == -1) {
mbed_official 462:e03396e14338 723 receive_idx = LPC_EMAC->RxConsumeIndex;
mbed_official 462:e03396e14338 724 } else {
mbed_official 462:e03396e14338 725 while(!(rxstat[receive_idx].Info & RINFO_LAST_FLAG) && ((uint32_t)receive_idx != LPC_EMAC->RxProduceIndex)) {
mbed_official 462:e03396e14338 726 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
mbed_official 462:e03396e14338 727 }
mbed_official 462:e03396e14338 728 unsigned int info = rxstat[receive_idx].Info;
mbed_official 462:e03396e14338 729 int slen = (info & RINFO_SIZE) + 1;
mbed_official 462:e03396e14338 730
mbed_official 462:e03396e14338 731 if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
mbed_official 462:e03396e14338 732 /* Invalid frame, ignore it and free buffer. */
mbed_official 462:e03396e14338 733 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
mbed_official 462:e03396e14338 734 }
mbed_official 462:e03396e14338 735 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
mbed_official 462:e03396e14338 736 receive_soff = 0;
mbed_official 462:e03396e14338 737
mbed_official 462:e03396e14338 738 LPC_EMAC->RxConsumeIndex = receive_idx;
mbed_official 462:e03396e14338 739 }
mbed_official 462:e03396e14338 740
mbed_official 462:e03396e14338 741 if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex) {
mbed_official 462:e03396e14338 742 receive_idx = -1;
mbed_official 462:e03396e14338 743 return 0;
mbed_official 462:e03396e14338 744 }
mbed_official 462:e03396e14338 745
mbed_official 462:e03396e14338 746 return (rxstat[receive_idx].Info & RINFO_SIZE) - 3;
mbed_official 462:e03396e14338 747 #endif
mbed_official 462:e03396e14338 748 }
mbed_official 462:e03396e14338 749
mbed_official 462:e03396e14338 750 // Read from an recevied ethernet packet.
mbed_official 462:e03396e14338 751 // After receive returnd a number bigger than 0 it is
mbed_official 462:e03396e14338 752 // possible to read bytes from this packet.
mbed_official 462:e03396e14338 753 // Read will write up to size bytes into data.
mbed_official 462:e03396e14338 754 // It is possible to use read multible times.
mbed_official 462:e03396e14338 755 // Each time read will start reading after the last read byte before.
mbed_official 462:e03396e14338 756
mbed_official 462:e03396e14338 757 int ethernet_read(char *data, int dlen) {
mbed_official 462:e03396e14338 758 #if NEW_LOGIC
mbed_official 462:e03396e14338 759 // Check we have a valid buffer to read
mbed_official 462:e03396e14338 760 if(rx_consume_offset < 0) {
mbed_official 462:e03396e14338 761 return 0;
mbed_official 462:e03396e14338 762 }
mbed_official 462:e03396e14338 763
mbed_official 462:e03396e14338 764 // Assume 1 fragment block
mbed_official 462:e03396e14338 765 uint32_t info = rxstat[LPC_EMAC->RxConsumeIndex].Info;
mbed_official 462:e03396e14338 766 int size = (info & RINFO_SIZE) + 1 - 4; // exclude checksum
mbed_official 462:e03396e14338 767
mbed_official 462:e03396e14338 768 int remaining = size - rx_consume_offset;
mbed_official 462:e03396e14338 769 int requested = dlen;
mbed_official 462:e03396e14338 770 int ncopy = min(remaining, requested);
mbed_official 462:e03396e14338 771
mbed_official 462:e03396e14338 772 void *psrc = (void *)(rxdesc[LPC_EMAC->RxConsumeIndex].Packet + rx_consume_offset);
mbed_official 462:e03396e14338 773 void *pdst = (void *)(data);
mbed_official 462:e03396e14338 774
mbed_official 462:e03396e14338 775 if(data != NULL && ncopy > 0) {
mbed_official 462:e03396e14338 776 memcpy(pdst, psrc, ncopy);
mbed_official 462:e03396e14338 777 }
mbed_official 462:e03396e14338 778
mbed_official 462:e03396e14338 779 rx_consume_offset += ncopy;
mbed_official 462:e03396e14338 780
mbed_official 462:e03396e14338 781 return ncopy;
mbed_official 462:e03396e14338 782 #else
mbed_official 462:e03396e14338 783 int slen;
mbed_official 462:e03396e14338 784 int copy = 0;
mbed_official 462:e03396e14338 785 unsigned int more;
mbed_official 462:e03396e14338 786 unsigned int info;
mbed_official 462:e03396e14338 787 void *pdst, *psrc;
mbed_official 462:e03396e14338 788 int doff = 0;
mbed_official 462:e03396e14338 789
mbed_official 462:e03396e14338 790 if((uint32_t)receive_idx == LPC_EMAC->RxProduceIndex || receive_idx == -1) {
mbed_official 462:e03396e14338 791 return 0;
mbed_official 462:e03396e14338 792 }
mbed_official 462:e03396e14338 793
mbed_official 462:e03396e14338 794 do {
mbed_official 462:e03396e14338 795 info = rxstat[receive_idx].Info;
mbed_official 462:e03396e14338 796 more = !(info & RINFO_LAST_FLAG);
mbed_official 462:e03396e14338 797 slen = (info & RINFO_SIZE) + 1;
mbed_official 462:e03396e14338 798
mbed_official 462:e03396e14338 799 if(slen > ethernet_MTU_SIZE || (info & RINFO_ERR_MASK)) {
mbed_official 462:e03396e14338 800 /* Invalid frame, ignore it and free buffer. */
mbed_official 462:e03396e14338 801 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
mbed_official 462:e03396e14338 802 } else {
mbed_official 462:e03396e14338 803
mbed_official 462:e03396e14338 804 copy = min(slen - receive_soff, dlen - doff);
mbed_official 462:e03396e14338 805 psrc = (void *)(rxdesc[receive_idx].Packet + receive_soff);
mbed_official 462:e03396e14338 806 pdst = (void *)(data + doff);
mbed_official 462:e03396e14338 807
mbed_official 462:e03396e14338 808 if(data != NULL) {
mbed_official 462:e03396e14338 809 /* check if Buffer available */
mbed_official 462:e03396e14338 810 memcpy(pdst, psrc, copy);
mbed_official 462:e03396e14338 811 }
mbed_official 462:e03396e14338 812
mbed_official 462:e03396e14338 813 receive_soff += copy;
mbed_official 462:e03396e14338 814 doff += copy;
mbed_official 462:e03396e14338 815
mbed_official 462:e03396e14338 816 if((more && (receive_soff == slen))) {
mbed_official 462:e03396e14338 817 receive_idx = rinc(receive_idx, NUM_RX_FRAG);
mbed_official 462:e03396e14338 818 receive_soff = 0;
mbed_official 462:e03396e14338 819 }
mbed_official 462:e03396e14338 820 }
mbed_official 462:e03396e14338 821 } while(more && !(doff == dlen) && !receive_soff);
mbed_official 462:e03396e14338 822
mbed_official 462:e03396e14338 823 return doff;
mbed_official 462:e03396e14338 824 #endif
mbed_official 462:e03396e14338 825 }
mbed_official 462:e03396e14338 826
mbed_official 462:e03396e14338 827 int ethernet_link(void) {
mbed_official 462:e03396e14338 828
mbed_official 462:e03396e14338 829 if (phy_id == DP83848C_ID) {
mbed_official 462:e03396e14338 830 return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
mbed_official 462:e03396e14338 831 }
mbed_official 462:e03396e14338 832 else { // LAN8720_ID
mbed_official 462:e03396e14338 833 return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
mbed_official 462:e03396e14338 834 }
mbed_official 462:e03396e14338 835 }
mbed_official 462:e03396e14338 836
mbed_official 462:e03396e14338 837 static int phy_write(unsigned int PhyReg, unsigned short Data) {
mbed_official 462:e03396e14338 838 unsigned int timeOut;
mbed_official 462:e03396e14338 839
mbed_official 462:e03396e14338 840 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
mbed_official 462:e03396e14338 841 LPC_EMAC->MWTD = Data;
mbed_official 462:e03396e14338 842
mbed_official 462:e03396e14338 843 for(timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) { /* Wait until operation completed */
mbed_official 462:e03396e14338 844 if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
mbed_official 462:e03396e14338 845 return 0;
mbed_official 462:e03396e14338 846 }
mbed_official 462:e03396e14338 847 }
mbed_official 462:e03396e14338 848
mbed_official 462:e03396e14338 849 return -1;
mbed_official 462:e03396e14338 850 }
mbed_official 462:e03396e14338 851
mbed_official 462:e03396e14338 852
mbed_official 462:e03396e14338 853 static int phy_read(unsigned int PhyReg) {
mbed_official 462:e03396e14338 854 unsigned int timeOut;
mbed_official 462:e03396e14338 855
mbed_official 462:e03396e14338 856 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
mbed_official 462:e03396e14338 857 LPC_EMAC->MCMD = MCMD_READ;
mbed_official 462:e03396e14338 858
mbed_official 462:e03396e14338 859 for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
mbed_official 462:e03396e14338 860 if((LPC_EMAC->MIND & MIND_BUSY) == 0) {
mbed_official 462:e03396e14338 861 LPC_EMAC->MCMD = 0;
mbed_official 462:e03396e14338 862 return LPC_EMAC->MRDD; /* Return a 16-bit value. */
mbed_official 462:e03396e14338 863 }
mbed_official 462:e03396e14338 864 }
mbed_official 462:e03396e14338 865
mbed_official 462:e03396e14338 866 return -1;
mbed_official 462:e03396e14338 867 }
mbed_official 462:e03396e14338 868
mbed_official 462:e03396e14338 869
mbed_official 462:e03396e14338 870 static void txdscr_init() {
mbed_official 462:e03396e14338 871 int i;
mbed_official 462:e03396e14338 872
mbed_official 462:e03396e14338 873 for(i = 0; i < NUM_TX_FRAG; i++) {
mbed_official 462:e03396e14338 874 txdesc[i].Packet = (uint32_t)&txbuf[i];
mbed_official 462:e03396e14338 875 txdesc[i].Ctrl = 0;
mbed_official 462:e03396e14338 876 txstat[i].Info = 0;
mbed_official 462:e03396e14338 877 }
mbed_official 462:e03396e14338 878
mbed_official 462:e03396e14338 879 LPC_EMAC->TxDescriptor = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
mbed_official 462:e03396e14338 880 LPC_EMAC->TxStatus = (uint32_t)txstat;
mbed_official 462:e03396e14338 881 LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
mbed_official 462:e03396e14338 882
mbed_official 462:e03396e14338 883 LPC_EMAC->TxProduceIndex = 0; /* Tx Descriptors Point to 0 */
mbed_official 462:e03396e14338 884 }
mbed_official 462:e03396e14338 885
mbed_official 462:e03396e14338 886
mbed_official 462:e03396e14338 887 static void rxdscr_init() {
mbed_official 462:e03396e14338 888 int i;
mbed_official 462:e03396e14338 889
mbed_official 462:e03396e14338 890 for(i = 0; i < NUM_RX_FRAG; i++) {
mbed_official 462:e03396e14338 891 rxdesc[i].Packet = (uint32_t)&rxbuf[i];
mbed_official 462:e03396e14338 892 rxdesc[i].Ctrl = RCTRL_INT | (ETH_FRAG_SIZE-1);
mbed_official 462:e03396e14338 893 rxstat[i].Info = 0;
mbed_official 462:e03396e14338 894 rxstat[i].HashCRC = 0;
mbed_official 462:e03396e14338 895 }
mbed_official 462:e03396e14338 896
mbed_official 462:e03396e14338 897 LPC_EMAC->RxDescriptor = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
mbed_official 462:e03396e14338 898 LPC_EMAC->RxStatus = (uint32_t)rxstat;
mbed_official 462:e03396e14338 899 LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
mbed_official 462:e03396e14338 900
mbed_official 462:e03396e14338 901 LPC_EMAC->RxConsumeIndex = 0; /* Rx Descriptors Point to 0 */
mbed_official 462:e03396e14338 902 }
mbed_official 462:e03396e14338 903
mbed_official 462:e03396e14338 904 void ethernet_address(char *mac) {
mbed_official 462:e03396e14338 905 mbed_mac_address(mac);
mbed_official 462:e03396e14338 906 }
mbed_official 462:e03396e14338 907
mbed_official 462:e03396e14338 908 void ethernet_set_link(int speed, int duplex) {
mbed_official 462:e03396e14338 909 unsigned short phy_data;
mbed_official 462:e03396e14338 910 int tout;
mbed_official 462:e03396e14338 911
mbed_official 462:e03396e14338 912 if((speed < 0) || (speed > 1)) {
mbed_official 462:e03396e14338 913 phy_data = PHY_AUTO_NEG;
mbed_official 462:e03396e14338 914 } else {
mbed_official 462:e03396e14338 915 phy_data = (((unsigned short) speed << 13) |
mbed_official 462:e03396e14338 916 ((unsigned short) duplex << 8));
mbed_official 462:e03396e14338 917 }
mbed_official 462:e03396e14338 918
mbed_official 462:e03396e14338 919 phy_write(PHY_REG_BMCR, phy_data);
mbed_official 462:e03396e14338 920
mbed_official 462:e03396e14338 921 for (tout = 100; tout; tout--) { __NOP(); } /* A short delay */
mbed_official 462:e03396e14338 922
mbed_official 462:e03396e14338 923 switch(phy_id) {
mbed_official 462:e03396e14338 924 case DP83848C_ID:
mbed_official 462:e03396e14338 925 phy_data = phy_read(PHY_REG_STS);
mbed_official 462:e03396e14338 926
mbed_official 462:e03396e14338 927 if(phy_data & PHY_STS_DUPLEX) {
mbed_official 462:e03396e14338 928 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
mbed_official 462:e03396e14338 929 LPC_EMAC->Command |= CR_FULL_DUP;
mbed_official 462:e03396e14338 930 LPC_EMAC->IPGT = IPGT_FULL_DUP;
mbed_official 462:e03396e14338 931 } else {
mbed_official 462:e03396e14338 932 LPC_EMAC->MAC2 &= ~MAC2_FULL_DUP;
mbed_official 462:e03396e14338 933 LPC_EMAC->Command &= ~CR_FULL_DUP;
mbed_official 462:e03396e14338 934 LPC_EMAC->IPGT = IPGT_HALF_DUP;
mbed_official 462:e03396e14338 935 }
mbed_official 462:e03396e14338 936
mbed_official 462:e03396e14338 937 if(phy_data & PHY_STS_SPEED) {
mbed_official 462:e03396e14338 938 LPC_EMAC->SUPP &= ~SUPP_SPEED;
mbed_official 462:e03396e14338 939 } else {
mbed_official 462:e03396e14338 940 LPC_EMAC->SUPP |= SUPP_SPEED;
mbed_official 462:e03396e14338 941 }
mbed_official 462:e03396e14338 942 break;
mbed_official 462:e03396e14338 943
mbed_official 462:e03396e14338 944 case LAN8720_ID:
mbed_official 462:e03396e14338 945 phy_data = phy_read(PHY_REG_SCSR);
mbed_official 462:e03396e14338 946
mbed_official 462:e03396e14338 947 if (phy_data & PHY_SCSR_DUPLEX) {
mbed_official 462:e03396e14338 948 LPC_EMAC->MAC2 |= MAC2_FULL_DUP;
mbed_official 462:e03396e14338 949 LPC_EMAC->Command |= CR_FULL_DUP;
mbed_official 462:e03396e14338 950 LPC_EMAC->IPGT = IPGT_FULL_DUP;
mbed_official 462:e03396e14338 951 } else {
mbed_official 462:e03396e14338 952 LPC_EMAC->Command &= ~CR_FULL_DUP;
mbed_official 462:e03396e14338 953 LPC_EMAC->IPGT = IPGT_HALF_DUP;
mbed_official 462:e03396e14338 954 }
mbed_official 462:e03396e14338 955
mbed_official 462:e03396e14338 956 if(phy_data & PHY_SCSR_100MBIT) {
mbed_official 462:e03396e14338 957 LPC_EMAC->SUPP |= SUPP_SPEED;
mbed_official 462:e03396e14338 958 } else {
mbed_official 462:e03396e14338 959 LPC_EMAC->SUPP &= ~SUPP_SPEED;
mbed_official 462:e03396e14338 960 }
mbed_official 462:e03396e14338 961
mbed_official 462:e03396e14338 962 break;
mbed_official 462:e03396e14338 963 }
mbed_official 462:e03396e14338 964 }