shinichi nakazawa / mbed-src

mbed library sources

Dependents:   Nucleo_blink_led

Fork of mbed-src by mbed official

targets/hal/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c@467:4961165abe5d, 2015-02-09 (annotated)

Committer:
mbed_official
Date:
Mon Feb 09 08:45:07 2015 +0000
Revision:
467:4961165abe5d
Parent:
285:31249416b6f9 
Synchronized with git revision aeeed2d0507dc81ed795d026940ad5234c03f314



Full URL: https://github.com/mbedmicro/mbed/commit/aeeed2d0507dc81ed795d026940ad5234c03f314/



Initial ethernet support for LPC433x

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 256:76fd9a263045 1 /* mbed Microcontroller Library
mbed_official 467:4961165abe5d 2 * Copyright (c) 2006-2015 ARM Limited
mbed_official 256:76fd9a263045 3 *
mbed_official 256:76fd9a263045 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 256:76fd9a263045 5 * you may not use this file except in compliance with the License.
mbed_official 256:76fd9a263045 6 * You may obtain a copy of the License at
mbed_official 256:76fd9a263045 7 *
mbed_official 256:76fd9a263045 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 256:76fd9a263045 9 *
mbed_official 256:76fd9a263045 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 256:76fd9a263045 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 256:76fd9a263045 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 256:76fd9a263045 13 * See the License for the specific language governing permissions and
mbed_official 256:76fd9a263045 14 * limitations under the License.
mbed_official 256:76fd9a263045 15 *
mbed_official 467:4961165abe5d 16 * Contribution by Nitin Bhaskar(nitin.bhaskar.27.09@gmail.com)
mbed_official 256:76fd9a263045 17 */
mbed_official 256:76fd9a263045 18 #include "ethernet_api.h"
mbed_official 256:76fd9a263045 19
mbed_official 256:76fd9a263045 20 #include <string.h>
mbed_official 256:76fd9a263045 21 #include "cmsis.h"
mbed_official 256:76fd9a263045 22 #include "mbed_interface.h"
mbed_official 256:76fd9a263045 23 #include "toolchain.h"
mbed_official 285:31249416b6f9 24 #include "mbed_error.h"
mbed_official 467:4961165abe5d 25 #include "pinmap.h"
mbed_official 256:76fd9a263045 26
mbed_official 256:76fd9a263045 27 #define NEW_LOGIC 0
mbed_official 256:76fd9a263045 28 #define NEW_ETH_BUFFER 0
mbed_official 256:76fd9a263045 29
mbed_official 256:76fd9a263045 30 #if NEW_ETH_BUFFER
mbed_official 256:76fd9a263045 31
mbed_official 256:76fd9a263045 32 #define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
mbed_official 256:76fd9a263045 33 #define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
mbed_official 256:76fd9a263045 34
mbed_official 256:76fd9a263045 35 #define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
mbed_official 256:76fd9a263045 36 #define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
mbed_official 256:76fd9a263045 37
mbed_official 256:76fd9a263045 38 #else
mbed_official 256:76fd9a263045 39
mbed_official 256:76fd9a263045 40 // Memfree calculation:
mbed_official 256:76fd9a263045 41 // (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
mbed_official 256:76fd9a263045 42 // (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
mbed_official 256:76fd9a263045 43 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
mbed_official 256:76fd9a263045 44 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
mbed_official 256:76fd9a263045 45 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
mbed_official 256:76fd9a263045 46 //#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
mbed_official 256:76fd9a263045 47
mbed_official 256:76fd9a263045 48 //#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
mbed_official 256:76fd9a263045 49 #define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
mbed_official 256:76fd9a263045 50 #define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
mbed_official 256:76fd9a263045 51
mbed_official 256:76fd9a263045 52 const int ethernet_MTU_SIZE = 0x300;
mbed_official 256:76fd9a263045 53
mbed_official 256:76fd9a263045 54 #endif
mbed_official 256:76fd9a263045 55
mbed_official 256:76fd9a263045 56 #define ETHERNET_ADDR_SIZE 6
mbed_official 256:76fd9a263045 57
mbed_official 467:4961165abe5d 58 /* Descriptors Fields bits */
mbed_official 467:4961165abe5d 59 #define TRDES_OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */
mbed_official 467:4961165abe5d 60 #define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */
mbed_official 467:4961165abe5d 61 #define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */
mbed_official 467:4961165abe5d 62 #define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */
mbed_official 467:4961165abe5d 63 #define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */
mbed_official 467:4961165abe5d 64 #define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */
mbed_official 467:4961165abe5d 65 #define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */
mbed_official 467:4961165abe5d 66
mbed_official 256:76fd9a263045 67 PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
mbed_official 467:4961165abe5d 68 unsigned int Status;
mbed_official 467:4961165abe5d 69 unsigned int Ctrl;
mbed_official 467:4961165abe5d 70 unsigned int BufAddr1;
mbed_official 467:4961165abe5d 71 unsigned int NextDescAddr;
mbed_official 256:76fd9a263045 72 };
mbed_official 256:76fd9a263045 73 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
mbed_official 256:76fd9a263045 74
mbed_official 256:76fd9a263045 75 PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
mbed_official 467:4961165abe5d 76 unsigned int Status;
mbed_official 467:4961165abe5d 77 unsigned int Ctrl;
mbed_official 467:4961165abe5d 78 unsigned int BufAddr1;
mbed_official 467:4961165abe5d 79 unsigned int NextDescAddr;
mbed_official 256:76fd9a263045 80 };
mbed_official 256:76fd9a263045 81 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
mbed_official 256:76fd9a263045 82
mbed_official 467:4961165abe5d 83 /* ETHMODE RMII SELECT */
mbed_official 467:4961165abe5d 84 #define RMII_SELECT 0x04
mbed_official 467:4961165abe5d 85 /* define to tell PHY about write operation */
mbed_official 467:4961165abe5d 86 #define MII_WRITE (1 << 1)
mbed_official 467:4961165abe5d 87 /* define to tell PHY about read operation */
mbed_official 467:4961165abe5d 88 #define MII_READ (0 << 1)
mbed_official 467:4961165abe5d 89 /* define to enable duplex mode */
mbed_official 467:4961165abe5d 90 #define MAC_DUPLEX_MODE (1 << 11)
mbed_official 256:76fd9a263045 91
mbed_official 467:4961165abe5d 92 /* MAC_FRAME_FILTER register bit defines */
mbed_official 467:4961165abe5d 93 #define MAC_FRAME_FILTER_PR (1 << 0) /* Promiscuous Mode */
mbed_official 467:4961165abe5d 94 #define MAC_FRAME_FILTER_RA (1UL << 31) /* Receive all */
mbed_official 467:4961165abe5d 95
mbed_official 467:4961165abe5d 96 /* MAC_CONFIG register bit defines */
mbed_official 467:4961165abe5d 97 #define MAC_CONFIG_RE (1 << 2) /* Receiver enable */
mbed_official 467:4961165abe5d 98 #define MAC_CONFIG_TE (1 << 3) /* Transmitter Enable */
mbed_official 256:76fd9a263045 99
mbed_official 467:4961165abe5d 100 /* DMA_OP_MODE register bit defines */
mbed_official 467:4961165abe5d 101 #define DMA_OP_MODE_SSR (1 << 1) /* Start/stop receive */
mbed_official 467:4961165abe5d 102 #define DMA_OP_MODE_SST (1 << 13) /* Start/Stop Transmission Command */
mbed_official 256:76fd9a263045 103
mbed_official 467:4961165abe5d 104 /* DMA_INT_EN register bit defines */
mbed_official 467:4961165abe5d 105 #define DMA_INT_EN_TIE (1 << 0) /* Transmit interrupt enable */
mbed_official 467:4961165abe5d 106 #define DMA_INT_EN_TSE (1 << 1) /* Transmit stopped enable */
mbed_official 467:4961165abe5d 107 #define DMA_INT_EN_TUE (1 << 2) /* Transmit buffer unavailable enable */
mbed_official 467:4961165abe5d 108 #define DMA_INT_EN_TJE (1 << 3) /* Transmit jabber timeout enable */
mbed_official 467:4961165abe5d 109 #define DMA_INT_EN_OVE (1 << 4) /* Overflow interrupt enable */
mbed_official 467:4961165abe5d 110 #define DMA_INT_EN_UNE (1 << 5) /* Underflow interrupt enable */
mbed_official 467:4961165abe5d 111 #define DMA_INT_EN_RIE (1 << 6) /* Receive interrupt enable */
mbed_official 467:4961165abe5d 112 #define DMA_INT_EN_RUE (1 << 7) /* Receive buffer unavailable enable */
mbed_official 467:4961165abe5d 113 #define DMA_INT_EN_RSE (1 << 8) /* Received stopped enable */
mbed_official 467:4961165abe5d 114 #define DMA_INT_EN_RWE (1 << 9) /* Receive watchdog timeout enable */
mbed_official 467:4961165abe5d 115 #define DMA_INT_EN_ETE (1 << 10) /* Early transmit interrupt enable */
mbed_official 467:4961165abe5d 116 #define DMA_INT_EN_FBE (1 << 13) /* Fatal bus error enable */
mbed_official 467:4961165abe5d 117 #define DMA_INT_EN_ERE (1 << 14) /* Early receive interrupt enable */
mbed_official 467:4961165abe5d 118 #define DMA_INT_EN_AIE (1 << 15) /* Abnormal interrupt summary enable */
mbed_official 467:4961165abe5d 119 #define DMA_INT_EN_NIE (1 << 16) /* Normal interrupt summary enable */
mbed_official 256:76fd9a263045 120
mbed_official 256:76fd9a263045 121
mbed_official 256:76fd9a263045 122
mbed_official 256:76fd9a263045 123 /* PHY Support Register */
mbed_official 467:4961165abe5d 124 #define SUPP_SPEED 0x00004000 /* Reduced MII Logic Current Speed */
mbed_official 256:76fd9a263045 125 //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
mbed_official 256:76fd9a263045 126 #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
mbed_official 256:76fd9a263045 127
mbed_official 256:76fd9a263045 128 /* MII Management Command Register */
mbed_official 256:76fd9a263045 129 #define MCMD_READ 0x00000001 /* MII Read */
mbed_official 256:76fd9a263045 130 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
mbed_official 256:76fd9a263045 131
mbed_official 256:76fd9a263045 132 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
mbed_official 256:76fd9a263045 133 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
mbed_official 256:76fd9a263045 134
mbed_official 256:76fd9a263045 135 /* MII Management Address Register */
mbed_official 256:76fd9a263045 136 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
mbed_official 256:76fd9a263045 137 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
mbed_official 256:76fd9a263045 138
mbed_official 256:76fd9a263045 139 /* MII Management Indicators Register */
mbed_official 256:76fd9a263045 140 #define MIND_BUSY 0x00000001 /* MII is Busy */
mbed_official 256:76fd9a263045 141 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
mbed_official 256:76fd9a263045 142 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
mbed_official 256:76fd9a263045 143 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
mbed_official 256:76fd9a263045 144
mbed_official 256:76fd9a263045 145 /* DP83848C PHY Registers */
mbed_official 256:76fd9a263045 146 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
mbed_official 256:76fd9a263045 147 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
mbed_official 256:76fd9a263045 148 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
mbed_official 256:76fd9a263045 149 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
mbed_official 256:76fd9a263045 150 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
mbed_official 256:76fd9a263045 151 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
mbed_official 256:76fd9a263045 152 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
mbed_official 256:76fd9a263045 153 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
mbed_official 256:76fd9a263045 154
mbed_official 256:76fd9a263045 155 /* PHY Extended Registers */
mbed_official 256:76fd9a263045 156 #define PHY_REG_STS 0x10 /* Status Register */
mbed_official 256:76fd9a263045 157 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
mbed_official 256:76fd9a263045 158 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
mbed_official 256:76fd9a263045 159 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
mbed_official 256:76fd9a263045 160 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
mbed_official 256:76fd9a263045 161 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
mbed_official 256:76fd9a263045 162 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
mbed_official 256:76fd9a263045 163 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
mbed_official 256:76fd9a263045 164 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
mbed_official 256:76fd9a263045 165 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
mbed_official 256:76fd9a263045 166 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
mbed_official 256:76fd9a263045 167 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
mbed_official 256:76fd9a263045 168
mbed_official 256:76fd9a263045 169 #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
mbed_official 256:76fd9a263045 170
mbed_official 256:76fd9a263045 171 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
mbed_official 256:76fd9a263045 172 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
mbed_official 256:76fd9a263045 173 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
mbed_official 256:76fd9a263045 174 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
mbed_official 467:4961165abe5d 175 #define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */
mbed_official 256:76fd9a263045 176
mbed_official 467:4961165abe5d 177 #define DP83848C_DEF_ADR 0x01 /* Default PHY device address */
mbed_official 256:76fd9a263045 178 #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
mbed_official 256:76fd9a263045 179
mbed_official 256:76fd9a263045 180 #define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
mbed_official 256:76fd9a263045 181
mbed_official 256:76fd9a263045 182 #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
mbed_official 256:76fd9a263045 183 #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
mbed_official 256:76fd9a263045 184 #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
mbed_official 256:76fd9a263045 185
mbed_official 256:76fd9a263045 186 #define PHY_BMCR_RESET 0x8000 /* PHY Reset */
mbed_official 256:76fd9a263045 187
mbed_official 256:76fd9a263045 188 #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
mbed_official 256:76fd9a263045 189
mbed_official 256:76fd9a263045 190 #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
mbed_official 256:76fd9a263045 191 #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
mbed_official 256:76fd9a263045 192
mbed_official 467:4961165abe5d 193 static int phy_read(unsigned int PhyReg);
mbed_official 467:4961165abe5d 194 static int phy_write(unsigned int PhyReg, unsigned short Data);
mbed_official 467:4961165abe5d 195
mbed_official 467:4961165abe5d 196 static void txdscr_init(void);
mbed_official 467:4961165abe5d 197 static void rxdscr_init(void);
mbed_official 467:4961165abe5d 198
mbed_official 256:76fd9a263045 199 #if defined (__ICCARM__)
mbed_official 256:76fd9a263045 200 # define AHBSRAM1
mbed_official 256:76fd9a263045 201 #elif defined(TOOLCHAIN_GCC_CR)
mbed_official 256:76fd9a263045 202 # define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
mbed_official 256:76fd9a263045 203 #else
mbed_official 256:76fd9a263045 204 # define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
mbed_official 256:76fd9a263045 205 #endif
mbed_official 256:76fd9a263045 206
mbed_official 256:76fd9a263045 207 AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
mbed_official 256:76fd9a263045 208 AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
mbed_official 256:76fd9a263045 209 AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
mbed_official 256:76fd9a263045 210 AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
mbed_official 256:76fd9a263045 211
mbed_official 256:76fd9a263045 212 #ifndef min
mbed_official 256:76fd9a263045 213 #define min(x, y) (((x)<(y))?(x):(y))
mbed_official 256:76fd9a263045 214 #endif
mbed_official 256:76fd9a263045 215
mbed_official 467:4961165abe5d 216 static uint32_t phy_id = 0;
mbed_official 467:4961165abe5d 217 static uint32_t TxDescIndex = 0;
mbed_official 467:4961165abe5d 218 static uint32_t RxDescIndex = 0;
mbed_official 467:4961165abe5d 219 static uint32_t RxOffset = 0;
mbed_official 467:4961165abe5d 220
mbed_official 256:76fd9a263045 221 /*----------------------------------------------------------------------------
mbed_official 256:76fd9a263045 222 Ethernet Device initialize
mbed_official 256:76fd9a263045 223 *----------------------------------------------------------------------------*/
mbed_official 467:4961165abe5d 224 int ethernet_init()
mbed_official 467:4961165abe5d 225 {
mbed_official 467:4961165abe5d 226 int regv, tout;
mbed_official 467:4961165abe5d 227 char mac[ETHERNET_ADDR_SIZE];
mbed_official 467:4961165abe5d 228
mbed_official 467:4961165abe5d 229 pin_function(PC_0, (SCU_MODE_INACT | FUNC3)); /* Enable ENET RX CLK */
mbed_official 467:4961165abe5d 230 pin_function(P1_19, (SCU_MODE_INACT | FUNC0)); /* Enable ENET TX CLK */
mbed_official 467:4961165abe5d 231
mbed_official 467:4961165abe5d 232 /* Ethernet pinmuxing */
mbed_official 467:4961165abe5d 233 pin_function(P2_0, SCU_PINIO_FAST | FUNC7); /* ENET_MDC */
mbed_official 467:4961165abe5d 234 pin_function(P1_17, SCU_PINIO_FAST | FUNC3); /* ENET_MDIO */
mbed_official 467:4961165abe5d 235 pin_function(P1_18, SCU_PINIO_FAST | FUNC3); /* ENET_TXD0 */
mbed_official 467:4961165abe5d 236 pin_function(P1_20, SCU_PINIO_FAST | FUNC3); /* ENET_TXD1 */
mbed_official 467:4961165abe5d 237 pin_function(P1_19, SCU_PINIO_FAST | FUNC0); /* ENET_REF */
mbed_official 467:4961165abe5d 238 pin_function(P0_1, SCU_PINIO_FAST | FUNC6); /* ENET_TX_EN */
mbed_official 467:4961165abe5d 239 pin_function(P1_15, SCU_PINIO_FAST | FUNC3); /* ENET_RXD0 */
mbed_official 467:4961165abe5d 240 pin_function(P0_0, SCU_PINIO_FAST | FUNC2); /* ENET_RXD1 */
mbed_official 467:4961165abe5d 241 pin_function(P1_16, SCU_PINIO_FAST | FUNC3); /* ENET_CRS */
mbed_official 467:4961165abe5d 242 pin_function(PC_9, SCU_PINIO_FAST | FUNC3); /* ENET_RX_ER */
mbed_official 467:4961165abe5d 243 pin_function(P1_16, SCU_PINIO_FAST | FUNC7); /* ENET_RXDV */
mbed_official 467:4961165abe5d 244
mbed_official 467:4961165abe5d 245 LPC_CREG->CREG6 |= RMII_SELECT;
mbed_official 467:4961165abe5d 246
mbed_official 467:4961165abe5d 247 /* perform RGU soft reset */
mbed_official 467:4961165abe5d 248 LPC_RGU->RESET_CTRL0 = 1 << 22;
mbed_official 467:4961165abe5d 249 LPC_RGU->RESET_CTRL0 = 0;
mbed_official 467:4961165abe5d 250
mbed_official 467:4961165abe5d 251 /* Wait until reset is performed */
mbed_official 467:4961165abe5d 252 while(1) {
mbed_official 467:4961165abe5d 253 if (LPC_RGU->RESET_ACTIVE_STATUS0 & (1 << 22))
mbed_official 467:4961165abe5d 254 break;
mbed_official 467:4961165abe5d 255 }
mbed_official 467:4961165abe5d 256
mbed_official 467:4961165abe5d 257 /* Reset MAC DMA Controller */
mbed_official 467:4961165abe5d 258 LPC_ETHERNET->DMA_BUS_MODE |= 0x01;
mbed_official 467:4961165abe5d 259 while(LPC_ETHERNET->DMA_BUS_MODE & 0x01);
mbed_official 467:4961165abe5d 260
mbed_official 467:4961165abe5d 261 phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
mbed_official 467:4961165abe5d 262
mbed_official 467:4961165abe5d 263 for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
mbed_official 467:4961165abe5d 264 regv = phy_read(PHY_REG_BMCR);
mbed_official 467:4961165abe5d 265 if(regv < 0 || tout == 0) {
mbed_official 467:4961165abe5d 266 return -1; /* Error */
mbed_official 467:4961165abe5d 267 }
mbed_official 467:4961165abe5d 268 if(!(regv & PHY_BMCR_RESET)) {
mbed_official 467:4961165abe5d 269 break; /* Reset complete. */
mbed_official 467:4961165abe5d 270 }
mbed_official 467:4961165abe5d 271 }
mbed_official 467:4961165abe5d 272
mbed_official 467:4961165abe5d 273 phy_id = (phy_read(PHY_REG_IDR1) << 16);
mbed_official 467:4961165abe5d 274 phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
mbed_official 467:4961165abe5d 275
mbed_official 467:4961165abe5d 276 if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
mbed_official 467:4961165abe5d 277 error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
mbed_official 467:4961165abe5d 278 }
mbed_official 467:4961165abe5d 279
mbed_official 467:4961165abe5d 280 ethernet_set_link(-1, 0);
mbed_official 467:4961165abe5d 281
mbed_official 467:4961165abe5d 282 /* Set the Ethernet MAC Address registers */
mbed_official 467:4961165abe5d 283 ethernet_address(mac);
mbed_official 467:4961165abe5d 284 LPC_ETHERNET->MAC_ADDR0_HIGH = (mac[5] << 8) | mac[4];
mbed_official 467:4961165abe5d 285 LPC_ETHERNET->MAC_ADDR0_LOW = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
mbed_official 467:4961165abe5d 286
mbed_official 467:4961165abe5d 287 txdscr_init(); /* initialize DMA TX Descriptor */
mbed_official 467:4961165abe5d 288 rxdscr_init(); /* initialize DMA RX Descriptor */
mbed_official 467:4961165abe5d 289
mbed_official 467:4961165abe5d 290 /* Configure Filter */
mbed_official 467:4961165abe5d 291 LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FRAME_FILTER_PR | MAC_FRAME_FILTER_RA;
mbed_official 467:4961165abe5d 292
mbed_official 467:4961165abe5d 293 /* Enable Receiver and Transmitter */
mbed_official 467:4961165abe5d 294 LPC_ETHERNET->MAC_CONFIG |= (MAC_CONFIG_RE | MAC_CONFIG_TE);
mbed_official 467:4961165abe5d 295
mbed_official 467:4961165abe5d 296 //LPC_ETHERNET->DMA_INT_EN = DMA_INT_EN_NIE | DMA_INT_EN_RIE | DMA_INT_EN_TJE; /* Enable EMAC interrupts. */
mbed_official 467:4961165abe5d 297
mbed_official 467:4961165abe5d 298 /* Start Transmission & Receive processes */
mbed_official 467:4961165abe5d 299 LPC_ETHERNET->DMA_OP_MODE |= (DMA_OP_MODE_SST | DMA_OP_MODE_SSR);
mbed_official 467:4961165abe5d 300
mbed_official 467:4961165abe5d 301 return 0;
mbed_official 256:76fd9a263045 302 }
mbed_official 256:76fd9a263045 303
mbed_official 256:76fd9a263045 304 /*----------------------------------------------------------------------------
mbed_official 256:76fd9a263045 305 Ethernet Device Uninitialize
mbed_official 256:76fd9a263045 306 *----------------------------------------------------------------------------*/
mbed_official 467:4961165abe5d 307 void ethernet_free()
mbed_official 467:4961165abe5d 308 {
mbed_official 467:4961165abe5d 309 }
mbed_official 467:4961165abe5d 310
mbed_official 467:4961165abe5d 311 /*----------------------------------------------------------------------------
mbed_official 467:4961165abe5d 312 Ethernet write
mbed_official 467:4961165abe5d 313 *----------------------------------------------------------------------------*/
mbed_official 467:4961165abe5d 314 int ethernet_write(const char *data, int slen)
mbed_official 467:4961165abe5d 315 {
mbed_official 467:4961165abe5d 316 if (slen > ETH_FRAG_SIZE)
mbed_official 467:4961165abe5d 317 return -1;
mbed_official 467:4961165abe5d 318
mbed_official 467:4961165abe5d 319 txdesc[TxDescIndex].Ctrl = slen;
mbed_official 467:4961165abe5d 320 memcpy((void *)txdesc[TxDescIndex].BufAddr1, data, slen);
mbed_official 467:4961165abe5d 321 return slen;
mbed_official 256:76fd9a263045 322 }
mbed_official 256:76fd9a263045 323
mbed_official 467:4961165abe5d 324 /*----------------------------------------------------------------------------
mbed_official 467:4961165abe5d 325 Ethernet Send
mbed_official 467:4961165abe5d 326 *----------------------------------------------------------------------------*/
mbed_official 467:4961165abe5d 327 int ethernet_send()
mbed_official 467:4961165abe5d 328 {
mbed_official 467:4961165abe5d 329 int s = txdesc[TxDescIndex].Ctrl;
mbed_official 467:4961165abe5d 330 txdesc[TxDescIndex].Status |= TRDES_OWN_BIT;
mbed_official 467:4961165abe5d 331 LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; // Wake Up the DMA if it's in Suspended Mode
mbed_official 467:4961165abe5d 332 TxDescIndex++;
mbed_official 467:4961165abe5d 333 if (TxDescIndex == NUM_TX_FRAG)
mbed_official 467:4961165abe5d 334 TxDescIndex = 0;
mbed_official 256:76fd9a263045 335
mbed_official 467:4961165abe5d 336 return s;
mbed_official 256:76fd9a263045 337 }
mbed_official 256:76fd9a263045 338
mbed_official 467:4961165abe5d 339 /*----------------------------------------------------------------------------
mbed_official 467:4961165abe5d 340 Ethernet receive
mbed_official 467:4961165abe5d 341 *----------------------------------------------------------------------------*/
mbed_official 467:4961165abe5d 342 int ethernet_receive()
mbed_official 467:4961165abe5d 343 {
mbed_official 467:4961165abe5d 344 int i, slen = 0;
mbed_official 467:4961165abe5d 345 for (i = RxDescIndex;; i++) {
mbed_official 467:4961165abe5d 346 if (rxdesc[i].Status & TRDES_OWN_BIT)
mbed_official 467:4961165abe5d 347 return (slen - RxOffset);
mbed_official 467:4961165abe5d 348 else
mbed_official 467:4961165abe5d 349 slen += (rxdesc[i].Status >> 16) & 0x03FFF;
mbed_official 467:4961165abe5d 350 }
mbed_official 467:4961165abe5d 351 return 0;
mbed_official 256:76fd9a263045 352 }
mbed_official 256:76fd9a263045 353
mbed_official 467:4961165abe5d 354
mbed_official 467:4961165abe5d 355 /*----------------------------------------------------------------------------
mbed_official 467:4961165abe5d 356 Ethernet read
mbed_official 467:4961165abe5d 357 *----------------------------------------------------------------------------*/
mbed_official 467:4961165abe5d 358 int ethernet_read(char *data, int dlen)
mbed_official 467:4961165abe5d 359 {
mbed_official 467:4961165abe5d 360 int copylen;
mbed_official 467:4961165abe5d 361 uint32_t *pSrc = (uint32_t *)rxdesc[RxDescIndex].BufAddr1;
mbed_official 467:4961165abe5d 362 copylen = (rxdesc[RxDescIndex].Status >> 16) & 0x03FFF;
mbed_official 467:4961165abe5d 363 if (rxdesc[RxDescIndex].Status & TRDES_OWN_BIT || (dlen + RxOffset) > copylen)
mbed_official 467:4961165abe5d 364 return -1;
mbed_official 256:76fd9a263045 365
mbed_official 467:4961165abe5d 366 if ((dlen + RxOffset) == copylen) {
mbed_official 467:4961165abe5d 367 memcpy(&pSrc[RxOffset], data, copylen);
mbed_official 467:4961165abe5d 368 rxdesc[RxDescIndex].Status = TRDES_OWN_BIT;
mbed_official 467:4961165abe5d 369 RxDescIndex++;
mbed_official 467:4961165abe5d 370 RxOffset = 0;
mbed_official 467:4961165abe5d 371 if (RxDescIndex == NUM_RX_FRAG)
mbed_official 467:4961165abe5d 372 RxDescIndex = 0;
mbed_official 467:4961165abe5d 373 } else if ((dlen + RxOffset) < copylen) {
mbed_official 467:4961165abe5d 374 copylen = dlen;
mbed_official 467:4961165abe5d 375 memcpy(&pSrc[RxOffset], data, copylen);
mbed_official 467:4961165abe5d 376 RxOffset += dlen;
mbed_official 467:4961165abe5d 377 }
mbed_official 467:4961165abe5d 378 return copylen;
mbed_official 256:76fd9a263045 379 }
mbed_official 256:76fd9a263045 380
mbed_official 467:4961165abe5d 381 int ethernet_link(void)
mbed_official 467:4961165abe5d 382 {
mbed_official 467:4961165abe5d 383
mbed_official 467:4961165abe5d 384 if (phy_id == DP83848C_ID) {
mbed_official 467:4961165abe5d 385 return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
mbed_official 467:4961165abe5d 386 } else { // LAN8720_ID
mbed_official 467:4961165abe5d 387 return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
mbed_official 467:4961165abe5d 388 }
mbed_official 467:4961165abe5d 389 }
mbed_official 256:76fd9a263045 390
mbed_official 467:4961165abe5d 391 static int phy_write(unsigned int PhyReg, unsigned short Data)
mbed_official 467:4961165abe5d 392 {
mbed_official 467:4961165abe5d 393 unsigned int timeOut;
mbed_official 467:4961165abe5d 394
mbed_official 467:4961165abe5d 395 while(LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY);
mbed_official 467:4961165abe5d 396 LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | MII_WRITE;
mbed_official 467:4961165abe5d 397 LPC_ETHERNET->MAC_MII_DATA = Data;
mbed_official 467:4961165abe5d 398 LPC_ETHERNET->MAC_MII_ADDR |= MIND_BUSY; // Start PHY Write Cycle
mbed_official 467:4961165abe5d 399
mbed_official 467:4961165abe5d 400 /* Wait utill operation completed */
mbed_official 467:4961165abe5d 401 for (timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {
mbed_official 467:4961165abe5d 402 if ((LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY) == 0) {
mbed_official 467:4961165abe5d 403 break;
mbed_official 467:4961165abe5d 404 }
mbed_official 467:4961165abe5d 405 }
mbed_official 467:4961165abe5d 406
mbed_official 256:76fd9a263045 407 return -1;
mbed_official 256:76fd9a263045 408 }
mbed_official 256:76fd9a263045 409
mbed_official 467:4961165abe5d 410 static int phy_read(unsigned int PhyReg)
mbed_official 467:4961165abe5d 411 {
mbed_official 467:4961165abe5d 412 unsigned int timeOut;
mbed_official 467:4961165abe5d 413
mbed_official 467:4961165abe5d 414 while(LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY);
mbed_official 467:4961165abe5d 415 LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | MII_READ;
mbed_official 467:4961165abe5d 416 LPC_ETHERNET->MAC_MII_ADDR |= MIND_BUSY;
mbed_official 467:4961165abe5d 417
mbed_official 467:4961165abe5d 418 for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
mbed_official 467:4961165abe5d 419 if((LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY) == 0) {
mbed_official 467:4961165abe5d 420 return LPC_ETHERNET->MAC_MII_DATA; /* Return a 16-bit value. */
mbed_official 467:4961165abe5d 421 }
mbed_official 467:4961165abe5d 422 }
mbed_official 467:4961165abe5d 423
mbed_official 256:76fd9a263045 424 return -1;
mbed_official 256:76fd9a263045 425 }
mbed_official 256:76fd9a263045 426
mbed_official 467:4961165abe5d 427 static void txdscr_init()
mbed_official 467:4961165abe5d 428 {
mbed_official 467:4961165abe5d 429 int i;
mbed_official 467:4961165abe5d 430
mbed_official 467:4961165abe5d 431 for(i = 0; i < NUM_TX_FRAG; i++) {
mbed_official 467:4961165abe5d 432 txdesc[i].Status = TX_LAST_SEGM | TX_FIRST_SEGM;;
mbed_official 467:4961165abe5d 433 txdesc[i].Ctrl = 0;
mbed_official 467:4961165abe5d 434 txdesc[i].BufAddr1 = (uint32_t)&txbuf[i];
mbed_official 467:4961165abe5d 435 if (i == (NUM_RX_FRAG - 1)) {
mbed_official 467:4961165abe5d 436 txdesc[i].Status |= TX_END_RING;
mbed_official 467:4961165abe5d 437 }
mbed_official 467:4961165abe5d 438 }
mbed_official 467:4961165abe5d 439
mbed_official 467:4961165abe5d 440 LPC_ETHERNET->DMA_TRANS_DES_ADDR = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
mbed_official 467:4961165abe5d 441 }
mbed_official 467:4961165abe5d 442
mbed_official 467:4961165abe5d 443
mbed_official 467:4961165abe5d 444 static void rxdscr_init()
mbed_official 467:4961165abe5d 445 {
mbed_official 467:4961165abe5d 446 int i;
mbed_official 467:4961165abe5d 447
mbed_official 467:4961165abe5d 448 for(i = 0; i < NUM_RX_FRAG; i++) {
mbed_official 467:4961165abe5d 449 rxdesc[i].Status = TRDES_OWN_BIT;
mbed_official 467:4961165abe5d 450 rxdesc[i].Ctrl = ETH_FRAG_SIZE;
mbed_official 467:4961165abe5d 451 rxdesc[i].BufAddr1 = (uint32_t)&rxbuf[i];
mbed_official 467:4961165abe5d 452 if (i == (NUM_RX_FRAG - 1)) {
mbed_official 467:4961165abe5d 453 rxdesc[i].Ctrl |= RX_END_RING;
mbed_official 467:4961165abe5d 454 }
mbed_official 467:4961165abe5d 455 }
mbed_official 467:4961165abe5d 456
mbed_official 467:4961165abe5d 457 LPC_ETHERNET->DMA_REC_DES_ADDR = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
mbed_official 467:4961165abe5d 458 }
mbed_official 467:4961165abe5d 459
mbed_official 467:4961165abe5d 460 void ethernet_address(char *mac)
mbed_official 467:4961165abe5d 461 {
mbed_official 467:4961165abe5d 462 mbed_mac_address(mac);
mbed_official 256:76fd9a263045 463 }
mbed_official 256:76fd9a263045 464
mbed_official 467:4961165abe5d 465 void ethernet_set_link(int speed, int duplex)
mbed_official 467:4961165abe5d 466 {
mbed_official 467:4961165abe5d 467 volatile unsigned short phy_data;
mbed_official 467:4961165abe5d 468 int tout;
mbed_official 467:4961165abe5d 469
mbed_official 467:4961165abe5d 470 if((speed < 0) || (speed > 1)) {
mbed_official 467:4961165abe5d 471
mbed_official 467:4961165abe5d 472 phy_data = PHY_AUTO_NEG;
mbed_official 467:4961165abe5d 473
mbed_official 467:4961165abe5d 474 } else {
mbed_official 467:4961165abe5d 475
mbed_official 467:4961165abe5d 476 phy_data = (((unsigned short) speed << 13) |
mbed_official 467:4961165abe5d 477 ((unsigned short) duplex << 8));
mbed_official 467:4961165abe5d 478 }
mbed_official 467:4961165abe5d 479
mbed_official 467:4961165abe5d 480 phy_write(PHY_REG_BMCR, phy_data);
mbed_official 467:4961165abe5d 481
mbed_official 467:4961165abe5d 482 for(tout = 100; tout; tout--) {
mbed_official 467:4961165abe5d 483 __NOP(); /* A short delay */
mbed_official 467:4961165abe5d 484 }
mbed_official 467:4961165abe5d 485
mbed_official 467:4961165abe5d 486 switch(phy_id) {
mbed_official 467:4961165abe5d 487 case DP83848C_ID:
mbed_official 467:4961165abe5d 488
mbed_official 467:4961165abe5d 489 phy_data = phy_read(PHY_REG_STS);
mbed_official 467:4961165abe5d 490
mbed_official 467:4961165abe5d 491 if(phy_data & PHY_STS_DUPLEX) {
mbed_official 467:4961165abe5d 492 /* Full duplex is enabled. */
mbed_official 467:4961165abe5d 493 LPC_ETHERNET->MAC_CONFIG |= MAC_DUPLEX_MODE;
mbed_official 467:4961165abe5d 494 } else {
mbed_official 467:4961165abe5d 495 LPC_ETHERNET->MAC_CONFIG &= ~MAC_DUPLEX_MODE;
mbed_official 467:4961165abe5d 496 }
mbed_official 467:4961165abe5d 497
mbed_official 467:4961165abe5d 498 if(phy_data & PHY_STS_SPEED) {
mbed_official 467:4961165abe5d 499 LPC_ETHERNET->MAC_CONFIG &= ~SUPP_SPEED;
mbed_official 467:4961165abe5d 500 } else {
mbed_official 467:4961165abe5d 501 LPC_ETHERNET->MAC_CONFIG |= SUPP_SPEED;
mbed_official 467:4961165abe5d 502 }
mbed_official 467:4961165abe5d 503 break;
mbed_official 467:4961165abe5d 504
mbed_official 467:4961165abe5d 505 case LAN8720_ID:
mbed_official 467:4961165abe5d 506
mbed_official 467:4961165abe5d 507 for(tout = 100; tout; tout--) {
mbed_official 467:4961165abe5d 508 phy_data = phy_read(PHY_REG_BMSR);
mbed_official 467:4961165abe5d 509 if (phy_data & PHY_STS_DUPLEX)
mbed_official 467:4961165abe5d 510 break;
mbed_official 467:4961165abe5d 511 }
mbed_official 467:4961165abe5d 512
mbed_official 467:4961165abe5d 513 if (phy_data & PHY_STS_DUPLEX) {
mbed_official 467:4961165abe5d 514 /* Full duplex is enabled. */
mbed_official 467:4961165abe5d 515 LPC_ETHERNET->MAC_CONFIG |= MAC_DUPLEX_MODE;
mbed_official 467:4961165abe5d 516 } else {
mbed_official 467:4961165abe5d 517 LPC_ETHERNET->MAC_CONFIG &= ~MAC_DUPLEX_MODE;
mbed_official 467:4961165abe5d 518 }
mbed_official 467:4961165abe5d 519
mbed_official 467:4961165abe5d 520 if(phy_data & PHY_STS_SPEED) {
mbed_official 467:4961165abe5d 521 LPC_ETHERNET->MAC_CONFIG &= ~SUPP_SPEED;
mbed_official 467:4961165abe5d 522 } else {
mbed_official 467:4961165abe5d 523 LPC_ETHERNET->MAC_CONFIG |= SUPP_SPEED;
mbed_official 467:4961165abe5d 524 }
mbed_official 467:4961165abe5d 525 break;
mbed_official 467:4961165abe5d 526 }
mbed_official 256:76fd9a263045 527 }
mbed_official 467:4961165abe5d 528