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targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/system_stm32f4xx.c@464:04583941e294, 2015-02-04 (annotated)

Committer:
mbed_official
Date:
Wed Feb 04 09:30:08 2015 +0000
Revision:
464:04583941e294
Synchronized with git revision c8f933ba07bc7c72c3e5e997a9862ba21d33f89c



Full URL: https://github.com/mbedmicro/mbed/commit/c8f933ba07bc7c72c3e5e997a9862ba21d33f89c/



UBLOX_C029 - new target based on STM32F439

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 464:04583941e294 1 /**
mbed_official 464:04583941e294 2 ******************************************************************************
mbed_official 464:04583941e294 3 * @file system_stm32f4xx.c
mbed_official 464:04583941e294 4 * @author MCD Application Team
mbed_official 464:04583941e294 5 * @version V2.1.0
mbed_official 464:04583941e294 6 * @date 19-June-2014
mbed_official 464:04583941e294 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 464:04583941e294 8 *
mbed_official 464:04583941e294 9 * This file provides two functions and one global variable to be called from
mbed_official 464:04583941e294 10 * user application:
mbed_official 464:04583941e294 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 464:04583941e294 12 * before branch to main program. This call is made inside
mbed_official 464:04583941e294 13 * the "startup_stm32f4xx.s" file.
mbed_official 464:04583941e294 14 *
mbed_official 464:04583941e294 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 464:04583941e294 16 * by the user application to setup the SysTick
mbed_official 464:04583941e294 17 * timer or configure other parameters.
mbed_official 464:04583941e294 18 *
mbed_official 464:04583941e294 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 464:04583941e294 20 * be called whenever the core clock is changed
mbed_official 464:04583941e294 21 * during program execution.
mbed_official 464:04583941e294 22 *
mbed_official 464:04583941e294 23 * This file configures the system clock as follows:
mbed_official 464:04583941e294 24 *-----------------------------------------------------------------------------
mbed_official 464:04583941e294 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 464:04583941e294 26 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 464:04583941e294 27 * | 2- PLL_HSE_XTAL |
mbed_official 464:04583941e294 28 * | (external 8 MHz xtal) |
mbed_official 464:04583941e294 29 *-----------------------------------------------------------------------------
mbed_official 464:04583941e294 30 * SYSCLK(MHz) | 100 | 100
mbed_official 464:04583941e294 31 *-----------------------------------------------------------------------------
mbed_official 464:04583941e294 32 * AHBCLK (MHz) | 100 | 100
mbed_official 464:04583941e294 33 *-----------------------------------------------------------------------------
mbed_official 464:04583941e294 34 * APB1CLK (MHz) | 50 | 50
mbed_official 464:04583941e294 35 *-----------------------------------------------------------------------------
mbed_official 464:04583941e294 36 * APB2CLK (MHz) | 100 | 100
mbed_official 464:04583941e294 37 *-----------------------------------------------------------------------------
mbed_official 464:04583941e294 38 * USB capable (48 MHz precise clock) | NO | NO
mbed_official 464:04583941e294 39 *-----------------------------------------------------------------------------
mbed_official 464:04583941e294 40 ******************************************************************************
mbed_official 464:04583941e294 41 * @attention
mbed_official 464:04583941e294 42 *
mbed_official 464:04583941e294 43 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
mbed_official 464:04583941e294 44 *
mbed_official 464:04583941e294 45 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 464:04583941e294 46 * are permitted provided that the following conditions are met:
mbed_official 464:04583941e294 47 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 464:04583941e294 48 * this list of conditions and the following disclaimer.
mbed_official 464:04583941e294 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 464:04583941e294 50 * this list of conditions and the following disclaimer in the documentation
mbed_official 464:04583941e294 51 * and/or other materials provided with the distribution.
mbed_official 464:04583941e294 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 464:04583941e294 53 * may be used to endorse or promote products derived from this software
mbed_official 464:04583941e294 54 * without specific prior written permission.
mbed_official 464:04583941e294 55 *
mbed_official 464:04583941e294 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 464:04583941e294 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 464:04583941e294 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 464:04583941e294 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 464:04583941e294 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 464:04583941e294 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 464:04583941e294 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 464:04583941e294 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 464:04583941e294 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 464:04583941e294 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 464:04583941e294 66 *
mbed_official 464:04583941e294 67 ******************************************************************************
mbed_official 464:04583941e294 68 */
mbed_official 464:04583941e294 69
mbed_official 464:04583941e294 70 /** @addtogroup CMSIS
mbed_official 464:04583941e294 71 * @{
mbed_official 464:04583941e294 72 */
mbed_official 464:04583941e294 73
mbed_official 464:04583941e294 74 /** @addtogroup stm32f4xx_system
mbed_official 464:04583941e294 75 * @{
mbed_official 464:04583941e294 76 */
mbed_official 464:04583941e294 77
mbed_official 464:04583941e294 78 /** @addtogroup STM32F4xx_System_Private_Includes
mbed_official 464:04583941e294 79 * @{
mbed_official 464:04583941e294 80 */
mbed_official 464:04583941e294 81
mbed_official 464:04583941e294 82
mbed_official 464:04583941e294 83 #include "stm32f4xx.h"
mbed_official 464:04583941e294 84 #include "hal_tick.h"
mbed_official 464:04583941e294 85
mbed_official 464:04583941e294 86 #if !defined (HSE_VALUE)
mbed_official 464:04583941e294 87 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
mbed_official 464:04583941e294 88 #endif /* HSE_VALUE */
mbed_official 464:04583941e294 89
mbed_official 464:04583941e294 90 #if !defined (HSI_VALUE)
mbed_official 464:04583941e294 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 464:04583941e294 92 #endif /* HSI_VALUE */
mbed_official 464:04583941e294 93
mbed_official 464:04583941e294 94 /**
mbed_official 464:04583941e294 95 * @}
mbed_official 464:04583941e294 96 */
mbed_official 464:04583941e294 97
mbed_official 464:04583941e294 98 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
mbed_official 464:04583941e294 99 * @{
mbed_official 464:04583941e294 100 */
mbed_official 464:04583941e294 101
mbed_official 464:04583941e294 102 /**
mbed_official 464:04583941e294 103 * @}
mbed_official 464:04583941e294 104 */
mbed_official 464:04583941e294 105
mbed_official 464:04583941e294 106 /** @addtogroup STM32F4xx_System_Private_Defines
mbed_official 464:04583941e294 107 * @{
mbed_official 464:04583941e294 108 */
mbed_official 464:04583941e294 109
mbed_official 464:04583941e294 110 /************************* Miscellaneous Configuration ************************/
mbed_official 464:04583941e294 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
mbed_official 464:04583941e294 112 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
mbed_official 464:04583941e294 113 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 464:04583941e294 114 /* #define DATA_IN_ExtSRAM */
mbed_official 464:04583941e294 115 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 464:04583941e294 116
mbed_official 464:04583941e294 117 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 464:04583941e294 118 /* #define DATA_IN_ExtSDRAM */
mbed_official 464:04583941e294 119 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 464:04583941e294 120
mbed_official 464:04583941e294 121 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
mbed_official 464:04583941e294 122 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
mbed_official 464:04583941e294 123 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
mbed_official 464:04583941e294 124
mbed_official 464:04583941e294 125 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 464:04583941e294 126 Internal SRAM. */
mbed_official 464:04583941e294 127 /* #define VECT_TAB_SRAM */
mbed_official 464:04583941e294 128 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 464:04583941e294 129 This value must be a multiple of 0x200. */
mbed_official 464:04583941e294 130 /******************************************************************************/
mbed_official 464:04583941e294 131
mbed_official 464:04583941e294 132 /**
mbed_official 464:04583941e294 133 * @}
mbed_official 464:04583941e294 134 */
mbed_official 464:04583941e294 135
mbed_official 464:04583941e294 136 /** @addtogroup STM32F4xx_System_Private_Macros
mbed_official 464:04583941e294 137 * @{
mbed_official 464:04583941e294 138 */
mbed_official 464:04583941e294 139
mbed_official 464:04583941e294 140 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 464:04583941e294 141 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 464:04583941e294 142 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 464:04583941e294 143
mbed_official 464:04583941e294 144 /**
mbed_official 464:04583941e294 145 * @}
mbed_official 464:04583941e294 146 */
mbed_official 464:04583941e294 147
mbed_official 464:04583941e294 148 /** @addtogroup STM32F4xx_System_Private_Variables
mbed_official 464:04583941e294 149 * @{
mbed_official 464:04583941e294 150 */
mbed_official 464:04583941e294 151 /* This variable is updated in three ways:
mbed_official 464:04583941e294 152 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 464:04583941e294 153 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 464:04583941e294 154 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 464:04583941e294 155 Note: If you use this function to configure the system clock; then there
mbed_official 464:04583941e294 156 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 464:04583941e294 157 variable is updated automatically.
mbed_official 464:04583941e294 158 */
mbed_official 464:04583941e294 159 uint32_t SystemCoreClock = 16000000;
mbed_official 464:04583941e294 160 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 464:04583941e294 161
mbed_official 464:04583941e294 162 /**
mbed_official 464:04583941e294 163 * @}
mbed_official 464:04583941e294 164 */
mbed_official 464:04583941e294 165
mbed_official 464:04583941e294 166 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
mbed_official 464:04583941e294 167 * @{
mbed_official 464:04583941e294 168 */
mbed_official 464:04583941e294 169
mbed_official 464:04583941e294 170 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 464:04583941e294 171 static void SystemInit_ExtMemCtl(void);
mbed_official 464:04583941e294 172 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 464:04583941e294 173
mbed_official 464:04583941e294 174 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 464:04583941e294 175 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 464:04583941e294 176 #endif
mbed_official 464:04583941e294 177
mbed_official 464:04583941e294 178 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 464:04583941e294 179
mbed_official 464:04583941e294 180 /**
mbed_official 464:04583941e294 181 * @}
mbed_official 464:04583941e294 182 */
mbed_official 464:04583941e294 183
mbed_official 464:04583941e294 184 /** @addtogroup STM32F4xx_System_Private_Functions
mbed_official 464:04583941e294 185 * @{
mbed_official 464:04583941e294 186 */
mbed_official 464:04583941e294 187
mbed_official 464:04583941e294 188 /**
mbed_official 464:04583941e294 189 * @brief Setup the microcontroller system
mbed_official 464:04583941e294 190 * Initialize the FPU setting, vector table location and External memory
mbed_official 464:04583941e294 191 * configuration.
mbed_official 464:04583941e294 192 * @param None
mbed_official 464:04583941e294 193 * @retval None
mbed_official 464:04583941e294 194 */
mbed_official 464:04583941e294 195 void SystemInit(void)
mbed_official 464:04583941e294 196 {
mbed_official 464:04583941e294 197 /* FPU settings ------------------------------------------------------------*/
mbed_official 464:04583941e294 198 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 464:04583941e294 199 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 464:04583941e294 200 #endif
mbed_official 464:04583941e294 201 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 464:04583941e294 202 /* Set HSION bit */
mbed_official 464:04583941e294 203 RCC->CR |= (uint32_t)0x00000001;
mbed_official 464:04583941e294 204
mbed_official 464:04583941e294 205 /* Reset CFGR register */
mbed_official 464:04583941e294 206 RCC->CFGR = 0x00000000;
mbed_official 464:04583941e294 207
mbed_official 464:04583941e294 208 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 464:04583941e294 209 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 464:04583941e294 210
mbed_official 464:04583941e294 211 /* Reset PLLCFGR register */
mbed_official 464:04583941e294 212 RCC->PLLCFGR = 0x24003010;
mbed_official 464:04583941e294 213
mbed_official 464:04583941e294 214 /* Reset HSEBYP bit */
mbed_official 464:04583941e294 215 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 464:04583941e294 216
mbed_official 464:04583941e294 217 /* Disable all interrupts */
mbed_official 464:04583941e294 218 RCC->CIR = 0x00000000;
mbed_official 464:04583941e294 219
mbed_official 464:04583941e294 220 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 464:04583941e294 221 SystemInit_ExtMemCtl();
mbed_official 464:04583941e294 222 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 464:04583941e294 223
mbed_official 464:04583941e294 224 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 464:04583941e294 225 #ifdef VECT_TAB_SRAM
mbed_official 464:04583941e294 226 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 464:04583941e294 227 #else
mbed_official 464:04583941e294 228 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 464:04583941e294 229 #endif
mbed_official 464:04583941e294 230
mbed_official 464:04583941e294 231 /* Configure the Cube driver */
mbed_official 464:04583941e294 232 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
mbed_official 464:04583941e294 233 HAL_Init();
mbed_official 464:04583941e294 234
mbed_official 464:04583941e294 235 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 464:04583941e294 236 AHB/APBx prescalers and Flash settings */
mbed_official 464:04583941e294 237 SetSysClock();
mbed_official 464:04583941e294 238
mbed_official 464:04583941e294 239 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 464:04583941e294 240 TIM_MST_RESET_ON;
mbed_official 464:04583941e294 241 TIM_MST_RESET_OFF;
mbed_official 464:04583941e294 242 }
mbed_official 464:04583941e294 243
mbed_official 464:04583941e294 244 /**
mbed_official 464:04583941e294 245 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 464:04583941e294 246 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 464:04583941e294 247 * be used by the user application to setup the SysTick timer or configure
mbed_official 464:04583941e294 248 * other parameters.
mbed_official 464:04583941e294 249 *
mbed_official 464:04583941e294 250 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 464:04583941e294 251 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 464:04583941e294 252 * based on this variable will be incorrect.
mbed_official 464:04583941e294 253 *
mbed_official 464:04583941e294 254 * @note - The system frequency computed by this function is not the real
mbed_official 464:04583941e294 255 * frequency in the chip. It is calculated based on the predefined
mbed_official 464:04583941e294 256 * constant and the selected clock source:
mbed_official 464:04583941e294 257 *
mbed_official 464:04583941e294 258 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 464:04583941e294 259 *
mbed_official 464:04583941e294 260 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 464:04583941e294 261 *
mbed_official 464:04583941e294 262 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 464:04583941e294 263 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 464:04583941e294 264 *
mbed_official 464:04583941e294 265 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official 464:04583941e294 266 * 16 MHz) but the real value may vary depending on the variations
mbed_official 464:04583941e294 267 * in voltage and temperature.
mbed_official 464:04583941e294 268 *
mbed_official 464:04583941e294 269 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
mbed_official 464:04583941e294 270 * depends on the application requirements), user has to ensure that HSE_VALUE
mbed_official 464:04583941e294 271 * is same as the real frequency of the crystal used. Otherwise, this function
mbed_official 464:04583941e294 272 * may have wrong result.
mbed_official 464:04583941e294 273 *
mbed_official 464:04583941e294 274 * - The result of this function could be not correct when using fractional
mbed_official 464:04583941e294 275 * value for HSE crystal.
mbed_official 464:04583941e294 276 *
mbed_official 464:04583941e294 277 * @param None
mbed_official 464:04583941e294 278 * @retval None
mbed_official 464:04583941e294 279 */
mbed_official 464:04583941e294 280 void SystemCoreClockUpdate(void)
mbed_official 464:04583941e294 281 {
mbed_official 464:04583941e294 282 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official 464:04583941e294 283
mbed_official 464:04583941e294 284 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 464:04583941e294 285 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 464:04583941e294 286
mbed_official 464:04583941e294 287 switch (tmp)
mbed_official 464:04583941e294 288 {
mbed_official 464:04583941e294 289 case 0x00: /* HSI used as system clock source */
mbed_official 464:04583941e294 290 SystemCoreClock = HSI_VALUE;
mbed_official 464:04583941e294 291 break;
mbed_official 464:04583941e294 292 case 0x04: /* HSE used as system clock source */
mbed_official 464:04583941e294 293 SystemCoreClock = HSE_VALUE;
mbed_official 464:04583941e294 294 break;
mbed_official 464:04583941e294 295 case 0x08: /* PLL used as system clock source */
mbed_official 464:04583941e294 296
mbed_official 464:04583941e294 297 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official 464:04583941e294 298 SYSCLK = PLL_VCO / PLL_P
mbed_official 464:04583941e294 299 */
mbed_official 464:04583941e294 300 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official 464:04583941e294 301 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 464:04583941e294 302
mbed_official 464:04583941e294 303 if (pllsource != 0)
mbed_official 464:04583941e294 304 {
mbed_official 464:04583941e294 305 /* HSE used as PLL clock source */
mbed_official 464:04583941e294 306 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 464:04583941e294 307 }
mbed_official 464:04583941e294 308 else
mbed_official 464:04583941e294 309 {
mbed_official 464:04583941e294 310 /* HSI used as PLL clock source */
mbed_official 464:04583941e294 311 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 464:04583941e294 312 }
mbed_official 464:04583941e294 313
mbed_official 464:04583941e294 314 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official 464:04583941e294 315 SystemCoreClock = pllvco/pllp;
mbed_official 464:04583941e294 316 break;
mbed_official 464:04583941e294 317 default:
mbed_official 464:04583941e294 318 SystemCoreClock = HSI_VALUE;
mbed_official 464:04583941e294 319 break;
mbed_official 464:04583941e294 320 }
mbed_official 464:04583941e294 321 /* Compute HCLK frequency --------------------------------------------------*/
mbed_official 464:04583941e294 322 /* Get HCLK prescaler */
mbed_official 464:04583941e294 323 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 464:04583941e294 324 /* HCLK frequency */
mbed_official 464:04583941e294 325 SystemCoreClock >>= tmp;
mbed_official 464:04583941e294 326 }
mbed_official 464:04583941e294 327
mbed_official 464:04583941e294 328 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 464:04583941e294 329 /**
mbed_official 464:04583941e294 330 * @brief Setup the external memory controller.
mbed_official 464:04583941e294 331 * Called in startup_stm32f4xx.s before jump to main.
mbed_official 464:04583941e294 332 * This function configures the external memories (SRAM/SDRAM)
mbed_official 464:04583941e294 333 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official 464:04583941e294 334 * @param None
mbed_official 464:04583941e294 335 * @retval None
mbed_official 464:04583941e294 336 */
mbed_official 464:04583941e294 337 void SystemInit_ExtMemCtl(void)
mbed_official 464:04583941e294 338 {
mbed_official 464:04583941e294 339 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 464:04583941e294 340 #if defined (DATA_IN_ExtSDRAM)
mbed_official 464:04583941e294 341 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 464:04583941e294 342 register uint32_t index;
mbed_official 464:04583941e294 343
mbed_official 464:04583941e294 344 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 464:04583941e294 345 clock */
mbed_official 464:04583941e294 346 RCC->AHB1ENR |= 0x000001F8;
mbed_official 464:04583941e294 347
mbed_official 464:04583941e294 348 /* Connect PDx pins to FMC Alternate function */
mbed_official 464:04583941e294 349 GPIOD->AFR[0] = 0x000000CC;
mbed_official 464:04583941e294 350 GPIOD->AFR[1] = 0xCC000CCC;
mbed_official 464:04583941e294 351 /* Configure PDx pins in Alternate function mode */
mbed_official 464:04583941e294 352 GPIOD->MODER = 0xA02A000A;
mbed_official 464:04583941e294 353 /* Configure PDx pins speed to 50 MHz */
mbed_official 464:04583941e294 354 GPIOD->OSPEEDR = 0xA02A000A;
mbed_official 464:04583941e294 355 /* Configure PDx pins Output type to push-pull */
mbed_official 464:04583941e294 356 GPIOD->OTYPER = 0x00000000;
mbed_official 464:04583941e294 357 /* No pull-up, pull-down for PDx pins */
mbed_official 464:04583941e294 358 GPIOD->PUPDR = 0x00000000;
mbed_official 464:04583941e294 359
mbed_official 464:04583941e294 360 /* Connect PEx pins to FMC Alternate function */
mbed_official 464:04583941e294 361 GPIOE->AFR[0] = 0xC00000CC;
mbed_official 464:04583941e294 362 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 464:04583941e294 363 /* Configure PEx pins in Alternate function mode */
mbed_official 464:04583941e294 364 GPIOE->MODER = 0xAAAA800A;
mbed_official 464:04583941e294 365 /* Configure PEx pins speed to 50 MHz */
mbed_official 464:04583941e294 366 GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official 464:04583941e294 367 /* Configure PEx pins Output type to push-pull */
mbed_official 464:04583941e294 368 GPIOE->OTYPER = 0x00000000;
mbed_official 464:04583941e294 369 /* No pull-up, pull-down for PEx pins */
mbed_official 464:04583941e294 370 GPIOE->PUPDR = 0x00000000;
mbed_official 464:04583941e294 371
mbed_official 464:04583941e294 372 /* Connect PFx pins to FMC Alternate function */
mbed_official 464:04583941e294 373 GPIOF->AFR[0] = 0xCCCCCCCC;
mbed_official 464:04583941e294 374 GPIOF->AFR[1] = 0xCCCCCCCC;
mbed_official 464:04583941e294 375 /* Configure PFx pins in Alternate function mode */
mbed_official 464:04583941e294 376 GPIOF->MODER = 0xAA800AAA;
mbed_official 464:04583941e294 377 /* Configure PFx pins speed to 50 MHz */
mbed_official 464:04583941e294 378 GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official 464:04583941e294 379 /* Configure PFx pins Output type to push-pull */
mbed_official 464:04583941e294 380 GPIOF->OTYPER = 0x00000000;
mbed_official 464:04583941e294 381 /* No pull-up, pull-down for PFx pins */
mbed_official 464:04583941e294 382 GPIOF->PUPDR = 0x00000000;
mbed_official 464:04583941e294 383
mbed_official 464:04583941e294 384 /* Connect PGx pins to FMC Alternate function */
mbed_official 464:04583941e294 385 GPIOG->AFR[0] = 0xCCCCCCCC;
mbed_official 464:04583941e294 386 GPIOG->AFR[1] = 0xCCCCCCCC;
mbed_official 464:04583941e294 387 /* Configure PGx pins in Alternate function mode */
mbed_official 464:04583941e294 388 GPIOG->MODER = 0xAAAAAAAA;
mbed_official 464:04583941e294 389 /* Configure PGx pins speed to 50 MHz */
mbed_official 464:04583941e294 390 GPIOG->OSPEEDR = 0xAAAAAAAA;
mbed_official 464:04583941e294 391 /* Configure PGx pins Output type to push-pull */
mbed_official 464:04583941e294 392 GPIOG->OTYPER = 0x00000000;
mbed_official 464:04583941e294 393 /* No pull-up, pull-down for PGx pins */
mbed_official 464:04583941e294 394 GPIOG->PUPDR = 0x00000000;
mbed_official 464:04583941e294 395
mbed_official 464:04583941e294 396 /* Connect PHx pins to FMC Alternate function */
mbed_official 464:04583941e294 397 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 464:04583941e294 398 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 464:04583941e294 399 /* Configure PHx pins in Alternate function mode */
mbed_official 464:04583941e294 400 GPIOH->MODER = 0xAAAA08A0;
mbed_official 464:04583941e294 401 /* Configure PHx pins speed to 50 MHz */
mbed_official 464:04583941e294 402 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 464:04583941e294 403 /* Configure PHx pins Output type to push-pull */
mbed_official 464:04583941e294 404 GPIOH->OTYPER = 0x00000000;
mbed_official 464:04583941e294 405 /* No pull-up, pull-down for PHx pins */
mbed_official 464:04583941e294 406 GPIOH->PUPDR = 0x00000000;
mbed_official 464:04583941e294 407
mbed_official 464:04583941e294 408 /* Connect PIx pins to FMC Alternate function */
mbed_official 464:04583941e294 409 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 464:04583941e294 410 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 464:04583941e294 411 /* Configure PIx pins in Alternate function mode */
mbed_official 464:04583941e294 412 GPIOI->MODER = 0x0028AAAA;
mbed_official 464:04583941e294 413 /* Configure PIx pins speed to 50 MHz */
mbed_official 464:04583941e294 414 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 464:04583941e294 415 /* Configure PIx pins Output type to push-pull */
mbed_official 464:04583941e294 416 GPIOI->OTYPER = 0x00000000;
mbed_official 464:04583941e294 417 /* No pull-up, pull-down for PIx pins */
mbed_official 464:04583941e294 418 GPIOI->PUPDR = 0x00000000;
mbed_official 464:04583941e294 419
mbed_official 464:04583941e294 420 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 464:04583941e294 421 /* Enable the FMC interface clock */
mbed_official 464:04583941e294 422 RCC->AHB3ENR |= 0x00000001;
mbed_official 464:04583941e294 423
mbed_official 464:04583941e294 424 /* Configure and enable SDRAM bank1 */
mbed_official 464:04583941e294 425 FMC_Bank5_6->SDCR[0] = 0x000019E0;
mbed_official 464:04583941e294 426 FMC_Bank5_6->SDTR[0] = 0x01115351;
mbed_official 464:04583941e294 427
mbed_official 464:04583941e294 428 /* SDRAM initialization sequence */
mbed_official 464:04583941e294 429 /* Clock enable command */
mbed_official 464:04583941e294 430 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 464:04583941e294 431 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 464:04583941e294 432 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 464:04583941e294 433 {
mbed_official 464:04583941e294 434 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 464:04583941e294 435 }
mbed_official 464:04583941e294 436
mbed_official 464:04583941e294 437 /* Delay */
mbed_official 464:04583941e294 438 for (index = 0; index<1000; index++);
mbed_official 464:04583941e294 439
mbed_official 464:04583941e294 440 /* PALL command */
mbed_official 464:04583941e294 441 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 464:04583941e294 442 timeout = 0xFFFF;
mbed_official 464:04583941e294 443 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 464:04583941e294 444 {
mbed_official 464:04583941e294 445 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 464:04583941e294 446 }
mbed_official 464:04583941e294 447
mbed_official 464:04583941e294 448 /* Auto refresh command */
mbed_official 464:04583941e294 449 FMC_Bank5_6->SDCMR = 0x00000073;
mbed_official 464:04583941e294 450 timeout = 0xFFFF;
mbed_official 464:04583941e294 451 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 464:04583941e294 452 {
mbed_official 464:04583941e294 453 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 464:04583941e294 454 }
mbed_official 464:04583941e294 455
mbed_official 464:04583941e294 456 /* MRD register program */
mbed_official 464:04583941e294 457 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 464:04583941e294 458 timeout = 0xFFFF;
mbed_official 464:04583941e294 459 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 464:04583941e294 460 {
mbed_official 464:04583941e294 461 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 464:04583941e294 462 }
mbed_official 464:04583941e294 463
mbed_official 464:04583941e294 464 /* Set refresh count */
mbed_official 464:04583941e294 465 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 464:04583941e294 466 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
mbed_official 464:04583941e294 467
mbed_official 464:04583941e294 468 /* Disable write protection */
mbed_official 464:04583941e294 469 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 464:04583941e294 470 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 464:04583941e294 471 #endif /* DATA_IN_ExtSDRAM */
mbed_official 464:04583941e294 472 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 464:04583941e294 473
mbed_official 464:04583941e294 474 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 464:04583941e294 475 #if defined(DATA_IN_ExtSRAM)
mbed_official 464:04583941e294 476 /*-- GPIOs Configuration -----------------------------------------------------*/
mbed_official 464:04583941e294 477 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official 464:04583941e294 478 RCC->AHB1ENR |= 0x00000078;
mbed_official 464:04583941e294 479
mbed_official 464:04583941e294 480 /* Connect PDx pins to FMC Alternate function */
mbed_official 464:04583941e294 481 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 464:04583941e294 482 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 464:04583941e294 483 /* Configure PDx pins in Alternate function mode */
mbed_official 464:04583941e294 484 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 464:04583941e294 485 /* Configure PDx pins speed to 100 MHz */
mbed_official 464:04583941e294 486 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 464:04583941e294 487 /* Configure PDx pins Output type to push-pull */
mbed_official 464:04583941e294 488 GPIOD->OTYPER = 0x00000000;
mbed_official 464:04583941e294 489 /* No pull-up, pull-down for PDx pins */
mbed_official 464:04583941e294 490 GPIOD->PUPDR = 0x00000000;
mbed_official 464:04583941e294 491
mbed_official 464:04583941e294 492 /* Connect PEx pins to FMC Alternate function */
mbed_official 464:04583941e294 493 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 464:04583941e294 494 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 464:04583941e294 495 /* Configure PEx pins in Alternate function mode */
mbed_official 464:04583941e294 496 GPIOE->MODER = 0xAAAA828A;
mbed_official 464:04583941e294 497 /* Configure PEx pins speed to 100 MHz */
mbed_official 464:04583941e294 498 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 464:04583941e294 499 /* Configure PEx pins Output type to push-pull */
mbed_official 464:04583941e294 500 GPIOE->OTYPER = 0x00000000;
mbed_official 464:04583941e294 501 /* No pull-up, pull-down for PEx pins */
mbed_official 464:04583941e294 502 GPIOE->PUPDR = 0x00000000;
mbed_official 464:04583941e294 503
mbed_official 464:04583941e294 504 /* Connect PFx pins to FMC Alternate function */
mbed_official 464:04583941e294 505 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 464:04583941e294 506 GPIOF->AFR[1] = 0xCCCC0000;
mbed_official 464:04583941e294 507 /* Configure PFx pins in Alternate function mode */
mbed_official 464:04583941e294 508 GPIOF->MODER = 0xAA000AAA;
mbed_official 464:04583941e294 509 /* Configure PFx pins speed to 100 MHz */
mbed_official 464:04583941e294 510 GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official 464:04583941e294 511 /* Configure PFx pins Output type to push-pull */
mbed_official 464:04583941e294 512 GPIOF->OTYPER = 0x00000000;
mbed_official 464:04583941e294 513 /* No pull-up, pull-down for PFx pins */
mbed_official 464:04583941e294 514 GPIOF->PUPDR = 0x00000000;
mbed_official 464:04583941e294 515
mbed_official 464:04583941e294 516 /* Connect PGx pins to FMC Alternate function */
mbed_official 464:04583941e294 517 GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official 464:04583941e294 518 GPIOG->AFR[1] = 0x000000C0;
mbed_official 464:04583941e294 519 /* Configure PGx pins in Alternate function mode */
mbed_official 464:04583941e294 520 GPIOG->MODER = 0x00085AAA;
mbed_official 464:04583941e294 521 /* Configure PGx pins speed to 100 MHz */
mbed_official 464:04583941e294 522 GPIOG->OSPEEDR = 0x000CAFFF;
mbed_official 464:04583941e294 523 /* Configure PGx pins Output type to push-pull */
mbed_official 464:04583941e294 524 GPIOG->OTYPER = 0x00000000;
mbed_official 464:04583941e294 525 /* No pull-up, pull-down for PGx pins */
mbed_official 464:04583941e294 526 GPIOG->PUPDR = 0x00000000;
mbed_official 464:04583941e294 527
mbed_official 464:04583941e294 528 /*-- FMC/FSMC Configuration --------------------------------------------------*/
mbed_official 464:04583941e294 529 /* Enable the FMC/FSMC interface clock */
mbed_official 464:04583941e294 530 RCC->AHB3ENR |= 0x00000001;
mbed_official 464:04583941e294 531
mbed_official 464:04583941e294 532 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 464:04583941e294 533 /* Configure and enable Bank1_SRAM2 */
mbed_official 464:04583941e294 534 FMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 464:04583941e294 535 FMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 464:04583941e294 536 FMC_Bank1E->BWTR[2] = 0x0fffffff;
mbed_official 464:04583941e294 537 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 464:04583941e294 538
mbed_official 464:04583941e294 539 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 464:04583941e294 540 /* Configure and enable Bank1_SRAM2 */
mbed_official 464:04583941e294 541 FSMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 464:04583941e294 542 FSMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 464:04583941e294 543 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
mbed_official 464:04583941e294 544 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 464:04583941e294 545
mbed_official 464:04583941e294 546 #endif /* DATA_IN_ExtSRAM */
mbed_official 464:04583941e294 547 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 464:04583941e294 548 }
mbed_official 464:04583941e294 549 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 464:04583941e294 550
mbed_official 464:04583941e294 551 /**
mbed_official 464:04583941e294 552 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 464:04583941e294 553 * AHB/APBx prescalers and Flash settings
mbed_official 464:04583941e294 554 * @note This function should be called only once the RCC clock configuration
mbed_official 464:04583941e294 555 * is reset to the default reset state (done in SystemInit() function).
mbed_official 464:04583941e294 556 * @param None
mbed_official 464:04583941e294 557 * @retval None
mbed_official 464:04583941e294 558 */
mbed_official 464:04583941e294 559 void SetSysClock(void)
mbed_official 464:04583941e294 560 {
mbed_official 464:04583941e294 561 /* 1- Try to start with HSE and external clock */
mbed_official 464:04583941e294 562 #if USE_PLL_HSE_EXTC != 0
mbed_official 464:04583941e294 563 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 464:04583941e294 564 #endif
mbed_official 464:04583941e294 565 {
mbed_official 464:04583941e294 566 /* 2- If fail try to start with HSE and external xtal */
mbed_official 464:04583941e294 567 #if USE_PLL_HSE_XTAL != 0
mbed_official 464:04583941e294 568 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 464:04583941e294 569 #endif
mbed_official 464:04583941e294 570 {
mbed_official 464:04583941e294 571 /* 3- If fail start with HSI clock */
mbed_official 464:04583941e294 572 if (SetSysClock_PLL_HSI() == 0)
mbed_official 464:04583941e294 573 {
mbed_official 464:04583941e294 574 while(1)
mbed_official 464:04583941e294 575 {
mbed_official 464:04583941e294 576 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 464:04583941e294 577 }
mbed_official 464:04583941e294 578 }
mbed_official 464:04583941e294 579 }
mbed_official 464:04583941e294 580 }
mbed_official 464:04583941e294 581
mbed_official 464:04583941e294 582 /* Output clock on MCO2 pin(PC9) for debugging purpose */
mbed_official 464:04583941e294 583 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
mbed_official 464:04583941e294 584 }
mbed_official 464:04583941e294 585
mbed_official 464:04583941e294 586 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 464:04583941e294 587 /******************************************************************************/
mbed_official 464:04583941e294 588 /* PLL (clocked by HSE) used as System clock source */
mbed_official 464:04583941e294 589 /******************************************************************************/
mbed_official 464:04583941e294 590 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 464:04583941e294 591 {
mbed_official 464:04583941e294 592 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 464:04583941e294 593 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 464:04583941e294 594
mbed_official 464:04583941e294 595 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 464:04583941e294 596 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 464:04583941e294 597 regarding system frequency refer to product datasheet. */
mbed_official 464:04583941e294 598 __PWR_CLK_ENABLE();
mbed_official 464:04583941e294 599 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
mbed_official 464:04583941e294 600
mbed_official 464:04583941e294 601 /* Enable HSE oscillator and activate PLL with HSE as source */
mbed_official 464:04583941e294 602 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 464:04583941e294 603 if (bypass == 0)
mbed_official 464:04583941e294 604 {
mbed_official 464:04583941e294 605 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 464:04583941e294 606 }
mbed_official 464:04583941e294 607 else
mbed_official 464:04583941e294 608 {
mbed_official 464:04583941e294 609 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 464:04583941e294 610 }
mbed_official 464:04583941e294 611 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 464:04583941e294 612 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 464:04583941e294 613 //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
mbed_official 464:04583941e294 614 //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
mbed_official 464:04583941e294 615 RCC_OscInitStruct.PLL.PLLM = 4; // VCO input clock = 2 MHz (8 MHz / 4)
mbed_official 464:04583941e294 616 RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
mbed_official 464:04583941e294 617 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
mbed_official 464:04583941e294 618 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
mbed_official 464:04583941e294 619 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 464:04583941e294 620 {
mbed_official 464:04583941e294 621 return 0; // FAIL
mbed_official 464:04583941e294 622 }
mbed_official 464:04583941e294 623
mbed_official 464:04583941e294 624 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 464:04583941e294 625 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 464:04583941e294 626 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
mbed_official 464:04583941e294 627 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
mbed_official 464:04583941e294 628 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
mbed_official 464:04583941e294 629 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
mbed_official 464:04583941e294 630 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
mbed_official 464:04583941e294 631 {
mbed_official 464:04583941e294 632 return 0; // FAIL
mbed_official 464:04583941e294 633 }
mbed_official 464:04583941e294 634
mbed_official 464:04583941e294 635 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 464:04583941e294 636
mbed_official 464:04583941e294 637 //if (bypass == 0)
mbed_official 464:04583941e294 638 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
mbed_official 464:04583941e294 639 //else
mbed_official 464:04583941e294 640 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
mbed_official 464:04583941e294 641
mbed_official 464:04583941e294 642 return 1; // OK
mbed_official 464:04583941e294 643 }
mbed_official 464:04583941e294 644 #endif
mbed_official 464:04583941e294 645
mbed_official 464:04583941e294 646 /******************************************************************************/
mbed_official 464:04583941e294 647 /* PLL (clocked by HSI) used as System clock source */
mbed_official 464:04583941e294 648 /******************************************************************************/
mbed_official 464:04583941e294 649 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 464:04583941e294 650 {
mbed_official 464:04583941e294 651 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 464:04583941e294 652 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 464:04583941e294 653
mbed_official 464:04583941e294 654 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 464:04583941e294 655 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 464:04583941e294 656 regarding system frequency refer to product datasheet. */
mbed_official 464:04583941e294 657 __PWR_CLK_ENABLE();
mbed_official 464:04583941e294 658 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
mbed_official 464:04583941e294 659
mbed_official 464:04583941e294 660 /* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official 464:04583941e294 661 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 464:04583941e294 662 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 464:04583941e294 663 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 464:04583941e294 664 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 464:04583941e294 665 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 464:04583941e294 666 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 464:04583941e294 667 //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
mbed_official 464:04583941e294 668 //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
mbed_official 464:04583941e294 669 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
mbed_official 464:04583941e294 670 RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
mbed_official 464:04583941e294 671 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
mbed_official 464:04583941e294 672 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
mbed_official 464:04583941e294 673 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 464:04583941e294 674 {
mbed_official 464:04583941e294 675 return 0; // FAIL
mbed_official 464:04583941e294 676 }
mbed_official 464:04583941e294 677
mbed_official 464:04583941e294 678 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 464:04583941e294 679 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 464:04583941e294 680 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
mbed_official 464:04583941e294 681 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
mbed_official 464:04583941e294 682 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
mbed_official 464:04583941e294 683 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
mbed_official 464:04583941e294 684 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
mbed_official 464:04583941e294 685 {
mbed_official 464:04583941e294 686 return 0; // FAIL
mbed_official 464:04583941e294 687 }
mbed_official 464:04583941e294 688
mbed_official 464:04583941e294 689 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 464:04583941e294 690 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 464:04583941e294 691
mbed_official 464:04583941e294 692 return 1; // OK
mbed_official 464:04583941e294 693 }
mbed_official 464:04583941e294 694
mbed_official 464:04583941e294 695 /**
mbed_official 464:04583941e294 696 * @}
mbed_official 464:04583941e294 697 */
mbed_official 464:04583941e294 698
mbed_official 464:04583941e294 699 /**
mbed_official 464:04583941e294 700 * @}
mbed_official 464:04583941e294 701 */
mbed_official 464:04583941e294 702
mbed_official 464:04583941e294 703 /**
mbed_official 464:04583941e294 704 * @}
mbed_official 464:04583941e294 705 */
mbed_official 464:04583941e294 706 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/