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targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_UBLOX_C029/stm32f439xx.h@464:04583941e294, 2015-02-04 (annotated)

Committer:
mbed_official
Date:
Wed Feb 04 09:30:08 2015 +0000
Revision:
464:04583941e294
Synchronized with git revision c8f933ba07bc7c72c3e5e997a9862ba21d33f89c



Full URL: https://github.com/mbedmicro/mbed/commit/c8f933ba07bc7c72c3e5e997a9862ba21d33f89c/



UBLOX_C029 - new target based on STM32F439

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UserRevisionLine numberNew contents of line
mbed_official 464:04583941e294 1 /**
mbed_official 464:04583941e294 2 ******************************************************************************
mbed_official 464:04583941e294 3 * @file stm32f439xx.h
mbed_official 464:04583941e294 4 * @author MCD Application Team
mbed_official 464:04583941e294 5 * @version V2.1.0
mbed_official 464:04583941e294 6 * @date 19-June-2014
mbed_official 464:04583941e294 7 * @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File.
mbed_official 464:04583941e294 8 *
mbed_official 464:04583941e294 9 * This file contains:
mbed_official 464:04583941e294 10 * - Data structures and the address mapping for all peripherals
mbed_official 464:04583941e294 11 * - Peripheral's registers declarations and bits definition
mbed_official 464:04583941e294 12 * - Macros to access peripheral’s registers hardware
mbed_official 464:04583941e294 13 *
mbed_official 464:04583941e294 14 ******************************************************************************
mbed_official 464:04583941e294 15 * @attention
mbed_official 464:04583941e294 16 *
mbed_official 464:04583941e294 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 464:04583941e294 18 *
mbed_official 464:04583941e294 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 464:04583941e294 20 * are permitted provided that the following conditions are met:
mbed_official 464:04583941e294 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 464:04583941e294 22 * this list of conditions and the following disclaimer.
mbed_official 464:04583941e294 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 464:04583941e294 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 464:04583941e294 25 * and/or other materials provided with the distribution.
mbed_official 464:04583941e294 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 464:04583941e294 27 * may be used to endorse or promote products derived from this software
mbed_official 464:04583941e294 28 * without specific prior written permission.
mbed_official 464:04583941e294 29 *
mbed_official 464:04583941e294 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 464:04583941e294 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 464:04583941e294 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 464:04583941e294 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 464:04583941e294 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 464:04583941e294 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 464:04583941e294 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 464:04583941e294 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 464:04583941e294 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 464:04583941e294 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 464:04583941e294 40 *
mbed_official 464:04583941e294 41 ******************************************************************************
mbed_official 464:04583941e294 42 */
mbed_official 464:04583941e294 43
mbed_official 464:04583941e294 44 /** @addtogroup CMSIS_Device
mbed_official 464:04583941e294 45 * @{
mbed_official 464:04583941e294 46 */
mbed_official 464:04583941e294 47
mbed_official 464:04583941e294 48 /** @addtogroup stm32f439xx
mbed_official 464:04583941e294 49 * @{
mbed_official 464:04583941e294 50 */
mbed_official 464:04583941e294 51
mbed_official 464:04583941e294 52 #ifndef __STM32F439xx_H
mbed_official 464:04583941e294 53 #define __STM32F439xx_H
mbed_official 464:04583941e294 54
mbed_official 464:04583941e294 55 #ifdef __cplusplus
mbed_official 464:04583941e294 56 extern "C" {
mbed_official 464:04583941e294 57 #endif /* __cplusplus */
mbed_official 464:04583941e294 58
mbed_official 464:04583941e294 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 464:04583941e294 60 * @{
mbed_official 464:04583941e294 61 */
mbed_official 464:04583941e294 62
mbed_official 464:04583941e294 63 /**
mbed_official 464:04583941e294 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 464:04583941e294 65 */
mbed_official 464:04583941e294 66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
mbed_official 464:04583941e294 67 #define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */
mbed_official 464:04583941e294 68 #define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
mbed_official 464:04583941e294 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 464:04583941e294 70 #define __FPU_PRESENT 1 /*!< FPU present */
mbed_official 464:04583941e294 71
mbed_official 464:04583941e294 72 /**
mbed_official 464:04583941e294 73 * @}
mbed_official 464:04583941e294 74 */
mbed_official 464:04583941e294 75
mbed_official 464:04583941e294 76 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 464:04583941e294 77 * @{
mbed_official 464:04583941e294 78 */
mbed_official 464:04583941e294 79
mbed_official 464:04583941e294 80 /**
mbed_official 464:04583941e294 81 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
mbed_official 464:04583941e294 82 * in @ref Library_configuration_section
mbed_official 464:04583941e294 83 */
mbed_official 464:04583941e294 84 typedef enum
mbed_official 464:04583941e294 85 {
mbed_official 464:04583941e294 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 464:04583941e294 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 464:04583941e294 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 464:04583941e294 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 464:04583941e294 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 464:04583941e294 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 464:04583941e294 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 464:04583941e294 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 464:04583941e294 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 464:04583941e294 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 464:04583941e294 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 464:04583941e294 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 464:04583941e294 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 464:04583941e294 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
mbed_official 464:04583941e294 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 464:04583941e294 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 464:04583941e294 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 464:04583941e294 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 464:04583941e294 104 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 464:04583941e294 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 464:04583941e294 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 464:04583941e294 107 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
mbed_official 464:04583941e294 108 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
mbed_official 464:04583941e294 109 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
mbed_official 464:04583941e294 110 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
mbed_official 464:04583941e294 111 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
mbed_official 464:04583941e294 112 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
mbed_official 464:04583941e294 113 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
mbed_official 464:04583941e294 114 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
mbed_official 464:04583941e294 115 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
mbed_official 464:04583941e294 116 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
mbed_official 464:04583941e294 117 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
mbed_official 464:04583941e294 118 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
mbed_official 464:04583941e294 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 464:04583941e294 120 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
mbed_official 464:04583941e294 121 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
mbed_official 464:04583941e294 122 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
mbed_official 464:04583941e294 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 464:04583941e294 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 464:04583941e294 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 464:04583941e294 126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 464:04583941e294 127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 464:04583941e294 128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 464:04583941e294 129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 464:04583941e294 130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 464:04583941e294 131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 464:04583941e294 132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 464:04583941e294 133 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 464:04583941e294 134 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 464:04583941e294 135 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 464:04583941e294 136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 464:04583941e294 137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 464:04583941e294 138 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
mbed_official 464:04583941e294 139 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
mbed_official 464:04583941e294 140 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
mbed_official 464:04583941e294 141 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
mbed_official 464:04583941e294 142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
mbed_official 464:04583941e294 143 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
mbed_official 464:04583941e294 144 FMC_IRQn = 48, /*!< FMC global Interrupt */
mbed_official 464:04583941e294 145 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
mbed_official 464:04583941e294 146 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
mbed_official 464:04583941e294 147 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 464:04583941e294 148 UART4_IRQn = 52, /*!< UART4 global Interrupt */
mbed_official 464:04583941e294 149 UART5_IRQn = 53, /*!< UART5 global Interrupt */
mbed_official 464:04583941e294 150 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
mbed_official 464:04583941e294 151 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
mbed_official 464:04583941e294 152 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
mbed_official 464:04583941e294 153 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
mbed_official 464:04583941e294 154 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
mbed_official 464:04583941e294 155 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
mbed_official 464:04583941e294 156 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
mbed_official 464:04583941e294 157 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
mbed_official 464:04583941e294 158 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
mbed_official 464:04583941e294 159 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
mbed_official 464:04583941e294 160 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
mbed_official 464:04583941e294 161 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
mbed_official 464:04583941e294 162 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
mbed_official 464:04583941e294 163 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
mbed_official 464:04583941e294 164 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
mbed_official 464:04583941e294 165 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
mbed_official 464:04583941e294 166 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
mbed_official 464:04583941e294 167 USART6_IRQn = 71, /*!< USART6 global interrupt */
mbed_official 464:04583941e294 168 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
mbed_official 464:04583941e294 169 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
mbed_official 464:04583941e294 170 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
mbed_official 464:04583941e294 171 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
mbed_official 464:04583941e294 172 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
mbed_official 464:04583941e294 173 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
mbed_official 464:04583941e294 174 DCMI_IRQn = 78, /*!< DCMI global interrupt */
mbed_official 464:04583941e294 175 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
mbed_official 464:04583941e294 176 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
mbed_official 464:04583941e294 177 FPU_IRQn = 81, /*!< FPU global interrupt */
mbed_official 464:04583941e294 178 UART7_IRQn = 82, /*!< UART7 global interrupt */
mbed_official 464:04583941e294 179 UART8_IRQn = 83, /*!< UART8 global interrupt */
mbed_official 464:04583941e294 180 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
mbed_official 464:04583941e294 181 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
mbed_official 464:04583941e294 182 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
mbed_official 464:04583941e294 183 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
mbed_official 464:04583941e294 184 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
mbed_official 464:04583941e294 185 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
mbed_official 464:04583941e294 186 DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
mbed_official 464:04583941e294 187 } IRQn_Type;
mbed_official 464:04583941e294 188
mbed_official 464:04583941e294 189 /**
mbed_official 464:04583941e294 190 * @}
mbed_official 464:04583941e294 191 */
mbed_official 464:04583941e294 192
mbed_official 464:04583941e294 193 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 464:04583941e294 194 #include "system_stm32f4xx.h"
mbed_official 464:04583941e294 195 #include <stdint.h>
mbed_official 464:04583941e294 196
mbed_official 464:04583941e294 197 /** @addtogroup Peripheral_registers_structures
mbed_official 464:04583941e294 198 * @{
mbed_official 464:04583941e294 199 */
mbed_official 464:04583941e294 200
mbed_official 464:04583941e294 201 /**
mbed_official 464:04583941e294 202 * @brief Analog to Digital Converter
mbed_official 464:04583941e294 203 */
mbed_official 464:04583941e294 204
mbed_official 464:04583941e294 205 typedef struct
mbed_official 464:04583941e294 206 {
mbed_official 464:04583941e294 207 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 464:04583941e294 208 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 464:04583941e294 209 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 464:04583941e294 210 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 464:04583941e294 211 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 464:04583941e294 212 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
mbed_official 464:04583941e294 213 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
mbed_official 464:04583941e294 214 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
mbed_official 464:04583941e294 215 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
mbed_official 464:04583941e294 216 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
mbed_official 464:04583941e294 217 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
mbed_official 464:04583941e294 218 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
mbed_official 464:04583941e294 219 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
mbed_official 464:04583941e294 220 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
mbed_official 464:04583941e294 221 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
mbed_official 464:04583941e294 222 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
mbed_official 464:04583941e294 223 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
mbed_official 464:04583941e294 224 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
mbed_official 464:04583941e294 225 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
mbed_official 464:04583941e294 226 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
mbed_official 464:04583941e294 227 } ADC_TypeDef;
mbed_official 464:04583941e294 228
mbed_official 464:04583941e294 229 typedef struct
mbed_official 464:04583941e294 230 {
mbed_official 464:04583941e294 231 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 464:04583941e294 232 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 464:04583941e294 233 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 464:04583941e294 234 AND triple modes, Address offset: ADC1 base address + 0x308 */
mbed_official 464:04583941e294 235 } ADC_Common_TypeDef;
mbed_official 464:04583941e294 236
mbed_official 464:04583941e294 237
mbed_official 464:04583941e294 238 /**
mbed_official 464:04583941e294 239 * @brief Controller Area Network TxMailBox
mbed_official 464:04583941e294 240 */
mbed_official 464:04583941e294 241
mbed_official 464:04583941e294 242 typedef struct
mbed_official 464:04583941e294 243 {
mbed_official 464:04583941e294 244 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 464:04583941e294 245 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 464:04583941e294 246 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 464:04583941e294 247 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 464:04583941e294 248 } CAN_TxMailBox_TypeDef;
mbed_official 464:04583941e294 249
mbed_official 464:04583941e294 250 /**
mbed_official 464:04583941e294 251 * @brief Controller Area Network FIFOMailBox
mbed_official 464:04583941e294 252 */
mbed_official 464:04583941e294 253
mbed_official 464:04583941e294 254 typedef struct
mbed_official 464:04583941e294 255 {
mbed_official 464:04583941e294 256 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 464:04583941e294 257 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 464:04583941e294 258 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 464:04583941e294 259 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 464:04583941e294 260 } CAN_FIFOMailBox_TypeDef;
mbed_official 464:04583941e294 261
mbed_official 464:04583941e294 262 /**
mbed_official 464:04583941e294 263 * @brief Controller Area Network FilterRegister
mbed_official 464:04583941e294 264 */
mbed_official 464:04583941e294 265
mbed_official 464:04583941e294 266 typedef struct
mbed_official 464:04583941e294 267 {
mbed_official 464:04583941e294 268 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 464:04583941e294 269 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 464:04583941e294 270 } CAN_FilterRegister_TypeDef;
mbed_official 464:04583941e294 271
mbed_official 464:04583941e294 272 /**
mbed_official 464:04583941e294 273 * @brief Controller Area Network
mbed_official 464:04583941e294 274 */
mbed_official 464:04583941e294 275
mbed_official 464:04583941e294 276 typedef struct
mbed_official 464:04583941e294 277 {
mbed_official 464:04583941e294 278 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 464:04583941e294 279 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 464:04583941e294 280 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 464:04583941e294 281 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 464:04583941e294 282 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 464:04583941e294 283 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 464:04583941e294 284 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 464:04583941e294 285 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 464:04583941e294 286 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 464:04583941e294 287 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 464:04583941e294 288 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 464:04583941e294 289 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 464:04583941e294 290 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 464:04583941e294 291 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 464:04583941e294 292 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 464:04583941e294 293 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 464:04583941e294 294 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 464:04583941e294 295 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 464:04583941e294 296 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 464:04583941e294 297 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 464:04583941e294 298 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 464:04583941e294 299 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 464:04583941e294 300 } CAN_TypeDef;
mbed_official 464:04583941e294 301
mbed_official 464:04583941e294 302 /**
mbed_official 464:04583941e294 303 * @brief CRC calculation unit
mbed_official 464:04583941e294 304 */
mbed_official 464:04583941e294 305
mbed_official 464:04583941e294 306 typedef struct
mbed_official 464:04583941e294 307 {
mbed_official 464:04583941e294 308 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 464:04583941e294 309 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 464:04583941e294 310 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 464:04583941e294 311 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 464:04583941e294 312 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 464:04583941e294 313 } CRC_TypeDef;
mbed_official 464:04583941e294 314
mbed_official 464:04583941e294 315 /**
mbed_official 464:04583941e294 316 * @brief Digital to Analog Converter
mbed_official 464:04583941e294 317 */
mbed_official 464:04583941e294 318
mbed_official 464:04583941e294 319 typedef struct
mbed_official 464:04583941e294 320 {
mbed_official 464:04583941e294 321 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 464:04583941e294 322 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 464:04583941e294 323 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 464:04583941e294 324 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 464:04583941e294 325 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 464:04583941e294 326 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 464:04583941e294 327 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 464:04583941e294 328 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 464:04583941e294 329 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 464:04583941e294 330 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 464:04583941e294 331 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 464:04583941e294 332 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 464:04583941e294 333 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 464:04583941e294 334 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 464:04583941e294 335 } DAC_TypeDef;
mbed_official 464:04583941e294 336
mbed_official 464:04583941e294 337 /**
mbed_official 464:04583941e294 338 * @brief Debug MCU
mbed_official 464:04583941e294 339 */
mbed_official 464:04583941e294 340
mbed_official 464:04583941e294 341 typedef struct
mbed_official 464:04583941e294 342 {
mbed_official 464:04583941e294 343 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 464:04583941e294 344 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 464:04583941e294 345 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 464:04583941e294 346 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 464:04583941e294 347 }DBGMCU_TypeDef;
mbed_official 464:04583941e294 348
mbed_official 464:04583941e294 349 /**
mbed_official 464:04583941e294 350 * @brief DCMI
mbed_official 464:04583941e294 351 */
mbed_official 464:04583941e294 352
mbed_official 464:04583941e294 353 typedef struct
mbed_official 464:04583941e294 354 {
mbed_official 464:04583941e294 355 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
mbed_official 464:04583941e294 356 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
mbed_official 464:04583941e294 357 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
mbed_official 464:04583941e294 358 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
mbed_official 464:04583941e294 359 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
mbed_official 464:04583941e294 360 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
mbed_official 464:04583941e294 361 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
mbed_official 464:04583941e294 362 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
mbed_official 464:04583941e294 363 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
mbed_official 464:04583941e294 364 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
mbed_official 464:04583941e294 365 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
mbed_official 464:04583941e294 366 } DCMI_TypeDef;
mbed_official 464:04583941e294 367
mbed_official 464:04583941e294 368 /**
mbed_official 464:04583941e294 369 * @brief DMA Controller
mbed_official 464:04583941e294 370 */
mbed_official 464:04583941e294 371
mbed_official 464:04583941e294 372 typedef struct
mbed_official 464:04583941e294 373 {
mbed_official 464:04583941e294 374 __IO uint32_t CR; /*!< DMA stream x configuration register */
mbed_official 464:04583941e294 375 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
mbed_official 464:04583941e294 376 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
mbed_official 464:04583941e294 377 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
mbed_official 464:04583941e294 378 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
mbed_official 464:04583941e294 379 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
mbed_official 464:04583941e294 380 } DMA_Stream_TypeDef;
mbed_official 464:04583941e294 381
mbed_official 464:04583941e294 382 typedef struct
mbed_official 464:04583941e294 383 {
mbed_official 464:04583941e294 384 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
mbed_official 464:04583941e294 385 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
mbed_official 464:04583941e294 386 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
mbed_official 464:04583941e294 387 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
mbed_official 464:04583941e294 388 } DMA_TypeDef;
mbed_official 464:04583941e294 389
mbed_official 464:04583941e294 390 /**
mbed_official 464:04583941e294 391 * @brief DMA2D Controller
mbed_official 464:04583941e294 392 */
mbed_official 464:04583941e294 393
mbed_official 464:04583941e294 394 typedef struct
mbed_official 464:04583941e294 395 {
mbed_official 464:04583941e294 396 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
mbed_official 464:04583941e294 397 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
mbed_official 464:04583941e294 398 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
mbed_official 464:04583941e294 399 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
mbed_official 464:04583941e294 400 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
mbed_official 464:04583941e294 401 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
mbed_official 464:04583941e294 402 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
mbed_official 464:04583941e294 403 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
mbed_official 464:04583941e294 404 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
mbed_official 464:04583941e294 405 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
mbed_official 464:04583941e294 406 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
mbed_official 464:04583941e294 407 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
mbed_official 464:04583941e294 408 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
mbed_official 464:04583941e294 409 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
mbed_official 464:04583941e294 410 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
mbed_official 464:04583941e294 411 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
mbed_official 464:04583941e294 412 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
mbed_official 464:04583941e294 413 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
mbed_official 464:04583941e294 414 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
mbed_official 464:04583941e294 415 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
mbed_official 464:04583941e294 416 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
mbed_official 464:04583941e294 417 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
mbed_official 464:04583941e294 418 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
mbed_official 464:04583941e294 419 } DMA2D_TypeDef;
mbed_official 464:04583941e294 420
mbed_official 464:04583941e294 421 /**
mbed_official 464:04583941e294 422 * @brief Ethernet MAC
mbed_official 464:04583941e294 423 */
mbed_official 464:04583941e294 424
mbed_official 464:04583941e294 425 typedef struct
mbed_official 464:04583941e294 426 {
mbed_official 464:04583941e294 427 __IO uint32_t MACCR;
mbed_official 464:04583941e294 428 __IO uint32_t MACFFR;
mbed_official 464:04583941e294 429 __IO uint32_t MACHTHR;
mbed_official 464:04583941e294 430 __IO uint32_t MACHTLR;
mbed_official 464:04583941e294 431 __IO uint32_t MACMIIAR;
mbed_official 464:04583941e294 432 __IO uint32_t MACMIIDR;
mbed_official 464:04583941e294 433 __IO uint32_t MACFCR;
mbed_official 464:04583941e294 434 __IO uint32_t MACVLANTR; /* 8 */
mbed_official 464:04583941e294 435 uint32_t RESERVED0[2];
mbed_official 464:04583941e294 436 __IO uint32_t MACRWUFFR; /* 11 */
mbed_official 464:04583941e294 437 __IO uint32_t MACPMTCSR;
mbed_official 464:04583941e294 438 uint32_t RESERVED1[2];
mbed_official 464:04583941e294 439 __IO uint32_t MACSR; /* 15 */
mbed_official 464:04583941e294 440 __IO uint32_t MACIMR;
mbed_official 464:04583941e294 441 __IO uint32_t MACA0HR;
mbed_official 464:04583941e294 442 __IO uint32_t MACA0LR;
mbed_official 464:04583941e294 443 __IO uint32_t MACA1HR;
mbed_official 464:04583941e294 444 __IO uint32_t MACA1LR;
mbed_official 464:04583941e294 445 __IO uint32_t MACA2HR;
mbed_official 464:04583941e294 446 __IO uint32_t MACA2LR;
mbed_official 464:04583941e294 447 __IO uint32_t MACA3HR;
mbed_official 464:04583941e294 448 __IO uint32_t MACA3LR; /* 24 */
mbed_official 464:04583941e294 449 uint32_t RESERVED2[40];
mbed_official 464:04583941e294 450 __IO uint32_t MMCCR; /* 65 */
mbed_official 464:04583941e294 451 __IO uint32_t MMCRIR;
mbed_official 464:04583941e294 452 __IO uint32_t MMCTIR;
mbed_official 464:04583941e294 453 __IO uint32_t MMCRIMR;
mbed_official 464:04583941e294 454 __IO uint32_t MMCTIMR; /* 69 */
mbed_official 464:04583941e294 455 uint32_t RESERVED3[14];
mbed_official 464:04583941e294 456 __IO uint32_t MMCTGFSCCR; /* 84 */
mbed_official 464:04583941e294 457 __IO uint32_t MMCTGFMSCCR;
mbed_official 464:04583941e294 458 uint32_t RESERVED4[5];
mbed_official 464:04583941e294 459 __IO uint32_t MMCTGFCR;
mbed_official 464:04583941e294 460 uint32_t RESERVED5[10];
mbed_official 464:04583941e294 461 __IO uint32_t MMCRFCECR;
mbed_official 464:04583941e294 462 __IO uint32_t MMCRFAECR;
mbed_official 464:04583941e294 463 uint32_t RESERVED6[10];
mbed_official 464:04583941e294 464 __IO uint32_t MMCRGUFCR;
mbed_official 464:04583941e294 465 uint32_t RESERVED7[334];
mbed_official 464:04583941e294 466 __IO uint32_t PTPTSCR;
mbed_official 464:04583941e294 467 __IO uint32_t PTPSSIR;
mbed_official 464:04583941e294 468 __IO uint32_t PTPTSHR;
mbed_official 464:04583941e294 469 __IO uint32_t PTPTSLR;
mbed_official 464:04583941e294 470 __IO uint32_t PTPTSHUR;
mbed_official 464:04583941e294 471 __IO uint32_t PTPTSLUR;
mbed_official 464:04583941e294 472 __IO uint32_t PTPTSAR;
mbed_official 464:04583941e294 473 __IO uint32_t PTPTTHR;
mbed_official 464:04583941e294 474 __IO uint32_t PTPTTLR;
mbed_official 464:04583941e294 475 __IO uint32_t RESERVED8;
mbed_official 464:04583941e294 476 __IO uint32_t PTPTSSR;
mbed_official 464:04583941e294 477 uint32_t RESERVED9[565];
mbed_official 464:04583941e294 478 __IO uint32_t DMABMR;
mbed_official 464:04583941e294 479 __IO uint32_t DMATPDR;
mbed_official 464:04583941e294 480 __IO uint32_t DMARPDR;
mbed_official 464:04583941e294 481 __IO uint32_t DMARDLAR;
mbed_official 464:04583941e294 482 __IO uint32_t DMATDLAR;
mbed_official 464:04583941e294 483 __IO uint32_t DMASR;
mbed_official 464:04583941e294 484 __IO uint32_t DMAOMR;
mbed_official 464:04583941e294 485 __IO uint32_t DMAIER;
mbed_official 464:04583941e294 486 __IO uint32_t DMAMFBOCR;
mbed_official 464:04583941e294 487 __IO uint32_t DMARSWTR;
mbed_official 464:04583941e294 488 uint32_t RESERVED10[8];
mbed_official 464:04583941e294 489 __IO uint32_t DMACHTDR;
mbed_official 464:04583941e294 490 __IO uint32_t DMACHRDR;
mbed_official 464:04583941e294 491 __IO uint32_t DMACHTBAR;
mbed_official 464:04583941e294 492 __IO uint32_t DMACHRBAR;
mbed_official 464:04583941e294 493 } ETH_TypeDef;
mbed_official 464:04583941e294 494
mbed_official 464:04583941e294 495 /**
mbed_official 464:04583941e294 496 * @brief External Interrupt/Event Controller
mbed_official 464:04583941e294 497 */
mbed_official 464:04583941e294 498
mbed_official 464:04583941e294 499 typedef struct
mbed_official 464:04583941e294 500 {
mbed_official 464:04583941e294 501 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 464:04583941e294 502 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 464:04583941e294 503 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 464:04583941e294 504 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 464:04583941e294 505 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 464:04583941e294 506 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 464:04583941e294 507 } EXTI_TypeDef;
mbed_official 464:04583941e294 508
mbed_official 464:04583941e294 509 /**
mbed_official 464:04583941e294 510 * @brief FLASH Registers
mbed_official 464:04583941e294 511 */
mbed_official 464:04583941e294 512
mbed_official 464:04583941e294 513 typedef struct
mbed_official 464:04583941e294 514 {
mbed_official 464:04583941e294 515 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 464:04583941e294 516 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 464:04583941e294 517 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 464:04583941e294 518 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 464:04583941e294 519 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 464:04583941e294 520 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
mbed_official 464:04583941e294 521 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
mbed_official 464:04583941e294 522 } FLASH_TypeDef;
mbed_official 464:04583941e294 523
mbed_official 464:04583941e294 524 /**
mbed_official 464:04583941e294 525 * @brief Flexible Memory Controller
mbed_official 464:04583941e294 526 */
mbed_official 464:04583941e294 527
mbed_official 464:04583941e294 528 typedef struct
mbed_official 464:04583941e294 529 {
mbed_official 464:04583941e294 530 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
mbed_official 464:04583941e294 531 } FMC_Bank1_TypeDef;
mbed_official 464:04583941e294 532
mbed_official 464:04583941e294 533 /**
mbed_official 464:04583941e294 534 * @brief Flexible Memory Controller Bank1E
mbed_official 464:04583941e294 535 */
mbed_official 464:04583941e294 536
mbed_official 464:04583941e294 537 typedef struct
mbed_official 464:04583941e294 538 {
mbed_official 464:04583941e294 539 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
mbed_official 464:04583941e294 540 } FMC_Bank1E_TypeDef;
mbed_official 464:04583941e294 541
mbed_official 464:04583941e294 542 /**
mbed_official 464:04583941e294 543 * @brief Flexible Memory Controller Bank2
mbed_official 464:04583941e294 544 */
mbed_official 464:04583941e294 545
mbed_official 464:04583941e294 546 typedef struct
mbed_official 464:04583941e294 547 {
mbed_official 464:04583941e294 548 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
mbed_official 464:04583941e294 549 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
mbed_official 464:04583941e294 550 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
mbed_official 464:04583941e294 551 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
mbed_official 464:04583941e294 552 uint32_t RESERVED0; /*!< Reserved, 0x70 */
mbed_official 464:04583941e294 553 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
mbed_official 464:04583941e294 554 uint32_t RESERVED1; /*!< Reserved, 0x78 */
mbed_official 464:04583941e294 555 uint32_t RESERVED2; /*!< Reserved, 0x7C */
mbed_official 464:04583941e294 556 __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */
mbed_official 464:04583941e294 557 __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
mbed_official 464:04583941e294 558 __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
mbed_official 464:04583941e294 559 __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
mbed_official 464:04583941e294 560 uint32_t RESERVED3; /*!< Reserved, 0x90 */
mbed_official 464:04583941e294 561 __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
mbed_official 464:04583941e294 562 } FMC_Bank2_3_TypeDef;
mbed_official 464:04583941e294 563
mbed_official 464:04583941e294 564 /**
mbed_official 464:04583941e294 565 * @brief Flexible Memory Controller Bank4
mbed_official 464:04583941e294 566 */
mbed_official 464:04583941e294 567
mbed_official 464:04583941e294 568 typedef struct
mbed_official 464:04583941e294 569 {
mbed_official 464:04583941e294 570 __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */
mbed_official 464:04583941e294 571 __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */
mbed_official 464:04583941e294 572 __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */
mbed_official 464:04583941e294 573 __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
mbed_official 464:04583941e294 574 __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
mbed_official 464:04583941e294 575 } FMC_Bank4_TypeDef;
mbed_official 464:04583941e294 576
mbed_official 464:04583941e294 577 /**
mbed_official 464:04583941e294 578 * @brief Flexible Memory Controller Bank5_6
mbed_official 464:04583941e294 579 */
mbed_official 464:04583941e294 580
mbed_official 464:04583941e294 581 typedef struct
mbed_official 464:04583941e294 582 {
mbed_official 464:04583941e294 583 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
mbed_official 464:04583941e294 584 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
mbed_official 464:04583941e294 585 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
mbed_official 464:04583941e294 586 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
mbed_official 464:04583941e294 587 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
mbed_official 464:04583941e294 588 } FMC_Bank5_6_TypeDef;
mbed_official 464:04583941e294 589
mbed_official 464:04583941e294 590 /**
mbed_official 464:04583941e294 591 * @brief General Purpose I/O
mbed_official 464:04583941e294 592 */
mbed_official 464:04583941e294 593
mbed_official 464:04583941e294 594 typedef struct
mbed_official 464:04583941e294 595 {
mbed_official 464:04583941e294 596 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 464:04583941e294 597 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 464:04583941e294 598 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 464:04583941e294 599 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 464:04583941e294 600 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 464:04583941e294 601 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 464:04583941e294 602 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
mbed_official 464:04583941e294 603 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
mbed_official 464:04583941e294 604 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 464:04583941e294 605 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 464:04583941e294 606 } GPIO_TypeDef;
mbed_official 464:04583941e294 607
mbed_official 464:04583941e294 608 /**
mbed_official 464:04583941e294 609 * @brief System configuration controller
mbed_official 464:04583941e294 610 */
mbed_official 464:04583941e294 611
mbed_official 464:04583941e294 612 typedef struct
mbed_official 464:04583941e294 613 {
mbed_official 464:04583941e294 614 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 464:04583941e294 615 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 464:04583941e294 616 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 464:04583941e294 617 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
mbed_official 464:04583941e294 618 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
mbed_official 464:04583941e294 619 } SYSCFG_TypeDef;
mbed_official 464:04583941e294 620
mbed_official 464:04583941e294 621 /**
mbed_official 464:04583941e294 622 * @brief Inter-integrated Circuit Interface
mbed_official 464:04583941e294 623 */
mbed_official 464:04583941e294 624
mbed_official 464:04583941e294 625 typedef struct
mbed_official 464:04583941e294 626 {
mbed_official 464:04583941e294 627 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 464:04583941e294 628 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 464:04583941e294 629 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
mbed_official 464:04583941e294 630 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
mbed_official 464:04583941e294 631 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
mbed_official 464:04583941e294 632 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
mbed_official 464:04583941e294 633 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
mbed_official 464:04583941e294 634 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
mbed_official 464:04583941e294 635 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
mbed_official 464:04583941e294 636 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
mbed_official 464:04583941e294 637 } I2C_TypeDef;
mbed_official 464:04583941e294 638
mbed_official 464:04583941e294 639 /**
mbed_official 464:04583941e294 640 * @brief Independent WATCHDOG
mbed_official 464:04583941e294 641 */
mbed_official 464:04583941e294 642
mbed_official 464:04583941e294 643 typedef struct
mbed_official 464:04583941e294 644 {
mbed_official 464:04583941e294 645 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 464:04583941e294 646 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 464:04583941e294 647 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 464:04583941e294 648 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 464:04583941e294 649 } IWDG_TypeDef;
mbed_official 464:04583941e294 650
mbed_official 464:04583941e294 651 /**
mbed_official 464:04583941e294 652 * @brief LCD-TFT Display Controller
mbed_official 464:04583941e294 653 */
mbed_official 464:04583941e294 654
mbed_official 464:04583941e294 655 typedef struct
mbed_official 464:04583941e294 656 {
mbed_official 464:04583941e294 657 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
mbed_official 464:04583941e294 658 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
mbed_official 464:04583941e294 659 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
mbed_official 464:04583941e294 660 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
mbed_official 464:04583941e294 661 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
mbed_official 464:04583941e294 662 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
mbed_official 464:04583941e294 663 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
mbed_official 464:04583941e294 664 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
mbed_official 464:04583941e294 665 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
mbed_official 464:04583941e294 666 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
mbed_official 464:04583941e294 667 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
mbed_official 464:04583941e294 668 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
mbed_official 464:04583941e294 669 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
mbed_official 464:04583941e294 670 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
mbed_official 464:04583941e294 671 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
mbed_official 464:04583941e294 672 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
mbed_official 464:04583941e294 673 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
mbed_official 464:04583941e294 674 } LTDC_TypeDef;
mbed_official 464:04583941e294 675
mbed_official 464:04583941e294 676 /**
mbed_official 464:04583941e294 677 * @brief LCD-TFT Display layer x Controller
mbed_official 464:04583941e294 678 */
mbed_official 464:04583941e294 679
mbed_official 464:04583941e294 680 typedef struct
mbed_official 464:04583941e294 681 {
mbed_official 464:04583941e294 682 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
mbed_official 464:04583941e294 683 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
mbed_official 464:04583941e294 684 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
mbed_official 464:04583941e294 685 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
mbed_official 464:04583941e294 686 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
mbed_official 464:04583941e294 687 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
mbed_official 464:04583941e294 688 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
mbed_official 464:04583941e294 689 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
mbed_official 464:04583941e294 690 uint32_t RESERVED0[2]; /*!< Reserved */
mbed_official 464:04583941e294 691 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
mbed_official 464:04583941e294 692 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
mbed_official 464:04583941e294 693 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
mbed_official 464:04583941e294 694 uint32_t RESERVED1[3]; /*!< Reserved */
mbed_official 464:04583941e294 695 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
mbed_official 464:04583941e294 696
mbed_official 464:04583941e294 697 } LTDC_Layer_TypeDef;
mbed_official 464:04583941e294 698
mbed_official 464:04583941e294 699 /**
mbed_official 464:04583941e294 700 * @brief Power Control
mbed_official 464:04583941e294 701 */
mbed_official 464:04583941e294 702
mbed_official 464:04583941e294 703 typedef struct
mbed_official 464:04583941e294 704 {
mbed_official 464:04583941e294 705 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 464:04583941e294 706 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 464:04583941e294 707 } PWR_TypeDef;
mbed_official 464:04583941e294 708
mbed_official 464:04583941e294 709 /**
mbed_official 464:04583941e294 710 * @brief Reset and Clock Control
mbed_official 464:04583941e294 711 */
mbed_official 464:04583941e294 712
mbed_official 464:04583941e294 713 typedef struct
mbed_official 464:04583941e294 714 {
mbed_official 464:04583941e294 715 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 464:04583941e294 716 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
mbed_official 464:04583941e294 717 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
mbed_official 464:04583941e294 718 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
mbed_official 464:04583941e294 719 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
mbed_official 464:04583941e294 720 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
mbed_official 464:04583941e294 721 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
mbed_official 464:04583941e294 722 uint32_t RESERVED0; /*!< Reserved, 0x1C */
mbed_official 464:04583941e294 723 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
mbed_official 464:04583941e294 724 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
mbed_official 464:04583941e294 725 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
mbed_official 464:04583941e294 726 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
mbed_official 464:04583941e294 727 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
mbed_official 464:04583941e294 728 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
mbed_official 464:04583941e294 729 uint32_t RESERVED2; /*!< Reserved, 0x3C */
mbed_official 464:04583941e294 730 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
mbed_official 464:04583941e294 731 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
mbed_official 464:04583941e294 732 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
mbed_official 464:04583941e294 733 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
mbed_official 464:04583941e294 734 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
mbed_official 464:04583941e294 735 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
mbed_official 464:04583941e294 736 uint32_t RESERVED4; /*!< Reserved, 0x5C */
mbed_official 464:04583941e294 737 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
mbed_official 464:04583941e294 738 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
mbed_official 464:04583941e294 739 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
mbed_official 464:04583941e294 740 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
mbed_official 464:04583941e294 741 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
mbed_official 464:04583941e294 742 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
mbed_official 464:04583941e294 743 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
mbed_official 464:04583941e294 744 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
mbed_official 464:04583941e294 745 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
mbed_official 464:04583941e294 746 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
mbed_official 464:04583941e294 747
mbed_official 464:04583941e294 748 } RCC_TypeDef;
mbed_official 464:04583941e294 749
mbed_official 464:04583941e294 750 /**
mbed_official 464:04583941e294 751 * @brief Real-Time Clock
mbed_official 464:04583941e294 752 */
mbed_official 464:04583941e294 753
mbed_official 464:04583941e294 754 typedef struct
mbed_official 464:04583941e294 755 {
mbed_official 464:04583941e294 756 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 464:04583941e294 757 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 464:04583941e294 758 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 464:04583941e294 759 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 464:04583941e294 760 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 464:04583941e294 761 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 464:04583941e294 762 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
mbed_official 464:04583941e294 763 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 464:04583941e294 764 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 464:04583941e294 765 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 464:04583941e294 766 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 464:04583941e294 767 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 464:04583941e294 768 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 464:04583941e294 769 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 464:04583941e294 770 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 464:04583941e294 771 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 464:04583941e294 772 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 464:04583941e294 773 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 464:04583941e294 774 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 464:04583941e294 775 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 464:04583941e294 776 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
mbed_official 464:04583941e294 777 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 464:04583941e294 778 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 464:04583941e294 779 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 464:04583941e294 780 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 464:04583941e294 781 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 464:04583941e294 782 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 464:04583941e294 783 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 464:04583941e294 784 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 464:04583941e294 785 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 464:04583941e294 786 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 464:04583941e294 787 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 464:04583941e294 788 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 464:04583941e294 789 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 464:04583941e294 790 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 464:04583941e294 791 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 464:04583941e294 792 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 464:04583941e294 793 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 464:04583941e294 794 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 464:04583941e294 795 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 464:04583941e294 796 } RTC_TypeDef;
mbed_official 464:04583941e294 797
mbed_official 464:04583941e294 798 /**
mbed_official 464:04583941e294 799 * @brief Serial Audio Interface
mbed_official 464:04583941e294 800 */
mbed_official 464:04583941e294 801
mbed_official 464:04583941e294 802 typedef struct
mbed_official 464:04583941e294 803 {
mbed_official 464:04583941e294 804 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
mbed_official 464:04583941e294 805 } SAI_TypeDef;
mbed_official 464:04583941e294 806
mbed_official 464:04583941e294 807 typedef struct
mbed_official 464:04583941e294 808 {
mbed_official 464:04583941e294 809 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
mbed_official 464:04583941e294 810 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
mbed_official 464:04583941e294 811 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
mbed_official 464:04583941e294 812 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
mbed_official 464:04583941e294 813 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
mbed_official 464:04583941e294 814 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
mbed_official 464:04583941e294 815 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
mbed_official 464:04583941e294 816 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
mbed_official 464:04583941e294 817 } SAI_Block_TypeDef;
mbed_official 464:04583941e294 818
mbed_official 464:04583941e294 819 /**
mbed_official 464:04583941e294 820 * @brief SD host Interface
mbed_official 464:04583941e294 821 */
mbed_official 464:04583941e294 822
mbed_official 464:04583941e294 823 typedef struct
mbed_official 464:04583941e294 824 {
mbed_official 464:04583941e294 825 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
mbed_official 464:04583941e294 826 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
mbed_official 464:04583941e294 827 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
mbed_official 464:04583941e294 828 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
mbed_official 464:04583941e294 829 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
mbed_official 464:04583941e294 830 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
mbed_official 464:04583941e294 831 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
mbed_official 464:04583941e294 832 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
mbed_official 464:04583941e294 833 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
mbed_official 464:04583941e294 834 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
mbed_official 464:04583941e294 835 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
mbed_official 464:04583941e294 836 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
mbed_official 464:04583941e294 837 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
mbed_official 464:04583941e294 838 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
mbed_official 464:04583941e294 839 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
mbed_official 464:04583941e294 840 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
mbed_official 464:04583941e294 841 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
mbed_official 464:04583941e294 842 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
mbed_official 464:04583941e294 843 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
mbed_official 464:04583941e294 844 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
mbed_official 464:04583941e294 845 } SDIO_TypeDef;
mbed_official 464:04583941e294 846
mbed_official 464:04583941e294 847 /**
mbed_official 464:04583941e294 848 * @brief Serial Peripheral Interface
mbed_official 464:04583941e294 849 */
mbed_official 464:04583941e294 850
mbed_official 464:04583941e294 851 typedef struct
mbed_official 464:04583941e294 852 {
mbed_official 464:04583941e294 853 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 464:04583941e294 854 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
mbed_official 464:04583941e294 855 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
mbed_official 464:04583941e294 856 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 464:04583941e294 857 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 464:04583941e294 858 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 464:04583941e294 859 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 464:04583941e294 860 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 464:04583941e294 861 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 464:04583941e294 862 } SPI_TypeDef;
mbed_official 464:04583941e294 863
mbed_official 464:04583941e294 864 /**
mbed_official 464:04583941e294 865 * @brief TIM
mbed_official 464:04583941e294 866 */
mbed_official 464:04583941e294 867
mbed_official 464:04583941e294 868 typedef struct
mbed_official 464:04583941e294 869 {
mbed_official 464:04583941e294 870 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 464:04583941e294 871 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 464:04583941e294 872 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 464:04583941e294 873 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 464:04583941e294 874 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 464:04583941e294 875 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 464:04583941e294 876 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 464:04583941e294 877 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 464:04583941e294 878 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 464:04583941e294 879 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 464:04583941e294 880 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 464:04583941e294 881 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 464:04583941e294 882 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 464:04583941e294 883 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 464:04583941e294 884 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 464:04583941e294 885 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 464:04583941e294 886 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 464:04583941e294 887 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 464:04583941e294 888 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 464:04583941e294 889 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 464:04583941e294 890 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 464:04583941e294 891 } TIM_TypeDef;
mbed_official 464:04583941e294 892
mbed_official 464:04583941e294 893 /**
mbed_official 464:04583941e294 894 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 464:04583941e294 895 */
mbed_official 464:04583941e294 896
mbed_official 464:04583941e294 897 typedef struct
mbed_official 464:04583941e294 898 {
mbed_official 464:04583941e294 899 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 464:04583941e294 900 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 464:04583941e294 901 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 464:04583941e294 902 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 464:04583941e294 903 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 464:04583941e294 904 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 464:04583941e294 905 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 464:04583941e294 906 } USART_TypeDef;
mbed_official 464:04583941e294 907
mbed_official 464:04583941e294 908 /**
mbed_official 464:04583941e294 909 * @brief Window WATCHDOG
mbed_official 464:04583941e294 910 */
mbed_official 464:04583941e294 911
mbed_official 464:04583941e294 912 typedef struct
mbed_official 464:04583941e294 913 {
mbed_official 464:04583941e294 914 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 464:04583941e294 915 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 464:04583941e294 916 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 464:04583941e294 917 } WWDG_TypeDef;
mbed_official 464:04583941e294 918
mbed_official 464:04583941e294 919 /**
mbed_official 464:04583941e294 920 * @brief Crypto Processor
mbed_official 464:04583941e294 921 */
mbed_official 464:04583941e294 922
mbed_official 464:04583941e294 923 typedef struct
mbed_official 464:04583941e294 924 {
mbed_official 464:04583941e294 925 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
mbed_official 464:04583941e294 926 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
mbed_official 464:04583941e294 927 __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */
mbed_official 464:04583941e294 928 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
mbed_official 464:04583941e294 929 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
mbed_official 464:04583941e294 930 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
mbed_official 464:04583941e294 931 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
mbed_official 464:04583941e294 932 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
mbed_official 464:04583941e294 933 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
mbed_official 464:04583941e294 934 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
mbed_official 464:04583941e294 935 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
mbed_official 464:04583941e294 936 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
mbed_official 464:04583941e294 937 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
mbed_official 464:04583941e294 938 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
mbed_official 464:04583941e294 939 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
mbed_official 464:04583941e294 940 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
mbed_official 464:04583941e294 941 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
mbed_official 464:04583941e294 942 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
mbed_official 464:04583941e294 943 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
mbed_official 464:04583941e294 944 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
mbed_official 464:04583941e294 945 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
mbed_official 464:04583941e294 946 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
mbed_official 464:04583941e294 947 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
mbed_official 464:04583941e294 948 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
mbed_official 464:04583941e294 949 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
mbed_official 464:04583941e294 950 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
mbed_official 464:04583941e294 951 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
mbed_official 464:04583941e294 952 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
mbed_official 464:04583941e294 953 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
mbed_official 464:04583941e294 954 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
mbed_official 464:04583941e294 955 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
mbed_official 464:04583941e294 956 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
mbed_official 464:04583941e294 957 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
mbed_official 464:04583941e294 958 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
mbed_official 464:04583941e294 959 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
mbed_official 464:04583941e294 960 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
mbed_official 464:04583941e294 961 } CRYP_TypeDef;
mbed_official 464:04583941e294 962
mbed_official 464:04583941e294 963 /**
mbed_official 464:04583941e294 964 * @brief HASH
mbed_official 464:04583941e294 965 */
mbed_official 464:04583941e294 966
mbed_official 464:04583941e294 967 typedef struct
mbed_official 464:04583941e294 968 {
mbed_official 464:04583941e294 969 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
mbed_official 464:04583941e294 970 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
mbed_official 464:04583941e294 971 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
mbed_official 464:04583941e294 972 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
mbed_official 464:04583941e294 973 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
mbed_official 464:04583941e294 974 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
mbed_official 464:04583941e294 975 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
mbed_official 464:04583941e294 976 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
mbed_official 464:04583941e294 977 } HASH_TypeDef;
mbed_official 464:04583941e294 978
mbed_official 464:04583941e294 979 /**
mbed_official 464:04583941e294 980 * @brief HASH_DIGEST
mbed_official 464:04583941e294 981 */
mbed_official 464:04583941e294 982
mbed_official 464:04583941e294 983 typedef struct
mbed_official 464:04583941e294 984 {
mbed_official 464:04583941e294 985 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
mbed_official 464:04583941e294 986 } HASH_DIGEST_TypeDef;
mbed_official 464:04583941e294 987
mbed_official 464:04583941e294 988 /**
mbed_official 464:04583941e294 989 * @brief RNG
mbed_official 464:04583941e294 990 */
mbed_official 464:04583941e294 991
mbed_official 464:04583941e294 992 typedef struct
mbed_official 464:04583941e294 993 {
mbed_official 464:04583941e294 994 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
mbed_official 464:04583941e294 995 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
mbed_official 464:04583941e294 996 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
mbed_official 464:04583941e294 997 } RNG_TypeDef;
mbed_official 464:04583941e294 998
mbed_official 464:04583941e294 999
mbed_official 464:04583941e294 1000 /**
mbed_official 464:04583941e294 1001 * @brief __USB_OTG_Core_register
mbed_official 464:04583941e294 1002 */
mbed_official 464:04583941e294 1003 typedef struct
mbed_official 464:04583941e294 1004 {
mbed_official 464:04583941e294 1005 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
mbed_official 464:04583941e294 1006 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
mbed_official 464:04583941e294 1007 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
mbed_official 464:04583941e294 1008 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
mbed_official 464:04583941e294 1009 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
mbed_official 464:04583941e294 1010 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
mbed_official 464:04583941e294 1011 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
mbed_official 464:04583941e294 1012 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
mbed_official 464:04583941e294 1013 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
mbed_official 464:04583941e294 1014 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h */
mbed_official 464:04583941e294 1015 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/
mbed_official 464:04583941e294 1016 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
mbed_official 464:04583941e294 1017 uint32_t Reserved30[2]; /* Reserved 030h*/
mbed_official 464:04583941e294 1018 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
mbed_official 464:04583941e294 1019 __IO uint32_t CID; /* User ID Register 03Ch*/
mbed_official 464:04583941e294 1020 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
mbed_official 464:04583941e294 1021 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
mbed_official 464:04583941e294 1022 __IO uint32_t DIEPTXF[0x0F];/* dev Periodic Transmit FIFO */
mbed_official 464:04583941e294 1023 }
mbed_official 464:04583941e294 1024 USB_OTG_GlobalTypeDef;
mbed_official 464:04583941e294 1025
mbed_official 464:04583941e294 1026
mbed_official 464:04583941e294 1027 /**
mbed_official 464:04583941e294 1028 * @brief __device_Registers
mbed_official 464:04583941e294 1029 */
mbed_official 464:04583941e294 1030 typedef struct
mbed_official 464:04583941e294 1031 {
mbed_official 464:04583941e294 1032 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
mbed_official 464:04583941e294 1033 __IO uint32_t DCTL; /* dev Control Register 804h*/
mbed_official 464:04583941e294 1034 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
mbed_official 464:04583941e294 1035 uint32_t Reserved0C; /* Reserved 80Ch*/
mbed_official 464:04583941e294 1036 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
mbed_official 464:04583941e294 1037 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
mbed_official 464:04583941e294 1038 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
mbed_official 464:04583941e294 1039 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
mbed_official 464:04583941e294 1040 uint32_t Reserved20; /* Reserved 820h*/
mbed_official 464:04583941e294 1041 uint32_t Reserved9; /* Reserved 824h*/
mbed_official 464:04583941e294 1042 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
mbed_official 464:04583941e294 1043 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
mbed_official 464:04583941e294 1044 __IO uint32_t DTHRCTL; /* dev thr 830h*/
mbed_official 464:04583941e294 1045 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
mbed_official 464:04583941e294 1046 __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
mbed_official 464:04583941e294 1047 __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
mbed_official 464:04583941e294 1048 uint32_t Reserved40; /* dedicated EP mask 840h*/
mbed_official 464:04583941e294 1049 __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
mbed_official 464:04583941e294 1050 uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
mbed_official 464:04583941e294 1051 __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
mbed_official 464:04583941e294 1052 }
mbed_official 464:04583941e294 1053 USB_OTG_DeviceTypeDef;
mbed_official 464:04583941e294 1054
mbed_official 464:04583941e294 1055
mbed_official 464:04583941e294 1056 /**
mbed_official 464:04583941e294 1057 * @brief __IN_Endpoint-Specific_Register
mbed_official 464:04583941e294 1058 */
mbed_official 464:04583941e294 1059 typedef struct
mbed_official 464:04583941e294 1060 {
mbed_official 464:04583941e294 1061 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
mbed_official 464:04583941e294 1062 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
mbed_official 464:04583941e294 1063 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
mbed_official 464:04583941e294 1064 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
mbed_official 464:04583941e294 1065 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
mbed_official 464:04583941e294 1066 __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
mbed_official 464:04583941e294 1067 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
mbed_official 464:04583941e294 1068 uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
mbed_official 464:04583941e294 1069 }
mbed_official 464:04583941e294 1070 USB_OTG_INEndpointTypeDef;
mbed_official 464:04583941e294 1071
mbed_official 464:04583941e294 1072
mbed_official 464:04583941e294 1073 /**
mbed_official 464:04583941e294 1074 * @brief __OUT_Endpoint-Specific_Registers
mbed_official 464:04583941e294 1075 */
mbed_official 464:04583941e294 1076 typedef struct
mbed_official 464:04583941e294 1077 {
mbed_official 464:04583941e294 1078 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
mbed_official 464:04583941e294 1079 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
mbed_official 464:04583941e294 1080 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
mbed_official 464:04583941e294 1081 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
mbed_official 464:04583941e294 1082 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
mbed_official 464:04583941e294 1083 __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
mbed_official 464:04583941e294 1084 uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
mbed_official 464:04583941e294 1085 }
mbed_official 464:04583941e294 1086 USB_OTG_OUTEndpointTypeDef;
mbed_official 464:04583941e294 1087
mbed_official 464:04583941e294 1088
mbed_official 464:04583941e294 1089 /**
mbed_official 464:04583941e294 1090 * @brief __Host_Mode_Register_Structures
mbed_official 464:04583941e294 1091 */
mbed_official 464:04583941e294 1092 typedef struct
mbed_official 464:04583941e294 1093 {
mbed_official 464:04583941e294 1094 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
mbed_official 464:04583941e294 1095 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
mbed_official 464:04583941e294 1096 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
mbed_official 464:04583941e294 1097 uint32_t Reserved40C; /* Reserved 40Ch*/
mbed_official 464:04583941e294 1098 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
mbed_official 464:04583941e294 1099 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
mbed_official 464:04583941e294 1100 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
mbed_official 464:04583941e294 1101 }
mbed_official 464:04583941e294 1102 USB_OTG_HostTypeDef;
mbed_official 464:04583941e294 1103
mbed_official 464:04583941e294 1104 /**
mbed_official 464:04583941e294 1105 * @brief __Host_Channel_Specific_Registers
mbed_official 464:04583941e294 1106 */
mbed_official 464:04583941e294 1107 typedef struct
mbed_official 464:04583941e294 1108 {
mbed_official 464:04583941e294 1109 __IO uint32_t HCCHAR;
mbed_official 464:04583941e294 1110 __IO uint32_t HCSPLT;
mbed_official 464:04583941e294 1111 __IO uint32_t HCINT;
mbed_official 464:04583941e294 1112 __IO uint32_t HCINTMSK;
mbed_official 464:04583941e294 1113 __IO uint32_t HCTSIZ;
mbed_official 464:04583941e294 1114 __IO uint32_t HCDMA;
mbed_official 464:04583941e294 1115 uint32_t Reserved[2];
mbed_official 464:04583941e294 1116 }
mbed_official 464:04583941e294 1117 USB_OTG_HostChannelTypeDef;
mbed_official 464:04583941e294 1118 /**
mbed_official 464:04583941e294 1119 * @}
mbed_official 464:04583941e294 1120 */
mbed_official 464:04583941e294 1121
mbed_official 464:04583941e294 1122 /** @addtogroup Peripheral_memory_map
mbed_official 464:04583941e294 1123 * @{
mbed_official 464:04583941e294 1124 */
mbed_official 464:04583941e294 1125 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 2 MB) base address in the alias region */
mbed_official 464:04583941e294 1126 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
mbed_official 464:04583941e294 1127 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
mbed_official 464:04583941e294 1128 #define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
mbed_official 464:04583941e294 1129 #define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
mbed_official 464:04583941e294 1130 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 464:04583941e294 1131 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
mbed_official 464:04583941e294 1132 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
mbed_official 464:04583941e294 1133 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
mbed_official 464:04583941e294 1134 #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
mbed_official 464:04583941e294 1135 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
mbed_official 464:04583941e294 1136 #define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
mbed_official 464:04583941e294 1137 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 464:04583941e294 1138 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
mbed_official 464:04583941e294 1139 #define FLASH_END ((uint32_t)0x081FFFFF) /*!< FLASH end address */
mbed_official 464:04583941e294 1140 #define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
mbed_official 464:04583941e294 1141
mbed_official 464:04583941e294 1142 /* Legacy defines */
mbed_official 464:04583941e294 1143 #define SRAM_BASE SRAM1_BASE
mbed_official 464:04583941e294 1144 #define SRAM_BB_BASE SRAM1_BB_BASE
mbed_official 464:04583941e294 1145
mbed_official 464:04583941e294 1146
mbed_official 464:04583941e294 1147 /*!< Peripheral memory map */
mbed_official 464:04583941e294 1148 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 464:04583941e294 1149 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 464:04583941e294 1150 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 464:04583941e294 1151 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official 464:04583941e294 1152
mbed_official 464:04583941e294 1153 /*!< APB1 peripherals */
mbed_official 464:04583941e294 1154 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
mbed_official 464:04583941e294 1155 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
mbed_official 464:04583941e294 1156 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
mbed_official 464:04583941e294 1157 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
mbed_official 464:04583941e294 1158 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
mbed_official 464:04583941e294 1159 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
mbed_official 464:04583941e294 1160 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
mbed_official 464:04583941e294 1161 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
mbed_official 464:04583941e294 1162 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
mbed_official 464:04583941e294 1163 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
mbed_official 464:04583941e294 1164 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
mbed_official 464:04583941e294 1165 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
mbed_official 464:04583941e294 1166 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
mbed_official 464:04583941e294 1167 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
mbed_official 464:04583941e294 1168 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
mbed_official 464:04583941e294 1169 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
mbed_official 464:04583941e294 1170 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
mbed_official 464:04583941e294 1171 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
mbed_official 464:04583941e294 1172 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
mbed_official 464:04583941e294 1173 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
mbed_official 464:04583941e294 1174 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
mbed_official 464:04583941e294 1175 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
mbed_official 464:04583941e294 1176 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
mbed_official 464:04583941e294 1177 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
mbed_official 464:04583941e294 1178 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
mbed_official 464:04583941e294 1179 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
mbed_official 464:04583941e294 1180 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
mbed_official 464:04583941e294 1181 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
mbed_official 464:04583941e294 1182 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
mbed_official 464:04583941e294 1183
mbed_official 464:04583941e294 1184 /*!< APB2 peripherals */
mbed_official 464:04583941e294 1185 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
mbed_official 464:04583941e294 1186 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
mbed_official 464:04583941e294 1187 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
mbed_official 464:04583941e294 1188 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
mbed_official 464:04583941e294 1189 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
mbed_official 464:04583941e294 1190 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
mbed_official 464:04583941e294 1191 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
mbed_official 464:04583941e294 1192 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
mbed_official 464:04583941e294 1193 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
mbed_official 464:04583941e294 1194 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
mbed_official 464:04583941e294 1195 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
mbed_official 464:04583941e294 1196 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
mbed_official 464:04583941e294 1197 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
mbed_official 464:04583941e294 1198 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
mbed_official 464:04583941e294 1199 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
mbed_official 464:04583941e294 1200 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
mbed_official 464:04583941e294 1201 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
mbed_official 464:04583941e294 1202 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
mbed_official 464:04583941e294 1203 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
mbed_official 464:04583941e294 1204 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
mbed_official 464:04583941e294 1205 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
mbed_official 464:04583941e294 1206 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
mbed_official 464:04583941e294 1207 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
mbed_official 464:04583941e294 1208 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
mbed_official 464:04583941e294 1209
mbed_official 464:04583941e294 1210 /*!< AHB1 peripherals */
mbed_official 464:04583941e294 1211 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
mbed_official 464:04583941e294 1212 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
mbed_official 464:04583941e294 1213 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
mbed_official 464:04583941e294 1214 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
mbed_official 464:04583941e294 1215 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
mbed_official 464:04583941e294 1216 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
mbed_official 464:04583941e294 1217 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
mbed_official 464:04583941e294 1218 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
mbed_official 464:04583941e294 1219 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
mbed_official 464:04583941e294 1220 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
mbed_official 464:04583941e294 1221 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
mbed_official 464:04583941e294 1222 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
mbed_official 464:04583941e294 1223 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
mbed_official 464:04583941e294 1224 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
mbed_official 464:04583941e294 1225 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
mbed_official 464:04583941e294 1226 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
mbed_official 464:04583941e294 1227 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
mbed_official 464:04583941e294 1228 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
mbed_official 464:04583941e294 1229 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
mbed_official 464:04583941e294 1230 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
mbed_official 464:04583941e294 1231 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
mbed_official 464:04583941e294 1232 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
mbed_official 464:04583941e294 1233 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
mbed_official 464:04583941e294 1234 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
mbed_official 464:04583941e294 1235 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
mbed_official 464:04583941e294 1236 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
mbed_official 464:04583941e294 1237 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
mbed_official 464:04583941e294 1238 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
mbed_official 464:04583941e294 1239 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
mbed_official 464:04583941e294 1240 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
mbed_official 464:04583941e294 1241 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
mbed_official 464:04583941e294 1242 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
mbed_official 464:04583941e294 1243 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
mbed_official 464:04583941e294 1244 #define ETH_MAC_BASE (ETH_BASE)
mbed_official 464:04583941e294 1245 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
mbed_official 464:04583941e294 1246 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
mbed_official 464:04583941e294 1247 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
mbed_official 464:04583941e294 1248 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
mbed_official 464:04583941e294 1249
mbed_official 464:04583941e294 1250 /*!< AHB2 peripherals */
mbed_official 464:04583941e294 1251 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
mbed_official 464:04583941e294 1252 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)
mbed_official 464:04583941e294 1253 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400)
mbed_official 464:04583941e294 1254 #define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
mbed_official 464:04583941e294 1255 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
mbed_official 464:04583941e294 1256
mbed_official 464:04583941e294 1257 /*!< FMC Bankx registers base address */
mbed_official 464:04583941e294 1258 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
mbed_official 464:04583941e294 1259 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
mbed_official 464:04583941e294 1260 #define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060)
mbed_official 464:04583941e294 1261 #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
mbed_official 464:04583941e294 1262 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
mbed_official 464:04583941e294 1263
mbed_official 464:04583941e294 1264 /* Debug MCU registers base address */
mbed_official 464:04583941e294 1265 #define DBGMCU_BASE ((uint32_t )0xE0042000)
mbed_official 464:04583941e294 1266
mbed_official 464:04583941e294 1267 /*!< USB registers base address */
mbed_official 464:04583941e294 1268 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
mbed_official 464:04583941e294 1269 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
mbed_official 464:04583941e294 1270
mbed_official 464:04583941e294 1271 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
mbed_official 464:04583941e294 1272 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
mbed_official 464:04583941e294 1273 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
mbed_official 464:04583941e294 1274 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
mbed_official 464:04583941e294 1275 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
mbed_official 464:04583941e294 1276 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
mbed_official 464:04583941e294 1277 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
mbed_official 464:04583941e294 1278 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
mbed_official 464:04583941e294 1279 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
mbed_official 464:04583941e294 1280 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
mbed_official 464:04583941e294 1281 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
mbed_official 464:04583941e294 1282 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
mbed_official 464:04583941e294 1283
mbed_official 464:04583941e294 1284 /**
mbed_official 464:04583941e294 1285 * @}
mbed_official 464:04583941e294 1286 */
mbed_official 464:04583941e294 1287
mbed_official 464:04583941e294 1288 /** @addtogroup Peripheral_declaration
mbed_official 464:04583941e294 1289 * @{
mbed_official 464:04583941e294 1290 */
mbed_official 464:04583941e294 1291 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 464:04583941e294 1292 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 464:04583941e294 1293 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 464:04583941e294 1294 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 464:04583941e294 1295 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 464:04583941e294 1296 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 464:04583941e294 1297 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
mbed_official 464:04583941e294 1298 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
mbed_official 464:04583941e294 1299 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 464:04583941e294 1300 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 464:04583941e294 1301 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 464:04583941e294 1302 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 464:04583941e294 1303 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
mbed_official 464:04583941e294 1304 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 464:04583941e294 1305 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 464:04583941e294 1306 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
mbed_official 464:04583941e294 1307 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 464:04583941e294 1308 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 464:04583941e294 1309 #define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official 464:04583941e294 1310 #define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official 464:04583941e294 1311 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 464:04583941e294 1312 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 464:04583941e294 1313 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
mbed_official 464:04583941e294 1314 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
mbed_official 464:04583941e294 1315 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
mbed_official 464:04583941e294 1316 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 464:04583941e294 1317 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 464:04583941e294 1318 #define UART7 ((USART_TypeDef *) UART7_BASE)
mbed_official 464:04583941e294 1319 #define UART8 ((USART_TypeDef *) UART8_BASE)
mbed_official 464:04583941e294 1320 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 464:04583941e294 1321 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
mbed_official 464:04583941e294 1322 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 464:04583941e294 1323 #define USART6 ((USART_TypeDef *) USART6_BASE)
mbed_official 464:04583941e294 1324 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 464:04583941e294 1325 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 464:04583941e294 1326 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
mbed_official 464:04583941e294 1327 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
mbed_official 464:04583941e294 1328 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
mbed_official 464:04583941e294 1329 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 464:04583941e294 1330 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
mbed_official 464:04583941e294 1331 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 464:04583941e294 1332 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 464:04583941e294 1333 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 464:04583941e294 1334 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official 464:04583941e294 1335 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 464:04583941e294 1336 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
mbed_official 464:04583941e294 1337 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
mbed_official 464:04583941e294 1338 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
mbed_official 464:04583941e294 1339 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
mbed_official 464:04583941e294 1340 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
mbed_official 464:04583941e294 1341 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
mbed_official 464:04583941e294 1342 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
mbed_official 464:04583941e294 1343 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
mbed_official 464:04583941e294 1344
mbed_official 464:04583941e294 1345 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 464:04583941e294 1346 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 464:04583941e294 1347 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 464:04583941e294 1348 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 464:04583941e294 1349 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 464:04583941e294 1350 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 464:04583941e294 1351 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
mbed_official 464:04583941e294 1352 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 464:04583941e294 1353 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
mbed_official 464:04583941e294 1354 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
mbed_official 464:04583941e294 1355 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
mbed_official 464:04583941e294 1356 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 464:04583941e294 1357 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 464:04583941e294 1358 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 464:04583941e294 1359 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 464:04583941e294 1360 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
mbed_official 464:04583941e294 1361 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
mbed_official 464:04583941e294 1362 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
mbed_official 464:04583941e294 1363 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
mbed_official 464:04583941e294 1364 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
mbed_official 464:04583941e294 1365 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
mbed_official 464:04583941e294 1366 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
mbed_official 464:04583941e294 1367 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
mbed_official 464:04583941e294 1368 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 464:04583941e294 1369 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
mbed_official 464:04583941e294 1370 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
mbed_official 464:04583941e294 1371 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
mbed_official 464:04583941e294 1372 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
mbed_official 464:04583941e294 1373 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
mbed_official 464:04583941e294 1374 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
mbed_official 464:04583941e294 1375 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
mbed_official 464:04583941e294 1376 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
mbed_official 464:04583941e294 1377 #define ETH ((ETH_TypeDef *) ETH_BASE)
mbed_official 464:04583941e294 1378 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
mbed_official 464:04583941e294 1379 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
mbed_official 464:04583941e294 1380 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
mbed_official 464:04583941e294 1381 #define HASH ((HASH_TypeDef *) HASH_BASE)
mbed_official 464:04583941e294 1382 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
mbed_official 464:04583941e294 1383 #define RNG ((RNG_TypeDef *) RNG_BASE)
mbed_official 464:04583941e294 1384 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
mbed_official 464:04583941e294 1385 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
mbed_official 464:04583941e294 1386 #define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE)
mbed_official 464:04583941e294 1387 #define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
mbed_official 464:04583941e294 1388 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
mbed_official 464:04583941e294 1389
mbed_official 464:04583941e294 1390 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 464:04583941e294 1391
mbed_official 464:04583941e294 1392 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
mbed_official 464:04583941e294 1393 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
mbed_official 464:04583941e294 1394
mbed_official 464:04583941e294 1395 /**
mbed_official 464:04583941e294 1396 * @}
mbed_official 464:04583941e294 1397 */
mbed_official 464:04583941e294 1398
mbed_official 464:04583941e294 1399 /** @addtogroup Exported_constants
mbed_official 464:04583941e294 1400 * @{
mbed_official 464:04583941e294 1401 */
mbed_official 464:04583941e294 1402
mbed_official 464:04583941e294 1403 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 464:04583941e294 1404 * @{
mbed_official 464:04583941e294 1405 */
mbed_official 464:04583941e294 1406
mbed_official 464:04583941e294 1407 /******************************************************************************/
mbed_official 464:04583941e294 1408 /* Peripheral Registers_Bits_Definition */
mbed_official 464:04583941e294 1409 /******************************************************************************/
mbed_official 464:04583941e294 1410
mbed_official 464:04583941e294 1411 /******************************************************************************/
mbed_official 464:04583941e294 1412 /* */
mbed_official 464:04583941e294 1413 /* Analog to Digital Converter */
mbed_official 464:04583941e294 1414 /* */
mbed_official 464:04583941e294 1415 /******************************************************************************/
mbed_official 464:04583941e294 1416 /******************** Bit definition for ADC_SR register ********************/
mbed_official 464:04583941e294 1417 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
mbed_official 464:04583941e294 1418 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
mbed_official 464:04583941e294 1419 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
mbed_official 464:04583941e294 1420 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
mbed_official 464:04583941e294 1421 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
mbed_official 464:04583941e294 1422 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
mbed_official 464:04583941e294 1423
mbed_official 464:04583941e294 1424 /******************* Bit definition for ADC_CR1 register ********************/
mbed_official 464:04583941e294 1425 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 464:04583941e294 1426 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 1427 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 1428 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 1429 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 1430 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 1431 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
mbed_official 464:04583941e294 1432 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
mbed_official 464:04583941e294 1433 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
mbed_official 464:04583941e294 1434 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
mbed_official 464:04583941e294 1435 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
mbed_official 464:04583941e294 1436 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
mbed_official 464:04583941e294 1437 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
mbed_official 464:04583941e294 1438 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
mbed_official 464:04583941e294 1439 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
mbed_official 464:04583941e294 1440 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 464:04583941e294 1441 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 464:04583941e294 1442 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 464:04583941e294 1443 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
mbed_official 464:04583941e294 1444 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
mbed_official 464:04583941e294 1445 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
mbed_official 464:04583941e294 1446 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 1447 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 1448 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
mbed_official 464:04583941e294 1449
mbed_official 464:04583941e294 1450 /******************* Bit definition for ADC_CR2 register ********************/
mbed_official 464:04583941e294 1451 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
mbed_official 464:04583941e294 1452 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
mbed_official 464:04583941e294 1453 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
mbed_official 464:04583941e294 1454 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
mbed_official 464:04583941e294 1455 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
mbed_official 464:04583941e294 1456 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
mbed_official 464:04583941e294 1457 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
mbed_official 464:04583941e294 1458 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 1459 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 1460 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 1461 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 1462 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
mbed_official 464:04583941e294 1463 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 1464 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 1465 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
mbed_official 464:04583941e294 1466 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
mbed_official 464:04583941e294 1467 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 1468 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 1469 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 1470 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 1471 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
mbed_official 464:04583941e294 1472 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 464:04583941e294 1473 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 464:04583941e294 1474 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
mbed_official 464:04583941e294 1475
mbed_official 464:04583941e294 1476 /****************** Bit definition for ADC_SMPR1 register *******************/
mbed_official 464:04583941e294 1477 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
mbed_official 464:04583941e294 1478 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 1479 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 1480 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 1481 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
mbed_official 464:04583941e294 1482 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 464:04583941e294 1483 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 464:04583941e294 1484 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 464:04583941e294 1485 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
mbed_official 464:04583941e294 1486 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 464:04583941e294 1487 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 464:04583941e294 1488 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 464:04583941e294 1489 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
mbed_official 464:04583941e294 1490 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 464:04583941e294 1491 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 464:04583941e294 1492 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 464:04583941e294 1493 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
mbed_official 464:04583941e294 1494 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 464:04583941e294 1495 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 464:04583941e294 1496 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 464:04583941e294 1497 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
mbed_official 464:04583941e294 1498 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 464:04583941e294 1499 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 464:04583941e294 1500 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 464:04583941e294 1501 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
mbed_official 464:04583941e294 1502 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 464:04583941e294 1503 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 464:04583941e294 1504 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 464:04583941e294 1505 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
mbed_official 464:04583941e294 1506 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 464:04583941e294 1507 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 464:04583941e294 1508 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 464:04583941e294 1509 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
mbed_official 464:04583941e294 1510 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 1511 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 1512 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 1513
mbed_official 464:04583941e294 1514 /****************** Bit definition for ADC_SMPR2 register *******************/
mbed_official 464:04583941e294 1515 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
mbed_official 464:04583941e294 1516 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 1517 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 1518 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 1519 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
mbed_official 464:04583941e294 1520 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 464:04583941e294 1521 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 464:04583941e294 1522 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 464:04583941e294 1523 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
mbed_official 464:04583941e294 1524 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 464:04583941e294 1525 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 464:04583941e294 1526 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 464:04583941e294 1527 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
mbed_official 464:04583941e294 1528 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 464:04583941e294 1529 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 464:04583941e294 1530 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 464:04583941e294 1531 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
mbed_official 464:04583941e294 1532 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 464:04583941e294 1533 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 464:04583941e294 1534 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 464:04583941e294 1535 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
mbed_official 464:04583941e294 1536 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 464:04583941e294 1537 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 464:04583941e294 1538 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 464:04583941e294 1539 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
mbed_official 464:04583941e294 1540 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 464:04583941e294 1541 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 464:04583941e294 1542 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
mbed_official 464:04583941e294 1543 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
mbed_official 464:04583941e294 1544 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 464:04583941e294 1545 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 464:04583941e294 1546 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 464:04583941e294 1547 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
mbed_official 464:04583941e294 1548 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 1549 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 1550 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 1551 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
mbed_official 464:04583941e294 1552 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
mbed_official 464:04583941e294 1553 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
mbed_official 464:04583941e294 1554 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
mbed_official 464:04583941e294 1555
mbed_official 464:04583941e294 1556 /****************** Bit definition for ADC_JOFR1 register *******************/
mbed_official 464:04583941e294 1557 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
mbed_official 464:04583941e294 1558
mbed_official 464:04583941e294 1559 /****************** Bit definition for ADC_JOFR2 register *******************/
mbed_official 464:04583941e294 1560 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
mbed_official 464:04583941e294 1561
mbed_official 464:04583941e294 1562 /****************** Bit definition for ADC_JOFR3 register *******************/
mbed_official 464:04583941e294 1563 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
mbed_official 464:04583941e294 1564
mbed_official 464:04583941e294 1565 /****************** Bit definition for ADC_JOFR4 register *******************/
mbed_official 464:04583941e294 1566 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
mbed_official 464:04583941e294 1567
mbed_official 464:04583941e294 1568 /******************* Bit definition for ADC_HTR register ********************/
mbed_official 464:04583941e294 1569 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
mbed_official 464:04583941e294 1570
mbed_official 464:04583941e294 1571 /******************* Bit definition for ADC_LTR register ********************/
mbed_official 464:04583941e294 1572 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
mbed_official 464:04583941e294 1573
mbed_official 464:04583941e294 1574 /******************* Bit definition for ADC_SQR1 register *******************/
mbed_official 464:04583941e294 1575 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
mbed_official 464:04583941e294 1576 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 1577 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 1578 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 1579 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 1580 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 1581 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
mbed_official 464:04583941e294 1582 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 464:04583941e294 1583 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 464:04583941e294 1584 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 464:04583941e294 1585 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 464:04583941e294 1586 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 464:04583941e294 1587 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
mbed_official 464:04583941e294 1588 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 464:04583941e294 1589 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 464:04583941e294 1590 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 464:04583941e294 1591 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 464:04583941e294 1592 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 464:04583941e294 1593 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
mbed_official 464:04583941e294 1594 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 464:04583941e294 1595 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 464:04583941e294 1596 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 464:04583941e294 1597 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 464:04583941e294 1598 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 464:04583941e294 1599 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
mbed_official 464:04583941e294 1600 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 1601 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 1602 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 1603 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 1604
mbed_official 464:04583941e294 1605 /******************* Bit definition for ADC_SQR2 register *******************/
mbed_official 464:04583941e294 1606 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
mbed_official 464:04583941e294 1607 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 1608 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 1609 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 1610 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 1611 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 1612 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
mbed_official 464:04583941e294 1613 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 464:04583941e294 1614 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 464:04583941e294 1615 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 464:04583941e294 1616 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 464:04583941e294 1617 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 464:04583941e294 1618 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
mbed_official 464:04583941e294 1619 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 464:04583941e294 1620 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 464:04583941e294 1621 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 464:04583941e294 1622 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 464:04583941e294 1623 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 464:04583941e294 1624 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
mbed_official 464:04583941e294 1625 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 464:04583941e294 1626 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 464:04583941e294 1627 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 464:04583941e294 1628 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 464:04583941e294 1629 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 464:04583941e294 1630 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
mbed_official 464:04583941e294 1631 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 1632 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 1633 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 1634 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 1635 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 464:04583941e294 1636 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
mbed_official 464:04583941e294 1637 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 464:04583941e294 1638 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 464:04583941e294 1639 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 464:04583941e294 1640 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 464:04583941e294 1641 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 464:04583941e294 1642
mbed_official 464:04583941e294 1643 /******************* Bit definition for ADC_SQR3 register *******************/
mbed_official 464:04583941e294 1644 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
mbed_official 464:04583941e294 1645 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 1646 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 1647 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 1648 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 1649 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 1650 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
mbed_official 464:04583941e294 1651 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 464:04583941e294 1652 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 464:04583941e294 1653 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 464:04583941e294 1654 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 464:04583941e294 1655 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 464:04583941e294 1656 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
mbed_official 464:04583941e294 1657 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 464:04583941e294 1658 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 464:04583941e294 1659 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 464:04583941e294 1660 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 464:04583941e294 1661 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 464:04583941e294 1662 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
mbed_official 464:04583941e294 1663 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 464:04583941e294 1664 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 464:04583941e294 1665 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 464:04583941e294 1666 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 464:04583941e294 1667 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 464:04583941e294 1668 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
mbed_official 464:04583941e294 1669 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 1670 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 1671 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 1672 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 1673 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
mbed_official 464:04583941e294 1674 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
mbed_official 464:04583941e294 1675 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
mbed_official 464:04583941e294 1676 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
mbed_official 464:04583941e294 1677 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
mbed_official 464:04583941e294 1678 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
mbed_official 464:04583941e294 1679 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
mbed_official 464:04583941e294 1680
mbed_official 464:04583941e294 1681 /******************* Bit definition for ADC_JSQR register *******************/
mbed_official 464:04583941e294 1682 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
mbed_official 464:04583941e294 1683 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 1684 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 1685 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 1686 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 1687 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 1688 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
mbed_official 464:04583941e294 1689 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 464:04583941e294 1690 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 464:04583941e294 1691 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 464:04583941e294 1692 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 464:04583941e294 1693 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
mbed_official 464:04583941e294 1694 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
mbed_official 464:04583941e294 1695 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 464:04583941e294 1696 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 464:04583941e294 1697 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 464:04583941e294 1698 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 464:04583941e294 1699 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
mbed_official 464:04583941e294 1700 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
mbed_official 464:04583941e294 1701 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 464:04583941e294 1702 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 464:04583941e294 1703 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
mbed_official 464:04583941e294 1704 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
mbed_official 464:04583941e294 1705 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
mbed_official 464:04583941e294 1706 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
mbed_official 464:04583941e294 1707 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 1708 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 1709
mbed_official 464:04583941e294 1710 /******************* Bit definition for ADC_JDR1 register *******************/
mbed_official 464:04583941e294 1711 #define ADC_JDR1_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 464:04583941e294 1712
mbed_official 464:04583941e294 1713 /******************* Bit definition for ADC_JDR2 register *******************/
mbed_official 464:04583941e294 1714 #define ADC_JDR2_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 464:04583941e294 1715
mbed_official 464:04583941e294 1716 /******************* Bit definition for ADC_JDR3 register *******************/
mbed_official 464:04583941e294 1717 #define ADC_JDR3_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 464:04583941e294 1718
mbed_official 464:04583941e294 1719 /******************* Bit definition for ADC_JDR4 register *******************/
mbed_official 464:04583941e294 1720 #define ADC_JDR4_JDATA ((uint32_t)0xFFFF) /*!<Injected data */
mbed_official 464:04583941e294 1721
mbed_official 464:04583941e294 1722 /******************** Bit definition for ADC_DR register ********************/
mbed_official 464:04583941e294 1723 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
mbed_official 464:04583941e294 1724 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
mbed_official 464:04583941e294 1725
mbed_official 464:04583941e294 1726 /******************* Bit definition for ADC_CSR register ********************/
mbed_official 464:04583941e294 1727 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
mbed_official 464:04583941e294 1728 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
mbed_official 464:04583941e294 1729 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
mbed_official 464:04583941e294 1730 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
mbed_official 464:04583941e294 1731 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
mbed_official 464:04583941e294 1732 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
mbed_official 464:04583941e294 1733 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
mbed_official 464:04583941e294 1734 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
mbed_official 464:04583941e294 1735 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
mbed_official 464:04583941e294 1736 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
mbed_official 464:04583941e294 1737 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
mbed_official 464:04583941e294 1738 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
mbed_official 464:04583941e294 1739 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
mbed_official 464:04583941e294 1740 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
mbed_official 464:04583941e294 1741 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
mbed_official 464:04583941e294 1742 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
mbed_official 464:04583941e294 1743 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
mbed_official 464:04583941e294 1744 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
mbed_official 464:04583941e294 1745
mbed_official 464:04583941e294 1746 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 464:04583941e294 1747 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
mbed_official 464:04583941e294 1748 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 1749 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 1750 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 1751 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 1752 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 1753 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
mbed_official 464:04583941e294 1754 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 1755 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 1756 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 1757 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 1758 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
mbed_official 464:04583941e294 1759 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
mbed_official 464:04583941e294 1760 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 464:04583941e294 1761 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 464:04583941e294 1762 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
mbed_official 464:04583941e294 1763 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 1764 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 1765 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
mbed_official 464:04583941e294 1766 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
mbed_official 464:04583941e294 1767
mbed_official 464:04583941e294 1768 /******************* Bit definition for ADC_CDR register ********************/
mbed_official 464:04583941e294 1769 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
mbed_official 464:04583941e294 1770 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
mbed_official 464:04583941e294 1771
mbed_official 464:04583941e294 1772 /******************************************************************************/
mbed_official 464:04583941e294 1773 /* */
mbed_official 464:04583941e294 1774 /* Controller Area Network */
mbed_official 464:04583941e294 1775 /* */
mbed_official 464:04583941e294 1776 /******************************************************************************/
mbed_official 464:04583941e294 1777 /*!<CAN control and status registers */
mbed_official 464:04583941e294 1778 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 464:04583941e294 1779 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
mbed_official 464:04583941e294 1780 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
mbed_official 464:04583941e294 1781 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
mbed_official 464:04583941e294 1782 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
mbed_official 464:04583941e294 1783 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
mbed_official 464:04583941e294 1784 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
mbed_official 464:04583941e294 1785 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
mbed_official 464:04583941e294 1786 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
mbed_official 464:04583941e294 1787 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
mbed_official 464:04583941e294 1788 #define CAN_MCR_DBF ((uint32_t)0x00010000) /*!<bxCAN Debug freeze */
mbed_official 464:04583941e294 1789 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 464:04583941e294 1790 #define CAN_MSR_INAK ((uint32_t)0x0001) /*!<Initialization Acknowledge */
mbed_official 464:04583941e294 1791 #define CAN_MSR_SLAK ((uint32_t)0x0002) /*!<Sleep Acknowledge */
mbed_official 464:04583941e294 1792 #define CAN_MSR_ERRI ((uint32_t)0x0004) /*!<Error Interrupt */
mbed_official 464:04583941e294 1793 #define CAN_MSR_WKUI ((uint32_t)0x0008) /*!<Wakeup Interrupt */
mbed_official 464:04583941e294 1794 #define CAN_MSR_SLAKI ((uint32_t)0x0010) /*!<Sleep Acknowledge Interrupt */
mbed_official 464:04583941e294 1795 #define CAN_MSR_TXM ((uint32_t)0x0100) /*!<Transmit Mode */
mbed_official 464:04583941e294 1796 #define CAN_MSR_RXM ((uint32_t)0x0200) /*!<Receive Mode */
mbed_official 464:04583941e294 1797 #define CAN_MSR_SAMP ((uint32_t)0x0400) /*!<Last Sample Point */
mbed_official 464:04583941e294 1798 #define CAN_MSR_RX ((uint32_t)0x0800) /*!<CAN Rx Signal */
mbed_official 464:04583941e294 1799
mbed_official 464:04583941e294 1800 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 464:04583941e294 1801 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 464:04583941e294 1802 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 464:04583941e294 1803 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 464:04583941e294 1804 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 464:04583941e294 1805 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 464:04583941e294 1806 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 464:04583941e294 1807 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 464:04583941e294 1808 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 464:04583941e294 1809 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 464:04583941e294 1810 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 464:04583941e294 1811 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 464:04583941e294 1812 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 464:04583941e294 1813 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 464:04583941e294 1814 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 464:04583941e294 1815 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 464:04583941e294 1816 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 464:04583941e294 1817
mbed_official 464:04583941e294 1818 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 464:04583941e294 1819 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 464:04583941e294 1820 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 464:04583941e294 1821 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 464:04583941e294 1822
mbed_official 464:04583941e294 1823 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 464:04583941e294 1824 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 464:04583941e294 1825 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 464:04583941e294 1826 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 464:04583941e294 1827
mbed_official 464:04583941e294 1828 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 464:04583941e294 1829 #define CAN_RF0R_FMP0 ((uint32_t)0x03) /*!<FIFO 0 Message Pending */
mbed_official 464:04583941e294 1830 #define CAN_RF0R_FULL0 ((uint32_t)0x08) /*!<FIFO 0 Full */
mbed_official 464:04583941e294 1831 #define CAN_RF0R_FOVR0 ((uint32_t)0x10) /*!<FIFO 0 Overrun */
mbed_official 464:04583941e294 1832 #define CAN_RF0R_RFOM0 ((uint32_t)0x20) /*!<Release FIFO 0 Output Mailbox */
mbed_official 464:04583941e294 1833
mbed_official 464:04583941e294 1834 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 464:04583941e294 1835 #define CAN_RF1R_FMP1 ((uint32_t)0x03) /*!<FIFO 1 Message Pending */
mbed_official 464:04583941e294 1836 #define CAN_RF1R_FULL1 ((uint32_t)0x08) /*!<FIFO 1 Full */
mbed_official 464:04583941e294 1837 #define CAN_RF1R_FOVR1 ((uint32_t)0x10) /*!<FIFO 1 Overrun */
mbed_official 464:04583941e294 1838 #define CAN_RF1R_RFOM1 ((uint32_t)0x20) /*!<Release FIFO 1 Output Mailbox */
mbed_official 464:04583941e294 1839
mbed_official 464:04583941e294 1840 /******************** Bit definition for CAN_IER register *******************/
mbed_official 464:04583941e294 1841 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 464:04583941e294 1842 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 464:04583941e294 1843 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 464:04583941e294 1844 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 464:04583941e294 1845 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 464:04583941e294 1846 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 464:04583941e294 1847 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 464:04583941e294 1848 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 464:04583941e294 1849 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 464:04583941e294 1850 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 464:04583941e294 1851 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 464:04583941e294 1852 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 464:04583941e294 1853 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 464:04583941e294 1854 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 464:04583941e294 1855 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error warning interrupt enable */
mbed_official 464:04583941e294 1856 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error passive interrupt enable */
mbed_official 464:04583941e294 1857 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-off interrupt enable */
mbed_official 464:04583941e294 1858 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last error code interrupt enable */
mbed_official 464:04583941e294 1859 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error interrupt enable */
mbed_official 464:04583941e294 1860
mbed_official 464:04583941e294 1861
mbed_official 464:04583941e294 1862 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 464:04583941e294 1863 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 464:04583941e294 1864 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 464:04583941e294 1865 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 464:04583941e294 1866
mbed_official 464:04583941e294 1867 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 464:04583941e294 1868 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 1869 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 1870 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 1871
mbed_official 464:04583941e294 1872 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 464:04583941e294 1873 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 464:04583941e294 1874
mbed_official 464:04583941e294 1875 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 464:04583941e294 1876 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 464:04583941e294 1877 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 464:04583941e294 1878 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 1879 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 1880 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 1881 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 1882 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 464:04583941e294 1883 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 1884 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 1885 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 1886 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 464:04583941e294 1887 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 1888 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 1889 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 464:04583941e294 1890 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 464:04583941e294 1891
mbed_official 464:04583941e294 1892
mbed_official 464:04583941e294 1893 /*!<Mailbox registers */
mbed_official 464:04583941e294 1894 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 464:04583941e294 1895 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 464:04583941e294 1896 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 464:04583941e294 1897 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 464:04583941e294 1898 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 464:04583941e294 1899 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 464:04583941e294 1900
mbed_official 464:04583941e294 1901 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 464:04583941e294 1902 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 464:04583941e294 1903 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 464:04583941e294 1904 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 464:04583941e294 1905
mbed_official 464:04583941e294 1906 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 464:04583941e294 1907 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 464:04583941e294 1908 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 464:04583941e294 1909 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 464:04583941e294 1910 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 464:04583941e294 1911
mbed_official 464:04583941e294 1912 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 464:04583941e294 1913 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 464:04583941e294 1914 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 464:04583941e294 1915 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 464:04583941e294 1916 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 464:04583941e294 1917
mbed_official 464:04583941e294 1918 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 464:04583941e294 1919 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 464:04583941e294 1920 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 464:04583941e294 1921 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 464:04583941e294 1922 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 464:04583941e294 1923 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 464:04583941e294 1924
mbed_official 464:04583941e294 1925 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 464:04583941e294 1926 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 464:04583941e294 1927 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 464:04583941e294 1928 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 464:04583941e294 1929
mbed_official 464:04583941e294 1930 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 464:04583941e294 1931 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 464:04583941e294 1932 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 464:04583941e294 1933 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 464:04583941e294 1934 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 464:04583941e294 1935
mbed_official 464:04583941e294 1936 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 464:04583941e294 1937 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 464:04583941e294 1938 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 464:04583941e294 1939 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 464:04583941e294 1940 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 464:04583941e294 1941
mbed_official 464:04583941e294 1942 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 464:04583941e294 1943 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 464:04583941e294 1944 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 464:04583941e294 1945 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 464:04583941e294 1946 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 464:04583941e294 1947 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 464:04583941e294 1948
mbed_official 464:04583941e294 1949 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 464:04583941e294 1950 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 464:04583941e294 1951 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 464:04583941e294 1952 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 464:04583941e294 1953
mbed_official 464:04583941e294 1954 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 464:04583941e294 1955 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 464:04583941e294 1956 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 464:04583941e294 1957 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 464:04583941e294 1958 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 464:04583941e294 1959
mbed_official 464:04583941e294 1960 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 464:04583941e294 1961 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 464:04583941e294 1962 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 464:04583941e294 1963 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 464:04583941e294 1964 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 464:04583941e294 1965
mbed_official 464:04583941e294 1966 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 464:04583941e294 1967 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 464:04583941e294 1968 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 464:04583941e294 1969 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 464:04583941e294 1970 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 464:04583941e294 1971
mbed_official 464:04583941e294 1972 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 464:04583941e294 1973 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 464:04583941e294 1974 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 464:04583941e294 1975 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 464:04583941e294 1976
mbed_official 464:04583941e294 1977 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 464:04583941e294 1978 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 464:04583941e294 1979 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 464:04583941e294 1980 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 464:04583941e294 1981 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 464:04583941e294 1982
mbed_official 464:04583941e294 1983 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 464:04583941e294 1984 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 464:04583941e294 1985 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 464:04583941e294 1986 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 464:04583941e294 1987 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 464:04583941e294 1988
mbed_official 464:04583941e294 1989 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 464:04583941e294 1990 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 464:04583941e294 1991 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 464:04583941e294 1992 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 464:04583941e294 1993 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 464:04583941e294 1994
mbed_official 464:04583941e294 1995 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 464:04583941e294 1996 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 464:04583941e294 1997 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 464:04583941e294 1998 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 464:04583941e294 1999
mbed_official 464:04583941e294 2000 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 464:04583941e294 2001 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 464:04583941e294 2002 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 464:04583941e294 2003 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 464:04583941e294 2004 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 464:04583941e294 2005
mbed_official 464:04583941e294 2006 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 464:04583941e294 2007 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 464:04583941e294 2008 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 464:04583941e294 2009 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 464:04583941e294 2010 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 464:04583941e294 2011
mbed_official 464:04583941e294 2012 /*!<CAN filter registers */
mbed_official 464:04583941e294 2013 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 464:04583941e294 2014 #define CAN_FMR_FINIT ((uint32_t)0x01) /*!<Filter Init Mode */
mbed_official 464:04583941e294 2015 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
mbed_official 464:04583941e294 2016
mbed_official 464:04583941e294 2017 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 464:04583941e294 2018 #define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
mbed_official 464:04583941e294 2019 #define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
mbed_official 464:04583941e294 2020 #define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
mbed_official 464:04583941e294 2021 #define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
mbed_official 464:04583941e294 2022 #define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
mbed_official 464:04583941e294 2023 #define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
mbed_official 464:04583941e294 2024 #define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
mbed_official 464:04583941e294 2025 #define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
mbed_official 464:04583941e294 2026 #define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
mbed_official 464:04583941e294 2027 #define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
mbed_official 464:04583941e294 2028 #define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
mbed_official 464:04583941e294 2029 #define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
mbed_official 464:04583941e294 2030 #define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
mbed_official 464:04583941e294 2031 #define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
mbed_official 464:04583941e294 2032 #define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
mbed_official 464:04583941e294 2033
mbed_official 464:04583941e294 2034 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 464:04583941e294 2035 #define CAN_FS1R_FSC ((uint32_t)0x3FFF) /*!<Filter Scale Configuration */
mbed_official 464:04583941e294 2036 #define CAN_FS1R_FSC0 ((uint32_t)0x0001) /*!<Filter Scale Configuration bit 0 */
mbed_official 464:04583941e294 2037 #define CAN_FS1R_FSC1 ((uint32_t)0x0002) /*!<Filter Scale Configuration bit 1 */
mbed_official 464:04583941e294 2038 #define CAN_FS1R_FSC2 ((uint32_t)0x0004) /*!<Filter Scale Configuration bit 2 */
mbed_official 464:04583941e294 2039 #define CAN_FS1R_FSC3 ((uint32_t)0x0008) /*!<Filter Scale Configuration bit 3 */
mbed_official 464:04583941e294 2040 #define CAN_FS1R_FSC4 ((uint32_t)0x0010) /*!<Filter Scale Configuration bit 4 */
mbed_official 464:04583941e294 2041 #define CAN_FS1R_FSC5 ((uint32_t)0x0020) /*!<Filter Scale Configuration bit 5 */
mbed_official 464:04583941e294 2042 #define CAN_FS1R_FSC6 ((uint32_t)0x0040) /*!<Filter Scale Configuration bit 6 */
mbed_official 464:04583941e294 2043 #define CAN_FS1R_FSC7 ((uint32_t)0x0080) /*!<Filter Scale Configuration bit 7 */
mbed_official 464:04583941e294 2044 #define CAN_FS1R_FSC8 ((uint32_t)0x0100) /*!<Filter Scale Configuration bit 8 */
mbed_official 464:04583941e294 2045 #define CAN_FS1R_FSC9 ((uint32_t)0x0200) /*!<Filter Scale Configuration bit 9 */
mbed_official 464:04583941e294 2046 #define CAN_FS1R_FSC10 ((uint32_t)0x0400) /*!<Filter Scale Configuration bit 10 */
mbed_official 464:04583941e294 2047 #define CAN_FS1R_FSC11 ((uint32_t)0x0800) /*!<Filter Scale Configuration bit 11 */
mbed_official 464:04583941e294 2048 #define CAN_FS1R_FSC12 ((uint32_t)0x1000) /*!<Filter Scale Configuration bit 12 */
mbed_official 464:04583941e294 2049 #define CAN_FS1R_FSC13 ((uint32_t)0x2000) /*!<Filter Scale Configuration bit 13 */
mbed_official 464:04583941e294 2050
mbed_official 464:04583941e294 2051 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 464:04583941e294 2052 #define CAN_FFA1R_FFA ((uint32_t)0x3FFF) /*!<Filter FIFO Assignment */
mbed_official 464:04583941e294 2053 #define CAN_FFA1R_FFA0 ((uint32_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
mbed_official 464:04583941e294 2054 #define CAN_FFA1R_FFA1 ((uint32_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
mbed_official 464:04583941e294 2055 #define CAN_FFA1R_FFA2 ((uint32_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
mbed_official 464:04583941e294 2056 #define CAN_FFA1R_FFA3 ((uint32_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
mbed_official 464:04583941e294 2057 #define CAN_FFA1R_FFA4 ((uint32_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
mbed_official 464:04583941e294 2058 #define CAN_FFA1R_FFA5 ((uint32_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
mbed_official 464:04583941e294 2059 #define CAN_FFA1R_FFA6 ((uint32_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
mbed_official 464:04583941e294 2060 #define CAN_FFA1R_FFA7 ((uint32_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
mbed_official 464:04583941e294 2061 #define CAN_FFA1R_FFA8 ((uint32_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
mbed_official 464:04583941e294 2062 #define CAN_FFA1R_FFA9 ((uint32_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
mbed_official 464:04583941e294 2063 #define CAN_FFA1R_FFA10 ((uint32_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
mbed_official 464:04583941e294 2064 #define CAN_FFA1R_FFA11 ((uint32_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
mbed_official 464:04583941e294 2065 #define CAN_FFA1R_FFA12 ((uint32_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
mbed_official 464:04583941e294 2066 #define CAN_FFA1R_FFA13 ((uint32_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
mbed_official 464:04583941e294 2067
mbed_official 464:04583941e294 2068 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 464:04583941e294 2069 #define CAN_FA1R_FACT ((uint32_t)0x3FFF) /*!<Filter Active */
mbed_official 464:04583941e294 2070 #define CAN_FA1R_FACT0 ((uint32_t)0x0001) /*!<Filter 0 Active */
mbed_official 464:04583941e294 2071 #define CAN_FA1R_FACT1 ((uint32_t)0x0002) /*!<Filter 1 Active */
mbed_official 464:04583941e294 2072 #define CAN_FA1R_FACT2 ((uint32_t)0x0004) /*!<Filter 2 Active */
mbed_official 464:04583941e294 2073 #define CAN_FA1R_FACT3 ((uint32_t)0x0008) /*!<Filter 3 Active */
mbed_official 464:04583941e294 2074 #define CAN_FA1R_FACT4 ((uint32_t)0x0010) /*!<Filter 4 Active */
mbed_official 464:04583941e294 2075 #define CAN_FA1R_FACT5 ((uint32_t)0x0020) /*!<Filter 5 Active */
mbed_official 464:04583941e294 2076 #define CAN_FA1R_FACT6 ((uint32_t)0x0040) /*!<Filter 6 Active */
mbed_official 464:04583941e294 2077 #define CAN_FA1R_FACT7 ((uint32_t)0x0080) /*!<Filter 7 Active */
mbed_official 464:04583941e294 2078 #define CAN_FA1R_FACT8 ((uint32_t)0x0100) /*!<Filter 8 Active */
mbed_official 464:04583941e294 2079 #define CAN_FA1R_FACT9 ((uint32_t)0x0200) /*!<Filter 9 Active */
mbed_official 464:04583941e294 2080 #define CAN_FA1R_FACT10 ((uint32_t)0x0400) /*!<Filter 10 Active */
mbed_official 464:04583941e294 2081 #define CAN_FA1R_FACT11 ((uint32_t)0x0800) /*!<Filter 11 Active */
mbed_official 464:04583941e294 2082 #define CAN_FA1R_FACT12 ((uint32_t)0x1000) /*!<Filter 12 Active */
mbed_official 464:04583941e294 2083 #define CAN_FA1R_FACT13 ((uint32_t)0x2000) /*!<Filter 13 Active */
mbed_official 464:04583941e294 2084
mbed_official 464:04583941e294 2085 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 464:04583941e294 2086 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2087 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2088 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2089 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2090 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2091 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2092 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2093 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2094 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2095 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2096 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2097 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2098 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2099 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2100 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2101 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2102 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2103 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2104 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2105 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2106 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2107 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2108 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2109 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2110 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2111 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2112 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2113 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2114 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2115 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2116 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2117 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2118
mbed_official 464:04583941e294 2119 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 464:04583941e294 2120 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2121 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2122 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2123 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2124 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2125 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2126 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2127 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2128 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2129 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2130 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2131 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2132 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2133 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2134 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2135 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2136 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2137 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2138 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2139 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2140 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2141 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2142 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2143 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2144 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2145 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2146 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2147 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2148 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2149 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2150 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2151 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2152
mbed_official 464:04583941e294 2153 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 464:04583941e294 2154 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2155 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2156 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2157 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2158 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2159 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2160 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2161 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2162 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2163 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2164 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2165 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2166 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2167 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2168 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2169 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2170 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2171 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2172 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2173 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2174 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2175 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2176 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2177 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2178 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2179 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2180 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2181 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2182 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2183 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2184 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2185 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2186
mbed_official 464:04583941e294 2187 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 464:04583941e294 2188 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2189 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2190 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2191 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2192 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2193 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2194 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2195 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2196 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2197 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2198 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2199 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2200 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2201 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2202 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2203 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2204 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2205 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2206 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2207 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2208 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2209 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2210 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2211 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2212 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2213 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2214 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2215 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2216 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2217 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2218 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2219 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2220
mbed_official 464:04583941e294 2221 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 464:04583941e294 2222 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2223 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2224 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2225 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2226 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2227 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2228 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2229 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2230 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2231 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2232 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2233 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2234 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2235 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2236 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2237 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2238 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2239 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2240 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2241 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2242 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2243 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2244 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2245 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2246 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2247 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2248 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2249 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2250 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2251 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2252 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2253 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2254
mbed_official 464:04583941e294 2255 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 464:04583941e294 2256 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2257 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2258 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2259 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2260 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2261 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2262 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2263 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2264 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2265 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2266 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2267 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2268 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2269 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2270 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2271 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2272 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2273 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2274 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2275 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2276 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2277 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2278 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2279 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2280 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2281 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2282 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2283 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2284 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2285 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2286 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2287 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2288
mbed_official 464:04583941e294 2289 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 464:04583941e294 2290 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2291 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2292 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2293 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2294 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2295 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2296 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2297 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2298 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2299 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2300 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2301 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2302 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2303 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2304 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2305 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2306 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2307 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2308 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2309 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2310 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2311 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2312 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2313 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2314 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2315 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2316 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2317 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2318 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2319 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2320 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2321 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2322
mbed_official 464:04583941e294 2323 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 464:04583941e294 2324 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2325 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2326 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2327 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2328 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2329 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2330 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2331 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2332 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2333 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2334 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2335 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2336 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2337 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2338 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2339 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2340 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2341 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2342 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2343 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2344 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2345 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2346 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2347 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2348 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2349 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2350 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2351 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2352 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2353 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2354 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2355 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2356
mbed_official 464:04583941e294 2357 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 464:04583941e294 2358 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2359 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2360 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2361 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2362 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2363 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2364 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2365 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2366 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2367 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2368 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2369 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2370 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2371 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2372 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2373 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2374 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2375 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2376 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2377 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2378 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2379 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2380 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2381 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2382 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2383 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2384 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2385 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2386 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2387 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2388 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2389 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2390
mbed_official 464:04583941e294 2391 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 464:04583941e294 2392 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2393 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2394 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2395 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2396 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2397 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2398 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2399 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2400 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2401 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2402 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2403 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2404 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2405 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2406 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2407 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2408 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2409 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2410 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2411 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2412 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2413 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2414 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2415 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2416 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2417 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2418 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2419 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2420 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2421 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2422 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2423 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2424
mbed_official 464:04583941e294 2425 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 464:04583941e294 2426 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2427 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2428 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2429 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2430 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2431 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2432 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2433 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2434 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2435 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2436 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2437 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2438 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2439 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2440 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2441 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2442 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2443 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2444 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2445 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2446 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2447 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2448 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2449 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2450 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2451 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2452 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2453 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2454 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2455 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2456 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2457 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2458
mbed_official 464:04583941e294 2459 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 464:04583941e294 2460 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2461 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2462 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2463 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2464 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2465 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2466 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2467 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2468 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2469 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2470 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2471 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2472 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2473 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2474 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2475 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2476 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2477 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2478 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2479 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2480 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2481 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2482 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2483 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2484 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2485 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2486 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2487 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2488 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2489 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2490 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2491 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2492
mbed_official 464:04583941e294 2493 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 464:04583941e294 2494 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2495 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2496 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2497 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2498 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2499 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2500 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2501 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2502 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2503 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2504 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2505 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2506 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2507 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2508 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2509 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2510 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2511 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2512 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2513 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2514 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2515 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2516 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2517 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2518 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2519 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2520 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2521 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2522 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2523 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2524 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2525 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2526
mbed_official 464:04583941e294 2527 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 464:04583941e294 2528 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2529 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2530 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2531 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2532 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2533 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2534 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2535 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2536 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2537 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2538 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2539 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2540 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2541 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2542 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2543 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2544 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2545 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2546 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2547 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2548 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2549 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2550 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2551 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2552 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2553 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2554 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2555 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2556 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2557 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2558 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2559 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2560
mbed_official 464:04583941e294 2561 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 464:04583941e294 2562 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2563 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2564 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2565 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2566 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2567 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2568 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2569 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2570 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2571 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2572 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2573 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2574 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2575 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2576 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2577 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2578 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2579 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2580 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2581 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2582 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2583 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2584 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2585 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2586 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2587 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2588 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2589 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2590 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2591 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2592 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2593 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2594
mbed_official 464:04583941e294 2595 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 464:04583941e294 2596 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2597 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2598 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2599 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2600 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2601 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2602 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2603 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2604 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2605 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2606 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2607 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2608 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2609 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2610 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2611 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2612 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2613 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2614 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2615 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2616 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2617 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2618 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2619 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2620 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2621 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2622 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2623 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2624 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2625 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2626 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2627 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2628
mbed_official 464:04583941e294 2629 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 464:04583941e294 2630 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2631 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2632 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2633 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2634 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2635 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2636 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2637 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2638 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2639 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2640 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2641 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2642 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2643 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2644 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2645 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2646 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2647 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2648 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2649 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2650 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2651 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2652 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2653 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2654 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2655 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2656 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2657 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2658 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2659 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2660 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2661 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2662
mbed_official 464:04583941e294 2663 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 464:04583941e294 2664 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2665 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2666 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2667 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2668 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2669 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2670 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2671 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2672 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2673 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2674 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2675 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2676 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2677 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2678 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2679 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2680 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2681 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2682 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2683 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2684 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2685 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2686 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2687 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2688 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2689 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2690 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2691 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2692 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2693 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2694 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2695 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2696
mbed_official 464:04583941e294 2697 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 464:04583941e294 2698 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2699 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2700 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2701 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2702 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2703 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2704 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2705 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2706 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2707 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2708 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2709 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2710 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2711 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2712 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2713 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2714 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2715 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2716 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2717 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2718 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2719 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2720 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2721 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2722 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2723 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2724 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2725 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2726 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2727 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2728 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2729 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2730
mbed_official 464:04583941e294 2731 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 464:04583941e294 2732 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2733 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2734 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2735 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2736 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2737 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2738 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2739 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2740 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2741 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2742 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2743 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2744 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2745 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2746 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2747 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2748 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2749 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2750 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2751 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2752 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2753 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2754 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2755 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2756 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2757 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2758 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2759 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2760 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2761 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2762 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2763 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2764
mbed_official 464:04583941e294 2765 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 464:04583941e294 2766 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2767 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2768 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2769 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2770 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2771 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2772 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2773 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2774 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2775 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2776 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2777 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2778 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2779 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2780 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2781 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2782 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2783 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2784 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2785 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2786 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2787 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2788 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2789 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2790 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2791 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2792 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2793 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2794 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2795 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2796 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2797 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2798
mbed_official 464:04583941e294 2799 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 464:04583941e294 2800 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2801 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2802 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2803 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2804 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2805 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2806 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2807 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2808 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2809 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2810 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2811 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2812 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2813 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2814 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2815 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2816 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2817 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2818 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2819 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2820 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2821 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2822 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2823 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2824 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2825 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2826 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2827 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2828 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2829 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2830 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2831 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2832
mbed_official 464:04583941e294 2833 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 464:04583941e294 2834 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2835 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2836 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2837 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2838 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2839 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2840 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2841 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2842 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2843 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2844 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2845 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2846 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2847 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2848 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2849 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2850 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2851 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2852 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2853 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2854 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2855 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2856 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2857 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2858 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2859 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2860 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2861 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2862 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2863 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2864 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2865 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2866
mbed_official 464:04583941e294 2867 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 464:04583941e294 2868 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2869 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2870 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2871 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2872 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2873 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2874 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2875 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2876 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2877 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2878 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2879 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2880 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2881 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2882 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2883 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2884 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2885 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2886 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2887 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2888 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2889 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2890 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2891 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2892 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2893 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2894 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2895 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2896 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2897 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2898 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2899 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2900
mbed_official 464:04583941e294 2901 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 464:04583941e294 2902 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2903 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2904 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2905 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2906 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2907 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2908 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2909 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2910 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2911 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2912 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2913 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2914 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2915 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2916 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2917 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2918 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2919 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2920 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2921 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2922 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2923 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2924 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2925 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2926 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2927 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2928 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2929 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2930 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2931 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2932 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2933 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2934
mbed_official 464:04583941e294 2935 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 464:04583941e294 2936 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2937 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2938 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2939 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2940 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2941 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2942 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2943 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2944 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2945 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2946 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2947 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2948 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2949 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2950 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2951 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2952 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2953 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2954 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2955 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2956 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2957 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2958 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2959 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2960 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2961 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2962 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2963 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2964 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2965 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 2966 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 2967 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 2968
mbed_official 464:04583941e294 2969 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 464:04583941e294 2970 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 2971 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 2972 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 2973 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 2974 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 2975 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 2976 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 2977 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 2978 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 2979 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 2980 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 2981 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 2982 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 2983 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 2984 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 2985 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 2986 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 2987 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 2988 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 2989 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 2990 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 2991 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 2992 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 2993 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 2994 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 2995 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 2996 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 2997 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 2998 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 2999 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 3000 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 3001 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 3002
mbed_official 464:04583941e294 3003 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 464:04583941e294 3004 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 464:04583941e294 3005 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 464:04583941e294 3006 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 464:04583941e294 3007 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 464:04583941e294 3008 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 464:04583941e294 3009 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 464:04583941e294 3010 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 464:04583941e294 3011 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 464:04583941e294 3012 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 464:04583941e294 3013 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 464:04583941e294 3014 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 464:04583941e294 3015 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 464:04583941e294 3016 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 464:04583941e294 3017 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 464:04583941e294 3018 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 464:04583941e294 3019 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 464:04583941e294 3020 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 464:04583941e294 3021 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 464:04583941e294 3022 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 464:04583941e294 3023 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 464:04583941e294 3024 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 464:04583941e294 3025 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 464:04583941e294 3026 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 464:04583941e294 3027 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 464:04583941e294 3028 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 464:04583941e294 3029 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 464:04583941e294 3030 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 464:04583941e294 3031 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 464:04583941e294 3032 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 464:04583941e294 3033 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 464:04583941e294 3034 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 464:04583941e294 3035 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 464:04583941e294 3036
mbed_official 464:04583941e294 3037 /******************************************************************************/
mbed_official 464:04583941e294 3038 /* */
mbed_official 464:04583941e294 3039 /* CRC calculation unit */
mbed_official 464:04583941e294 3040 /* */
mbed_official 464:04583941e294 3041 /******************************************************************************/
mbed_official 464:04583941e294 3042 /******************* Bit definition for CRC_DR register *********************/
mbed_official 464:04583941e294 3043 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 464:04583941e294 3044
mbed_official 464:04583941e294 3045
mbed_official 464:04583941e294 3046 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 464:04583941e294 3047 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 464:04583941e294 3048
mbed_official 464:04583941e294 3049
mbed_official 464:04583941e294 3050 /******************** Bit definition for CRC_CR register ********************/
mbed_official 464:04583941e294 3051 #define CRC_CR_RESET ((uint32_t)0x01) /*!< RESET bit */
mbed_official 464:04583941e294 3052
mbed_official 464:04583941e294 3053 /******************************************************************************/
mbed_official 464:04583941e294 3054 /* */
mbed_official 464:04583941e294 3055 /* Crypto Processor */
mbed_official 464:04583941e294 3056 /* */
mbed_official 464:04583941e294 3057 /******************************************************************************/
mbed_official 464:04583941e294 3058 /******************* Bits definition for CRYP_CR register ********************/
mbed_official 464:04583941e294 3059 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3060
mbed_official 464:04583941e294 3061 #define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)
mbed_official 464:04583941e294 3062 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3063 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3064 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3065 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
mbed_official 464:04583941e294 3066 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3067 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3068 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)
mbed_official 464:04583941e294 3069 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3070 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)
mbed_official 464:04583941e294 3071 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)
mbed_official 464:04583941e294 3072 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)
mbed_official 464:04583941e294 3073
mbed_official 464:04583941e294 3074 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)
mbed_official 464:04583941e294 3075 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3076 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 3077 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)
mbed_official 464:04583941e294 3078 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3079 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3080 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000)
mbed_official 464:04583941e294 3081 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000)
mbed_official 464:04583941e294 3082
mbed_official 464:04583941e294 3083 #define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)
mbed_official 464:04583941e294 3084 #define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 3085 #define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 3086 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 3087
mbed_official 464:04583941e294 3088 /****************** Bits definition for CRYP_SR register *********************/
mbed_official 464:04583941e294 3089 #define CRYP_SR_IFEM ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3090 #define CRYP_SR_IFNF ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3091 #define CRYP_SR_OFNE ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3092 #define CRYP_SR_OFFU ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3093 #define CRYP_SR_BUSY ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3094 /****************** Bits definition for CRYP_DMACR register ******************/
mbed_official 464:04583941e294 3095 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3096 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3097 /***************** Bits definition for CRYP_IMSCR register ******************/
mbed_official 464:04583941e294 3098 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3099 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3100 /****************** Bits definition for CRYP_RISR register *******************/
mbed_official 464:04583941e294 3101 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3102 #define CRYP_RISR_INRIS ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3103 /****************** Bits definition for CRYP_MISR register *******************/
mbed_official 464:04583941e294 3104 #define CRYP_MISR_INMIS ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3105 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3106
mbed_official 464:04583941e294 3107 /******************************************************************************/
mbed_official 464:04583941e294 3108 /* */
mbed_official 464:04583941e294 3109 /* Digital to Analog Converter */
mbed_official 464:04583941e294 3110 /* */
mbed_official 464:04583941e294 3111 /******************************************************************************/
mbed_official 464:04583941e294 3112 /******************** Bit definition for DAC_CR register ********************/
mbed_official 464:04583941e294 3113 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
mbed_official 464:04583941e294 3114 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
mbed_official 464:04583941e294 3115 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
mbed_official 464:04583941e294 3116
mbed_official 464:04583941e294 3117 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 464:04583941e294 3118 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 464:04583941e294 3119 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 464:04583941e294 3120 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 464:04583941e294 3121
mbed_official 464:04583941e294 3122 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 464:04583941e294 3123 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 464:04583941e294 3124 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 464:04583941e294 3125
mbed_official 464:04583941e294 3126 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 464:04583941e294 3127 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 3128 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 3129 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 3130 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 3131
mbed_official 464:04583941e294 3132 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
mbed_official 464:04583941e294 3133 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
mbed_official 464:04583941e294 3134 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
mbed_official 464:04583941e294 3135 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
mbed_official 464:04583941e294 3136
mbed_official 464:04583941e294 3137 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 464:04583941e294 3138 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
mbed_official 464:04583941e294 3139 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
mbed_official 464:04583941e294 3140 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
mbed_official 464:04583941e294 3141
mbed_official 464:04583941e294 3142 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 464:04583941e294 3143 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 464:04583941e294 3144 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 464:04583941e294 3145
mbed_official 464:04583941e294 3146 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 464:04583941e294 3147 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 3148 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 3149 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 3150 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 3151
mbed_official 464:04583941e294 3152 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
mbed_official 464:04583941e294 3153
mbed_official 464:04583941e294 3154 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 464:04583941e294 3155 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
mbed_official 464:04583941e294 3156 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
mbed_official 464:04583941e294 3157
mbed_official 464:04583941e294 3158 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 464:04583941e294 3159 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 464:04583941e294 3160
mbed_official 464:04583941e294 3161 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 464:04583941e294 3162 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 464:04583941e294 3163
mbed_official 464:04583941e294 3164 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 464:04583941e294 3165 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 464:04583941e294 3166
mbed_official 464:04583941e294 3167 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 464:04583941e294 3168 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 464:04583941e294 3169
mbed_official 464:04583941e294 3170 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 464:04583941e294 3171 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 464:04583941e294 3172
mbed_official 464:04583941e294 3173 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 464:04583941e294 3174 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 464:04583941e294 3175
mbed_official 464:04583941e294 3176 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 464:04583941e294 3177 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 464:04583941e294 3178 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 464:04583941e294 3179
mbed_official 464:04583941e294 3180 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 464:04583941e294 3181 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 464:04583941e294 3182 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 464:04583941e294 3183
mbed_official 464:04583941e294 3184 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 464:04583941e294 3185 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 464:04583941e294 3186 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 464:04583941e294 3187
mbed_official 464:04583941e294 3188 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 464:04583941e294 3189 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
mbed_official 464:04583941e294 3190
mbed_official 464:04583941e294 3191 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 464:04583941e294 3192 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
mbed_official 464:04583941e294 3193
mbed_official 464:04583941e294 3194 /******************** Bit definition for DAC_SR register ********************/
mbed_official 464:04583941e294 3195 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
mbed_official 464:04583941e294 3196 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
mbed_official 464:04583941e294 3197
mbed_official 464:04583941e294 3198 /******************************************************************************/
mbed_official 464:04583941e294 3199 /* */
mbed_official 464:04583941e294 3200 /* Debug MCU */
mbed_official 464:04583941e294 3201 /* */
mbed_official 464:04583941e294 3202 /******************************************************************************/
mbed_official 464:04583941e294 3203
mbed_official 464:04583941e294 3204 /******************************************************************************/
mbed_official 464:04583941e294 3205 /* */
mbed_official 464:04583941e294 3206 /* DCMI */
mbed_official 464:04583941e294 3207 /* */
mbed_official 464:04583941e294 3208 /******************************************************************************/
mbed_official 464:04583941e294 3209 /******************** Bits definition for DCMI_CR register ******************/
mbed_official 464:04583941e294 3210 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3211 #define DCMI_CR_CM ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3212 #define DCMI_CR_CROP ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3213 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3214 #define DCMI_CR_ESS ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3215 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3216 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3217 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
mbed_official 464:04583941e294 3218 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3219 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3220 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 3221 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 3222 #define DCMI_CR_CRE ((uint32_t)0x00001000)
mbed_official 464:04583941e294 3223 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
mbed_official 464:04583941e294 3224
mbed_official 464:04583941e294 3225 /******************** Bits definition for DCMI_SR register ******************/
mbed_official 464:04583941e294 3226 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3227 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3228 #define DCMI_SR_FNE ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3229
mbed_official 464:04583941e294 3230 /******************** Bits definition for DCMI_RISR register ****************/
mbed_official 464:04583941e294 3231 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3232 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3233 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3234 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3235 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3236
mbed_official 464:04583941e294 3237 /******************** Bits definition for DCMI_IER register *****************/
mbed_official 464:04583941e294 3238 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3239 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3240 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3241 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3242 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3243
mbed_official 464:04583941e294 3244 /******************** Bits definition for DCMI_MISR register ****************/
mbed_official 464:04583941e294 3245 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3246 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3247 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3248 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3249 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3250
mbed_official 464:04583941e294 3251 /******************** Bits definition for DCMI_ICR register *****************/
mbed_official 464:04583941e294 3252 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3253 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3254 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3255 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3256 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3257
mbed_official 464:04583941e294 3258 /******************************************************************************/
mbed_official 464:04583941e294 3259 /* */
mbed_official 464:04583941e294 3260 /* DMA Controller */
mbed_official 464:04583941e294 3261 /* */
mbed_official 464:04583941e294 3262 /******************************************************************************/
mbed_official 464:04583941e294 3263 /******************** Bits definition for DMA_SxCR register *****************/
mbed_official 464:04583941e294 3264 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
mbed_official 464:04583941e294 3265 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 3266 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 3267 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 3268 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
mbed_official 464:04583941e294 3269 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
mbed_official 464:04583941e294 3270 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 3271 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
mbed_official 464:04583941e294 3272 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 3273 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 3274 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
mbed_official 464:04583941e294 3275 #define DMA_SxCR_CT ((uint32_t)0x00080000)
mbed_official 464:04583941e294 3276 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
mbed_official 464:04583941e294 3277 #define DMA_SxCR_PL ((uint32_t)0x00030000)
mbed_official 464:04583941e294 3278 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 3279 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 3280 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
mbed_official 464:04583941e294 3281 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
mbed_official 464:04583941e294 3282 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 3283 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 3284 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
mbed_official 464:04583941e294 3285 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 3286 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 3287 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
mbed_official 464:04583941e294 3288 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3289 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3290 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
mbed_official 464:04583941e294 3291 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3292 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 3293 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3294 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3295 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3296 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3297 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3298 #define DMA_SxCR_EN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3299
mbed_official 464:04583941e294 3300 /******************** Bits definition for DMA_SxCNDTR register **************/
mbed_official 464:04583941e294 3301 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
mbed_official 464:04583941e294 3302 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3303 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3304 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3305 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3306 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3307 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3308 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3309 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 3310 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3311 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3312 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 3313 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 3314 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 3315 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 3316 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 3317 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 3318
mbed_official 464:04583941e294 3319 /******************** Bits definition for DMA_SxFCR register ****************/
mbed_official 464:04583941e294 3320 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
mbed_official 464:04583941e294 3321 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
mbed_official 464:04583941e294 3322 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3323 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3324 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3325 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3326 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
mbed_official 464:04583941e294 3327 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3328 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3329
mbed_official 464:04583941e294 3330 /******************** Bits definition for DMA_LISR register *****************/
mbed_official 464:04583941e294 3331 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 3332 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 3333 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 3334 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 3335 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 3336 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 3337 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 3338 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 3339 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 3340 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 3341 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 3342 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 3343 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3344 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3345 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3346 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3347 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3348 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3349 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3350 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3351
mbed_official 464:04583941e294 3352 /******************** Bits definition for DMA_HISR register *****************/
mbed_official 464:04583941e294 3353 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 3354 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 3355 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 3356 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 3357 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 3358 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 3359 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 3360 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 3361 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 3362 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 3363 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 3364 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 3365 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3366 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3367 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3368 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3369 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3370 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3371 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3372 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3373
mbed_official 464:04583941e294 3374 /******************** Bits definition for DMA_LIFCR register ****************/
mbed_official 464:04583941e294 3375 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 3376 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 3377 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 3378 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 3379 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 3380 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 3381 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 3382 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 3383 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 3384 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 3385 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 3386 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 3387 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3388 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3389 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3390 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3391 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3392 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3393 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3394 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3395
mbed_official 464:04583941e294 3396 /******************** Bits definition for DMA_HIFCR register ****************/
mbed_official 464:04583941e294 3397 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 3398 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 3399 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 3400 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 3401 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 3402 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 3403 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 3404 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 3405 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 3406 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 3407 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 3408 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 3409 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3410 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3411 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3412 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3413 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3414 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3415 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3416 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3417
mbed_official 464:04583941e294 3418
mbed_official 464:04583941e294 3419 /******************************************************************************/
mbed_official 464:04583941e294 3420 /* */
mbed_official 464:04583941e294 3421 /* AHB Master DMA2D Controller (DMA2D) */
mbed_official 464:04583941e294 3422 /* */
mbed_official 464:04583941e294 3423 /******************************************************************************/
mbed_official 464:04583941e294 3424
mbed_official 464:04583941e294 3425 /******************** Bit definition for DMA2D_CR register ******************/
mbed_official 464:04583941e294 3426
mbed_official 464:04583941e294 3427 #define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
mbed_official 464:04583941e294 3428 #define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
mbed_official 464:04583941e294 3429 #define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
mbed_official 464:04583941e294 3430 #define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
mbed_official 464:04583941e294 3431 #define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
mbed_official 464:04583941e294 3432 #define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
mbed_official 464:04583941e294 3433 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
mbed_official 464:04583941e294 3434 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
mbed_official 464:04583941e294 3435 #define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
mbed_official 464:04583941e294 3436 #define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
mbed_official 464:04583941e294 3437
mbed_official 464:04583941e294 3438 /******************** Bit definition for DMA2D_ISR register *****************/
mbed_official 464:04583941e294 3439
mbed_official 464:04583941e294 3440 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
mbed_official 464:04583941e294 3441 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
mbed_official 464:04583941e294 3442 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
mbed_official 464:04583941e294 3443 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
mbed_official 464:04583941e294 3444 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
mbed_official 464:04583941e294 3445 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
mbed_official 464:04583941e294 3446
mbed_official 464:04583941e294 3447 /******************** Bit definition for DMA2D_IFSR register ****************/
mbed_official 464:04583941e294 3448
mbed_official 464:04583941e294 3449 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
mbed_official 464:04583941e294 3450 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
mbed_official 464:04583941e294 3451 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
mbed_official 464:04583941e294 3452 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
mbed_official 464:04583941e294 3453 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
mbed_official 464:04583941e294 3454 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
mbed_official 464:04583941e294 3455
mbed_official 464:04583941e294 3456 /******************** Bit definition for DMA2D_FGMAR register ***************/
mbed_official 464:04583941e294 3457
mbed_official 464:04583941e294 3458 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 464:04583941e294 3459
mbed_official 464:04583941e294 3460 /******************** Bit definition for DMA2D_FGOR register ****************/
mbed_official 464:04583941e294 3461
mbed_official 464:04583941e294 3462 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
mbed_official 464:04583941e294 3463
mbed_official 464:04583941e294 3464 /******************** Bit definition for DMA2D_BGMAR register ***************/
mbed_official 464:04583941e294 3465
mbed_official 464:04583941e294 3466 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 464:04583941e294 3467
mbed_official 464:04583941e294 3468 /******************** Bit definition for DMA2D_BGOR register ****************/
mbed_official 464:04583941e294 3469
mbed_official 464:04583941e294 3470 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
mbed_official 464:04583941e294 3471
mbed_official 464:04583941e294 3472 /******************** Bit definition for DMA2D_FGPFCCR register *************/
mbed_official 464:04583941e294 3473
mbed_official 464:04583941e294 3474 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
mbed_official 464:04583941e294 3475 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
mbed_official 464:04583941e294 3476 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
mbed_official 464:04583941e294 3477 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
mbed_official 464:04583941e294 3478 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
mbed_official 464:04583941e294 3479 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
mbed_official 464:04583941e294 3480
mbed_official 464:04583941e294 3481 /******************** Bit definition for DMA2D_FGCOLR register **************/
mbed_official 464:04583941e294 3482
mbed_official 464:04583941e294 3483 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
mbed_official 464:04583941e294 3484 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
mbed_official 464:04583941e294 3485 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
mbed_official 464:04583941e294 3486
mbed_official 464:04583941e294 3487 /******************** Bit definition for DMA2D_BGPFCCR register *************/
mbed_official 464:04583941e294 3488
mbed_official 464:04583941e294 3489 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
mbed_official 464:04583941e294 3490 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
mbed_official 464:04583941e294 3491 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
mbed_official 464:04583941e294 3492 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
mbed_official 464:04583941e294 3493 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
mbed_official 464:04583941e294 3494 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
mbed_official 464:04583941e294 3495
mbed_official 464:04583941e294 3496 /******************** Bit definition for DMA2D_BGCOLR register **************/
mbed_official 464:04583941e294 3497
mbed_official 464:04583941e294 3498 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
mbed_official 464:04583941e294 3499 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
mbed_official 464:04583941e294 3500 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
mbed_official 464:04583941e294 3501
mbed_official 464:04583941e294 3502 /******************** Bit definition for DMA2D_FGCMAR register **************/
mbed_official 464:04583941e294 3503
mbed_official 464:04583941e294 3504 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 464:04583941e294 3505
mbed_official 464:04583941e294 3506 /******************** Bit definition for DMA2D_BGCMAR register **************/
mbed_official 464:04583941e294 3507
mbed_official 464:04583941e294 3508 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 464:04583941e294 3509
mbed_official 464:04583941e294 3510 /******************** Bit definition for DMA2D_OPFCCR register **************/
mbed_official 464:04583941e294 3511
mbed_official 464:04583941e294 3512 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
mbed_official 464:04583941e294 3513
mbed_official 464:04583941e294 3514 /******************** Bit definition for DMA2D_OCOLR register ***************/
mbed_official 464:04583941e294 3515
mbed_official 464:04583941e294 3516 /*!<Mode_ARGB8888/RGB888 */
mbed_official 464:04583941e294 3517
mbed_official 464:04583941e294 3518 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
mbed_official 464:04583941e294 3519 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
mbed_official 464:04583941e294 3520 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
mbed_official 464:04583941e294 3521 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
mbed_official 464:04583941e294 3522
mbed_official 464:04583941e294 3523 /*!<Mode_RGB565 */
mbed_official 464:04583941e294 3524 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
mbed_official 464:04583941e294 3525 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
mbed_official 464:04583941e294 3526 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
mbed_official 464:04583941e294 3527
mbed_official 464:04583941e294 3528 /*!<Mode_ARGB1555 */
mbed_official 464:04583941e294 3529 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
mbed_official 464:04583941e294 3530 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
mbed_official 464:04583941e294 3531 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
mbed_official 464:04583941e294 3532 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
mbed_official 464:04583941e294 3533
mbed_official 464:04583941e294 3534 /*!<Mode_ARGB4444 */
mbed_official 464:04583941e294 3535 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
mbed_official 464:04583941e294 3536 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
mbed_official 464:04583941e294 3537 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
mbed_official 464:04583941e294 3538 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
mbed_official 464:04583941e294 3539
mbed_official 464:04583941e294 3540 /******************** Bit definition for DMA2D_OMAR register ****************/
mbed_official 464:04583941e294 3541
mbed_official 464:04583941e294 3542 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 464:04583941e294 3543
mbed_official 464:04583941e294 3544 /******************** Bit definition for DMA2D_OOR register *****************/
mbed_official 464:04583941e294 3545
mbed_official 464:04583941e294 3546 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
mbed_official 464:04583941e294 3547
mbed_official 464:04583941e294 3548 /******************** Bit definition for DMA2D_NLR register *****************/
mbed_official 464:04583941e294 3549
mbed_official 464:04583941e294 3550 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
mbed_official 464:04583941e294 3551 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
mbed_official 464:04583941e294 3552
mbed_official 464:04583941e294 3553 /******************** Bit definition for DMA2D_LWR register *****************/
mbed_official 464:04583941e294 3554
mbed_official 464:04583941e294 3555 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
mbed_official 464:04583941e294 3556
mbed_official 464:04583941e294 3557 /******************** Bit definition for DMA2D_AMTCR register ***************/
mbed_official 464:04583941e294 3558
mbed_official 464:04583941e294 3559 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
mbed_official 464:04583941e294 3560 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
mbed_official 464:04583941e294 3561
mbed_official 464:04583941e294 3562
mbed_official 464:04583941e294 3563 /******************** Bit definition for DMA2D_FGCLUT register **************/
mbed_official 464:04583941e294 3564
mbed_official 464:04583941e294 3565 /******************** Bit definition for DMA2D_BGCLUT register **************/
mbed_official 464:04583941e294 3566
mbed_official 464:04583941e294 3567
mbed_official 464:04583941e294 3568
mbed_official 464:04583941e294 3569 /******************************************************************************/
mbed_official 464:04583941e294 3570 /* */
mbed_official 464:04583941e294 3571 /* External Interrupt/Event Controller */
mbed_official 464:04583941e294 3572 /* */
mbed_official 464:04583941e294 3573 /******************************************************************************/
mbed_official 464:04583941e294 3574 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 464:04583941e294 3575 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 464:04583941e294 3576 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 464:04583941e294 3577 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 464:04583941e294 3578 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 464:04583941e294 3579 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 464:04583941e294 3580 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 464:04583941e294 3581 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 464:04583941e294 3582 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 464:04583941e294 3583 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 464:04583941e294 3584 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 464:04583941e294 3585 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 464:04583941e294 3586 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 464:04583941e294 3587 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 464:04583941e294 3588 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 464:04583941e294 3589 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 464:04583941e294 3590 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 464:04583941e294 3591 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 464:04583941e294 3592 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 464:04583941e294 3593 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 464:04583941e294 3594 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 464:04583941e294 3595
mbed_official 464:04583941e294 3596 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 464:04583941e294 3597 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 464:04583941e294 3598 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 464:04583941e294 3599 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 464:04583941e294 3600 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 464:04583941e294 3601 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 464:04583941e294 3602 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 464:04583941e294 3603 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 464:04583941e294 3604 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 464:04583941e294 3605 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 464:04583941e294 3606 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 464:04583941e294 3607 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 464:04583941e294 3608 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 464:04583941e294 3609 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 464:04583941e294 3610 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 464:04583941e294 3611 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 464:04583941e294 3612 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 464:04583941e294 3613 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 464:04583941e294 3614 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 464:04583941e294 3615 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 464:04583941e294 3616 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 464:04583941e294 3617
mbed_official 464:04583941e294 3618 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 464:04583941e294 3619 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 464:04583941e294 3620 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 464:04583941e294 3621 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 464:04583941e294 3622 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 464:04583941e294 3623 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 464:04583941e294 3624 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 464:04583941e294 3625 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 464:04583941e294 3626 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 464:04583941e294 3627 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 464:04583941e294 3628 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 464:04583941e294 3629 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 464:04583941e294 3630 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 464:04583941e294 3631 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 464:04583941e294 3632 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 464:04583941e294 3633 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 464:04583941e294 3634 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 464:04583941e294 3635 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 464:04583941e294 3636 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 464:04583941e294 3637 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 464:04583941e294 3638 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 464:04583941e294 3639
mbed_official 464:04583941e294 3640 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 464:04583941e294 3641 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 464:04583941e294 3642 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 464:04583941e294 3643 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 464:04583941e294 3644 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 464:04583941e294 3645 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 464:04583941e294 3646 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 464:04583941e294 3647 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 464:04583941e294 3648 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 464:04583941e294 3649 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 464:04583941e294 3650 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 464:04583941e294 3651 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 464:04583941e294 3652 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 464:04583941e294 3653 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 464:04583941e294 3654 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 464:04583941e294 3655 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 464:04583941e294 3656 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 464:04583941e294 3657 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 464:04583941e294 3658 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 464:04583941e294 3659 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 464:04583941e294 3660 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 464:04583941e294 3661
mbed_official 464:04583941e294 3662 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 464:04583941e294 3663 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 464:04583941e294 3664 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 464:04583941e294 3665 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 464:04583941e294 3666 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 464:04583941e294 3667 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 464:04583941e294 3668 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 464:04583941e294 3669 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 464:04583941e294 3670 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 464:04583941e294 3671 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 464:04583941e294 3672 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 464:04583941e294 3673 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 464:04583941e294 3674 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 464:04583941e294 3675 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 464:04583941e294 3676 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 464:04583941e294 3677 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 464:04583941e294 3678 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 464:04583941e294 3679 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 464:04583941e294 3680 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 464:04583941e294 3681 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 464:04583941e294 3682 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 464:04583941e294 3683
mbed_official 464:04583941e294 3684 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 464:04583941e294 3685 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 464:04583941e294 3686 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 464:04583941e294 3687 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 464:04583941e294 3688 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 464:04583941e294 3689 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 464:04583941e294 3690 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 464:04583941e294 3691 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 464:04583941e294 3692 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 464:04583941e294 3693 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 464:04583941e294 3694 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 464:04583941e294 3695 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 464:04583941e294 3696 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 464:04583941e294 3697 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 464:04583941e294 3698 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 464:04583941e294 3699 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 464:04583941e294 3700 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 464:04583941e294 3701 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 464:04583941e294 3702 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 464:04583941e294 3703 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 464:04583941e294 3704 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 464:04583941e294 3705
mbed_official 464:04583941e294 3706 /******************************************************************************/
mbed_official 464:04583941e294 3707 /* */
mbed_official 464:04583941e294 3708 /* FLASH */
mbed_official 464:04583941e294 3709 /* */
mbed_official 464:04583941e294 3710 /******************************************************************************/
mbed_official 464:04583941e294 3711 /******************* Bits definition for FLASH_ACR register *****************/
mbed_official 464:04583941e294 3712 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
mbed_official 464:04583941e294 3713 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
mbed_official 464:04583941e294 3714 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3715 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3716 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
mbed_official 464:04583941e294 3717 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3718 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
mbed_official 464:04583941e294 3719 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
mbed_official 464:04583941e294 3720 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
mbed_official 464:04583941e294 3721 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3722 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
mbed_official 464:04583941e294 3723 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
mbed_official 464:04583941e294 3724 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
mbed_official 464:04583941e294 3725 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
mbed_official 464:04583941e294 3726 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
mbed_official 464:04583941e294 3727 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
mbed_official 464:04583941e294 3728 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
mbed_official 464:04583941e294 3729 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3730 #define FLASH_ACR_ICEN ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3731 #define FLASH_ACR_DCEN ((uint32_t)0x00000400)
mbed_official 464:04583941e294 3732 #define FLASH_ACR_ICRST ((uint32_t)0x00000800)
mbed_official 464:04583941e294 3733 #define FLASH_ACR_DCRST ((uint32_t)0x00001000)
mbed_official 464:04583941e294 3734 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)
mbed_official 464:04583941e294 3735 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)
mbed_official 464:04583941e294 3736
mbed_official 464:04583941e294 3737 /******************* Bits definition for FLASH_SR register ******************/
mbed_official 464:04583941e294 3738 #define FLASH_SR_EOP ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3739 #define FLASH_SR_SOP ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3740 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3741 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3742 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3743 #define FLASH_SR_PGSERR ((uint32_t)0x00000080)
mbed_official 464:04583941e294 3744 #define FLASH_SR_BSY ((uint32_t)0x00010000)
mbed_official 464:04583941e294 3745
mbed_official 464:04583941e294 3746 /******************* Bits definition for FLASH_CR register ******************/
mbed_official 464:04583941e294 3747 #define FLASH_CR_PG ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3748 #define FLASH_CR_SER ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3749 #define FLASH_CR_MER ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3750 #define FLASH_CR_MER1 FLASH_CR_MER
mbed_official 464:04583941e294 3751 #define FLASH_CR_SNB ((uint32_t)0x000000F8)
mbed_official 464:04583941e294 3752 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3753 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3754 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3755 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3756 #define FLASH_CR_SNB_4 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 3757 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
mbed_official 464:04583941e294 3758 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3759 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3760 #define FLASH_CR_MER2 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 3761 #define FLASH_CR_STRT ((uint32_t)0x00010000)
mbed_official 464:04583941e294 3762 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
mbed_official 464:04583941e294 3763 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
mbed_official 464:04583941e294 3764
mbed_official 464:04583941e294 3765 /******************* Bits definition for FLASH_OPTCR register ***************/
mbed_official 464:04583941e294 3766 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
mbed_official 464:04583941e294 3767 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
mbed_official 464:04583941e294 3768 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 3769 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 3770 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
mbed_official 464:04583941e294 3771 #define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 3772 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)
mbed_official 464:04583941e294 3773 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
mbed_official 464:04583941e294 3774 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
mbed_official 464:04583941e294 3775 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
mbed_official 464:04583941e294 3776 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 3777 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 3778 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 3779 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 3780 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 3781 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 3782 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 3783 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 3784 #define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)
mbed_official 464:04583941e294 3785 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 3786 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 3787 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 3788 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 3789 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 3790 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 3791 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 3792 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
mbed_official 464:04583941e294 3793 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 3794 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 3795 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 3796 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 3797 #define FLASH_OPTCR_DB1M ((uint32_t)0x40000000)
mbed_official 464:04583941e294 3798 #define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000)
mbed_official 464:04583941e294 3799
mbed_official 464:04583941e294 3800 /****************** Bits definition for FLASH_OPTCR1 register ***************/
mbed_official 464:04583941e294 3801 #define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)
mbed_official 464:04583941e294 3802 #define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 3803 #define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 3804 #define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 3805 #define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 3806 #define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 3807 #define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 3808 #define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 3809 #define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)
mbed_official 464:04583941e294 3810 #define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 3811 #define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 3812 #define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 3813 #define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 3814
mbed_official 464:04583941e294 3815 /******************************************************************************/
mbed_official 464:04583941e294 3816 /* */
mbed_official 464:04583941e294 3817 /* Flexible Memory Controller */
mbed_official 464:04583941e294 3818 /* */
mbed_official 464:04583941e294 3819 /******************************************************************************/
mbed_official 464:04583941e294 3820 /****************** Bit definition for FMC_BCR1 register *******************/
mbed_official 464:04583941e294 3821 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 464:04583941e294 3822 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 464:04583941e294 3823
mbed_official 464:04583941e294 3824 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 464:04583941e294 3825 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 464:04583941e294 3826 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 464:04583941e294 3827
mbed_official 464:04583941e294 3828 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 464:04583941e294 3829 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 3830 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 3831
mbed_official 464:04583941e294 3832 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 464:04583941e294 3833 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 464:04583941e294 3834 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 464:04583941e294 3835 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 464:04583941e294 3836 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 464:04583941e294 3837 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 464:04583941e294 3838 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 464:04583941e294 3839 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 464:04583941e294 3840 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 464:04583941e294 3841 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 464:04583941e294 3842 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
mbed_official 464:04583941e294 3843
mbed_official 464:04583941e294 3844 /****************** Bit definition for FMC_BCR2 register *******************/
mbed_official 464:04583941e294 3845 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 464:04583941e294 3846 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 464:04583941e294 3847
mbed_official 464:04583941e294 3848 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 464:04583941e294 3849 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 464:04583941e294 3850 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 464:04583941e294 3851
mbed_official 464:04583941e294 3852 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 464:04583941e294 3853 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 3854 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 3855
mbed_official 464:04583941e294 3856 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 464:04583941e294 3857 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 464:04583941e294 3858 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 464:04583941e294 3859 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 464:04583941e294 3860 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 464:04583941e294 3861 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 464:04583941e294 3862 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 464:04583941e294 3863 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 464:04583941e294 3864 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 464:04583941e294 3865 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 464:04583941e294 3866
mbed_official 464:04583941e294 3867 /****************** Bit definition for FMC_BCR3 register *******************/
mbed_official 464:04583941e294 3868 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 464:04583941e294 3869 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 464:04583941e294 3870
mbed_official 464:04583941e294 3871 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 464:04583941e294 3872 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 464:04583941e294 3873 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 464:04583941e294 3874
mbed_official 464:04583941e294 3875 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 464:04583941e294 3876 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 3877 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 3878
mbed_official 464:04583941e294 3879 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 464:04583941e294 3880 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 464:04583941e294 3881 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 464:04583941e294 3882 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 464:04583941e294 3883 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 464:04583941e294 3884 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 464:04583941e294 3885 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 464:04583941e294 3886 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 464:04583941e294 3887 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 464:04583941e294 3888 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 464:04583941e294 3889
mbed_official 464:04583941e294 3890 /****************** Bit definition for FMC_BCR4 register *******************/
mbed_official 464:04583941e294 3891 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
mbed_official 464:04583941e294 3892 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
mbed_official 464:04583941e294 3893
mbed_official 464:04583941e294 3894 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
mbed_official 464:04583941e294 3895 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 464:04583941e294 3896 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 464:04583941e294 3897
mbed_official 464:04583941e294 3898 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
mbed_official 464:04583941e294 3899 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 3900 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 3901
mbed_official 464:04583941e294 3902 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
mbed_official 464:04583941e294 3903 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
mbed_official 464:04583941e294 3904 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
mbed_official 464:04583941e294 3905 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
mbed_official 464:04583941e294 3906 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
mbed_official 464:04583941e294 3907 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
mbed_official 464:04583941e294 3908 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
mbed_official 464:04583941e294 3909 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
mbed_official 464:04583941e294 3910 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
mbed_official 464:04583941e294 3911 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
mbed_official 464:04583941e294 3912
mbed_official 464:04583941e294 3913 /****************** Bit definition for FMC_BTR1 register ******************/
mbed_official 464:04583941e294 3914 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 464:04583941e294 3915 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 3916 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 3917 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 3918 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 3919
mbed_official 464:04583941e294 3920 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 464:04583941e294 3921 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 3922 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 3923 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 3924 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 3925
mbed_official 464:04583941e294 3926 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 464:04583941e294 3927 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 3928 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 3929 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 3930 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 3931 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 3932 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 3933 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 3934 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 3935
mbed_official 464:04583941e294 3936 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 464:04583941e294 3937 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 3938 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 3939 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 3940 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 3941
mbed_official 464:04583941e294 3942 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 464:04583941e294 3943 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 3944 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 3945 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 3946 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 3947
mbed_official 464:04583941e294 3948 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 464:04583941e294 3949 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 3950 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 3951 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 3952 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 3953
mbed_official 464:04583941e294 3954 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 464:04583941e294 3955 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 464:04583941e294 3956 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 464:04583941e294 3957
mbed_official 464:04583941e294 3958 /****************** Bit definition for FMC_BTR2 register *******************/
mbed_official 464:04583941e294 3959 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 464:04583941e294 3960 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 3961 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 3962 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 3963 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 3964
mbed_official 464:04583941e294 3965 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 464:04583941e294 3966 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 3967 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 3968 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 3969 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 3970
mbed_official 464:04583941e294 3971 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 464:04583941e294 3972 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 3973 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 3974 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 3975 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 3976 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 3977 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 3978 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 3979 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 3980
mbed_official 464:04583941e294 3981 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 464:04583941e294 3982 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 3983 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 3984 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 3985 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 3986
mbed_official 464:04583941e294 3987 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 464:04583941e294 3988 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 3989 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 3990 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 3991 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 3992
mbed_official 464:04583941e294 3993 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 464:04583941e294 3994 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 3995 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 3996 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 3997 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 3998
mbed_official 464:04583941e294 3999 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 464:04583941e294 4000 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4001 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4002
mbed_official 464:04583941e294 4003 /******************* Bit definition for FMC_BTR3 register *******************/
mbed_official 464:04583941e294 4004 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 464:04583941e294 4005 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4006 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4007 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4008 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4009
mbed_official 464:04583941e294 4010 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 464:04583941e294 4011 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4012 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4013 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 4014 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 4015
mbed_official 464:04583941e294 4016 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 464:04583941e294 4017 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4018 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4019 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4020 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4021 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4022 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4023 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4024 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4025
mbed_official 464:04583941e294 4026 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 464:04583941e294 4027 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4028 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4029 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4030 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 4031
mbed_official 464:04583941e294 4032 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 464:04583941e294 4033 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 4034 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 4035 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 4036 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 4037
mbed_official 464:04583941e294 4038 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 464:04583941e294 4039 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4040 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4041 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4042 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4043
mbed_official 464:04583941e294 4044 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 464:04583941e294 4045 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4046 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4047
mbed_official 464:04583941e294 4048 /****************** Bit definition for FMC_BTR4 register *******************/
mbed_official 464:04583941e294 4049 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 464:04583941e294 4050 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4051 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4052 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4053 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4054
mbed_official 464:04583941e294 4055 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 464:04583941e294 4056 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4057 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4058 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 4059 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 4060
mbed_official 464:04583941e294 4061 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 464:04583941e294 4062 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4063 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4064 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4065 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4066 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4067 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4068 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4069 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4070
mbed_official 464:04583941e294 4071 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
mbed_official 464:04583941e294 4072 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4073 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4074 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4075 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 4076
mbed_official 464:04583941e294 4077 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 464:04583941e294 4078 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 4079 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 4080 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 4081 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 4082
mbed_official 464:04583941e294 4083 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 464:04583941e294 4084 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4085 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4086 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4087 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4088
mbed_official 464:04583941e294 4089 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 464:04583941e294 4090 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4091 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4092
mbed_official 464:04583941e294 4093 /****************** Bit definition for FMC_BWTR1 register ******************/
mbed_official 464:04583941e294 4094 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 464:04583941e294 4095 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4096 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4097 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4098 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4099
mbed_official 464:04583941e294 4100 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 464:04583941e294 4101 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4102 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4103 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 4104 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 4105
mbed_official 464:04583941e294 4106 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 464:04583941e294 4107 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4108 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4109 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4110 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4111 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4112 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4113 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4114 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4115
mbed_official 464:04583941e294 4116 #define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 464:04583941e294 4117 #define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 4118 #define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 4119 #define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 4120 #define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 4121
mbed_official 464:04583941e294 4122 #define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 464:04583941e294 4123 #define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4124 #define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4125 #define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4126 #define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4127
mbed_official 464:04583941e294 4128 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 464:04583941e294 4129 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4130 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4131
mbed_official 464:04583941e294 4132 /****************** Bit definition for FMC_BWTR2 register ******************/
mbed_official 464:04583941e294 4133 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 464:04583941e294 4134 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4135 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4136 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4137 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4138
mbed_official 464:04583941e294 4139 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 464:04583941e294 4140 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4141 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4142 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 4143 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 4144
mbed_official 464:04583941e294 4145 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 464:04583941e294 4146 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4147 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4148 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4149 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4150 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4151 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4152 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4153 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4154
mbed_official 464:04583941e294 4155 #define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 464:04583941e294 4156 #define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 4157 #define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/
mbed_official 464:04583941e294 4158 #define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 4159 #define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 4160
mbed_official 464:04583941e294 4161 #define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 464:04583941e294 4162 #define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4163 #define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4164 #define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4165 #define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4166
mbed_official 464:04583941e294 4167 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 464:04583941e294 4168 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4169 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4170
mbed_official 464:04583941e294 4171 /****************** Bit definition for FMC_BWTR3 register ******************/
mbed_official 464:04583941e294 4172 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 464:04583941e294 4173 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4174 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4175 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4176 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4177
mbed_official 464:04583941e294 4178 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 464:04583941e294 4179 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4180 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4181 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 4182 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 4183
mbed_official 464:04583941e294 4184 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 464:04583941e294 4185 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4186 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4187 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4188 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4189 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4190 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4191 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4192 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4193
mbed_official 464:04583941e294 4194 #define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 464:04583941e294 4195 #define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 4196 #define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 4197 #define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 4198 #define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 4199
mbed_official 464:04583941e294 4200 #define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 464:04583941e294 4201 #define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4202 #define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4203 #define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4204 #define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4205
mbed_official 464:04583941e294 4206 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 464:04583941e294 4207 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4208 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4209
mbed_official 464:04583941e294 4210 /****************** Bit definition for FMC_BWTR4 register ******************/
mbed_official 464:04583941e294 4211 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
mbed_official 464:04583941e294 4212 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4213 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4214 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4215 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4216
mbed_official 464:04583941e294 4217 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
mbed_official 464:04583941e294 4218 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4219 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4220 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 4221 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 4222
mbed_official 464:04583941e294 4223 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
mbed_official 464:04583941e294 4224 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4225 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4226 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4227 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4228 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4229 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4230 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4231 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4232
mbed_official 464:04583941e294 4233 #define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
mbed_official 464:04583941e294 4234 #define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 4235 #define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 4236 #define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 4237 #define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
mbed_official 464:04583941e294 4238
mbed_official 464:04583941e294 4239 #define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
mbed_official 464:04583941e294 4240 #define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4241 #define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4242 #define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4243 #define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4244
mbed_official 464:04583941e294 4245 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
mbed_official 464:04583941e294 4246 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4247 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4248
mbed_official 464:04583941e294 4249 /****************** Bit definition for FMC_PCR2 register *******************/
mbed_official 464:04583941e294 4250 #define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 464:04583941e294 4251 #define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 464:04583941e294 4252 #define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 464:04583941e294 4253
mbed_official 464:04583941e294 4254 #define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 464:04583941e294 4255 #define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4256 #define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4257
mbed_official 464:04583941e294 4258 #define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 464:04583941e294 4259
mbed_official 464:04583941e294 4260 #define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 464:04583941e294 4261 #define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 464:04583941e294 4262 #define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 464:04583941e294 4263 #define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 464:04583941e294 4264 #define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 464:04583941e294 4265
mbed_official 464:04583941e294 4266 #define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 464:04583941e294 4267 #define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 464:04583941e294 4268 #define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 464:04583941e294 4269 #define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 464:04583941e294 4270 #define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 464:04583941e294 4271
mbed_official 464:04583941e294 4272 #define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */
mbed_official 464:04583941e294 4273 #define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 464:04583941e294 4274 #define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 464:04583941e294 4275 #define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 464:04583941e294 4276
mbed_official 464:04583941e294 4277 /****************** Bit definition for FMC_PCR3 register *******************/
mbed_official 464:04583941e294 4278 #define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 464:04583941e294 4279 #define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 464:04583941e294 4280 #define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 464:04583941e294 4281
mbed_official 464:04583941e294 4282 #define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 464:04583941e294 4283 #define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4284 #define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4285
mbed_official 464:04583941e294 4286 #define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 464:04583941e294 4287
mbed_official 464:04583941e294 4288 #define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 464:04583941e294 4289 #define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 464:04583941e294 4290 #define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 464:04583941e294 4291 #define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 464:04583941e294 4292 #define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 464:04583941e294 4293
mbed_official 464:04583941e294 4294 #define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 464:04583941e294 4295 #define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 464:04583941e294 4296 #define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 464:04583941e294 4297 #define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 464:04583941e294 4298 #define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 464:04583941e294 4299
mbed_official 464:04583941e294 4300 #define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
mbed_official 464:04583941e294 4301 #define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 464:04583941e294 4302 #define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 464:04583941e294 4303 #define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 464:04583941e294 4304
mbed_official 464:04583941e294 4305 /****************** Bit definition for FMC_PCR4 register *******************/
mbed_official 464:04583941e294 4306 #define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
mbed_official 464:04583941e294 4307 #define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
mbed_official 464:04583941e294 4308 #define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */
mbed_official 464:04583941e294 4309
mbed_official 464:04583941e294 4310 #define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
mbed_official 464:04583941e294 4311 #define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4312 #define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4313
mbed_official 464:04583941e294 4314 #define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
mbed_official 464:04583941e294 4315
mbed_official 464:04583941e294 4316 #define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
mbed_official 464:04583941e294 4317 #define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 464:04583941e294 4318 #define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 464:04583941e294 4319 #define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
mbed_official 464:04583941e294 4320 #define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
mbed_official 464:04583941e294 4321
mbed_official 464:04583941e294 4322 #define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
mbed_official 464:04583941e294 4323 #define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 464:04583941e294 4324 #define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 464:04583941e294 4325 #define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 464:04583941e294 4326 #define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 464:04583941e294 4327
mbed_official 464:04583941e294 4328 #define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
mbed_official 464:04583941e294 4329 #define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 464:04583941e294 4330 #define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 464:04583941e294 4331 #define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 464:04583941e294 4332
mbed_official 464:04583941e294 4333 /******************* Bit definition for FMC_SR2 register *******************/
mbed_official 464:04583941e294 4334 #define FMC_SR2_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 464:04583941e294 4335 #define FMC_SR2_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 464:04583941e294 4336 #define FMC_SR2_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 464:04583941e294 4337 #define FMC_SR2_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 464:04583941e294 4338 #define FMC_SR2_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 464:04583941e294 4339 #define FMC_SR2_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 464:04583941e294 4340 #define FMC_SR2_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 464:04583941e294 4341
mbed_official 464:04583941e294 4342 /******************* Bit definition for FMC_SR3 register *******************/
mbed_official 464:04583941e294 4343 #define FMC_SR3_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 464:04583941e294 4344 #define FMC_SR3_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 464:04583941e294 4345 #define FMC_SR3_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 464:04583941e294 4346 #define FMC_SR3_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 464:04583941e294 4347 #define FMC_SR3_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 464:04583941e294 4348 #define FMC_SR3_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 464:04583941e294 4349 #define FMC_SR3_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 464:04583941e294 4350
mbed_official 464:04583941e294 4351 /******************* Bit definition for FMC_SR4 register *******************/
mbed_official 464:04583941e294 4352 #define FMC_SR4_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
mbed_official 464:04583941e294 4353 #define FMC_SR4_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
mbed_official 464:04583941e294 4354 #define FMC_SR4_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
mbed_official 464:04583941e294 4355 #define FMC_SR4_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
mbed_official 464:04583941e294 4356 #define FMC_SR4_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
mbed_official 464:04583941e294 4357 #define FMC_SR4_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
mbed_official 464:04583941e294 4358 #define FMC_SR4_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
mbed_official 464:04583941e294 4359
mbed_official 464:04583941e294 4360 /****************** Bit definition for FMC_PMEM2 register ******************/
mbed_official 464:04583941e294 4361 #define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
mbed_official 464:04583941e294 4362 #define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4363 #define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4364 #define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4365 #define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4366 #define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 4367 #define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 4368 #define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 464:04583941e294 4369 #define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 464:04583941e294 4370
mbed_official 464:04583941e294 4371 #define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
mbed_official 464:04583941e294 4372 #define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4373 #define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4374 #define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4375 #define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4376 #define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4377 #define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4378 #define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4379 #define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4380
mbed_official 464:04583941e294 4381 #define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
mbed_official 464:04583941e294 4382 #define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4383 #define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4384 #define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4385 #define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 4386 #define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 464:04583941e294 4387 #define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 464:04583941e294 4388 #define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 464:04583941e294 4389 #define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 464:04583941e294 4390
mbed_official 464:04583941e294 4391 #define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
mbed_official 464:04583941e294 4392 #define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4393 #define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4394 #define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4395 #define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4396 #define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 464:04583941e294 4397 #define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 464:04583941e294 4398 #define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 464:04583941e294 4399 #define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 464:04583941e294 4400
mbed_official 464:04583941e294 4401 /****************** Bit definition for FMC_PMEM3 register ******************/
mbed_official 464:04583941e294 4402 #define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
mbed_official 464:04583941e294 4403 #define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4404 #define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4405 #define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4406 #define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4407 #define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 4408 #define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 4409 #define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 464:04583941e294 4410 #define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 464:04583941e294 4411
mbed_official 464:04583941e294 4412 #define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
mbed_official 464:04583941e294 4413 #define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4414 #define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4415 #define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4416 #define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4417 #define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4418 #define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4419 #define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4420 #define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4421
mbed_official 464:04583941e294 4422 #define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
mbed_official 464:04583941e294 4423 #define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4424 #define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4425 #define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4426 #define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 4427 #define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 464:04583941e294 4428 #define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 464:04583941e294 4429 #define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 464:04583941e294 4430 #define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 464:04583941e294 4431
mbed_official 464:04583941e294 4432 #define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
mbed_official 464:04583941e294 4433 #define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4434 #define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4435 #define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4436 #define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4437 #define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 464:04583941e294 4438 #define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 464:04583941e294 4439 #define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 464:04583941e294 4440 #define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 464:04583941e294 4441
mbed_official 464:04583941e294 4442 /****************** Bit definition for FMC_PMEM4 register ******************/
mbed_official 464:04583941e294 4443 #define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
mbed_official 464:04583941e294 4444 #define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4445 #define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4446 #define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4447 #define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4448 #define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 4449 #define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 4450 #define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 464:04583941e294 4451 #define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 464:04583941e294 4452
mbed_official 464:04583941e294 4453 #define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
mbed_official 464:04583941e294 4454 #define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4455 #define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4456 #define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4457 #define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4458 #define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4459 #define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4460 #define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4461 #define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4462
mbed_official 464:04583941e294 4463 #define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
mbed_official 464:04583941e294 4464 #define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4465 #define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4466 #define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4467 #define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 4468 #define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 464:04583941e294 4469 #define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 464:04583941e294 4470 #define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 464:04583941e294 4471 #define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 464:04583941e294 4472
mbed_official 464:04583941e294 4473 #define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
mbed_official 464:04583941e294 4474 #define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4475 #define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4476 #define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4477 #define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4478 #define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 464:04583941e294 4479 #define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 464:04583941e294 4480 #define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 464:04583941e294 4481 #define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 464:04583941e294 4482
mbed_official 464:04583941e294 4483 /****************** Bit definition for FMC_PATT2 register ******************/
mbed_official 464:04583941e294 4484 #define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
mbed_official 464:04583941e294 4485 #define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4486 #define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4487 #define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4488 #define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4489 #define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 4490 #define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 4491 #define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 464:04583941e294 4492 #define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 464:04583941e294 4493
mbed_official 464:04583941e294 4494 #define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
mbed_official 464:04583941e294 4495 #define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4496 #define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4497 #define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4498 #define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4499 #define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4500 #define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4501 #define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4502 #define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4503
mbed_official 464:04583941e294 4504 #define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
mbed_official 464:04583941e294 4505 #define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4506 #define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4507 #define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4508 #define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 4509 #define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 464:04583941e294 4510 #define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 464:04583941e294 4511 #define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 464:04583941e294 4512 #define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 464:04583941e294 4513
mbed_official 464:04583941e294 4514 #define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
mbed_official 464:04583941e294 4515 #define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4516 #define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4517 #define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4518 #define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4519 #define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 464:04583941e294 4520 #define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 464:04583941e294 4521 #define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 464:04583941e294 4522 #define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 464:04583941e294 4523
mbed_official 464:04583941e294 4524 /****************** Bit definition for FMC_PATT3 register ******************/
mbed_official 464:04583941e294 4525 #define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
mbed_official 464:04583941e294 4526 #define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4527 #define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4528 #define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4529 #define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4530 #define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 4531 #define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 4532 #define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 464:04583941e294 4533 #define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 464:04583941e294 4534
mbed_official 464:04583941e294 4535 #define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
mbed_official 464:04583941e294 4536 #define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4537 #define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4538 #define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4539 #define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4540 #define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4541 #define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4542 #define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4543 #define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4544
mbed_official 464:04583941e294 4545 #define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
mbed_official 464:04583941e294 4546 #define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4547 #define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4548 #define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4549 #define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 4550 #define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 464:04583941e294 4551 #define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 464:04583941e294 4552 #define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 464:04583941e294 4553 #define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 464:04583941e294 4554
mbed_official 464:04583941e294 4555 #define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
mbed_official 464:04583941e294 4556 #define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4557 #define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4558 #define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4559 #define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4560 #define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 464:04583941e294 4561 #define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 464:04583941e294 4562 #define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 464:04583941e294 4563 #define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 464:04583941e294 4564
mbed_official 464:04583941e294 4565 /****************** Bit definition for FMC_PATT4 register ******************/
mbed_official 464:04583941e294 4566 #define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
mbed_official 464:04583941e294 4567 #define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4568 #define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4569 #define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4570 #define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4571 #define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 4572 #define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 4573 #define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 464:04583941e294 4574 #define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 464:04583941e294 4575
mbed_official 464:04583941e294 4576 #define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
mbed_official 464:04583941e294 4577 #define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4578 #define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4579 #define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4580 #define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4581 #define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4582 #define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4583 #define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4584 #define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4585
mbed_official 464:04583941e294 4586 #define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
mbed_official 464:04583941e294 4587 #define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4588 #define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4589 #define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4590 #define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 4591 #define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 464:04583941e294 4592 #define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 464:04583941e294 4593 #define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 464:04583941e294 4594 #define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 464:04583941e294 4595
mbed_official 464:04583941e294 4596 #define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
mbed_official 464:04583941e294 4597 #define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4598 #define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4599 #define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4600 #define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4601 #define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 464:04583941e294 4602 #define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 464:04583941e294 4603 #define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 464:04583941e294 4604 #define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 464:04583941e294 4605
mbed_official 464:04583941e294 4606 /****************** Bit definition for FMC_PIO4 register *******************/
mbed_official 464:04583941e294 4607 #define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */
mbed_official 464:04583941e294 4608 #define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4609 #define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4610 #define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4611 #define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4612 #define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 4613 #define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 4614 #define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 464:04583941e294 4615 #define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 464:04583941e294 4616
mbed_official 464:04583941e294 4617 #define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
mbed_official 464:04583941e294 4618 #define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4619 #define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4620 #define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4621 #define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4622 #define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 4623 #define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 4624 #define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 4625 #define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 464:04583941e294 4626
mbed_official 464:04583941e294 4627 #define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
mbed_official 464:04583941e294 4628 #define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4629 #define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4630 #define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4631 #define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 4632 #define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 464:04583941e294 4633 #define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 464:04583941e294 4634 #define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 464:04583941e294 4635 #define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 464:04583941e294 4636
mbed_official 464:04583941e294 4637 #define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
mbed_official 464:04583941e294 4638 #define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4639 #define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4640 #define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4641 #define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 4642 #define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 464:04583941e294 4643 #define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 464:04583941e294 4644 #define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 464:04583941e294 4645 #define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 464:04583941e294 4646
mbed_official 464:04583941e294 4647 /****************** Bit definition for FMC_ECCR2 register ******************/
mbed_official 464:04583941e294 4648 #define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
mbed_official 464:04583941e294 4649
mbed_official 464:04583941e294 4650 /****************** Bit definition for FMC_ECCR3 register ******************/
mbed_official 464:04583941e294 4651 #define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
mbed_official 464:04583941e294 4652
mbed_official 464:04583941e294 4653 /****************** Bit definition for FMC_SDCR1 register ******************/
mbed_official 464:04583941e294 4654 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
mbed_official 464:04583941e294 4655 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4656 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4657
mbed_official 464:04583941e294 4658 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 464:04583941e294 4659 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 464:04583941e294 4660 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 464:04583941e294 4661
mbed_official 464:04583941e294 4662 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 464:04583941e294 4663 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4664 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4665
mbed_official 464:04583941e294 4666 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
mbed_official 464:04583941e294 4667
mbed_official 464:04583941e294 4668 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
mbed_official 464:04583941e294 4669 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 464:04583941e294 4670 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 464:04583941e294 4671
mbed_official 464:04583941e294 4672 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
mbed_official 464:04583941e294 4673
mbed_official 464:04583941e294 4674 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
mbed_official 464:04583941e294 4675 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 464:04583941e294 4676 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 464:04583941e294 4677
mbed_official 464:04583941e294 4678 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
mbed_official 464:04583941e294 4679
mbed_official 464:04583941e294 4680 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
mbed_official 464:04583941e294 4681 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 464:04583941e294 4682 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 464:04583941e294 4683
mbed_official 464:04583941e294 4684 /****************** Bit definition for FMC_SDCR2 register ******************/
mbed_official 464:04583941e294 4685 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
mbed_official 464:04583941e294 4686 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4687 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4688
mbed_official 464:04583941e294 4689 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 464:04583941e294 4690 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 464:04583941e294 4691 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 464:04583941e294 4692
mbed_official 464:04583941e294 4693 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
mbed_official 464:04583941e294 4694 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4695 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4696
mbed_official 464:04583941e294 4697 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
mbed_official 464:04583941e294 4698
mbed_official 464:04583941e294 4699 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
mbed_official 464:04583941e294 4700 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 464:04583941e294 4701 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 464:04583941e294 4702
mbed_official 464:04583941e294 4703 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
mbed_official 464:04583941e294 4704
mbed_official 464:04583941e294 4705 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
mbed_official 464:04583941e294 4706 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 464:04583941e294 4707 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 464:04583941e294 4708
mbed_official 464:04583941e294 4709 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
mbed_official 464:04583941e294 4710
mbed_official 464:04583941e294 4711 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
mbed_official 464:04583941e294 4712 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 464:04583941e294 4713 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 464:04583941e294 4714
mbed_official 464:04583941e294 4715 /****************** Bit definition for FMC_SDTR1 register ******************/
mbed_official 464:04583941e294 4716 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
mbed_official 464:04583941e294 4717 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4718 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4719 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4720 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4721
mbed_official 464:04583941e294 4722 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
mbed_official 464:04583941e294 4723 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4724 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4725 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 4726 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 4727
mbed_official 464:04583941e294 4728 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
mbed_official 464:04583941e294 4729 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4730 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4731 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4732 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4733
mbed_official 464:04583941e294 4734 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
mbed_official 464:04583941e294 4735 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 464:04583941e294 4736 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 464:04583941e294 4737 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 464:04583941e294 4738
mbed_official 464:04583941e294 4739 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
mbed_official 464:04583941e294 4740 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4741 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4742 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4743
mbed_official 464:04583941e294 4744 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
mbed_official 464:04583941e294 4745 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 4746 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 4747 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 4748
mbed_official 464:04583941e294 4749 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
mbed_official 464:04583941e294 4750 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4751 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4752 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4753
mbed_official 464:04583941e294 4754 /****************** Bit definition for FMC_SDTR2 register ******************/
mbed_official 464:04583941e294 4755 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
mbed_official 464:04583941e294 4756 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4757 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4758 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 4759 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 4760
mbed_official 464:04583941e294 4761 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
mbed_official 464:04583941e294 4762 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 4763 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 4764 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 4765 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 4766
mbed_official 464:04583941e294 4767 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
mbed_official 464:04583941e294 4768 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 4769 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 4770 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 4771 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 4772
mbed_official 464:04583941e294 4773 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
mbed_official 464:04583941e294 4774 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 464:04583941e294 4775 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 464:04583941e294 4776 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 464:04583941e294 4777
mbed_official 464:04583941e294 4778 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
mbed_official 464:04583941e294 4779 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 4780 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 4781 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 4782
mbed_official 464:04583941e294 4783 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
mbed_official 464:04583941e294 4784 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 4785 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 4786 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 464:04583941e294 4787
mbed_official 464:04583941e294 4788 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
mbed_official 464:04583941e294 4789 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 4790 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 4791 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 4792
mbed_official 464:04583941e294 4793 /****************** Bit definition for FMC_SDCMR register ******************/
mbed_official 464:04583941e294 4794 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
mbed_official 464:04583941e294 4795 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 4796 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 4797 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
mbed_official 464:04583941e294 4798
mbed_official 464:04583941e294 4799 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
mbed_official 464:04583941e294 4800
mbed_official 464:04583941e294 4801 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
mbed_official 464:04583941e294 4802
mbed_official 464:04583941e294 4803 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
mbed_official 464:04583941e294 4804 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 464:04583941e294 4805 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 464:04583941e294 4806 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 464:04583941e294 4807 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
mbed_official 464:04583941e294 4808
mbed_official 464:04583941e294 4809 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
mbed_official 464:04583941e294 4810
mbed_official 464:04583941e294 4811 /****************** Bit definition for FMC_SDRTR register ******************/
mbed_official 464:04583941e294 4812 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
mbed_official 464:04583941e294 4813
mbed_official 464:04583941e294 4814 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
mbed_official 464:04583941e294 4815
mbed_official 464:04583941e294 4816 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
mbed_official 464:04583941e294 4817
mbed_official 464:04583941e294 4818 /****************** Bit definition for FMC_SDSR register ******************/
mbed_official 464:04583941e294 4819 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
mbed_official 464:04583941e294 4820
mbed_official 464:04583941e294 4821 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
mbed_official 464:04583941e294 4822 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 464:04583941e294 4823 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 464:04583941e294 4824
mbed_official 464:04583941e294 4825 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
mbed_official 464:04583941e294 4826 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 464:04583941e294 4827 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 464:04583941e294 4828 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
mbed_official 464:04583941e294 4829
mbed_official 464:04583941e294 4830
mbed_official 464:04583941e294 4831
mbed_official 464:04583941e294 4832 /******************************************************************************/
mbed_official 464:04583941e294 4833 /* */
mbed_official 464:04583941e294 4834 /* General Purpose I/O */
mbed_official 464:04583941e294 4835 /* */
mbed_official 464:04583941e294 4836 /******************************************************************************/
mbed_official 464:04583941e294 4837 /****************** Bits definition for GPIO_MODER register *****************/
mbed_official 464:04583941e294 4838 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 464:04583941e294 4839 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 4840 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 4841
mbed_official 464:04583941e294 4842 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 464:04583941e294 4843 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 4844 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 4845
mbed_official 464:04583941e294 4846 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 464:04583941e294 4847 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 4848 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 4849
mbed_official 464:04583941e294 4850 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 464:04583941e294 4851 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 4852 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 4853
mbed_official 464:04583941e294 4854 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 464:04583941e294 4855 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 4856 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 4857
mbed_official 464:04583941e294 4858 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 464:04583941e294 4859 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 4860 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 4861
mbed_official 464:04583941e294 4862 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 464:04583941e294 4863 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 4864 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 4865
mbed_official 464:04583941e294 4866 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 464:04583941e294 4867 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 4868 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 4869
mbed_official 464:04583941e294 4870 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 464:04583941e294 4871 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 4872 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 4873
mbed_official 464:04583941e294 4874 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 464:04583941e294 4875 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 4876 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 4877
mbed_official 464:04583941e294 4878 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 464:04583941e294 4879 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 4880 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 4881
mbed_official 464:04583941e294 4882 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 464:04583941e294 4883 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 4884 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 464:04583941e294 4885
mbed_official 464:04583941e294 4886 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 464:04583941e294 4887 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 4888 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 4889
mbed_official 464:04583941e294 4890 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 464:04583941e294 4891 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 4892 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 4893
mbed_official 464:04583941e294 4894 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 464:04583941e294 4895 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 464:04583941e294 4896 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 464:04583941e294 4897
mbed_official 464:04583941e294 4898 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 464:04583941e294 4899 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 464:04583941e294 4900 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 464:04583941e294 4901
mbed_official 464:04583941e294 4902 /****************** Bits definition for GPIO_OTYPER register ****************/
mbed_official 464:04583941e294 4903 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 4904 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 4905 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 4906 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 4907 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 4908 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 4909 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 4910 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 4911 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 4912 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 4913 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 4914 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 4915 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 4916 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 4917 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 4918 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 4919
mbed_official 464:04583941e294 4920 /****************** Bits definition for GPIO_OSPEEDR register ***************/
mbed_official 464:04583941e294 4921 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 464:04583941e294 4922 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 4923 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 4924
mbed_official 464:04583941e294 4925 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 464:04583941e294 4926 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 4927 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 4928
mbed_official 464:04583941e294 4929 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 464:04583941e294 4930 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 4931 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 4932
mbed_official 464:04583941e294 4933 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 464:04583941e294 4934 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 4935 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 4936
mbed_official 464:04583941e294 4937 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 464:04583941e294 4938 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 4939 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 4940
mbed_official 464:04583941e294 4941 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 464:04583941e294 4942 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 4943 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 4944
mbed_official 464:04583941e294 4945 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 464:04583941e294 4946 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 4947 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 4948
mbed_official 464:04583941e294 4949 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 464:04583941e294 4950 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 4951 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 4952
mbed_official 464:04583941e294 4953 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 464:04583941e294 4954 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 4955 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 4956
mbed_official 464:04583941e294 4957 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 464:04583941e294 4958 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 4959 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 4960
mbed_official 464:04583941e294 4961 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 464:04583941e294 4962 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 4963 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 4964
mbed_official 464:04583941e294 4965 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 464:04583941e294 4966 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 4967 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 464:04583941e294 4968
mbed_official 464:04583941e294 4969 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 464:04583941e294 4970 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 4971 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 4972
mbed_official 464:04583941e294 4973 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 464:04583941e294 4974 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 4975 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 4976
mbed_official 464:04583941e294 4977 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 464:04583941e294 4978 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 464:04583941e294 4979 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 464:04583941e294 4980
mbed_official 464:04583941e294 4981 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 464:04583941e294 4982 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 464:04583941e294 4983 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 464:04583941e294 4984
mbed_official 464:04583941e294 4985 /****************** Bits definition for GPIO_PUPDR register *****************/
mbed_official 464:04583941e294 4986 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 464:04583941e294 4987 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 4988 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 4989
mbed_official 464:04583941e294 4990 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 464:04583941e294 4991 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 4992 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 4993
mbed_official 464:04583941e294 4994 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 464:04583941e294 4995 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 4996 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 4997
mbed_official 464:04583941e294 4998 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 464:04583941e294 4999 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5000 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5001
mbed_official 464:04583941e294 5002 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 464:04583941e294 5003 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5004 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5005
mbed_official 464:04583941e294 5006 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 464:04583941e294 5007 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5008 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5009
mbed_official 464:04583941e294 5010 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 464:04583941e294 5011 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5012 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5013
mbed_official 464:04583941e294 5014 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 464:04583941e294 5015 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5016 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 5017
mbed_official 464:04583941e294 5018 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 464:04583941e294 5019 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5020 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5021
mbed_official 464:04583941e294 5022 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 464:04583941e294 5023 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5024 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 5025
mbed_official 464:04583941e294 5026 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 464:04583941e294 5027 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5028 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5029
mbed_official 464:04583941e294 5030 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 464:04583941e294 5031 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5032 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 464:04583941e294 5033
mbed_official 464:04583941e294 5034 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 464:04583941e294 5035 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 5036 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5037
mbed_official 464:04583941e294 5038 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 464:04583941e294 5039 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5040 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 5041
mbed_official 464:04583941e294 5042 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 464:04583941e294 5043 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 464:04583941e294 5044 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 464:04583941e294 5045
mbed_official 464:04583941e294 5046 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 464:04583941e294 5047 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 464:04583941e294 5048 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 464:04583941e294 5049
mbed_official 464:04583941e294 5050 /****************** Bits definition for GPIO_IDR register *******************/
mbed_official 464:04583941e294 5051 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5052 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5053 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5054 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5055 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5056 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5057 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5058 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5059 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5060 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5061 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5062 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5063 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5064 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5065 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5066 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 5067 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
mbed_official 464:04583941e294 5068 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
mbed_official 464:04583941e294 5069 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
mbed_official 464:04583941e294 5070 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
mbed_official 464:04583941e294 5071 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
mbed_official 464:04583941e294 5072 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
mbed_official 464:04583941e294 5073 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
mbed_official 464:04583941e294 5074 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
mbed_official 464:04583941e294 5075 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
mbed_official 464:04583941e294 5076 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
mbed_official 464:04583941e294 5077 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
mbed_official 464:04583941e294 5078 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
mbed_official 464:04583941e294 5079 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
mbed_official 464:04583941e294 5080 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
mbed_official 464:04583941e294 5081 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
mbed_official 464:04583941e294 5082 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
mbed_official 464:04583941e294 5083 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
mbed_official 464:04583941e294 5084
mbed_official 464:04583941e294 5085 /****************** Bits definition for GPIO_ODR register *******************/
mbed_official 464:04583941e294 5086 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5087 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5088 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5089 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5090 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5091 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5092 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5093 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5094 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5095 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5096 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5097 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5098 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5099 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5100 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5101 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 5102 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
mbed_official 464:04583941e294 5103 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
mbed_official 464:04583941e294 5104 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
mbed_official 464:04583941e294 5105 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
mbed_official 464:04583941e294 5106 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
mbed_official 464:04583941e294 5107 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
mbed_official 464:04583941e294 5108 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
mbed_official 464:04583941e294 5109 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
mbed_official 464:04583941e294 5110 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
mbed_official 464:04583941e294 5111 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
mbed_official 464:04583941e294 5112 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
mbed_official 464:04583941e294 5113 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
mbed_official 464:04583941e294 5114 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
mbed_official 464:04583941e294 5115 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
mbed_official 464:04583941e294 5116 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
mbed_official 464:04583941e294 5117 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
mbed_official 464:04583941e294 5118 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
mbed_official 464:04583941e294 5119
mbed_official 464:04583941e294 5120 /****************** Bits definition for GPIO_BSRR register ******************/
mbed_official 464:04583941e294 5121 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5122 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5123 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5124 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5125 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5126 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5127 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5128 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5129 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5130 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5131 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5132 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5133 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5134 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5135 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5136 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 5137 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5138 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5139 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5140 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 5141 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5142 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5143 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5144 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 464:04583941e294 5145 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 5146 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5147 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5148 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 5149 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 464:04583941e294 5150 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 464:04583941e294 5151 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 464:04583941e294 5152 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 464:04583941e294 5153
mbed_official 464:04583941e294 5154 /****************** Bit definition for GPIO_LCKR register *********************/
mbed_official 464:04583941e294 5155 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5156 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5157 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5158 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5159 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5160 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5161 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5162 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5163 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5164 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5165 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5166 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5167 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5168 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5169 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5170 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 5171 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5172
mbed_official 464:04583941e294 5173 /******************************************************************************/
mbed_official 464:04583941e294 5174 /* */
mbed_official 464:04583941e294 5175 /* HASH */
mbed_official 464:04583941e294 5176 /* */
mbed_official 464:04583941e294 5177 /******************************************************************************/
mbed_official 464:04583941e294 5178 /****************** Bits definition for HASH_CR register ********************/
mbed_official 464:04583941e294 5179 #define HASH_CR_INIT ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5180 #define HASH_CR_DMAE ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5181 #define HASH_CR_DATATYPE ((uint32_t)0x00000030)
mbed_official 464:04583941e294 5182 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5183 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5184 #define HASH_CR_MODE ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5185 #define HASH_CR_ALGO ((uint32_t)0x00040080)
mbed_official 464:04583941e294 5186 #define HASH_CR_ALGO_0 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5187 #define HASH_CR_ALGO_1 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5188 #define HASH_CR_NBW ((uint32_t)0x00000F00)
mbed_official 464:04583941e294 5189 #define HASH_CR_NBW_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5190 #define HASH_CR_NBW_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5191 #define HASH_CR_NBW_2 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5192 #define HASH_CR_NBW_3 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5193 #define HASH_CR_DINNE ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5194 #define HASH_CR_MDMAT ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5195 #define HASH_CR_LKEY ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5196
mbed_official 464:04583941e294 5197 /****************** Bits definition for HASH_STR register *******************/
mbed_official 464:04583941e294 5198 #define HASH_STR_NBW ((uint32_t)0x0000001F)
mbed_official 464:04583941e294 5199 #define HASH_STR_NBW_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5200 #define HASH_STR_NBW_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5201 #define HASH_STR_NBW_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5202 #define HASH_STR_NBW_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5203 #define HASH_STR_NBW_4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5204 #define HASH_STR_DCAL ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5205
mbed_official 464:04583941e294 5206 /****************** Bits definition for HASH_IMR register *******************/
mbed_official 464:04583941e294 5207 #define HASH_IMR_DINIM ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5208 #define HASH_IMR_DCIM ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5209
mbed_official 464:04583941e294 5210 /****************** Bits definition for HASH_SR register ********************/
mbed_official 464:04583941e294 5211 #define HASH_SR_DINIS ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5212 #define HASH_SR_DCIS ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5213 #define HASH_SR_DMAS ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5214 #define HASH_SR_BUSY ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5215
mbed_official 464:04583941e294 5216 /******************************************************************************/
mbed_official 464:04583941e294 5217 /* */
mbed_official 464:04583941e294 5218 /* Inter-integrated Circuit Interface */
mbed_official 464:04583941e294 5219 /* */
mbed_official 464:04583941e294 5220 /******************************************************************************/
mbed_official 464:04583941e294 5221 /******************* Bit definition for I2C_CR1 register ********************/
mbed_official 464:04583941e294 5222 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!<Peripheral Enable */
mbed_official 464:04583941e294 5223 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!<SMBus Mode */
mbed_official 464:04583941e294 5224 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!<SMBus Type */
mbed_official 464:04583941e294 5225 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!<ARP Enable */
mbed_official 464:04583941e294 5226 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!<PEC Enable */
mbed_official 464:04583941e294 5227 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!<General Call Enable */
mbed_official 464:04583941e294 5228 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!<Clock Stretching Disable (Slave mode) */
mbed_official 464:04583941e294 5229 #define I2C_CR1_START ((uint32_t)0x00000100) /*!<Start Generation */
mbed_official 464:04583941e294 5230 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!<Stop Generation */
mbed_official 464:04583941e294 5231 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!<Acknowledge Enable */
mbed_official 464:04583941e294 5232 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!<Acknowledge/PEC Position (for data reception) */
mbed_official 464:04583941e294 5233 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!<Packet Error Checking */
mbed_official 464:04583941e294 5234 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!<SMBus Alert */
mbed_official 464:04583941e294 5235 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!<Software Reset */
mbed_official 464:04583941e294 5236
mbed_official 464:04583941e294 5237 /******************* Bit definition for I2C_CR2 register ********************/
mbed_official 464:04583941e294 5238 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
mbed_official 464:04583941e294 5239 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 5240 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 5241 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 5242 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 5243 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 5244 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 5245
mbed_official 464:04583941e294 5246 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!<Error Interrupt Enable */
mbed_official 464:04583941e294 5247 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!<Event Interrupt Enable */
mbed_official 464:04583941e294 5248 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!<Buffer Interrupt Enable */
mbed_official 464:04583941e294 5249 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!<DMA Requests Enable */
mbed_official 464:04583941e294 5250 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!<DMA Last Transfer */
mbed_official 464:04583941e294 5251
mbed_official 464:04583941e294 5252 /******************* Bit definition for I2C_OAR1 register *******************/
mbed_official 464:04583941e294 5253 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!<Interface Address */
mbed_official 464:04583941e294 5254 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!<Interface Address */
mbed_official 464:04583941e294 5255
mbed_official 464:04583941e294 5256 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 5257 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 5258 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 5259 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 5260 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 5261 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 5262 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 464:04583941e294 5263 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 464:04583941e294 5264 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!<Bit 8 */
mbed_official 464:04583941e294 5265 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!<Bit 9 */
mbed_official 464:04583941e294 5266
mbed_official 464:04583941e294 5267 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!<Addressing Mode (Slave mode) */
mbed_official 464:04583941e294 5268
mbed_official 464:04583941e294 5269 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 464:04583941e294 5270 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!<Dual addressing mode enable */
mbed_official 464:04583941e294 5271 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!<Interface address */
mbed_official 464:04583941e294 5272
mbed_official 464:04583941e294 5273 /******************** Bit definition for I2C_DR register ********************/
mbed_official 464:04583941e294 5274 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!<8-bit Data Register */
mbed_official 464:04583941e294 5275
mbed_official 464:04583941e294 5276 /******************* Bit definition for I2C_SR1 register ********************/
mbed_official 464:04583941e294 5277 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!<Start Bit (Master mode) */
mbed_official 464:04583941e294 5278 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!<Address sent (master mode)/matched (slave mode) */
mbed_official 464:04583941e294 5279 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!<Byte Transfer Finished */
mbed_official 464:04583941e294 5280 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!<10-bit header sent (Master mode) */
mbed_official 464:04583941e294 5281 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!<Stop detection (Slave mode) */
mbed_official 464:04583941e294 5282 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!<Data Register not Empty (receivers) */
mbed_official 464:04583941e294 5283 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!<Data Register Empty (transmitters) */
mbed_official 464:04583941e294 5284 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!<Bus Error */
mbed_official 464:04583941e294 5285 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!<Arbitration Lost (master mode) */
mbed_official 464:04583941e294 5286 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!<Acknowledge Failure */
mbed_official 464:04583941e294 5287 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!<Overrun/Underrun */
mbed_official 464:04583941e294 5288 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!<PEC Error in reception */
mbed_official 464:04583941e294 5289 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!<Timeout or Tlow Error */
mbed_official 464:04583941e294 5290 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!<SMBus Alert */
mbed_official 464:04583941e294 5291
mbed_official 464:04583941e294 5292 /******************* Bit definition for I2C_SR2 register ********************/
mbed_official 464:04583941e294 5293 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!<Master/Slave */
mbed_official 464:04583941e294 5294 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!<Bus Busy */
mbed_official 464:04583941e294 5295 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!<Transmitter/Receiver */
mbed_official 464:04583941e294 5296 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!<General Call Address (Slave mode) */
mbed_official 464:04583941e294 5297 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!<SMBus Device Default Address (Slave mode) */
mbed_official 464:04583941e294 5298 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!<SMBus Host Header (Slave mode) */
mbed_official 464:04583941e294 5299 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!<Dual Flag (Slave mode) */
mbed_official 464:04583941e294 5300 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!<Packet Error Checking Register */
mbed_official 464:04583941e294 5301
mbed_official 464:04583941e294 5302 /******************* Bit definition for I2C_CCR register ********************/
mbed_official 464:04583941e294 5303 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */
mbed_official 464:04583941e294 5304 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!<Fast Mode Duty Cycle */
mbed_official 464:04583941e294 5305 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!<I2C Master Mode Selection */
mbed_official 464:04583941e294 5306
mbed_official 464:04583941e294 5307 /****************** Bit definition for I2C_TRISE register *******************/
mbed_official 464:04583941e294 5308 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 464:04583941e294 5309
mbed_official 464:04583941e294 5310 /****************** Bit definition for I2C_FLTR register *******************/
mbed_official 464:04583941e294 5311 #define I2C_FLTR_DNF ((uint32_t)0x0000000F) /*!<Digital Noise Filter */
mbed_official 464:04583941e294 5312 #define I2C_FLTR_ANOFF ((uint32_t)0x00000010) /*!<Analog Noise Filter OFF */
mbed_official 464:04583941e294 5313
mbed_official 464:04583941e294 5314 /******************************************************************************/
mbed_official 464:04583941e294 5315 /* */
mbed_official 464:04583941e294 5316 /* Independent WATCHDOG */
mbed_official 464:04583941e294 5317 /* */
mbed_official 464:04583941e294 5318 /******************************************************************************/
mbed_official 464:04583941e294 5319 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 464:04583941e294 5320 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
mbed_official 464:04583941e294 5321
mbed_official 464:04583941e294 5322 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 464:04583941e294 5323 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
mbed_official 464:04583941e294 5324 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 464:04583941e294 5325 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 464:04583941e294 5326 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 464:04583941e294 5327
mbed_official 464:04583941e294 5328 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 464:04583941e294 5329 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
mbed_official 464:04583941e294 5330
mbed_official 464:04583941e294 5331 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 464:04583941e294 5332 #define IWDG_SR_PVU ((uint32_t)0x01) /*!<Watchdog prescaler value update */
mbed_official 464:04583941e294 5333 #define IWDG_SR_RVU ((uint32_t)0x02) /*!<Watchdog counter reload value update */
mbed_official 464:04583941e294 5334
mbed_official 464:04583941e294 5335
mbed_official 464:04583941e294 5336 /******************************************************************************/
mbed_official 464:04583941e294 5337 /* */
mbed_official 464:04583941e294 5338 /* LCD-TFT Display Controller (LTDC) */
mbed_official 464:04583941e294 5339 /* */
mbed_official 464:04583941e294 5340 /******************************************************************************/
mbed_official 464:04583941e294 5341
mbed_official 464:04583941e294 5342 /******************** Bit definition for LTDC_SSCR register *****************/
mbed_official 464:04583941e294 5343
mbed_official 464:04583941e294 5344 #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
mbed_official 464:04583941e294 5345 #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
mbed_official 464:04583941e294 5346
mbed_official 464:04583941e294 5347 /******************** Bit definition for LTDC_BPCR register *****************/
mbed_official 464:04583941e294 5348
mbed_official 464:04583941e294 5349 #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
mbed_official 464:04583941e294 5350 #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
mbed_official 464:04583941e294 5351
mbed_official 464:04583941e294 5352 /******************** Bit definition for LTDC_AWCR register *****************/
mbed_official 464:04583941e294 5353
mbed_official 464:04583941e294 5354 #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
mbed_official 464:04583941e294 5355 #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
mbed_official 464:04583941e294 5356
mbed_official 464:04583941e294 5357 /******************** Bit definition for LTDC_TWCR register *****************/
mbed_official 464:04583941e294 5358
mbed_official 464:04583941e294 5359 #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
mbed_official 464:04583941e294 5360 #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
mbed_official 464:04583941e294 5361
mbed_official 464:04583941e294 5362 /******************** Bit definition for LTDC_GCR register ******************/
mbed_official 464:04583941e294 5363
mbed_official 464:04583941e294 5364 #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
mbed_official 464:04583941e294 5365 #define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
mbed_official 464:04583941e294 5366 #define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
mbed_official 464:04583941e294 5367 #define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
mbed_official 464:04583941e294 5368 #define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
mbed_official 464:04583941e294 5369 #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
mbed_official 464:04583941e294 5370 #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
mbed_official 464:04583941e294 5371 #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
mbed_official 464:04583941e294 5372 #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
mbed_official 464:04583941e294 5373
mbed_official 464:04583941e294 5374 /******************** Bit definition for LTDC_SRCR register *****************/
mbed_official 464:04583941e294 5375
mbed_official 464:04583941e294 5376 #define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
mbed_official 464:04583941e294 5377 #define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
mbed_official 464:04583941e294 5378
mbed_official 464:04583941e294 5379 /******************** Bit definition for LTDC_BCCR register *****************/
mbed_official 464:04583941e294 5380
mbed_official 464:04583941e294 5381 #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
mbed_official 464:04583941e294 5382 #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
mbed_official 464:04583941e294 5383 #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
mbed_official 464:04583941e294 5384
mbed_official 464:04583941e294 5385 /******************** Bit definition for LTDC_IER register ******************/
mbed_official 464:04583941e294 5386
mbed_official 464:04583941e294 5387 #define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
mbed_official 464:04583941e294 5388 #define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
mbed_official 464:04583941e294 5389 #define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
mbed_official 464:04583941e294 5390 #define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
mbed_official 464:04583941e294 5391
mbed_official 464:04583941e294 5392 /******************** Bit definition for LTDC_ISR register ******************/
mbed_official 464:04583941e294 5393
mbed_official 464:04583941e294 5394 #define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
mbed_official 464:04583941e294 5395 #define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
mbed_official 464:04583941e294 5396 #define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
mbed_official 464:04583941e294 5397 #define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
mbed_official 464:04583941e294 5398
mbed_official 464:04583941e294 5399 /******************** Bit definition for LTDC_ICR register ******************/
mbed_official 464:04583941e294 5400
mbed_official 464:04583941e294 5401 #define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
mbed_official 464:04583941e294 5402 #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
mbed_official 464:04583941e294 5403 #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
mbed_official 464:04583941e294 5404 #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
mbed_official 464:04583941e294 5405
mbed_official 464:04583941e294 5406 /******************** Bit definition for LTDC_LIPCR register ****************/
mbed_official 464:04583941e294 5407
mbed_official 464:04583941e294 5408 #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
mbed_official 464:04583941e294 5409
mbed_official 464:04583941e294 5410 /******************** Bit definition for LTDC_CPSR register *****************/
mbed_official 464:04583941e294 5411
mbed_official 464:04583941e294 5412 #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
mbed_official 464:04583941e294 5413 #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
mbed_official 464:04583941e294 5414
mbed_official 464:04583941e294 5415 /******************** Bit definition for LTDC_CDSR register *****************/
mbed_official 464:04583941e294 5416
mbed_official 464:04583941e294 5417 #define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
mbed_official 464:04583941e294 5418 #define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
mbed_official 464:04583941e294 5419 #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
mbed_official 464:04583941e294 5420 #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
mbed_official 464:04583941e294 5421
mbed_official 464:04583941e294 5422 /******************** Bit definition for LTDC_LxCR register *****************/
mbed_official 464:04583941e294 5423
mbed_official 464:04583941e294 5424 #define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
mbed_official 464:04583941e294 5425 #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
mbed_official 464:04583941e294 5426 #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
mbed_official 464:04583941e294 5427
mbed_official 464:04583941e294 5428 /******************** Bit definition for LTDC_LxWHPCR register **************/
mbed_official 464:04583941e294 5429
mbed_official 464:04583941e294 5430 #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
mbed_official 464:04583941e294 5431 #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
mbed_official 464:04583941e294 5432
mbed_official 464:04583941e294 5433 /******************** Bit definition for LTDC_LxWVPCR register **************/
mbed_official 464:04583941e294 5434
mbed_official 464:04583941e294 5435 #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
mbed_official 464:04583941e294 5436 #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
mbed_official 464:04583941e294 5437
mbed_official 464:04583941e294 5438 /******************** Bit definition for LTDC_LxCKCR register ***************/
mbed_official 464:04583941e294 5439
mbed_official 464:04583941e294 5440 #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
mbed_official 464:04583941e294 5441 #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
mbed_official 464:04583941e294 5442 #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
mbed_official 464:04583941e294 5443
mbed_official 464:04583941e294 5444 /******************** Bit definition for LTDC_LxPFCR register ***************/
mbed_official 464:04583941e294 5445
mbed_official 464:04583941e294 5446 #define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
mbed_official 464:04583941e294 5447
mbed_official 464:04583941e294 5448 /******************** Bit definition for LTDC_LxCACR register ***************/
mbed_official 464:04583941e294 5449
mbed_official 464:04583941e294 5450 #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
mbed_official 464:04583941e294 5451
mbed_official 464:04583941e294 5452 /******************** Bit definition for LTDC_LxDCCR register ***************/
mbed_official 464:04583941e294 5453
mbed_official 464:04583941e294 5454 #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
mbed_official 464:04583941e294 5455 #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
mbed_official 464:04583941e294 5456 #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
mbed_official 464:04583941e294 5457 #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
mbed_official 464:04583941e294 5458
mbed_official 464:04583941e294 5459 /******************** Bit definition for LTDC_LxBFCR register ***************/
mbed_official 464:04583941e294 5460
mbed_official 464:04583941e294 5461 #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
mbed_official 464:04583941e294 5462 #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
mbed_official 464:04583941e294 5463
mbed_official 464:04583941e294 5464 /******************** Bit definition for LTDC_LxCFBAR register **************/
mbed_official 464:04583941e294 5465
mbed_official 464:04583941e294 5466 #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
mbed_official 464:04583941e294 5467
mbed_official 464:04583941e294 5468 /******************** Bit definition for LTDC_LxCFBLR register **************/
mbed_official 464:04583941e294 5469
mbed_official 464:04583941e294 5470 #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
mbed_official 464:04583941e294 5471 #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
mbed_official 464:04583941e294 5472
mbed_official 464:04583941e294 5473 /******************** Bit definition for LTDC_LxCFBLNR register *************/
mbed_official 464:04583941e294 5474
mbed_official 464:04583941e294 5475 #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
mbed_official 464:04583941e294 5476
mbed_official 464:04583941e294 5477 /******************** Bit definition for LTDC_LxCLUTWR register *************/
mbed_official 464:04583941e294 5478
mbed_official 464:04583941e294 5479 #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
mbed_official 464:04583941e294 5480 #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
mbed_official 464:04583941e294 5481 #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
mbed_official 464:04583941e294 5482 #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
mbed_official 464:04583941e294 5483
mbed_official 464:04583941e294 5484
mbed_official 464:04583941e294 5485 /******************************************************************************/
mbed_official 464:04583941e294 5486 /* */
mbed_official 464:04583941e294 5487 /* Power Control */
mbed_official 464:04583941e294 5488 /* */
mbed_official 464:04583941e294 5489 /******************************************************************************/
mbed_official 464:04583941e294 5490 /******************** Bit definition for PWR_CR register ********************/
mbed_official 464:04583941e294 5491 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
mbed_official 464:04583941e294 5492 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 464:04583941e294 5493 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 464:04583941e294 5494 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 464:04583941e294 5495 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 464:04583941e294 5496
mbed_official 464:04583941e294 5497 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 464:04583941e294 5498 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 464:04583941e294 5499 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 464:04583941e294 5500 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 464:04583941e294 5501
mbed_official 464:04583941e294 5502 /*!< PVD level configuration */
mbed_official 464:04583941e294 5503 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 464:04583941e294 5504 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 464:04583941e294 5505 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 464:04583941e294 5506 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 464:04583941e294 5507 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 464:04583941e294 5508 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 464:04583941e294 5509 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 464:04583941e294 5510 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 464:04583941e294 5511 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 464:04583941e294 5512 #define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
mbed_official 464:04583941e294 5513 #define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
mbed_official 464:04583941e294 5514 #define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */
mbed_official 464:04583941e294 5515 #define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 464:04583941e294 5516 #define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
mbed_official 464:04583941e294 5517 #define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 464:04583941e294 5518 #define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 464:04583941e294 5519 #define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
mbed_official 464:04583941e294 5520 #define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
mbed_official 464:04583941e294 5521 #define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
mbed_official 464:04583941e294 5522 #define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 464:04583941e294 5523 #define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 464:04583941e294 5524
mbed_official 464:04583941e294 5525 /* Legacy define */
mbed_official 464:04583941e294 5526 #define PWR_CR_PMODE PWR_CR_VOS
mbed_official 464:04583941e294 5527 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
mbed_official 464:04583941e294 5528 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
mbed_official 464:04583941e294 5529
mbed_official 464:04583941e294 5530 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 464:04583941e294 5531 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 464:04583941e294 5532 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 464:04583941e294 5533 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 464:04583941e294 5534 #define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
mbed_official 464:04583941e294 5535 #define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */
mbed_official 464:04583941e294 5536 #define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
mbed_official 464:04583941e294 5537 #define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
mbed_official 464:04583941e294 5538 #define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
mbed_official 464:04583941e294 5539 #define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
mbed_official 464:04583941e294 5540 #define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
mbed_official 464:04583941e294 5541
mbed_official 464:04583941e294 5542 /* Legacy define */
mbed_official 464:04583941e294 5543 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
mbed_official 464:04583941e294 5544
mbed_official 464:04583941e294 5545 /******************************************************************************/
mbed_official 464:04583941e294 5546 /* */
mbed_official 464:04583941e294 5547 /* Reset and Clock Control */
mbed_official 464:04583941e294 5548 /* */
mbed_official 464:04583941e294 5549 /******************************************************************************/
mbed_official 464:04583941e294 5550 /******************** Bit definition for RCC_CR register ********************/
mbed_official 464:04583941e294 5551 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5552 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5553
mbed_official 464:04583941e294 5554 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 464:04583941e294 5555 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
mbed_official 464:04583941e294 5556 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
mbed_official 464:04583941e294 5557 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
mbed_official 464:04583941e294 5558 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
mbed_official 464:04583941e294 5559 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
mbed_official 464:04583941e294 5560
mbed_official 464:04583941e294 5561 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 464:04583941e294 5562 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
mbed_official 464:04583941e294 5563 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
mbed_official 464:04583941e294 5564 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
mbed_official 464:04583941e294 5565 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
mbed_official 464:04583941e294 5566 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
mbed_official 464:04583941e294 5567 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
mbed_official 464:04583941e294 5568 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
mbed_official 464:04583941e294 5569 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
mbed_official 464:04583941e294 5570
mbed_official 464:04583941e294 5571 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5572 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5573 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5574 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 464:04583941e294 5575 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 464:04583941e294 5576 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5577 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5578 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
mbed_official 464:04583941e294 5579 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
mbed_official 464:04583941e294 5580 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
mbed_official 464:04583941e294 5581
mbed_official 464:04583941e294 5582 /******************** Bit definition for RCC_PLLCFGR register ***************/
mbed_official 464:04583941e294 5583 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
mbed_official 464:04583941e294 5584 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5585 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5586 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5587 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5588 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5589 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5590
mbed_official 464:04583941e294 5591 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
mbed_official 464:04583941e294 5592 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5593 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5594 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5595 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5596 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5597 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5598 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5599 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5600 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5601
mbed_official 464:04583941e294 5602 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
mbed_official 464:04583941e294 5603 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5604 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5605
mbed_official 464:04583941e294 5606 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5607 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5608 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
mbed_official 464:04583941e294 5609
mbed_official 464:04583941e294 5610 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
mbed_official 464:04583941e294 5611 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 5612 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5613 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5614 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 5615
mbed_official 464:04583941e294 5616 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 464:04583941e294 5617 /*!< SW configuration */
mbed_official 464:04583941e294 5618 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 464:04583941e294 5619 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 464:04583941e294 5620 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 464:04583941e294 5621
mbed_official 464:04583941e294 5622 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 464:04583941e294 5623 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 464:04583941e294 5624 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 464:04583941e294 5625
mbed_official 464:04583941e294 5626 /*!< SWS configuration */
mbed_official 464:04583941e294 5627 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 464:04583941e294 5628 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 464:04583941e294 5629 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 464:04583941e294 5630
mbed_official 464:04583941e294 5631 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 464:04583941e294 5632 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 464:04583941e294 5633 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 464:04583941e294 5634
mbed_official 464:04583941e294 5635 /*!< HPRE configuration */
mbed_official 464:04583941e294 5636 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 464:04583941e294 5637 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 464:04583941e294 5638 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 464:04583941e294 5639 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 464:04583941e294 5640 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 464:04583941e294 5641
mbed_official 464:04583941e294 5642 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 464:04583941e294 5643 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 464:04583941e294 5644 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 464:04583941e294 5645 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 464:04583941e294 5646 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 464:04583941e294 5647 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 464:04583941e294 5648 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 464:04583941e294 5649 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 464:04583941e294 5650 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 464:04583941e294 5651
mbed_official 464:04583941e294 5652 /*!< PPRE1 configuration */
mbed_official 464:04583941e294 5653 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 464:04583941e294 5654 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 464:04583941e294 5655 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 464:04583941e294 5656 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 464:04583941e294 5657
mbed_official 464:04583941e294 5658 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 464:04583941e294 5659 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
mbed_official 464:04583941e294 5660 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
mbed_official 464:04583941e294 5661 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
mbed_official 464:04583941e294 5662 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
mbed_official 464:04583941e294 5663
mbed_official 464:04583941e294 5664 /*!< PPRE2 configuration */
mbed_official 464:04583941e294 5665 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 464:04583941e294 5666 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 464:04583941e294 5667 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 464:04583941e294 5668 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 464:04583941e294 5669
mbed_official 464:04583941e294 5670 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 464:04583941e294 5671 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
mbed_official 464:04583941e294 5672 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
mbed_official 464:04583941e294 5673 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
mbed_official 464:04583941e294 5674 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
mbed_official 464:04583941e294 5675
mbed_official 464:04583941e294 5676 /*!< RTCPRE configuration */
mbed_official 464:04583941e294 5677 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
mbed_official 464:04583941e294 5678 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5679 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5680 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5681 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 5682 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5683
mbed_official 464:04583941e294 5684 /*!< MCO1 configuration */
mbed_official 464:04583941e294 5685 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
mbed_official 464:04583941e294 5686 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5687 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5688
mbed_official 464:04583941e294 5689 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
mbed_official 464:04583941e294 5690
mbed_official 464:04583941e294 5691 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
mbed_official 464:04583941e294 5692 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 5693 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5694 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5695
mbed_official 464:04583941e294 5696 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
mbed_official 464:04583941e294 5697 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 5698 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
mbed_official 464:04583941e294 5699 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
mbed_official 464:04583941e294 5700
mbed_official 464:04583941e294 5701 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
mbed_official 464:04583941e294 5702 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
mbed_official 464:04583941e294 5703 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
mbed_official 464:04583941e294 5704
mbed_official 464:04583941e294 5705 /******************** Bit definition for RCC_CIR register *******************/
mbed_official 464:04583941e294 5706 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5707 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5708 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5709 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5710 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5711 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5712 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5713 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5714 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5715 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5716 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5717 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5718 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5719 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5720 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5721 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5722 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5723 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5724 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
mbed_official 464:04583941e294 5725 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5726 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5727 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5728 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
mbed_official 464:04583941e294 5729
mbed_official 464:04583941e294 5730 /******************** Bit definition for RCC_AHB1RSTR register **************/
mbed_official 464:04583941e294 5731 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5732 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5733 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5734 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5735 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5736 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5737 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5738 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5739 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5740 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5741 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5742 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5743 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5744 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5745 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
mbed_official 464:04583941e294 5746 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5747 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)
mbed_official 464:04583941e294 5748
mbed_official 464:04583941e294 5749 /******************** Bit definition for RCC_AHB2RSTR register **************/
mbed_official 464:04583941e294 5750 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5751 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5752 #define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5753 /* maintained for legacy purpose */
mbed_official 464:04583941e294 5754 #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST
mbed_official 464:04583941e294 5755 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5756 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5757
mbed_official 464:04583941e294 5758 /******************** Bit definition for RCC_AHB3RSTR register **************/
mbed_official 464:04583941e294 5759 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5760
mbed_official 464:04583941e294 5761 /******************** Bit definition for RCC_APB1RSTR register **************/
mbed_official 464:04583941e294 5762 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5763 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5764 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5765 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5766 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5767 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5768 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5769 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5770 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5771 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5772 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5773 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
mbed_official 464:04583941e294 5774 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5775 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5776 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
mbed_official 464:04583941e294 5777 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5778 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5779 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5780 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
mbed_official 464:04583941e294 5781 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5782 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5783 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
mbed_official 464:04583941e294 5784 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
mbed_official 464:04583941e294 5785 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
mbed_official 464:04583941e294 5786 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
mbed_official 464:04583941e294 5787
mbed_official 464:04583941e294 5788 /******************** Bit definition for RCC_APB2RSTR register **************/
mbed_official 464:04583941e294 5789 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5790 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5791 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5792 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5793 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5794 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5795 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5796 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5797 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5798 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5799 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5800 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5801 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5802 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5803 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5804 #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5805
mbed_official 464:04583941e294 5806 /* Old SPI1RST bit definition, maintained for legacy purpose */
mbed_official 464:04583941e294 5807 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
mbed_official 464:04583941e294 5808
mbed_official 464:04583941e294 5809 /******************** Bit definition for RCC_AHB1ENR register ***************/
mbed_official 464:04583941e294 5810 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5811 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5812 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5813 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5814 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5815 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5816 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5817 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5818 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5819 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5820 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5821
mbed_official 464:04583941e294 5822 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5823 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5824 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5825 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5826 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5827 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
mbed_official 464:04583941e294 5828
mbed_official 464:04583941e294 5829 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5830 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5831 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
mbed_official 464:04583941e294 5832 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
mbed_official 464:04583941e294 5833 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
mbed_official 464:04583941e294 5834 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
mbed_official 464:04583941e294 5835
mbed_official 464:04583941e294 5836 /******************** Bit definition for RCC_AHB2ENR register ***************/
mbed_official 464:04583941e294 5837 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5838 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5839 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5840 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5841 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5842
mbed_official 464:04583941e294 5843 /******************** Bit definition for RCC_AHB3ENR register ***************/
mbed_official 464:04583941e294 5844 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5845
mbed_official 464:04583941e294 5846 /******************** Bit definition for RCC_APB1ENR register ***************/
mbed_official 464:04583941e294 5847 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5848 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5849 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5850 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5851 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5852 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5853 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5854 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5855 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5856 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5857 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5858 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
mbed_official 464:04583941e294 5859 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5860 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5861 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
mbed_official 464:04583941e294 5862 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5863 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5864 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5865 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
mbed_official 464:04583941e294 5866 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5867 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5868 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
mbed_official 464:04583941e294 5869 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
mbed_official 464:04583941e294 5870 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
mbed_official 464:04583941e294 5871 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
mbed_official 464:04583941e294 5872
mbed_official 464:04583941e294 5873 /******************** Bit definition for RCC_APB2ENR register ***************/
mbed_official 464:04583941e294 5874 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5875 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5876 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5877 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5878 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5879 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5880 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5881 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5882 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5883 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5884 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5885 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5886 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5887 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5888 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5889 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5890 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5891 #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5892
mbed_official 464:04583941e294 5893 /******************** Bit definition for RCC_AHB1LPENR register *************/
mbed_official 464:04583941e294 5894 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5895 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5896 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5897 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5898 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5899 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5900 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5901 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5902 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5903 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5904 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5905
mbed_official 464:04583941e294 5906 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5907 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
mbed_official 464:04583941e294 5908 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5909 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5910 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5911 #define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)
mbed_official 464:04583941e294 5912 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5913 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5914 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
mbed_official 464:04583941e294 5915
mbed_official 464:04583941e294 5916 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5917 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5918 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
mbed_official 464:04583941e294 5919 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
mbed_official 464:04583941e294 5920 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
mbed_official 464:04583941e294 5921 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
mbed_official 464:04583941e294 5922
mbed_official 464:04583941e294 5923 /******************** Bit definition for RCC_AHB2LPENR register *************/
mbed_official 464:04583941e294 5924 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5925 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5926 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5927 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5928 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5929
mbed_official 464:04583941e294 5930 /******************** Bit definition for RCC_AHB3LPENR register *************/
mbed_official 464:04583941e294 5931 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5932
mbed_official 464:04583941e294 5933 /******************** Bit definition for RCC_APB1LPENR register *************/
mbed_official 464:04583941e294 5934 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5935 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5936 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5937 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
mbed_official 464:04583941e294 5938 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5939 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5940 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
mbed_official 464:04583941e294 5941 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
mbed_official 464:04583941e294 5942 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5943 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5944 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5945 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
mbed_official 464:04583941e294 5946 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5947 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5948 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
mbed_official 464:04583941e294 5949 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5950 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5951 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5952 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
mbed_official 464:04583941e294 5953 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5954 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5955 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
mbed_official 464:04583941e294 5956 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
mbed_official 464:04583941e294 5957 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
mbed_official 464:04583941e294 5958 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
mbed_official 464:04583941e294 5959
mbed_official 464:04583941e294 5960 /******************** Bit definition for RCC_APB2LPENR register *************/
mbed_official 464:04583941e294 5961 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5962 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5963 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
mbed_official 464:04583941e294 5964 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
mbed_official 464:04583941e294 5965 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5966 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5967 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
mbed_official 464:04583941e294 5968 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)
mbed_official 464:04583941e294 5969 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
mbed_official 464:04583941e294 5970 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
mbed_official 464:04583941e294 5971 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
mbed_official 464:04583941e294 5972 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5973 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
mbed_official 464:04583941e294 5974 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
mbed_official 464:04583941e294 5975 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
mbed_official 464:04583941e294 5976 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
mbed_official 464:04583941e294 5977 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
mbed_official 464:04583941e294 5978 #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5979
mbed_official 464:04583941e294 5980 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 464:04583941e294 5981 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5982 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5983 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
mbed_official 464:04583941e294 5984
mbed_official 464:04583941e294 5985 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
mbed_official 464:04583941e294 5986 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 5987 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 5988
mbed_official 464:04583941e294 5989 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
mbed_official 464:04583941e294 5990 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
mbed_official 464:04583941e294 5991
mbed_official 464:04583941e294 5992 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 464:04583941e294 5993 #define RCC_CSR_LSION ((uint32_t)0x00000001)
mbed_official 464:04583941e294 5994 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
mbed_official 464:04583941e294 5995 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
mbed_official 464:04583941e294 5996 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
mbed_official 464:04583941e294 5997 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000)
mbed_official 464:04583941e294 5998 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
mbed_official 464:04583941e294 5999 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
mbed_official 464:04583941e294 6000 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)
mbed_official 464:04583941e294 6001 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
mbed_official 464:04583941e294 6002 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
mbed_official 464:04583941e294 6003
mbed_official 464:04583941e294 6004 /******************** Bit definition for RCC_SSCGR register *****************/
mbed_official 464:04583941e294 6005 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
mbed_official 464:04583941e294 6006 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
mbed_official 464:04583941e294 6007 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
mbed_official 464:04583941e294 6008 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
mbed_official 464:04583941e294 6009
mbed_official 464:04583941e294 6010 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
mbed_official 464:04583941e294 6011 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
mbed_official 464:04583941e294 6012 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 6013 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 6014 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6015 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6016 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6017 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6018 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6019 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6020 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6021
mbed_official 464:04583941e294 6022 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
mbed_official 464:04583941e294 6023 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 6024 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 6025 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 6026 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 6027
mbed_official 464:04583941e294 6028 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
mbed_official 464:04583941e294 6029 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
mbed_official 464:04583941e294 6030 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
mbed_official 464:04583941e294 6031 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
mbed_official 464:04583941e294 6032
mbed_official 464:04583941e294 6033
mbed_official 464:04583941e294 6034 /******************** Bit definition for RCC_PLLSAICFGR register ************/
mbed_official 464:04583941e294 6035 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
mbed_official 464:04583941e294 6036 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 6037 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 6038 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6039 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6040 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6041 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6042 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6043 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6044 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6045
mbed_official 464:04583941e294 6046 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
mbed_official 464:04583941e294 6047 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 6048 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 6049 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 6050 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 6051
mbed_official 464:04583941e294 6052 #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
mbed_official 464:04583941e294 6053 #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
mbed_official 464:04583941e294 6054 #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
mbed_official 464:04583941e294 6055 #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
mbed_official 464:04583941e294 6056
mbed_official 464:04583941e294 6057 /******************** Bit definition for RCC_DCKCFGR register ***************/
mbed_official 464:04583941e294 6058 #define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)
mbed_official 464:04583941e294 6059 #define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)
mbed_official 464:04583941e294 6060 #define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)
mbed_official 464:04583941e294 6061 #define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)
mbed_official 464:04583941e294 6062 #define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)
mbed_official 464:04583941e294 6063 #define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)
mbed_official 464:04583941e294 6064
mbed_official 464:04583941e294 6065
mbed_official 464:04583941e294 6066 /******************************************************************************/
mbed_official 464:04583941e294 6067 /* */
mbed_official 464:04583941e294 6068 /* RNG */
mbed_official 464:04583941e294 6069 /* */
mbed_official 464:04583941e294 6070 /******************************************************************************/
mbed_official 464:04583941e294 6071 /******************** Bits definition for RNG_CR register *******************/
mbed_official 464:04583941e294 6072 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6073 #define RNG_CR_IE ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6074
mbed_official 464:04583941e294 6075 /******************** Bits definition for RNG_SR register *******************/
mbed_official 464:04583941e294 6076 #define RNG_SR_DRDY ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6077 #define RNG_SR_CECS ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6078 #define RNG_SR_SECS ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6079 #define RNG_SR_CEIS ((uint32_t)0x00000020)
mbed_official 464:04583941e294 6080 #define RNG_SR_SEIS ((uint32_t)0x00000040)
mbed_official 464:04583941e294 6081
mbed_official 464:04583941e294 6082 /******************************************************************************/
mbed_official 464:04583941e294 6083 /* */
mbed_official 464:04583941e294 6084 /* Real-Time Clock (RTC) */
mbed_official 464:04583941e294 6085 /* */
mbed_official 464:04583941e294 6086 /******************************************************************************/
mbed_official 464:04583941e294 6087 /******************** Bits definition for RTC_TR register *******************/
mbed_official 464:04583941e294 6088 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 464:04583941e294 6089 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 464:04583941e294 6090 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 6091 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 6092 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 464:04583941e294 6093 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 6094 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 6095 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 6096 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 6097 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 464:04583941e294 6098 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6099 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6100 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6101 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 464:04583941e294 6102 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6103 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6104 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6105 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6106 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 464:04583941e294 6107 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 6108 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 6109 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 6110 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 464:04583941e294 6111 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6112 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6113 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6114 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6115
mbed_official 464:04583941e294 6116 /******************** Bits definition for RTC_DR register *******************/
mbed_official 464:04583941e294 6117 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 464:04583941e294 6118 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 6119 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 6120 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 6121 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 464:04583941e294 6122 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 464:04583941e294 6123 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 6124 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 6125 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 6126 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 6127 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 464:04583941e294 6128 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6129 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6130 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 6131 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6132 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 464:04583941e294 6133 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6134 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6135 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6136 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6137 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 464:04583941e294 6138 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 6139 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 6140 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 464:04583941e294 6141 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6142 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6143 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6144 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6145
mbed_official 464:04583941e294 6146 /******************** Bits definition for RTC_CR register *******************/
mbed_official 464:04583941e294 6147 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 464:04583941e294 6148 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 464:04583941e294 6149 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 6150 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 464:04583941e294 6151 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 464:04583941e294 6152 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 464:04583941e294 6153 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 464:04583941e294 6154 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 464:04583941e294 6155 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 464:04583941e294 6156 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 464:04583941e294 6157 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6158 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6159 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6160 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6161 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6162 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6163 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6164 #define RTC_CR_DCE ((uint32_t)0x00000080)
mbed_official 464:04583941e294 6165 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 464:04583941e294 6166 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 464:04583941e294 6167 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 464:04583941e294 6168 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6169 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 464:04583941e294 6170 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6171 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6172 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6173
mbed_official 464:04583941e294 6174 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 464:04583941e294 6175 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 464:04583941e294 6176 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6177 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6178 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6179 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6180 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6181 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6182 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6183 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 464:04583941e294 6184 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 464:04583941e294 6185 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 464:04583941e294 6186 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 464:04583941e294 6187 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6188 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6189 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6190 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6191
mbed_official 464:04583941e294 6192 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 464:04583941e294 6193 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 464:04583941e294 6194 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)
mbed_official 464:04583941e294 6195
mbed_official 464:04583941e294 6196 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 464:04583941e294 6197 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 464:04583941e294 6198
mbed_official 464:04583941e294 6199 /******************** Bits definition for RTC_CALIBR register ***************/
mbed_official 464:04583941e294 6200 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
mbed_official 464:04583941e294 6201 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
mbed_official 464:04583941e294 6202
mbed_official 464:04583941e294 6203 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 464:04583941e294 6204 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 464:04583941e294 6205 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 464:04583941e294 6206 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 464:04583941e294 6207 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 464:04583941e294 6208 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 464:04583941e294 6209 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 464:04583941e294 6210 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 6211 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 6212 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 6213 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 6214 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 464:04583941e294 6215 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 464:04583941e294 6216 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 464:04583941e294 6217 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 6218 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 6219 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 464:04583941e294 6220 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 6221 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 6222 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 6223 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 6224 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 6225 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 464:04583941e294 6226 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6227 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6228 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6229 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 464:04583941e294 6230 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6231 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6232 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6233 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6234 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 6235 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 464:04583941e294 6236 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 6237 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 6238 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 6239 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 464:04583941e294 6240 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6241 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6242 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6243 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6244
mbed_official 464:04583941e294 6245 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 464:04583941e294 6246 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 464:04583941e294 6247 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 464:04583941e294 6248 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 464:04583941e294 6249 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 464:04583941e294 6250 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 464:04583941e294 6251 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 464:04583941e294 6252 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 6253 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 6254 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 6255 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 6256 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 464:04583941e294 6257 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 464:04583941e294 6258 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 464:04583941e294 6259 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 6260 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 6261 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 464:04583941e294 6262 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 6263 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 6264 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 6265 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 6266 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 6267 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 464:04583941e294 6268 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6269 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6270 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6271 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 464:04583941e294 6272 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6273 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6274 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6275 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6276 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 6277 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 464:04583941e294 6278 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 6279 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 6280 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 6281 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 464:04583941e294 6282 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6283 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6284 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6285 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6286
mbed_official 464:04583941e294 6287 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 464:04583941e294 6288 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 464:04583941e294 6289
mbed_official 464:04583941e294 6290 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 464:04583941e294 6291 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 464:04583941e294 6292
mbed_official 464:04583941e294 6293 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 464:04583941e294 6294 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 464:04583941e294 6295 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 464:04583941e294 6296
mbed_official 464:04583941e294 6297 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 464:04583941e294 6298 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 464:04583941e294 6299 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 464:04583941e294 6300 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 464:04583941e294 6301 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 464:04583941e294 6302 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 464:04583941e294 6303 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 464:04583941e294 6304 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 464:04583941e294 6305 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 464:04583941e294 6306 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 464:04583941e294 6307 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 464:04583941e294 6308 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6309 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6310 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6311 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 464:04583941e294 6312 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6313 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6314 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6315 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6316 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 464:04583941e294 6317 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 6318 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 6319 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 6320 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 464:04583941e294 6321 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6322 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6323 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6324 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6325
mbed_official 464:04583941e294 6326 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 464:04583941e294 6327 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 464:04583941e294 6328 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6329 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6330 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 464:04583941e294 6331 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6332 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 464:04583941e294 6333 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6334 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6335 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6336 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6337 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 464:04583941e294 6338 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 6339 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 6340 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 464:04583941e294 6341 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6342 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6343 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6344 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6345
mbed_official 464:04583941e294 6346 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 464:04583941e294 6347 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 464:04583941e294 6348
mbed_official 464:04583941e294 6349 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 464:04583941e294 6350 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 464:04583941e294 6351 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6352 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6353 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 464:04583941e294 6354 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6355 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6356 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6357 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6358 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 464:04583941e294 6359 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 464:04583941e294 6360 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 464:04583941e294 6361 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 464:04583941e294 6362 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6363
mbed_official 464:04583941e294 6364 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 464:04583941e294 6365 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 464:04583941e294 6366 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)
mbed_official 464:04583941e294 6367 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)
mbed_official 464:04583941e294 6368 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 464:04583941e294 6369 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 464:04583941e294 6370 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 464:04583941e294 6371 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 464:04583941e294 6372 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 464:04583941e294 6373 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 464:04583941e294 6374 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 464:04583941e294 6375 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 464:04583941e294 6376 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 464:04583941e294 6377 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 464:04583941e294 6378 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 464:04583941e294 6379 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 464:04583941e294 6380 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 464:04583941e294 6381 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 464:04583941e294 6382 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6383 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6384 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6385
mbed_official 464:04583941e294 6386 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 464:04583941e294 6387 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 464:04583941e294 6388 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 6389 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 6390 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 6391 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 6392 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 464:04583941e294 6393
mbed_official 464:04583941e294 6394 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 464:04583941e294 6395 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 464:04583941e294 6396 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 464:04583941e294 6397 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 464:04583941e294 6398 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 464:04583941e294 6399 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 464:04583941e294 6400 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 464:04583941e294 6401
mbed_official 464:04583941e294 6402 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 464:04583941e294 6403 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6404
mbed_official 464:04583941e294 6405 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 464:04583941e294 6406 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6407
mbed_official 464:04583941e294 6408 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 464:04583941e294 6409 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6410
mbed_official 464:04583941e294 6411 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 464:04583941e294 6412 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6413
mbed_official 464:04583941e294 6414 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 464:04583941e294 6415 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6416
mbed_official 464:04583941e294 6417 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 464:04583941e294 6418 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6419
mbed_official 464:04583941e294 6420 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 464:04583941e294 6421 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6422
mbed_official 464:04583941e294 6423 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 464:04583941e294 6424 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6425
mbed_official 464:04583941e294 6426 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 464:04583941e294 6427 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6428
mbed_official 464:04583941e294 6429 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 464:04583941e294 6430 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6431
mbed_official 464:04583941e294 6432 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 464:04583941e294 6433 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6434
mbed_official 464:04583941e294 6435 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 464:04583941e294 6436 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6437
mbed_official 464:04583941e294 6438 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 464:04583941e294 6439 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6440
mbed_official 464:04583941e294 6441 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 464:04583941e294 6442 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6443
mbed_official 464:04583941e294 6444 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 464:04583941e294 6445 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6446
mbed_official 464:04583941e294 6447 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 464:04583941e294 6448 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6449
mbed_official 464:04583941e294 6450 /******************** Bits definition for RTC_BKP16R register ***************/
mbed_official 464:04583941e294 6451 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6452
mbed_official 464:04583941e294 6453 /******************** Bits definition for RTC_BKP17R register ***************/
mbed_official 464:04583941e294 6454 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6455
mbed_official 464:04583941e294 6456 /******************** Bits definition for RTC_BKP18R register ***************/
mbed_official 464:04583941e294 6457 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6458
mbed_official 464:04583941e294 6459 /******************** Bits definition for RTC_BKP19R register ***************/
mbed_official 464:04583941e294 6460 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6461
mbed_official 464:04583941e294 6462 /******************************************************************************/
mbed_official 464:04583941e294 6463 /* */
mbed_official 464:04583941e294 6464 /* Serial Audio Interface */
mbed_official 464:04583941e294 6465 /* */
mbed_official 464:04583941e294 6466 /******************************************************************************/
mbed_official 464:04583941e294 6467 /******************** Bit definition for SAI_GCR register *******************/
mbed_official 464:04583941e294 6468 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
mbed_official 464:04583941e294 6469 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 6470 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 6471
mbed_official 464:04583941e294 6472 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
mbed_official 464:04583941e294 6473 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 6474 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 6475
mbed_official 464:04583941e294 6476 /******************* Bit definition for SAI_xCR1 register *******************/
mbed_official 464:04583941e294 6477 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
mbed_official 464:04583941e294 6478 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 6479 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 6480
mbed_official 464:04583941e294 6481 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
mbed_official 464:04583941e294 6482 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 464:04583941e294 6483 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 464:04583941e294 6484
mbed_official 464:04583941e294 6485 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
mbed_official 464:04583941e294 6486 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 464:04583941e294 6487 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 464:04583941e294 6488 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 464:04583941e294 6489
mbed_official 464:04583941e294 6490 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
mbed_official 464:04583941e294 6491 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
mbed_official 464:04583941e294 6492
mbed_official 464:04583941e294 6493 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
mbed_official 464:04583941e294 6494 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 464:04583941e294 6495 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 464:04583941e294 6496
mbed_official 464:04583941e294 6497 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
mbed_official 464:04583941e294 6498 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
mbed_official 464:04583941e294 6499 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
mbed_official 464:04583941e294 6500 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
mbed_official 464:04583941e294 6501 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
mbed_official 464:04583941e294 6502
mbed_official 464:04583941e294 6503 #define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
mbed_official 464:04583941e294 6504 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */
mbed_official 464:04583941e294 6505 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */
mbed_official 464:04583941e294 6506 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */
mbed_official 464:04583941e294 6507 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */
mbed_official 464:04583941e294 6508
mbed_official 464:04583941e294 6509 /******************* Bit definition for SAI_xCR2 register *******************/
mbed_official 464:04583941e294 6510 #define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */
mbed_official 464:04583941e294 6511 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 6512 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 6513
mbed_official 464:04583941e294 6514 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
mbed_official 464:04583941e294 6515 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
mbed_official 464:04583941e294 6516 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
mbed_official 464:04583941e294 6517 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
mbed_official 464:04583941e294 6518
mbed_official 464:04583941e294 6519 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
mbed_official 464:04583941e294 6520 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 464:04583941e294 6521 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 464:04583941e294 6522 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
mbed_official 464:04583941e294 6523 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
mbed_official 464:04583941e294 6524 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
mbed_official 464:04583941e294 6525 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
mbed_official 464:04583941e294 6526
mbed_official 464:04583941e294 6527 #define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */
mbed_official 464:04583941e294 6528
mbed_official 464:04583941e294 6529 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
mbed_official 464:04583941e294 6530 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 464:04583941e294 6531 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 464:04583941e294 6532
mbed_official 464:04583941e294 6533 /****************** Bit definition for SAI_xFRCR register *******************/
mbed_official 464:04583941e294 6534 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
mbed_official 464:04583941e294 6535 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 6536 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 6537 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 6538 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 6539 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 6540 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 6541 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 464:04583941e294 6542 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 464:04583941e294 6543
mbed_official 464:04583941e294 6544 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
mbed_official 464:04583941e294 6545 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 6546 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 6547 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 6548 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 6549 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 464:04583941e294 6550 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 464:04583941e294 6551 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 464:04583941e294 6552
mbed_official 464:04583941e294 6553 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
mbed_official 464:04583941e294 6554 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
mbed_official 464:04583941e294 6555 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
mbed_official 464:04583941e294 6556
mbed_official 464:04583941e294 6557 /****************** Bit definition for SAI_xSLOTR register *******************/
mbed_official 464:04583941e294 6558 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
mbed_official 464:04583941e294 6559 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 6560 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 6561 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 6562 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 6563 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 6564
mbed_official 464:04583941e294 6565 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
mbed_official 464:04583941e294 6566 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 464:04583941e294 6567 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 464:04583941e294 6568
mbed_official 464:04583941e294 6569 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
mbed_official 464:04583941e294 6570 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 6571 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 6572 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 464:04583941e294 6573 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 464:04583941e294 6574
mbed_official 464:04583941e294 6575 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
mbed_official 464:04583941e294 6576
mbed_official 464:04583941e294 6577 /******************* Bit definition for SAI_xIMR register *******************/
mbed_official 464:04583941e294 6578 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
mbed_official 464:04583941e294 6579 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
mbed_official 464:04583941e294 6580 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
mbed_official 464:04583941e294 6581 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
mbed_official 464:04583941e294 6582 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
mbed_official 464:04583941e294 6583 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
mbed_official 464:04583941e294 6584 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
mbed_official 464:04583941e294 6585
mbed_official 464:04583941e294 6586 /******************** Bit definition for SAI_xSR register *******************/
mbed_official 464:04583941e294 6587 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
mbed_official 464:04583941e294 6588 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
mbed_official 464:04583941e294 6589 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
mbed_official 464:04583941e294 6590 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
mbed_official 464:04583941e294 6591 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
mbed_official 464:04583941e294 6592 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
mbed_official 464:04583941e294 6593 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
mbed_official 464:04583941e294 6594
mbed_official 464:04583941e294 6595 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
mbed_official 464:04583941e294 6596 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 6597 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 6598 #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */
mbed_official 464:04583941e294 6599
mbed_official 464:04583941e294 6600 /****************** Bit definition for SAI_xCLRFR register ******************/
mbed_official 464:04583941e294 6601 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
mbed_official 464:04583941e294 6602 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
mbed_official 464:04583941e294 6603 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
mbed_official 464:04583941e294 6604 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
mbed_official 464:04583941e294 6605 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
mbed_official 464:04583941e294 6606 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
mbed_official 464:04583941e294 6607 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
mbed_official 464:04583941e294 6608
mbed_official 464:04583941e294 6609 /****************** Bit definition for SAI_xDR register ******************/
mbed_official 464:04583941e294 6610 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
mbed_official 464:04583941e294 6611
mbed_official 464:04583941e294 6612
mbed_official 464:04583941e294 6613 /******************************************************************************/
mbed_official 464:04583941e294 6614 /* */
mbed_official 464:04583941e294 6615 /* SD host Interface */
mbed_official 464:04583941e294 6616 /* */
mbed_official 464:04583941e294 6617 /******************************************************************************/
mbed_official 464:04583941e294 6618 /****************** Bit definition for SDIO_POWER register ******************/
mbed_official 464:04583941e294 6619 #define SDIO_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
mbed_official 464:04583941e294 6620 #define SDIO_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 464:04583941e294 6621 #define SDIO_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 464:04583941e294 6622
mbed_official 464:04583941e294 6623 /****************** Bit definition for SDIO_CLKCR register ******************/
mbed_official 464:04583941e294 6624 #define SDIO_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
mbed_official 464:04583941e294 6625 #define SDIO_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
mbed_official 464:04583941e294 6626 #define SDIO_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
mbed_official 464:04583941e294 6627 #define SDIO_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
mbed_official 464:04583941e294 6628
mbed_official 464:04583941e294 6629 #define SDIO_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
mbed_official 464:04583941e294 6630 #define SDIO_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
mbed_official 464:04583941e294 6631 #define SDIO_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
mbed_official 464:04583941e294 6632
mbed_official 464:04583941e294 6633 #define SDIO_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDIO_CK dephasing selection bit */
mbed_official 464:04583941e294 6634 #define SDIO_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
mbed_official 464:04583941e294 6635
mbed_official 464:04583941e294 6636 /******************* Bit definition for SDIO_ARG register *******************/
mbed_official 464:04583941e294 6637 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
mbed_official 464:04583941e294 6638
mbed_official 464:04583941e294 6639 /******************* Bit definition for SDIO_CMD register *******************/
mbed_official 464:04583941e294 6640 #define SDIO_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
mbed_official 464:04583941e294 6641
mbed_official 464:04583941e294 6642 #define SDIO_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
mbed_official 464:04583941e294 6643 #define SDIO_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
mbed_official 464:04583941e294 6644 #define SDIO_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
mbed_official 464:04583941e294 6645
mbed_official 464:04583941e294 6646 #define SDIO_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
mbed_official 464:04583941e294 6647 #define SDIO_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
mbed_official 464:04583941e294 6648 #define SDIO_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
mbed_official 464:04583941e294 6649 #define SDIO_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
mbed_official 464:04583941e294 6650 #define SDIO_CMD_ENCMDCOMPL ((uint32_t)0x1000) /*!<Enable CMD completion */
mbed_official 464:04583941e294 6651 #define SDIO_CMD_NIEN ((uint32_t)0x2000) /*!<Not Interrupt Enable */
mbed_official 464:04583941e294 6652 #define SDIO_CMD_CEATACMD ((uint32_t)0x4000) /*!<CE-ATA command */
mbed_official 464:04583941e294 6653
mbed_official 464:04583941e294 6654 /***************** Bit definition for SDIO_RESPCMD register *****************/
mbed_official 464:04583941e294 6655 #define SDIO_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
mbed_official 464:04583941e294 6656
mbed_official 464:04583941e294 6657 /****************** Bit definition for SDIO_RESP0 register ******************/
mbed_official 464:04583941e294 6658 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 464:04583941e294 6659
mbed_official 464:04583941e294 6660 /****************** Bit definition for SDIO_RESP1 register ******************/
mbed_official 464:04583941e294 6661 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 464:04583941e294 6662
mbed_official 464:04583941e294 6663 /****************** Bit definition for SDIO_RESP2 register ******************/
mbed_official 464:04583941e294 6664 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 464:04583941e294 6665
mbed_official 464:04583941e294 6666 /****************** Bit definition for SDIO_RESP3 register ******************/
mbed_official 464:04583941e294 6667 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 464:04583941e294 6668
mbed_official 464:04583941e294 6669 /****************** Bit definition for SDIO_RESP4 register ******************/
mbed_official 464:04583941e294 6670 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
mbed_official 464:04583941e294 6671
mbed_official 464:04583941e294 6672 /****************** Bit definition for SDIO_DTIMER register *****************/
mbed_official 464:04583941e294 6673 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
mbed_official 464:04583941e294 6674
mbed_official 464:04583941e294 6675 /****************** Bit definition for SDIO_DLEN register *******************/
mbed_official 464:04583941e294 6676 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
mbed_official 464:04583941e294 6677
mbed_official 464:04583941e294 6678 /****************** Bit definition for SDIO_DCTRL register ******************/
mbed_official 464:04583941e294 6679 #define SDIO_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
mbed_official 464:04583941e294 6680 #define SDIO_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
mbed_official 464:04583941e294 6681 #define SDIO_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
mbed_official 464:04583941e294 6682 #define SDIO_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
mbed_official 464:04583941e294 6683
mbed_official 464:04583941e294 6684 #define SDIO_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
mbed_official 464:04583941e294 6685 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 464:04583941e294 6686 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 464:04583941e294 6687 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 464:04583941e294 6688 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 464:04583941e294 6689
mbed_official 464:04583941e294 6690 #define SDIO_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
mbed_official 464:04583941e294 6691 #define SDIO_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
mbed_official 464:04583941e294 6692 #define SDIO_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
mbed_official 464:04583941e294 6693 #define SDIO_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
mbed_official 464:04583941e294 6694
mbed_official 464:04583941e294 6695 /****************** Bit definition for SDIO_DCOUNT register *****************/
mbed_official 464:04583941e294 6696 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
mbed_official 464:04583941e294 6697
mbed_official 464:04583941e294 6698 /****************** Bit definition for SDIO_STA register ********************/
mbed_official 464:04583941e294 6699 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
mbed_official 464:04583941e294 6700 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
mbed_official 464:04583941e294 6701 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
mbed_official 464:04583941e294 6702 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
mbed_official 464:04583941e294 6703 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
mbed_official 464:04583941e294 6704 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
mbed_official 464:04583941e294 6705 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
mbed_official 464:04583941e294 6706 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
mbed_official 464:04583941e294 6707 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
mbed_official 464:04583941e294 6708 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */
mbed_official 464:04583941e294 6709 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
mbed_official 464:04583941e294 6710 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
mbed_official 464:04583941e294 6711 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
mbed_official 464:04583941e294 6712 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
mbed_official 464:04583941e294 6713 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
mbed_official 464:04583941e294 6714 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
mbed_official 464:04583941e294 6715 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
mbed_official 464:04583941e294 6716 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
mbed_official 464:04583941e294 6717 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
mbed_official 464:04583941e294 6718 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
mbed_official 464:04583941e294 6719 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
mbed_official 464:04583941e294 6720 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
mbed_official 464:04583941e294 6721 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */
mbed_official 464:04583941e294 6722 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */
mbed_official 464:04583941e294 6723
mbed_official 464:04583941e294 6724 /******************* Bit definition for SDIO_ICR register *******************/
mbed_official 464:04583941e294 6725 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
mbed_official 464:04583941e294 6726 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
mbed_official 464:04583941e294 6727 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
mbed_official 464:04583941e294 6728 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
mbed_official 464:04583941e294 6729 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
mbed_official 464:04583941e294 6730 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
mbed_official 464:04583941e294 6731 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
mbed_official 464:04583941e294 6732 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
mbed_official 464:04583941e294 6733 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
mbed_official 464:04583941e294 6734 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */
mbed_official 464:04583941e294 6735 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
mbed_official 464:04583941e294 6736 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */
mbed_official 464:04583941e294 6737 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */
mbed_official 464:04583941e294 6738
mbed_official 464:04583941e294 6739 /****************** Bit definition for SDIO_MASK register *******************/
mbed_official 464:04583941e294 6740 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
mbed_official 464:04583941e294 6741 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
mbed_official 464:04583941e294 6742 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
mbed_official 464:04583941e294 6743 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
mbed_official 464:04583941e294 6744 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
mbed_official 464:04583941e294 6745 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
mbed_official 464:04583941e294 6746 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
mbed_official 464:04583941e294 6747 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
mbed_official 464:04583941e294 6748 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
mbed_official 464:04583941e294 6749 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */
mbed_official 464:04583941e294 6750 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
mbed_official 464:04583941e294 6751 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
mbed_official 464:04583941e294 6752 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
mbed_official 464:04583941e294 6753 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
mbed_official 464:04583941e294 6754 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
mbed_official 464:04583941e294 6755 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
mbed_official 464:04583941e294 6756 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
mbed_official 464:04583941e294 6757 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
mbed_official 464:04583941e294 6758 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
mbed_official 464:04583941e294 6759 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
mbed_official 464:04583941e294 6760 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
mbed_official 464:04583941e294 6761 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
mbed_official 464:04583941e294 6762 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */
mbed_official 464:04583941e294 6763 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */
mbed_official 464:04583941e294 6764
mbed_official 464:04583941e294 6765 /***************** Bit definition for SDIO_FIFOCNT register *****************/
mbed_official 464:04583941e294 6766 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
mbed_official 464:04583941e294 6767
mbed_official 464:04583941e294 6768 /****************** Bit definition for SDIO_FIFO register *******************/
mbed_official 464:04583941e294 6769 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
mbed_official 464:04583941e294 6770
mbed_official 464:04583941e294 6771 /******************************************************************************/
mbed_official 464:04583941e294 6772 /* */
mbed_official 464:04583941e294 6773 /* Serial Peripheral Interface */
mbed_official 464:04583941e294 6774 /* */
mbed_official 464:04583941e294 6775 /******************************************************************************/
mbed_official 464:04583941e294 6776 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 464:04583941e294 6777 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */
mbed_official 464:04583941e294 6778 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */
mbed_official 464:04583941e294 6779 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */
mbed_official 464:04583941e294 6780
mbed_official 464:04583941e294 6781 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */
mbed_official 464:04583941e294 6782 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 464:04583941e294 6783 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 464:04583941e294 6784 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 464:04583941e294 6785
mbed_official 464:04583941e294 6786 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */
mbed_official 464:04583941e294 6787 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */
mbed_official 464:04583941e294 6788 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */
mbed_official 464:04583941e294 6789 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */
mbed_official 464:04583941e294 6790 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */
mbed_official 464:04583941e294 6791 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!<Data Frame Format */
mbed_official 464:04583941e294 6792 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */
mbed_official 464:04583941e294 6793 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */
mbed_official 464:04583941e294 6794 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */
mbed_official 464:04583941e294 6795 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */
mbed_official 464:04583941e294 6796
mbed_official 464:04583941e294 6797 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 464:04583941e294 6798 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!<Rx Buffer DMA Enable */
mbed_official 464:04583941e294 6799 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!<Tx Buffer DMA Enable */
mbed_official 464:04583941e294 6800 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!<SS Output Enable */
mbed_official 464:04583941e294 6801 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!<Frame Format */
mbed_official 464:04583941e294 6802 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!<Error Interrupt Enable */
mbed_official 464:04583941e294 6803 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!<RX buffer Not Empty Interrupt Enable */
mbed_official 464:04583941e294 6804 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!<Tx buffer Empty Interrupt Enable */
mbed_official 464:04583941e294 6805
mbed_official 464:04583941e294 6806 /******************** Bit definition for SPI_SR register ********************/
mbed_official 464:04583941e294 6807 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!<Receive buffer Not Empty */
mbed_official 464:04583941e294 6808 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!<Transmit buffer Empty */
mbed_official 464:04583941e294 6809 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!<Channel side */
mbed_official 464:04583941e294 6810 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!<Underrun flag */
mbed_official 464:04583941e294 6811 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!<CRC Error flag */
mbed_official 464:04583941e294 6812 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!<Mode fault */
mbed_official 464:04583941e294 6813 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!<Overrun flag */
mbed_official 464:04583941e294 6814 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!<Busy flag */
mbed_official 464:04583941e294 6815 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
mbed_official 464:04583941e294 6816
mbed_official 464:04583941e294 6817 /******************** Bit definition for SPI_DR register ********************/
mbed_official 464:04583941e294 6818 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */
mbed_official 464:04583941e294 6819
mbed_official 464:04583941e294 6820 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 464:04583941e294 6821 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */
mbed_official 464:04583941e294 6822
mbed_official 464:04583941e294 6823 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 464:04583941e294 6824 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */
mbed_official 464:04583941e294 6825
mbed_official 464:04583941e294 6826 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 464:04583941e294 6827 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */
mbed_official 464:04583941e294 6828
mbed_official 464:04583941e294 6829 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 464:04583941e294 6830 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 464:04583941e294 6831
mbed_official 464:04583941e294 6832 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 464:04583941e294 6833 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 464:04583941e294 6834 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 464:04583941e294 6835
mbed_official 464:04583941e294 6836 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 464:04583941e294 6837
mbed_official 464:04583941e294 6838 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 464:04583941e294 6839 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 6840 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 6841
mbed_official 464:04583941e294 6842 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 464:04583941e294 6843
mbed_official 464:04583941e294 6844 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 464:04583941e294 6845 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 464:04583941e294 6846 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 464:04583941e294 6847
mbed_official 464:04583941e294 6848 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 464:04583941e294 6849 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 464:04583941e294 6850
mbed_official 464:04583941e294 6851 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 464:04583941e294 6852 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 464:04583941e294 6853 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 464:04583941e294 6854 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 464:04583941e294 6855
mbed_official 464:04583941e294 6856 /******************************************************************************/
mbed_official 464:04583941e294 6857 /* */
mbed_official 464:04583941e294 6858 /* SYSCFG */
mbed_official 464:04583941e294 6859 /* */
mbed_official 464:04583941e294 6860 /******************************************************************************/
mbed_official 464:04583941e294 6861 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
mbed_official 464:04583941e294 6862 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */
mbed_official 464:04583941e294 6863 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
mbed_official 464:04583941e294 6864 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
mbed_official 464:04583941e294 6865 #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
mbed_official 464:04583941e294 6866
mbed_official 464:04583941e294 6867 #define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */
mbed_official 464:04583941e294 6868 #define SYSCFG_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC memory mapping swap */
mbed_official 464:04583941e294 6869
mbed_official 464:04583941e294 6870 /****************** Bit definition for SYSCFG_PMC register ******************/
mbed_official 464:04583941e294 6871 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 464:04583941e294 6872 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 464:04583941e294 6873 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 464:04583941e294 6874 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
mbed_official 464:04583941e294 6875
mbed_official 464:04583941e294 6876 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
mbed_official 464:04583941e294 6877 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
mbed_official 464:04583941e294 6878 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL
mbed_official 464:04583941e294 6879
mbed_official 464:04583941e294 6880 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 464:04583941e294 6881 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
mbed_official 464:04583941e294 6882 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
mbed_official 464:04583941e294 6883 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
mbed_official 464:04583941e294 6884 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
mbed_official 464:04583941e294 6885 /**
mbed_official 464:04583941e294 6886 * @brief EXTI0 configuration
mbed_official 464:04583941e294 6887 */
mbed_official 464:04583941e294 6888 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
mbed_official 464:04583941e294 6889 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
mbed_official 464:04583941e294 6890 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
mbed_official 464:04583941e294 6891 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
mbed_official 464:04583941e294 6892 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
mbed_official 464:04583941e294 6893 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
mbed_official 464:04583941e294 6894 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
mbed_official 464:04583941e294 6895 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
mbed_official 464:04583941e294 6896 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
mbed_official 464:04583941e294 6897 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
mbed_official 464:04583941e294 6898 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
mbed_official 464:04583941e294 6899
mbed_official 464:04583941e294 6900 /**
mbed_official 464:04583941e294 6901 * @brief EXTI1 configuration
mbed_official 464:04583941e294 6902 */
mbed_official 464:04583941e294 6903 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
mbed_official 464:04583941e294 6904 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
mbed_official 464:04583941e294 6905 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
mbed_official 464:04583941e294 6906 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
mbed_official 464:04583941e294 6907 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
mbed_official 464:04583941e294 6908 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
mbed_official 464:04583941e294 6909 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
mbed_official 464:04583941e294 6910 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
mbed_official 464:04583941e294 6911 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
mbed_official 464:04583941e294 6912 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
mbed_official 464:04583941e294 6913 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
mbed_official 464:04583941e294 6914
mbed_official 464:04583941e294 6915
mbed_official 464:04583941e294 6916 /**
mbed_official 464:04583941e294 6917 * @brief EXTI2 configuration
mbed_official 464:04583941e294 6918 */
mbed_official 464:04583941e294 6919 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
mbed_official 464:04583941e294 6920 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
mbed_official 464:04583941e294 6921 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
mbed_official 464:04583941e294 6922 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
mbed_official 464:04583941e294 6923 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
mbed_official 464:04583941e294 6924 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
mbed_official 464:04583941e294 6925 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
mbed_official 464:04583941e294 6926 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
mbed_official 464:04583941e294 6927 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
mbed_official 464:04583941e294 6928 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
mbed_official 464:04583941e294 6929 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
mbed_official 464:04583941e294 6930
mbed_official 464:04583941e294 6931
mbed_official 464:04583941e294 6932 /**
mbed_official 464:04583941e294 6933 * @brief EXTI3 configuration
mbed_official 464:04583941e294 6934 */
mbed_official 464:04583941e294 6935 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
mbed_official 464:04583941e294 6936 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
mbed_official 464:04583941e294 6937 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
mbed_official 464:04583941e294 6938 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
mbed_official 464:04583941e294 6939 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
mbed_official 464:04583941e294 6940 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
mbed_official 464:04583941e294 6941 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
mbed_official 464:04583941e294 6942 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
mbed_official 464:04583941e294 6943 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
mbed_official 464:04583941e294 6944 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
mbed_official 464:04583941e294 6945 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
mbed_official 464:04583941e294 6946
mbed_official 464:04583941e294 6947
mbed_official 464:04583941e294 6948 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 464:04583941e294 6949 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
mbed_official 464:04583941e294 6950 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
mbed_official 464:04583941e294 6951 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
mbed_official 464:04583941e294 6952 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
mbed_official 464:04583941e294 6953 /**
mbed_official 464:04583941e294 6954 * @brief EXTI4 configuration
mbed_official 464:04583941e294 6955 */
mbed_official 464:04583941e294 6956 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
mbed_official 464:04583941e294 6957 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
mbed_official 464:04583941e294 6958 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
mbed_official 464:04583941e294 6959 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
mbed_official 464:04583941e294 6960 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
mbed_official 464:04583941e294 6961 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
mbed_official 464:04583941e294 6962 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
mbed_official 464:04583941e294 6963 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
mbed_official 464:04583941e294 6964 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
mbed_official 464:04583941e294 6965 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
mbed_official 464:04583941e294 6966 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
mbed_official 464:04583941e294 6967
mbed_official 464:04583941e294 6968 /**
mbed_official 464:04583941e294 6969 * @brief EXTI5 configuration
mbed_official 464:04583941e294 6970 */
mbed_official 464:04583941e294 6971 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
mbed_official 464:04583941e294 6972 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
mbed_official 464:04583941e294 6973 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
mbed_official 464:04583941e294 6974 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
mbed_official 464:04583941e294 6975 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
mbed_official 464:04583941e294 6976 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
mbed_official 464:04583941e294 6977 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
mbed_official 464:04583941e294 6978 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
mbed_official 464:04583941e294 6979 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
mbed_official 464:04583941e294 6980 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
mbed_official 464:04583941e294 6981 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
mbed_official 464:04583941e294 6982
mbed_official 464:04583941e294 6983 /**
mbed_official 464:04583941e294 6984 * @brief EXTI6 configuration
mbed_official 464:04583941e294 6985 */
mbed_official 464:04583941e294 6986 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
mbed_official 464:04583941e294 6987 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
mbed_official 464:04583941e294 6988 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
mbed_official 464:04583941e294 6989 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
mbed_official 464:04583941e294 6990 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
mbed_official 464:04583941e294 6991 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
mbed_official 464:04583941e294 6992 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
mbed_official 464:04583941e294 6993 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
mbed_official 464:04583941e294 6994 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
mbed_official 464:04583941e294 6995 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
mbed_official 464:04583941e294 6996 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
mbed_official 464:04583941e294 6997
mbed_official 464:04583941e294 6998
mbed_official 464:04583941e294 6999 /**
mbed_official 464:04583941e294 7000 * @brief EXTI7 configuration
mbed_official 464:04583941e294 7001 */
mbed_official 464:04583941e294 7002 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
mbed_official 464:04583941e294 7003 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
mbed_official 464:04583941e294 7004 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
mbed_official 464:04583941e294 7005 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
mbed_official 464:04583941e294 7006 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
mbed_official 464:04583941e294 7007 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
mbed_official 464:04583941e294 7008 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
mbed_official 464:04583941e294 7009 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
mbed_official 464:04583941e294 7010 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
mbed_official 464:04583941e294 7011 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
mbed_official 464:04583941e294 7012 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
mbed_official 464:04583941e294 7013
mbed_official 464:04583941e294 7014 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 464:04583941e294 7015 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
mbed_official 464:04583941e294 7016 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
mbed_official 464:04583941e294 7017 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
mbed_official 464:04583941e294 7018 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
mbed_official 464:04583941e294 7019
mbed_official 464:04583941e294 7020 /**
mbed_official 464:04583941e294 7021 * @brief EXTI8 configuration
mbed_official 464:04583941e294 7022 */
mbed_official 464:04583941e294 7023 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
mbed_official 464:04583941e294 7024 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
mbed_official 464:04583941e294 7025 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
mbed_official 464:04583941e294 7026 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
mbed_official 464:04583941e294 7027 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
mbed_official 464:04583941e294 7028 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
mbed_official 464:04583941e294 7029 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
mbed_official 464:04583941e294 7030 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
mbed_official 464:04583941e294 7031 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
mbed_official 464:04583941e294 7032 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
mbed_official 464:04583941e294 7033
mbed_official 464:04583941e294 7034 /**
mbed_official 464:04583941e294 7035 * @brief EXTI9 configuration
mbed_official 464:04583941e294 7036 */
mbed_official 464:04583941e294 7037 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
mbed_official 464:04583941e294 7038 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
mbed_official 464:04583941e294 7039 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
mbed_official 464:04583941e294 7040 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
mbed_official 464:04583941e294 7041 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
mbed_official 464:04583941e294 7042 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
mbed_official 464:04583941e294 7043 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
mbed_official 464:04583941e294 7044 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
mbed_official 464:04583941e294 7045 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
mbed_official 464:04583941e294 7046 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
mbed_official 464:04583941e294 7047
mbed_official 464:04583941e294 7048
mbed_official 464:04583941e294 7049 /**
mbed_official 464:04583941e294 7050 * @brief EXTI10 configuration
mbed_official 464:04583941e294 7051 */
mbed_official 464:04583941e294 7052 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
mbed_official 464:04583941e294 7053 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
mbed_official 464:04583941e294 7054 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
mbed_official 464:04583941e294 7055 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
mbed_official 464:04583941e294 7056 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
mbed_official 464:04583941e294 7057 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
mbed_official 464:04583941e294 7058 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
mbed_official 464:04583941e294 7059 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
mbed_official 464:04583941e294 7060 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
mbed_official 464:04583941e294 7061 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
mbed_official 464:04583941e294 7062
mbed_official 464:04583941e294 7063
mbed_official 464:04583941e294 7064 /**
mbed_official 464:04583941e294 7065 * @brief EXTI11 configuration
mbed_official 464:04583941e294 7066 */
mbed_official 464:04583941e294 7067 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
mbed_official 464:04583941e294 7068 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
mbed_official 464:04583941e294 7069 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
mbed_official 464:04583941e294 7070 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
mbed_official 464:04583941e294 7071 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
mbed_official 464:04583941e294 7072 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
mbed_official 464:04583941e294 7073 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
mbed_official 464:04583941e294 7074 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
mbed_official 464:04583941e294 7075 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
mbed_official 464:04583941e294 7076 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
mbed_official 464:04583941e294 7077
mbed_official 464:04583941e294 7078
mbed_official 464:04583941e294 7079 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
mbed_official 464:04583941e294 7080 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
mbed_official 464:04583941e294 7081 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
mbed_official 464:04583941e294 7082 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
mbed_official 464:04583941e294 7083 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
mbed_official 464:04583941e294 7084 /**
mbed_official 464:04583941e294 7085 * @brief EXTI12 configuration
mbed_official 464:04583941e294 7086 */
mbed_official 464:04583941e294 7087 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
mbed_official 464:04583941e294 7088 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
mbed_official 464:04583941e294 7089 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
mbed_official 464:04583941e294 7090 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
mbed_official 464:04583941e294 7091 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
mbed_official 464:04583941e294 7092 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
mbed_official 464:04583941e294 7093 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
mbed_official 464:04583941e294 7094 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
mbed_official 464:04583941e294 7095 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
mbed_official 464:04583941e294 7096 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
mbed_official 464:04583941e294 7097
mbed_official 464:04583941e294 7098
mbed_official 464:04583941e294 7099 /**
mbed_official 464:04583941e294 7100 * @brief EXTI13 configuration
mbed_official 464:04583941e294 7101 */
mbed_official 464:04583941e294 7102 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
mbed_official 464:04583941e294 7103 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
mbed_official 464:04583941e294 7104 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
mbed_official 464:04583941e294 7105 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
mbed_official 464:04583941e294 7106 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
mbed_official 464:04583941e294 7107 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
mbed_official 464:04583941e294 7108 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
mbed_official 464:04583941e294 7109 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
mbed_official 464:04583941e294 7110 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
mbed_official 464:04583941e294 7111 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
mbed_official 464:04583941e294 7112
mbed_official 464:04583941e294 7113
mbed_official 464:04583941e294 7114 /**
mbed_official 464:04583941e294 7115 * @brief EXTI14 configuration
mbed_official 464:04583941e294 7116 */
mbed_official 464:04583941e294 7117 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
mbed_official 464:04583941e294 7118 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
mbed_official 464:04583941e294 7119 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
mbed_official 464:04583941e294 7120 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
mbed_official 464:04583941e294 7121 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
mbed_official 464:04583941e294 7122 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
mbed_official 464:04583941e294 7123 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
mbed_official 464:04583941e294 7124 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
mbed_official 464:04583941e294 7125 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
mbed_official 464:04583941e294 7126 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
mbed_official 464:04583941e294 7127
mbed_official 464:04583941e294 7128
mbed_official 464:04583941e294 7129 /**
mbed_official 464:04583941e294 7130 * @brief EXTI15 configuration
mbed_official 464:04583941e294 7131 */
mbed_official 464:04583941e294 7132 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
mbed_official 464:04583941e294 7133 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
mbed_official 464:04583941e294 7134 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
mbed_official 464:04583941e294 7135 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
mbed_official 464:04583941e294 7136 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
mbed_official 464:04583941e294 7137 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
mbed_official 464:04583941e294 7138 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
mbed_official 464:04583941e294 7139 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
mbed_official 464:04583941e294 7140 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
mbed_official 464:04583941e294 7141 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
mbed_official 464:04583941e294 7142
mbed_official 464:04583941e294 7143 /****************** Bit definition for SYSCFG_CMPCR register ****************/
mbed_official 464:04583941e294 7144 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */
mbed_official 464:04583941e294 7145 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */
mbed_official 464:04583941e294 7146
mbed_official 464:04583941e294 7147 /******************************************************************************/
mbed_official 464:04583941e294 7148 /* */
mbed_official 464:04583941e294 7149 /* TIM */
mbed_official 464:04583941e294 7150 /* */
mbed_official 464:04583941e294 7151 /******************************************************************************/
mbed_official 464:04583941e294 7152 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 464:04583941e294 7153 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
mbed_official 464:04583941e294 7154 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
mbed_official 464:04583941e294 7155 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
mbed_official 464:04583941e294 7156 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
mbed_official 464:04583941e294 7157 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
mbed_official 464:04583941e294 7158
mbed_official 464:04583941e294 7159 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 464:04583941e294 7160 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
mbed_official 464:04583941e294 7161 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
mbed_official 464:04583941e294 7162
mbed_official 464:04583941e294 7163 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
mbed_official 464:04583941e294 7164
mbed_official 464:04583941e294 7165 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
mbed_official 464:04583941e294 7166 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 464:04583941e294 7167 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 464:04583941e294 7168
mbed_official 464:04583941e294 7169 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 464:04583941e294 7170 #define TIM_CR2_CCPC ((uint32_t)0x0001) /*!<Capture/Compare Preloaded Control */
mbed_official 464:04583941e294 7171 #define TIM_CR2_CCUS ((uint32_t)0x0004) /*!<Capture/Compare Control Update Selection */
mbed_official 464:04583941e294 7172 #define TIM_CR2_CCDS ((uint32_t)0x0008) /*!<Capture/Compare DMA Selection */
mbed_official 464:04583941e294 7173
mbed_official 464:04583941e294 7174 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 464:04583941e294 7175 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 464:04583941e294 7176 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 464:04583941e294 7177 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 464:04583941e294 7178
mbed_official 464:04583941e294 7179 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
mbed_official 464:04583941e294 7180 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 464:04583941e294 7181 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 464:04583941e294 7182 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 464:04583941e294 7183 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 464:04583941e294 7184 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 464:04583941e294 7185 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 464:04583941e294 7186 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 464:04583941e294 7187
mbed_official 464:04583941e294 7188 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 464:04583941e294 7189 #define TIM_SMCR_SMS ((uint32_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 464:04583941e294 7190 #define TIM_SMCR_SMS_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 464:04583941e294 7191 #define TIM_SMCR_SMS_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 464:04583941e294 7192 #define TIM_SMCR_SMS_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 464:04583941e294 7193
mbed_official 464:04583941e294 7194 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 464:04583941e294 7195 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 464:04583941e294 7196 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 464:04583941e294 7197 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 464:04583941e294 7198
mbed_official 464:04583941e294 7199 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
mbed_official 464:04583941e294 7200
mbed_official 464:04583941e294 7201 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 464:04583941e294 7202 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 464:04583941e294 7203 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 464:04583941e294 7204 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 464:04583941e294 7205 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 464:04583941e294 7206
mbed_official 464:04583941e294 7207 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 464:04583941e294 7208 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 464:04583941e294 7209 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 464:04583941e294 7210
mbed_official 464:04583941e294 7211 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
mbed_official 464:04583941e294 7212 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
mbed_official 464:04583941e294 7213
mbed_official 464:04583941e294 7214 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 464:04583941e294 7215 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
mbed_official 464:04583941e294 7216 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 464:04583941e294 7217 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 464:04583941e294 7218 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 464:04583941e294 7219 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 464:04583941e294 7220 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
mbed_official 464:04583941e294 7221 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
mbed_official 464:04583941e294 7222 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
mbed_official 464:04583941e294 7223 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
mbed_official 464:04583941e294 7224 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 464:04583941e294 7225 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 464:04583941e294 7226 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 464:04583941e294 7227 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 464:04583941e294 7228 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
mbed_official 464:04583941e294 7229 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
mbed_official 464:04583941e294 7230
mbed_official 464:04583941e294 7231 /******************** Bit definition for TIM_SR register ********************/
mbed_official 464:04583941e294 7232 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
mbed_official 464:04583941e294 7233 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 464:04583941e294 7234 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 464:04583941e294 7235 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 464:04583941e294 7236 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 464:04583941e294 7237 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
mbed_official 464:04583941e294 7238 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
mbed_official 464:04583941e294 7239 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
mbed_official 464:04583941e294 7240 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 464:04583941e294 7241 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 464:04583941e294 7242 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 464:04583941e294 7243 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 464:04583941e294 7244
mbed_official 464:04583941e294 7245 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 464:04583941e294 7246 #define TIM_EGR_UG ((uint32_t)0x01) /*!<Update Generation */
mbed_official 464:04583941e294 7247 #define TIM_EGR_CC1G ((uint32_t)0x02) /*!<Capture/Compare 1 Generation */
mbed_official 464:04583941e294 7248 #define TIM_EGR_CC2G ((uint32_t)0x04) /*!<Capture/Compare 2 Generation */
mbed_official 464:04583941e294 7249 #define TIM_EGR_CC3G ((uint32_t)0x08) /*!<Capture/Compare 3 Generation */
mbed_official 464:04583941e294 7250 #define TIM_EGR_CC4G ((uint32_t)0x10) /*!<Capture/Compare 4 Generation */
mbed_official 464:04583941e294 7251 #define TIM_EGR_COMG ((uint32_t)0x20) /*!<Capture/Compare Control Update Generation */
mbed_official 464:04583941e294 7252 #define TIM_EGR_TG ((uint32_t)0x40) /*!<Trigger Generation */
mbed_official 464:04583941e294 7253 #define TIM_EGR_BG ((uint32_t)0x80) /*!<Break Generation */
mbed_official 464:04583941e294 7254
mbed_official 464:04583941e294 7255 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 464:04583941e294 7256 #define TIM_CCMR1_CC1S ((uint32_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 464:04583941e294 7257 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 464:04583941e294 7258 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 464:04583941e294 7259
mbed_official 464:04583941e294 7260 #define TIM_CCMR1_OC1FE ((uint32_t)0x0004) /*!<Output Compare 1 Fast enable */
mbed_official 464:04583941e294 7261 #define TIM_CCMR1_OC1PE ((uint32_t)0x0008) /*!<Output Compare 1 Preload enable */
mbed_official 464:04583941e294 7262
mbed_official 464:04583941e294 7263 #define TIM_CCMR1_OC1M ((uint32_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 464:04583941e294 7264 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 464:04583941e294 7265 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 464:04583941e294 7266 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 464:04583941e294 7267
mbed_official 464:04583941e294 7268 #define TIM_CCMR1_OC1CE ((uint32_t)0x0080) /*!<Output Compare 1Clear Enable */
mbed_official 464:04583941e294 7269
mbed_official 464:04583941e294 7270 #define TIM_CCMR1_CC2S ((uint32_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 464:04583941e294 7271 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 464:04583941e294 7272 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 464:04583941e294 7273
mbed_official 464:04583941e294 7274 #define TIM_CCMR1_OC2FE ((uint32_t)0x0400) /*!<Output Compare 2 Fast enable */
mbed_official 464:04583941e294 7275 #define TIM_CCMR1_OC2PE ((uint32_t)0x0800) /*!<Output Compare 2 Preload enable */
mbed_official 464:04583941e294 7276
mbed_official 464:04583941e294 7277 #define TIM_CCMR1_OC2M ((uint32_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 464:04583941e294 7278 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 464:04583941e294 7279 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 464:04583941e294 7280 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 464:04583941e294 7281
mbed_official 464:04583941e294 7282 #define TIM_CCMR1_OC2CE ((uint32_t)0x8000) /*!<Output Compare 2 Clear Enable */
mbed_official 464:04583941e294 7283
mbed_official 464:04583941e294 7284 /*----------------------------------------------------------------------------*/
mbed_official 464:04583941e294 7285
mbed_official 464:04583941e294 7286 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 464:04583941e294 7287 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 464:04583941e294 7288 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 464:04583941e294 7289
mbed_official 464:04583941e294 7290 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 464:04583941e294 7291 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 464:04583941e294 7292 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 464:04583941e294 7293 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 464:04583941e294 7294 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 464:04583941e294 7295
mbed_official 464:04583941e294 7296 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 464:04583941e294 7297 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 464:04583941e294 7298 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 464:04583941e294 7299
mbed_official 464:04583941e294 7300 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 464:04583941e294 7301 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 464:04583941e294 7302 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 464:04583941e294 7303 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 464:04583941e294 7304 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 464:04583941e294 7305
mbed_official 464:04583941e294 7306 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 464:04583941e294 7307 #define TIM_CCMR2_CC3S ((uint32_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 464:04583941e294 7308 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 464:04583941e294 7309 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 464:04583941e294 7310
mbed_official 464:04583941e294 7311 #define TIM_CCMR2_OC3FE ((uint32_t)0x0004) /*!<Output Compare 3 Fast enable */
mbed_official 464:04583941e294 7312 #define TIM_CCMR2_OC3PE ((uint32_t)0x0008) /*!<Output Compare 3 Preload enable */
mbed_official 464:04583941e294 7313
mbed_official 464:04583941e294 7314 #define TIM_CCMR2_OC3M ((uint32_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 464:04583941e294 7315 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 464:04583941e294 7316 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 464:04583941e294 7317 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 464:04583941e294 7318
mbed_official 464:04583941e294 7319 #define TIM_CCMR2_OC3CE ((uint32_t)0x0080) /*!<Output Compare 3 Clear Enable */
mbed_official 464:04583941e294 7320
mbed_official 464:04583941e294 7321 #define TIM_CCMR2_CC4S ((uint32_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 464:04583941e294 7322 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 464:04583941e294 7323 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 464:04583941e294 7324
mbed_official 464:04583941e294 7325 #define TIM_CCMR2_OC4FE ((uint32_t)0x0400) /*!<Output Compare 4 Fast enable */
mbed_official 464:04583941e294 7326 #define TIM_CCMR2_OC4PE ((uint32_t)0x0800) /*!<Output Compare 4 Preload enable */
mbed_official 464:04583941e294 7327
mbed_official 464:04583941e294 7328 #define TIM_CCMR2_OC4M ((uint32_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 464:04583941e294 7329 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 464:04583941e294 7330 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 464:04583941e294 7331 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 464:04583941e294 7332
mbed_official 464:04583941e294 7333 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
mbed_official 464:04583941e294 7334
mbed_official 464:04583941e294 7335 /*----------------------------------------------------------------------------*/
mbed_official 464:04583941e294 7336
mbed_official 464:04583941e294 7337 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 464:04583941e294 7338 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
mbed_official 464:04583941e294 7339 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
mbed_official 464:04583941e294 7340
mbed_official 464:04583941e294 7341 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 464:04583941e294 7342 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
mbed_official 464:04583941e294 7343 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
mbed_official 464:04583941e294 7344 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
mbed_official 464:04583941e294 7345 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
mbed_official 464:04583941e294 7346
mbed_official 464:04583941e294 7347 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 464:04583941e294 7348 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 464:04583941e294 7349 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 464:04583941e294 7350
mbed_official 464:04583941e294 7351 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 464:04583941e294 7352 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 464:04583941e294 7353 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 464:04583941e294 7354 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
mbed_official 464:04583941e294 7355 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
mbed_official 464:04583941e294 7356
mbed_official 464:04583941e294 7357 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 464:04583941e294 7358 #define TIM_CCER_CC1E ((uint32_t)0x0001) /*!<Capture/Compare 1 output enable */
mbed_official 464:04583941e294 7359 #define TIM_CCER_CC1P ((uint32_t)0x0002) /*!<Capture/Compare 1 output Polarity */
mbed_official 464:04583941e294 7360 #define TIM_CCER_CC1NE ((uint32_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 464:04583941e294 7361 #define TIM_CCER_CC1NP ((uint32_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 464:04583941e294 7362 #define TIM_CCER_CC2E ((uint32_t)0x0010) /*!<Capture/Compare 2 output enable */
mbed_official 464:04583941e294 7363 #define TIM_CCER_CC2P ((uint32_t)0x0020) /*!<Capture/Compare 2 output Polarity */
mbed_official 464:04583941e294 7364 #define TIM_CCER_CC2NE ((uint32_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 464:04583941e294 7365 #define TIM_CCER_CC2NP ((uint32_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 464:04583941e294 7366 #define TIM_CCER_CC3E ((uint32_t)0x0100) /*!<Capture/Compare 3 output enable */
mbed_official 464:04583941e294 7367 #define TIM_CCER_CC3P ((uint32_t)0x0200) /*!<Capture/Compare 3 output Polarity */
mbed_official 464:04583941e294 7368 #define TIM_CCER_CC3NE ((uint32_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 464:04583941e294 7369 #define TIM_CCER_CC3NP ((uint32_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 464:04583941e294 7370 #define TIM_CCER_CC4E ((uint32_t)0x1000) /*!<Capture/Compare 4 output enable */
mbed_official 464:04583941e294 7371 #define TIM_CCER_CC4P ((uint32_t)0x2000) /*!<Capture/Compare 4 output Polarity */
mbed_official 464:04583941e294 7372 #define TIM_CCER_CC4NP ((uint32_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 464:04583941e294 7373
mbed_official 464:04583941e294 7374 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 464:04583941e294 7375 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
mbed_official 464:04583941e294 7376
mbed_official 464:04583941e294 7377 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 464:04583941e294 7378 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
mbed_official 464:04583941e294 7379
mbed_official 464:04583941e294 7380 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 464:04583941e294 7381 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
mbed_official 464:04583941e294 7382
mbed_official 464:04583941e294 7383 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 464:04583941e294 7384 #define TIM_RCR_REP ((uint32_t)0xFF) /*!<Repetition Counter Value */
mbed_official 464:04583941e294 7385
mbed_official 464:04583941e294 7386 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 464:04583941e294 7387 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
mbed_official 464:04583941e294 7388
mbed_official 464:04583941e294 7389 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 464:04583941e294 7390 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
mbed_official 464:04583941e294 7391
mbed_official 464:04583941e294 7392 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 464:04583941e294 7393 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
mbed_official 464:04583941e294 7394
mbed_official 464:04583941e294 7395 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 464:04583941e294 7396 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
mbed_official 464:04583941e294 7397
mbed_official 464:04583941e294 7398 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 464:04583941e294 7399 #define TIM_BDTR_DTG ((uint32_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 464:04583941e294 7400 #define TIM_BDTR_DTG_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 464:04583941e294 7401 #define TIM_BDTR_DTG_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 464:04583941e294 7402 #define TIM_BDTR_DTG_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 464:04583941e294 7403 #define TIM_BDTR_DTG_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 464:04583941e294 7404 #define TIM_BDTR_DTG_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 464:04583941e294 7405 #define TIM_BDTR_DTG_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 464:04583941e294 7406 #define TIM_BDTR_DTG_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 464:04583941e294 7407 #define TIM_BDTR_DTG_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 464:04583941e294 7408
mbed_official 464:04583941e294 7409 #define TIM_BDTR_LOCK ((uint32_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 464:04583941e294 7410 #define TIM_BDTR_LOCK_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 464:04583941e294 7411 #define TIM_BDTR_LOCK_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 464:04583941e294 7412
mbed_official 464:04583941e294 7413 #define TIM_BDTR_OSSI ((uint32_t)0x0400) /*!<Off-State Selection for Idle mode */
mbed_official 464:04583941e294 7414 #define TIM_BDTR_OSSR ((uint32_t)0x0800) /*!<Off-State Selection for Run mode */
mbed_official 464:04583941e294 7415 #define TIM_BDTR_BKE ((uint32_t)0x1000) /*!<Break enable */
mbed_official 464:04583941e294 7416 #define TIM_BDTR_BKP ((uint32_t)0x2000) /*!<Break Polarity */
mbed_official 464:04583941e294 7417 #define TIM_BDTR_AOE ((uint32_t)0x4000) /*!<Automatic Output enable */
mbed_official 464:04583941e294 7418 #define TIM_BDTR_MOE ((uint32_t)0x8000) /*!<Main Output enable */
mbed_official 464:04583941e294 7419
mbed_official 464:04583941e294 7420 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 464:04583941e294 7421 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 464:04583941e294 7422 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 464:04583941e294 7423 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 464:04583941e294 7424 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 464:04583941e294 7425 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 464:04583941e294 7426 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 464:04583941e294 7427
mbed_official 464:04583941e294 7428 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 464:04583941e294 7429 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
mbed_official 464:04583941e294 7430 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
mbed_official 464:04583941e294 7431 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
mbed_official 464:04583941e294 7432 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
mbed_official 464:04583941e294 7433 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
mbed_official 464:04583941e294 7434
mbed_official 464:04583941e294 7435 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 464:04583941e294 7436 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
mbed_official 464:04583941e294 7437
mbed_official 464:04583941e294 7438 /******************* Bit definition for TIM_OR register *********************/
mbed_official 464:04583941e294 7439 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
mbed_official 464:04583941e294 7440 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
mbed_official 464:04583941e294 7441 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
mbed_official 464:04583941e294 7442 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
mbed_official 464:04583941e294 7443 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
mbed_official 464:04583941e294 7444 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
mbed_official 464:04583941e294 7445
mbed_official 464:04583941e294 7446
mbed_official 464:04583941e294 7447 /******************************************************************************/
mbed_official 464:04583941e294 7448 /* */
mbed_official 464:04583941e294 7449 /* Universal Synchronous Asynchronous Receiver Transmitter */
mbed_official 464:04583941e294 7450 /* */
mbed_official 464:04583941e294 7451 /******************************************************************************/
mbed_official 464:04583941e294 7452 /******************* Bit definition for USART_SR register *******************/
mbed_official 464:04583941e294 7453 #define USART_SR_PE ((uint32_t)0x0001) /*!<Parity Error */
mbed_official 464:04583941e294 7454 #define USART_SR_FE ((uint32_t)0x0002) /*!<Framing Error */
mbed_official 464:04583941e294 7455 #define USART_SR_NE ((uint32_t)0x0004) /*!<Noise Error Flag */
mbed_official 464:04583941e294 7456 #define USART_SR_ORE ((uint32_t)0x0008) /*!<OverRun Error */
mbed_official 464:04583941e294 7457 #define USART_SR_IDLE ((uint32_t)0x0010) /*!<IDLE line detected */
mbed_official 464:04583941e294 7458 #define USART_SR_RXNE ((uint32_t)0x0020) /*!<Read Data Register Not Empty */
mbed_official 464:04583941e294 7459 #define USART_SR_TC ((uint32_t)0x0040) /*!<Transmission Complete */
mbed_official 464:04583941e294 7460 #define USART_SR_TXE ((uint32_t)0x0080) /*!<Transmit Data Register Empty */
mbed_official 464:04583941e294 7461 #define USART_SR_LBD ((uint32_t)0x0100) /*!<LIN Break Detection Flag */
mbed_official 464:04583941e294 7462 #define USART_SR_CTS ((uint32_t)0x0200) /*!<CTS Flag */
mbed_official 464:04583941e294 7463
mbed_official 464:04583941e294 7464 /******************* Bit definition for USART_DR register *******************/
mbed_official 464:04583941e294 7465 #define USART_DR_DR ((uint32_t)0x01FF) /*!<Data value */
mbed_official 464:04583941e294 7466
mbed_official 464:04583941e294 7467 /****************** Bit definition for USART_BRR register *******************/
mbed_official 464:04583941e294 7468 #define USART_BRR_DIV_Fraction ((uint32_t)0x000F) /*!<Fraction of USARTDIV */
mbed_official 464:04583941e294 7469 #define USART_BRR_DIV_Mantissa ((uint32_t)0xFFF0) /*!<Mantissa of USARTDIV */
mbed_official 464:04583941e294 7470
mbed_official 464:04583941e294 7471 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 464:04583941e294 7472 #define USART_CR1_SBK ((uint32_t)0x0001) /*!<Send Break */
mbed_official 464:04583941e294 7473 #define USART_CR1_RWU ((uint32_t)0x0002) /*!<Receiver wakeup */
mbed_official 464:04583941e294 7474 #define USART_CR1_RE ((uint32_t)0x0004) /*!<Receiver Enable */
mbed_official 464:04583941e294 7475 #define USART_CR1_TE ((uint32_t)0x0008) /*!<Transmitter Enable */
mbed_official 464:04583941e294 7476 #define USART_CR1_IDLEIE ((uint32_t)0x0010) /*!<IDLE Interrupt Enable */
mbed_official 464:04583941e294 7477 #define USART_CR1_RXNEIE ((uint32_t)0x0020) /*!<RXNE Interrupt Enable */
mbed_official 464:04583941e294 7478 #define USART_CR1_TCIE ((uint32_t)0x0040) /*!<Transmission Complete Interrupt Enable */
mbed_official 464:04583941e294 7479 #define USART_CR1_TXEIE ((uint32_t)0x0080) /*!<PE Interrupt Enable */
mbed_official 464:04583941e294 7480 #define USART_CR1_PEIE ((uint32_t)0x0100) /*!<PE Interrupt Enable */
mbed_official 464:04583941e294 7481 #define USART_CR1_PS ((uint32_t)0x0200) /*!<Parity Selection */
mbed_official 464:04583941e294 7482 #define USART_CR1_PCE ((uint32_t)0x0400) /*!<Parity Control Enable */
mbed_official 464:04583941e294 7483 #define USART_CR1_WAKE ((uint32_t)0x0800) /*!<Wakeup method */
mbed_official 464:04583941e294 7484 #define USART_CR1_M ((uint32_t)0x1000) /*!<Word length */
mbed_official 464:04583941e294 7485 #define USART_CR1_UE ((uint32_t)0x2000) /*!<USART Enable */
mbed_official 464:04583941e294 7486 #define USART_CR1_OVER8 ((uint32_t)0x8000) /*!<USART Oversampling by 8 enable */
mbed_official 464:04583941e294 7487
mbed_official 464:04583941e294 7488 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 464:04583941e294 7489 #define USART_CR2_ADD ((uint32_t)0x000F) /*!<Address of the USART node */
mbed_official 464:04583941e294 7490 #define USART_CR2_LBDL ((uint32_t)0x0020) /*!<LIN Break Detection Length */
mbed_official 464:04583941e294 7491 #define USART_CR2_LBDIE ((uint32_t)0x0040) /*!<LIN Break Detection Interrupt Enable */
mbed_official 464:04583941e294 7492 #define USART_CR2_LBCL ((uint32_t)0x0100) /*!<Last Bit Clock pulse */
mbed_official 464:04583941e294 7493 #define USART_CR2_CPHA ((uint32_t)0x0200) /*!<Clock Phase */
mbed_official 464:04583941e294 7494 #define USART_CR2_CPOL ((uint32_t)0x0400) /*!<Clock Polarity */
mbed_official 464:04583941e294 7495 #define USART_CR2_CLKEN ((uint32_t)0x0800) /*!<Clock Enable */
mbed_official 464:04583941e294 7496
mbed_official 464:04583941e294 7497 #define USART_CR2_STOP ((uint32_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */
mbed_official 464:04583941e294 7498 #define USART_CR2_STOP_0 ((uint32_t)0x1000) /*!<Bit 0 */
mbed_official 464:04583941e294 7499 #define USART_CR2_STOP_1 ((uint32_t)0x2000) /*!<Bit 1 */
mbed_official 464:04583941e294 7500
mbed_official 464:04583941e294 7501 #define USART_CR2_LINEN ((uint32_t)0x4000) /*!<LIN mode enable */
mbed_official 464:04583941e294 7502
mbed_official 464:04583941e294 7503 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 464:04583941e294 7504 #define USART_CR3_EIE ((uint32_t)0x0001) /*!<Error Interrupt Enable */
mbed_official 464:04583941e294 7505 #define USART_CR3_IREN ((uint32_t)0x0002) /*!<IrDA mode Enable */
mbed_official 464:04583941e294 7506 #define USART_CR3_IRLP ((uint32_t)0x0004) /*!<IrDA Low-Power */
mbed_official 464:04583941e294 7507 #define USART_CR3_HDSEL ((uint32_t)0x0008) /*!<Half-Duplex Selection */
mbed_official 464:04583941e294 7508 #define USART_CR3_NACK ((uint32_t)0x0010) /*!<Smartcard NACK enable */
mbed_official 464:04583941e294 7509 #define USART_CR3_SCEN ((uint32_t)0x0020) /*!<Smartcard mode enable */
mbed_official 464:04583941e294 7510 #define USART_CR3_DMAR ((uint32_t)0x0040) /*!<DMA Enable Receiver */
mbed_official 464:04583941e294 7511 #define USART_CR3_DMAT ((uint32_t)0x0080) /*!<DMA Enable Transmitter */
mbed_official 464:04583941e294 7512 #define USART_CR3_RTSE ((uint32_t)0x0100) /*!<RTS Enable */
mbed_official 464:04583941e294 7513 #define USART_CR3_CTSE ((uint32_t)0x0200) /*!<CTS Enable */
mbed_official 464:04583941e294 7514 #define USART_CR3_CTSIE ((uint32_t)0x0400) /*!<CTS Interrupt Enable */
mbed_official 464:04583941e294 7515 #define USART_CR3_ONEBIT ((uint32_t)0x0800) /*!<USART One bit method enable */
mbed_official 464:04583941e294 7516
mbed_official 464:04583941e294 7517 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 464:04583941e294 7518 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
mbed_official 464:04583941e294 7519 #define USART_GTPR_PSC_0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 464:04583941e294 7520 #define USART_GTPR_PSC_1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 464:04583941e294 7521 #define USART_GTPR_PSC_2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 464:04583941e294 7522 #define USART_GTPR_PSC_3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 464:04583941e294 7523 #define USART_GTPR_PSC_4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 464:04583941e294 7524 #define USART_GTPR_PSC_5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 464:04583941e294 7525 #define USART_GTPR_PSC_6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 464:04583941e294 7526 #define USART_GTPR_PSC_7 ((uint32_t)0x0080) /*!<Bit 7 */
mbed_official 464:04583941e294 7527
mbed_official 464:04583941e294 7528 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!<Guard time value */
mbed_official 464:04583941e294 7529
mbed_official 464:04583941e294 7530 /******************************************************************************/
mbed_official 464:04583941e294 7531 /* */
mbed_official 464:04583941e294 7532 /* Window WATCHDOG */
mbed_official 464:04583941e294 7533 /* */
mbed_official 464:04583941e294 7534 /******************************************************************************/
mbed_official 464:04583941e294 7535 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 464:04583941e294 7536 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 464:04583941e294 7537 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 464:04583941e294 7538 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 464:04583941e294 7539 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 464:04583941e294 7540 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 464:04583941e294 7541 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 464:04583941e294 7542 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 464:04583941e294 7543 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 464:04583941e294 7544
mbed_official 464:04583941e294 7545 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 464:04583941e294 7546
mbed_official 464:04583941e294 7547 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 464:04583941e294 7548 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 464:04583941e294 7549 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 464:04583941e294 7550 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 464:04583941e294 7551 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 464:04583941e294 7552 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 464:04583941e294 7553 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 464:04583941e294 7554 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 464:04583941e294 7555 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 464:04583941e294 7556
mbed_official 464:04583941e294 7557 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 464:04583941e294 7558 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 464:04583941e294 7559 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 464:04583941e294 7560
mbed_official 464:04583941e294 7561 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 464:04583941e294 7562
mbed_official 464:04583941e294 7563 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 464:04583941e294 7564 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 464:04583941e294 7565
mbed_official 464:04583941e294 7566
mbed_official 464:04583941e294 7567 /******************************************************************************/
mbed_official 464:04583941e294 7568 /* */
mbed_official 464:04583941e294 7569 /* DBG */
mbed_official 464:04583941e294 7570 /* */
mbed_official 464:04583941e294 7571 /******************************************************************************/
mbed_official 464:04583941e294 7572 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 464:04583941e294 7573 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 464:04583941e294 7574 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 464:04583941e294 7575
mbed_official 464:04583941e294 7576 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 464:04583941e294 7577 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 464:04583941e294 7578 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 464:04583941e294 7579 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 464:04583941e294 7580 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 464:04583941e294 7581
mbed_official 464:04583941e294 7582 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 464:04583941e294 7583 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
mbed_official 464:04583941e294 7584 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
mbed_official 464:04583941e294 7585
mbed_official 464:04583941e294 7586 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 464:04583941e294 7587 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
mbed_official 464:04583941e294 7588 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
mbed_official 464:04583941e294 7589 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
mbed_official 464:04583941e294 7590 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
mbed_official 464:04583941e294 7591 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 464:04583941e294 7592 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
mbed_official 464:04583941e294 7593 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
mbed_official 464:04583941e294 7594 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
mbed_official 464:04583941e294 7595 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
mbed_official 464:04583941e294 7596 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 464:04583941e294 7597 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 464:04583941e294 7598 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 464:04583941e294 7599 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 464:04583941e294 7600 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
mbed_official 464:04583941e294 7601 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
mbed_official 464:04583941e294 7602 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
mbed_official 464:04583941e294 7603 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
mbed_official 464:04583941e294 7604 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
mbed_official 464:04583941e294 7605 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
mbed_official 464:04583941e294 7606
mbed_official 464:04583941e294 7607 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 464:04583941e294 7608 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 464:04583941e294 7609 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
mbed_official 464:04583941e294 7610 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
mbed_official 464:04583941e294 7611 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
mbed_official 464:04583941e294 7612 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
mbed_official 464:04583941e294 7613
mbed_official 464:04583941e294 7614 /******************************************************************************/
mbed_official 464:04583941e294 7615 /* */
mbed_official 464:04583941e294 7616 /* Ethernet MAC Registers bits definitions */
mbed_official 464:04583941e294 7617 /* */
mbed_official 464:04583941e294 7618 /******************************************************************************/
mbed_official 464:04583941e294 7619 /* Bit definition for Ethernet MAC Control Register register */
mbed_official 464:04583941e294 7620 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
mbed_official 464:04583941e294 7621 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
mbed_official 464:04583941e294 7622 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
mbed_official 464:04583941e294 7623 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
mbed_official 464:04583941e294 7624 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
mbed_official 464:04583941e294 7625 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
mbed_official 464:04583941e294 7626 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
mbed_official 464:04583941e294 7627 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
mbed_official 464:04583941e294 7628 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
mbed_official 464:04583941e294 7629 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
mbed_official 464:04583941e294 7630 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
mbed_official 464:04583941e294 7631 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
mbed_official 464:04583941e294 7632 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
mbed_official 464:04583941e294 7633 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
mbed_official 464:04583941e294 7634 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
mbed_official 464:04583941e294 7635 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
mbed_official 464:04583941e294 7636 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
mbed_official 464:04583941e294 7637 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
mbed_official 464:04583941e294 7638 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
mbed_official 464:04583941e294 7639 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
mbed_official 464:04583941e294 7640 a transmission attempt during retries after a collision: 0 =< r <2^k */
mbed_official 464:04583941e294 7641 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
mbed_official 464:04583941e294 7642 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
mbed_official 464:04583941e294 7643 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
mbed_official 464:04583941e294 7644 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
mbed_official 464:04583941e294 7645 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
mbed_official 464:04583941e294 7646 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
mbed_official 464:04583941e294 7647 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
mbed_official 464:04583941e294 7648
mbed_official 464:04583941e294 7649 /* Bit definition for Ethernet MAC Frame Filter Register */
mbed_official 464:04583941e294 7650 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
mbed_official 464:04583941e294 7651 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
mbed_official 464:04583941e294 7652 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
mbed_official 464:04583941e294 7653 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
mbed_official 464:04583941e294 7654 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
mbed_official 464:04583941e294 7655 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
mbed_official 464:04583941e294 7656 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
mbed_official 464:04583941e294 7657 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
mbed_official 464:04583941e294 7658 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
mbed_official 464:04583941e294 7659 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
mbed_official 464:04583941e294 7660 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
mbed_official 464:04583941e294 7661 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
mbed_official 464:04583941e294 7662 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
mbed_official 464:04583941e294 7663 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
mbed_official 464:04583941e294 7664
mbed_official 464:04583941e294 7665 /* Bit definition for Ethernet MAC Hash Table High Register */
mbed_official 464:04583941e294 7666 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
mbed_official 464:04583941e294 7667
mbed_official 464:04583941e294 7668 /* Bit definition for Ethernet MAC Hash Table Low Register */
mbed_official 464:04583941e294 7669 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
mbed_official 464:04583941e294 7670
mbed_official 464:04583941e294 7671 /* Bit definition for Ethernet MAC MII Address Register */
mbed_official 464:04583941e294 7672 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
mbed_official 464:04583941e294 7673 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
mbed_official 464:04583941e294 7674 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
mbed_official 464:04583941e294 7675 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
mbed_official 464:04583941e294 7676 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
mbed_official 464:04583941e294 7677 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
mbed_official 464:04583941e294 7678 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
mbed_official 464:04583941e294 7679 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
mbed_official 464:04583941e294 7680 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
mbed_official 464:04583941e294 7681 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
mbed_official 464:04583941e294 7682
mbed_official 464:04583941e294 7683 /* Bit definition for Ethernet MAC MII Data Register */
mbed_official 464:04583941e294 7684 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
mbed_official 464:04583941e294 7685
mbed_official 464:04583941e294 7686 /* Bit definition for Ethernet MAC Flow Control Register */
mbed_official 464:04583941e294 7687 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
mbed_official 464:04583941e294 7688 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
mbed_official 464:04583941e294 7689 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
mbed_official 464:04583941e294 7690 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
mbed_official 464:04583941e294 7691 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
mbed_official 464:04583941e294 7692 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
mbed_official 464:04583941e294 7693 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
mbed_official 464:04583941e294 7694 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
mbed_official 464:04583941e294 7695 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
mbed_official 464:04583941e294 7696 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
mbed_official 464:04583941e294 7697 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
mbed_official 464:04583941e294 7698
mbed_official 464:04583941e294 7699 /* Bit definition for Ethernet MAC VLAN Tag Register */
mbed_official 464:04583941e294 7700 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
mbed_official 464:04583941e294 7701 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
mbed_official 464:04583941e294 7702
mbed_official 464:04583941e294 7703 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
mbed_official 464:04583941e294 7704 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
mbed_official 464:04583941e294 7705 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
mbed_official 464:04583941e294 7706 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
mbed_official 464:04583941e294 7707 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
mbed_official 464:04583941e294 7708 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
mbed_official 464:04583941e294 7709 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
mbed_official 464:04583941e294 7710 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
mbed_official 464:04583941e294 7711 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
mbed_official 464:04583941e294 7712 RSVD - Filter1 Command - RSVD - Filter0 Command
mbed_official 464:04583941e294 7713 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
mbed_official 464:04583941e294 7714 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
mbed_official 464:04583941e294 7715 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
mbed_official 464:04583941e294 7716
mbed_official 464:04583941e294 7717 /* Bit definition for Ethernet MAC PMT Control and Status Register */
mbed_official 464:04583941e294 7718 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
mbed_official 464:04583941e294 7719 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
mbed_official 464:04583941e294 7720 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
mbed_official 464:04583941e294 7721 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
mbed_official 464:04583941e294 7722 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
mbed_official 464:04583941e294 7723 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
mbed_official 464:04583941e294 7724 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
mbed_official 464:04583941e294 7725
mbed_official 464:04583941e294 7726 /* Bit definition for Ethernet MAC Status Register */
mbed_official 464:04583941e294 7727 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
mbed_official 464:04583941e294 7728 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
mbed_official 464:04583941e294 7729 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
mbed_official 464:04583941e294 7730 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
mbed_official 464:04583941e294 7731 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
mbed_official 464:04583941e294 7732
mbed_official 464:04583941e294 7733 /* Bit definition for Ethernet MAC Interrupt Mask Register */
mbed_official 464:04583941e294 7734 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
mbed_official 464:04583941e294 7735 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
mbed_official 464:04583941e294 7736
mbed_official 464:04583941e294 7737 /* Bit definition for Ethernet MAC Address0 High Register */
mbed_official 464:04583941e294 7738 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
mbed_official 464:04583941e294 7739
mbed_official 464:04583941e294 7740 /* Bit definition for Ethernet MAC Address0 Low Register */
mbed_official 464:04583941e294 7741 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
mbed_official 464:04583941e294 7742
mbed_official 464:04583941e294 7743 /* Bit definition for Ethernet MAC Address1 High Register */
mbed_official 464:04583941e294 7744 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
mbed_official 464:04583941e294 7745 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
mbed_official 464:04583941e294 7746 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
mbed_official 464:04583941e294 7747 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
mbed_official 464:04583941e294 7748 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
mbed_official 464:04583941e294 7749 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
mbed_official 464:04583941e294 7750 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
mbed_official 464:04583941e294 7751 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
mbed_official 464:04583941e294 7752 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
mbed_official 464:04583941e294 7753 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
mbed_official 464:04583941e294 7754
mbed_official 464:04583941e294 7755 /* Bit definition for Ethernet MAC Address1 Low Register */
mbed_official 464:04583941e294 7756 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
mbed_official 464:04583941e294 7757
mbed_official 464:04583941e294 7758 /* Bit definition for Ethernet MAC Address2 High Register */
mbed_official 464:04583941e294 7759 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
mbed_official 464:04583941e294 7760 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
mbed_official 464:04583941e294 7761 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
mbed_official 464:04583941e294 7762 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
mbed_official 464:04583941e294 7763 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
mbed_official 464:04583941e294 7764 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
mbed_official 464:04583941e294 7765 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
mbed_official 464:04583941e294 7766 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
mbed_official 464:04583941e294 7767 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
mbed_official 464:04583941e294 7768 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
mbed_official 464:04583941e294 7769
mbed_official 464:04583941e294 7770 /* Bit definition for Ethernet MAC Address2 Low Register */
mbed_official 464:04583941e294 7771 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
mbed_official 464:04583941e294 7772
mbed_official 464:04583941e294 7773 /* Bit definition for Ethernet MAC Address3 High Register */
mbed_official 464:04583941e294 7774 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
mbed_official 464:04583941e294 7775 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
mbed_official 464:04583941e294 7776 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
mbed_official 464:04583941e294 7777 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
mbed_official 464:04583941e294 7778 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
mbed_official 464:04583941e294 7779 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
mbed_official 464:04583941e294 7780 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
mbed_official 464:04583941e294 7781 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
mbed_official 464:04583941e294 7782 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
mbed_official 464:04583941e294 7783 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
mbed_official 464:04583941e294 7784
mbed_official 464:04583941e294 7785 /* Bit definition for Ethernet MAC Address3 Low Register */
mbed_official 464:04583941e294 7786 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
mbed_official 464:04583941e294 7787
mbed_official 464:04583941e294 7788 /******************************************************************************/
mbed_official 464:04583941e294 7789 /* Ethernet MMC Registers bits definition */
mbed_official 464:04583941e294 7790 /******************************************************************************/
mbed_official 464:04583941e294 7791
mbed_official 464:04583941e294 7792 /* Bit definition for Ethernet MMC Contol Register */
mbed_official 464:04583941e294 7793 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
mbed_official 464:04583941e294 7794 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
mbed_official 464:04583941e294 7795 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
mbed_official 464:04583941e294 7796 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
mbed_official 464:04583941e294 7797 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
mbed_official 464:04583941e294 7798 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
mbed_official 464:04583941e294 7799
mbed_official 464:04583941e294 7800 /* Bit definition for Ethernet MMC Receive Interrupt Register */
mbed_official 464:04583941e294 7801 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
mbed_official 464:04583941e294 7802 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
mbed_official 464:04583941e294 7803 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
mbed_official 464:04583941e294 7804
mbed_official 464:04583941e294 7805 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
mbed_official 464:04583941e294 7806 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
mbed_official 464:04583941e294 7807 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
mbed_official 464:04583941e294 7808 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
mbed_official 464:04583941e294 7809
mbed_official 464:04583941e294 7810 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
mbed_official 464:04583941e294 7811 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
mbed_official 464:04583941e294 7812 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
mbed_official 464:04583941e294 7813 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
mbed_official 464:04583941e294 7814
mbed_official 464:04583941e294 7815 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
mbed_official 464:04583941e294 7816 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
mbed_official 464:04583941e294 7817 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
mbed_official 464:04583941e294 7818 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
mbed_official 464:04583941e294 7819
mbed_official 464:04583941e294 7820 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
mbed_official 464:04583941e294 7821 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
mbed_official 464:04583941e294 7822
mbed_official 464:04583941e294 7823 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
mbed_official 464:04583941e294 7824 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
mbed_official 464:04583941e294 7825
mbed_official 464:04583941e294 7826 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
mbed_official 464:04583941e294 7827 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
mbed_official 464:04583941e294 7828
mbed_official 464:04583941e294 7829 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
mbed_official 464:04583941e294 7830 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
mbed_official 464:04583941e294 7831
mbed_official 464:04583941e294 7832 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
mbed_official 464:04583941e294 7833 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
mbed_official 464:04583941e294 7834
mbed_official 464:04583941e294 7835 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
mbed_official 464:04583941e294 7836 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
mbed_official 464:04583941e294 7837
mbed_official 464:04583941e294 7838 /******************************************************************************/
mbed_official 464:04583941e294 7839 /* Ethernet PTP Registers bits definition */
mbed_official 464:04583941e294 7840 /******************************************************************************/
mbed_official 464:04583941e294 7841
mbed_official 464:04583941e294 7842 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
mbed_official 464:04583941e294 7843 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
mbed_official 464:04583941e294 7844 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
mbed_official 464:04583941e294 7845 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
mbed_official 464:04583941e294 7846 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
mbed_official 464:04583941e294 7847 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
mbed_official 464:04583941e294 7848 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
mbed_official 464:04583941e294 7849 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
mbed_official 464:04583941e294 7850 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
mbed_official 464:04583941e294 7851 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
mbed_official 464:04583941e294 7852
mbed_official 464:04583941e294 7853 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
mbed_official 464:04583941e294 7854 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
mbed_official 464:04583941e294 7855 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
mbed_official 464:04583941e294 7856 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
mbed_official 464:04583941e294 7857 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
mbed_official 464:04583941e294 7858 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
mbed_official 464:04583941e294 7859
mbed_official 464:04583941e294 7860 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
mbed_official 464:04583941e294 7861 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
mbed_official 464:04583941e294 7862
mbed_official 464:04583941e294 7863 /* Bit definition for Ethernet PTP Time Stamp High Register */
mbed_official 464:04583941e294 7864 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
mbed_official 464:04583941e294 7865
mbed_official 464:04583941e294 7866 /* Bit definition for Ethernet PTP Time Stamp Low Register */
mbed_official 464:04583941e294 7867 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
mbed_official 464:04583941e294 7868 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
mbed_official 464:04583941e294 7869
mbed_official 464:04583941e294 7870 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
mbed_official 464:04583941e294 7871 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
mbed_official 464:04583941e294 7872
mbed_official 464:04583941e294 7873 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
mbed_official 464:04583941e294 7874 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
mbed_official 464:04583941e294 7875 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
mbed_official 464:04583941e294 7876
mbed_official 464:04583941e294 7877 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
mbed_official 464:04583941e294 7878 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
mbed_official 464:04583941e294 7879
mbed_official 464:04583941e294 7880 /* Bit definition for Ethernet PTP Target Time High Register */
mbed_official 464:04583941e294 7881 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
mbed_official 464:04583941e294 7882
mbed_official 464:04583941e294 7883 /* Bit definition for Ethernet PTP Target Time Low Register */
mbed_official 464:04583941e294 7884 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
mbed_official 464:04583941e294 7885
mbed_official 464:04583941e294 7886 /* Bit definition for Ethernet PTP Time Stamp Status Register */
mbed_official 464:04583941e294 7887 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
mbed_official 464:04583941e294 7888 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
mbed_official 464:04583941e294 7889
mbed_official 464:04583941e294 7890 /******************************************************************************/
mbed_official 464:04583941e294 7891 /* Ethernet DMA Registers bits definition */
mbed_official 464:04583941e294 7892 /******************************************************************************/
mbed_official 464:04583941e294 7893
mbed_official 464:04583941e294 7894 /* Bit definition for Ethernet DMA Bus Mode Register */
mbed_official 464:04583941e294 7895 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
mbed_official 464:04583941e294 7896 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
mbed_official 464:04583941e294 7897 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
mbed_official 464:04583941e294 7898 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
mbed_official 464:04583941e294 7899 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
mbed_official 464:04583941e294 7900 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
mbed_official 464:04583941e294 7901 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 464:04583941e294 7902 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 464:04583941e294 7903 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 464:04583941e294 7904 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 464:04583941e294 7905 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 464:04583941e294 7906 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 464:04583941e294 7907 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 464:04583941e294 7908 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 464:04583941e294 7909 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
mbed_official 464:04583941e294 7910 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
mbed_official 464:04583941e294 7911 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
mbed_official 464:04583941e294 7912 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
mbed_official 464:04583941e294 7913 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
mbed_official 464:04583941e294 7914 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
mbed_official 464:04583941e294 7915 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
mbed_official 464:04583941e294 7916 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
mbed_official 464:04583941e294 7917 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
mbed_official 464:04583941e294 7918 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
mbed_official 464:04583941e294 7919 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
mbed_official 464:04583941e294 7920 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 464:04583941e294 7921 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 464:04583941e294 7922 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 464:04583941e294 7923 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 464:04583941e294 7924 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 464:04583941e294 7925 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 464:04583941e294 7926 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 464:04583941e294 7927 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 464:04583941e294 7928 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
mbed_official 464:04583941e294 7929 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
mbed_official 464:04583941e294 7930 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
mbed_official 464:04583941e294 7931 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
mbed_official 464:04583941e294 7932 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
mbed_official 464:04583941e294 7933 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
mbed_official 464:04583941e294 7934
mbed_official 464:04583941e294 7935 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
mbed_official 464:04583941e294 7936 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
mbed_official 464:04583941e294 7937
mbed_official 464:04583941e294 7938 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
mbed_official 464:04583941e294 7939 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
mbed_official 464:04583941e294 7940
mbed_official 464:04583941e294 7941 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
mbed_official 464:04583941e294 7942 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
mbed_official 464:04583941e294 7943
mbed_official 464:04583941e294 7944 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
mbed_official 464:04583941e294 7945 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
mbed_official 464:04583941e294 7946
mbed_official 464:04583941e294 7947 /* Bit definition for Ethernet DMA Status Register */
mbed_official 464:04583941e294 7948 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
mbed_official 464:04583941e294 7949 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
mbed_official 464:04583941e294 7950 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
mbed_official 464:04583941e294 7951 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
mbed_official 464:04583941e294 7952 /* combination with EBS[2:0] for GetFlagStatus function */
mbed_official 464:04583941e294 7953 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
mbed_official 464:04583941e294 7954 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
mbed_official 464:04583941e294 7955 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
mbed_official 464:04583941e294 7956 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
mbed_official 464:04583941e294 7957 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
mbed_official 464:04583941e294 7958 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
mbed_official 464:04583941e294 7959 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
mbed_official 464:04583941e294 7960 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
mbed_official 464:04583941e294 7961 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
mbed_official 464:04583941e294 7962 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
mbed_official 464:04583941e294 7963 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
mbed_official 464:04583941e294 7964 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
mbed_official 464:04583941e294 7965 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
mbed_official 464:04583941e294 7966 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
mbed_official 464:04583941e294 7967 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
mbed_official 464:04583941e294 7968 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
mbed_official 464:04583941e294 7969 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
mbed_official 464:04583941e294 7970 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
mbed_official 464:04583941e294 7971 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
mbed_official 464:04583941e294 7972 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
mbed_official 464:04583941e294 7973 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
mbed_official 464:04583941e294 7974 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
mbed_official 464:04583941e294 7975 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
mbed_official 464:04583941e294 7976 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
mbed_official 464:04583941e294 7977 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
mbed_official 464:04583941e294 7978 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
mbed_official 464:04583941e294 7979 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
mbed_official 464:04583941e294 7980 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
mbed_official 464:04583941e294 7981 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
mbed_official 464:04583941e294 7982 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
mbed_official 464:04583941e294 7983 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
mbed_official 464:04583941e294 7984 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
mbed_official 464:04583941e294 7985
mbed_official 464:04583941e294 7986 /* Bit definition for Ethernet DMA Operation Mode Register */
mbed_official 464:04583941e294 7987 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
mbed_official 464:04583941e294 7988 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
mbed_official 464:04583941e294 7989 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
mbed_official 464:04583941e294 7990 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
mbed_official 464:04583941e294 7991 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
mbed_official 464:04583941e294 7992 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
mbed_official 464:04583941e294 7993 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
mbed_official 464:04583941e294 7994 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
mbed_official 464:04583941e294 7995 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
mbed_official 464:04583941e294 7996 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
mbed_official 464:04583941e294 7997 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
mbed_official 464:04583941e294 7998 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
mbed_official 464:04583941e294 7999 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
mbed_official 464:04583941e294 8000 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
mbed_official 464:04583941e294 8001 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
mbed_official 464:04583941e294 8002 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
mbed_official 464:04583941e294 8003 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
mbed_official 464:04583941e294 8004 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
mbed_official 464:04583941e294 8005 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
mbed_official 464:04583941e294 8006 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
mbed_official 464:04583941e294 8007 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
mbed_official 464:04583941e294 8008 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
mbed_official 464:04583941e294 8009 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
mbed_official 464:04583941e294 8010 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
mbed_official 464:04583941e294 8011
mbed_official 464:04583941e294 8012 /* Bit definition for Ethernet DMA Interrupt Enable Register */
mbed_official 464:04583941e294 8013 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
mbed_official 464:04583941e294 8014 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
mbed_official 464:04583941e294 8015 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
mbed_official 464:04583941e294 8016 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
mbed_official 464:04583941e294 8017 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
mbed_official 464:04583941e294 8018 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
mbed_official 464:04583941e294 8019 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
mbed_official 464:04583941e294 8020 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
mbed_official 464:04583941e294 8021 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
mbed_official 464:04583941e294 8022 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
mbed_official 464:04583941e294 8023 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
mbed_official 464:04583941e294 8024 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
mbed_official 464:04583941e294 8025 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
mbed_official 464:04583941e294 8026 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
mbed_official 464:04583941e294 8027 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
mbed_official 464:04583941e294 8028
mbed_official 464:04583941e294 8029 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
mbed_official 464:04583941e294 8030 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
mbed_official 464:04583941e294 8031 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
mbed_official 464:04583941e294 8032 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
mbed_official 464:04583941e294 8033 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
mbed_official 464:04583941e294 8034
mbed_official 464:04583941e294 8035 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
mbed_official 464:04583941e294 8036 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
mbed_official 464:04583941e294 8037
mbed_official 464:04583941e294 8038 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
mbed_official 464:04583941e294 8039 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
mbed_official 464:04583941e294 8040
mbed_official 464:04583941e294 8041 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
mbed_official 464:04583941e294 8042 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
mbed_official 464:04583941e294 8043
mbed_official 464:04583941e294 8044 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
mbed_official 464:04583941e294 8045 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
mbed_official 464:04583941e294 8046
mbed_official 464:04583941e294 8047 /******************************************************************************/
mbed_official 464:04583941e294 8048 /* */
mbed_official 464:04583941e294 8049 /* USB_OTG */
mbed_official 464:04583941e294 8050 /* */
mbed_official 464:04583941e294 8051 /******************************************************************************/
mbed_official 464:04583941e294 8052 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
mbed_official 464:04583941e294 8053 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
mbed_official 464:04583941e294 8054 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
mbed_official 464:04583941e294 8055 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host negotiation success */
mbed_official 464:04583941e294 8056 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
mbed_official 464:04583941e294 8057 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
mbed_official 464:04583941e294 8058 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
mbed_official 464:04583941e294 8059 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
mbed_official 464:04583941e294 8060 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
mbed_official 464:04583941e294 8061 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
mbed_official 464:04583941e294 8062 #define USB_OTG_GOTGCTL_BSVLD ((uint32_t)0x00080000) /*!< B-session valid */
mbed_official 464:04583941e294 8063
mbed_official 464:04583941e294 8064 /******************** Bit definition forUSB_OTG_HCFG register ********************/
mbed_official 464:04583941e294 8065
mbed_official 464:04583941e294 8066 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
mbed_official 464:04583941e294 8067 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 8068 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 8069 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
mbed_official 464:04583941e294 8070
mbed_official 464:04583941e294 8071 /******************** Bit definition forUSB_OTG_DCFG register ********************/
mbed_official 464:04583941e294 8072
mbed_official 464:04583941e294 8073 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
mbed_official 464:04583941e294 8074 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 8075 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 8076 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
mbed_official 464:04583941e294 8077
mbed_official 464:04583941e294 8078 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
mbed_official 464:04583941e294 8079 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 8080 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 8081 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 8082 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 464:04583941e294 8083 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
mbed_official 464:04583941e294 8084 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
mbed_official 464:04583941e294 8085 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
mbed_official 464:04583941e294 8086
mbed_official 464:04583941e294 8087 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
mbed_official 464:04583941e294 8088 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 464:04583941e294 8089 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 464:04583941e294 8090
mbed_official 464:04583941e294 8091 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
mbed_official 464:04583941e294 8092 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 8093 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 8094
mbed_official 464:04583941e294 8095 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
mbed_official 464:04583941e294 8096 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
mbed_official 464:04583941e294 8097 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
mbed_official 464:04583941e294 8098 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
mbed_official 464:04583941e294 8099
mbed_official 464:04583941e294 8100 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
mbed_official 464:04583941e294 8101 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
mbed_official 464:04583941e294 8102 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
mbed_official 464:04583941e294 8103 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
mbed_official 464:04583941e294 8104 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
mbed_official 464:04583941e294 8105 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
mbed_official 464:04583941e294 8106 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
mbed_official 464:04583941e294 8107
mbed_official 464:04583941e294 8108 /******************** Bit definition forUSB_OTG_DCTL register ********************/
mbed_official 464:04583941e294 8109 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
mbed_official 464:04583941e294 8110 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
mbed_official 464:04583941e294 8111 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
mbed_official 464:04583941e294 8112 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
mbed_official 464:04583941e294 8113
mbed_official 464:04583941e294 8114 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
mbed_official 464:04583941e294 8115 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 464:04583941e294 8116 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 464:04583941e294 8117 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 464:04583941e294 8118 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
mbed_official 464:04583941e294 8119 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
mbed_official 464:04583941e294 8120 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
mbed_official 464:04583941e294 8121 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
mbed_official 464:04583941e294 8122 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
mbed_official 464:04583941e294 8123
mbed_official 464:04583941e294 8124 /******************** Bit definition forUSB_OTG_HFIR register ********************/
mbed_official 464:04583941e294 8125 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
mbed_official 464:04583941e294 8126
mbed_official 464:04583941e294 8127 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
mbed_official 464:04583941e294 8128 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
mbed_official 464:04583941e294 8129 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
mbed_official 464:04583941e294 8130
mbed_official 464:04583941e294 8131 /******************** Bit definition forUSB_OTG_DSTS register ********************/
mbed_official 464:04583941e294 8132 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
mbed_official 464:04583941e294 8133
mbed_official 464:04583941e294 8134 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
mbed_official 464:04583941e294 8135 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 464:04583941e294 8136 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 464:04583941e294 8137 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
mbed_official 464:04583941e294 8138 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
mbed_official 464:04583941e294 8139
mbed_official 464:04583941e294 8140 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
mbed_official 464:04583941e294 8141 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
mbed_official 464:04583941e294 8142
mbed_official 464:04583941e294 8143 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
mbed_official 464:04583941e294 8144 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 464:04583941e294 8145 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 464:04583941e294 8146 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
mbed_official 464:04583941e294 8147 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
mbed_official 464:04583941e294 8148 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
mbed_official 464:04583941e294 8149 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
mbed_official 464:04583941e294 8150 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
mbed_official 464:04583941e294 8151
mbed_official 464:04583941e294 8152 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
mbed_official 464:04583941e294 8153
mbed_official 464:04583941e294 8154 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
mbed_official 464:04583941e294 8155 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 8156 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 8157 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 8158 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
mbed_official 464:04583941e294 8159 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
mbed_official 464:04583941e294 8160 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
mbed_official 464:04583941e294 8161
mbed_official 464:04583941e294 8162 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
mbed_official 464:04583941e294 8163 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 464:04583941e294 8164 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 464:04583941e294 8165 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
mbed_official 464:04583941e294 8166 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
mbed_official 464:04583941e294 8167 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
mbed_official 464:04583941e294 8168 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
mbed_official 464:04583941e294 8169 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
mbed_official 464:04583941e294 8170 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
mbed_official 464:04583941e294 8171 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
mbed_official 464:04583941e294 8172 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
mbed_official 464:04583941e294 8173 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
mbed_official 464:04583941e294 8174 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
mbed_official 464:04583941e294 8175 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
mbed_official 464:04583941e294 8176 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
mbed_official 464:04583941e294 8177 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
mbed_official 464:04583941e294 8178 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
mbed_official 464:04583941e294 8179 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
mbed_official 464:04583941e294 8180
mbed_official 464:04583941e294 8181 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
mbed_official 464:04583941e294 8182 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
mbed_official 464:04583941e294 8183 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
mbed_official 464:04583941e294 8184 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
mbed_official 464:04583941e294 8185 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
mbed_official 464:04583941e294 8186 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
mbed_official 464:04583941e294 8187
mbed_official 464:04583941e294 8188 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
mbed_official 464:04583941e294 8189 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 464:04583941e294 8190 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 464:04583941e294 8191 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
mbed_official 464:04583941e294 8192 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
mbed_official 464:04583941e294 8193 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
mbed_official 464:04583941e294 8194 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
mbed_official 464:04583941e294 8195 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
mbed_official 464:04583941e294 8196
mbed_official 464:04583941e294 8197 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
mbed_official 464:04583941e294 8198 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 464:04583941e294 8199 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 464:04583941e294 8200 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 464:04583941e294 8201 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 464:04583941e294 8202 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 464:04583941e294 8203 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 464:04583941e294 8204 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 464:04583941e294 8205 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 464:04583941e294 8206
mbed_official 464:04583941e294 8207 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
mbed_official 464:04583941e294 8208 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
mbed_official 464:04583941e294 8209
mbed_official 464:04583941e294 8210 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
mbed_official 464:04583941e294 8211 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 8212 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 8213 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 8214 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 8215 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 464:04583941e294 8216 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 464:04583941e294 8217 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 464:04583941e294 8218 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 464:04583941e294 8219
mbed_official 464:04583941e294 8220 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
mbed_official 464:04583941e294 8221 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 8222 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 8223 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 8224 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 8225 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 464:04583941e294 8226 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 464:04583941e294 8227 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 464:04583941e294 8228 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
mbed_official 464:04583941e294 8229
mbed_official 464:04583941e294 8230 /******************** Bit definition forUSB_OTG_HAINT register ********************/
mbed_official 464:04583941e294 8231 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
mbed_official 464:04583941e294 8232
mbed_official 464:04583941e294 8233 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
mbed_official 464:04583941e294 8234 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 464:04583941e294 8235 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 464:04583941e294 8236 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
mbed_official 464:04583941e294 8237 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
mbed_official 464:04583941e294 8238 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
mbed_official 464:04583941e294 8239 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 464:04583941e294 8240 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 464:04583941e294 8241
mbed_official 464:04583941e294 8242 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
mbed_official 464:04583941e294 8243 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
mbed_official 464:04583941e294 8244 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
mbed_official 464:04583941e294 8245 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
mbed_official 464:04583941e294 8246 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
mbed_official 464:04583941e294 8247 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
mbed_official 464:04583941e294 8248 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
mbed_official 464:04583941e294 8249 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
mbed_official 464:04583941e294 8250 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
mbed_official 464:04583941e294 8251 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
mbed_official 464:04583941e294 8252 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
mbed_official 464:04583941e294 8253 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
mbed_official 464:04583941e294 8254 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
mbed_official 464:04583941e294 8255 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
mbed_official 464:04583941e294 8256 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
mbed_official 464:04583941e294 8257 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
mbed_official 464:04583941e294 8258 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
mbed_official 464:04583941e294 8259 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
mbed_official 464:04583941e294 8260 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
mbed_official 464:04583941e294 8261 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
mbed_official 464:04583941e294 8262 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
mbed_official 464:04583941e294 8263 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
mbed_official 464:04583941e294 8264 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
mbed_official 464:04583941e294 8265 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
mbed_official 464:04583941e294 8266 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
mbed_official 464:04583941e294 8267 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
mbed_official 464:04583941e294 8268 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
mbed_official 464:04583941e294 8269
mbed_official 464:04583941e294 8270 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
mbed_official 464:04583941e294 8271 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
mbed_official 464:04583941e294 8272 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
mbed_official 464:04583941e294 8273 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
mbed_official 464:04583941e294 8274 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
mbed_official 464:04583941e294 8275 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
mbed_official 464:04583941e294 8276 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
mbed_official 464:04583941e294 8277 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
mbed_official 464:04583941e294 8278 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
mbed_official 464:04583941e294 8279 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
mbed_official 464:04583941e294 8280 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
mbed_official 464:04583941e294 8281 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
mbed_official 464:04583941e294 8282 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
mbed_official 464:04583941e294 8283 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
mbed_official 464:04583941e294 8284 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
mbed_official 464:04583941e294 8285 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
mbed_official 464:04583941e294 8286 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
mbed_official 464:04583941e294 8287 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
mbed_official 464:04583941e294 8288 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
mbed_official 464:04583941e294 8289 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
mbed_official 464:04583941e294 8290 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
mbed_official 464:04583941e294 8291 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
mbed_official 464:04583941e294 8292 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
mbed_official 464:04583941e294 8293 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
mbed_official 464:04583941e294 8294 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
mbed_official 464:04583941e294 8295 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
mbed_official 464:04583941e294 8296 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
mbed_official 464:04583941e294 8297
mbed_official 464:04583941e294 8298 /******************** Bit definition forUSB_OTG_DAINT register ********************/
mbed_official 464:04583941e294 8299 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
mbed_official 464:04583941e294 8300 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
mbed_official 464:04583941e294 8301
mbed_official 464:04583941e294 8302 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
mbed_official 464:04583941e294 8303 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
mbed_official 464:04583941e294 8304
mbed_official 464:04583941e294 8305 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
mbed_official 464:04583941e294 8306 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
mbed_official 464:04583941e294 8307 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
mbed_official 464:04583941e294 8308 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
mbed_official 464:04583941e294 8309 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
mbed_official 464:04583941e294 8310
mbed_official 464:04583941e294 8311 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
mbed_official 464:04583941e294 8312 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
mbed_official 464:04583941e294 8313 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
mbed_official 464:04583941e294 8314
mbed_official 464:04583941e294 8315 /******************** Bit definition for OTG register ********************/
mbed_official 464:04583941e294 8316
mbed_official 464:04583941e294 8317 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 464:04583941e294 8318 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 8319 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 8320 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 8321 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 8322 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 464:04583941e294 8323
mbed_official 464:04583941e294 8324 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 464:04583941e294 8325 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 464:04583941e294 8326 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 464:04583941e294 8327
mbed_official 464:04583941e294 8328 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 464:04583941e294 8329 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 464:04583941e294 8330 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 464:04583941e294 8331 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 464:04583941e294 8332 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 464:04583941e294 8333
mbed_official 464:04583941e294 8334 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 464:04583941e294 8335 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 8336 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 8337 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 8338 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 8339
mbed_official 464:04583941e294 8340 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 464:04583941e294 8341 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 464:04583941e294 8342 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 464:04583941e294 8343 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 464:04583941e294 8344 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 464:04583941e294 8345
mbed_official 464:04583941e294 8346 /******************** Bit definition for OTG register ********************/
mbed_official 464:04583941e294 8347
mbed_official 464:04583941e294 8348 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
mbed_official 464:04583941e294 8349 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 8350 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 8351 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 8352 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 8353 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
mbed_official 464:04583941e294 8354
mbed_official 464:04583941e294 8355 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
mbed_official 464:04583941e294 8356 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
mbed_official 464:04583941e294 8357 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
mbed_official 464:04583941e294 8358
mbed_official 464:04583941e294 8359 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
mbed_official 464:04583941e294 8360 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 464:04583941e294 8361 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 464:04583941e294 8362 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 464:04583941e294 8363 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 464:04583941e294 8364
mbed_official 464:04583941e294 8365 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
mbed_official 464:04583941e294 8366 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 8367 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 8368 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 8369 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 8370
mbed_official 464:04583941e294 8371 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
mbed_official 464:04583941e294 8372 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
mbed_official 464:04583941e294 8373 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
mbed_official 464:04583941e294 8374 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 464:04583941e294 8375 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 464:04583941e294 8376
mbed_official 464:04583941e294 8377 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
mbed_official 464:04583941e294 8378 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
mbed_official 464:04583941e294 8379
mbed_official 464:04583941e294 8380 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
mbed_official 464:04583941e294 8381 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
mbed_official 464:04583941e294 8382
mbed_official 464:04583941e294 8383 /******************** Bit definition for OTG register ********************/
mbed_official 464:04583941e294 8384 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
mbed_official 464:04583941e294 8385 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
mbed_official 464:04583941e294 8386 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
mbed_official 464:04583941e294 8387 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
mbed_official 464:04583941e294 8388
mbed_official 464:04583941e294 8389 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
mbed_official 464:04583941e294 8390 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
mbed_official 464:04583941e294 8391
mbed_official 464:04583941e294 8392 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
mbed_official 464:04583941e294 8393 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
mbed_official 464:04583941e294 8394
mbed_official 464:04583941e294 8395 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
mbed_official 464:04583941e294 8396 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
mbed_official 464:04583941e294 8397 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
mbed_official 464:04583941e294 8398 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
mbed_official 464:04583941e294 8399 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
mbed_official 464:04583941e294 8400 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
mbed_official 464:04583941e294 8401 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
mbed_official 464:04583941e294 8402 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
mbed_official 464:04583941e294 8403 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
mbed_official 464:04583941e294 8404
mbed_official 464:04583941e294 8405 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
mbed_official 464:04583941e294 8406 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 464:04583941e294 8407 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 464:04583941e294 8408 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 464:04583941e294 8409 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 464:04583941e294 8410 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
mbed_official 464:04583941e294 8411 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
mbed_official 464:04583941e294 8412 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
mbed_official 464:04583941e294 8413
mbed_official 464:04583941e294 8414 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
mbed_official 464:04583941e294 8415 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
mbed_official 464:04583941e294 8416 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
mbed_official 464:04583941e294 8417
mbed_official 464:04583941e294 8418 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
mbed_official 464:04583941e294 8419 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 464:04583941e294 8420 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 464:04583941e294 8421 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
mbed_official 464:04583941e294 8422 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
mbed_official 464:04583941e294 8423 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
mbed_official 464:04583941e294 8424 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
mbed_official 464:04583941e294 8425 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
mbed_official 464:04583941e294 8426 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
mbed_official 464:04583941e294 8427 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
mbed_official 464:04583941e294 8428 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
mbed_official 464:04583941e294 8429
mbed_official 464:04583941e294 8430 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
mbed_official 464:04583941e294 8431 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 464:04583941e294 8432 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 464:04583941e294 8433 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 464:04583941e294 8434 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 464:04583941e294 8435 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 464:04583941e294 8436 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 464:04583941e294 8437 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 464:04583941e294 8438 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
mbed_official 464:04583941e294 8439 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
mbed_official 464:04583941e294 8440 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
mbed_official 464:04583941e294 8441
mbed_official 464:04583941e294 8442 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
mbed_official 464:04583941e294 8443 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
mbed_official 464:04583941e294 8444
mbed_official 464:04583941e294 8445 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
mbed_official 464:04583941e294 8446 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
mbed_official 464:04583941e294 8447 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
mbed_official 464:04583941e294 8448
mbed_official 464:04583941e294 8449 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
mbed_official 464:04583941e294 8450 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
mbed_official 464:04583941e294 8451 #define USB_OTG_GCCFG_I2CPADEN ((uint32_t)0x00020000) /*!< Enable I2C bus connection for the external I2C PHY interface */
mbed_official 464:04583941e294 8452 #define USB_OTG_GCCFG_VBUSASEN ((uint32_t)0x00040000) /*!< Enable the VBUS sensing device */
mbed_official 464:04583941e294 8453 #define USB_OTG_GCCFG_VBUSBSEN ((uint32_t)0x00080000) /*!< Enable the VBUS sensing device */
mbed_official 464:04583941e294 8454 #define USB_OTG_GCCFG_SOFOUTEN ((uint32_t)0x00100000) /*!< SOF output enable */
mbed_official 464:04583941e294 8455 #define USB_OTG_GCCFG_NOVBUSSENS ((uint32_t)0x00200000) /*!< VBUS sensing disable option */
mbed_official 464:04583941e294 8456
mbed_official 464:04583941e294 8457 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
mbed_official 464:04583941e294 8458 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
mbed_official 464:04583941e294 8459 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
mbed_official 464:04583941e294 8460
mbed_official 464:04583941e294 8461 /******************** Bit definition forUSB_OTG_CID register ********************/
mbed_official 464:04583941e294 8462 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
mbed_official 464:04583941e294 8463
mbed_official 464:04583941e294 8464 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
mbed_official 464:04583941e294 8465 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 464:04583941e294 8466 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 464:04583941e294 8467 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
mbed_official 464:04583941e294 8468 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 464:04583941e294 8469 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 464:04583941e294 8470 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 464:04583941e294 8471 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
mbed_official 464:04583941e294 8472 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 464:04583941e294 8473 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 464:04583941e294 8474
mbed_official 464:04583941e294 8475 /******************** Bit definition forUSB_OTG_HPRT register ********************/
mbed_official 464:04583941e294 8476 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
mbed_official 464:04583941e294 8477 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
mbed_official 464:04583941e294 8478 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
mbed_official 464:04583941e294 8479 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
mbed_official 464:04583941e294 8480 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
mbed_official 464:04583941e294 8481 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
mbed_official 464:04583941e294 8482 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
mbed_official 464:04583941e294 8483 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
mbed_official 464:04583941e294 8484 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
mbed_official 464:04583941e294 8485
mbed_official 464:04583941e294 8486 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
mbed_official 464:04583941e294 8487 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 464:04583941e294 8488 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 464:04583941e294 8489 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
mbed_official 464:04583941e294 8490
mbed_official 464:04583941e294 8491 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
mbed_official 464:04583941e294 8492 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
mbed_official 464:04583941e294 8493 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
mbed_official 464:04583941e294 8494 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
mbed_official 464:04583941e294 8495 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 464:04583941e294 8496
mbed_official 464:04583941e294 8497 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
mbed_official 464:04583941e294 8498 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 464:04583941e294 8499 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 464:04583941e294 8500
mbed_official 464:04583941e294 8501 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
mbed_official 464:04583941e294 8502 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
mbed_official 464:04583941e294 8503 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
mbed_official 464:04583941e294 8504 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
mbed_official 464:04583941e294 8505 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
mbed_official 464:04583941e294 8506 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
mbed_official 464:04583941e294 8507 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
mbed_official 464:04583941e294 8508 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
mbed_official 464:04583941e294 8509 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
mbed_official 464:04583941e294 8510 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
mbed_official 464:04583941e294 8511 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
mbed_official 464:04583941e294 8512 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
mbed_official 464:04583941e294 8513
mbed_official 464:04583941e294 8514 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
mbed_official 464:04583941e294 8515 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
mbed_official 464:04583941e294 8516 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
mbed_official 464:04583941e294 8517
mbed_official 464:04583941e294 8518 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
mbed_official 464:04583941e294 8519 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 464:04583941e294 8520 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 464:04583941e294 8521 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
mbed_official 464:04583941e294 8522 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 464:04583941e294 8523
mbed_official 464:04583941e294 8524 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 464:04583941e294 8525 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 464:04583941e294 8526 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 464:04583941e294 8527 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 464:04583941e294 8528
mbed_official 464:04583941e294 8529 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
mbed_official 464:04583941e294 8530 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 464:04583941e294 8531 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 464:04583941e294 8532 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 464:04583941e294 8533 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 464:04583941e294 8534 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 464:04583941e294 8535 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 464:04583941e294 8536 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 464:04583941e294 8537 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 464:04583941e294 8538 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 464:04583941e294 8539 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 464:04583941e294 8540
mbed_official 464:04583941e294 8541 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
mbed_official 464:04583941e294 8542 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
mbed_official 464:04583941e294 8543
mbed_official 464:04583941e294 8544 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
mbed_official 464:04583941e294 8545 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
mbed_official 464:04583941e294 8546 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
mbed_official 464:04583941e294 8547 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
mbed_official 464:04583941e294 8548 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
mbed_official 464:04583941e294 8549 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
mbed_official 464:04583941e294 8550 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
mbed_official 464:04583941e294 8551
mbed_official 464:04583941e294 8552 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 464:04583941e294 8553 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 464:04583941e294 8554 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 464:04583941e294 8555
mbed_official 464:04583941e294 8556 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
mbed_official 464:04583941e294 8557 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 464:04583941e294 8558 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 464:04583941e294 8559
mbed_official 464:04583941e294 8560 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
mbed_official 464:04583941e294 8561 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 464:04583941e294 8562 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 464:04583941e294 8563 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
mbed_official 464:04583941e294 8564 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
mbed_official 464:04583941e294 8565 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
mbed_official 464:04583941e294 8566 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
mbed_official 464:04583941e294 8567 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
mbed_official 464:04583941e294 8568 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
mbed_official 464:04583941e294 8569 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
mbed_official 464:04583941e294 8570 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
mbed_official 464:04583941e294 8571
mbed_official 464:04583941e294 8572 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
mbed_official 464:04583941e294 8573
mbed_official 464:04583941e294 8574 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
mbed_official 464:04583941e294 8575 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 464:04583941e294 8576 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 464:04583941e294 8577 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 464:04583941e294 8578 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 464:04583941e294 8579 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 464:04583941e294 8580 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 464:04583941e294 8581 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 464:04583941e294 8582
mbed_official 464:04583941e294 8583 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
mbed_official 464:04583941e294 8584 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 464:04583941e294 8585 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 464:04583941e294 8586 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
mbed_official 464:04583941e294 8587 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
mbed_official 464:04583941e294 8588 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
mbed_official 464:04583941e294 8589 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
mbed_official 464:04583941e294 8590 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
mbed_official 464:04583941e294 8591
mbed_official 464:04583941e294 8592 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
mbed_official 464:04583941e294 8593 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
mbed_official 464:04583941e294 8594 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
mbed_official 464:04583941e294 8595 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
mbed_official 464:04583941e294 8596 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
mbed_official 464:04583941e294 8597
mbed_official 464:04583941e294 8598 /******************** Bit definition forUSB_OTG_HCINT register ********************/
mbed_official 464:04583941e294 8599 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
mbed_official 464:04583941e294 8600 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
mbed_official 464:04583941e294 8601 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 464:04583941e294 8602 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
mbed_official 464:04583941e294 8603 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
mbed_official 464:04583941e294 8604 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
mbed_official 464:04583941e294 8605 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
mbed_official 464:04583941e294 8606 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
mbed_official 464:04583941e294 8607 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
mbed_official 464:04583941e294 8608 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
mbed_official 464:04583941e294 8609 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
mbed_official 464:04583941e294 8610
mbed_official 464:04583941e294 8611 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
mbed_official 464:04583941e294 8612 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 464:04583941e294 8613 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 464:04583941e294 8614 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
mbed_official 464:04583941e294 8615 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
mbed_official 464:04583941e294 8616 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
mbed_official 464:04583941e294 8617 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
mbed_official 464:04583941e294 8618 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
mbed_official 464:04583941e294 8619 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
mbed_official 464:04583941e294 8620 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
mbed_official 464:04583941e294 8621 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
mbed_official 464:04583941e294 8622 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
mbed_official 464:04583941e294 8623
mbed_official 464:04583941e294 8624 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
mbed_official 464:04583941e294 8625 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
mbed_official 464:04583941e294 8626 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
mbed_official 464:04583941e294 8627 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
mbed_official 464:04583941e294 8628 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
mbed_official 464:04583941e294 8629 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
mbed_official 464:04583941e294 8630 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
mbed_official 464:04583941e294 8631 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
mbed_official 464:04583941e294 8632 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
mbed_official 464:04583941e294 8633 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
mbed_official 464:04583941e294 8634 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
mbed_official 464:04583941e294 8635 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
mbed_official 464:04583941e294 8636
mbed_official 464:04583941e294 8637 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
mbed_official 464:04583941e294 8638
mbed_official 464:04583941e294 8639 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 464:04583941e294 8640 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 464:04583941e294 8641 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
mbed_official 464:04583941e294 8642 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
mbed_official 464:04583941e294 8643 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 464:04583941e294 8644 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 464:04583941e294 8645 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
mbed_official 464:04583941e294 8646 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
mbed_official 464:04583941e294 8647 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 464:04583941e294 8648 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 464:04583941e294 8649
mbed_official 464:04583941e294 8650 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
mbed_official 464:04583941e294 8651 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 464:04583941e294 8652
mbed_official 464:04583941e294 8653 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
mbed_official 464:04583941e294 8654 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
mbed_official 464:04583941e294 8655
mbed_official 464:04583941e294 8656 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
mbed_official 464:04583941e294 8657 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
mbed_official 464:04583941e294 8658
mbed_official 464:04583941e294 8659 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
mbed_official 464:04583941e294 8660 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
mbed_official 464:04583941e294 8661 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
mbed_official 464:04583941e294 8662
mbed_official 464:04583941e294 8663 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
mbed_official 464:04583941e294 8664
mbed_official 464:04583941e294 8665 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
mbed_official 464:04583941e294 8666 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
mbed_official 464:04583941e294 8667 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
mbed_official 464:04583941e294 8668 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
mbed_official 464:04583941e294 8669 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
mbed_official 464:04583941e294 8670 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
mbed_official 464:04583941e294 8671 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
mbed_official 464:04583941e294 8672 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
mbed_official 464:04583941e294 8673 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
mbed_official 464:04583941e294 8674 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
mbed_official 464:04583941e294 8675 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
mbed_official 464:04583941e294 8676 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
mbed_official 464:04583941e294 8677 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
mbed_official 464:04583941e294 8678 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
mbed_official 464:04583941e294 8679
mbed_official 464:04583941e294 8680 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
mbed_official 464:04583941e294 8681 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
mbed_official 464:04583941e294 8682 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
mbed_official 464:04583941e294 8683 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
mbed_official 464:04583941e294 8684 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
mbed_official 464:04583941e294 8685 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
mbed_official 464:04583941e294 8686 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
mbed_official 464:04583941e294 8687
mbed_official 464:04583941e294 8688 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
mbed_official 464:04583941e294 8689
mbed_official 464:04583941e294 8690 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
mbed_official 464:04583941e294 8691 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
mbed_official 464:04583941e294 8692
mbed_official 464:04583941e294 8693 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
mbed_official 464:04583941e294 8694 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
mbed_official 464:04583941e294 8695 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
mbed_official 464:04583941e294 8696
mbed_official 464:04583941e294 8697 /******************** Bit definition for PCGCCTL register ********************/
mbed_official 464:04583941e294 8698 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
mbed_official 464:04583941e294 8699 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 464:04583941e294 8700 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 464:04583941e294 8701
mbed_official 464:04583941e294 8702
mbed_official 464:04583941e294 8703 /**
mbed_official 464:04583941e294 8704 * @}
mbed_official 464:04583941e294 8705 */
mbed_official 464:04583941e294 8706
mbed_official 464:04583941e294 8707 /**
mbed_official 464:04583941e294 8708 * @}
mbed_official 464:04583941e294 8709 */
mbed_official 464:04583941e294 8710
mbed_official 464:04583941e294 8711 /** @addtogroup Exported_macros
mbed_official 464:04583941e294 8712 * @{
mbed_official 464:04583941e294 8713 */
mbed_official 464:04583941e294 8714
mbed_official 464:04583941e294 8715 /******************************* ADC Instances ********************************/
mbed_official 464:04583941e294 8716 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
mbed_official 464:04583941e294 8717 ((INSTANCE) == ADC2) || \
mbed_official 464:04583941e294 8718 ((INSTANCE) == ADC3))
mbed_official 464:04583941e294 8719
mbed_official 464:04583941e294 8720 /******************************* CAN Instances ********************************/
mbed_official 464:04583941e294 8721 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
mbed_official 464:04583941e294 8722 ((INSTANCE) == CAN2))
mbed_official 464:04583941e294 8723
mbed_official 464:04583941e294 8724 /******************************* CRC Instances ********************************/
mbed_official 464:04583941e294 8725 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 464:04583941e294 8726
mbed_official 464:04583941e294 8727 /******************************* DAC Instances ********************************/
mbed_official 464:04583941e294 8728 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 464:04583941e294 8729
mbed_official 464:04583941e294 8730 /******************************* DCMI Instances *******************************/
mbed_official 464:04583941e294 8731 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
mbed_official 464:04583941e294 8732
mbed_official 464:04583941e294 8733 /******************************* DMA2D Instances *******************************/
mbed_official 464:04583941e294 8734 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
mbed_official 464:04583941e294 8735
mbed_official 464:04583941e294 8736 /******************************** DMA Instances *******************************/
mbed_official 464:04583941e294 8737 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
mbed_official 464:04583941e294 8738 ((INSTANCE) == DMA1_Stream1) || \
mbed_official 464:04583941e294 8739 ((INSTANCE) == DMA1_Stream2) || \
mbed_official 464:04583941e294 8740 ((INSTANCE) == DMA1_Stream3) || \
mbed_official 464:04583941e294 8741 ((INSTANCE) == DMA1_Stream4) || \
mbed_official 464:04583941e294 8742 ((INSTANCE) == DMA1_Stream5) || \
mbed_official 464:04583941e294 8743 ((INSTANCE) == DMA1_Stream6) || \
mbed_official 464:04583941e294 8744 ((INSTANCE) == DMA1_Stream7) || \
mbed_official 464:04583941e294 8745 ((INSTANCE) == DMA2_Stream0) || \
mbed_official 464:04583941e294 8746 ((INSTANCE) == DMA2_Stream1) || \
mbed_official 464:04583941e294 8747 ((INSTANCE) == DMA2_Stream2) || \
mbed_official 464:04583941e294 8748 ((INSTANCE) == DMA2_Stream3) || \
mbed_official 464:04583941e294 8749 ((INSTANCE) == DMA2_Stream4) || \
mbed_official 464:04583941e294 8750 ((INSTANCE) == DMA2_Stream5) || \
mbed_official 464:04583941e294 8751 ((INSTANCE) == DMA2_Stream6) || \
mbed_official 464:04583941e294 8752 ((INSTANCE) == DMA2_Stream7))
mbed_official 464:04583941e294 8753
mbed_official 464:04583941e294 8754 /******************************* GPIO Instances *******************************/
mbed_official 464:04583941e294 8755 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 464:04583941e294 8756 ((INSTANCE) == GPIOB) || \
mbed_official 464:04583941e294 8757 ((INSTANCE) == GPIOC) || \
mbed_official 464:04583941e294 8758 ((INSTANCE) == GPIOD) || \
mbed_official 464:04583941e294 8759 ((INSTANCE) == GPIOE) || \
mbed_official 464:04583941e294 8760 ((INSTANCE) == GPIOF) || \
mbed_official 464:04583941e294 8761 ((INSTANCE) == GPIOG) || \
mbed_official 464:04583941e294 8762 ((INSTANCE) == GPIOH) || \
mbed_official 464:04583941e294 8763 ((INSTANCE) == GPIOI) || \
mbed_official 464:04583941e294 8764 ((INSTANCE) == GPIOJ) || \
mbed_official 464:04583941e294 8765 ((INSTANCE) == GPIOK))
mbed_official 464:04583941e294 8766
mbed_official 464:04583941e294 8767 /******************************** I2C Instances *******************************/
mbed_official 464:04583941e294 8768 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 464:04583941e294 8769 ((INSTANCE) == I2C2) || \
mbed_official 464:04583941e294 8770 ((INSTANCE) == I2C3))
mbed_official 464:04583941e294 8771
mbed_official 464:04583941e294 8772 /******************************** I2S Instances *******************************/
mbed_official 464:04583941e294 8773 #define IS_I2S_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
mbed_official 464:04583941e294 8774 ((INSTANCE) == SPI3))
mbed_official 464:04583941e294 8775
mbed_official 464:04583941e294 8776 /*************************** I2S Extended Instances ***************************/
mbed_official 464:04583941e294 8777 #define IS_I2S_INSTANCE_EXT(PERIPH) (((INSTANCE) == SPI2) || \
mbed_official 464:04583941e294 8778 ((INSTANCE) == SPI3) || \
mbed_official 464:04583941e294 8779 ((INSTANCE) == I2S2ext) || \
mbed_official 464:04583941e294 8780 ((INSTANCE) == I2S3ext))
mbed_official 464:04583941e294 8781
mbed_official 464:04583941e294 8782 /****************************** LTDC Instances ********************************/
mbed_official 464:04583941e294 8783 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
mbed_official 464:04583941e294 8784
mbed_official 464:04583941e294 8785 /******************************* RNG Instances ********************************/
mbed_official 464:04583941e294 8786 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
mbed_official 464:04583941e294 8787
mbed_official 464:04583941e294 8788 /****************************** RTC Instances *********************************/
mbed_official 464:04583941e294 8789 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 464:04583941e294 8790
mbed_official 464:04583941e294 8791 /******************************* SAI Instances ********************************/
mbed_official 464:04583941e294 8792 #define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
mbed_official 464:04583941e294 8793 ((PERIPH) == SAI1_Block_B))
mbed_official 464:04583941e294 8794
mbed_official 464:04583941e294 8795 /******************************** SPI Instances *******************************/
mbed_official 464:04583941e294 8796 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 464:04583941e294 8797 ((INSTANCE) == SPI2) || \
mbed_official 464:04583941e294 8798 ((INSTANCE) == SPI3) || \
mbed_official 464:04583941e294 8799 ((INSTANCE) == SPI4) || \
mbed_official 464:04583941e294 8800 ((INSTANCE) == SPI5) || \
mbed_official 464:04583941e294 8801 ((INSTANCE) == SPI6))
mbed_official 464:04583941e294 8802
mbed_official 464:04583941e294 8803 /*************************** SPI Extended Instances ***************************/
mbed_official 464:04583941e294 8804 #define IS_SPI_ALL_INSTANCE_EXT(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 464:04583941e294 8805 ((INSTANCE) == SPI2) || \
mbed_official 464:04583941e294 8806 ((INSTANCE) == SPI3) || \
mbed_official 464:04583941e294 8807 ((INSTANCE) == SPI4) || \
mbed_official 464:04583941e294 8808 ((INSTANCE) == SPI5) || \
mbed_official 464:04583941e294 8809 ((INSTANCE) == SPI6) || \
mbed_official 464:04583941e294 8810 ((INSTANCE) == I2S2ext) || \
mbed_official 464:04583941e294 8811 ((INSTANCE) == I2S3ext))
mbed_official 464:04583941e294 8812
mbed_official 464:04583941e294 8813 /****************** TIM Instances : All supported instances *******************/
mbed_official 464:04583941e294 8814 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8815 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8816 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8817 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8818 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8819 ((INSTANCE) == TIM6) || \
mbed_official 464:04583941e294 8820 ((INSTANCE) == TIM7) || \
mbed_official 464:04583941e294 8821 ((INSTANCE) == TIM8) || \
mbed_official 464:04583941e294 8822 ((INSTANCE) == TIM9) || \
mbed_official 464:04583941e294 8823 ((INSTANCE) == TIM10) || \
mbed_official 464:04583941e294 8824 ((INSTANCE) == TIM11) || \
mbed_official 464:04583941e294 8825 ((INSTANCE) == TIM12) || \
mbed_official 464:04583941e294 8826 ((INSTANCE) == TIM13) || \
mbed_official 464:04583941e294 8827 ((INSTANCE) == TIM14))
mbed_official 464:04583941e294 8828
mbed_official 464:04583941e294 8829 /************* TIM Instances : at least 1 capture/compare channel *************/
mbed_official 464:04583941e294 8830 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8831 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8832 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8833 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8834 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8835 ((INSTANCE) == TIM8) || \
mbed_official 464:04583941e294 8836 ((INSTANCE) == TIM9) || \
mbed_official 464:04583941e294 8837 ((INSTANCE) == TIM10) || \
mbed_official 464:04583941e294 8838 ((INSTANCE) == TIM11) || \
mbed_official 464:04583941e294 8839 ((INSTANCE) == TIM12) || \
mbed_official 464:04583941e294 8840 ((INSTANCE) == TIM13) || \
mbed_official 464:04583941e294 8841 ((INSTANCE) == TIM14))
mbed_official 464:04583941e294 8842
mbed_official 464:04583941e294 8843 /************ TIM Instances : at least 2 capture/compare channels *************/
mbed_official 464:04583941e294 8844 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8845 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8846 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8847 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8848 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8849 ((INSTANCE) == TIM8) || \
mbed_official 464:04583941e294 8850 ((INSTANCE) == TIM9) || \
mbed_official 464:04583941e294 8851 ((INSTANCE) == TIM12))
mbed_official 464:04583941e294 8852
mbed_official 464:04583941e294 8853 /************ TIM Instances : at least 3 capture/compare channels *************/
mbed_official 464:04583941e294 8854 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8855 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8856 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8857 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8858 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8859 ((INSTANCE) == TIM8))
mbed_official 464:04583941e294 8860
mbed_official 464:04583941e294 8861 /************ TIM Instances : at least 4 capture/compare channels *************/
mbed_official 464:04583941e294 8862 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8863 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8864 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8865 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8866 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8867 ((INSTANCE) == TIM8))
mbed_official 464:04583941e294 8868
mbed_official 464:04583941e294 8869 /******************** TIM Instances : Advanced-control timers *****************/
mbed_official 464:04583941e294 8870 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8871 ((INSTANCE) == TIM8))
mbed_official 464:04583941e294 8872
mbed_official 464:04583941e294 8873 /******************* TIM Instances : Timer input XOR function *****************/
mbed_official 464:04583941e294 8874 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8875 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8876 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8877 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8878 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8879 ((INSTANCE) == TIM8))
mbed_official 464:04583941e294 8880
mbed_official 464:04583941e294 8881 /****************** TIM Instances : DMA requests generation (UDE) *************/
mbed_official 464:04583941e294 8882 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8883 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8884 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8885 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8886 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8887 ((INSTANCE) == TIM6) || \
mbed_official 464:04583941e294 8888 ((INSTANCE) == TIM7) || \
mbed_official 464:04583941e294 8889 ((INSTANCE) == TIM8))
mbed_official 464:04583941e294 8890
mbed_official 464:04583941e294 8891 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
mbed_official 464:04583941e294 8892 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8893 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8894 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8895 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8896 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8897 ((INSTANCE) == TIM8))
mbed_official 464:04583941e294 8898
mbed_official 464:04583941e294 8899 /************ TIM Instances : DMA requests generation (COMDE) *****************/
mbed_official 464:04583941e294 8900 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8901 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8902 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8903 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8904 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8905 ((INSTANCE) == TIM8))
mbed_official 464:04583941e294 8906
mbed_official 464:04583941e294 8907 /******************** TIM Instances : DMA burst feature ***********************/
mbed_official 464:04583941e294 8908 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8909 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8910 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8911 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8912 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8913 ((INSTANCE) == TIM8))
mbed_official 464:04583941e294 8914
mbed_official 464:04583941e294 8915 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
mbed_official 464:04583941e294 8916 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8917 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8918 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8919 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8920 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8921 ((INSTANCE) == TIM6) || \
mbed_official 464:04583941e294 8922 ((INSTANCE) == TIM7) || \
mbed_official 464:04583941e294 8923 ((INSTANCE) == TIM8) || \
mbed_official 464:04583941e294 8924 ((INSTANCE) == TIM9) || \
mbed_official 464:04583941e294 8925 ((INSTANCE) == TIM12))
mbed_official 464:04583941e294 8926
mbed_official 464:04583941e294 8927 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
mbed_official 464:04583941e294 8928 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8929 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8930 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8931 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8932 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8933 ((INSTANCE) == TIM8) || \
mbed_official 464:04583941e294 8934 ((INSTANCE) == TIM9) || \
mbed_official 464:04583941e294 8935 ((INSTANCE) == TIM12))
mbed_official 464:04583941e294 8936
mbed_official 464:04583941e294 8937 /********************** TIM Instances : 32 bit Counter ************************/
mbed_official 464:04583941e294 8938 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8939 ((INSTANCE) == TIM5))
mbed_official 464:04583941e294 8940
mbed_official 464:04583941e294 8941 /***************** TIM Instances : external trigger input availabe ************/
mbed_official 464:04583941e294 8942 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
mbed_official 464:04583941e294 8943 ((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8944 ((INSTANCE) == TIM3) || \
mbed_official 464:04583941e294 8945 ((INSTANCE) == TIM4) || \
mbed_official 464:04583941e294 8946 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8947 ((INSTANCE) == TIM8))
mbed_official 464:04583941e294 8948
mbed_official 464:04583941e294 8949 /****************** TIM Instances : remapping capability **********************/
mbed_official 464:04583941e294 8950 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 464:04583941e294 8951 ((INSTANCE) == TIM5) || \
mbed_official 464:04583941e294 8952 ((INSTANCE) == TIM11))
mbed_official 464:04583941e294 8953
mbed_official 464:04583941e294 8954 /******************* TIM Instances : output(s) available **********************/
mbed_official 464:04583941e294 8955 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 464:04583941e294 8956 ((((INSTANCE) == TIM1) && \
mbed_official 464:04583941e294 8957 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 464:04583941e294 8958 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 464:04583941e294 8959 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 464:04583941e294 8960 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 464:04583941e294 8961 || \
mbed_official 464:04583941e294 8962 (((INSTANCE) == TIM2) && \
mbed_official 464:04583941e294 8963 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 464:04583941e294 8964 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 464:04583941e294 8965 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 464:04583941e294 8966 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 464:04583941e294 8967 || \
mbed_official 464:04583941e294 8968 (((INSTANCE) == TIM3) && \
mbed_official 464:04583941e294 8969 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 464:04583941e294 8970 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 464:04583941e294 8971 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 464:04583941e294 8972 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 464:04583941e294 8973 || \
mbed_official 464:04583941e294 8974 (((INSTANCE) == TIM4) && \
mbed_official 464:04583941e294 8975 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 464:04583941e294 8976 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 464:04583941e294 8977 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 464:04583941e294 8978 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 464:04583941e294 8979 || \
mbed_official 464:04583941e294 8980 (((INSTANCE) == TIM5) && \
mbed_official 464:04583941e294 8981 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 464:04583941e294 8982 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 464:04583941e294 8983 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 464:04583941e294 8984 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 464:04583941e294 8985 || \
mbed_official 464:04583941e294 8986 (((INSTANCE) == TIM8) && \
mbed_official 464:04583941e294 8987 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 464:04583941e294 8988 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 464:04583941e294 8989 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 464:04583941e294 8990 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 464:04583941e294 8991 || \
mbed_official 464:04583941e294 8992 (((INSTANCE) == TIM9) && \
mbed_official 464:04583941e294 8993 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 464:04583941e294 8994 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 464:04583941e294 8995 || \
mbed_official 464:04583941e294 8996 (((INSTANCE) == TIM10) && \
mbed_official 464:04583941e294 8997 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 464:04583941e294 8998 || \
mbed_official 464:04583941e294 8999 (((INSTANCE) == TIM11) && \
mbed_official 464:04583941e294 9000 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 464:04583941e294 9001 || \
mbed_official 464:04583941e294 9002 (((INSTANCE) == TIM12) && \
mbed_official 464:04583941e294 9003 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 464:04583941e294 9004 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 464:04583941e294 9005 || \
mbed_official 464:04583941e294 9006 (((INSTANCE) == TIM13) && \
mbed_official 464:04583941e294 9007 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 464:04583941e294 9008 || \
mbed_official 464:04583941e294 9009 (((INSTANCE) == TIM14) && \
mbed_official 464:04583941e294 9010 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 464:04583941e294 9011
mbed_official 464:04583941e294 9012 /************ TIM Instances : complementary output(s) available ***************/
mbed_official 464:04583941e294 9013 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 464:04583941e294 9014 ((((INSTANCE) == TIM1) && \
mbed_official 464:04583941e294 9015 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 464:04583941e294 9016 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 464:04583941e294 9017 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 464:04583941e294 9018 || \
mbed_official 464:04583941e294 9019 (((INSTANCE) == TIM8) && \
mbed_official 464:04583941e294 9020 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 464:04583941e294 9021 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 464:04583941e294 9022 ((CHANNEL) == TIM_CHANNEL_3))))
mbed_official 464:04583941e294 9023
mbed_official 464:04583941e294 9024 /******************** USART Instances : Synchronous mode **********************/
mbed_official 464:04583941e294 9025 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 464:04583941e294 9026 ((INSTANCE) == USART2) || \
mbed_official 464:04583941e294 9027 ((INSTANCE) == USART3) || \
mbed_official 464:04583941e294 9028 ((INSTANCE) == USART6))
mbed_official 464:04583941e294 9029
mbed_official 464:04583941e294 9030 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 464:04583941e294 9031 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 464:04583941e294 9032 ((INSTANCE) == USART2) || \
mbed_official 464:04583941e294 9033 ((INSTANCE) == USART3) || \
mbed_official 464:04583941e294 9034 ((INSTANCE) == UART4) || \
mbed_official 464:04583941e294 9035 ((INSTANCE) == UART5) || \
mbed_official 464:04583941e294 9036 ((INSTANCE) == USART6) || \
mbed_official 464:04583941e294 9037 ((INSTANCE) == UART7) || \
mbed_official 464:04583941e294 9038 ((INSTANCE) == UART8))
mbed_official 464:04583941e294 9039
mbed_official 464:04583941e294 9040 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 464:04583941e294 9041 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 464:04583941e294 9042 ((INSTANCE) == USART2) || \
mbed_official 464:04583941e294 9043 ((INSTANCE) == USART3) || \
mbed_official 464:04583941e294 9044 ((INSTANCE) == USART6))
mbed_official 464:04583941e294 9045
mbed_official 464:04583941e294 9046 /********************* UART Instances : Smard card mode ***********************/
mbed_official 464:04583941e294 9047 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 464:04583941e294 9048 ((INSTANCE) == USART2) || \
mbed_official 464:04583941e294 9049 ((INSTANCE) == USART3) || \
mbed_official 464:04583941e294 9050 ((INSTANCE) == USART6))
mbed_official 464:04583941e294 9051
mbed_official 464:04583941e294 9052 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 464:04583941e294 9053 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 464:04583941e294 9054 ((INSTANCE) == USART2) || \
mbed_official 464:04583941e294 9055 ((INSTANCE) == USART3) || \
mbed_official 464:04583941e294 9056 ((INSTANCE) == UART4) || \
mbed_official 464:04583941e294 9057 ((INSTANCE) == UART5) || \
mbed_official 464:04583941e294 9058 ((INSTANCE) == USART6) || \
mbed_official 464:04583941e294 9059 ((INSTANCE) == UART7) || \
mbed_official 464:04583941e294 9060 ((INSTANCE) == UART8))
mbed_official 464:04583941e294 9061
mbed_official 464:04583941e294 9062 /****************************** IWDG Instances ********************************/
mbed_official 464:04583941e294 9063 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 464:04583941e294 9064
mbed_official 464:04583941e294 9065 /****************************** WWDG Instances ********************************/
mbed_official 464:04583941e294 9066 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 464:04583941e294 9067
mbed_official 464:04583941e294 9068 /******************************************************************************/
mbed_official 464:04583941e294 9069 /* For a painless codes migration between the STM32F4xx device product */
mbed_official 464:04583941e294 9070 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 464:04583941e294 9071 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 464:04583941e294 9072 /* No need to update developed interrupt code when moving across */
mbed_official 464:04583941e294 9073 /* product lines within the same STM32F4 Family */
mbed_official 464:04583941e294 9074 /******************************************************************************/
mbed_official 464:04583941e294 9075
mbed_official 464:04583941e294 9076 /* Aliases for __IRQn */
mbed_official 464:04583941e294 9077 #define FSMC_IRQn FMC_IRQn
mbed_official 464:04583941e294 9078
mbed_official 464:04583941e294 9079 /* Aliases for __IRQHandler */
mbed_official 464:04583941e294 9080 #define FSMC_IRQHandler FMC_IRQHandler
mbed_official 464:04583941e294 9081
mbed_official 464:04583941e294 9082 /**
mbed_official 464:04583941e294 9083 * @}
mbed_official 464:04583941e294 9084 */
mbed_official 464:04583941e294 9085
mbed_official 464:04583941e294 9086 /**
mbed_official 464:04583941e294 9087 * @}
mbed_official 464:04583941e294 9088 */
mbed_official 464:04583941e294 9089
mbed_official 464:04583941e294 9090 /**
mbed_official 464:04583941e294 9091 * @}
mbed_official 464:04583941e294 9092 */
mbed_official 464:04583941e294 9093
mbed_official 464:04583941e294 9094 #ifdef __cplusplus
mbed_official 464:04583941e294 9095 }
mbed_official 464:04583941e294 9096 #endif /* __cplusplus */
mbed_official 464:04583941e294 9097
mbed_official 464:04583941e294 9098 #endif /* __STM32F439xx_H */
mbed_official 464:04583941e294 9099
mbed_official 464:04583941e294 9100
mbed_official 464:04583941e294 9101
mbed_official 464:04583941e294 9102 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/