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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F072RB/system_stm32f0xx.c@205:c41fc65bcfb4, 2014-05-22 (annotated)

Committer:
mbed_official
Date:
Thu May 22 20:00:09 2014 +0100
Revision:
205:c41fc65bcfb4
Child:
218:44081b78fdc2
Synchronized with git revision ea4b6f76efab17a3f7d7777b0cc1ef05fec6d1cb



Full URL: https://github.com/mbedmicro/mbed/commit/ea4b6f76efab17a3f7d7777b0cc1ef05fec6d1cb/



[NUCLEO_F072RB] cmsis files

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UserRevisionLine numberNew contents of line
mbed_official 205:c41fc65bcfb4 1 /**
mbed_official 205:c41fc65bcfb4 2 ******************************************************************************
mbed_official 205:c41fc65bcfb4 3 * @file system_stm32f0xx.c
mbed_official 205:c41fc65bcfb4 4 * @author MCD Application Team
mbed_official 205:c41fc65bcfb4 5 * @version $VERSION$
mbed_official 205:c41fc65bcfb4 6 * @date $DATE$
mbed_official 205:c41fc65bcfb4 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
mbed_official 205:c41fc65bcfb4 8 *
mbed_official 205:c41fc65bcfb4 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 205:c41fc65bcfb4 10 * user application:
mbed_official 205:c41fc65bcfb4 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 205:c41fc65bcfb4 12 * before branch to main program. This call is made inside
mbed_official 205:c41fc65bcfb4 13 * the "startup_stm32f0xx.s" file.
mbed_official 205:c41fc65bcfb4 14 *
mbed_official 205:c41fc65bcfb4 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 205:c41fc65bcfb4 16 * by the user application to setup the SysTick
mbed_official 205:c41fc65bcfb4 17 * timer or configure other parameters.
mbed_official 205:c41fc65bcfb4 18 *
mbed_official 205:c41fc65bcfb4 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 205:c41fc65bcfb4 20 * be called whenever the core clock is changed
mbed_official 205:c41fc65bcfb4 21 * during program execution.
mbed_official 205:c41fc65bcfb4 22 *
mbed_official 205:c41fc65bcfb4 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 205:c41fc65bcfb4 24 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
mbed_official 205:c41fc65bcfb4 25 * configure the system clock before to branch to main program.
mbed_official 205:c41fc65bcfb4 26 *
mbed_official 205:c41fc65bcfb4 27 * 3. This file configures the system clock as follows:
mbed_official 205:c41fc65bcfb4 28 *=============================================================================
mbed_official 205:c41fc65bcfb4 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 205:c41fc65bcfb4 30 * | (external 8 MHz clock) | (internal 48 MHz)
mbed_official 205:c41fc65bcfb4 31 * | 2- PLL_HSE_XTAL |
mbed_official 205:c41fc65bcfb4 32 * | (external 8 MHz xtal) |
mbed_official 205:c41fc65bcfb4 33 *-----------------------------------------------------------------------------
mbed_official 205:c41fc65bcfb4 34 * SYSCLK(MHz) | 48 | 48
mbed_official 205:c41fc65bcfb4 35 *-----------------------------------------------------------------------------
mbed_official 205:c41fc65bcfb4 36 * AHBCLK (MHz) | 48 | 48
mbed_official 205:c41fc65bcfb4 37 *-----------------------------------------------------------------------------
mbed_official 205:c41fc65bcfb4 38 * APB1CLK (MHz) | 48 | 48
mbed_official 205:c41fc65bcfb4 39 *-----------------------------------------------------------------------------
mbed_official 205:c41fc65bcfb4 40 * USB capable (48 MHz precise clock) | YES | YES
mbed_official 205:c41fc65bcfb4 41 *=============================================================================
mbed_official 205:c41fc65bcfb4 42 ******************************************************************************
mbed_official 205:c41fc65bcfb4 43 * @attention
mbed_official 205:c41fc65bcfb4 44 *
mbed_official 205:c41fc65bcfb4 45 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 205:c41fc65bcfb4 46 *
mbed_official 205:c41fc65bcfb4 47 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 205:c41fc65bcfb4 48 * are permitted provided that the following conditions are met:
mbed_official 205:c41fc65bcfb4 49 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 205:c41fc65bcfb4 50 * this list of conditions and the following disclaimer.
mbed_official 205:c41fc65bcfb4 51 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 205:c41fc65bcfb4 52 * this list of conditions and the following disclaimer in the documentation
mbed_official 205:c41fc65bcfb4 53 * and/or other materials provided with the distribution.
mbed_official 205:c41fc65bcfb4 54 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 205:c41fc65bcfb4 55 * may be used to endorse or promote products derived from this software
mbed_official 205:c41fc65bcfb4 56 * without specific prior written permission.
mbed_official 205:c41fc65bcfb4 57 *
mbed_official 205:c41fc65bcfb4 58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 205:c41fc65bcfb4 59 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 205:c41fc65bcfb4 60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 205:c41fc65bcfb4 61 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 205:c41fc65bcfb4 62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 205:c41fc65bcfb4 63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 205:c41fc65bcfb4 64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 205:c41fc65bcfb4 65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 205:c41fc65bcfb4 66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 205:c41fc65bcfb4 67 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 205:c41fc65bcfb4 68 *
mbed_official 205:c41fc65bcfb4 69 ******************************************************************************
mbed_official 205:c41fc65bcfb4 70 */
mbed_official 205:c41fc65bcfb4 71
mbed_official 205:c41fc65bcfb4 72 /** @addtogroup CMSIS
mbed_official 205:c41fc65bcfb4 73 * @{
mbed_official 205:c41fc65bcfb4 74 */
mbed_official 205:c41fc65bcfb4 75
mbed_official 205:c41fc65bcfb4 76 /** @addtogroup stm32f0xx_system
mbed_official 205:c41fc65bcfb4 77 * @{
mbed_official 205:c41fc65bcfb4 78 */
mbed_official 205:c41fc65bcfb4 79
mbed_official 205:c41fc65bcfb4 80 /** @addtogroup STM32F0xx_System_Private_Includes
mbed_official 205:c41fc65bcfb4 81 * @{
mbed_official 205:c41fc65bcfb4 82 */
mbed_official 205:c41fc65bcfb4 83
mbed_official 205:c41fc65bcfb4 84 #include "stm32f0xx.h"
mbed_official 205:c41fc65bcfb4 85
mbed_official 205:c41fc65bcfb4 86 /**
mbed_official 205:c41fc65bcfb4 87 * @}
mbed_official 205:c41fc65bcfb4 88 */
mbed_official 205:c41fc65bcfb4 89
mbed_official 205:c41fc65bcfb4 90 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
mbed_official 205:c41fc65bcfb4 91 * @{
mbed_official 205:c41fc65bcfb4 92 */
mbed_official 205:c41fc65bcfb4 93
mbed_official 205:c41fc65bcfb4 94 /**
mbed_official 205:c41fc65bcfb4 95 * @}
mbed_official 205:c41fc65bcfb4 96 */
mbed_official 205:c41fc65bcfb4 97
mbed_official 205:c41fc65bcfb4 98 /** @addtogroup STM32F0xx_System_Private_Defines
mbed_official 205:c41fc65bcfb4 99 * @{
mbed_official 205:c41fc65bcfb4 100 */
mbed_official 205:c41fc65bcfb4 101 #if !defined (HSE_VALUE)
mbed_official 205:c41fc65bcfb4 102 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official 205:c41fc65bcfb4 103 This value can be provided and adapted by the user application. */
mbed_official 205:c41fc65bcfb4 104 #endif /* HSE_VALUE */
mbed_official 205:c41fc65bcfb4 105
mbed_official 205:c41fc65bcfb4 106 #if !defined (HSI_VALUE)
mbed_official 205:c41fc65bcfb4 107 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official 205:c41fc65bcfb4 108 This value can be provided and adapted by the user application. */
mbed_official 205:c41fc65bcfb4 109 #endif /* HSI_VALUE */
mbed_official 205:c41fc65bcfb4 110 /**
mbed_official 205:c41fc65bcfb4 111 * @}
mbed_official 205:c41fc65bcfb4 112 */
mbed_official 205:c41fc65bcfb4 113
mbed_official 205:c41fc65bcfb4 114 /** @addtogroup STM32F0xx_System_Private_Macros
mbed_official 205:c41fc65bcfb4 115 * @{
mbed_official 205:c41fc65bcfb4 116 */
mbed_official 205:c41fc65bcfb4 117
mbed_official 205:c41fc65bcfb4 118 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 205:c41fc65bcfb4 119 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 205:c41fc65bcfb4 120 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 205:c41fc65bcfb4 121
mbed_official 205:c41fc65bcfb4 122 /**
mbed_official 205:c41fc65bcfb4 123 * @}
mbed_official 205:c41fc65bcfb4 124 */
mbed_official 205:c41fc65bcfb4 125
mbed_official 205:c41fc65bcfb4 126 /** @addtogroup STM32F0xx_System_Private_Variables
mbed_official 205:c41fc65bcfb4 127 * @{
mbed_official 205:c41fc65bcfb4 128 */
mbed_official 205:c41fc65bcfb4 129 /* This variable is updated in three ways:
mbed_official 205:c41fc65bcfb4 130 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 205:c41fc65bcfb4 131 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 205:c41fc65bcfb4 132 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 205:c41fc65bcfb4 133 Note: If you use this function to configure the system clock; then there
mbed_official 205:c41fc65bcfb4 134 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 205:c41fc65bcfb4 135 variable is updated automatically.
mbed_official 205:c41fc65bcfb4 136 */
mbed_official 205:c41fc65bcfb4 137 uint32_t SystemCoreClock = 48000000;
mbed_official 205:c41fc65bcfb4 138 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 205:c41fc65bcfb4 139
mbed_official 205:c41fc65bcfb4 140 /**
mbed_official 205:c41fc65bcfb4 141 * @}
mbed_official 205:c41fc65bcfb4 142 */
mbed_official 205:c41fc65bcfb4 143
mbed_official 205:c41fc65bcfb4 144 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
mbed_official 205:c41fc65bcfb4 145 * @{
mbed_official 205:c41fc65bcfb4 146 */
mbed_official 205:c41fc65bcfb4 147
mbed_official 205:c41fc65bcfb4 148 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 205:c41fc65bcfb4 149 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 205:c41fc65bcfb4 150 #endif
mbed_official 205:c41fc65bcfb4 151
mbed_official 205:c41fc65bcfb4 152 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 205:c41fc65bcfb4 153
mbed_official 205:c41fc65bcfb4 154 /**
mbed_official 205:c41fc65bcfb4 155 * @}
mbed_official 205:c41fc65bcfb4 156 */
mbed_official 205:c41fc65bcfb4 157
mbed_official 205:c41fc65bcfb4 158 /** @addtogroup STM32F0xx_System_Private_Functions
mbed_official 205:c41fc65bcfb4 159 * @{
mbed_official 205:c41fc65bcfb4 160 */
mbed_official 205:c41fc65bcfb4 161
mbed_official 205:c41fc65bcfb4 162 /**
mbed_official 205:c41fc65bcfb4 163 * @brief Setup the microcontroller system.
mbed_official 205:c41fc65bcfb4 164 * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
mbed_official 205:c41fc65bcfb4 165 * @param None
mbed_official 205:c41fc65bcfb4 166 * @retval None
mbed_official 205:c41fc65bcfb4 167 */
mbed_official 205:c41fc65bcfb4 168 void SystemInit(void)
mbed_official 205:c41fc65bcfb4 169 {
mbed_official 205:c41fc65bcfb4 170 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 205:c41fc65bcfb4 171 /* Set HSION bit */
mbed_official 205:c41fc65bcfb4 172 RCC->CR |= (uint32_t)0x00000001;
mbed_official 205:c41fc65bcfb4 173
mbed_official 205:c41fc65bcfb4 174 #if defined (STM32F051x8) || defined (STM32F058x8)
mbed_official 205:c41fc65bcfb4 175 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
mbed_official 205:c41fc65bcfb4 176 RCC->CFGR &= (uint32_t)0xF8FFB80C;
mbed_official 205:c41fc65bcfb4 177 #else
mbed_official 205:c41fc65bcfb4 178 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
mbed_official 205:c41fc65bcfb4 179 RCC->CFGR &= (uint32_t)0x08FFB80C;
mbed_official 205:c41fc65bcfb4 180 #endif /* STM32F051x8 or STM32F058x8 */
mbed_official 205:c41fc65bcfb4 181
mbed_official 205:c41fc65bcfb4 182 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 205:c41fc65bcfb4 183 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 205:c41fc65bcfb4 184
mbed_official 205:c41fc65bcfb4 185 /* Reset HSEBYP bit */
mbed_official 205:c41fc65bcfb4 186 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 205:c41fc65bcfb4 187
mbed_official 205:c41fc65bcfb4 188 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official 205:c41fc65bcfb4 189 RCC->CFGR &= (uint32_t)0xFFC0FFFF;
mbed_official 205:c41fc65bcfb4 190
mbed_official 205:c41fc65bcfb4 191 /* Reset PREDIV[3:0] bits */
mbed_official 205:c41fc65bcfb4 192 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 205:c41fc65bcfb4 193
mbed_official 205:c41fc65bcfb4 194 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
mbed_official 205:c41fc65bcfb4 195 /* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official 205:c41fc65bcfb4 196 RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
mbed_official 205:c41fc65bcfb4 197 #elif defined (STM32F091xC)
mbed_official 205:c41fc65bcfb4 198 /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
mbed_official 205:c41fc65bcfb4 199 RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
mbed_official 205:c41fc65bcfb4 200 #else
mbed_official 205:c41fc65bcfb4 201 /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official 205:c41fc65bcfb4 202 RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
mbed_official 205:c41fc65bcfb4 203 #endif
mbed_official 205:c41fc65bcfb4 204
mbed_official 205:c41fc65bcfb4 205 /* Reset HSI14 bit */
mbed_official 205:c41fc65bcfb4 206 RCC->CR2 &= (uint32_t)0xFFFFFFFE;
mbed_official 205:c41fc65bcfb4 207
mbed_official 205:c41fc65bcfb4 208 /* Disable all interrupts */
mbed_official 205:c41fc65bcfb4 209 RCC->CIR = 0x00000000;
mbed_official 205:c41fc65bcfb4 210
mbed_official 205:c41fc65bcfb4 211 /* Configure the Cube driver */
mbed_official 205:c41fc65bcfb4 212 HAL_Init();
mbed_official 205:c41fc65bcfb4 213
mbed_official 205:c41fc65bcfb4 214 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 205:c41fc65bcfb4 215 AHB/APBx prescalers and Flash settings */
mbed_official 205:c41fc65bcfb4 216 SetSysClock();
mbed_official 205:c41fc65bcfb4 217 }
mbed_official 205:c41fc65bcfb4 218
mbed_official 205:c41fc65bcfb4 219 /**
mbed_official 205:c41fc65bcfb4 220 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 205:c41fc65bcfb4 221 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 205:c41fc65bcfb4 222 * be used by the user application to setup the SysTick timer or configure
mbed_official 205:c41fc65bcfb4 223 * other parameters.
mbed_official 205:c41fc65bcfb4 224 *
mbed_official 205:c41fc65bcfb4 225 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 205:c41fc65bcfb4 226 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 205:c41fc65bcfb4 227 * based on this variable will be incorrect.
mbed_official 205:c41fc65bcfb4 228 *
mbed_official 205:c41fc65bcfb4 229 * @note - The system frequency computed by this function is not the real
mbed_official 205:c41fc65bcfb4 230 * frequency in the chip. It is calculated based on the predefined
mbed_official 205:c41fc65bcfb4 231 * constant and the selected clock source:
mbed_official 205:c41fc65bcfb4 232 *
mbed_official 205:c41fc65bcfb4 233 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 205:c41fc65bcfb4 234 *
mbed_official 205:c41fc65bcfb4 235 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 205:c41fc65bcfb4 236 *
mbed_official 205:c41fc65bcfb4 237 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 205:c41fc65bcfb4 238 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 205:c41fc65bcfb4 239 *
mbed_official 205:c41fc65bcfb4 240 * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official 205:c41fc65bcfb4 241 * 8 MHz) but the real value may vary depending on the variations
mbed_official 205:c41fc65bcfb4 242 * in voltage and temperature.
mbed_official 205:c41fc65bcfb4 243 *
mbed_official 205:c41fc65bcfb4 244 * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official 205:c41fc65bcfb4 245 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 205:c41fc65bcfb4 246 * frequency of the crystal used. Otherwise, this function may
mbed_official 205:c41fc65bcfb4 247 * have wrong result.
mbed_official 205:c41fc65bcfb4 248 *
mbed_official 205:c41fc65bcfb4 249 * - The result of this function could be not correct when using fractional
mbed_official 205:c41fc65bcfb4 250 * value for HSE crystal.
mbed_official 205:c41fc65bcfb4 251 *
mbed_official 205:c41fc65bcfb4 252 * @param None
mbed_official 205:c41fc65bcfb4 253 * @retval None
mbed_official 205:c41fc65bcfb4 254 */
mbed_official 205:c41fc65bcfb4 255 void SystemCoreClockUpdate (void)
mbed_official 205:c41fc65bcfb4 256 {
mbed_official 205:c41fc65bcfb4 257 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
mbed_official 205:c41fc65bcfb4 258
mbed_official 205:c41fc65bcfb4 259 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 205:c41fc65bcfb4 260 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 205:c41fc65bcfb4 261
mbed_official 205:c41fc65bcfb4 262 switch (tmp)
mbed_official 205:c41fc65bcfb4 263 {
mbed_official 205:c41fc65bcfb4 264 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
mbed_official 205:c41fc65bcfb4 265 SystemCoreClock = HSI_VALUE;
mbed_official 205:c41fc65bcfb4 266 break;
mbed_official 205:c41fc65bcfb4 267 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 205:c41fc65bcfb4 268 SystemCoreClock = HSE_VALUE;
mbed_official 205:c41fc65bcfb4 269 break;
mbed_official 205:c41fc65bcfb4 270 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 205:c41fc65bcfb4 271 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 205:c41fc65bcfb4 272 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 205:c41fc65bcfb4 273 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 205:c41fc65bcfb4 274 pllmull = ( pllmull >> 18) + 2;
mbed_official 205:c41fc65bcfb4 275
mbed_official 205:c41fc65bcfb4 276 if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
mbed_official 205:c41fc65bcfb4 277 {
mbed_official 205:c41fc65bcfb4 278 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 205:c41fc65bcfb4 279 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 205:c41fc65bcfb4 280 }
mbed_official 205:c41fc65bcfb4 281 else
mbed_official 205:c41fc65bcfb4 282 {
mbed_official 205:c41fc65bcfb4 283 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 205:c41fc65bcfb4 284 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 205:c41fc65bcfb4 285 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
mbed_official 205:c41fc65bcfb4 286 }
mbed_official 205:c41fc65bcfb4 287 break;
mbed_official 205:c41fc65bcfb4 288 default: /* HSI used as system clock */
mbed_official 205:c41fc65bcfb4 289 SystemCoreClock = HSI_VALUE;
mbed_official 205:c41fc65bcfb4 290 break;
mbed_official 205:c41fc65bcfb4 291 }
mbed_official 205:c41fc65bcfb4 292 /* Compute HCLK clock frequency ----------------*/
mbed_official 205:c41fc65bcfb4 293 /* Get HCLK prescaler */
mbed_official 205:c41fc65bcfb4 294 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 205:c41fc65bcfb4 295 /* HCLK clock frequency */
mbed_official 205:c41fc65bcfb4 296 SystemCoreClock >>= tmp;
mbed_official 205:c41fc65bcfb4 297 }
mbed_official 205:c41fc65bcfb4 298
mbed_official 205:c41fc65bcfb4 299 /**
mbed_official 205:c41fc65bcfb4 300 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 205:c41fc65bcfb4 301 * AHB/APBx prescalers and Flash settings
mbed_official 205:c41fc65bcfb4 302 * @note This function should be called only once the RCC clock configuration
mbed_official 205:c41fc65bcfb4 303 * is reset to the default reset state (done in SystemInit() function).
mbed_official 205:c41fc65bcfb4 304 * @param None
mbed_official 205:c41fc65bcfb4 305 * @retval None
mbed_official 205:c41fc65bcfb4 306 */
mbed_official 205:c41fc65bcfb4 307 void SetSysClock(void)
mbed_official 205:c41fc65bcfb4 308 {
mbed_official 205:c41fc65bcfb4 309 /* 1- Try to start with HSE and external clock */
mbed_official 205:c41fc65bcfb4 310 #if USE_PLL_HSE_EXTC != 0
mbed_official 205:c41fc65bcfb4 311 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 205:c41fc65bcfb4 312 #endif
mbed_official 205:c41fc65bcfb4 313 {
mbed_official 205:c41fc65bcfb4 314 /* 2- If fail try to start with HSE and external xtal */
mbed_official 205:c41fc65bcfb4 315 #if USE_PLL_HSE_XTAL != 0
mbed_official 205:c41fc65bcfb4 316 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 205:c41fc65bcfb4 317 #endif
mbed_official 205:c41fc65bcfb4 318 {
mbed_official 205:c41fc65bcfb4 319 /* 3- If fail start with HSI clock */
mbed_official 205:c41fc65bcfb4 320 if (SetSysClock_PLL_HSI() == 0)
mbed_official 205:c41fc65bcfb4 321 {
mbed_official 205:c41fc65bcfb4 322 while(1)
mbed_official 205:c41fc65bcfb4 323 {
mbed_official 205:c41fc65bcfb4 324 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 205:c41fc65bcfb4 325 }
mbed_official 205:c41fc65bcfb4 326 }
mbed_official 205:c41fc65bcfb4 327 }
mbed_official 205:c41fc65bcfb4 328 }
mbed_official 205:c41fc65bcfb4 329
mbed_official 205:c41fc65bcfb4 330 // Output clock on MCO pin(PA8) for debugging purpose
mbed_official 205:c41fc65bcfb4 331 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
mbed_official 205:c41fc65bcfb4 332 }
mbed_official 205:c41fc65bcfb4 333
mbed_official 205:c41fc65bcfb4 334 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 205:c41fc65bcfb4 335 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 336 /* PLL (clocked by HSE) used as System clock source */
mbed_official 205:c41fc65bcfb4 337 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 338 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 205:c41fc65bcfb4 339 {
mbed_official 205:c41fc65bcfb4 340 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 205:c41fc65bcfb4 341 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 205:c41fc65bcfb4 342
mbed_official 205:c41fc65bcfb4 343 // Select HSE oscillator as PLL source
mbed_official 205:c41fc65bcfb4 344 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
mbed_official 205:c41fc65bcfb4 345 if (bypass == 0) {
mbed_official 205:c41fc65bcfb4 346 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
mbed_official 205:c41fc65bcfb4 347 } else {
mbed_official 205:c41fc65bcfb4 348 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
mbed_official 205:c41fc65bcfb4 349 }
mbed_official 205:c41fc65bcfb4 350 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
mbed_official 205:c41fc65bcfb4 351 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 205:c41fc65bcfb4 352 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 205:c41fc65bcfb4 353 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
mbed_official 205:c41fc65bcfb4 354 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
mbed_official 205:c41fc65bcfb4 355 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official 205:c41fc65bcfb4 356 return 0; // FAIL
mbed_official 205:c41fc65bcfb4 357 }
mbed_official 205:c41fc65bcfb4 358
mbed_official 205:c41fc65bcfb4 359 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official 205:c41fc65bcfb4 360 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
mbed_official 205:c41fc65bcfb4 361 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official 205:c41fc65bcfb4 362 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official 205:c41fc65bcfb4 363 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official 205:c41fc65bcfb4 364 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official 205:c41fc65bcfb4 365 return 0; // FAIL
mbed_official 205:c41fc65bcfb4 366 }
mbed_official 205:c41fc65bcfb4 367
mbed_official 205:c41fc65bcfb4 368 // Output clock on MCO pin(PA8) for debugging purpose
mbed_official 205:c41fc65bcfb4 369 //if (bypass == 0)
mbed_official 205:c41fc65bcfb4 370 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz
mbed_official 205:c41fc65bcfb4 371 //else
mbed_official 205:c41fc65bcfb4 372 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz
mbed_official 205:c41fc65bcfb4 373
mbed_official 205:c41fc65bcfb4 374 return 1; // OK
mbed_official 205:c41fc65bcfb4 375 }
mbed_official 205:c41fc65bcfb4 376 #endif
mbed_official 205:c41fc65bcfb4 377
mbed_official 205:c41fc65bcfb4 378 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 379 /* PLL (clocked by HSI) used as System clock source */
mbed_official 205:c41fc65bcfb4 380 /******************************************************************************/
mbed_official 205:c41fc65bcfb4 381 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 205:c41fc65bcfb4 382 {
mbed_official 205:c41fc65bcfb4 383 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 205:c41fc65bcfb4 384 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 205:c41fc65bcfb4 385
mbed_official 205:c41fc65bcfb4 386 // Select HSI48 oscillator as PLL source
mbed_official 205:c41fc65bcfb4 387 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
mbed_official 205:c41fc65bcfb4 388 RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
mbed_official 205:c41fc65bcfb4 389 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 205:c41fc65bcfb4 390 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48;
mbed_official 205:c41fc65bcfb4 391 RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
mbed_official 205:c41fc65bcfb4 392 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
mbed_official 205:c41fc65bcfb4 393 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official 205:c41fc65bcfb4 394 return 0; // FAIL
mbed_official 205:c41fc65bcfb4 395 }
mbed_official 205:c41fc65bcfb4 396
mbed_official 205:c41fc65bcfb4 397 // Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official 205:c41fc65bcfb4 398 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
mbed_official 205:c41fc65bcfb4 399 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official 205:c41fc65bcfb4 400 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official 205:c41fc65bcfb4 401 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official 205:c41fc65bcfb4 402 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official 205:c41fc65bcfb4 403 return 0; // FAIL
mbed_official 205:c41fc65bcfb4 404 }
mbed_official 205:c41fc65bcfb4 405
mbed_official 205:c41fc65bcfb4 406 // Output clock on MCO1 pin(PA8) for debugging purpose
mbed_official 205:c41fc65bcfb4 407 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
mbed_official 205:c41fc65bcfb4 408
mbed_official 205:c41fc65bcfb4 409 return 1; // OK
mbed_official 205:c41fc65bcfb4 410 }
mbed_official 205:c41fc65bcfb4 411
mbed_official 205:c41fc65bcfb4 412 /* Used for the different timeouts in the HAL */
mbed_official 205:c41fc65bcfb4 413 void SysTick_Handler(void)
mbed_official 205:c41fc65bcfb4 414 {
mbed_official 205:c41fc65bcfb4 415 HAL_IncTick();
mbed_official 205:c41fc65bcfb4 416 }
mbed_official 205:c41fc65bcfb4 417
mbed_official 205:c41fc65bcfb4 418 /**
mbed_official 205:c41fc65bcfb4 419 * @}
mbed_official 205:c41fc65bcfb4 420 */
mbed_official 205:c41fc65bcfb4 421
mbed_official 205:c41fc65bcfb4 422 /**
mbed_official 205:c41fc65bcfb4 423 * @}
mbed_official 205:c41fc65bcfb4 424 */
mbed_official 205:c41fc65bcfb4 425
mbed_official 205:c41fc65bcfb4 426 /**
mbed_official 205:c41fc65bcfb4 427 * @}
mbed_official 205:c41fc65bcfb4 428 */
mbed_official 205:c41fc65bcfb4 429
mbed_official 205:c41fc65bcfb4 430 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 205:c41fc65bcfb4 431