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mbed w/ spi bug fig

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targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx.h@240:9a7c54113eaf, 2014-06-26 (annotated)

Committer:
mbed_official
Date:
Thu Jun 26 09:45:08 2014 +0100
Revision:
240:9a7c54113eaf
Parent:
130:1dec54e4aec3 
Synchronized with git revision 288cce7281f1f4bd5ab515fff36cdf6090bc4480



Full URL: https://github.com/mbedmicro/mbed/commit/288cce7281f1f4bd5ab515fff36cdf6090bc4480/



[DISCO-F051R8] Updated with F030R8 recent changes

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UserRevisionLine numberNew contents of line
mbed_official 130:1dec54e4aec3 1 /**
mbed_official 130:1dec54e4aec3 2 ******************************************************************************
mbed_official 130:1dec54e4aec3 3 * @file stm32f0xx.h
mbed_official 130:1dec54e4aec3 4 * @author MCD Application Team
mbed_official 130:1dec54e4aec3 5 * @version V1.3.1
mbed_official 130:1dec54e4aec3 6 * @date 17-January-2014
mbed_official 130:1dec54e4aec3 7 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
mbed_official 130:1dec54e4aec3 8 * This file contains all the peripheral register's definitions, bits
mbed_official 130:1dec54e4aec3 9 * definitions and memory mapping for STM32F0xx devices.
mbed_official 130:1dec54e4aec3 10 *
mbed_official 130:1dec54e4aec3 11 * The file is the unique include file that the application programmer
mbed_official 130:1dec54e4aec3 12 * is using in the C source code, usually in main.c. This file contains:
mbed_official 130:1dec54e4aec3 13 * - Configuration section that allows to select:
mbed_official 130:1dec54e4aec3 14 * - The device used in the target application
mbed_official 130:1dec54e4aec3 15 * - To use or not the peripheral’s drivers in application code(i.e.
mbed_official 130:1dec54e4aec3 16 * code will be based on direct access to peripheral’s registers
mbed_official 130:1dec54e4aec3 17 * rather than drivers API), this option is controlled by
mbed_official 130:1dec54e4aec3 18 * "#define USE_STDPERIPH_DRIVER"
mbed_official 130:1dec54e4aec3 19 * - To change few application-specific parameters such as the HSE
mbed_official 130:1dec54e4aec3 20 * crystal frequency
mbed_official 130:1dec54e4aec3 21 * - Data structures and the address mapping for all peripherals
mbed_official 130:1dec54e4aec3 22 * - Peripheral's registers declarations and bits definition
mbed_official 130:1dec54e4aec3 23 * - Macros to access peripheral’s registers hardware
mbed_official 130:1dec54e4aec3 24 *
mbed_official 130:1dec54e4aec3 25 ******************************************************************************
mbed_official 130:1dec54e4aec3 26 * @attention
mbed_official 130:1dec54e4aec3 27 *
mbed_official 130:1dec54e4aec3 28 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 130:1dec54e4aec3 29 *
mbed_official 130:1dec54e4aec3 30 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 130:1dec54e4aec3 31 * are permitted provided that the following conditions are met:
mbed_official 130:1dec54e4aec3 32 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 130:1dec54e4aec3 33 * this list of conditions and the following disclaimer.
mbed_official 130:1dec54e4aec3 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 130:1dec54e4aec3 35 * this list of conditions and the following disclaimer in the documentation
mbed_official 130:1dec54e4aec3 36 * and/or other materials provided with the distribution.
mbed_official 130:1dec54e4aec3 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 130:1dec54e4aec3 38 * may be used to endorse or promote products derived from this software
mbed_official 130:1dec54e4aec3 39 * without specific prior written permission.
mbed_official 130:1dec54e4aec3 40 *
mbed_official 130:1dec54e4aec3 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 130:1dec54e4aec3 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 130:1dec54e4aec3 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 130:1dec54e4aec3 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 130:1dec54e4aec3 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 130:1dec54e4aec3 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 130:1dec54e4aec3 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 130:1dec54e4aec3 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 130:1dec54e4aec3 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 130:1dec54e4aec3 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 130:1dec54e4aec3 51 *
mbed_official 130:1dec54e4aec3 52 ******************************************************************************
mbed_official 130:1dec54e4aec3 53 */
mbed_official 130:1dec54e4aec3 54
mbed_official 130:1dec54e4aec3 55 /** @addtogroup CMSIS
mbed_official 130:1dec54e4aec3 56 * @{
mbed_official 130:1dec54e4aec3 57 */
mbed_official 130:1dec54e4aec3 58
mbed_official 130:1dec54e4aec3 59 /** @addtogroup stm32f0xx
mbed_official 130:1dec54e4aec3 60 * @{
mbed_official 130:1dec54e4aec3 61 */
mbed_official 130:1dec54e4aec3 62
mbed_official 130:1dec54e4aec3 63 #ifndef __STM32F0XX_H
mbed_official 130:1dec54e4aec3 64 #define __STM32F0XX_H
mbed_official 130:1dec54e4aec3 65
mbed_official 130:1dec54e4aec3 66 #ifdef __cplusplus
mbed_official 130:1dec54e4aec3 67 extern "C" {
mbed_official 130:1dec54e4aec3 68 #endif
mbed_official 130:1dec54e4aec3 69
mbed_official 130:1dec54e4aec3 70 /** @addtogroup Library_configuration_section
mbed_official 130:1dec54e4aec3 71 * @{
mbed_official 130:1dec54e4aec3 72 */
mbed_official 130:1dec54e4aec3 73
mbed_official 130:1dec54e4aec3 74 /* Uncomment the line below according to the target STM32F0 device used in your
mbed_official 130:1dec54e4aec3 75 application
mbed_official 130:1dec54e4aec3 76 */
mbed_official 130:1dec54e4aec3 77
mbed_official 130:1dec54e4aec3 78 #if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
mbed_official 240:9a7c54113eaf 79 /* #define STM32F030 */
mbed_official 130:1dec54e4aec3 80 /* #define STM32F031 */
mbed_official 130:1dec54e4aec3 81 #define STM32F051
mbed_official 130:1dec54e4aec3 82 /* #define STM32F072 */
mbed_official 130:1dec54e4aec3 83 /* #define STM32F042 */
mbed_official 130:1dec54e4aec3 84 #endif
mbed_official 130:1dec54e4aec3 85
mbed_official 130:1dec54e4aec3 86 /* Tip: To avoid modifying this file each time you need to switch between these
mbed_official 130:1dec54e4aec3 87 devices, you can define the device in your toolchain compiler preprocessor.
mbed_official 130:1dec54e4aec3 88 */
mbed_official 130:1dec54e4aec3 89
mbed_official 130:1dec54e4aec3 90 /* Old STM32F0XX definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 91 #if defined(STM32F0XX) || defined(STM32F0XX_MD)
mbed_official 130:1dec54e4aec3 92 #define STM32F051
mbed_official 130:1dec54e4aec3 93 #endif /* STM32F0XX */
mbed_official 130:1dec54e4aec3 94
mbed_official 130:1dec54e4aec3 95 /* Old STM32F0XX_LD definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 96 #ifdef STM32F0XX_LD
mbed_official 130:1dec54e4aec3 97 #define STM32F031
mbed_official 130:1dec54e4aec3 98 #endif /* STM32F0XX_LD */
mbed_official 130:1dec54e4aec3 99
mbed_official 130:1dec54e4aec3 100 /* Old STM32F0XX_HD definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 101 #ifdef STM32F0XX_HD
mbed_official 130:1dec54e4aec3 102 #define STM32F072
mbed_official 130:1dec54e4aec3 103 #endif /* STM32F0XX_HD */
mbed_official 130:1dec54e4aec3 104
mbed_official 130:1dec54e4aec3 105 /* Old STM32F030X6/X8 definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 106 #if defined (STM32F030X8) || defined (STM32F030X6)
mbed_official 130:1dec54e4aec3 107 #define STM32F030
mbed_official 130:1dec54e4aec3 108 #endif /* STM32F030X8 or STM32F030X6 */
mbed_official 130:1dec54e4aec3 109
mbed_official 130:1dec54e4aec3 110
mbed_official 130:1dec54e4aec3 111 #if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
mbed_official 130:1dec54e4aec3 112 #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
mbed_official 130:1dec54e4aec3 113 #endif
mbed_official 130:1dec54e4aec3 114
mbed_official 130:1dec54e4aec3 115 #if !defined USE_STDPERIPH_DRIVER
mbed_official 130:1dec54e4aec3 116 /**
mbed_official 130:1dec54e4aec3 117 * @brief Comment the line below if you will not use the peripherals drivers.
mbed_official 130:1dec54e4aec3 118 In this case, these drivers will not be included and the application code will
mbed_official 130:1dec54e4aec3 119 be based on direct access to peripherals registers
mbed_official 130:1dec54e4aec3 120 */
mbed_official 130:1dec54e4aec3 121 #define USE_STDPERIPH_DRIVER
mbed_official 130:1dec54e4aec3 122 #endif /* USE_STDPERIPH_DRIVER */
mbed_official 130:1dec54e4aec3 123
mbed_official 130:1dec54e4aec3 124 /**
mbed_official 130:1dec54e4aec3 125 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
mbed_official 130:1dec54e4aec3 126 used in your application
mbed_official 130:1dec54e4aec3 127
mbed_official 130:1dec54e4aec3 128 Tip: To avoid modifying this file each time you need to use different HSE, you
mbed_official 130:1dec54e4aec3 129 can define the HSE value in your toolchain compiler preprocessor.
mbed_official 130:1dec54e4aec3 130 */
mbed_official 130:1dec54e4aec3 131 #if !defined (HSE_VALUE)
mbed_official 130:1dec54e4aec3 132 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
mbed_official 130:1dec54e4aec3 133 #endif /* HSE_VALUE */
mbed_official 130:1dec54e4aec3 134
mbed_official 130:1dec54e4aec3 135 /**
mbed_official 130:1dec54e4aec3 136 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
mbed_official 130:1dec54e4aec3 137 Timeout value
mbed_official 130:1dec54e4aec3 138 */
mbed_official 130:1dec54e4aec3 139 #if !defined (HSE_STARTUP_TIMEOUT)
mbed_official 130:1dec54e4aec3 140 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
mbed_official 130:1dec54e4aec3 141 #endif /* HSE_STARTUP_TIMEOUT */
mbed_official 130:1dec54e4aec3 142
mbed_official 130:1dec54e4aec3 143 /**
mbed_official 130:1dec54e4aec3 144 * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
mbed_official 130:1dec54e4aec3 145 Timeout value
mbed_official 130:1dec54e4aec3 146 */
mbed_official 130:1dec54e4aec3 147 #if !defined (HSI_STARTUP_TIMEOUT)
mbed_official 130:1dec54e4aec3 148 #define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
mbed_official 130:1dec54e4aec3 149 #endif /* HSI_STARTUP_TIMEOUT */
mbed_official 130:1dec54e4aec3 150
mbed_official 130:1dec54e4aec3 151 #if !defined (HSI_VALUE)
mbed_official 130:1dec54e4aec3 152 #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
mbed_official 130:1dec54e4aec3 153 The real value may vary depending on the variations
mbed_official 130:1dec54e4aec3 154 in voltage and temperature. */
mbed_official 130:1dec54e4aec3 155 #endif /* HSI_VALUE */
mbed_official 130:1dec54e4aec3 156
mbed_official 130:1dec54e4aec3 157 #if !defined (HSI14_VALUE)
mbed_official 130:1dec54e4aec3 158 #define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
mbed_official 130:1dec54e4aec3 159 The real value may vary depending on the variations
mbed_official 130:1dec54e4aec3 160 in voltage and temperature. */
mbed_official 130:1dec54e4aec3 161 #endif /* HSI14_VALUE */
mbed_official 130:1dec54e4aec3 162
mbed_official 130:1dec54e4aec3 163 #if !defined (HSI48_VALUE)
mbed_official 130:1dec54e4aec3 164 #define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
mbed_official 130:1dec54e4aec3 165 The real value may vary depending on the variations
mbed_official 130:1dec54e4aec3 166 in voltage and temperature. */
mbed_official 130:1dec54e4aec3 167 #endif /* HSI48_VALUE */
mbed_official 130:1dec54e4aec3 168
mbed_official 130:1dec54e4aec3 169 #if !defined (LSI_VALUE)
mbed_official 130:1dec54e4aec3 170 #define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz
mbed_official 130:1dec54e4aec3 171 The real value may vary depending on the variations
mbed_official 130:1dec54e4aec3 172 in voltage and temperature. */
mbed_official 130:1dec54e4aec3 173 #endif /* LSI_VALUE */
mbed_official 130:1dec54e4aec3 174
mbed_official 130:1dec54e4aec3 175 #if !defined (LSE_VALUE)
mbed_official 130:1dec54e4aec3 176 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
mbed_official 130:1dec54e4aec3 177 #endif /* LSE_VALUE */
mbed_official 130:1dec54e4aec3 178
mbed_official 130:1dec54e4aec3 179 /**
mbed_official 130:1dec54e4aec3 180 * @brief STM32F0xx Standard Peripheral Library version number V1.3.1
mbed_official 130:1dec54e4aec3 181 */
mbed_official 130:1dec54e4aec3 182 #define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
mbed_official 130:1dec54e4aec3 183 #define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
mbed_official 130:1dec54e4aec3 184 #define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
mbed_official 130:1dec54e4aec3 185 #define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
mbed_official 130:1dec54e4aec3 186 #define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
mbed_official 130:1dec54e4aec3 187 |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
mbed_official 130:1dec54e4aec3 188 |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
mbed_official 130:1dec54e4aec3 189 |(__STM32F0XX_STDPERIPH_VERSION_RC))
mbed_official 130:1dec54e4aec3 190
mbed_official 130:1dec54e4aec3 191 /**
mbed_official 130:1dec54e4aec3 192 * @}
mbed_official 130:1dec54e4aec3 193 */
mbed_official 130:1dec54e4aec3 194
mbed_official 130:1dec54e4aec3 195 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 130:1dec54e4aec3 196 * @{
mbed_official 130:1dec54e4aec3 197 */
mbed_official 130:1dec54e4aec3 198
mbed_official 130:1dec54e4aec3 199 /**
mbed_official 130:1dec54e4aec3 200 * @brief STM32F0xx Interrupt Number Definition, according to the selected device
mbed_official 130:1dec54e4aec3 201 * in @ref Library_configuration_section
mbed_official 130:1dec54e4aec3 202 */
mbed_official 130:1dec54e4aec3 203 #define __CM0_REV 0 /*!< Core Revision r0p0 */
mbed_official 130:1dec54e4aec3 204 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
mbed_official 130:1dec54e4aec3 205 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
mbed_official 130:1dec54e4aec3 206 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 130:1dec54e4aec3 207
mbed_official 130:1dec54e4aec3 208 /*!< Interrupt Number Definition */
mbed_official 130:1dec54e4aec3 209 typedef enum IRQn
mbed_official 130:1dec54e4aec3 210 {
mbed_official 130:1dec54e4aec3 211 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
mbed_official 130:1dec54e4aec3 212 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 130:1dec54e4aec3 213 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
mbed_official 130:1dec54e4aec3 214 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
mbed_official 130:1dec54e4aec3 215 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
mbed_official 130:1dec54e4aec3 216 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
mbed_official 130:1dec54e4aec3 217
mbed_official 130:1dec54e4aec3 218 #if defined (STM32F051)
mbed_official 130:1dec54e4aec3 219 /****** STM32F051 specific Interrupt Numbers *************************************/
mbed_official 130:1dec54e4aec3 220 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 130:1dec54e4aec3 221 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
mbed_official 130:1dec54e4aec3 222 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
mbed_official 130:1dec54e4aec3 223 FLASH_IRQn = 3, /*!< FLASH Interrupt */
mbed_official 130:1dec54e4aec3 224 RCC_IRQn = 4, /*!< RCC Interrupt */
mbed_official 130:1dec54e4aec3 225 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
mbed_official 130:1dec54e4aec3 226 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
mbed_official 130:1dec54e4aec3 227 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
mbed_official 130:1dec54e4aec3 228 TS_IRQn = 8, /*!< Touch sense controller Interrupt */
mbed_official 130:1dec54e4aec3 229 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
mbed_official 130:1dec54e4aec3 230 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
mbed_official 130:1dec54e4aec3 231 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
mbed_official 130:1dec54e4aec3 232 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
mbed_official 130:1dec54e4aec3 233 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
mbed_official 130:1dec54e4aec3 234 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
mbed_official 130:1dec54e4aec3 235 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
mbed_official 130:1dec54e4aec3 236 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
mbed_official 130:1dec54e4aec3 237 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
mbed_official 130:1dec54e4aec3 238 TIM14_IRQn = 19, /*!< TIM14 Interrupt */
mbed_official 130:1dec54e4aec3 239 TIM15_IRQn = 20, /*!< TIM15 Interrupt */
mbed_official 130:1dec54e4aec3 240 TIM16_IRQn = 21, /*!< TIM16 Interrupt */
mbed_official 130:1dec54e4aec3 241 TIM17_IRQn = 22, /*!< TIM17 Interrupt */
mbed_official 130:1dec54e4aec3 242 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
mbed_official 130:1dec54e4aec3 243 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
mbed_official 130:1dec54e4aec3 244 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
mbed_official 130:1dec54e4aec3 245 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
mbed_official 130:1dec54e4aec3 246 USART1_IRQn = 27, /*!< USART1 Interrupt */
mbed_official 130:1dec54e4aec3 247 USART2_IRQn = 28, /*!< USART2 Interrupt */
mbed_official 130:1dec54e4aec3 248 CEC_IRQn = 30 /*!< CEC Interrupt */
mbed_official 130:1dec54e4aec3 249 #elif defined (STM32F031)
mbed_official 130:1dec54e4aec3 250 /****** STM32F031 specific Interrupt Numbers *************************************/
mbed_official 130:1dec54e4aec3 251 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 130:1dec54e4aec3 252 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
mbed_official 130:1dec54e4aec3 253 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
mbed_official 130:1dec54e4aec3 254 FLASH_IRQn = 3, /*!< FLASH Interrupt */
mbed_official 130:1dec54e4aec3 255 RCC_IRQn = 4, /*!< RCC Interrupt */
mbed_official 130:1dec54e4aec3 256 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
mbed_official 130:1dec54e4aec3 257 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
mbed_official 130:1dec54e4aec3 258 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
mbed_official 130:1dec54e4aec3 259 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
mbed_official 130:1dec54e4aec3 260 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
mbed_official 130:1dec54e4aec3 261 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
mbed_official 130:1dec54e4aec3 262 ADC1_IRQn = 12, /*!< ADC1 Interrupt */
mbed_official 130:1dec54e4aec3 263 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
mbed_official 130:1dec54e4aec3 264 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
mbed_official 130:1dec54e4aec3 265 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
mbed_official 130:1dec54e4aec3 266 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
mbed_official 130:1dec54e4aec3 267 TIM14_IRQn = 19, /*!< TIM14 Interrupt */
mbed_official 130:1dec54e4aec3 268 TIM16_IRQn = 21, /*!< TIM16 Interrupt */
mbed_official 130:1dec54e4aec3 269 TIM17_IRQn = 22, /*!< TIM17 Interrupt */
mbed_official 130:1dec54e4aec3 270 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
mbed_official 130:1dec54e4aec3 271 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
mbed_official 130:1dec54e4aec3 272 USART1_IRQn = 27 /*!< USART1 Interrupt */
mbed_official 130:1dec54e4aec3 273 #elif defined (STM32F030)
mbed_official 130:1dec54e4aec3 274 /****** STM32F030 specific Interrupt Numbers *************************************/
mbed_official 130:1dec54e4aec3 275 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 130:1dec54e4aec3 276 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
mbed_official 130:1dec54e4aec3 277 FLASH_IRQn = 3, /*!< FLASH Interrupt */
mbed_official 130:1dec54e4aec3 278 RCC_IRQn = 4, /*!< RCC Interrupt */
mbed_official 130:1dec54e4aec3 279 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
mbed_official 130:1dec54e4aec3 280 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
mbed_official 130:1dec54e4aec3 281 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
mbed_official 130:1dec54e4aec3 282 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
mbed_official 130:1dec54e4aec3 283 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
mbed_official 130:1dec54e4aec3 284 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
mbed_official 130:1dec54e4aec3 285 ADC1_IRQn = 12, /*!< ADC1 Interrupt */
mbed_official 130:1dec54e4aec3 286 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
mbed_official 130:1dec54e4aec3 287 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
mbed_official 130:1dec54e4aec3 288 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
mbed_official 130:1dec54e4aec3 289 TIM14_IRQn = 19, /*!< TIM14 Interrupt */
mbed_official 130:1dec54e4aec3 290 TIM15_IRQn = 20, /*!< TIM15 Interrupt */
mbed_official 130:1dec54e4aec3 291 TIM16_IRQn = 21, /*!< TIM16 Interrupt */
mbed_official 130:1dec54e4aec3 292 TIM17_IRQn = 22, /*!< TIM17 Interrupt */
mbed_official 130:1dec54e4aec3 293 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
mbed_official 130:1dec54e4aec3 294 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
mbed_official 130:1dec54e4aec3 295 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
mbed_official 130:1dec54e4aec3 296 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
mbed_official 130:1dec54e4aec3 297 USART1_IRQn = 27, /*!< USART1 Interrupt */
mbed_official 130:1dec54e4aec3 298 USART2_IRQn = 28 /*!< USART2 Interrupt */
mbed_official 130:1dec54e4aec3 299 #elif defined (STM32F072)
mbed_official 130:1dec54e4aec3 300 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 130:1dec54e4aec3 301 PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
mbed_official 130:1dec54e4aec3 302 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
mbed_official 130:1dec54e4aec3 303 FLASH_IRQn = 3, /*!< FLASH Interrupt */
mbed_official 130:1dec54e4aec3 304 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
mbed_official 130:1dec54e4aec3 305 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
mbed_official 130:1dec54e4aec3 306 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
mbed_official 130:1dec54e4aec3 307 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
mbed_official 130:1dec54e4aec3 308 TSC_IRQn = 8, /*!< TSC Interrupt */
mbed_official 130:1dec54e4aec3 309 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
mbed_official 130:1dec54e4aec3 310 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
mbed_official 130:1dec54e4aec3 311 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
mbed_official 130:1dec54e4aec3 312 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
mbed_official 130:1dec54e4aec3 313 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
mbed_official 130:1dec54e4aec3 314 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
mbed_official 130:1dec54e4aec3 315 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
mbed_official 130:1dec54e4aec3 316 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
mbed_official 130:1dec54e4aec3 317 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
mbed_official 130:1dec54e4aec3 318 TIM7_IRQn = 18, /*!< TIM7 Interrupts */
mbed_official 130:1dec54e4aec3 319 TIM14_IRQn = 19, /*!< TIM14 Interrupt */
mbed_official 130:1dec54e4aec3 320 TIM15_IRQn = 20, /*!< TIM15 Interrupt */
mbed_official 130:1dec54e4aec3 321 TIM16_IRQn = 21, /*!< TIM16 Interrupt */
mbed_official 130:1dec54e4aec3 322 TIM17_IRQn = 22, /*!< TIM17 Interrupt */
mbed_official 130:1dec54e4aec3 323 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
mbed_official 130:1dec54e4aec3 324 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
mbed_official 130:1dec54e4aec3 325 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
mbed_official 130:1dec54e4aec3 326 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
mbed_official 130:1dec54e4aec3 327 USART1_IRQn = 27, /*!< USART1 Interrupt */
mbed_official 130:1dec54e4aec3 328 USART2_IRQn = 28, /*!< USART2 Interrupt */
mbed_official 130:1dec54e4aec3 329 USART3_4_IRQn = 29, /*!< USART3 and USART4 Interrupts */
mbed_official 130:1dec54e4aec3 330 CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */
mbed_official 130:1dec54e4aec3 331 USB_IRQn = 31 /*!< USB Low Priority global Interrupt */
mbed_official 130:1dec54e4aec3 332 #elif defined (STM32F042)
mbed_official 130:1dec54e4aec3 333 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 130:1dec54e4aec3 334 PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
mbed_official 130:1dec54e4aec3 335 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
mbed_official 130:1dec54e4aec3 336 FLASH_IRQn = 3, /*!< FLASH Interrupt */
mbed_official 130:1dec54e4aec3 337 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
mbed_official 130:1dec54e4aec3 338 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
mbed_official 130:1dec54e4aec3 339 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
mbed_official 130:1dec54e4aec3 340 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
mbed_official 130:1dec54e4aec3 341 TSC_IRQn = 8, /*!< TSC Interrupt */
mbed_official 130:1dec54e4aec3 342 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
mbed_official 130:1dec54e4aec3 343 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
mbed_official 130:1dec54e4aec3 344 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4, Channel 5 Interrupts */
mbed_official 130:1dec54e4aec3 345 ADC1_IRQn = 12, /*!< ADC1 Interrupts */
mbed_official 130:1dec54e4aec3 346 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
mbed_official 130:1dec54e4aec3 347 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
mbed_official 130:1dec54e4aec3 348 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
mbed_official 130:1dec54e4aec3 349 TIM3_IRQn = 16, /*!< TIM3 Interrupt */
mbed_official 130:1dec54e4aec3 350 TIM14_IRQn = 19, /*!< TIM14 Interrupt */
mbed_official 130:1dec54e4aec3 351 TIM16_IRQn = 21, /*!< TIM16 Interrupt */
mbed_official 130:1dec54e4aec3 352 TIM17_IRQn = 22, /*!< TIM17 Interrupt */
mbed_official 130:1dec54e4aec3 353 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
mbed_official 130:1dec54e4aec3 354 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
mbed_official 130:1dec54e4aec3 355 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
mbed_official 130:1dec54e4aec3 356 USART1_IRQn = 27, /*!< USART1 Interrupt */
mbed_official 130:1dec54e4aec3 357 USART2_IRQn = 28, /*!< USART2 Interrupt */
mbed_official 130:1dec54e4aec3 358 CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */
mbed_official 130:1dec54e4aec3 359 USB_IRQn = 31 /*!< USB Low Priority global Interrupt */
mbed_official 130:1dec54e4aec3 360 #endif /* STM32F051 */
mbed_official 130:1dec54e4aec3 361 } IRQn_Type;
mbed_official 130:1dec54e4aec3 362
mbed_official 130:1dec54e4aec3 363 /**
mbed_official 130:1dec54e4aec3 364 * @}
mbed_official 130:1dec54e4aec3 365 */
mbed_official 130:1dec54e4aec3 366
mbed_official 130:1dec54e4aec3 367 #include "core_cm0.h"
mbed_official 130:1dec54e4aec3 368 #include "system_stm32f0xx.h"
mbed_official 130:1dec54e4aec3 369 #include <stdint.h>
mbed_official 130:1dec54e4aec3 370
mbed_official 130:1dec54e4aec3 371 /** @addtogroup Exported_types
mbed_official 130:1dec54e4aec3 372 * @{
mbed_official 130:1dec54e4aec3 373 */
mbed_official 130:1dec54e4aec3 374
mbed_official 130:1dec54e4aec3 375 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
mbed_official 130:1dec54e4aec3 376
mbed_official 130:1dec54e4aec3 377 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
mbed_official 130:1dec54e4aec3 378 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
mbed_official 130:1dec54e4aec3 379
mbed_official 130:1dec54e4aec3 380 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
mbed_official 130:1dec54e4aec3 381
mbed_official 130:1dec54e4aec3 382 /** @addtogroup Peripheral_registers_structures
mbed_official 130:1dec54e4aec3 383 * @{
mbed_official 130:1dec54e4aec3 384 */
mbed_official 130:1dec54e4aec3 385
mbed_official 130:1dec54e4aec3 386 /**
mbed_official 130:1dec54e4aec3 387 * @brief Analog to Digital Converter
mbed_official 130:1dec54e4aec3 388 */
mbed_official 130:1dec54e4aec3 389
mbed_official 130:1dec54e4aec3 390 typedef struct
mbed_official 130:1dec54e4aec3 391 {
mbed_official 130:1dec54e4aec3 392 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
mbed_official 130:1dec54e4aec3 393 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
mbed_official 130:1dec54e4aec3 394 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
mbed_official 130:1dec54e4aec3 395 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
mbed_official 130:1dec54e4aec3 396 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
mbed_official 130:1dec54e4aec3 397 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
mbed_official 130:1dec54e4aec3 398 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 130:1dec54e4aec3 399 uint32_t RESERVED2; /*!< Reserved, 0x1C */
mbed_official 130:1dec54e4aec3 400 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
mbed_official 130:1dec54e4aec3 401 uint32_t RESERVED3; /*!< Reserved, 0x24 */
mbed_official 130:1dec54e4aec3 402 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
mbed_official 130:1dec54e4aec3 403 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
mbed_official 130:1dec54e4aec3 404 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
mbed_official 130:1dec54e4aec3 405 } ADC_TypeDef;
mbed_official 130:1dec54e4aec3 406
mbed_official 130:1dec54e4aec3 407 typedef struct
mbed_official 130:1dec54e4aec3 408 {
mbed_official 130:1dec54e4aec3 409 __IO uint32_t CCR;
mbed_official 130:1dec54e4aec3 410 } ADC_Common_TypeDef;
mbed_official 130:1dec54e4aec3 411
mbed_official 130:1dec54e4aec3 412
mbed_official 130:1dec54e4aec3 413 /**
mbed_official 130:1dec54e4aec3 414 * @brief Controller Area Network TxMailBox
mbed_official 130:1dec54e4aec3 415 */
mbed_official 130:1dec54e4aec3 416 typedef struct
mbed_official 130:1dec54e4aec3 417 {
mbed_official 130:1dec54e4aec3 418 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 130:1dec54e4aec3 419 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 130:1dec54e4aec3 420 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 130:1dec54e4aec3 421 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 130:1dec54e4aec3 422 } CAN_TxMailBox_TypeDef;
mbed_official 130:1dec54e4aec3 423
mbed_official 130:1dec54e4aec3 424 /**
mbed_official 130:1dec54e4aec3 425 * @brief Controller Area Network FIFOMailBox
mbed_official 130:1dec54e4aec3 426 */
mbed_official 130:1dec54e4aec3 427 typedef struct
mbed_official 130:1dec54e4aec3 428 {
mbed_official 130:1dec54e4aec3 429 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 130:1dec54e4aec3 430 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 130:1dec54e4aec3 431 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 130:1dec54e4aec3 432 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 130:1dec54e4aec3 433 } CAN_FIFOMailBox_TypeDef;
mbed_official 130:1dec54e4aec3 434
mbed_official 130:1dec54e4aec3 435 /**
mbed_official 130:1dec54e4aec3 436 * @brief Controller Area Network FilterRegister
mbed_official 130:1dec54e4aec3 437 */
mbed_official 130:1dec54e4aec3 438 typedef struct
mbed_official 130:1dec54e4aec3 439 {
mbed_official 130:1dec54e4aec3 440 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 130:1dec54e4aec3 441 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 130:1dec54e4aec3 442 } CAN_FilterRegister_TypeDef;
mbed_official 130:1dec54e4aec3 443
mbed_official 130:1dec54e4aec3 444 /**
mbed_official 130:1dec54e4aec3 445 * @brief Controller Area Network
mbed_official 130:1dec54e4aec3 446 */
mbed_official 130:1dec54e4aec3 447 typedef struct
mbed_official 130:1dec54e4aec3 448 {
mbed_official 130:1dec54e4aec3 449 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 450 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 451 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 452 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 453 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 454 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 455 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 456 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 457 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 130:1dec54e4aec3 458 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 130:1dec54e4aec3 459 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 130:1dec54e4aec3 460 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 130:1dec54e4aec3 461 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 130:1dec54e4aec3 462 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 130:1dec54e4aec3 463 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 130:1dec54e4aec3 464 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 130:1dec54e4aec3 465 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 130:1dec54e4aec3 466 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 130:1dec54e4aec3 467 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 130:1dec54e4aec3 468 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 130:1dec54e4aec3 469 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 130:1dec54e4aec3 470 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 130:1dec54e4aec3 471 } CAN_TypeDef;
mbed_official 130:1dec54e4aec3 472
mbed_official 130:1dec54e4aec3 473 /**
mbed_official 130:1dec54e4aec3 474 * @brief HDMI-CEC
mbed_official 130:1dec54e4aec3 475 */
mbed_official 130:1dec54e4aec3 476
mbed_official 130:1dec54e4aec3 477 typedef struct
mbed_official 130:1dec54e4aec3 478 {
mbed_official 130:1dec54e4aec3 479 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
mbed_official 130:1dec54e4aec3 480 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
mbed_official 130:1dec54e4aec3 481 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
mbed_official 130:1dec54e4aec3 482 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
mbed_official 130:1dec54e4aec3 483 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
mbed_official 130:1dec54e4aec3 484 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
mbed_official 130:1dec54e4aec3 485 }CEC_TypeDef;
mbed_official 130:1dec54e4aec3 486
mbed_official 130:1dec54e4aec3 487 /**
mbed_official 130:1dec54e4aec3 488 * @brief Comparator
mbed_official 130:1dec54e4aec3 489 */
mbed_official 130:1dec54e4aec3 490
mbed_official 130:1dec54e4aec3 491 typedef struct
mbed_official 130:1dec54e4aec3 492 {
mbed_official 130:1dec54e4aec3 493 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 494 } COMP_TypeDef;
mbed_official 130:1dec54e4aec3 495
mbed_official 130:1dec54e4aec3 496
mbed_official 130:1dec54e4aec3 497 /**
mbed_official 130:1dec54e4aec3 498 * @brief CRC calculation unit
mbed_official 130:1dec54e4aec3 499 */
mbed_official 130:1dec54e4aec3 500
mbed_official 130:1dec54e4aec3 501 typedef struct
mbed_official 130:1dec54e4aec3 502 {
mbed_official 130:1dec54e4aec3 503 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 504 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 505 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 130:1dec54e4aec3 506 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 130:1dec54e4aec3 507 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 508 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 130:1dec54e4aec3 509 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 510 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 511 } CRC_TypeDef;
mbed_official 130:1dec54e4aec3 512
mbed_official 130:1dec54e4aec3 513 /**
mbed_official 130:1dec54e4aec3 514 * @brief Clock Recovery System
mbed_official 130:1dec54e4aec3 515 */
mbed_official 130:1dec54e4aec3 516 typedef struct
mbed_official 130:1dec54e4aec3 517 {
mbed_official 130:1dec54e4aec3 518 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 519 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 520 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 521 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 522 } CRS_TypeDef;
mbed_official 130:1dec54e4aec3 523
mbed_official 130:1dec54e4aec3 524 /**
mbed_official 130:1dec54e4aec3 525 * @brief Digital to Analog Converter
mbed_official 130:1dec54e4aec3 526 */
mbed_official 130:1dec54e4aec3 527
mbed_official 130:1dec54e4aec3 528 typedef struct
mbed_official 130:1dec54e4aec3 529 {
mbed_official 130:1dec54e4aec3 530 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 531 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 532 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 533 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 534 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 535 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 536 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 537 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 538 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 130:1dec54e4aec3 539 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 130:1dec54e4aec3 540 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 130:1dec54e4aec3 541 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 130:1dec54e4aec3 542 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 130:1dec54e4aec3 543 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 130:1dec54e4aec3 544 } DAC_TypeDef;
mbed_official 130:1dec54e4aec3 545
mbed_official 130:1dec54e4aec3 546 /**
mbed_official 130:1dec54e4aec3 547 * @brief Debug MCU
mbed_official 130:1dec54e4aec3 548 */
mbed_official 130:1dec54e4aec3 549
mbed_official 130:1dec54e4aec3 550 typedef struct
mbed_official 130:1dec54e4aec3 551 {
mbed_official 130:1dec54e4aec3 552 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 553 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 554 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 555 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 556 }DBGMCU_TypeDef;
mbed_official 130:1dec54e4aec3 557
mbed_official 130:1dec54e4aec3 558 /**
mbed_official 130:1dec54e4aec3 559 * @brief DMA Controller
mbed_official 130:1dec54e4aec3 560 */
mbed_official 130:1dec54e4aec3 561
mbed_official 130:1dec54e4aec3 562 typedef struct
mbed_official 130:1dec54e4aec3 563 {
mbed_official 130:1dec54e4aec3 564 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 130:1dec54e4aec3 565 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 130:1dec54e4aec3 566 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 130:1dec54e4aec3 567 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 130:1dec54e4aec3 568 } DMA_Channel_TypeDef;
mbed_official 130:1dec54e4aec3 569
mbed_official 130:1dec54e4aec3 570 typedef struct
mbed_official 130:1dec54e4aec3 571 {
mbed_official 130:1dec54e4aec3 572 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 573 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 574 } DMA_TypeDef;
mbed_official 130:1dec54e4aec3 575
mbed_official 130:1dec54e4aec3 576 /**
mbed_official 130:1dec54e4aec3 577 * @brief External Interrupt/Event Controller
mbed_official 130:1dec54e4aec3 578 */
mbed_official 130:1dec54e4aec3 579
mbed_official 130:1dec54e4aec3 580 typedef struct
mbed_official 130:1dec54e4aec3 581 {
mbed_official 130:1dec54e4aec3 582 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 583 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 584 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 585 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 586 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 587 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 588 }EXTI_TypeDef;
mbed_official 130:1dec54e4aec3 589
mbed_official 130:1dec54e4aec3 590 /**
mbed_official 130:1dec54e4aec3 591 * @brief FLASH Registers
mbed_official 130:1dec54e4aec3 592 */
mbed_official 130:1dec54e4aec3 593 typedef struct
mbed_official 130:1dec54e4aec3 594 {
mbed_official 130:1dec54e4aec3 595 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 596 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 597 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 598 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 599 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 600 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 601 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 130:1dec54e4aec3 602 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 603 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
mbed_official 130:1dec54e4aec3 604 } FLASH_TypeDef;
mbed_official 130:1dec54e4aec3 605
mbed_official 130:1dec54e4aec3 606
mbed_official 130:1dec54e4aec3 607 /**
mbed_official 130:1dec54e4aec3 608 * @brief Option Bytes Registers
mbed_official 130:1dec54e4aec3 609 */
mbed_official 130:1dec54e4aec3 610 typedef struct
mbed_official 130:1dec54e4aec3 611 {
mbed_official 130:1dec54e4aec3 612 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 613 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
mbed_official 130:1dec54e4aec3 614 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 615 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
mbed_official 130:1dec54e4aec3 616 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 617 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
mbed_official 130:1dec54e4aec3 618 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 619 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
mbed_official 130:1dec54e4aec3 620 } OB_TypeDef;
mbed_official 130:1dec54e4aec3 621
mbed_official 130:1dec54e4aec3 622
mbed_official 130:1dec54e4aec3 623 /**
mbed_official 130:1dec54e4aec3 624 * @brief General Purpose IO
mbed_official 130:1dec54e4aec3 625 */
mbed_official 130:1dec54e4aec3 626
mbed_official 130:1dec54e4aec3 627 typedef struct
mbed_official 130:1dec54e4aec3 628 {
mbed_official 130:1dec54e4aec3 629 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 630 __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 631 uint16_t RESERVED0; /*!< Reserved, 0x06 */
mbed_official 130:1dec54e4aec3 632 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 633 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 634 __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 635 uint16_t RESERVED1; /*!< Reserved, 0x12 */
mbed_official 130:1dec54e4aec3 636 __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 637 uint16_t RESERVED2; /*!< Reserved, 0x16 */
mbed_official 130:1dec54e4aec3 638 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 639 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 640 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
mbed_official 130:1dec54e4aec3 641 __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 130:1dec54e4aec3 642 uint16_t RESERVED3; /*!< Reserved, 0x2A */
mbed_official 130:1dec54e4aec3 643 }GPIO_TypeDef;
mbed_official 130:1dec54e4aec3 644
mbed_official 130:1dec54e4aec3 645 /**
mbed_official 130:1dec54e4aec3 646 * @brief SysTem Configuration
mbed_official 130:1dec54e4aec3 647 */
mbed_official 130:1dec54e4aec3 648
mbed_official 130:1dec54e4aec3 649 typedef struct
mbed_official 130:1dec54e4aec3 650 {
mbed_official 130:1dec54e4aec3 651 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 652 uint32_t RESERVED; /*!< Reserved, 0x04 */
mbed_official 130:1dec54e4aec3 653 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
mbed_official 130:1dec54e4aec3 654 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 655 } SYSCFG_TypeDef;
mbed_official 130:1dec54e4aec3 656
mbed_official 130:1dec54e4aec3 657 /**
mbed_official 130:1dec54e4aec3 658 * @brief Inter-integrated Circuit Interface
mbed_official 130:1dec54e4aec3 659 */
mbed_official 130:1dec54e4aec3 660
mbed_official 130:1dec54e4aec3 661 typedef struct
mbed_official 130:1dec54e4aec3 662 {
mbed_official 130:1dec54e4aec3 663 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 664 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 665 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 666 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 667 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 668 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 669 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 670 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 671 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 130:1dec54e4aec3 672 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 130:1dec54e4aec3 673 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 130:1dec54e4aec3 674 }I2C_TypeDef;
mbed_official 130:1dec54e4aec3 675
mbed_official 130:1dec54e4aec3 676
mbed_official 130:1dec54e4aec3 677 /**
mbed_official 130:1dec54e4aec3 678 * @brief Independent WATCHDOG
mbed_official 130:1dec54e4aec3 679 */
mbed_official 130:1dec54e4aec3 680 typedef struct
mbed_official 130:1dec54e4aec3 681 {
mbed_official 130:1dec54e4aec3 682 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 683 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 684 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 685 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 686 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 687 } IWDG_TypeDef;
mbed_official 130:1dec54e4aec3 688
mbed_official 130:1dec54e4aec3 689 /**
mbed_official 130:1dec54e4aec3 690 * @brief Power Control
mbed_official 130:1dec54e4aec3 691 */
mbed_official 130:1dec54e4aec3 692
mbed_official 130:1dec54e4aec3 693 typedef struct
mbed_official 130:1dec54e4aec3 694 {
mbed_official 130:1dec54e4aec3 695 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 696 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 697 } PWR_TypeDef;
mbed_official 130:1dec54e4aec3 698
mbed_official 130:1dec54e4aec3 699
mbed_official 130:1dec54e4aec3 700 /**
mbed_official 130:1dec54e4aec3 701 * @brief Reset and Clock Control
mbed_official 130:1dec54e4aec3 702 */
mbed_official 130:1dec54e4aec3 703 typedef struct
mbed_official 130:1dec54e4aec3 704 {
mbed_official 130:1dec54e4aec3 705 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 706 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 707 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 708 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 709 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 710 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 711 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 712 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 713 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
mbed_official 130:1dec54e4aec3 714 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
mbed_official 130:1dec54e4aec3 715 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
mbed_official 130:1dec54e4aec3 716 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
mbed_official 130:1dec54e4aec3 717 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
mbed_official 130:1dec54e4aec3 718 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
mbed_official 130:1dec54e4aec3 719 } RCC_TypeDef;
mbed_official 130:1dec54e4aec3 720
mbed_official 130:1dec54e4aec3 721 /**
mbed_official 130:1dec54e4aec3 722 * @brief Real-Time Clock
mbed_official 130:1dec54e4aec3 723 */
mbed_official 130:1dec54e4aec3 724
mbed_official 130:1dec54e4aec3 725 typedef struct
mbed_official 130:1dec54e4aec3 726 {
mbed_official 130:1dec54e4aec3 727 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 728 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 729 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 730 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 731 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 732 __IO uint32_t WUTR; /*!< RTC wakeup timer register,(only for STM32F072 devices) Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 733 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 734 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 735 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
mbed_official 130:1dec54e4aec3 736 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 130:1dec54e4aec3 737 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 130:1dec54e4aec3 738 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 130:1dec54e4aec3 739 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 130:1dec54e4aec3 740 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 130:1dec54e4aec3 741 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 130:1dec54e4aec3 742 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 130:1dec54e4aec3 743 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 130:1dec54e4aec3 744 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 130:1dec54e4aec3 745 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
mbed_official 130:1dec54e4aec3 746 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
mbed_official 130:1dec54e4aec3 747 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 130:1dec54e4aec3 748 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 130:1dec54e4aec3 749 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 130:1dec54e4aec3 750 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 130:1dec54e4aec3 751 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 130:1dec54e4aec3 752 } RTC_TypeDef;
mbed_official 130:1dec54e4aec3 753
mbed_official 130:1dec54e4aec3 754 /* Old register name definition maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 755 #define CAL CALR
mbed_official 130:1dec54e4aec3 756
mbed_official 130:1dec54e4aec3 757 /**
mbed_official 130:1dec54e4aec3 758 * @brief Serial Peripheral Interface
mbed_official 130:1dec54e4aec3 759 */
mbed_official 130:1dec54e4aec3 760
mbed_official 130:1dec54e4aec3 761 typedef struct
mbed_official 130:1dec54e4aec3 762 {
mbed_official 130:1dec54e4aec3 763 __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 764 uint16_t RESERVED0; /*!< Reserved, 0x02 */
mbed_official 130:1dec54e4aec3 765 __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 766 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 130:1dec54e4aec3 767 __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 768 uint16_t RESERVED2; /*!< Reserved, 0x0A */
mbed_official 130:1dec54e4aec3 769 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 770 uint16_t RESERVED3; /*!< Reserved, 0x0E */
mbed_official 130:1dec54e4aec3 771 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 772 uint16_t RESERVED4; /*!< Reserved, 0x12 */
mbed_official 130:1dec54e4aec3 773 __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 774 uint16_t RESERVED5; /*!< Reserved, 0x16 */
mbed_official 130:1dec54e4aec3 775 __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 776 uint16_t RESERVED6; /*!< Reserved, 0x1A */
mbed_official 130:1dec54e4aec3 777 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 778 uint16_t RESERVED7; /*!< Reserved, 0x1E */
mbed_official 130:1dec54e4aec3 779 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 130:1dec54e4aec3 780 uint16_t RESERVED8; /*!< Reserved, 0x22 */
mbed_official 130:1dec54e4aec3 781 } SPI_TypeDef;
mbed_official 130:1dec54e4aec3 782
mbed_official 130:1dec54e4aec3 783
mbed_official 130:1dec54e4aec3 784 /**
mbed_official 130:1dec54e4aec3 785 * @brief TIM
mbed_official 130:1dec54e4aec3 786 */
mbed_official 130:1dec54e4aec3 787 typedef struct
mbed_official 130:1dec54e4aec3 788 {
mbed_official 130:1dec54e4aec3 789 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 790 uint16_t RESERVED0; /*!< Reserved, 0x02 */
mbed_official 130:1dec54e4aec3 791 __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 792 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 130:1dec54e4aec3 793 __IO uint16_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 794 uint16_t RESERVED2; /*!< Reserved, 0x0A */
mbed_official 130:1dec54e4aec3 795 __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 796 uint16_t RESERVED3; /*!< Reserved, 0x0E */
mbed_official 130:1dec54e4aec3 797 __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 798 uint16_t RESERVED4; /*!< Reserved, 0x12 */
mbed_official 130:1dec54e4aec3 799 __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 800 uint16_t RESERVED5; /*!< Reserved, 0x16 */
mbed_official 130:1dec54e4aec3 801 __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 802 uint16_t RESERVED6; /*!< Reserved, 0x1A */
mbed_official 130:1dec54e4aec3 803 __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 804 uint16_t RESERVED7; /*!< Reserved, 0x1E */
mbed_official 130:1dec54e4aec3 805 __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 130:1dec54e4aec3 806 uint16_t RESERVED8; /*!< Reserved, 0x22 */
mbed_official 130:1dec54e4aec3 807 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 130:1dec54e4aec3 808 __IO uint16_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 130:1dec54e4aec3 809 uint16_t RESERVED10; /*!< Reserved, 0x2A */
mbed_official 130:1dec54e4aec3 810 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 130:1dec54e4aec3 811 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 130:1dec54e4aec3 812 uint16_t RESERVED12; /*!< Reserved, 0x32 */
mbed_official 130:1dec54e4aec3 813 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 130:1dec54e4aec3 814 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 130:1dec54e4aec3 815 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 130:1dec54e4aec3 816 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 130:1dec54e4aec3 817 __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 130:1dec54e4aec3 818 uint16_t RESERVED17; /*!< Reserved, 0x26 */
mbed_official 130:1dec54e4aec3 819 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 130:1dec54e4aec3 820 uint16_t RESERVED18; /*!< Reserved, 0x4A */
mbed_official 130:1dec54e4aec3 821 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
mbed_official 130:1dec54e4aec3 822 uint16_t RESERVED19; /*!< Reserved, 0x4E */
mbed_official 130:1dec54e4aec3 823 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 130:1dec54e4aec3 824 uint16_t RESERVED20; /*!< Reserved, 0x52 */
mbed_official 130:1dec54e4aec3 825 } TIM_TypeDef;
mbed_official 130:1dec54e4aec3 826
mbed_official 130:1dec54e4aec3 827 /**
mbed_official 130:1dec54e4aec3 828 * @brief Touch Sensing Controller (TSC)
mbed_official 130:1dec54e4aec3 829 */
mbed_official 130:1dec54e4aec3 830 typedef struct
mbed_official 130:1dec54e4aec3 831 {
mbed_official 130:1dec54e4aec3 832 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 833 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 834 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 835 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 836 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 837 __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 838 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 839 __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 840 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
mbed_official 130:1dec54e4aec3 841 __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
mbed_official 130:1dec54e4aec3 842 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
mbed_official 130:1dec54e4aec3 843 __IO uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
mbed_official 130:1dec54e4aec3 844 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
mbed_official 130:1dec54e4aec3 845 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
mbed_official 130:1dec54e4aec3 846 } TSC_TypeDef;
mbed_official 130:1dec54e4aec3 847
mbed_official 130:1dec54e4aec3 848 /**
mbed_official 130:1dec54e4aec3 849 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 130:1dec54e4aec3 850 */
mbed_official 130:1dec54e4aec3 851
mbed_official 130:1dec54e4aec3 852 typedef struct
mbed_official 130:1dec54e4aec3 853 {
mbed_official 130:1dec54e4aec3 854 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 855 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 856 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 857 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 130:1dec54e4aec3 858 uint16_t RESERVED1; /*!< Reserved, 0x0E */
mbed_official 130:1dec54e4aec3 859 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 130:1dec54e4aec3 860 uint16_t RESERVED2; /*!< Reserved, 0x12 */
mbed_official 130:1dec54e4aec3 861 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 130:1dec54e4aec3 862 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 130:1dec54e4aec3 863 uint16_t RESERVED3; /*!< Reserved, 0x1A */
mbed_official 130:1dec54e4aec3 864 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 130:1dec54e4aec3 865 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 130:1dec54e4aec3 866 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 130:1dec54e4aec3 867 uint16_t RESERVED4; /*!< Reserved, 0x26 */
mbed_official 130:1dec54e4aec3 868 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 130:1dec54e4aec3 869 uint16_t RESERVED5; /*!< Reserved, 0x2A */
mbed_official 130:1dec54e4aec3 870 } USART_TypeDef;
mbed_official 130:1dec54e4aec3 871
mbed_official 130:1dec54e4aec3 872
mbed_official 130:1dec54e4aec3 873 /**
mbed_official 130:1dec54e4aec3 874 * @brief Window WATCHDOG
mbed_official 130:1dec54e4aec3 875 */
mbed_official 130:1dec54e4aec3 876 typedef struct
mbed_official 130:1dec54e4aec3 877 {
mbed_official 130:1dec54e4aec3 878 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 130:1dec54e4aec3 879 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 130:1dec54e4aec3 880 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 130:1dec54e4aec3 881 } WWDG_TypeDef;
mbed_official 130:1dec54e4aec3 882
mbed_official 130:1dec54e4aec3 883
mbed_official 130:1dec54e4aec3 884 /**
mbed_official 130:1dec54e4aec3 885 * @}
mbed_official 130:1dec54e4aec3 886 */
mbed_official 130:1dec54e4aec3 887
mbed_official 130:1dec54e4aec3 888 /** @addtogroup Peripheral_memory_map
mbed_official 130:1dec54e4aec3 889 * @{
mbed_official 130:1dec54e4aec3 890 */
mbed_official 130:1dec54e4aec3 891
mbed_official 130:1dec54e4aec3 892 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
mbed_official 130:1dec54e4aec3 893 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
mbed_official 130:1dec54e4aec3 894 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 130:1dec54e4aec3 895
mbed_official 130:1dec54e4aec3 896 /*!< Peripheral memory map */
mbed_official 130:1dec54e4aec3 897 #define APBPERIPH_BASE PERIPH_BASE
mbed_official 130:1dec54e4aec3 898 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 130:1dec54e4aec3 899 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official 130:1dec54e4aec3 900
mbed_official 130:1dec54e4aec3 901 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
mbed_official 130:1dec54e4aec3 902 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
mbed_official 130:1dec54e4aec3 903 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
mbed_official 130:1dec54e4aec3 904 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
mbed_official 130:1dec54e4aec3 905 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
mbed_official 130:1dec54e4aec3 906 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
mbed_official 130:1dec54e4aec3 907 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
mbed_official 130:1dec54e4aec3 908 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
mbed_official 130:1dec54e4aec3 909 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
mbed_official 130:1dec54e4aec3 910 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
mbed_official 130:1dec54e4aec3 911 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
mbed_official 130:1dec54e4aec3 912 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
mbed_official 130:1dec54e4aec3 913 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
mbed_official 130:1dec54e4aec3 914 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
mbed_official 130:1dec54e4aec3 915 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
mbed_official 130:1dec54e4aec3 916 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
mbed_official 130:1dec54e4aec3 917 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
mbed_official 130:1dec54e4aec3 918 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
mbed_official 130:1dec54e4aec3 919 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
mbed_official 130:1dec54e4aec3 920
mbed_official 130:1dec54e4aec3 921 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
mbed_official 130:1dec54e4aec3 922 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
mbed_official 130:1dec54e4aec3 923 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
mbed_official 130:1dec54e4aec3 924 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
mbed_official 130:1dec54e4aec3 925 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
mbed_official 130:1dec54e4aec3 926 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
mbed_official 130:1dec54e4aec3 927 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
mbed_official 130:1dec54e4aec3 928 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
mbed_official 130:1dec54e4aec3 929 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
mbed_official 130:1dec54e4aec3 930 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
mbed_official 130:1dec54e4aec3 931 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
mbed_official 130:1dec54e4aec3 932 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
mbed_official 130:1dec54e4aec3 933
mbed_official 130:1dec54e4aec3 934 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official 130:1dec54e4aec3 935 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official 130:1dec54e4aec3 936 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official 130:1dec54e4aec3 937 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official 130:1dec54e4aec3 938 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official 130:1dec54e4aec3 939 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official 130:1dec54e4aec3 940 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
mbed_official 130:1dec54e4aec3 941 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
mbed_official 130:1dec54e4aec3 942
mbed_official 130:1dec54e4aec3 943 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official 130:1dec54e4aec3 944 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
mbed_official 130:1dec54e4aec3 945 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
mbed_official 130:1dec54e4aec3 946 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official 130:1dec54e4aec3 947 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
mbed_official 130:1dec54e4aec3 948
mbed_official 130:1dec54e4aec3 949 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official 130:1dec54e4aec3 950 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official 130:1dec54e4aec3 951 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official 130:1dec54e4aec3 952 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
mbed_official 130:1dec54e4aec3 953 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
mbed_official 130:1dec54e4aec3 954 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official 130:1dec54e4aec3 955
mbed_official 130:1dec54e4aec3 956 /**
mbed_official 130:1dec54e4aec3 957 * @}
mbed_official 130:1dec54e4aec3 958 */
mbed_official 130:1dec54e4aec3 959
mbed_official 130:1dec54e4aec3 960 /** @addtogroup Peripheral_declaration
mbed_official 130:1dec54e4aec3 961 * @{
mbed_official 130:1dec54e4aec3 962 */
mbed_official 130:1dec54e4aec3 963
mbed_official 130:1dec54e4aec3 964 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 130:1dec54e4aec3 965 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 130:1dec54e4aec3 966 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 130:1dec54e4aec3 967 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 130:1dec54e4aec3 968 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 130:1dec54e4aec3 969 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 130:1dec54e4aec3 970 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 130:1dec54e4aec3 971 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 130:1dec54e4aec3 972 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 130:1dec54e4aec3 973 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 130:1dec54e4aec3 974 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 130:1dec54e4aec3 975 #define USART4 ((USART_TypeDef *) USART4_BASE)
mbed_official 130:1dec54e4aec3 976 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 130:1dec54e4aec3 977 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 130:1dec54e4aec3 978 #define CAN ((CAN_TypeDef *) CAN_BASE)
mbed_official 130:1dec54e4aec3 979 #define CRS ((CRS_TypeDef *) CRS_BASE)
mbed_official 130:1dec54e4aec3 980 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 130:1dec54e4aec3 981 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 130:1dec54e4aec3 982 #define CEC ((CEC_TypeDef *) CEC_BASE)
mbed_official 130:1dec54e4aec3 983
mbed_official 130:1dec54e4aec3 984 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 130:1dec54e4aec3 985 #define COMP ((COMP_TypeDef *) COMP_BASE)
mbed_official 130:1dec54e4aec3 986 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 130:1dec54e4aec3 987 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 130:1dec54e4aec3 988 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 130:1dec54e4aec3 989 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 130:1dec54e4aec3 990 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 130:1dec54e4aec3 991 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 130:1dec54e4aec3 992 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official 130:1dec54e4aec3 993 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official 130:1dec54e4aec3 994 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official 130:1dec54e4aec3 995 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 130:1dec54e4aec3 996
mbed_official 130:1dec54e4aec3 997 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 130:1dec54e4aec3 998 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 130:1dec54e4aec3 999 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 130:1dec54e4aec3 1000 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 130:1dec54e4aec3 1001 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 130:1dec54e4aec3 1002 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 130:1dec54e4aec3 1003 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 130:1dec54e4aec3 1004 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 130:1dec54e4aec3 1005 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 130:1dec54e4aec3 1006 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 130:1dec54e4aec3 1007 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 130:1dec54e4aec3 1008 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 130:1dec54e4aec3 1009 #define TSC ((TSC_TypeDef *) TSC_BASE)
mbed_official 130:1dec54e4aec3 1010
mbed_official 130:1dec54e4aec3 1011 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 130:1dec54e4aec3 1012 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 130:1dec54e4aec3 1013 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 130:1dec54e4aec3 1014 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 130:1dec54e4aec3 1015 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 130:1dec54e4aec3 1016 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 130:1dec54e4aec3 1017
mbed_official 130:1dec54e4aec3 1018 /**
mbed_official 130:1dec54e4aec3 1019 * @}
mbed_official 130:1dec54e4aec3 1020 */
mbed_official 130:1dec54e4aec3 1021
mbed_official 130:1dec54e4aec3 1022 /** @addtogroup Exported_constants
mbed_official 130:1dec54e4aec3 1023 * @{
mbed_official 130:1dec54e4aec3 1024 */
mbed_official 130:1dec54e4aec3 1025
mbed_official 130:1dec54e4aec3 1026 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 130:1dec54e4aec3 1027 * @{
mbed_official 130:1dec54e4aec3 1028 */
mbed_official 130:1dec54e4aec3 1029
mbed_official 130:1dec54e4aec3 1030 /******************************************************************************/
mbed_official 130:1dec54e4aec3 1031 /* Peripheral Registers Bits Definition */
mbed_official 130:1dec54e4aec3 1032 /******************************************************************************/
mbed_official 130:1dec54e4aec3 1033 /******************************************************************************/
mbed_official 130:1dec54e4aec3 1034 /* */
mbed_official 130:1dec54e4aec3 1035 /* Analog to Digital Converter (ADC) */
mbed_official 130:1dec54e4aec3 1036 /* */
mbed_official 130:1dec54e4aec3 1037 /******************************************************************************/
mbed_official 130:1dec54e4aec3 1038 /******************** Bits definition for ADC_ISR register ******************/
mbed_official 130:1dec54e4aec3 1039 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
mbed_official 130:1dec54e4aec3 1040 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
mbed_official 130:1dec54e4aec3 1041 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
mbed_official 130:1dec54e4aec3 1042 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
mbed_official 130:1dec54e4aec3 1043 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
mbed_official 130:1dec54e4aec3 1044 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
mbed_official 130:1dec54e4aec3 1045
mbed_official 130:1dec54e4aec3 1046 /* Old EOSEQ bit definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 1047 #define ADC_ISR_EOS ADC_ISR_EOSEQ
mbed_official 130:1dec54e4aec3 1048
mbed_official 130:1dec54e4aec3 1049 /******************** Bits definition for ADC_IER register ******************/
mbed_official 130:1dec54e4aec3 1050 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
mbed_official 130:1dec54e4aec3 1051 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
mbed_official 130:1dec54e4aec3 1052 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
mbed_official 130:1dec54e4aec3 1053 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
mbed_official 130:1dec54e4aec3 1054 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
mbed_official 130:1dec54e4aec3 1055 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
mbed_official 130:1dec54e4aec3 1056
mbed_official 130:1dec54e4aec3 1057 /* Old EOSEQIE bit definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 1058 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
mbed_official 130:1dec54e4aec3 1059
mbed_official 130:1dec54e4aec3 1060 /******************** Bits definition for ADC_CR register *******************/
mbed_official 130:1dec54e4aec3 1061 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
mbed_official 130:1dec54e4aec3 1062 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
mbed_official 130:1dec54e4aec3 1063 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
mbed_official 130:1dec54e4aec3 1064 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
mbed_official 130:1dec54e4aec3 1065 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
mbed_official 130:1dec54e4aec3 1066
mbed_official 130:1dec54e4aec3 1067 /******************* Bits definition for ADC_CFGR1 register *****************/
mbed_official 130:1dec54e4aec3 1068 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 130:1dec54e4aec3 1069 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 1070 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 1071 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 1072 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 1073 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 130:1dec54e4aec3 1074 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
mbed_official 130:1dec54e4aec3 1075 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
mbed_official 130:1dec54e4aec3 1076 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
mbed_official 130:1dec54e4aec3 1077 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
mbed_official 130:1dec54e4aec3 1078 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
mbed_official 130:1dec54e4aec3 1079 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
mbed_official 130:1dec54e4aec3 1080 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
mbed_official 130:1dec54e4aec3 1081 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
mbed_official 130:1dec54e4aec3 1082 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 1083 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 1084 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
mbed_official 130:1dec54e4aec3 1085 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 1086 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 1087 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 1088 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
mbed_official 130:1dec54e4aec3 1089 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
mbed_official 130:1dec54e4aec3 1090 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 1091 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 1092 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
mbed_official 130:1dec54e4aec3 1093 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
mbed_official 130:1dec54e4aec3 1094 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
mbed_official 130:1dec54e4aec3 1095
mbed_official 130:1dec54e4aec3 1096 /* Old WAIT bit definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 1097 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
mbed_official 130:1dec54e4aec3 1098
mbed_official 130:1dec54e4aec3 1099 /******************* Bits definition for ADC_CFGR2 register *****************/
mbed_official 130:1dec54e4aec3 1100 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
mbed_official 130:1dec54e4aec3 1101 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
mbed_official 130:1dec54e4aec3 1102 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
mbed_official 130:1dec54e4aec3 1103
mbed_official 130:1dec54e4aec3 1104 /* Old bit definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 1105 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
mbed_official 130:1dec54e4aec3 1106 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
mbed_official 130:1dec54e4aec3 1107
mbed_official 130:1dec54e4aec3 1108 /****************** Bit definition for ADC_SMPR register ********************/
mbed_official 130:1dec54e4aec3 1109 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
mbed_official 130:1dec54e4aec3 1110 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 1111 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 1112 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 1113
mbed_official 130:1dec54e4aec3 1114 /* Old bit definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 1115 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
mbed_official 130:1dec54e4aec3 1116 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 1117 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 1118 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 1119
mbed_official 130:1dec54e4aec3 1120 /******************* Bit definition for ADC_TR register ********************/
mbed_official 130:1dec54e4aec3 1121 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
mbed_official 130:1dec54e4aec3 1122 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
mbed_official 130:1dec54e4aec3 1123
mbed_official 130:1dec54e4aec3 1124 /* Old bit definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 1125 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
mbed_official 130:1dec54e4aec3 1126 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
mbed_official 130:1dec54e4aec3 1127
mbed_official 130:1dec54e4aec3 1128 /****************** Bit definition for ADC_CHSELR register ******************/
mbed_official 130:1dec54e4aec3 1129 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
mbed_official 130:1dec54e4aec3 1130 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
mbed_official 130:1dec54e4aec3 1131 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
mbed_official 130:1dec54e4aec3 1132 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
mbed_official 130:1dec54e4aec3 1133 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
mbed_official 130:1dec54e4aec3 1134 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
mbed_official 130:1dec54e4aec3 1135 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
mbed_official 130:1dec54e4aec3 1136 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
mbed_official 130:1dec54e4aec3 1137 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
mbed_official 130:1dec54e4aec3 1138 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
mbed_official 130:1dec54e4aec3 1139 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
mbed_official 130:1dec54e4aec3 1140 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
mbed_official 130:1dec54e4aec3 1141 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
mbed_official 130:1dec54e4aec3 1142 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
mbed_official 130:1dec54e4aec3 1143 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
mbed_official 130:1dec54e4aec3 1144 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
mbed_official 130:1dec54e4aec3 1145 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
mbed_official 130:1dec54e4aec3 1146 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
mbed_official 130:1dec54e4aec3 1147 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
mbed_official 130:1dec54e4aec3 1148
mbed_official 130:1dec54e4aec3 1149 /******************** Bit definition for ADC_DR register ********************/
mbed_official 130:1dec54e4aec3 1150 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
mbed_official 130:1dec54e4aec3 1151
mbed_official 130:1dec54e4aec3 1152 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 130:1dec54e4aec3 1153 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
mbed_official 130:1dec54e4aec3 1154 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
mbed_official 130:1dec54e4aec3 1155 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
mbed_official 130:1dec54e4aec3 1156
mbed_official 130:1dec54e4aec3 1157 /******************************************************************************/
mbed_official 130:1dec54e4aec3 1158 /* */
mbed_official 130:1dec54e4aec3 1159 /* Controller Area Network (CAN ) */
mbed_official 130:1dec54e4aec3 1160 /* */
mbed_official 130:1dec54e4aec3 1161 /******************************************************************************/
mbed_official 130:1dec54e4aec3 1162 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 130:1dec54e4aec3 1163 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
mbed_official 130:1dec54e4aec3 1164 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
mbed_official 130:1dec54e4aec3 1165 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
mbed_official 130:1dec54e4aec3 1166 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
mbed_official 130:1dec54e4aec3 1167 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
mbed_official 130:1dec54e4aec3 1168 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
mbed_official 130:1dec54e4aec3 1169 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
mbed_official 130:1dec54e4aec3 1170 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
mbed_official 130:1dec54e4aec3 1171 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
mbed_official 130:1dec54e4aec3 1172
mbed_official 130:1dec54e4aec3 1173 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 130:1dec54e4aec3 1174 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
mbed_official 130:1dec54e4aec3 1175 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
mbed_official 130:1dec54e4aec3 1176 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
mbed_official 130:1dec54e4aec3 1177 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
mbed_official 130:1dec54e4aec3 1178 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
mbed_official 130:1dec54e4aec3 1179 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
mbed_official 130:1dec54e4aec3 1180 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
mbed_official 130:1dec54e4aec3 1181 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
mbed_official 130:1dec54e4aec3 1182 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
mbed_official 130:1dec54e4aec3 1183
mbed_official 130:1dec54e4aec3 1184 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 130:1dec54e4aec3 1185 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 130:1dec54e4aec3 1186 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 130:1dec54e4aec3 1187 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 130:1dec54e4aec3 1188 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 130:1dec54e4aec3 1189 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 130:1dec54e4aec3 1190 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 130:1dec54e4aec3 1191 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 130:1dec54e4aec3 1192 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 130:1dec54e4aec3 1193 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 130:1dec54e4aec3 1194 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 130:1dec54e4aec3 1195 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 130:1dec54e4aec3 1196 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 130:1dec54e4aec3 1197 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 130:1dec54e4aec3 1198 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 130:1dec54e4aec3 1199 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 130:1dec54e4aec3 1200 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 130:1dec54e4aec3 1201
mbed_official 130:1dec54e4aec3 1202 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 130:1dec54e4aec3 1203 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 130:1dec54e4aec3 1204 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 130:1dec54e4aec3 1205 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 130:1dec54e4aec3 1206
mbed_official 130:1dec54e4aec3 1207 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 130:1dec54e4aec3 1208 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 130:1dec54e4aec3 1209 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 130:1dec54e4aec3 1210 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 130:1dec54e4aec3 1211
mbed_official 130:1dec54e4aec3 1212 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 130:1dec54e4aec3 1213 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
mbed_official 130:1dec54e4aec3 1214 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
mbed_official 130:1dec54e4aec3 1215 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
mbed_official 130:1dec54e4aec3 1216 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
mbed_official 130:1dec54e4aec3 1217
mbed_official 130:1dec54e4aec3 1218 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 130:1dec54e4aec3 1219 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
mbed_official 130:1dec54e4aec3 1220 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
mbed_official 130:1dec54e4aec3 1221 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
mbed_official 130:1dec54e4aec3 1222 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
mbed_official 130:1dec54e4aec3 1223
mbed_official 130:1dec54e4aec3 1224 /******************** Bit definition for CAN_IER register *******************/
mbed_official 130:1dec54e4aec3 1225 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 130:1dec54e4aec3 1226 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 130:1dec54e4aec3 1227 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 130:1dec54e4aec3 1228 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 130:1dec54e4aec3 1229 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 130:1dec54e4aec3 1230 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 130:1dec54e4aec3 1231 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 130:1dec54e4aec3 1232 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 130:1dec54e4aec3 1233 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 130:1dec54e4aec3 1234 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 130:1dec54e4aec3 1235 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 130:1dec54e4aec3 1236 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 130:1dec54e4aec3 1237 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 130:1dec54e4aec3 1238 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 130:1dec54e4aec3 1239
mbed_official 130:1dec54e4aec3 1240 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 130:1dec54e4aec3 1241 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 130:1dec54e4aec3 1242 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 130:1dec54e4aec3 1243 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 130:1dec54e4aec3 1244
mbed_official 130:1dec54e4aec3 1245 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 130:1dec54e4aec3 1246 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 1247 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 1248 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 1249
mbed_official 130:1dec54e4aec3 1250 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 130:1dec54e4aec3 1251 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 130:1dec54e4aec3 1252
mbed_official 130:1dec54e4aec3 1253 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 130:1dec54e4aec3 1254 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 130:1dec54e4aec3 1255 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 130:1dec54e4aec3 1256 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 130:1dec54e4aec3 1257 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 130:1dec54e4aec3 1258 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 130:1dec54e4aec3 1259 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 130:1dec54e4aec3 1260
mbed_official 130:1dec54e4aec3 1261 /*!<Mailbox registers */
mbed_official 130:1dec54e4aec3 1262 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 130:1dec54e4aec3 1263 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 130:1dec54e4aec3 1264 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 130:1dec54e4aec3 1265 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 130:1dec54e4aec3 1266 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 130:1dec54e4aec3 1267 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 130:1dec54e4aec3 1268
mbed_official 130:1dec54e4aec3 1269 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 130:1dec54e4aec3 1270 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 130:1dec54e4aec3 1271 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 130:1dec54e4aec3 1272 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 130:1dec54e4aec3 1273
mbed_official 130:1dec54e4aec3 1274 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 130:1dec54e4aec3 1275 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 130:1dec54e4aec3 1276 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 130:1dec54e4aec3 1277 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 130:1dec54e4aec3 1278 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 130:1dec54e4aec3 1279
mbed_official 130:1dec54e4aec3 1280 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 130:1dec54e4aec3 1281 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 130:1dec54e4aec3 1282 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 130:1dec54e4aec3 1283 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 130:1dec54e4aec3 1284 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 130:1dec54e4aec3 1285
mbed_official 130:1dec54e4aec3 1286 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 130:1dec54e4aec3 1287 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 130:1dec54e4aec3 1288 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 130:1dec54e4aec3 1289 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 130:1dec54e4aec3 1290 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 130:1dec54e4aec3 1291 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 130:1dec54e4aec3 1292
mbed_official 130:1dec54e4aec3 1293 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 130:1dec54e4aec3 1294 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 130:1dec54e4aec3 1295 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 130:1dec54e4aec3 1296 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 130:1dec54e4aec3 1297
mbed_official 130:1dec54e4aec3 1298 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 130:1dec54e4aec3 1299 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 130:1dec54e4aec3 1300 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 130:1dec54e4aec3 1301 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 130:1dec54e4aec3 1302 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 130:1dec54e4aec3 1303
mbed_official 130:1dec54e4aec3 1304 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 130:1dec54e4aec3 1305 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 130:1dec54e4aec3 1306 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 130:1dec54e4aec3 1307 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 130:1dec54e4aec3 1308 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 130:1dec54e4aec3 1309
mbed_official 130:1dec54e4aec3 1310 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 130:1dec54e4aec3 1311 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 130:1dec54e4aec3 1312 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 130:1dec54e4aec3 1313 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 130:1dec54e4aec3 1314 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 130:1dec54e4aec3 1315 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 130:1dec54e4aec3 1316
mbed_official 130:1dec54e4aec3 1317 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 130:1dec54e4aec3 1318 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 130:1dec54e4aec3 1319 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 130:1dec54e4aec3 1320 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 130:1dec54e4aec3 1321
mbed_official 130:1dec54e4aec3 1322 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 130:1dec54e4aec3 1323 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 130:1dec54e4aec3 1324 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 130:1dec54e4aec3 1325 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 130:1dec54e4aec3 1326 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 130:1dec54e4aec3 1327
mbed_official 130:1dec54e4aec3 1328 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 130:1dec54e4aec3 1329 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 130:1dec54e4aec3 1330 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 130:1dec54e4aec3 1331 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 130:1dec54e4aec3 1332 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 130:1dec54e4aec3 1333
mbed_official 130:1dec54e4aec3 1334 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 130:1dec54e4aec3 1335 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 130:1dec54e4aec3 1336 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 130:1dec54e4aec3 1337 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 130:1dec54e4aec3 1338 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 130:1dec54e4aec3 1339
mbed_official 130:1dec54e4aec3 1340 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 130:1dec54e4aec3 1341 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 130:1dec54e4aec3 1342 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 130:1dec54e4aec3 1343 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 130:1dec54e4aec3 1344
mbed_official 130:1dec54e4aec3 1345 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 130:1dec54e4aec3 1346 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 130:1dec54e4aec3 1347 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 130:1dec54e4aec3 1348 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 130:1dec54e4aec3 1349 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 130:1dec54e4aec3 1350
mbed_official 130:1dec54e4aec3 1351 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 130:1dec54e4aec3 1352 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 130:1dec54e4aec3 1353 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 130:1dec54e4aec3 1354 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 130:1dec54e4aec3 1355 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 130:1dec54e4aec3 1356
mbed_official 130:1dec54e4aec3 1357 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 130:1dec54e4aec3 1358 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 130:1dec54e4aec3 1359 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 130:1dec54e4aec3 1360 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 130:1dec54e4aec3 1361 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 130:1dec54e4aec3 1362
mbed_official 130:1dec54e4aec3 1363 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 130:1dec54e4aec3 1364 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 130:1dec54e4aec3 1365 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 130:1dec54e4aec3 1366 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 130:1dec54e4aec3 1367
mbed_official 130:1dec54e4aec3 1368 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 130:1dec54e4aec3 1369 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 130:1dec54e4aec3 1370 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 130:1dec54e4aec3 1371 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 130:1dec54e4aec3 1372 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 130:1dec54e4aec3 1373
mbed_official 130:1dec54e4aec3 1374 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 130:1dec54e4aec3 1375 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 130:1dec54e4aec3 1376 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 130:1dec54e4aec3 1377 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 130:1dec54e4aec3 1378 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 130:1dec54e4aec3 1379
mbed_official 130:1dec54e4aec3 1380 /*!<CAN filter registers */
mbed_official 130:1dec54e4aec3 1381 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 130:1dec54e4aec3 1382 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
mbed_official 130:1dec54e4aec3 1383
mbed_official 130:1dec54e4aec3 1384 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 130:1dec54e4aec3 1385 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
mbed_official 130:1dec54e4aec3 1386 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
mbed_official 130:1dec54e4aec3 1387 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
mbed_official 130:1dec54e4aec3 1388 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
mbed_official 130:1dec54e4aec3 1389 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
mbed_official 130:1dec54e4aec3 1390 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
mbed_official 130:1dec54e4aec3 1391 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
mbed_official 130:1dec54e4aec3 1392 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
mbed_official 130:1dec54e4aec3 1393 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
mbed_official 130:1dec54e4aec3 1394 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
mbed_official 130:1dec54e4aec3 1395 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
mbed_official 130:1dec54e4aec3 1396 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
mbed_official 130:1dec54e4aec3 1397 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
mbed_official 130:1dec54e4aec3 1398 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
mbed_official 130:1dec54e4aec3 1399 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
mbed_official 130:1dec54e4aec3 1400
mbed_official 130:1dec54e4aec3 1401 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 130:1dec54e4aec3 1402 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
mbed_official 130:1dec54e4aec3 1403 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
mbed_official 130:1dec54e4aec3 1404 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
mbed_official 130:1dec54e4aec3 1405 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
mbed_official 130:1dec54e4aec3 1406 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
mbed_official 130:1dec54e4aec3 1407 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
mbed_official 130:1dec54e4aec3 1408 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
mbed_official 130:1dec54e4aec3 1409 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
mbed_official 130:1dec54e4aec3 1410 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
mbed_official 130:1dec54e4aec3 1411 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
mbed_official 130:1dec54e4aec3 1412 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
mbed_official 130:1dec54e4aec3 1413 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
mbed_official 130:1dec54e4aec3 1414 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
mbed_official 130:1dec54e4aec3 1415 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
mbed_official 130:1dec54e4aec3 1416 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
mbed_official 130:1dec54e4aec3 1417
mbed_official 130:1dec54e4aec3 1418 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 130:1dec54e4aec3 1419 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
mbed_official 130:1dec54e4aec3 1420 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
mbed_official 130:1dec54e4aec3 1421 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
mbed_official 130:1dec54e4aec3 1422 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
mbed_official 130:1dec54e4aec3 1423 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
mbed_official 130:1dec54e4aec3 1424 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
mbed_official 130:1dec54e4aec3 1425 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
mbed_official 130:1dec54e4aec3 1426 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
mbed_official 130:1dec54e4aec3 1427 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
mbed_official 130:1dec54e4aec3 1428 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
mbed_official 130:1dec54e4aec3 1429 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
mbed_official 130:1dec54e4aec3 1430 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
mbed_official 130:1dec54e4aec3 1431 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
mbed_official 130:1dec54e4aec3 1432 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
mbed_official 130:1dec54e4aec3 1433 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
mbed_official 130:1dec54e4aec3 1434
mbed_official 130:1dec54e4aec3 1435 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 130:1dec54e4aec3 1436 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
mbed_official 130:1dec54e4aec3 1437 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
mbed_official 130:1dec54e4aec3 1438 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
mbed_official 130:1dec54e4aec3 1439 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
mbed_official 130:1dec54e4aec3 1440 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
mbed_official 130:1dec54e4aec3 1441 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
mbed_official 130:1dec54e4aec3 1442 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
mbed_official 130:1dec54e4aec3 1443 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
mbed_official 130:1dec54e4aec3 1444 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
mbed_official 130:1dec54e4aec3 1445 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
mbed_official 130:1dec54e4aec3 1446 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
mbed_official 130:1dec54e4aec3 1447 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
mbed_official 130:1dec54e4aec3 1448 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
mbed_official 130:1dec54e4aec3 1449 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
mbed_official 130:1dec54e4aec3 1450 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
mbed_official 130:1dec54e4aec3 1451
mbed_official 130:1dec54e4aec3 1452 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 130:1dec54e4aec3 1453 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1454 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1455 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1456 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1457 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1458 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1459 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1460 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1461 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1462 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1463 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1464 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1465 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1466 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1467 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1468 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1469 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1470 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1471 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1472 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1473 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1474 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1475 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1476 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1477 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1478 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1479 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1480 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1481 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1482 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1483 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1484 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1485
mbed_official 130:1dec54e4aec3 1486 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 130:1dec54e4aec3 1487 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1488 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1489 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1490 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1491 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1492 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1493 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1494 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1495 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1496 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1497 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1498 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1499 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1500 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1501 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1502 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1503 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1504 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1505 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1506 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1507 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1508 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1509 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1510 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1511 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1512 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1513 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1514 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1515 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1516 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1517 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1518 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1519
mbed_official 130:1dec54e4aec3 1520 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 130:1dec54e4aec3 1521 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1522 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1523 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1524 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1525 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1526 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1527 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1528 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1529 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1530 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1531 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1532 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1533 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1534 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1535 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1536 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1537 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1538 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1539 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1540 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1541 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1542 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1543 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1544 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1545 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1546 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1547 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1548 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1549 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1550 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1551 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1552 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1553
mbed_official 130:1dec54e4aec3 1554 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 130:1dec54e4aec3 1555 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1556 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1557 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1558 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1559 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1560 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1561 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1562 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1563 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1564 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1565 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1566 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1567 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1568 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1569 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1570 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1571 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1572 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1573 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1574 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1575 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1576 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1577 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1578 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1579 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1580 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1581 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1582 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1583 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1584 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1585 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1586 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1587
mbed_official 130:1dec54e4aec3 1588 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 130:1dec54e4aec3 1589 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1590 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1591 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1592 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1593 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1594 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1595 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1596 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1597 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1598 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1599 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1600 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1601 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1602 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1603 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1604 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1605 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1606 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1607 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1608 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1609 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1610 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1611 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1612 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1613 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1614 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1615 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1616 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1617 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1618 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1619 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1620 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1621
mbed_official 130:1dec54e4aec3 1622 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 130:1dec54e4aec3 1623 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1624 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1625 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1626 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1627 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1628 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1629 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1630 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1631 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1632 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1633 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1634 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1635 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1636 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1637 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1638 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1639 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1640 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1641 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1642 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1643 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1644 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1645 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1646 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1647 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1648 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1649 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1650 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1651 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1652 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1653 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1654 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1655
mbed_official 130:1dec54e4aec3 1656 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 130:1dec54e4aec3 1657 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1658 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1659 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1660 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1661 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1662 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1663 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1664 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1665 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1666 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1667 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1668 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1669 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1670 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1671 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1672 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1673 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1674 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1675 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1676 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1677 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1678 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1679 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1680 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1681 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1682 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1683 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1684 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1685 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1686 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1687 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1688 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1689
mbed_official 130:1dec54e4aec3 1690 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 130:1dec54e4aec3 1691 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1692 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1693 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1694 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1695 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1696 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1697 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1698 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1699 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1700 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1701 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1702 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1703 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1704 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1705 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1706 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1707 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1708 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1709 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1710 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1711 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1712 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1713 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1714 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1715 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1716 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1717 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1718 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1719 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1720 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1721 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1722 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1723
mbed_official 130:1dec54e4aec3 1724 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 130:1dec54e4aec3 1725 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1726 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1727 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1728 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1729 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1730 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1731 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1732 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1733 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1734 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1735 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1736 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1737 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1738 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1739 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1740 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1741 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1742 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1743 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1744 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1745 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1746 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1747 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1748 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1749 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1750 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1751 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1752 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1753 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1754 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1755 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1756 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1757
mbed_official 130:1dec54e4aec3 1758 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 130:1dec54e4aec3 1759 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1760 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1761 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1762 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1763 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1764 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1765 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1766 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1767 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1768 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1769 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1770 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1771 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1772 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1773 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1774 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1775 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1776 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1777 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1778 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1779 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1780 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1781 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1782 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1783 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1784 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1785 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1786 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1787 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1788 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1789 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1790 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1791
mbed_official 130:1dec54e4aec3 1792 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 130:1dec54e4aec3 1793 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1794 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1795 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1796 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1797 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1798 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1799 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1800 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1801 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1802 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1803 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1804 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1805 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1806 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1807 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1808 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1809 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1810 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1811 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1812 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1813 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1814 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1815 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1816 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1817 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1818 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1819 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1820 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1821 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1822 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1823 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1824 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1825
mbed_official 130:1dec54e4aec3 1826 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 130:1dec54e4aec3 1827 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1828 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1829 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1830 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1831 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1832 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1833 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1834 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1835 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1836 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1837 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1838 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1839 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1840 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1841 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1842 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1843 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1844 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1845 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1846 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1847 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1848 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1849 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1850 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1851 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1852 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1853 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1854 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1855 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1856 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1857 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1858 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1859
mbed_official 130:1dec54e4aec3 1860 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 130:1dec54e4aec3 1861 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1862 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1863 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1864 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1865 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1866 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1867 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1868 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1869 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1870 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1871 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1872 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1873 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1874 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1875 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1876 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1877 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1878 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1879 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1880 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1881 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1882 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1883 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1884 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1885 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1886 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1887 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1888 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1889 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1890 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1891 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1892 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1893
mbed_official 130:1dec54e4aec3 1894 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 130:1dec54e4aec3 1895 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1896 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1897 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1898 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1899 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1900 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1901 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1902 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1903 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1904 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1905 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1906 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1907 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1908 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1909 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1910 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1911 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1912 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1913 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1914 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1915 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1916 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1917 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1918 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1919 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1920 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1921 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1922 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1923 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1924 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1925 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1926 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1927
mbed_official 130:1dec54e4aec3 1928 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 130:1dec54e4aec3 1929 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1930 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1931 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1932 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1933 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1934 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1935 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1936 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1937 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1938 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1939 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1940 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1941 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1942 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1943 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1944 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1945 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1946 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1947 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1948 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1949 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1950 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1951 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1952 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1953 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1954 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1955 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1956 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1957 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1958 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1959 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1960 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1961
mbed_official 130:1dec54e4aec3 1962 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 130:1dec54e4aec3 1963 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1964 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1965 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 1966 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 1967 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 1968 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 1969 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 1970 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 1971 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 1972 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 1973 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 1974 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 1975 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 1976 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 1977 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 1978 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 1979 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 1980 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 1981 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 1982 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 1983 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 1984 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 1985 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 1986 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 1987 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 1988 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 1989 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 1990 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 1991 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 1992 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 1993 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 1994 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 1995
mbed_official 130:1dec54e4aec3 1996 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 130:1dec54e4aec3 1997 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 1998 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 1999 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2000 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2001 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2002 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2003 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2004 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2005 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2006 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2007 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2008 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2009 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2010 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2011 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2012 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2013 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2014 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2015 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2016 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2017 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2018 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2019 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2020 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2021 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2022 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2023 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2024 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2025 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2026 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2027 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2028 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2029
mbed_official 130:1dec54e4aec3 2030 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 130:1dec54e4aec3 2031 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2032 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2033 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2034 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2035 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2036 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2037 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2038 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2039 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2040 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2041 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2042 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2043 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2044 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2045 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2046 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2047 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2048 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2049 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2050 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2051 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2052 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2053 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2054 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2055 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2056 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2057 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2058 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2059 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2060 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2061 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2062 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2063
mbed_official 130:1dec54e4aec3 2064 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 130:1dec54e4aec3 2065 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2066 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2067 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2068 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2069 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2070 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2071 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2072 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2073 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2074 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2075 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2076 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2077 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2078 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2079 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2080 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2081 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2082 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2083 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2084 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2085 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2086 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2087 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2088 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2089 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2090 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2091 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2092 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2093 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2094 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2095 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2096 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2097
mbed_official 130:1dec54e4aec3 2098 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 130:1dec54e4aec3 2099 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2100 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2101 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2102 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2103 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2104 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2105 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2106 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2107 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2108 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2109 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2110 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2111 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2112 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2113 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2114 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2115 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2116 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2117 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2118 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2119 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2120 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2121 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2122 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2123 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2124 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2125 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2126 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2127 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2128 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2129 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2130 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2131
mbed_official 130:1dec54e4aec3 2132 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 130:1dec54e4aec3 2133 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2134 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2135 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2136 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2137 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2138 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2139 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2140 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2141 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2142 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2143 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2144 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2145 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2146 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2147 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2148 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2149 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2150 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2151 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2152 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2153 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2154 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2155 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2156 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2157 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2158 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2159 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2160 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2161 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2162 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2163 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2164 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2165
mbed_official 130:1dec54e4aec3 2166 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 130:1dec54e4aec3 2167 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2168 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2169 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2170 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2171 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2172 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2173 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2174 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2175 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2176 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2177 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2178 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2179 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2180 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2181 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2182 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2183 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2184 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2185 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2186 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2187 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2188 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2189 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2190 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2191 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2192 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2193 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2194 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2195 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2196 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2197 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2198 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2199
mbed_official 130:1dec54e4aec3 2200 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 130:1dec54e4aec3 2201 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2202 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2203 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2204 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2205 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2206 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2207 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2208 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2209 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2210 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2211 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2212 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2213 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2214 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2215 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2216 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2217 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2218 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2219 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2220 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2221 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2222 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2223 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2224 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2225 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2226 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2227 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2228 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2229 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2230 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2231 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2232 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2233
mbed_official 130:1dec54e4aec3 2234 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 130:1dec54e4aec3 2235 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2236 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2237 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2238 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2239 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2240 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2241 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2242 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2243 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2244 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2245 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2246 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2247 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2248 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2249 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2250 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2251 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2252 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2253 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2254 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2255 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2256 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2257 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2258 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2259 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2260 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2261 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2262 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2263 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2264 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2265 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2266 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2267
mbed_official 130:1dec54e4aec3 2268 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 130:1dec54e4aec3 2269 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2270 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2271 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2272 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2273 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2274 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2275 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2276 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2277 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2278 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2279 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2280 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2281 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2282 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2283 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2284 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2285 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2286 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2287 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2288 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2289 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2290 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2291 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2292 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2293 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2294 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2295 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2296 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2297 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2298 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2299 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2300 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2301
mbed_official 130:1dec54e4aec3 2302 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 130:1dec54e4aec3 2303 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2304 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2305 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2306 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2307 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2308 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2309 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2310 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2311 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2312 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2313 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2314 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2315 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2316 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2317 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2318 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2319 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2320 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2321 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2322 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2323 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2324 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2325 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2326 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2327 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2328 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2329 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2330 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2331 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2332 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2333 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2334 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2335
mbed_official 130:1dec54e4aec3 2336 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 130:1dec54e4aec3 2337 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2338 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2339 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2340 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2341 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2342 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2343 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2344 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2345 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2346 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2347 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2348 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2349 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2350 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2351 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2352 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2353 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2354 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2355 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2356 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2357 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2358 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2359 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2360 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2361 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2362 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2363 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2364 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2365 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2366 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2367 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2368 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2369
mbed_official 130:1dec54e4aec3 2370 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 130:1dec54e4aec3 2371 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 130:1dec54e4aec3 2372 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 130:1dec54e4aec3 2373 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 130:1dec54e4aec3 2374 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 130:1dec54e4aec3 2375 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 130:1dec54e4aec3 2376 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 130:1dec54e4aec3 2377 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 130:1dec54e4aec3 2378 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 130:1dec54e4aec3 2379 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 130:1dec54e4aec3 2380 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 130:1dec54e4aec3 2381 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 130:1dec54e4aec3 2382 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 130:1dec54e4aec3 2383 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 130:1dec54e4aec3 2384 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 130:1dec54e4aec3 2385 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 130:1dec54e4aec3 2386 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 130:1dec54e4aec3 2387 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 130:1dec54e4aec3 2388 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 130:1dec54e4aec3 2389 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 130:1dec54e4aec3 2390 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 130:1dec54e4aec3 2391 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 130:1dec54e4aec3 2392 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 130:1dec54e4aec3 2393 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 130:1dec54e4aec3 2394 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 130:1dec54e4aec3 2395 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 130:1dec54e4aec3 2396 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 130:1dec54e4aec3 2397 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 130:1dec54e4aec3 2398 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 130:1dec54e4aec3 2399 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 130:1dec54e4aec3 2400 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 130:1dec54e4aec3 2401 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 130:1dec54e4aec3 2402 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 130:1dec54e4aec3 2403
mbed_official 130:1dec54e4aec3 2404
mbed_official 130:1dec54e4aec3 2405 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2406 /* */
mbed_official 130:1dec54e4aec3 2407 /* HDMI-CEC (CEC) */
mbed_official 130:1dec54e4aec3 2408 /* */
mbed_official 130:1dec54e4aec3 2409 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2410
mbed_official 130:1dec54e4aec3 2411 /******************* Bit definition for CEC_CR register *********************/
mbed_official 130:1dec54e4aec3 2412 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
mbed_official 130:1dec54e4aec3 2413 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
mbed_official 130:1dec54e4aec3 2414 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
mbed_official 130:1dec54e4aec3 2415
mbed_official 130:1dec54e4aec3 2416 /******************* Bit definition for CEC_CFGR register *******************/
mbed_official 130:1dec54e4aec3 2417 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
mbed_official 130:1dec54e4aec3 2418 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
mbed_official 130:1dec54e4aec3 2419 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
mbed_official 130:1dec54e4aec3 2420 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
mbed_official 130:1dec54e4aec3 2421 #define CEC_CFGR_LREGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */
mbed_official 130:1dec54e4aec3 2422 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */
mbed_official 130:1dec54e4aec3 2423 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
mbed_official 130:1dec54e4aec3 2424 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
mbed_official 130:1dec54e4aec3 2425 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
mbed_official 130:1dec54e4aec3 2426
mbed_official 130:1dec54e4aec3 2427 /******************* Bit definition for CEC_TXDR register *******************/
mbed_official 130:1dec54e4aec3 2428 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
mbed_official 130:1dec54e4aec3 2429
mbed_official 130:1dec54e4aec3 2430 /******************* Bit definition for CEC_RXDR register *******************/
mbed_official 130:1dec54e4aec3 2431 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
mbed_official 130:1dec54e4aec3 2432
mbed_official 130:1dec54e4aec3 2433 /******************* Bit definition for CEC_ISR register ********************/
mbed_official 130:1dec54e4aec3 2434 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
mbed_official 130:1dec54e4aec3 2435 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
mbed_official 130:1dec54e4aec3 2436 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
mbed_official 130:1dec54e4aec3 2437 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
mbed_official 130:1dec54e4aec3 2438 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
mbed_official 130:1dec54e4aec3 2439 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
mbed_official 130:1dec54e4aec3 2440 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
mbed_official 130:1dec54e4aec3 2441 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
mbed_official 130:1dec54e4aec3 2442 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
mbed_official 130:1dec54e4aec3 2443 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
mbed_official 130:1dec54e4aec3 2444 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
mbed_official 130:1dec54e4aec3 2445 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
mbed_official 130:1dec54e4aec3 2446 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
mbed_official 130:1dec54e4aec3 2447
mbed_official 130:1dec54e4aec3 2448 /******************* Bit definition for CEC_IER register ********************/
mbed_official 130:1dec54e4aec3 2449 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
mbed_official 130:1dec54e4aec3 2450 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
mbed_official 130:1dec54e4aec3 2451 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
mbed_official 130:1dec54e4aec3 2452 #define CEC_IER_BREIEIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
mbed_official 130:1dec54e4aec3 2453 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
mbed_official 130:1dec54e4aec3 2454 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
mbed_official 130:1dec54e4aec3 2455 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
mbed_official 130:1dec54e4aec3 2456 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
mbed_official 130:1dec54e4aec3 2457 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
mbed_official 130:1dec54e4aec3 2458 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
mbed_official 130:1dec54e4aec3 2459 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
mbed_official 130:1dec54e4aec3 2460 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
mbed_official 130:1dec54e4aec3 2461 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
mbed_official 130:1dec54e4aec3 2462
mbed_official 130:1dec54e4aec3 2463 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2464 /* */
mbed_official 130:1dec54e4aec3 2465 /* Analog Comparators (COMP) */
mbed_official 130:1dec54e4aec3 2466 /* */
mbed_official 130:1dec54e4aec3 2467 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2468 /*********************** Bit definition for COMP_CSR register ***************/
mbed_official 130:1dec54e4aec3 2469 /* COMP1 bits definition */
mbed_official 130:1dec54e4aec3 2470 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
mbed_official 130:1dec54e4aec3 2471 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
mbed_official 130:1dec54e4aec3 2472 #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
mbed_official 130:1dec54e4aec3 2473 #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
mbed_official 130:1dec54e4aec3 2474 #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
mbed_official 130:1dec54e4aec3 2475 #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
mbed_official 130:1dec54e4aec3 2476 #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
mbed_official 130:1dec54e4aec3 2477 #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
mbed_official 130:1dec54e4aec3 2478 #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
mbed_official 130:1dec54e4aec3 2479 #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
mbed_official 130:1dec54e4aec3 2480 #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
mbed_official 130:1dec54e4aec3 2481 #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
mbed_official 130:1dec54e4aec3 2482 #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
mbed_official 130:1dec54e4aec3 2483 #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
mbed_official 130:1dec54e4aec3 2484 #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
mbed_official 130:1dec54e4aec3 2485 #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
mbed_official 130:1dec54e4aec3 2486 #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
mbed_official 130:1dec54e4aec3 2487 #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
mbed_official 130:1dec54e4aec3 2488 #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
mbed_official 130:1dec54e4aec3 2489 /* COMP2 bits definition */
mbed_official 130:1dec54e4aec3 2490 #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
mbed_official 130:1dec54e4aec3 2491 #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
mbed_official 130:1dec54e4aec3 2492 #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
mbed_official 130:1dec54e4aec3 2493 #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
mbed_official 130:1dec54e4aec3 2494 #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
mbed_official 130:1dec54e4aec3 2495 #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
mbed_official 130:1dec54e4aec3 2496 #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
mbed_official 130:1dec54e4aec3 2497 #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
mbed_official 130:1dec54e4aec3 2498 #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
mbed_official 130:1dec54e4aec3 2499 #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
mbed_official 130:1dec54e4aec3 2500 #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
mbed_official 130:1dec54e4aec3 2501 #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
mbed_official 130:1dec54e4aec3 2502 #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
mbed_official 130:1dec54e4aec3 2503 #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
mbed_official 130:1dec54e4aec3 2504 #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
mbed_official 130:1dec54e4aec3 2505 #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
mbed_official 130:1dec54e4aec3 2506 #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
mbed_official 130:1dec54e4aec3 2507 #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
mbed_official 130:1dec54e4aec3 2508 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
mbed_official 130:1dec54e4aec3 2509
mbed_official 130:1dec54e4aec3 2510 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2511 /* */
mbed_official 130:1dec54e4aec3 2512 /* CRC calculation unit (CRC) */
mbed_official 130:1dec54e4aec3 2513 /* */
mbed_official 130:1dec54e4aec3 2514 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2515 /******************* Bit definition for CRC_DR register *********************/
mbed_official 130:1dec54e4aec3 2516 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 130:1dec54e4aec3 2517
mbed_official 130:1dec54e4aec3 2518 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 130:1dec54e4aec3 2519 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 130:1dec54e4aec3 2520
mbed_official 130:1dec54e4aec3 2521 /******************** Bit definition for CRC_CR register ********************/
mbed_official 130:1dec54e4aec3 2522 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
mbed_official 130:1dec54e4aec3 2523 #define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits (only for STM32F072 devices)*/
mbed_official 130:1dec54e4aec3 2524 #define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2525 #define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2526 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
mbed_official 130:1dec54e4aec3 2527 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
mbed_official 130:1dec54e4aec3 2528 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
mbed_official 130:1dec54e4aec3 2529 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
mbed_official 130:1dec54e4aec3 2530
mbed_official 130:1dec54e4aec3 2531 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 130:1dec54e4aec3 2532 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
mbed_official 130:1dec54e4aec3 2533
mbed_official 130:1dec54e4aec3 2534 /******************* Bit definition for CRC_POL register ********************/
mbed_official 130:1dec54e4aec3 2535 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2536
mbed_official 130:1dec54e4aec3 2537 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2538 /* */
mbed_official 130:1dec54e4aec3 2539 /* CRS Clock Recovery System */
mbed_official 130:1dec54e4aec3 2540 /* (Available only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2541 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2542
mbed_official 130:1dec54e4aec3 2543 /******************* Bit definition for CRS_CR register *********************/
mbed_official 130:1dec54e4aec3 2544 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
mbed_official 130:1dec54e4aec3 2545 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
mbed_official 130:1dec54e4aec3 2546 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
mbed_official 130:1dec54e4aec3 2547 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
mbed_official 130:1dec54e4aec3 2548 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
mbed_official 130:1dec54e4aec3 2549 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
mbed_official 130:1dec54e4aec3 2550 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
mbed_official 130:1dec54e4aec3 2551 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
mbed_official 130:1dec54e4aec3 2552
mbed_official 130:1dec54e4aec3 2553 /******************* Bit definition for CRS_CFGR register *********************/
mbed_official 130:1dec54e4aec3 2554 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
mbed_official 130:1dec54e4aec3 2555 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
mbed_official 130:1dec54e4aec3 2556 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
mbed_official 130:1dec54e4aec3 2557 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
mbed_official 130:1dec54e4aec3 2558 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
mbed_official 130:1dec54e4aec3 2559 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
mbed_official 130:1dec54e4aec3 2560 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
mbed_official 130:1dec54e4aec3 2561 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
mbed_official 130:1dec54e4aec3 2562 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
mbed_official 130:1dec54e4aec3 2563 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
mbed_official 130:1dec54e4aec3 2564
mbed_official 130:1dec54e4aec3 2565 /******************* Bit definition for CRS_ISR register *********************/
mbed_official 130:1dec54e4aec3 2566 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
mbed_official 130:1dec54e4aec3 2567 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
mbed_official 130:1dec54e4aec3 2568 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
mbed_official 130:1dec54e4aec3 2569 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
mbed_official 130:1dec54e4aec3 2570 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
mbed_official 130:1dec54e4aec3 2571 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
mbed_official 130:1dec54e4aec3 2572 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
mbed_official 130:1dec54e4aec3 2573 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
mbed_official 130:1dec54e4aec3 2574 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
mbed_official 130:1dec54e4aec3 2575
mbed_official 130:1dec54e4aec3 2576 /******************* Bit definition for CRS_ICR register *********************/
mbed_official 130:1dec54e4aec3 2577 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
mbed_official 130:1dec54e4aec3 2578 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
mbed_official 130:1dec54e4aec3 2579 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
mbed_official 130:1dec54e4aec3 2580 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
mbed_official 130:1dec54e4aec3 2581
mbed_official 130:1dec54e4aec3 2582 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2583 /* */
mbed_official 130:1dec54e4aec3 2584 /* Digital to Analog Converter (DAC) */
mbed_official 130:1dec54e4aec3 2585 /* */
mbed_official 130:1dec54e4aec3 2586 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2587 /******************** Bit definition for DAC_CR register ********************/
mbed_official 130:1dec54e4aec3 2588 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
mbed_official 130:1dec54e4aec3 2589 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
mbed_official 130:1dec54e4aec3 2590 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
mbed_official 130:1dec54e4aec3 2591
mbed_official 130:1dec54e4aec3 2592 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 130:1dec54e4aec3 2593 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 2594 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 2595 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 2596
mbed_official 130:1dec54e4aec3 2597 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)(only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2598 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 2599 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 2600
mbed_official 130:1dec54e4aec3 2601 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2602 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 2603 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 2604 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 2605 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 2606
mbed_official 130:1dec54e4aec3 2607 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
mbed_official 130:1dec54e4aec3 2608 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA Underrun Interrupt enable */
mbed_official 130:1dec54e4aec3 2609 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
mbed_official 130:1dec54e4aec3 2610 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
mbed_official 130:1dec54e4aec3 2611 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
mbed_official 130:1dec54e4aec3 2612
mbed_official 130:1dec54e4aec3 2613 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 130:1dec54e4aec3 2614 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 2615 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 2616 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 2617
mbed_official 130:1dec54e4aec3 2618 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 130:1dec54e4aec3 2619 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 2620 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 2621
mbed_official 130:1dec54e4aec3 2622 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 130:1dec54e4aec3 2623 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 2624 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 2625 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 2626 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 2627
mbed_official 130:1dec54e4aec3 2628 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
mbed_official 130:1dec54e4aec3 2629 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA Underrun Interrupt enable */
mbed_official 130:1dec54e4aec3 2630
mbed_official 130:1dec54e4aec3 2631 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 130:1dec54e4aec3 2632 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */
mbed_official 130:1dec54e4aec3 2633 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!<DAC channel2 software trigger */
mbed_official 130:1dec54e4aec3 2634
mbed_official 130:1dec54e4aec3 2635 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 130:1dec54e4aec3 2636 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 130:1dec54e4aec3 2637
mbed_official 130:1dec54e4aec3 2638 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 130:1dec54e4aec3 2639 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 130:1dec54e4aec3 2640
mbed_official 130:1dec54e4aec3 2641 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 130:1dec54e4aec3 2642 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 130:1dec54e4aec3 2643
mbed_official 130:1dec54e4aec3 2644 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 130:1dec54e4aec3 2645 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */
mbed_official 130:1dec54e4aec3 2646
mbed_official 130:1dec54e4aec3 2647 /******************** Bit definition for DAC_SR register ********************/
mbed_official 130:1dec54e4aec3 2648 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
mbed_official 130:1dec54e4aec3 2649 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag (only for STM32F072 and STM32F042 devices) */
mbed_official 130:1dec54e4aec3 2650
mbed_official 130:1dec54e4aec3 2651 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2652 /* */
mbed_official 130:1dec54e4aec3 2653 /* Debug MCU (DBGMCU) */
mbed_official 130:1dec54e4aec3 2654 /* */
mbed_official 130:1dec54e4aec3 2655 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2656
mbed_official 130:1dec54e4aec3 2657 /**************** Bit definition for DBGMCU_IDCODE register *****************/
mbed_official 130:1dec54e4aec3 2658 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
mbed_official 130:1dec54e4aec3 2659
mbed_official 130:1dec54e4aec3 2660 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
mbed_official 130:1dec54e4aec3 2661 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 2662 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 2663 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 2664 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 2665 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 130:1dec54e4aec3 2666 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 130:1dec54e4aec3 2667 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 130:1dec54e4aec3 2668 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 130:1dec54e4aec3 2669 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 130:1dec54e4aec3 2670 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 130:1dec54e4aec3 2671 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 130:1dec54e4aec3 2672 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 130:1dec54e4aec3 2673 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 130:1dec54e4aec3 2674 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 130:1dec54e4aec3 2675 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 130:1dec54e4aec3 2676 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 130:1dec54e4aec3 2677
mbed_official 130:1dec54e4aec3 2678 /****************** Bit definition for DBGMCU_CR register *******************/
mbed_official 130:1dec54e4aec3 2679 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
mbed_official 130:1dec54e4aec3 2680 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
mbed_official 130:1dec54e4aec3 2681
mbed_official 130:1dec54e4aec3 2682 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
mbed_official 130:1dec54e4aec3 2683 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
mbed_official 130:1dec54e4aec3 2684 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
mbed_official 130:1dec54e4aec3 2685 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)*/
mbed_official 130:1dec54e4aec3 2686 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2687 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
mbed_official 130:1dec54e4aec3 2688 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
mbed_official 130:1dec54e4aec3 2689 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
mbed_official 130:1dec54e4aec3 2690 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
mbed_official 130:1dec54e4aec3 2691 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
mbed_official 130:1dec54e4aec3 2692 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2693
mbed_official 130:1dec54e4aec3 2694 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
mbed_official 130:1dec54e4aec3 2695 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
mbed_official 130:1dec54e4aec3 2696 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) */
mbed_official 130:1dec54e4aec3 2697 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
mbed_official 130:1dec54e4aec3 2698 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
mbed_official 130:1dec54e4aec3 2699
mbed_official 130:1dec54e4aec3 2700 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2701 /* */
mbed_official 130:1dec54e4aec3 2702 /* DMA Controller (DMA) */
mbed_official 130:1dec54e4aec3 2703 /* */
mbed_official 130:1dec54e4aec3 2704 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2705
mbed_official 130:1dec54e4aec3 2706 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 130:1dec54e4aec3 2707 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 130:1dec54e4aec3 2708 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 130:1dec54e4aec3 2709 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 130:1dec54e4aec3 2710 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 130:1dec54e4aec3 2711 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 130:1dec54e4aec3 2712 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 130:1dec54e4aec3 2713 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 130:1dec54e4aec3 2714 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 130:1dec54e4aec3 2715 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 130:1dec54e4aec3 2716 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 130:1dec54e4aec3 2717 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 130:1dec54e4aec3 2718 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 130:1dec54e4aec3 2719 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 130:1dec54e4aec3 2720 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 130:1dec54e4aec3 2721 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 130:1dec54e4aec3 2722 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 130:1dec54e4aec3 2723 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 130:1dec54e4aec3 2724 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 130:1dec54e4aec3 2725 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 130:1dec54e4aec3 2726 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 130:1dec54e4aec3 2727 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2728 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2729 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2730 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2731 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2732 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2733 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2734 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2735
mbed_official 130:1dec54e4aec3 2736 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 130:1dec54e4aec3 2737 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 130:1dec54e4aec3 2738 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 130:1dec54e4aec3 2739 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 130:1dec54e4aec3 2740 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 130:1dec54e4aec3 2741 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 130:1dec54e4aec3 2742 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 130:1dec54e4aec3 2743 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 130:1dec54e4aec3 2744 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 130:1dec54e4aec3 2745 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 130:1dec54e4aec3 2746 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 130:1dec54e4aec3 2747 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 130:1dec54e4aec3 2748 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 130:1dec54e4aec3 2749 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 130:1dec54e4aec3 2750 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 130:1dec54e4aec3 2751 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 130:1dec54e4aec3 2752 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 130:1dec54e4aec3 2753 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 130:1dec54e4aec3 2754 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 130:1dec54e4aec3 2755 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 130:1dec54e4aec3 2756 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 130:1dec54e4aec3 2757 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2758 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2759 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2760 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2761 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2762 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2763 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2764 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 2765
mbed_official 130:1dec54e4aec3 2766 /******************* Bit definition for DMA_CCR register ********************/
mbed_official 130:1dec54e4aec3 2767 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
mbed_official 130:1dec54e4aec3 2768 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 130:1dec54e4aec3 2769 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 130:1dec54e4aec3 2770 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 130:1dec54e4aec3 2771 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 130:1dec54e4aec3 2772 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 130:1dec54e4aec3 2773 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 130:1dec54e4aec3 2774 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 130:1dec54e4aec3 2775
mbed_official 130:1dec54e4aec3 2776 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 130:1dec54e4aec3 2777 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 2778 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 2779
mbed_official 130:1dec54e4aec3 2780 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 130:1dec54e4aec3 2781 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 2782 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 2783
mbed_official 130:1dec54e4aec3 2784 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
mbed_official 130:1dec54e4aec3 2785 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 2786 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 2787
mbed_official 130:1dec54e4aec3 2788 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 130:1dec54e4aec3 2789
mbed_official 130:1dec54e4aec3 2790 /****************** Bit definition for DMA_CNDTR register *******************/
mbed_official 130:1dec54e4aec3 2791 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 130:1dec54e4aec3 2792
mbed_official 130:1dec54e4aec3 2793 /****************** Bit definition for DMA_CPAR register ********************/
mbed_official 130:1dec54e4aec3 2794 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 130:1dec54e4aec3 2795
mbed_official 130:1dec54e4aec3 2796 /****************** Bit definition for DMA_CMAR register ********************/
mbed_official 130:1dec54e4aec3 2797 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 130:1dec54e4aec3 2798
mbed_official 130:1dec54e4aec3 2799 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2800 /* */
mbed_official 130:1dec54e4aec3 2801 /* External Interrupt/Event Controller (EXTI) */
mbed_official 130:1dec54e4aec3 2802 /* */
mbed_official 130:1dec54e4aec3 2803 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2804 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 130:1dec54e4aec3 2805 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 130:1dec54e4aec3 2806 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 130:1dec54e4aec3 2807 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 130:1dec54e4aec3 2808 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 130:1dec54e4aec3 2809 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 130:1dec54e4aec3 2810 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 130:1dec54e4aec3 2811 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 130:1dec54e4aec3 2812 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 130:1dec54e4aec3 2813 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 130:1dec54e4aec3 2814 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 130:1dec54e4aec3 2815 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 130:1dec54e4aec3 2816 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 130:1dec54e4aec3 2817 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 130:1dec54e4aec3 2818 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 130:1dec54e4aec3 2819 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 130:1dec54e4aec3 2820 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 130:1dec54e4aec3 2821 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 130:1dec54e4aec3 2822 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 130:1dec54e4aec3 2823 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 130:1dec54e4aec3 2824 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 130:1dec54e4aec3 2825 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 130:1dec54e4aec3 2826 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 130:1dec54e4aec3 2827 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 130:1dec54e4aec3 2828 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 130:1dec54e4aec3 2829 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
mbed_official 130:1dec54e4aec3 2830 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
mbed_official 130:1dec54e4aec3 2831 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
mbed_official 130:1dec54e4aec3 2832 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
mbed_official 130:1dec54e4aec3 2833 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
mbed_official 130:1dec54e4aec3 2834 #define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
mbed_official 130:1dec54e4aec3 2835 #define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
mbed_official 130:1dec54e4aec3 2836 #define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
mbed_official 130:1dec54e4aec3 2837
mbed_official 130:1dec54e4aec3 2838 /****************** Bit definition for EXTI_EMR register ********************/
mbed_official 130:1dec54e4aec3 2839 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 130:1dec54e4aec3 2840 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 130:1dec54e4aec3 2841 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 130:1dec54e4aec3 2842 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 130:1dec54e4aec3 2843 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 130:1dec54e4aec3 2844 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 130:1dec54e4aec3 2845 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 130:1dec54e4aec3 2846 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 130:1dec54e4aec3 2847 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 130:1dec54e4aec3 2848 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 130:1dec54e4aec3 2849 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 130:1dec54e4aec3 2850 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 130:1dec54e4aec3 2851 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 130:1dec54e4aec3 2852 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 130:1dec54e4aec3 2853 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 130:1dec54e4aec3 2854 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 130:1dec54e4aec3 2855 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 130:1dec54e4aec3 2856 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 130:1dec54e4aec3 2857 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 130:1dec54e4aec3 2858 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 130:1dec54e4aec3 2859 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 130:1dec54e4aec3 2860 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 130:1dec54e4aec3 2861 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 130:1dec54e4aec3 2862 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 130:1dec54e4aec3 2863 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
mbed_official 130:1dec54e4aec3 2864 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
mbed_official 130:1dec54e4aec3 2865 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
mbed_official 130:1dec54e4aec3 2866 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
mbed_official 130:1dec54e4aec3 2867 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
mbed_official 130:1dec54e4aec3 2868 #define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
mbed_official 130:1dec54e4aec3 2869 #define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
mbed_official 130:1dec54e4aec3 2870 #define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
mbed_official 130:1dec54e4aec3 2871
mbed_official 130:1dec54e4aec3 2872 /******************* Bit definition for EXTI_RTSR register ******************/
mbed_official 130:1dec54e4aec3 2873 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 130:1dec54e4aec3 2874 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 130:1dec54e4aec3 2875 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 130:1dec54e4aec3 2876 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 130:1dec54e4aec3 2877 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 130:1dec54e4aec3 2878 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 130:1dec54e4aec3 2879 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 130:1dec54e4aec3 2880 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 130:1dec54e4aec3 2881 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 130:1dec54e4aec3 2882 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 130:1dec54e4aec3 2883 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 130:1dec54e4aec3 2884 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 130:1dec54e4aec3 2885 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 130:1dec54e4aec3 2886 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 130:1dec54e4aec3 2887 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 130:1dec54e4aec3 2888 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 130:1dec54e4aec3 2889 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 130:1dec54e4aec3 2890 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 130:1dec54e4aec3 2891 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 130:1dec54e4aec3 2892 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 130:1dec54e4aec3 2893 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 130:1dec54e4aec3 2894 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 130:1dec54e4aec3 2895
mbed_official 130:1dec54e4aec3 2896 /******************* Bit definition for EXTI_FTSR register *******************/
mbed_official 130:1dec54e4aec3 2897 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 130:1dec54e4aec3 2898 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 130:1dec54e4aec3 2899 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 130:1dec54e4aec3 2900 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 130:1dec54e4aec3 2901 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 130:1dec54e4aec3 2902 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 130:1dec54e4aec3 2903 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 130:1dec54e4aec3 2904 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 130:1dec54e4aec3 2905 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 130:1dec54e4aec3 2906 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 130:1dec54e4aec3 2907 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 130:1dec54e4aec3 2908 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 130:1dec54e4aec3 2909 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 130:1dec54e4aec3 2910 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 130:1dec54e4aec3 2911 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 130:1dec54e4aec3 2912 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 130:1dec54e4aec3 2913 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 130:1dec54e4aec3 2914 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 130:1dec54e4aec3 2915 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 130:1dec54e4aec3 2916 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 130:1dec54e4aec3 2917 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 130:1dec54e4aec3 2918 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 130:1dec54e4aec3 2919
mbed_official 130:1dec54e4aec3 2920 /******************* Bit definition for EXTI_SWIER register *******************/
mbed_official 130:1dec54e4aec3 2921 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 130:1dec54e4aec3 2922 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 130:1dec54e4aec3 2923 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 130:1dec54e4aec3 2924 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 130:1dec54e4aec3 2925 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 130:1dec54e4aec3 2926 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 130:1dec54e4aec3 2927 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 130:1dec54e4aec3 2928 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 130:1dec54e4aec3 2929 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 130:1dec54e4aec3 2930 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 130:1dec54e4aec3 2931 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 130:1dec54e4aec3 2932 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 130:1dec54e4aec3 2933 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 130:1dec54e4aec3 2934 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 130:1dec54e4aec3 2935 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 130:1dec54e4aec3 2936 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 130:1dec54e4aec3 2937 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 130:1dec54e4aec3 2938 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 130:1dec54e4aec3 2939 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 130:1dec54e4aec3 2940 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 130:1dec54e4aec3 2941 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 130:1dec54e4aec3 2942 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 130:1dec54e4aec3 2943
mbed_official 130:1dec54e4aec3 2944 /****************** Bit definition for EXTI_PR register *********************/
mbed_official 130:1dec54e4aec3 2945 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
mbed_official 130:1dec54e4aec3 2946 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
mbed_official 130:1dec54e4aec3 2947 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
mbed_official 130:1dec54e4aec3 2948 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
mbed_official 130:1dec54e4aec3 2949 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
mbed_official 130:1dec54e4aec3 2950 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
mbed_official 130:1dec54e4aec3 2951 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
mbed_official 130:1dec54e4aec3 2952 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
mbed_official 130:1dec54e4aec3 2953 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
mbed_official 130:1dec54e4aec3 2954 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
mbed_official 130:1dec54e4aec3 2955 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
mbed_official 130:1dec54e4aec3 2956 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
mbed_official 130:1dec54e4aec3 2957 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
mbed_official 130:1dec54e4aec3 2958 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
mbed_official 130:1dec54e4aec3 2959 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
mbed_official 130:1dec54e4aec3 2960 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
mbed_official 130:1dec54e4aec3 2961 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
mbed_official 130:1dec54e4aec3 2962 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
mbed_official 130:1dec54e4aec3 2963 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
mbed_official 130:1dec54e4aec3 2964 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
mbed_official 130:1dec54e4aec3 2965 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
mbed_official 130:1dec54e4aec3 2966 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
mbed_official 130:1dec54e4aec3 2967
mbed_official 130:1dec54e4aec3 2968 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2969 /* */
mbed_official 130:1dec54e4aec3 2970 /* FLASH and Option Bytes Registers */
mbed_official 130:1dec54e4aec3 2971 /* */
mbed_official 130:1dec54e4aec3 2972 /******************************************************************************/
mbed_official 130:1dec54e4aec3 2973
mbed_official 130:1dec54e4aec3 2974 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 130:1dec54e4aec3 2975 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
mbed_official 130:1dec54e4aec3 2976
mbed_official 130:1dec54e4aec3 2977 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
mbed_official 130:1dec54e4aec3 2978 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
mbed_official 130:1dec54e4aec3 2979
mbed_official 130:1dec54e4aec3 2980 /****************** Bit definition for FLASH_KEYR register ******************/
mbed_official 130:1dec54e4aec3 2981 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
mbed_official 130:1dec54e4aec3 2982
mbed_official 130:1dec54e4aec3 2983 /***************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official 130:1dec54e4aec3 2984 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
mbed_official 130:1dec54e4aec3 2985
mbed_official 130:1dec54e4aec3 2986 /****************** FLASH Keys **********************************************/
mbed_official 130:1dec54e4aec3 2987 #define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
mbed_official 130:1dec54e4aec3 2988 #define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
mbed_official 130:1dec54e4aec3 2989 to unlock the write access to the FPEC. */
mbed_official 130:1dec54e4aec3 2990
mbed_official 130:1dec54e4aec3 2991 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
mbed_official 130:1dec54e4aec3 2992 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
mbed_official 130:1dec54e4aec3 2993 unlock the write access to the option byte block */
mbed_official 130:1dec54e4aec3 2994
mbed_official 130:1dec54e4aec3 2995 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 130:1dec54e4aec3 2996 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 130:1dec54e4aec3 2997 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
mbed_official 130:1dec54e4aec3 2998 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
mbed_official 130:1dec54e4aec3 2999 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
mbed_official 130:1dec54e4aec3 3000 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
mbed_official 130:1dec54e4aec3 3001
mbed_official 130:1dec54e4aec3 3002 /******************* Bit definition for FLASH_CR register *******************/
mbed_official 130:1dec54e4aec3 3003 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
mbed_official 130:1dec54e4aec3 3004 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
mbed_official 130:1dec54e4aec3 3005 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
mbed_official 130:1dec54e4aec3 3006 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
mbed_official 130:1dec54e4aec3 3007 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
mbed_official 130:1dec54e4aec3 3008 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
mbed_official 130:1dec54e4aec3 3009 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
mbed_official 130:1dec54e4aec3 3010 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
mbed_official 130:1dec54e4aec3 3011 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
mbed_official 130:1dec54e4aec3 3012 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
mbed_official 130:1dec54e4aec3 3013 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
mbed_official 130:1dec54e4aec3 3014
mbed_official 130:1dec54e4aec3 3015 /******************* Bit definition for FLASH_AR register *******************/
mbed_official 130:1dec54e4aec3 3016 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
mbed_official 130:1dec54e4aec3 3017
mbed_official 130:1dec54e4aec3 3018 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 130:1dec54e4aec3 3019 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
mbed_official 130:1dec54e4aec3 3020 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level bit 1 */
mbed_official 130:1dec54e4aec3 3021 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level bit 2 */
mbed_official 130:1dec54e4aec3 3022
mbed_official 130:1dec54e4aec3 3023 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
mbed_official 130:1dec54e4aec3 3024 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
mbed_official 130:1dec54e4aec3 3025 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
mbed_official 130:1dec54e4aec3 3026 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
mbed_official 130:1dec54e4aec3 3027 #define FLASH_OBR_nBOOT0 ((uint32_t)0x00000800) /*!< nBOOT0 */
mbed_official 130:1dec54e4aec3 3028 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
mbed_official 130:1dec54e4aec3 3029 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
mbed_official 130:1dec54e4aec3 3030 #define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM Parity Check */
mbed_official 130:1dec54e4aec3 3031 #define FLASH_OBR_nBOOT0_SW ((uint32_t)0x00008000) /*!< nBOOT0 SW (available only in the STM32F042 devices)*/
mbed_official 130:1dec54e4aec3 3032 #define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< DATA0 */
mbed_official 130:1dec54e4aec3 3033 #define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< DATA0 */
mbed_official 130:1dec54e4aec3 3034
mbed_official 130:1dec54e4aec3 3035 /* Old BOOT1 bit definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 3036 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
mbed_official 130:1dec54e4aec3 3037
mbed_official 130:1dec54e4aec3 3038 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 3039 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
mbed_official 130:1dec54e4aec3 3040
mbed_official 130:1dec54e4aec3 3041 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 130:1dec54e4aec3 3042 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 130:1dec54e4aec3 3043
mbed_official 130:1dec54e4aec3 3044 /*----------------------------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 3045
mbed_official 130:1dec54e4aec3 3046 /****************** Bit definition for OB_RDP register **********************/
mbed_official 130:1dec54e4aec3 3047 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
mbed_official 130:1dec54e4aec3 3048 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
mbed_official 130:1dec54e4aec3 3049
mbed_official 130:1dec54e4aec3 3050 /****************** Bit definition for OB_USER register *********************/
mbed_official 130:1dec54e4aec3 3051 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
mbed_official 130:1dec54e4aec3 3052 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
mbed_official 130:1dec54e4aec3 3053
mbed_official 130:1dec54e4aec3 3054 /****************** Bit definition for OB_WRP0 register *********************/
mbed_official 130:1dec54e4aec3 3055 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 130:1dec54e4aec3 3056 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 130:1dec54e4aec3 3057
mbed_official 130:1dec54e4aec3 3058 /****************** Bit definition for OB_WRP1 register *********************/
mbed_official 130:1dec54e4aec3 3059 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 130:1dec54e4aec3 3060 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 130:1dec54e4aec3 3061
mbed_official 130:1dec54e4aec3 3062 /****************** Bit definition for OB_WRP2 register *********************/
mbed_official 130:1dec54e4aec3 3063 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 3064 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 3065
mbed_official 130:1dec54e4aec3 3066 /****************** Bit definition for OB_WRP3 register *********************/
mbed_official 130:1dec54e4aec3 3067 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 3068 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
mbed_official 130:1dec54e4aec3 3069
mbed_official 130:1dec54e4aec3 3070 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3071 /* */
mbed_official 130:1dec54e4aec3 3072 /* General Purpose IOs (GPIO) */
mbed_official 130:1dec54e4aec3 3073 /* */
mbed_official 130:1dec54e4aec3 3074 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3075 /******************* Bit definition for GPIO_MODER register *****************/
mbed_official 130:1dec54e4aec3 3076 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 130:1dec54e4aec3 3077 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 3078 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 3079 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 130:1dec54e4aec3 3080 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 3081 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 3082 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 130:1dec54e4aec3 3083 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 3084 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 3085 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 130:1dec54e4aec3 3086 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 3087 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 3088 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 130:1dec54e4aec3 3089 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 3090 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 3091 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 130:1dec54e4aec3 3092 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 3093 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 3094 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 130:1dec54e4aec3 3095 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 3096 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 3097 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 130:1dec54e4aec3 3098 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 3099 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 3100 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 130:1dec54e4aec3 3101 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 3102 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 130:1dec54e4aec3 3103 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 130:1dec54e4aec3 3104 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 130:1dec54e4aec3 3105 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 130:1dec54e4aec3 3106 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 130:1dec54e4aec3 3107 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 130:1dec54e4aec3 3108 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 130:1dec54e4aec3 3109 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 130:1dec54e4aec3 3110 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 130:1dec54e4aec3 3111 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 130:1dec54e4aec3 3112 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 130:1dec54e4aec3 3113 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 130:1dec54e4aec3 3114 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 130:1dec54e4aec3 3115 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 130:1dec54e4aec3 3116 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 130:1dec54e4aec3 3117 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 130:1dec54e4aec3 3118 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 130:1dec54e4aec3 3119 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 130:1dec54e4aec3 3120 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 130:1dec54e4aec3 3121 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 130:1dec54e4aec3 3122 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 130:1dec54e4aec3 3123 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 130:1dec54e4aec3 3124
mbed_official 130:1dec54e4aec3 3125 /****************** Bit definition for GPIO_OTYPER register *****************/
mbed_official 130:1dec54e4aec3 3126 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 3127 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 3128 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 3129 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 3130 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 3131 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 3132 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 3133 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 3134 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 3135 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 3136 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 3137 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 3138 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 3139 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 3140 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 3141 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 3142
mbed_official 130:1dec54e4aec3 3143 /**************** Bit definition for GPIO_OSPEEDR register ******************/
mbed_official 130:1dec54e4aec3 3144 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 130:1dec54e4aec3 3145 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 3146 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 3147 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 130:1dec54e4aec3 3148 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 3149 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 3150 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 130:1dec54e4aec3 3151 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 3152 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 3153 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 130:1dec54e4aec3 3154 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 3155 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 3156 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 130:1dec54e4aec3 3157 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 3158 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 3159 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 130:1dec54e4aec3 3160 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 3161 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 3162 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 130:1dec54e4aec3 3163 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 3164 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 3165 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 130:1dec54e4aec3 3166 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 3167 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 3168 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 130:1dec54e4aec3 3169 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 3170 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 130:1dec54e4aec3 3171 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 130:1dec54e4aec3 3172 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 130:1dec54e4aec3 3173 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 130:1dec54e4aec3 3174 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 130:1dec54e4aec3 3175 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 130:1dec54e4aec3 3176 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 130:1dec54e4aec3 3177 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 130:1dec54e4aec3 3178 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 130:1dec54e4aec3 3179 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 130:1dec54e4aec3 3180 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 130:1dec54e4aec3 3181 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 130:1dec54e4aec3 3182 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 130:1dec54e4aec3 3183 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 130:1dec54e4aec3 3184 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 130:1dec54e4aec3 3185 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 130:1dec54e4aec3 3186 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 130:1dec54e4aec3 3187 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 130:1dec54e4aec3 3188 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 130:1dec54e4aec3 3189 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 130:1dec54e4aec3 3190 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 130:1dec54e4aec3 3191 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 130:1dec54e4aec3 3192
mbed_official 130:1dec54e4aec3 3193 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 3194 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
mbed_official 130:1dec54e4aec3 3195 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
mbed_official 130:1dec54e4aec3 3196 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
mbed_official 130:1dec54e4aec3 3197 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
mbed_official 130:1dec54e4aec3 3198 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
mbed_official 130:1dec54e4aec3 3199 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
mbed_official 130:1dec54e4aec3 3200 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
mbed_official 130:1dec54e4aec3 3201 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
mbed_official 130:1dec54e4aec3 3202 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
mbed_official 130:1dec54e4aec3 3203 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
mbed_official 130:1dec54e4aec3 3204 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
mbed_official 130:1dec54e4aec3 3205 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
mbed_official 130:1dec54e4aec3 3206 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
mbed_official 130:1dec54e4aec3 3207 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
mbed_official 130:1dec54e4aec3 3208 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
mbed_official 130:1dec54e4aec3 3209 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
mbed_official 130:1dec54e4aec3 3210 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
mbed_official 130:1dec54e4aec3 3211 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
mbed_official 130:1dec54e4aec3 3212 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
mbed_official 130:1dec54e4aec3 3213 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
mbed_official 130:1dec54e4aec3 3214 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
mbed_official 130:1dec54e4aec3 3215 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
mbed_official 130:1dec54e4aec3 3216 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
mbed_official 130:1dec54e4aec3 3217 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
mbed_official 130:1dec54e4aec3 3218 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
mbed_official 130:1dec54e4aec3 3219 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
mbed_official 130:1dec54e4aec3 3220 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
mbed_official 130:1dec54e4aec3 3221 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
mbed_official 130:1dec54e4aec3 3222 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
mbed_official 130:1dec54e4aec3 3223 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
mbed_official 130:1dec54e4aec3 3224 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
mbed_official 130:1dec54e4aec3 3225 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
mbed_official 130:1dec54e4aec3 3226 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
mbed_official 130:1dec54e4aec3 3227 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
mbed_official 130:1dec54e4aec3 3228 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
mbed_official 130:1dec54e4aec3 3229 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
mbed_official 130:1dec54e4aec3 3230 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
mbed_official 130:1dec54e4aec3 3231 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
mbed_official 130:1dec54e4aec3 3232 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
mbed_official 130:1dec54e4aec3 3233 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
mbed_official 130:1dec54e4aec3 3234 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
mbed_official 130:1dec54e4aec3 3235 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
mbed_official 130:1dec54e4aec3 3236 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
mbed_official 130:1dec54e4aec3 3237 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
mbed_official 130:1dec54e4aec3 3238 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
mbed_official 130:1dec54e4aec3 3239 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
mbed_official 130:1dec54e4aec3 3240 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
mbed_official 130:1dec54e4aec3 3241 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
mbed_official 130:1dec54e4aec3 3242
mbed_official 130:1dec54e4aec3 3243 /******************* Bit definition for GPIO_PUPDR register ******************/
mbed_official 130:1dec54e4aec3 3244 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 130:1dec54e4aec3 3245 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 3246 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 3247 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 130:1dec54e4aec3 3248 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 3249 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 3250 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 130:1dec54e4aec3 3251 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 3252 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 3253 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 130:1dec54e4aec3 3254 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 3255 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 3256 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 130:1dec54e4aec3 3257 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 3258 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 3259 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 130:1dec54e4aec3 3260 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 3261 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 3262 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 130:1dec54e4aec3 3263 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 3264 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 3265 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 130:1dec54e4aec3 3266 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 3267 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 3268 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 130:1dec54e4aec3 3269 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 3270 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 130:1dec54e4aec3 3271 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 130:1dec54e4aec3 3272 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 130:1dec54e4aec3 3273 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 130:1dec54e4aec3 3274 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 130:1dec54e4aec3 3275 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 130:1dec54e4aec3 3276 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 130:1dec54e4aec3 3277 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 130:1dec54e4aec3 3278 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 130:1dec54e4aec3 3279 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 130:1dec54e4aec3 3280 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 130:1dec54e4aec3 3281 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 130:1dec54e4aec3 3282 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 130:1dec54e4aec3 3283 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 130:1dec54e4aec3 3284 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 130:1dec54e4aec3 3285 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 130:1dec54e4aec3 3286 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 130:1dec54e4aec3 3287 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 130:1dec54e4aec3 3288 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 130:1dec54e4aec3 3289 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 130:1dec54e4aec3 3290 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 130:1dec54e4aec3 3291 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 130:1dec54e4aec3 3292
mbed_official 130:1dec54e4aec3 3293 /******************* Bit definition for GPIO_IDR register *******************/
mbed_official 130:1dec54e4aec3 3294 #define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 3295 #define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 3296 #define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 3297 #define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 3298 #define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 3299 #define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 3300 #define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 3301 #define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 3302 #define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 3303 #define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 3304 #define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 3305 #define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 3306 #define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 3307 #define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 3308 #define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 3309 #define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 3310
mbed_official 130:1dec54e4aec3 3311 /****************** Bit definition for GPIO_ODR register ********************/
mbed_official 130:1dec54e4aec3 3312 #define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 3313 #define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 3314 #define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 3315 #define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 3316 #define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 3317 #define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 3318 #define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 3319 #define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 3320 #define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 3321 #define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 3322 #define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 3323 #define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 3324 #define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 3325 #define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 3326 #define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 3327 #define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 3328
mbed_official 130:1dec54e4aec3 3329 /****************** Bit definition for GPIO_BSRR register ********************/
mbed_official 130:1dec54e4aec3 3330 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 3331 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 3332 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 3333 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 3334 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 3335 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 3336 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 3337 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 3338 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 3339 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 3340 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 3341 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 3342 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 3343 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 3344 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 3345 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 3346 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 3347 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 130:1dec54e4aec3 3348 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 130:1dec54e4aec3 3349 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 130:1dec54e4aec3 3350 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 130:1dec54e4aec3 3351 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 130:1dec54e4aec3 3352 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 130:1dec54e4aec3 3353 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 130:1dec54e4aec3 3354 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 130:1dec54e4aec3 3355 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 130:1dec54e4aec3 3356 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 130:1dec54e4aec3 3357 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 130:1dec54e4aec3 3358 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 130:1dec54e4aec3 3359 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 130:1dec54e4aec3 3360 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 130:1dec54e4aec3 3361 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 130:1dec54e4aec3 3362
mbed_official 130:1dec54e4aec3 3363 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 130:1dec54e4aec3 3364 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 3365 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 3366 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 3367 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 3368 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 3369 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 3370 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 3371 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 3372 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 3373 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 3374 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 3375 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 3376 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 3377 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 3378 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 3379 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 3380 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 3381
mbed_official 130:1dec54e4aec3 3382 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 130:1dec54e4aec3 3383 #define GPIO_AFRL_AFR0 ((uint32_t)0x0000000F)
mbed_official 130:1dec54e4aec3 3384 #define GPIO_AFRL_AFR1 ((uint32_t)0x000000F0)
mbed_official 130:1dec54e4aec3 3385 #define GPIO_AFRL_AFR2 ((uint32_t)0x00000F00)
mbed_official 130:1dec54e4aec3 3386 #define GPIO_AFRL_AFR3 ((uint32_t)0x0000F000)
mbed_official 130:1dec54e4aec3 3387 #define GPIO_AFRL_AFR4 ((uint32_t)0x000F0000)
mbed_official 130:1dec54e4aec3 3388 #define GPIO_AFRL_AFR5 ((uint32_t)0x00F00000)
mbed_official 130:1dec54e4aec3 3389 #define GPIO_AFRL_AFR6 ((uint32_t)0x0F000000)
mbed_official 130:1dec54e4aec3 3390 #define GPIO_AFRL_AFR7 ((uint32_t)0xF0000000)
mbed_official 130:1dec54e4aec3 3391
mbed_official 130:1dec54e4aec3 3392 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 130:1dec54e4aec3 3393 #define GPIO_AFRH_AFR8 ((uint32_t)0x0000000F)
mbed_official 130:1dec54e4aec3 3394 #define GPIO_AFRH_AFR9 ((uint32_t)0x000000F0)
mbed_official 130:1dec54e4aec3 3395 #define GPIO_AFRH_AFR10 ((uint32_t)0x00000F00)
mbed_official 130:1dec54e4aec3 3396 #define GPIO_AFRH_AFR11 ((uint32_t)0x0000F000)
mbed_official 130:1dec54e4aec3 3397 #define GPIO_AFRH_AFR12 ((uint32_t)0x000F0000)
mbed_official 130:1dec54e4aec3 3398 #define GPIO_AFRH_AFR13 ((uint32_t)0x00F00000)
mbed_official 130:1dec54e4aec3 3399 #define GPIO_AFRH_AFR14 ((uint32_t)0x0F000000)
mbed_official 130:1dec54e4aec3 3400 #define GPIO_AFRH_AFR15 ((uint32_t)0xF0000000)
mbed_official 130:1dec54e4aec3 3401
mbed_official 130:1dec54e4aec3 3402 /* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
mbed_official 130:1dec54e4aec3 3403 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFR0
mbed_official 130:1dec54e4aec3 3404 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFR1
mbed_official 130:1dec54e4aec3 3405 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFR2
mbed_official 130:1dec54e4aec3 3406 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFR3
mbed_official 130:1dec54e4aec3 3407 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFR4
mbed_official 130:1dec54e4aec3 3408 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFR5
mbed_official 130:1dec54e4aec3 3409 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFR6
mbed_official 130:1dec54e4aec3 3410 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFR7
mbed_official 130:1dec54e4aec3 3411
mbed_official 130:1dec54e4aec3 3412 /* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
mbed_official 130:1dec54e4aec3 3413 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFR8
mbed_official 130:1dec54e4aec3 3414 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFR9
mbed_official 130:1dec54e4aec3 3415 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFR10
mbed_official 130:1dec54e4aec3 3416 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFR11
mbed_official 130:1dec54e4aec3 3417 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFR12
mbed_official 130:1dec54e4aec3 3418 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFR13
mbed_official 130:1dec54e4aec3 3419 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFR14
mbed_official 130:1dec54e4aec3 3420 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFR15
mbed_official 130:1dec54e4aec3 3421
mbed_official 130:1dec54e4aec3 3422 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 130:1dec54e4aec3 3423 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 3424 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 3425 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 3426 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 3427 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 3428 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 3429 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 3430 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 3431 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 3432 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 3433 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 3434 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 3435 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 3436 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 3437 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 3438 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 3439
mbed_official 130:1dec54e4aec3 3440 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3441 /* */
mbed_official 130:1dec54e4aec3 3442 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 130:1dec54e4aec3 3443 /* */
mbed_official 130:1dec54e4aec3 3444 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3445
mbed_official 130:1dec54e4aec3 3446 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 130:1dec54e4aec3 3447 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 130:1dec54e4aec3 3448 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 130:1dec54e4aec3 3449 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 130:1dec54e4aec3 3450 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 130:1dec54e4aec3 3451 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 130:1dec54e4aec3 3452 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 130:1dec54e4aec3 3453 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 130:1dec54e4aec3 3454 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 130:1dec54e4aec3 3455 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 130:1dec54e4aec3 3456 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 130:1dec54e4aec3 3457 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 130:1dec54e4aec3 3458 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 130:1dec54e4aec3 3459 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 130:1dec54e4aec3 3460 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 130:1dec54e4aec3 3461 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 130:1dec54e4aec3 3462 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 130:1dec54e4aec3 3463 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 130:1dec54e4aec3 3464 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 130:1dec54e4aec3 3465 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 130:1dec54e4aec3 3466 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 130:1dec54e4aec3 3467 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 130:1dec54e4aec3 3468
mbed_official 130:1dec54e4aec3 3469 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 130:1dec54e4aec3 3470 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 130:1dec54e4aec3 3471 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 130:1dec54e4aec3 3472 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 130:1dec54e4aec3 3473 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 130:1dec54e4aec3 3474 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 130:1dec54e4aec3 3475 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 130:1dec54e4aec3 3476 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 130:1dec54e4aec3 3477 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 130:1dec54e4aec3 3478 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 130:1dec54e4aec3 3479 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 130:1dec54e4aec3 3480 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 130:1dec54e4aec3 3481
mbed_official 130:1dec54e4aec3 3482 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 130:1dec54e4aec3 3483 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 130:1dec54e4aec3 3484 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 130:1dec54e4aec3 3485 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 130:1dec54e4aec3 3486
mbed_official 130:1dec54e4aec3 3487 /******************* Bit definition for I2C_OAR2 register ******************/
mbed_official 130:1dec54e4aec3 3488 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 130:1dec54e4aec3 3489 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 130:1dec54e4aec3 3490 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 130:1dec54e4aec3 3491
mbed_official 130:1dec54e4aec3 3492 /******************* Bit definition for I2C_TIMINGR register *******************/
mbed_official 130:1dec54e4aec3 3493 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 130:1dec54e4aec3 3494 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 130:1dec54e4aec3 3495 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 130:1dec54e4aec3 3496 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 130:1dec54e4aec3 3497 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 130:1dec54e4aec3 3498
mbed_official 130:1dec54e4aec3 3499 /******************* Bit definition for I2C_TIMEOUTR register *******************/
mbed_official 130:1dec54e4aec3 3500 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 130:1dec54e4aec3 3501 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 130:1dec54e4aec3 3502 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 130:1dec54e4aec3 3503 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
mbed_official 130:1dec54e4aec3 3504 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 130:1dec54e4aec3 3505
mbed_official 130:1dec54e4aec3 3506 /****************** Bit definition for I2C_ISR register *********************/
mbed_official 130:1dec54e4aec3 3507 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 130:1dec54e4aec3 3508 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 130:1dec54e4aec3 3509 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 130:1dec54e4aec3 3510 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
mbed_official 130:1dec54e4aec3 3511 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 130:1dec54e4aec3 3512 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 130:1dec54e4aec3 3513 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 130:1dec54e4aec3 3514 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 130:1dec54e4aec3 3515 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 130:1dec54e4aec3 3516 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 130:1dec54e4aec3 3517 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 130:1dec54e4aec3 3518 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 130:1dec54e4aec3 3519 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 130:1dec54e4aec3 3520 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 130:1dec54e4aec3 3521 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 130:1dec54e4aec3 3522 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 130:1dec54e4aec3 3523 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 130:1dec54e4aec3 3524
mbed_official 130:1dec54e4aec3 3525 /****************** Bit definition for I2C_ICR register *********************/
mbed_official 130:1dec54e4aec3 3526 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 130:1dec54e4aec3 3527 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 130:1dec54e4aec3 3528 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 130:1dec54e4aec3 3529 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 130:1dec54e4aec3 3530 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 130:1dec54e4aec3 3531 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 130:1dec54e4aec3 3532 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 130:1dec54e4aec3 3533 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 130:1dec54e4aec3 3534 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 130:1dec54e4aec3 3535
mbed_official 130:1dec54e4aec3 3536 /****************** Bit definition for I2C_PECR register *********************/
mbed_official 130:1dec54e4aec3 3537 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 130:1dec54e4aec3 3538
mbed_official 130:1dec54e4aec3 3539 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 130:1dec54e4aec3 3540 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 130:1dec54e4aec3 3541
mbed_official 130:1dec54e4aec3 3542 /****************** Bit definition for I2C_TXDR register *********************/
mbed_official 130:1dec54e4aec3 3543 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 130:1dec54e4aec3 3544
mbed_official 130:1dec54e4aec3 3545 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3546 /* */
mbed_official 130:1dec54e4aec3 3547 /* Independent WATCHDOG (IWDG) */
mbed_official 130:1dec54e4aec3 3548 /* */
mbed_official 130:1dec54e4aec3 3549 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3550 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 130:1dec54e4aec3 3551 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
mbed_official 130:1dec54e4aec3 3552
mbed_official 130:1dec54e4aec3 3553 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 130:1dec54e4aec3 3554 #define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
mbed_official 130:1dec54e4aec3 3555 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3556 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3557 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 3558
mbed_official 130:1dec54e4aec3 3559 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 130:1dec54e4aec3 3560 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
mbed_official 130:1dec54e4aec3 3561
mbed_official 130:1dec54e4aec3 3562 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 130:1dec54e4aec3 3563 #define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
mbed_official 130:1dec54e4aec3 3564 #define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
mbed_official 130:1dec54e4aec3 3565 #define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */
mbed_official 130:1dec54e4aec3 3566
mbed_official 130:1dec54e4aec3 3567 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 130:1dec54e4aec3 3568 #define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */
mbed_official 130:1dec54e4aec3 3569
mbed_official 130:1dec54e4aec3 3570 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3571 /* */
mbed_official 130:1dec54e4aec3 3572 /* Power Control (PWR) */
mbed_official 130:1dec54e4aec3 3573 /* */
mbed_official 130:1dec54e4aec3 3574 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3575
mbed_official 130:1dec54e4aec3 3576 /******************** Bit definition for PWR_CR register ********************/
mbed_official 130:1dec54e4aec3 3577 #define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep */
mbed_official 130:1dec54e4aec3 3578 #define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
mbed_official 130:1dec54e4aec3 3579 #define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
mbed_official 130:1dec54e4aec3 3580 #define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
mbed_official 130:1dec54e4aec3 3581 #define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
mbed_official 130:1dec54e4aec3 3582
mbed_official 130:1dec54e4aec3 3583 #define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 130:1dec54e4aec3 3584 #define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3585 #define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3586 #define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 3587 /* PVD level configuration */
mbed_official 130:1dec54e4aec3 3588 #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
mbed_official 130:1dec54e4aec3 3589 #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
mbed_official 130:1dec54e4aec3 3590 #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
mbed_official 130:1dec54e4aec3 3591 #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
mbed_official 130:1dec54e4aec3 3592 #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
mbed_official 130:1dec54e4aec3 3593 #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
mbed_official 130:1dec54e4aec3 3594 #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
mbed_official 130:1dec54e4aec3 3595 #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
mbed_official 130:1dec54e4aec3 3596
mbed_official 130:1dec54e4aec3 3597 #define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
mbed_official 130:1dec54e4aec3 3598
mbed_official 130:1dec54e4aec3 3599 /* Old Bit definition maintained for legacy purpose ****/
mbed_official 130:1dec54e4aec3 3600 #define PWR_CR_LPSDSR PWR_CR_LPDS /*!< Low-power deepsleep */
mbed_official 130:1dec54e4aec3 3601
mbed_official 130:1dec54e4aec3 3602 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 130:1dec54e4aec3 3603 #define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
mbed_official 130:1dec54e4aec3 3604 #define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
mbed_official 130:1dec54e4aec3 3605 #define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
mbed_official 130:1dec54e4aec3 3606 #define PWR_CSR_VREFINTRDY ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready */
mbed_official 130:1dec54e4aec3 3607
mbed_official 130:1dec54e4aec3 3608 #define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
mbed_official 130:1dec54e4aec3 3609 #define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
mbed_official 130:1dec54e4aec3 3610 #define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
mbed_official 130:1dec54e4aec3 3611 #define PWR_CSR_EWUP4 ((uint16_t)0x0800) /*!< Enable WKUP pin 4 */
mbed_official 130:1dec54e4aec3 3612 #define PWR_CSR_EWUP5 ((uint16_t)0x1000) /*!< Enable WKUP pin 5 */
mbed_official 130:1dec54e4aec3 3613 #define PWR_CSR_EWUP6 ((uint16_t)0x2000) /*!< Enable WKUP pin 6 */
mbed_official 130:1dec54e4aec3 3614 #define PWR_CSR_EWUP7 ((uint16_t)0x4000) /*!< Enable WKUP pin 7 */
mbed_official 130:1dec54e4aec3 3615 #define PWR_CSR_EWUP8 ((uint16_t)0x8000) /*!< Enable WKUP pin 8 */
mbed_official 130:1dec54e4aec3 3616
mbed_official 130:1dec54e4aec3 3617 /* Old Bit definition maintained for legacy purpose ****/
mbed_official 130:1dec54e4aec3 3618 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDY /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 130:1dec54e4aec3 3619 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3620 /* */
mbed_official 130:1dec54e4aec3 3621 /* Reset and Clock Control */
mbed_official 130:1dec54e4aec3 3622 /* */
mbed_official 130:1dec54e4aec3 3623 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3624
mbed_official 130:1dec54e4aec3 3625 /******************** Bit definition for RCC_CR register ********************/
mbed_official 130:1dec54e4aec3 3626 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
mbed_official 130:1dec54e4aec3 3627 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
mbed_official 130:1dec54e4aec3 3628 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
mbed_official 130:1dec54e4aec3 3629 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
mbed_official 130:1dec54e4aec3 3630 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
mbed_official 130:1dec54e4aec3 3631 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
mbed_official 130:1dec54e4aec3 3632 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
mbed_official 130:1dec54e4aec3 3633 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
mbed_official 130:1dec54e4aec3 3634 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
mbed_official 130:1dec54e4aec3 3635 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
mbed_official 130:1dec54e4aec3 3636
mbed_official 130:1dec54e4aec3 3637 /******************* Bit definition for RCC_CFGR register *******************/
mbed_official 130:1dec54e4aec3 3638 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 130:1dec54e4aec3 3639 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3640 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3641 /* SW configuration */
mbed_official 130:1dec54e4aec3 3642 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 130:1dec54e4aec3 3643 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 130:1dec54e4aec3 3644 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 130:1dec54e4aec3 3645 #define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
mbed_official 130:1dec54e4aec3 3646
mbed_official 130:1dec54e4aec3 3647 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 130:1dec54e4aec3 3648 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3649 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3650 /* SWS configuration */
mbed_official 130:1dec54e4aec3 3651 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 130:1dec54e4aec3 3652 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 130:1dec54e4aec3 3653 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 130:1dec54e4aec3 3654 #define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 used as system clock */
mbed_official 130:1dec54e4aec3 3655
mbed_official 130:1dec54e4aec3 3656 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 130:1dec54e4aec3 3657 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3658 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3659 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 3660 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 3661 /* HPRE configuration */
mbed_official 130:1dec54e4aec3 3662 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 130:1dec54e4aec3 3663 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 130:1dec54e4aec3 3664 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 130:1dec54e4aec3 3665 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 130:1dec54e4aec3 3666 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 130:1dec54e4aec3 3667 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 130:1dec54e4aec3 3668 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 130:1dec54e4aec3 3669 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 130:1dec54e4aec3 3670 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 130:1dec54e4aec3 3671
mbed_official 130:1dec54e4aec3 3672 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
mbed_official 130:1dec54e4aec3 3673 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3674 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3675 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 3676 /* PPRE configuration */
mbed_official 130:1dec54e4aec3 3677 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 130:1dec54e4aec3 3678 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 130:1dec54e4aec3 3679 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 130:1dec54e4aec3 3680 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 130:1dec54e4aec3 3681 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 130:1dec54e4aec3 3682
mbed_official 130:1dec54e4aec3 3683 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
mbed_official 130:1dec54e4aec3 3684 done inside the ADC_CFGR2 */
mbed_official 130:1dec54e4aec3 3685
mbed_official 130:1dec54e4aec3 3686 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
mbed_official 130:1dec54e4aec3 3687 #define RCC_CFGR_PLLSRC_0 ((uint32_t)0x00008000) /*!< Bit 0 (available only in the STM32F072 devices) */
mbed_official 130:1dec54e4aec3 3688 #define RCC_CFGR_PLLSRC_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3689
mbed_official 130:1dec54e4aec3 3690 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source;
mbed_official 130:1dec54e4aec3 3691 Old PREDIV1 bit definition, maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 3692 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
mbed_official 130:1dec54e4aec3 3693 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI PREDIV clock selected as PLL entry clock source
mbed_official 130:1dec54e4aec3 3694 (This bit and configuration is only available for STM32F072 devices)*/
mbed_official 130:1dec54e4aec3 3695 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE PREDIV clock selected as PLL entry clock source */
mbed_official 130:1dec54e4aec3 3696 #define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48 PREDIV clock selected as PLL entry clock source */
mbed_official 130:1dec54e4aec3 3697
mbed_official 130:1dec54e4aec3 3698 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
mbed_official 130:1dec54e4aec3 3699 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
mbed_official 130:1dec54e4aec3 3700 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
mbed_official 130:1dec54e4aec3 3701
mbed_official 130:1dec54e4aec3 3702 /*!< Old bit definition maintained for legacy purposes */
mbed_official 130:1dec54e4aec3 3703 #define RCC_CFGR_PLLSRC_HSI_Div2 RCC_CFGR_PLLSRC_HSI_DIV2
mbed_official 130:1dec54e4aec3 3704
mbed_official 130:1dec54e4aec3 3705 /* PLLMUL configuration */
mbed_official 130:1dec54e4aec3 3706 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 130:1dec54e4aec3 3707 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3708 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3709 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 3710 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 3711
mbed_official 130:1dec54e4aec3 3712 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
mbed_official 130:1dec54e4aec3 3713 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
mbed_official 130:1dec54e4aec3 3714 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
mbed_official 130:1dec54e4aec3 3715 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
mbed_official 130:1dec54e4aec3 3716 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
mbed_official 130:1dec54e4aec3 3717 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
mbed_official 130:1dec54e4aec3 3718 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
mbed_official 130:1dec54e4aec3 3719 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
mbed_official 130:1dec54e4aec3 3720 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
mbed_official 130:1dec54e4aec3 3721 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
mbed_official 130:1dec54e4aec3 3722 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
mbed_official 130:1dec54e4aec3 3723 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
mbed_official 130:1dec54e4aec3 3724 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
mbed_official 130:1dec54e4aec3 3725 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
mbed_official 130:1dec54e4aec3 3726 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
mbed_official 130:1dec54e4aec3 3727
mbed_official 130:1dec54e4aec3 3728 /* Old PLLMUL configuration bit definition maintained for legacy purposes */
mbed_official 130:1dec54e4aec3 3729 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMUL /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 130:1dec54e4aec3 3730 #define RCC_CFGR_PLLMULL_0 RCC_CFGR_PLLMUL_0 /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3731 #define RCC_CFGR_PLLMULL_1 RCC_CFGR_PLLMUL_1 /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3732 #define RCC_CFGR_PLLMULL_2 RCC_CFGR_PLLMUL_2 /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 3733 #define RCC_CFGR_PLLMULL_3 RCC_CFGR_PLLMUL_3 /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 3734
mbed_official 130:1dec54e4aec3 3735 #define RCC_CFGR_PLLMULL2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
mbed_official 130:1dec54e4aec3 3736 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
mbed_official 130:1dec54e4aec3 3737 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
mbed_official 130:1dec54e4aec3 3738 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
mbed_official 130:1dec54e4aec3 3739 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
mbed_official 130:1dec54e4aec3 3740 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
mbed_official 130:1dec54e4aec3 3741 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
mbed_official 130:1dec54e4aec3 3742 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
mbed_official 130:1dec54e4aec3 3743 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMUL10 /*!< PLL input clock10 */
mbed_official 130:1dec54e4aec3 3744 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
mbed_official 130:1dec54e4aec3 3745 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
mbed_official 130:1dec54e4aec3 3746 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
mbed_official 130:1dec54e4aec3 3747 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
mbed_official 130:1dec54e4aec3 3748 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
mbed_official 130:1dec54e4aec3 3749 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
mbed_official 130:1dec54e4aec3 3750
mbed_official 130:1dec54e4aec3 3751 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
mbed_official 130:1dec54e4aec3 3752 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3753 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3754 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 3755 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 3756 /* MCO configuration */
mbed_official 130:1dec54e4aec3 3757 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 130:1dec54e4aec3 3758 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
mbed_official 130:1dec54e4aec3 3759 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
mbed_official 130:1dec54e4aec3 3760 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
mbed_official 130:1dec54e4aec3 3761 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
mbed_official 130:1dec54e4aec3 3762 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
mbed_official 130:1dec54e4aec3 3763 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
mbed_official 130:1dec54e4aec3 3764 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */
mbed_official 130:1dec54e4aec3 3765 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
mbed_official 130:1dec54e4aec3 3766
mbed_official 130:1dec54e4aec3 3767 #define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler (these bits are not available in the STM32F051 devices)*/
mbed_official 130:1dec54e4aec3 3768 #define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 (this bit are not available in the STM32F051 devices)*/
mbed_official 130:1dec54e4aec3 3769 #define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 (this bit are not available in the STM32F051 devices)*/
mbed_official 130:1dec54e4aec3 3770 #define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 (this bit are not available in the STM32F051 devices)*/
mbed_official 130:1dec54e4aec3 3771 #define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 (this bit are not available in the STM32F051 devices)*/
mbed_official 130:1dec54e4aec3 3772 #define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 (this bit are not available in the STM32F051 devices)*/
mbed_official 130:1dec54e4aec3 3773 #define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 (this bit are not available in the STM32F051 devices)*/
mbed_official 130:1dec54e4aec3 3774 #define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 (this bit are not available in the STM32F051 devices)*/
mbed_official 130:1dec54e4aec3 3775 #define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 (this bit are not available in the STM32F051 devices)*/
mbed_official 130:1dec54e4aec3 3776
mbed_official 130:1dec54e4aec3 3777 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO (this bit are not available in the STM32F051 devices) */
mbed_official 130:1dec54e4aec3 3778
mbed_official 130:1dec54e4aec3 3779 /******************* Bit definition for RCC_CIR register ********************/
mbed_official 130:1dec54e4aec3 3780 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 130:1dec54e4aec3 3781 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 130:1dec54e4aec3 3782 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 130:1dec54e4aec3 3783 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 130:1dec54e4aec3 3784 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 130:1dec54e4aec3 3785 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
mbed_official 130:1dec54e4aec3 3786 #define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
mbed_official 130:1dec54e4aec3 3787 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 130:1dec54e4aec3 3788 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 130:1dec54e4aec3 3789 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 130:1dec54e4aec3 3790 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 130:1dec54e4aec3 3791 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 130:1dec54e4aec3 3792 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 130:1dec54e4aec3 3793 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
mbed_official 130:1dec54e4aec3 3794 #define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
mbed_official 130:1dec54e4aec3 3795 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 130:1dec54e4aec3 3796 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 130:1dec54e4aec3 3797 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 130:1dec54e4aec3 3798 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 130:1dec54e4aec3 3799 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 130:1dec54e4aec3 3800 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
mbed_official 130:1dec54e4aec3 3801 #define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
mbed_official 130:1dec54e4aec3 3802 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 130:1dec54e4aec3 3803
mbed_official 130:1dec54e4aec3 3804 /***************** Bit definition for RCC_APB2RSTR register *****************/
mbed_official 130:1dec54e4aec3 3805 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
mbed_official 130:1dec54e4aec3 3806 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
mbed_official 130:1dec54e4aec3 3807 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
mbed_official 130:1dec54e4aec3 3808 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
mbed_official 130:1dec54e4aec3 3809 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
mbed_official 130:1dec54e4aec3 3810 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
mbed_official 130:1dec54e4aec3 3811 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
mbed_official 130:1dec54e4aec3 3812 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
mbed_official 130:1dec54e4aec3 3813 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
mbed_official 130:1dec54e4aec3 3814
mbed_official 130:1dec54e4aec3 3815 /* Old ADC1 clock reset bit definition maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 3816 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
mbed_official 130:1dec54e4aec3 3817
mbed_official 130:1dec54e4aec3 3818 /***************** Bit definition for RCC_APB1RSTR register *****************/
mbed_official 130:1dec54e4aec3 3819 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
mbed_official 130:1dec54e4aec3 3820 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
mbed_official 130:1dec54e4aec3 3821 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
mbed_official 130:1dec54e4aec3 3822 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
mbed_official 130:1dec54e4aec3 3823 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
mbed_official 130:1dec54e4aec3 3824 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
mbed_official 130:1dec54e4aec3 3825 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
mbed_official 130:1dec54e4aec3 3826 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
mbed_official 130:1dec54e4aec3 3827 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
mbed_official 130:1dec54e4aec3 3828 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
mbed_official 130:1dec54e4aec3 3829 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
mbed_official 130:1dec54e4aec3 3830 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
mbed_official 130:1dec54e4aec3 3831 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
mbed_official 130:1dec54e4aec3 3832 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
mbed_official 130:1dec54e4aec3 3833 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
mbed_official 130:1dec54e4aec3 3834 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
mbed_official 130:1dec54e4aec3 3835 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
mbed_official 130:1dec54e4aec3 3836 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
mbed_official 130:1dec54e4aec3 3837
mbed_official 130:1dec54e4aec3 3838 /****************** Bit definition for RCC_AHBENR register ******************/
mbed_official 130:1dec54e4aec3 3839 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */
mbed_official 130:1dec54e4aec3 3840 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
mbed_official 130:1dec54e4aec3 3841 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
mbed_official 130:1dec54e4aec3 3842 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
mbed_official 130:1dec54e4aec3 3843 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
mbed_official 130:1dec54e4aec3 3844 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
mbed_official 130:1dec54e4aec3 3845 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
mbed_official 130:1dec54e4aec3 3846 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
mbed_official 130:1dec54e4aec3 3847 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
mbed_official 130:1dec54e4aec3 3848 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
mbed_official 130:1dec54e4aec3 3849 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
mbed_official 130:1dec54e4aec3 3850
mbed_official 130:1dec54e4aec3 3851 /* Old Bit definition maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 3852 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
mbed_official 130:1dec54e4aec3 3853 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
mbed_official 130:1dec54e4aec3 3854
mbed_official 130:1dec54e4aec3 3855 /***************** Bit definition for RCC_APB2ENR register ******************/
mbed_official 130:1dec54e4aec3 3856 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
mbed_official 130:1dec54e4aec3 3857 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
mbed_official 130:1dec54e4aec3 3858 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
mbed_official 130:1dec54e4aec3 3859 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 130:1dec54e4aec3 3860 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 130:1dec54e4aec3 3861 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
mbed_official 130:1dec54e4aec3 3862 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
mbed_official 130:1dec54e4aec3 3863 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
mbed_official 130:1dec54e4aec3 3864 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
mbed_official 130:1dec54e4aec3 3865
mbed_official 130:1dec54e4aec3 3866 /* Old Bit definition maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 3867 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
mbed_official 130:1dec54e4aec3 3868 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
mbed_official 130:1dec54e4aec3 3869
mbed_official 130:1dec54e4aec3 3870 /***************** Bit definition for RCC_APB1ENR register ******************/
mbed_official 130:1dec54e4aec3 3871 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
mbed_official 130:1dec54e4aec3 3872 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 130:1dec54e4aec3 3873 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 130:1dec54e4aec3 3874 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 130:1dec54e4aec3 3875 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
mbed_official 130:1dec54e4aec3 3876 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 130:1dec54e4aec3 3877 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
mbed_official 130:1dec54e4aec3 3878 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
mbed_official 130:1dec54e4aec3 3879 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
mbed_official 130:1dec54e4aec3 3880 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
mbed_official 130:1dec54e4aec3 3881 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
mbed_official 130:1dec54e4aec3 3882 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
mbed_official 130:1dec54e4aec3 3883 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
mbed_official 130:1dec54e4aec3 3884 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
mbed_official 130:1dec54e4aec3 3885 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
mbed_official 130:1dec54e4aec3 3886 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
mbed_official 130:1dec54e4aec3 3887 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
mbed_official 130:1dec54e4aec3 3888 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
mbed_official 130:1dec54e4aec3 3889
mbed_official 130:1dec54e4aec3 3890 /******************* Bit definition for RCC_BDCR register *******************/
mbed_official 130:1dec54e4aec3 3891 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
mbed_official 130:1dec54e4aec3 3892 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
mbed_official 130:1dec54e4aec3 3893 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
mbed_official 130:1dec54e4aec3 3894
mbed_official 130:1dec54e4aec3 3895 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
mbed_official 130:1dec54e4aec3 3896 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3897 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3898
mbed_official 130:1dec54e4aec3 3899 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 130:1dec54e4aec3 3900 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3901 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3902
mbed_official 130:1dec54e4aec3 3903 /* RTC configuration */
mbed_official 130:1dec54e4aec3 3904 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 130:1dec54e4aec3 3905 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
mbed_official 130:1dec54e4aec3 3906 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
mbed_official 130:1dec54e4aec3 3907 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
mbed_official 130:1dec54e4aec3 3908
mbed_official 130:1dec54e4aec3 3909 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
mbed_official 130:1dec54e4aec3 3910 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
mbed_official 130:1dec54e4aec3 3911
mbed_official 130:1dec54e4aec3 3912 /******************* Bit definition for RCC_CSR register ********************/
mbed_official 130:1dec54e4aec3 3913 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 130:1dec54e4aec3 3914 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 130:1dec54e4aec3 3915 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
mbed_official 130:1dec54e4aec3 3916 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 130:1dec54e4aec3 3917 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
mbed_official 130:1dec54e4aec3 3918 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 130:1dec54e4aec3 3919 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 130:1dec54e4aec3 3920 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 130:1dec54e4aec3 3921 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 130:1dec54e4aec3 3922 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 130:1dec54e4aec3 3923 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 130:1dec54e4aec3 3924
mbed_official 130:1dec54e4aec3 3925 /* Old Bit definition maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 3926 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
mbed_official 130:1dec54e4aec3 3927 /******************* Bit definition for RCC_AHBRSTR register ****************/
mbed_official 130:1dec54e4aec3 3928 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
mbed_official 130:1dec54e4aec3 3929 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
mbed_official 130:1dec54e4aec3 3930 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
mbed_official 130:1dec54e4aec3 3931 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD clock reset */
mbed_official 130:1dec54e4aec3 3932 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00020000) /*!< GPIOE clock reset */
mbed_official 130:1dec54e4aec3 3933 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF clock reset */
mbed_official 130:1dec54e4aec3 3934 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x00100000) /*!< TS clock reset */
mbed_official 130:1dec54e4aec3 3935
mbed_official 130:1dec54e4aec3 3936 /* Old Bit definition maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 3937 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
mbed_official 130:1dec54e4aec3 3938
mbed_official 130:1dec54e4aec3 3939 /******************* Bit definition for RCC_CFGR2 register ******************/
mbed_official 130:1dec54e4aec3 3940 /* PREDIV1 configuration */
mbed_official 130:1dec54e4aec3 3941 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
mbed_official 130:1dec54e4aec3 3942 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3943 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3944 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 3945 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 3946
mbed_official 130:1dec54e4aec3 3947 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
mbed_official 130:1dec54e4aec3 3948 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
mbed_official 130:1dec54e4aec3 3949 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
mbed_official 130:1dec54e4aec3 3950 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
mbed_official 130:1dec54e4aec3 3951 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
mbed_official 130:1dec54e4aec3 3952 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
mbed_official 130:1dec54e4aec3 3953 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
mbed_official 130:1dec54e4aec3 3954 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
mbed_official 130:1dec54e4aec3 3955 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
mbed_official 130:1dec54e4aec3 3956 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
mbed_official 130:1dec54e4aec3 3957 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
mbed_official 130:1dec54e4aec3 3958 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
mbed_official 130:1dec54e4aec3 3959 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
mbed_official 130:1dec54e4aec3 3960 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
mbed_official 130:1dec54e4aec3 3961 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
mbed_official 130:1dec54e4aec3 3962 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
mbed_official 130:1dec54e4aec3 3963
mbed_official 130:1dec54e4aec3 3964 /******************* Bit definition for RCC_CFGR3 register ******************/
mbed_official 130:1dec54e4aec3 3965 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
mbed_official 130:1dec54e4aec3 3966 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3967 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3968 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
mbed_official 130:1dec54e4aec3 3969 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
mbed_official 130:1dec54e4aec3 3970 #define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
mbed_official 130:1dec54e4aec3 3971 #define RCC_CFGR3_ADCSW ((uint32_t)0x00000100) /*!< ADCSW bits */
mbed_official 130:1dec54e4aec3 3972 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
mbed_official 130:1dec54e4aec3 3973 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 3974 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 3975
mbed_official 130:1dec54e4aec3 3976 /******************* Bit definition for RCC_CR2 register ********************/
mbed_official 130:1dec54e4aec3 3977 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
mbed_official 130:1dec54e4aec3 3978 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
mbed_official 130:1dec54e4aec3 3979 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
mbed_official 130:1dec54e4aec3 3980 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
mbed_official 130:1dec54e4aec3 3981 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
mbed_official 130:1dec54e4aec3 3982 #define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
mbed_official 130:1dec54e4aec3 3983 #define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
mbed_official 130:1dec54e4aec3 3984 #define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
mbed_official 130:1dec54e4aec3 3985
mbed_official 130:1dec54e4aec3 3986 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3987 /* */
mbed_official 130:1dec54e4aec3 3988 /* Real-Time Clock (RTC) */
mbed_official 130:1dec54e4aec3 3989 /* */
mbed_official 130:1dec54e4aec3 3990 /******************************************************************************/
mbed_official 130:1dec54e4aec3 3991 /******************** Bits definition for RTC_TR register *******************/
mbed_official 130:1dec54e4aec3 3992 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 130:1dec54e4aec3 3993 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 130:1dec54e4aec3 3994 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 130:1dec54e4aec3 3995 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 130:1dec54e4aec3 3996 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 130:1dec54e4aec3 3997 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 3998 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 130:1dec54e4aec3 3999 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 130:1dec54e4aec3 4000 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 130:1dec54e4aec3 4001 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 130:1dec54e4aec3 4002 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 4003 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 4004 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 4005 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 130:1dec54e4aec3 4006 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 4007 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 4008 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 4009 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 4010 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 130:1dec54e4aec3 4011 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 4012 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 4013 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 4014 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 130:1dec54e4aec3 4015 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 4016 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 4017 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 4018 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 4019
mbed_official 130:1dec54e4aec3 4020 /******************** Bits definition for RTC_DR register *******************/
mbed_official 130:1dec54e4aec3 4021 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 130:1dec54e4aec3 4022 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 130:1dec54e4aec3 4023 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 130:1dec54e4aec3 4024 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 130:1dec54e4aec3 4025 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 130:1dec54e4aec3 4026 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 130:1dec54e4aec3 4027 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 4028 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 130:1dec54e4aec3 4029 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 130:1dec54e4aec3 4030 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 130:1dec54e4aec3 4031 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 130:1dec54e4aec3 4032 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 4033 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 4034 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 4035 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 4036 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 130:1dec54e4aec3 4037 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 4038 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 4039 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 4040 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 4041 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 130:1dec54e4aec3 4042 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 4043 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 4044 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 130:1dec54e4aec3 4045 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 4046 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 4047 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 4048 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 4049
mbed_official 130:1dec54e4aec3 4050 /******************** Bits definition for RTC_CR register *******************/
mbed_official 130:1dec54e4aec3 4051 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 130:1dec54e4aec3 4052 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 130:1dec54e4aec3 4053 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 130:1dec54e4aec3 4054 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 130:1dec54e4aec3 4055 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 130:1dec54e4aec3 4056 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 130:1dec54e4aec3 4057 #define RTC_CR_BKP ((uint32_t)0x00040000)
mbed_official 130:1dec54e4aec3 4058 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 130:1dec54e4aec3 4059 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 4060 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 4061 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 4062 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 4063 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 4064 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 4065 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 4066 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 4067 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 4068 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 4069 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 4070 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 130:1dec54e4aec3 4071 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 4072 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 4073 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 4074
mbed_official 130:1dec54e4aec3 4075 /* Old bit definition maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 4076 #define RTC_CR_BCK RTC_CR_BKP
mbed_official 130:1dec54e4aec3 4077 #define RTC_CR_CALSEL RTC_CR_COSEL
mbed_official 130:1dec54e4aec3 4078
mbed_official 130:1dec54e4aec3 4079 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 130:1dec54e4aec3 4080 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 4081 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 4082 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 4083 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 4084 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 4085 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 4086 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 4087 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 4088 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 4089 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 4090 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 4091 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 4092 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 4093 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 4094 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 4095
mbed_official 130:1dec54e4aec3 4096 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 130:1dec54e4aec3 4097 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 130:1dec54e4aec3 4098 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 130:1dec54e4aec3 4099
mbed_official 130:1dec54e4aec3 4100 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 130:1dec54e4aec3 4101 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 130:1dec54e4aec3 4102
mbed_official 130:1dec54e4aec3 4103 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 130:1dec54e4aec3 4104 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 130:1dec54e4aec3 4105 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 130:1dec54e4aec3 4106 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 130:1dec54e4aec3 4107 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 130:1dec54e4aec3 4108 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 130:1dec54e4aec3 4109 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 130:1dec54e4aec3 4110 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 130:1dec54e4aec3 4111 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 130:1dec54e4aec3 4112 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 130:1dec54e4aec3 4113 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 130:1dec54e4aec3 4114 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 130:1dec54e4aec3 4115 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 130:1dec54e4aec3 4116 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 130:1dec54e4aec3 4117 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 130:1dec54e4aec3 4118 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 130:1dec54e4aec3 4119 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 130:1dec54e4aec3 4120 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 4121 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 130:1dec54e4aec3 4122 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 130:1dec54e4aec3 4123 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 130:1dec54e4aec3 4124 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 4125 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 130:1dec54e4aec3 4126 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 4127 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 4128 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 4129 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 130:1dec54e4aec3 4130 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 4131 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 4132 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 4133 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 4134 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 4135 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 130:1dec54e4aec3 4136 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 4137 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 4138 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 4139 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 130:1dec54e4aec3 4140 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 4141 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 4142 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 4143 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 4144
mbed_official 130:1dec54e4aec3 4145 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 130:1dec54e4aec3 4146 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 130:1dec54e4aec3 4147
mbed_official 130:1dec54e4aec3 4148 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 130:1dec54e4aec3 4149 #define RTC_SSR_SS ((uint32_t)0x0003FFFF)
mbed_official 130:1dec54e4aec3 4150
mbed_official 130:1dec54e4aec3 4151 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 130:1dec54e4aec3 4152 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 130:1dec54e4aec3 4153 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 130:1dec54e4aec3 4154
mbed_official 130:1dec54e4aec3 4155 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 130:1dec54e4aec3 4156 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 130:1dec54e4aec3 4157 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 130:1dec54e4aec3 4158 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 130:1dec54e4aec3 4159 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 130:1dec54e4aec3 4160 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 130:1dec54e4aec3 4161 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 130:1dec54e4aec3 4162 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 130:1dec54e4aec3 4163 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 130:1dec54e4aec3 4164 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 130:1dec54e4aec3 4165 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 130:1dec54e4aec3 4166 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 4167 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 4168 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 4169 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 130:1dec54e4aec3 4170 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 4171 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 4172 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 4173 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 4174 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 130:1dec54e4aec3 4175 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 4176 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 4177 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 4178 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 130:1dec54e4aec3 4179 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 4180 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 4181 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 4182 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 4183
mbed_official 130:1dec54e4aec3 4184 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 130:1dec54e4aec3 4185 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 130:1dec54e4aec3 4186 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 4187 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 4188 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 4189 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 4190 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 130:1dec54e4aec3 4191 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 4192 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 4193 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 4194 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 4195 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 130:1dec54e4aec3 4196 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 4197 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 4198 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 130:1dec54e4aec3 4199 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 4200 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 4201 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 4202 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 4203
mbed_official 130:1dec54e4aec3 4204 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 130:1dec54e4aec3 4205 #define RTC_TSSSR_SS ((uint32_t)0x0003FFFF)
mbed_official 130:1dec54e4aec3 4206
mbed_official 130:1dec54e4aec3 4207 /******************** Bits definition for RTC_CALR register ******************/
mbed_official 130:1dec54e4aec3 4208 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 4209 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 4210 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 4211 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 130:1dec54e4aec3 4212 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 4213 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 4214 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 4215 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 4216 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 4217 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 4218 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 4219 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 4220 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 4221
mbed_official 130:1dec54e4aec3 4222 /* Old Bits definition for RTC_CAL register maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 4223 #define RTC_CAL_CALP RTC_CALR_CALP
mbed_official 130:1dec54e4aec3 4224 #define RTC_CAL_CALW8 RTC_CALR_CALW8
mbed_official 130:1dec54e4aec3 4225 #define RTC_CAL_CALW16 RTC_CALR_CALW16
mbed_official 130:1dec54e4aec3 4226 #define RTC_CAL_CALM RTC_CALR_CALM
mbed_official 130:1dec54e4aec3 4227 #define RTC_CAL_CALM_0 RTC_CALR_CALM_0
mbed_official 130:1dec54e4aec3 4228 #define RTC_CAL_CALM_1 RTC_CALR_CALM_1
mbed_official 130:1dec54e4aec3 4229 #define RTC_CAL_CALM_2 RTC_CALR_CALM_2
mbed_official 130:1dec54e4aec3 4230 #define RTC_CAL_CALM_3 RTC_CALR_CALM_3
mbed_official 130:1dec54e4aec3 4231 #define RTC_CAL_CALM_4 RTC_CALR_CALM_4
mbed_official 130:1dec54e4aec3 4232 #define RTC_CAL_CALM_5 RTC_CALR_CALM_5
mbed_official 130:1dec54e4aec3 4233 #define RTC_CAL_CALM_6 RTC_CALR_CALM_6
mbed_official 130:1dec54e4aec3 4234 #define RTC_CAL_CALM_7 RTC_CALR_CALM_7
mbed_official 130:1dec54e4aec3 4235 #define RTC_CAL_CALM_8 RTC_CALR_CALM_8
mbed_official 130:1dec54e4aec3 4236
mbed_official 130:1dec54e4aec3 4237 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 130:1dec54e4aec3 4238 #define RTC_TAFCR_PC15MODE ((uint32_t)0x00800000)
mbed_official 130:1dec54e4aec3 4239 #define RTC_TAFCR_PC15VALUE ((uint32_t)0x00400000)
mbed_official 130:1dec54e4aec3 4240 #define RTC_TAFCR_PC14MODE ((uint32_t)0x00200000)
mbed_official 130:1dec54e4aec3 4241 #define RTC_TAFCR_PC14VALUE ((uint32_t)0x00100000)
mbed_official 130:1dec54e4aec3 4242 #define RTC_TAFCR_PC13MODE ((uint32_t)0x00080000)
mbed_official 130:1dec54e4aec3 4243 #define RTC_TAFCR_PC13VALUE ((uint32_t)0x00040000)
mbed_official 130:1dec54e4aec3 4244 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 130:1dec54e4aec3 4245 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 130:1dec54e4aec3 4246 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 130:1dec54e4aec3 4247 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 130:1dec54e4aec3 4248 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 130:1dec54e4aec3 4249 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 130:1dec54e4aec3 4250 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 130:1dec54e4aec3 4251 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 130:1dec54e4aec3 4252 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 130:1dec54e4aec3 4253 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 130:1dec54e4aec3 4254 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 130:1dec54e4aec3 4255 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 130:1dec54e4aec3 4256 #define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040)
mbed_official 130:1dec54e4aec3 4257 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 130:1dec54e4aec3 4258 #define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010)
mbed_official 130:1dec54e4aec3 4259 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 130:1dec54e4aec3 4260 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 130:1dec54e4aec3 4261 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 130:1dec54e4aec3 4262 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 130:1dec54e4aec3 4263
mbed_official 130:1dec54e4aec3 4264 /* Old bit definition maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 4265 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
mbed_official 130:1dec54e4aec3 4266
mbed_official 130:1dec54e4aec3 4267 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 130:1dec54e4aec3 4268 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 130:1dec54e4aec3 4269 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 130:1dec54e4aec3 4270 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 130:1dec54e4aec3 4271 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 130:1dec54e4aec3 4272 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 130:1dec54e4aec3 4273 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 130:1dec54e4aec3 4274
mbed_official 130:1dec54e4aec3 4275 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 130:1dec54e4aec3 4276 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 130:1dec54e4aec3 4277
mbed_official 130:1dec54e4aec3 4278 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 130:1dec54e4aec3 4279 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 130:1dec54e4aec3 4280
mbed_official 130:1dec54e4aec3 4281 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 130:1dec54e4aec3 4282 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 130:1dec54e4aec3 4283
mbed_official 130:1dec54e4aec3 4284 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 130:1dec54e4aec3 4285 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 130:1dec54e4aec3 4286
mbed_official 130:1dec54e4aec3 4287 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 130:1dec54e4aec3 4288 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 130:1dec54e4aec3 4289
mbed_official 130:1dec54e4aec3 4290 /******************************************************************************/
mbed_official 130:1dec54e4aec3 4291 /* */
mbed_official 130:1dec54e4aec3 4292 /* Serial Peripheral Interface (SPI) */
mbed_official 130:1dec54e4aec3 4293 /* */
mbed_official 130:1dec54e4aec3 4294 /******************************************************************************/
mbed_official 130:1dec54e4aec3 4295 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 130:1dec54e4aec3 4296 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
mbed_official 130:1dec54e4aec3 4297 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
mbed_official 130:1dec54e4aec3 4298 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
mbed_official 130:1dec54e4aec3 4299 #define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 130:1dec54e4aec3 4300 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 4301 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 4302 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 4303 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
mbed_official 130:1dec54e4aec3 4304 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
mbed_official 130:1dec54e4aec3 4305 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
mbed_official 130:1dec54e4aec3 4306 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
mbed_official 130:1dec54e4aec3 4307 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
mbed_official 130:1dec54e4aec3 4308 #define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */
mbed_official 130:1dec54e4aec3 4309 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
mbed_official 130:1dec54e4aec3 4310 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
mbed_official 130:1dec54e4aec3 4311 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
mbed_official 130:1dec54e4aec3 4312 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
mbed_official 130:1dec54e4aec3 4313
mbed_official 130:1dec54e4aec3 4314 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 130:1dec54e4aec3 4315 #define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */
mbed_official 130:1dec54e4aec3 4316 #define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */
mbed_official 130:1dec54e4aec3 4317 #define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */
mbed_official 130:1dec54e4aec3 4318 #define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */
mbed_official 130:1dec54e4aec3 4319 #define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */
mbed_official 130:1dec54e4aec3 4320 #define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */
mbed_official 130:1dec54e4aec3 4321 #define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 130:1dec54e4aec3 4322 #define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 130:1dec54e4aec3 4323 #define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */
mbed_official 130:1dec54e4aec3 4324 #define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 4325 #define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 4326 #define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 4327 #define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 4328 #define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */
mbed_official 130:1dec54e4aec3 4329 #define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */
mbed_official 130:1dec54e4aec3 4330 #define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */
mbed_official 130:1dec54e4aec3 4331
mbed_official 130:1dec54e4aec3 4332 /******************** Bit definition for SPI_SR register ********************/
mbed_official 130:1dec54e4aec3 4333 #define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */
mbed_official 130:1dec54e4aec3 4334 #define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */
mbed_official 130:1dec54e4aec3 4335 #define SPI_SR_CHSIDE ((uint16_t)0x0004) /*!< Channel side */
mbed_official 130:1dec54e4aec3 4336 #define SPI_SR_UDR ((uint16_t)0x0008) /*!< Underrun flag */
mbed_official 130:1dec54e4aec3 4337 #define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */
mbed_official 130:1dec54e4aec3 4338 #define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */
mbed_official 130:1dec54e4aec3 4339 #define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */
mbed_official 130:1dec54e4aec3 4340 #define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */
mbed_official 130:1dec54e4aec3 4341 #define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */
mbed_official 130:1dec54e4aec3 4342 #define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */
mbed_official 130:1dec54e4aec3 4343 #define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 4344 #define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 4345 #define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */
mbed_official 130:1dec54e4aec3 4346 #define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 4347 #define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 4348
mbed_official 130:1dec54e4aec3 4349 /******************** Bit definition for SPI_DR register ********************/
mbed_official 130:1dec54e4aec3 4350 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
mbed_official 130:1dec54e4aec3 4351
mbed_official 130:1dec54e4aec3 4352 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 130:1dec54e4aec3 4353 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
mbed_official 130:1dec54e4aec3 4354
mbed_official 130:1dec54e4aec3 4355 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 130:1dec54e4aec3 4356 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
mbed_official 130:1dec54e4aec3 4357
mbed_official 130:1dec54e4aec3 4358 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 130:1dec54e4aec3 4359 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
mbed_official 130:1dec54e4aec3 4360
mbed_official 130:1dec54e4aec3 4361 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 130:1dec54e4aec3 4362 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
mbed_official 130:1dec54e4aec3 4363 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 130:1dec54e4aec3 4364 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4365 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4366 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
mbed_official 130:1dec54e4aec3 4367 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 130:1dec54e4aec3 4368 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4369 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4370 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
mbed_official 130:1dec54e4aec3 4371 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 130:1dec54e4aec3 4372 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4373 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4374 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
mbed_official 130:1dec54e4aec3 4375 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
mbed_official 130:1dec54e4aec3 4376
mbed_official 130:1dec54e4aec3 4377 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 130:1dec54e4aec3 4378 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
mbed_official 130:1dec54e4aec3 4379 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
mbed_official 130:1dec54e4aec3 4380 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
mbed_official 130:1dec54e4aec3 4381
mbed_official 130:1dec54e4aec3 4382 /******************************************************************************/
mbed_official 130:1dec54e4aec3 4383 /* */
mbed_official 130:1dec54e4aec3 4384 /* System Configuration (SYSCFG) */
mbed_official 130:1dec54e4aec3 4385 /* */
mbed_official 130:1dec54e4aec3 4386 /******************************************************************************/
mbed_official 130:1dec54e4aec3 4387 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
mbed_official 130:1dec54e4aec3 4388 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
mbed_official 130:1dec54e4aec3 4389 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
mbed_official 130:1dec54e4aec3 4390 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
mbed_official 130:1dec54e4aec3 4391 #define SYSCFG_CFGR1_PA11_PA12_RMP ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages (only for STM32F042 devices)*/
mbed_official 130:1dec54e4aec3 4392 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
mbed_official 130:1dec54e4aec3 4393 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
mbed_official 130:1dec54e4aec3 4394 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
mbed_official 130:1dec54e4aec3 4395 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
mbed_official 130:1dec54e4aec3 4396 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
mbed_official 130:1dec54e4aec3 4397 #define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 (only for STM32F072) */
mbed_official 130:1dec54e4aec3 4398 #define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 (only for STM32F072) */
mbed_official 130:1dec54e4aec3 4399 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
mbed_official 130:1dec54e4aec3 4400 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
mbed_official 130:1dec54e4aec3 4401 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
mbed_official 130:1dec54e4aec3 4402 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
mbed_official 130:1dec54e4aec3 4403 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F030, STM32F031 and STM32F072 devices) */
mbed_official 130:1dec54e4aec3 4404 #define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus (only for STM32F072) */
mbed_official 130:1dec54e4aec3 4405 #define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F030, STM32F031, STM32F042 and STM32F072 devices) */
mbed_official 130:1dec54e4aec3 4406 #define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F030, STM32F031, STM32F042 and STM32F072 devices) */
mbed_official 130:1dec54e4aec3 4407 #define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap (only for STM32F072) */
mbed_official 130:1dec54e4aec3 4408 #define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap (only for STM32F072) */
mbed_official 130:1dec54e4aec3 4409 #define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap (only for STM32F072) */
mbed_official 130:1dec54e4aec3 4410 #define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap (only for STM32F072) */
mbed_official 130:1dec54e4aec3 4411 #define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap (only for STM32F072) */
mbed_official 130:1dec54e4aec3 4412 #define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap (only for STM32F072) */
mbed_official 130:1dec54e4aec3 4413 #define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap (only for STM32F072) */
mbed_official 130:1dec54e4aec3 4414
mbed_official 130:1dec54e4aec3 4415 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 130:1dec54e4aec3 4416 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
mbed_official 130:1dec54e4aec3 4417 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
mbed_official 130:1dec54e4aec3 4418 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
mbed_official 130:1dec54e4aec3 4419 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
mbed_official 130:1dec54e4aec3 4420
mbed_official 130:1dec54e4aec3 4421 /**
mbed_official 130:1dec54e4aec3 4422 * @brief EXTI0 configuration
mbed_official 130:1dec54e4aec3 4423 */
mbed_official 130:1dec54e4aec3 4424 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
mbed_official 130:1dec54e4aec3 4425 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
mbed_official 130:1dec54e4aec3 4426 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
mbed_official 130:1dec54e4aec3 4427 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
mbed_official 130:1dec54e4aec3 4428 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
mbed_official 130:1dec54e4aec3 4429 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
mbed_official 130:1dec54e4aec3 4430
mbed_official 130:1dec54e4aec3 4431 /**
mbed_official 130:1dec54e4aec3 4432 * @brief EXTI1 configuration
mbed_official 130:1dec54e4aec3 4433 */
mbed_official 130:1dec54e4aec3 4434 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
mbed_official 130:1dec54e4aec3 4435 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
mbed_official 130:1dec54e4aec3 4436 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
mbed_official 130:1dec54e4aec3 4437 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
mbed_official 130:1dec54e4aec3 4438 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
mbed_official 130:1dec54e4aec3 4439 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
mbed_official 130:1dec54e4aec3 4440
mbed_official 130:1dec54e4aec3 4441 /**
mbed_official 130:1dec54e4aec3 4442 * @brief EXTI2 configuration
mbed_official 130:1dec54e4aec3 4443 */
mbed_official 130:1dec54e4aec3 4444 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
mbed_official 130:1dec54e4aec3 4445 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
mbed_official 130:1dec54e4aec3 4446 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
mbed_official 130:1dec54e4aec3 4447 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
mbed_official 130:1dec54e4aec3 4448 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
mbed_official 130:1dec54e4aec3 4449 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
mbed_official 130:1dec54e4aec3 4450
mbed_official 130:1dec54e4aec3 4451 /**
mbed_official 130:1dec54e4aec3 4452 * @brief EXTI3 configuration
mbed_official 130:1dec54e4aec3 4453 */
mbed_official 130:1dec54e4aec3 4454 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
mbed_official 130:1dec54e4aec3 4455 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
mbed_official 130:1dec54e4aec3 4456 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
mbed_official 130:1dec54e4aec3 4457 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
mbed_official 130:1dec54e4aec3 4458 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
mbed_official 130:1dec54e4aec3 4459 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
mbed_official 130:1dec54e4aec3 4460
mbed_official 130:1dec54e4aec3 4461 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
mbed_official 130:1dec54e4aec3 4462 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
mbed_official 130:1dec54e4aec3 4463 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
mbed_official 130:1dec54e4aec3 4464 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
mbed_official 130:1dec54e4aec3 4465 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
mbed_official 130:1dec54e4aec3 4466
mbed_official 130:1dec54e4aec3 4467 /**
mbed_official 130:1dec54e4aec3 4468 * @brief EXTI4 configuration
mbed_official 130:1dec54e4aec3 4469 */
mbed_official 130:1dec54e4aec3 4470 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
mbed_official 130:1dec54e4aec3 4471 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
mbed_official 130:1dec54e4aec3 4472 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
mbed_official 130:1dec54e4aec3 4473 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
mbed_official 130:1dec54e4aec3 4474 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
mbed_official 130:1dec54e4aec3 4475 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
mbed_official 130:1dec54e4aec3 4476
mbed_official 130:1dec54e4aec3 4477 /**
mbed_official 130:1dec54e4aec3 4478 * @brief EXTI5 configuration
mbed_official 130:1dec54e4aec3 4479 */
mbed_official 130:1dec54e4aec3 4480 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
mbed_official 130:1dec54e4aec3 4481 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
mbed_official 130:1dec54e4aec3 4482 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
mbed_official 130:1dec54e4aec3 4483 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
mbed_official 130:1dec54e4aec3 4484 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
mbed_official 130:1dec54e4aec3 4485 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
mbed_official 130:1dec54e4aec3 4486
mbed_official 130:1dec54e4aec3 4487 /**
mbed_official 130:1dec54e4aec3 4488 * @brief EXTI6 configuration
mbed_official 130:1dec54e4aec3 4489 */
mbed_official 130:1dec54e4aec3 4490 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
mbed_official 130:1dec54e4aec3 4491 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
mbed_official 130:1dec54e4aec3 4492 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
mbed_official 130:1dec54e4aec3 4493 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
mbed_official 130:1dec54e4aec3 4494 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
mbed_official 130:1dec54e4aec3 4495 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
mbed_official 130:1dec54e4aec3 4496
mbed_official 130:1dec54e4aec3 4497 /**
mbed_official 130:1dec54e4aec3 4498 * @brief EXTI7 configuration
mbed_official 130:1dec54e4aec3 4499 */
mbed_official 130:1dec54e4aec3 4500 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
mbed_official 130:1dec54e4aec3 4501 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
mbed_official 130:1dec54e4aec3 4502 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
mbed_official 130:1dec54e4aec3 4503 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
mbed_official 130:1dec54e4aec3 4504 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
mbed_official 130:1dec54e4aec3 4505 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
mbed_official 130:1dec54e4aec3 4506
mbed_official 130:1dec54e4aec3 4507 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
mbed_official 130:1dec54e4aec3 4508 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
mbed_official 130:1dec54e4aec3 4509 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
mbed_official 130:1dec54e4aec3 4510 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
mbed_official 130:1dec54e4aec3 4511 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
mbed_official 130:1dec54e4aec3 4512
mbed_official 130:1dec54e4aec3 4513 /**
mbed_official 130:1dec54e4aec3 4514 * @brief EXTI8 configuration
mbed_official 130:1dec54e4aec3 4515 */
mbed_official 130:1dec54e4aec3 4516 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
mbed_official 130:1dec54e4aec3 4517 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
mbed_official 130:1dec54e4aec3 4518 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
mbed_official 130:1dec54e4aec3 4519 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
mbed_official 130:1dec54e4aec3 4520 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
mbed_official 130:1dec54e4aec3 4521
mbed_official 130:1dec54e4aec3 4522 /**
mbed_official 130:1dec54e4aec3 4523 * @brief EXTI9 configuration
mbed_official 130:1dec54e4aec3 4524 */
mbed_official 130:1dec54e4aec3 4525 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
mbed_official 130:1dec54e4aec3 4526 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
mbed_official 130:1dec54e4aec3 4527 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
mbed_official 130:1dec54e4aec3 4528 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
mbed_official 130:1dec54e4aec3 4529 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
mbed_official 130:1dec54e4aec3 4530 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
mbed_official 130:1dec54e4aec3 4531
mbed_official 130:1dec54e4aec3 4532 /**
mbed_official 130:1dec54e4aec3 4533 * @brief EXTI10 configuration
mbed_official 130:1dec54e4aec3 4534 */
mbed_official 130:1dec54e4aec3 4535 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
mbed_official 130:1dec54e4aec3 4536 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
mbed_official 130:1dec54e4aec3 4537 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
mbed_official 130:1dec54e4aec3 4538 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
mbed_official 130:1dec54e4aec3 4539 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
mbed_official 130:1dec54e4aec3 4540 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
mbed_official 130:1dec54e4aec3 4541
mbed_official 130:1dec54e4aec3 4542 /**
mbed_official 130:1dec54e4aec3 4543 * @brief EXTI11 configuration
mbed_official 130:1dec54e4aec3 4544 */
mbed_official 130:1dec54e4aec3 4545 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
mbed_official 130:1dec54e4aec3 4546 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
mbed_official 130:1dec54e4aec3 4547 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
mbed_official 130:1dec54e4aec3 4548 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
mbed_official 130:1dec54e4aec3 4549 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
mbed_official 130:1dec54e4aec3 4550
mbed_official 130:1dec54e4aec3 4551 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
mbed_official 130:1dec54e4aec3 4552 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
mbed_official 130:1dec54e4aec3 4553 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
mbed_official 130:1dec54e4aec3 4554 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
mbed_official 130:1dec54e4aec3 4555 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
mbed_official 130:1dec54e4aec3 4556
mbed_official 130:1dec54e4aec3 4557 /**
mbed_official 130:1dec54e4aec3 4558 * @brief EXTI12 configuration
mbed_official 130:1dec54e4aec3 4559 */
mbed_official 130:1dec54e4aec3 4560 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
mbed_official 130:1dec54e4aec3 4561 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
mbed_official 130:1dec54e4aec3 4562 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
mbed_official 130:1dec54e4aec3 4563 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
mbed_official 130:1dec54e4aec3 4564 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
mbed_official 130:1dec54e4aec3 4565
mbed_official 130:1dec54e4aec3 4566 /**
mbed_official 130:1dec54e4aec3 4567 * @brief EXTI13 configuration
mbed_official 130:1dec54e4aec3 4568 */
mbed_official 130:1dec54e4aec3 4569 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
mbed_official 130:1dec54e4aec3 4570 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
mbed_official 130:1dec54e4aec3 4571 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
mbed_official 130:1dec54e4aec3 4572 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
mbed_official 130:1dec54e4aec3 4573 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
mbed_official 130:1dec54e4aec3 4574
mbed_official 130:1dec54e4aec3 4575 /**
mbed_official 130:1dec54e4aec3 4576 * @brief EXTI14 configuration
mbed_official 130:1dec54e4aec3 4577 */
mbed_official 130:1dec54e4aec3 4578 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
mbed_official 130:1dec54e4aec3 4579 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
mbed_official 130:1dec54e4aec3 4580 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
mbed_official 130:1dec54e4aec3 4581 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
mbed_official 130:1dec54e4aec3 4582 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
mbed_official 130:1dec54e4aec3 4583
mbed_official 130:1dec54e4aec3 4584 /**
mbed_official 130:1dec54e4aec3 4585 * @brief EXTI15 configuration
mbed_official 130:1dec54e4aec3 4586 */
mbed_official 130:1dec54e4aec3 4587 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
mbed_official 130:1dec54e4aec3 4588 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
mbed_official 130:1dec54e4aec3 4589 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
mbed_official 130:1dec54e4aec3 4590 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
mbed_official 130:1dec54e4aec3 4591 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
mbed_official 130:1dec54e4aec3 4592
mbed_official 130:1dec54e4aec3 4593 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
mbed_official 130:1dec54e4aec3 4594 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
mbed_official 130:1dec54e4aec3 4595 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
mbed_official 130:1dec54e4aec3 4596 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
mbed_official 130:1dec54e4aec3 4597 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
mbed_official 130:1dec54e4aec3 4598
mbed_official 130:1dec54e4aec3 4599 /* Old Bit definition maintained for legacy purpose */
mbed_official 130:1dec54e4aec3 4600 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF
mbed_official 130:1dec54e4aec3 4601 /******************************************************************************/
mbed_official 130:1dec54e4aec3 4602 /* */
mbed_official 130:1dec54e4aec3 4603 /* Timers (TIM) */
mbed_official 130:1dec54e4aec3 4604 /* */
mbed_official 130:1dec54e4aec3 4605 /******************************************************************************/
mbed_official 130:1dec54e4aec3 4606 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 130:1dec54e4aec3 4607 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
mbed_official 130:1dec54e4aec3 4608 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
mbed_official 130:1dec54e4aec3 4609 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
mbed_official 130:1dec54e4aec3 4610 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
mbed_official 130:1dec54e4aec3 4611 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
mbed_official 130:1dec54e4aec3 4612
mbed_official 130:1dec54e4aec3 4613 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 130:1dec54e4aec3 4614 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4615 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4616
mbed_official 130:1dec54e4aec3 4617 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
mbed_official 130:1dec54e4aec3 4618
mbed_official 130:1dec54e4aec3 4619 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
mbed_official 130:1dec54e4aec3 4620 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4621 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4622
mbed_official 130:1dec54e4aec3 4623 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 130:1dec54e4aec3 4624 #define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
mbed_official 130:1dec54e4aec3 4625 #define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
mbed_official 130:1dec54e4aec3 4626 #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
mbed_official 130:1dec54e4aec3 4627
mbed_official 130:1dec54e4aec3 4628 #define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 130:1dec54e4aec3 4629 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4630 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4631 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4632
mbed_official 130:1dec54e4aec3 4633 #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
mbed_official 130:1dec54e4aec3 4634 #define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 130:1dec54e4aec3 4635 #define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 130:1dec54e4aec3 4636 #define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 130:1dec54e4aec3 4637 #define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 130:1dec54e4aec3 4638 #define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 130:1dec54e4aec3 4639 #define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 130:1dec54e4aec3 4640 #define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 130:1dec54e4aec3 4641
mbed_official 130:1dec54e4aec3 4642 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 130:1dec54e4aec3 4643 #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 130:1dec54e4aec3 4644 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4645 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4646 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4647
mbed_official 130:1dec54e4aec3 4648 #define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!< OCREF clear selection */
mbed_official 130:1dec54e4aec3 4649
mbed_official 130:1dec54e4aec3 4650 #define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 130:1dec54e4aec3 4651 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4652 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4653 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4654
mbed_official 130:1dec54e4aec3 4655 #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
mbed_official 130:1dec54e4aec3 4656
mbed_official 130:1dec54e4aec3 4657 #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 130:1dec54e4aec3 4658 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4659 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4660 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4661 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
mbed_official 130:1dec54e4aec3 4662
mbed_official 130:1dec54e4aec3 4663 #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 130:1dec54e4aec3 4664 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4665 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4666
mbed_official 130:1dec54e4aec3 4667 #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
mbed_official 130:1dec54e4aec3 4668 #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
mbed_official 130:1dec54e4aec3 4669
mbed_official 130:1dec54e4aec3 4670 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 130:1dec54e4aec3 4671 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
mbed_official 130:1dec54e4aec3 4672 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 130:1dec54e4aec3 4673 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 130:1dec54e4aec3 4674 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 130:1dec54e4aec3 4675 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 130:1dec54e4aec3 4676 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
mbed_official 130:1dec54e4aec3 4677 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
mbed_official 130:1dec54e4aec3 4678 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
mbed_official 130:1dec54e4aec3 4679 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
mbed_official 130:1dec54e4aec3 4680 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 130:1dec54e4aec3 4681 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 130:1dec54e4aec3 4682 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 130:1dec54e4aec3 4683 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 130:1dec54e4aec3 4684 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
mbed_official 130:1dec54e4aec3 4685 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
mbed_official 130:1dec54e4aec3 4686
mbed_official 130:1dec54e4aec3 4687 /******************** Bit definition for TIM_SR register ********************/
mbed_official 130:1dec54e4aec3 4688 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
mbed_official 130:1dec54e4aec3 4689 #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 130:1dec54e4aec3 4690 #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 130:1dec54e4aec3 4691 #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 130:1dec54e4aec3 4692 #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 130:1dec54e4aec3 4693 #define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
mbed_official 130:1dec54e4aec3 4694 #define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
mbed_official 130:1dec54e4aec3 4695 #define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
mbed_official 130:1dec54e4aec3 4696 #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 130:1dec54e4aec3 4697 #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 130:1dec54e4aec3 4698 #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 130:1dec54e4aec3 4699 #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 130:1dec54e4aec3 4700
mbed_official 130:1dec54e4aec3 4701 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 130:1dec54e4aec3 4702 #define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
mbed_official 130:1dec54e4aec3 4703 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
mbed_official 130:1dec54e4aec3 4704 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
mbed_official 130:1dec54e4aec3 4705 #define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
mbed_official 130:1dec54e4aec3 4706 #define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
mbed_official 130:1dec54e4aec3 4707 #define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
mbed_official 130:1dec54e4aec3 4708 #define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
mbed_official 130:1dec54e4aec3 4709 #define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
mbed_official 130:1dec54e4aec3 4710
mbed_official 130:1dec54e4aec3 4711 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 130:1dec54e4aec3 4712 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 130:1dec54e4aec3 4713 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4714 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4715
mbed_official 130:1dec54e4aec3 4716 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
mbed_official 130:1dec54e4aec3 4717 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
mbed_official 130:1dec54e4aec3 4718
mbed_official 130:1dec54e4aec3 4719 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 130:1dec54e4aec3 4720 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4721 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4722 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4723
mbed_official 130:1dec54e4aec3 4724 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
mbed_official 130:1dec54e4aec3 4725
mbed_official 130:1dec54e4aec3 4726 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 130:1dec54e4aec3 4727 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4728 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4729
mbed_official 130:1dec54e4aec3 4730 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
mbed_official 130:1dec54e4aec3 4731 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
mbed_official 130:1dec54e4aec3 4732
mbed_official 130:1dec54e4aec3 4733 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 130:1dec54e4aec3 4734 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4735 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4736 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4737
mbed_official 130:1dec54e4aec3 4738 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
mbed_official 130:1dec54e4aec3 4739
mbed_official 130:1dec54e4aec3 4740 /*----------------------------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 4741
mbed_official 130:1dec54e4aec3 4742 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 130:1dec54e4aec3 4743 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4744 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4745
mbed_official 130:1dec54e4aec3 4746 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 130:1dec54e4aec3 4747 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4748 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4749 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4750 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
mbed_official 130:1dec54e4aec3 4751
mbed_official 130:1dec54e4aec3 4752 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 130:1dec54e4aec3 4753 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4754 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4755
mbed_official 130:1dec54e4aec3 4756 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 130:1dec54e4aec3 4757 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4758 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4759 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4760 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
mbed_official 130:1dec54e4aec3 4761
mbed_official 130:1dec54e4aec3 4762 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 130:1dec54e4aec3 4763 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 130:1dec54e4aec3 4764 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4765 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4766
mbed_official 130:1dec54e4aec3 4767 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
mbed_official 130:1dec54e4aec3 4768 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
mbed_official 130:1dec54e4aec3 4769
mbed_official 130:1dec54e4aec3 4770 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 130:1dec54e4aec3 4771 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4772 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4773 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4774
mbed_official 130:1dec54e4aec3 4775 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
mbed_official 130:1dec54e4aec3 4776
mbed_official 130:1dec54e4aec3 4777 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 130:1dec54e4aec3 4778 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4779 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4780
mbed_official 130:1dec54e4aec3 4781 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
mbed_official 130:1dec54e4aec3 4782 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
mbed_official 130:1dec54e4aec3 4783
mbed_official 130:1dec54e4aec3 4784 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 130:1dec54e4aec3 4785 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4786 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4787 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4788
mbed_official 130:1dec54e4aec3 4789 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
mbed_official 130:1dec54e4aec3 4790
mbed_official 130:1dec54e4aec3 4791 /*----------------------------------------------------------------------------*/
mbed_official 130:1dec54e4aec3 4792
mbed_official 130:1dec54e4aec3 4793 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 130:1dec54e4aec3 4794 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4795 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4796
mbed_official 130:1dec54e4aec3 4797 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 130:1dec54e4aec3 4798 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4799 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4800 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4801 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
mbed_official 130:1dec54e4aec3 4802
mbed_official 130:1dec54e4aec3 4803 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 130:1dec54e4aec3 4804 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4805 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4806
mbed_official 130:1dec54e4aec3 4807 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 130:1dec54e4aec3 4808 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4809 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4810 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4811 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
mbed_official 130:1dec54e4aec3 4812
mbed_official 130:1dec54e4aec3 4813 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 130:1dec54e4aec3 4814 #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
mbed_official 130:1dec54e4aec3 4815 #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
mbed_official 130:1dec54e4aec3 4816 #define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 130:1dec54e4aec3 4817 #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 130:1dec54e4aec3 4818 #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
mbed_official 130:1dec54e4aec3 4819 #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
mbed_official 130:1dec54e4aec3 4820 #define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 130:1dec54e4aec3 4821 #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 130:1dec54e4aec3 4822 #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
mbed_official 130:1dec54e4aec3 4823 #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
mbed_official 130:1dec54e4aec3 4824 #define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 130:1dec54e4aec3 4825 #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 130:1dec54e4aec3 4826 #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
mbed_official 130:1dec54e4aec3 4827 #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
mbed_official 130:1dec54e4aec3 4828 #define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 130:1dec54e4aec3 4829
mbed_official 130:1dec54e4aec3 4830 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 130:1dec54e4aec3 4831 #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
mbed_official 130:1dec54e4aec3 4832
mbed_official 130:1dec54e4aec3 4833 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 130:1dec54e4aec3 4834 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
mbed_official 130:1dec54e4aec3 4835
mbed_official 130:1dec54e4aec3 4836 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 130:1dec54e4aec3 4837 #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
mbed_official 130:1dec54e4aec3 4838
mbed_official 130:1dec54e4aec3 4839 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 130:1dec54e4aec3 4840 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
mbed_official 130:1dec54e4aec3 4841
mbed_official 130:1dec54e4aec3 4842 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 130:1dec54e4aec3 4843 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
mbed_official 130:1dec54e4aec3 4844
mbed_official 130:1dec54e4aec3 4845 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 130:1dec54e4aec3 4846 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
mbed_official 130:1dec54e4aec3 4847
mbed_official 130:1dec54e4aec3 4848 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 130:1dec54e4aec3 4849 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
mbed_official 130:1dec54e4aec3 4850
mbed_official 130:1dec54e4aec3 4851 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 130:1dec54e4aec3 4852 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
mbed_official 130:1dec54e4aec3 4853
mbed_official 130:1dec54e4aec3 4854 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 130:1dec54e4aec3 4855 #define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 130:1dec54e4aec3 4856 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4857 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4858 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4859 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
mbed_official 130:1dec54e4aec3 4860 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
mbed_official 130:1dec54e4aec3 4861 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
mbed_official 130:1dec54e4aec3 4862 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
mbed_official 130:1dec54e4aec3 4863 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
mbed_official 130:1dec54e4aec3 4864
mbed_official 130:1dec54e4aec3 4865 #define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 130:1dec54e4aec3 4866 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4867 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4868
mbed_official 130:1dec54e4aec3 4869 #define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
mbed_official 130:1dec54e4aec3 4870 #define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
mbed_official 130:1dec54e4aec3 4871 #define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
mbed_official 130:1dec54e4aec3 4872 #define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
mbed_official 130:1dec54e4aec3 4873 #define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
mbed_official 130:1dec54e4aec3 4874 #define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
mbed_official 130:1dec54e4aec3 4875
mbed_official 130:1dec54e4aec3 4876 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 130:1dec54e4aec3 4877 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 130:1dec54e4aec3 4878 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4879 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4880 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4881 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
mbed_official 130:1dec54e4aec3 4882 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
mbed_official 130:1dec54e4aec3 4883
mbed_official 130:1dec54e4aec3 4884 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 130:1dec54e4aec3 4885 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4886 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4887 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
mbed_official 130:1dec54e4aec3 4888 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
mbed_official 130:1dec54e4aec3 4889 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
mbed_official 130:1dec54e4aec3 4890
mbed_official 130:1dec54e4aec3 4891 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 130:1dec54e4aec3 4892 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
mbed_official 130:1dec54e4aec3 4893
mbed_official 130:1dec54e4aec3 4894 /******************* Bit definition for TIM_OR register *********************/
mbed_official 130:1dec54e4aec3 4895 #define TIM14_OR_TI1_RMP ((uint16_t)0x0003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
mbed_official 130:1dec54e4aec3 4896 #define TIM14_OR_TI1_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 130:1dec54e4aec3 4897 #define TIM14_OR_TI1_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 130:1dec54e4aec3 4898
mbed_official 130:1dec54e4aec3 4899
mbed_official 130:1dec54e4aec3 4900 /******************************************************************************/
mbed_official 130:1dec54e4aec3 4901 /* */
mbed_official 130:1dec54e4aec3 4902 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 130:1dec54e4aec3 4903 /* */
mbed_official 130:1dec54e4aec3 4904 /******************************************************************************/
mbed_official 130:1dec54e4aec3 4905 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 130:1dec54e4aec3 4906 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
mbed_official 130:1dec54e4aec3 4907 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
mbed_official 130:1dec54e4aec3 4908 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 130:1dec54e4aec3 4909 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 130:1dec54e4aec3 4910 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 130:1dec54e4aec3 4911 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 130:1dec54e4aec3 4912 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 130:1dec54e4aec3 4913 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
mbed_official 130:1dec54e4aec3 4914 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 130:1dec54e4aec3 4915 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 130:1dec54e4aec3 4916 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 130:1dec54e4aec3 4917 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
mbed_official 130:1dec54e4aec3 4918 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
mbed_official 130:1dec54e4aec3 4919 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
mbed_official 130:1dec54e4aec3 4920 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
mbed_official 130:1dec54e4aec3 4921 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 130:1dec54e4aec3 4922 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 130:1dec54e4aec3 4923 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 4924 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 4925 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 4926 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 4927 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 130:1dec54e4aec3 4928 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 130:1dec54e4aec3 4929 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 4930 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 4931 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 4932 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 4933 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
mbed_official 130:1dec54e4aec3 4934 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
mbed_official 130:1dec54e4aec3 4935 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
mbed_official 130:1dec54e4aec3 4936
mbed_official 130:1dec54e4aec3 4937 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 130:1dec54e4aec3 4938 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
mbed_official 130:1dec54e4aec3 4939 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 130:1dec54e4aec3 4940 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 130:1dec54e4aec3 4941 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 130:1dec54e4aec3 4942 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 130:1dec54e4aec3 4943 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 130:1dec54e4aec3 4944 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 130:1dec54e4aec3 4945 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 130:1dec54e4aec3 4946 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 4947 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 4948 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 130:1dec54e4aec3 4949 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
mbed_official 130:1dec54e4aec3 4950 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
mbed_official 130:1dec54e4aec3 4951 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
mbed_official 130:1dec54e4aec3 4952 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
mbed_official 130:1dec54e4aec3 4953 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
mbed_official 130:1dec54e4aec3 4954 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
mbed_official 130:1dec54e4aec3 4955 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 130:1dec54e4aec3 4956 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 4957 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 4958 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
mbed_official 130:1dec54e4aec3 4959 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
mbed_official 130:1dec54e4aec3 4960
mbed_official 130:1dec54e4aec3 4961 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 130:1dec54e4aec3 4962 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 130:1dec54e4aec3 4963 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 130:1dec54e4aec3 4964 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 130:1dec54e4aec3 4965 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 130:1dec54e4aec3 4966 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
mbed_official 130:1dec54e4aec3 4967 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
mbed_official 130:1dec54e4aec3 4968 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 130:1dec54e4aec3 4969 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 130:1dec54e4aec3 4970 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 130:1dec54e4aec3 4971 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 130:1dec54e4aec3 4972 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 130:1dec54e4aec3 4973 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 130:1dec54e4aec3 4974 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
mbed_official 130:1dec54e4aec3 4975 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
mbed_official 130:1dec54e4aec3 4976 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
mbed_official 130:1dec54e4aec3 4977 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
mbed_official 130:1dec54e4aec3 4978 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 130:1dec54e4aec3 4979 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 4980 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 4981 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 4982 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
mbed_official 130:1dec54e4aec3 4983 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 4984 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 4985 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
mbed_official 130:1dec54e4aec3 4986
mbed_official 130:1dec54e4aec3 4987 /****************** Bit definition for USART_BRR register *******************/
mbed_official 130:1dec54e4aec3 4988 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
mbed_official 130:1dec54e4aec3 4989 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
mbed_official 130:1dec54e4aec3 4990
mbed_official 130:1dec54e4aec3 4991 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 130:1dec54e4aec3 4992 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 130:1dec54e4aec3 4993 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
mbed_official 130:1dec54e4aec3 4994
mbed_official 130:1dec54e4aec3 4995
mbed_official 130:1dec54e4aec3 4996 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 130:1dec54e4aec3 4997 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
mbed_official 130:1dec54e4aec3 4998 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
mbed_official 130:1dec54e4aec3 4999
mbed_official 130:1dec54e4aec3 5000 /******************* Bit definition for USART_RQR register ******************/
mbed_official 130:1dec54e4aec3 5001 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
mbed_official 130:1dec54e4aec3 5002 #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
mbed_official 130:1dec54e4aec3 5003 #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
mbed_official 130:1dec54e4aec3 5004 #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
mbed_official 130:1dec54e4aec3 5005 #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
mbed_official 130:1dec54e4aec3 5006
mbed_official 130:1dec54e4aec3 5007 /******************* Bit definition for USART_ISR register ******************/
mbed_official 130:1dec54e4aec3 5008 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 130:1dec54e4aec3 5009 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 130:1dec54e4aec3 5010 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
mbed_official 130:1dec54e4aec3 5011 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 130:1dec54e4aec3 5012 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 130:1dec54e4aec3 5013 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 130:1dec54e4aec3 5014 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 130:1dec54e4aec3 5015 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 130:1dec54e4aec3 5016 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 130:1dec54e4aec3 5017 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
mbed_official 130:1dec54e4aec3 5018 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
mbed_official 130:1dec54e4aec3 5019 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
mbed_official 130:1dec54e4aec3 5020 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
mbed_official 130:1dec54e4aec3 5021 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
mbed_official 130:1dec54e4aec3 5022 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
mbed_official 130:1dec54e4aec3 5023 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
mbed_official 130:1dec54e4aec3 5024 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
mbed_official 130:1dec54e4aec3 5025 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
mbed_official 130:1dec54e4aec3 5026 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
mbed_official 130:1dec54e4aec3 5027 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
mbed_official 130:1dec54e4aec3 5028 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
mbed_official 130:1dec54e4aec3 5029 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
mbed_official 130:1dec54e4aec3 5030
mbed_official 130:1dec54e4aec3 5031 /******************* Bit definition for USART_ICR register ******************/
mbed_official 130:1dec54e4aec3 5032 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
mbed_official 130:1dec54e4aec3 5033 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
mbed_official 130:1dec54e4aec3 5034 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
mbed_official 130:1dec54e4aec3 5035 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
mbed_official 130:1dec54e4aec3 5036 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
mbed_official 130:1dec54e4aec3 5037 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
mbed_official 130:1dec54e4aec3 5038 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
mbed_official 130:1dec54e4aec3 5039 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
mbed_official 130:1dec54e4aec3 5040 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
mbed_official 130:1dec54e4aec3 5041 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
mbed_official 130:1dec54e4aec3 5042 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
mbed_official 130:1dec54e4aec3 5043 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
mbed_official 130:1dec54e4aec3 5044
mbed_official 130:1dec54e4aec3 5045 /******************* Bit definition for USART_RDR register ******************/
mbed_official 130:1dec54e4aec3 5046 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 130:1dec54e4aec3 5047
mbed_official 130:1dec54e4aec3 5048 /******************* Bit definition for USART_TDR register ******************/
mbed_official 130:1dec54e4aec3 5049 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 130:1dec54e4aec3 5050
mbed_official 130:1dec54e4aec3 5051 /******************************************************************************/
mbed_official 130:1dec54e4aec3 5052 /* */
mbed_official 130:1dec54e4aec3 5053 /* Window WATCHDOG (WWDG) */
mbed_official 130:1dec54e4aec3 5054 /* */
mbed_official 130:1dec54e4aec3 5055 /******************************************************************************/
mbed_official 130:1dec54e4aec3 5056
mbed_official 130:1dec54e4aec3 5057 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 130:1dec54e4aec3 5058 #define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 130:1dec54e4aec3 5059 #define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 5060 #define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 5061 #define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 5062 #define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 5063 #define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
mbed_official 130:1dec54e4aec3 5064 #define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
mbed_official 130:1dec54e4aec3 5065 #define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
mbed_official 130:1dec54e4aec3 5066
mbed_official 130:1dec54e4aec3 5067 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
mbed_official 130:1dec54e4aec3 5068
mbed_official 130:1dec54e4aec3 5069 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 130:1dec54e4aec3 5070 #define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
mbed_official 130:1dec54e4aec3 5071 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 5072 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 5073 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
mbed_official 130:1dec54e4aec3 5074 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
mbed_official 130:1dec54e4aec3 5075 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
mbed_official 130:1dec54e4aec3 5076 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
mbed_official 130:1dec54e4aec3 5077 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
mbed_official 130:1dec54e4aec3 5078
mbed_official 130:1dec54e4aec3 5079 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
mbed_official 130:1dec54e4aec3 5080 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
mbed_official 130:1dec54e4aec3 5081 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
mbed_official 130:1dec54e4aec3 5082
mbed_official 130:1dec54e4aec3 5083 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
mbed_official 130:1dec54e4aec3 5084
mbed_official 130:1dec54e4aec3 5085 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 130:1dec54e4aec3 5086 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
mbed_official 130:1dec54e4aec3 5087
mbed_official 130:1dec54e4aec3 5088 /**
mbed_official 130:1dec54e4aec3 5089 * @}
mbed_official 130:1dec54e4aec3 5090 */
mbed_official 130:1dec54e4aec3 5091
mbed_official 130:1dec54e4aec3 5092 /**
mbed_official 130:1dec54e4aec3 5093 * @}
mbed_official 130:1dec54e4aec3 5094 */
mbed_official 130:1dec54e4aec3 5095
mbed_official 130:1dec54e4aec3 5096 #ifdef USE_STDPERIPH_DRIVER
mbed_official 130:1dec54e4aec3 5097 #include "stm32f0xx_conf.h"
mbed_official 130:1dec54e4aec3 5098 #endif
mbed_official 130:1dec54e4aec3 5099
mbed_official 130:1dec54e4aec3 5100 /** @addtogroup Exported_macro
mbed_official 130:1dec54e4aec3 5101 * @{
mbed_official 130:1dec54e4aec3 5102 */
mbed_official 130:1dec54e4aec3 5103 /**
mbed_official 130:1dec54e4aec3 5104 * @}
mbed_official 130:1dec54e4aec3 5105 */
mbed_official 130:1dec54e4aec3 5106
mbed_official 130:1dec54e4aec3 5107 #ifdef __cplusplus
mbed_official 130:1dec54e4aec3 5108 }
mbed_official 130:1dec54e4aec3 5109 #endif
mbed_official 130:1dec54e4aec3 5110
mbed_official 130:1dec54e4aec3 5111 #endif /* __STM32F0XX_H */
mbed_official 130:1dec54e4aec3 5112
mbed_official 130:1dec54e4aec3 5113 /**
mbed_official 130:1dec54e4aec3 5114 * @}
mbed_official 130:1dec54e4aec3 5115 */
mbed_official 130:1dec54e4aec3 5116
mbed_official 130:1dec54e4aec3 5117 /**
mbed_official 130:1dec54e4aec3 5118 * @}
mbed_official 130:1dec54e4aec3 5119 */
mbed_official 130:1dec54e4aec3 5120
mbed_official 130:1dec54e4aec3 5121 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/