Mihail Stoyanov / mbed

Fork of the official mbed C/C++ SDK provides the software platform and libraries to build your applications. The fork has the documentation converted to Doxygen format

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LPC2368/ARM/core_arm7.h@27:7110ebee3484, 2011-11-29 (annotated)

Committer:
emilmont
Date:
Tue Nov 29 14:59:27 2011 +0000
Revision:
27:7110ebee3484
New Libraries 11.11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1 /* mbed Microcontroller Library
emilmont 27:7110ebee3484 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
emilmont 27:7110ebee3484 3 *
emilmont 27:7110ebee3484 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
emilmont 27:7110ebee3484 5 * based on core_cm3.h, V1.20
emilmont 27:7110ebee3484 6 */
emilmont 27:7110ebee3484 7
emilmont 27:7110ebee3484 8 #ifndef __ARM7_CORE_H__
emilmont 27:7110ebee3484 9 #define __ARM7_CORE_H__
emilmont 27:7110ebee3484 10
emilmont 27:7110ebee3484 11 #ifdef __cplusplus
emilmont 27:7110ebee3484 12 extern "C" {
emilmont 27:7110ebee3484 13 #endif
emilmont 27:7110ebee3484 14
emilmont 27:7110ebee3484 15 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
emilmont 27:7110ebee3484 16 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
emilmont 27:7110ebee3484 17 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
emilmont 27:7110ebee3484 18
emilmont 27:7110ebee3484 19 #define __CORTEX_M (0x03) /*!< Cortex core */
emilmont 27:7110ebee3484 20
emilmont 27:7110ebee3484 21 /**
emilmont 27:7110ebee3484 22 * Lint configuration \n
emilmont 27:7110ebee3484 23 * ----------------------- \n
emilmont 27:7110ebee3484 24 *
emilmont 27:7110ebee3484 25 * The following Lint messages will be suppressed and not shown: \n
emilmont 27:7110ebee3484 26 * \n
emilmont 27:7110ebee3484 27 * --- Error 10: --- \n
emilmont 27:7110ebee3484 28 * register uint32_t __regBasePri __asm("basepri"); \n
emilmont 27:7110ebee3484 29 * Error 10: Expecting ';' \n
emilmont 27:7110ebee3484 30 * \n
emilmont 27:7110ebee3484 31 * --- Error 530: --- \n
emilmont 27:7110ebee3484 32 * return(__regBasePri); \n
emilmont 27:7110ebee3484 33 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
emilmont 27:7110ebee3484 34 * \n
emilmont 27:7110ebee3484 35 * --- Error 550: --- \n
emilmont 27:7110ebee3484 36 * __regBasePri = (basePri & 0x1ff); \n
emilmont 27:7110ebee3484 37 * } \n
emilmont 27:7110ebee3484 38 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
emilmont 27:7110ebee3484 39 * \n
emilmont 27:7110ebee3484 40 * --- Error 754: --- \n
emilmont 27:7110ebee3484 41 * uint32_t RESERVED0[24]; \n
emilmont 27:7110ebee3484 42 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
emilmont 27:7110ebee3484 43 * \n
emilmont 27:7110ebee3484 44 * --- Error 750: --- \n
emilmont 27:7110ebee3484 45 * #define __CM3_CORE_H__ \n
emilmont 27:7110ebee3484 46 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
emilmont 27:7110ebee3484 47 * \n
emilmont 27:7110ebee3484 48 * --- Error 528: --- \n
emilmont 27:7110ebee3484 49 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
emilmont 27:7110ebee3484 50 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
emilmont 27:7110ebee3484 51 * \n
emilmont 27:7110ebee3484 52 * --- Error 751: --- \n
emilmont 27:7110ebee3484 53 * } InterruptType_Type; \n
emilmont 27:7110ebee3484 54 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
emilmont 27:7110ebee3484 55 * \n
emilmont 27:7110ebee3484 56 * \n
emilmont 27:7110ebee3484 57 * Note: To re-enable a Message, insert a space before 'lint' * \n
emilmont 27:7110ebee3484 58 *
emilmont 27:7110ebee3484 59 */
emilmont 27:7110ebee3484 60
emilmont 27:7110ebee3484 61 /*lint -save */
emilmont 27:7110ebee3484 62 /*lint -e10 */
emilmont 27:7110ebee3484 63 /*lint -e530 */
emilmont 27:7110ebee3484 64 /*lint -e550 */
emilmont 27:7110ebee3484 65 /*lint -e754 */
emilmont 27:7110ebee3484 66 /*lint -e750 */
emilmont 27:7110ebee3484 67 /*lint -e528 */
emilmont 27:7110ebee3484 68 /*lint -e751 */
emilmont 27:7110ebee3484 69
emilmont 27:7110ebee3484 70 #include <stdint.h> /* Include standard types */
emilmont 27:7110ebee3484 71
emilmont 27:7110ebee3484 72 #if defined ( __CC_ARM )
emilmont 27:7110ebee3484 73 /**
emilmont 27:7110ebee3484 74 * @brief Return the Main Stack Pointer (current ARM7 stack)
emilmont 27:7110ebee3484 75 *
emilmont 27:7110ebee3484 76 * @param none
emilmont 27:7110ebee3484 77 * @return uint32_t Main Stack Pointer
emilmont 27:7110ebee3484 78 *
emilmont 27:7110ebee3484 79 * Return the current value of the MSP (main stack pointer)
emilmont 27:7110ebee3484 80 * Cortex processor register
emilmont 27:7110ebee3484 81 */
emilmont 27:7110ebee3484 82 extern uint32_t __get_MSP(void);
emilmont 27:7110ebee3484 83 #endif
emilmont 27:7110ebee3484 84
emilmont 27:7110ebee3484 85
emilmont 27:7110ebee3484 86 #if defined (__ICCARM__)
emilmont 27:7110ebee3484 87 #include <intrinsics.h> /* IAR Intrinsics */
emilmont 27:7110ebee3484 88 #endif
emilmont 27:7110ebee3484 89
emilmont 27:7110ebee3484 90
emilmont 27:7110ebee3484 91 #ifndef __NVIC_PRIO_BITS
emilmont 27:7110ebee3484 92 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
emilmont 27:7110ebee3484 93 #endif
emilmont 27:7110ebee3484 94
emilmont 27:7110ebee3484 95 typedef struct
emilmont 27:7110ebee3484 96 {
emilmont 27:7110ebee3484 97 uint32_t IRQStatus;
emilmont 27:7110ebee3484 98 uint32_t FIQStatus;
emilmont 27:7110ebee3484 99 uint32_t RawIntr;
emilmont 27:7110ebee3484 100 uint32_t IntSelect;
emilmont 27:7110ebee3484 101 uint32_t IntEnable;
emilmont 27:7110ebee3484 102 uint32_t IntEnClr;
emilmont 27:7110ebee3484 103 uint32_t SoftInt;
emilmont 27:7110ebee3484 104 uint32_t SoftIntClr;
emilmont 27:7110ebee3484 105 uint32_t Protection;
emilmont 27:7110ebee3484 106 uint32_t SWPriorityMask;
emilmont 27:7110ebee3484 107 uint32_t RESERVED0[54];
emilmont 27:7110ebee3484 108 uint32_t VectAddr[32];
emilmont 27:7110ebee3484 109 uint32_t RESERVED1[32];
emilmont 27:7110ebee3484 110 uint32_t VectPriority[32];
emilmont 27:7110ebee3484 111 uint32_t RESERVED2[800];
emilmont 27:7110ebee3484 112 uint32_t Address;
emilmont 27:7110ebee3484 113 } NVIC_TypeDef;
emilmont 27:7110ebee3484 114
emilmont 27:7110ebee3484 115 #define NVIC_BASE (0xFFFFF000)
emilmont 27:7110ebee3484 116 #define NVIC (( NVIC_TypeDef *) NVIC_BASE)
emilmont 27:7110ebee3484 117
emilmont 27:7110ebee3484 118
emilmont 27:7110ebee3484 119
emilmont 27:7110ebee3484 120 /**
emilmont 27:7110ebee3484 121 * IO definitions
emilmont 27:7110ebee3484 122 *
emilmont 27:7110ebee3484 123 * define access restrictions to peripheral registers
emilmont 27:7110ebee3484 124 */
emilmont 27:7110ebee3484 125
emilmont 27:7110ebee3484 126 #ifdef __cplusplus
emilmont 27:7110ebee3484 127 #define __I volatile /*!< defines 'read only' permissions */
emilmont 27:7110ebee3484 128 #else
emilmont 27:7110ebee3484 129 #define __I volatile const /*!< defines 'read only' permissions */
emilmont 27:7110ebee3484 130 #endif
emilmont 27:7110ebee3484 131 #define __O volatile /*!< defines 'write only' permissions */
emilmont 27:7110ebee3484 132 #define __IO volatile /*!< defines 'read / write' permissions */
emilmont 27:7110ebee3484 133
emilmont 27:7110ebee3484 134
emilmont 27:7110ebee3484 135
emilmont 27:7110ebee3484 136
emilmont 27:7110ebee3484 137
emilmont 27:7110ebee3484 138 #if defined ( __CC_ARM )
emilmont 27:7110ebee3484 139 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 27:7110ebee3484 140 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 27:7110ebee3484 141
emilmont 27:7110ebee3484 142 #elif defined ( __ICCARM__ )
emilmont 27:7110ebee3484 143 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 27:7110ebee3484 144 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
emilmont 27:7110ebee3484 145
emilmont 27:7110ebee3484 146 #elif defined ( __GNUC__ )
emilmont 27:7110ebee3484 147 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 27:7110ebee3484 148 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 27:7110ebee3484 149
emilmont 27:7110ebee3484 150 #elif defined ( __TASKING__ )
emilmont 27:7110ebee3484 151 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 27:7110ebee3484 152 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 27:7110ebee3484 153
emilmont 27:7110ebee3484 154 #endif
emilmont 27:7110ebee3484 155
emilmont 27:7110ebee3484 156
emilmont 27:7110ebee3484 157 /* ################### Compiler specific Intrinsics ########################### */
emilmont 27:7110ebee3484 158
emilmont 27:7110ebee3484 159 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 27:7110ebee3484 160 /* ARM armcc specific functions */
emilmont 27:7110ebee3484 161
emilmont 27:7110ebee3484 162 #define __enable_fault_irq __enable_fiq
emilmont 27:7110ebee3484 163 #define __disable_fault_irq __disable_fiq
emilmont 27:7110ebee3484 164
emilmont 27:7110ebee3484 165 #define __NOP __nop
emilmont 27:7110ebee3484 166 //#define __WFI __wfi
emilmont 27:7110ebee3484 167 //#define __WFE __wfe
emilmont 27:7110ebee3484 168 //#define __SEV __sev
emilmont 27:7110ebee3484 169 //#define __ISB() __isb(0)
emilmont 27:7110ebee3484 170 //#define __DSB() __dsb(0)
emilmont 27:7110ebee3484 171 //#define __DMB() __dmb(0)
emilmont 27:7110ebee3484 172 //#define __REV __rev
emilmont 27:7110ebee3484 173 //#define __RBIT __rbit
emilmont 27:7110ebee3484 174 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
emilmont 27:7110ebee3484 175 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
emilmont 27:7110ebee3484 176 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
emilmont 27:7110ebee3484 177 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 27:7110ebee3484 178 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 27:7110ebee3484 179 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 27:7110ebee3484 180
emilmont 27:7110ebee3484 181
emilmont 27:7110ebee3484 182 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
emilmont 27:7110ebee3484 183
emilmont 27:7110ebee3484 184 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
emilmont 27:7110ebee3484 185 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
emilmont 27:7110ebee3484 186 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
emilmont 27:7110ebee3484 187
emilmont 27:7110ebee3484 188 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
emilmont 27:7110ebee3484 189
emilmont 27:7110ebee3484 190 static __INLINE void __enable_irq() {
emilmont 27:7110ebee3484 191 unsigned long temp;
emilmont 27:7110ebee3484 192 __asm__ __volatile__("mrs %0, cpsr\n"
emilmont 27:7110ebee3484 193 "bic %0, %0, #0x80\n"
emilmont 27:7110ebee3484 194 "msr cpsr_c, %0"
emilmont 27:7110ebee3484 195 : "=r" (temp)
emilmont 27:7110ebee3484 196 :
emilmont 27:7110ebee3484 197 : "memory");
emilmont 27:7110ebee3484 198 }
emilmont 27:7110ebee3484 199
emilmont 27:7110ebee3484 200 static __INLINE void __disable_irq() {
emilmont 27:7110ebee3484 201 unsigned long old,temp;
emilmont 27:7110ebee3484 202 __asm__ __volatile__("mrs %0, cpsr\n"
emilmont 27:7110ebee3484 203 "orr %1, %0, #0xc0\n"
emilmont 27:7110ebee3484 204 "msr cpsr_c, %1"
emilmont 27:7110ebee3484 205 : "=r" (old), "=r" (temp)
emilmont 27:7110ebee3484 206 :
emilmont 27:7110ebee3484 207 : "memory");
emilmont 27:7110ebee3484 208 // return (old & 0x80) == 0;
emilmont 27:7110ebee3484 209 }
emilmont 27:7110ebee3484 210
emilmont 27:7110ebee3484 211 static __INLINE void __NOP() { __ASM volatile ("nop"); }
emilmont 27:7110ebee3484 212
emilmont 27:7110ebee3484 213 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
emilmont 27:7110ebee3484 214 /* TASKING carm specific functions */
emilmont 27:7110ebee3484 215
emilmont 27:7110ebee3484 216 /*
emilmont 27:7110ebee3484 217 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 27:7110ebee3484 218 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 27:7110ebee3484 219 * Including the CMSIS ones.
emilmont 27:7110ebee3484 220 */
emilmont 27:7110ebee3484 221
emilmont 27:7110ebee3484 222 #endif
emilmont 27:7110ebee3484 223
emilmont 27:7110ebee3484 224
emilmont 27:7110ebee3484 225 /**
emilmont 27:7110ebee3484 226 * @brief Enable Interrupt in NVIC Interrupt Controller
emilmont 27:7110ebee3484 227 *
emilmont 27:7110ebee3484 228 * @param IRQn_Type IRQn specifies the interrupt number
emilmont 27:7110ebee3484 229 * @return none
emilmont 27:7110ebee3484 230 *
emilmont 27:7110ebee3484 231 * Enable a device specific interupt in the NVIC interrupt controller.
emilmont 27:7110ebee3484 232 * The interrupt number cannot be a negative value.
emilmont 27:7110ebee3484 233 */
emilmont 27:7110ebee3484 234 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 235 {
emilmont 27:7110ebee3484 236 NVIC->IntEnable = 1 << (uint32_t)IRQn;
emilmont 27:7110ebee3484 237 }
emilmont 27:7110ebee3484 238
emilmont 27:7110ebee3484 239
emilmont 27:7110ebee3484 240 /**
emilmont 27:7110ebee3484 241 * @brief Disable the interrupt line for external interrupt specified
emilmont 27:7110ebee3484 242 *
emilmont 27:7110ebee3484 243 * @param IRQn_Type IRQn is the positive number of the external interrupt
emilmont 27:7110ebee3484 244 * @return none
emilmont 27:7110ebee3484 245 *
emilmont 27:7110ebee3484 246 * Disable a device specific interupt in the NVIC interrupt controller.
emilmont 27:7110ebee3484 247 * The interrupt number cannot be a negative value.
emilmont 27:7110ebee3484 248 */
emilmont 27:7110ebee3484 249 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 250 {
emilmont 27:7110ebee3484 251 NVIC->IntEnClr = 1 << (uint32_t)IRQn;
emilmont 27:7110ebee3484 252 }
emilmont 27:7110ebee3484 253
emilmont 27:7110ebee3484 254
emilmont 27:7110ebee3484 255 #ifdef __cplusplus
emilmont 27:7110ebee3484 256 }
emilmont 27:7110ebee3484 257 #endif
emilmont 27:7110ebee3484 258
emilmont 27:7110ebee3484 259 #endif /* __ARM7_CORE_H__ */
emilmont 27:7110ebee3484 260
emilmont 27:7110ebee3484 261 /*lint -restore */