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LPC1768/uARM/core_cmInstr.h@27:7110ebee3484, 2011-11-29 (annotated)

Committer:
emilmont
Date:
Tue Nov 29 14:59:27 2011 +0000
Revision:
27:7110ebee3484
Child:
33:5364839841bd
New Libraries 11.11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1 /**************************************************************************//**
emilmont 27:7110ebee3484 2 * @file core_cmInstr.h
emilmont 27:7110ebee3484 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
emilmont 27:7110ebee3484 4 * @version V2.01
emilmont 27:7110ebee3484 5 * @date 06. December 2010
emilmont 27:7110ebee3484 6 *
emilmont 27:7110ebee3484 7 * @note
emilmont 27:7110ebee3484 8 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
emilmont 27:7110ebee3484 9 *
emilmont 27:7110ebee3484 10 * @par
emilmont 27:7110ebee3484 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 27:7110ebee3484 12 * processor based microcontrollers. This file can be freely distributed
emilmont 27:7110ebee3484 13 * within development tools that are supporting such ARM based processors.
emilmont 27:7110ebee3484 14 *
emilmont 27:7110ebee3484 15 * @par
emilmont 27:7110ebee3484 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 27:7110ebee3484 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 27:7110ebee3484 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 27:7110ebee3484 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 27:7110ebee3484 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 27:7110ebee3484 21 *
emilmont 27:7110ebee3484 22 ******************************************************************************/
emilmont 27:7110ebee3484 23
emilmont 27:7110ebee3484 24 #ifndef __CORE_CMINSTR_H__
emilmont 27:7110ebee3484 25 #define __CORE_CMINSTR_H__
emilmont 27:7110ebee3484 26
emilmont 27:7110ebee3484 27
emilmont 27:7110ebee3484 28 /* ########################## Core Instruction Access ######################### */
emilmont 27:7110ebee3484 29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 27:7110ebee3484 30 Access to dedicated instructions
emilmont 27:7110ebee3484 31 @{
emilmont 27:7110ebee3484 32 */
emilmont 27:7110ebee3484 33
emilmont 27:7110ebee3484 34 #if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
emilmont 27:7110ebee3484 35 /* ARM armcc specific functions */
emilmont 27:7110ebee3484 36
emilmont 27:7110ebee3484 37 /** \brief No Operation
emilmont 27:7110ebee3484 38
emilmont 27:7110ebee3484 39 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 27:7110ebee3484 40 */
emilmont 27:7110ebee3484 41 #define __NOP __nop
emilmont 27:7110ebee3484 42
emilmont 27:7110ebee3484 43
emilmont 27:7110ebee3484 44 /** \brief Wait For Interrupt
emilmont 27:7110ebee3484 45
emilmont 27:7110ebee3484 46 Wait For Interrupt is a hint instruction that suspends execution
emilmont 27:7110ebee3484 47 until one of a number of events occurs.
emilmont 27:7110ebee3484 48 */
emilmont 27:7110ebee3484 49 #define __WFI __wfi
emilmont 27:7110ebee3484 50
emilmont 27:7110ebee3484 51
emilmont 27:7110ebee3484 52 /** \brief Wait For Event
emilmont 27:7110ebee3484 53
emilmont 27:7110ebee3484 54 Wait For Event is a hint instruction that permits the processor to enter
emilmont 27:7110ebee3484 55 a low-power state until one of a number of events occurs.
emilmont 27:7110ebee3484 56 */
emilmont 27:7110ebee3484 57 #define __WFE __wfe
emilmont 27:7110ebee3484 58
emilmont 27:7110ebee3484 59
emilmont 27:7110ebee3484 60 /** \brief Send Event
emilmont 27:7110ebee3484 61
emilmont 27:7110ebee3484 62 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 27:7110ebee3484 63 */
emilmont 27:7110ebee3484 64 #define __SEV __sev
emilmont 27:7110ebee3484 65
emilmont 27:7110ebee3484 66
emilmont 27:7110ebee3484 67 /** \brief Instruction Synchronization Barrier
emilmont 27:7110ebee3484 68
emilmont 27:7110ebee3484 69 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 27:7110ebee3484 70 so that all instructions following the ISB are fetched from cache or
emilmont 27:7110ebee3484 71 memory, after the instruction has been completed.
emilmont 27:7110ebee3484 72 */
emilmont 27:7110ebee3484 73 #define __ISB() __isb(0xF)
emilmont 27:7110ebee3484 74
emilmont 27:7110ebee3484 75
emilmont 27:7110ebee3484 76 /** \brief Data Synchronization Barrier
emilmont 27:7110ebee3484 77
emilmont 27:7110ebee3484 78 This function acts as a special kind of Data Memory Barrier.
emilmont 27:7110ebee3484 79 It completes when all explicit memory accesses before this instruction complete.
emilmont 27:7110ebee3484 80 */
emilmont 27:7110ebee3484 81 #define __DSB() __dsb(0xF)
emilmont 27:7110ebee3484 82
emilmont 27:7110ebee3484 83
emilmont 27:7110ebee3484 84 /** \brief Data Memory Barrier
emilmont 27:7110ebee3484 85
emilmont 27:7110ebee3484 86 This function ensures the apparent order of the explicit memory operations before
emilmont 27:7110ebee3484 87 and after the instruction, without ensuring their completion.
emilmont 27:7110ebee3484 88 */
emilmont 27:7110ebee3484 89 #define __DMB() __dmb(0xF)
emilmont 27:7110ebee3484 90
emilmont 27:7110ebee3484 91
emilmont 27:7110ebee3484 92 /** \brief Reverse byte order (32 bit)
emilmont 27:7110ebee3484 93
emilmont 27:7110ebee3484 94 This function reverses the byte order in integer value.
emilmont 27:7110ebee3484 95
emilmont 27:7110ebee3484 96 \param [in] value Value to reverse
emilmont 27:7110ebee3484 97 \return Reversed value
emilmont 27:7110ebee3484 98 */
emilmont 27:7110ebee3484 99 #define __REV __rev
emilmont 27:7110ebee3484 100
emilmont 27:7110ebee3484 101
emilmont 27:7110ebee3484 102 /** \brief Reverse byte order (16 bit)
emilmont 27:7110ebee3484 103
emilmont 27:7110ebee3484 104 This function reverses the byte order in two unsigned short values.
emilmont 27:7110ebee3484 105
emilmont 27:7110ebee3484 106 \param [in] value Value to reverse
emilmont 27:7110ebee3484 107 \return Reversed value
emilmont 27:7110ebee3484 108 */
emilmont 27:7110ebee3484 109 #if (__ARMCC_VERSION < 400677)
emilmont 27:7110ebee3484 110 extern uint32_t __REV16(uint32_t value);
emilmont 27:7110ebee3484 111 #else /* (__ARMCC_VERSION >= 400677) */
emilmont 27:7110ebee3484 112 static __INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 27:7110ebee3484 113 {
emilmont 27:7110ebee3484 114 rev16 r0, r0
emilmont 27:7110ebee3484 115 bx lr
emilmont 27:7110ebee3484 116 }
emilmont 27:7110ebee3484 117 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 118
emilmont 27:7110ebee3484 119
emilmont 27:7110ebee3484 120 /** \brief Reverse byte order in signed short value
emilmont 27:7110ebee3484 121
emilmont 27:7110ebee3484 122 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 27:7110ebee3484 123
emilmont 27:7110ebee3484 124 \param [in] value Value to reverse
emilmont 27:7110ebee3484 125 \return Reversed value
emilmont 27:7110ebee3484 126 */
emilmont 27:7110ebee3484 127 #if (__ARMCC_VERSION < 400677)
emilmont 27:7110ebee3484 128 extern int32_t __REVSH(int32_t value);
emilmont 27:7110ebee3484 129 #else /* (__ARMCC_VERSION >= 400677) */
emilmont 27:7110ebee3484 130 static __INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 27:7110ebee3484 131 {
emilmont 27:7110ebee3484 132 revsh r0, r0
emilmont 27:7110ebee3484 133 bx lr
emilmont 27:7110ebee3484 134 }
emilmont 27:7110ebee3484 135 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 136
emilmont 27:7110ebee3484 137
emilmont 27:7110ebee3484 138 #if (__CORTEX_M >= 0x03)
emilmont 27:7110ebee3484 139
emilmont 27:7110ebee3484 140 /** \brief Reverse bit order of value
emilmont 27:7110ebee3484 141
emilmont 27:7110ebee3484 142 This function reverses the bit order of the given value.
emilmont 27:7110ebee3484 143
emilmont 27:7110ebee3484 144 \param [in] value Value to reverse
emilmont 27:7110ebee3484 145 \return Reversed value
emilmont 27:7110ebee3484 146 */
emilmont 27:7110ebee3484 147 #define __RBIT __rbit
emilmont 27:7110ebee3484 148
emilmont 27:7110ebee3484 149
emilmont 27:7110ebee3484 150 /** \brief LDR Exclusive (8 bit)
emilmont 27:7110ebee3484 151
emilmont 27:7110ebee3484 152 This function performs a exclusive LDR command for 8 bit value.
emilmont 27:7110ebee3484 153
emilmont 27:7110ebee3484 154 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 155 \return value of type uint8_t at (*ptr)
emilmont 27:7110ebee3484 156 */
emilmont 27:7110ebee3484 157 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 27:7110ebee3484 158
emilmont 27:7110ebee3484 159
emilmont 27:7110ebee3484 160 /** \brief LDR Exclusive (16 bit)
emilmont 27:7110ebee3484 161
emilmont 27:7110ebee3484 162 This function performs a exclusive LDR command for 16 bit values.
emilmont 27:7110ebee3484 163
emilmont 27:7110ebee3484 164 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 165 \return value of type uint16_t at (*ptr)
emilmont 27:7110ebee3484 166 */
emilmont 27:7110ebee3484 167 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 27:7110ebee3484 168
emilmont 27:7110ebee3484 169
emilmont 27:7110ebee3484 170 /** \brief LDR Exclusive (32 bit)
emilmont 27:7110ebee3484 171
emilmont 27:7110ebee3484 172 This function performs a exclusive LDR command for 32 bit values.
emilmont 27:7110ebee3484 173
emilmont 27:7110ebee3484 174 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 175 \return value of type uint32_t at (*ptr)
emilmont 27:7110ebee3484 176 */
emilmont 27:7110ebee3484 177 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 27:7110ebee3484 178
emilmont 27:7110ebee3484 179
emilmont 27:7110ebee3484 180 /** \brief STR Exclusive (8 bit)
emilmont 27:7110ebee3484 181
emilmont 27:7110ebee3484 182 This function performs a exclusive STR command for 8 bit values.
emilmont 27:7110ebee3484 183
emilmont 27:7110ebee3484 184 \param [in] value Value to store
emilmont 27:7110ebee3484 185 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 186 \return 0 Function succeeded
emilmont 27:7110ebee3484 187 \return 1 Function failed
emilmont 27:7110ebee3484 188 */
emilmont 27:7110ebee3484 189 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 27:7110ebee3484 190
emilmont 27:7110ebee3484 191
emilmont 27:7110ebee3484 192 /** \brief STR Exclusive (16 bit)
emilmont 27:7110ebee3484 193
emilmont 27:7110ebee3484 194 This function performs a exclusive STR command for 16 bit values.
emilmont 27:7110ebee3484 195
emilmont 27:7110ebee3484 196 \param [in] value Value to store
emilmont 27:7110ebee3484 197 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 198 \return 0 Function succeeded
emilmont 27:7110ebee3484 199 \return 1 Function failed
emilmont 27:7110ebee3484 200 */
emilmont 27:7110ebee3484 201 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 27:7110ebee3484 202
emilmont 27:7110ebee3484 203
emilmont 27:7110ebee3484 204 /** \brief STR Exclusive (32 bit)
emilmont 27:7110ebee3484 205
emilmont 27:7110ebee3484 206 This function performs a exclusive STR command for 32 bit values.
emilmont 27:7110ebee3484 207
emilmont 27:7110ebee3484 208 \param [in] value Value to store
emilmont 27:7110ebee3484 209 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 210 \return 0 Function succeeded
emilmont 27:7110ebee3484 211 \return 1 Function failed
emilmont 27:7110ebee3484 212 */
emilmont 27:7110ebee3484 213 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 27:7110ebee3484 214
emilmont 27:7110ebee3484 215
emilmont 27:7110ebee3484 216 /** \brief Remove the exclusive lock
emilmont 27:7110ebee3484 217
emilmont 27:7110ebee3484 218 This function removes the exclusive lock which is created by LDREX.
emilmont 27:7110ebee3484 219
emilmont 27:7110ebee3484 220 */
emilmont 27:7110ebee3484 221 #if (__ARMCC_VERSION < 400000)
emilmont 27:7110ebee3484 222 extern void __CLREX(void);
emilmont 27:7110ebee3484 223 #else /* (__ARMCC_VERSION >= 400000) */
emilmont 27:7110ebee3484 224 #define __CLREX __clrex
emilmont 27:7110ebee3484 225 #endif /* __ARMCC_VERSION */
emilmont 27:7110ebee3484 226
emilmont 27:7110ebee3484 227
emilmont 27:7110ebee3484 228 /** \brief Signed Saturate
emilmont 27:7110ebee3484 229
emilmont 27:7110ebee3484 230 This function saturates a signed value.
emilmont 27:7110ebee3484 231
emilmont 27:7110ebee3484 232 \param [in] value Value to be saturated
emilmont 27:7110ebee3484 233 \param [in] sat Bit position to saturate to (1..32)
emilmont 27:7110ebee3484 234 \return Saturated value
emilmont 27:7110ebee3484 235 */
emilmont 27:7110ebee3484 236 #define __SSAT __ssat
emilmont 27:7110ebee3484 237
emilmont 27:7110ebee3484 238
emilmont 27:7110ebee3484 239 /** \brief Unsigned Saturate
emilmont 27:7110ebee3484 240
emilmont 27:7110ebee3484 241 This function saturates an unsigned value.
emilmont 27:7110ebee3484 242
emilmont 27:7110ebee3484 243 \param [in] value Value to be saturated
emilmont 27:7110ebee3484 244 \param [in] sat Bit position to saturate to (0..31)
emilmont 27:7110ebee3484 245 \return Saturated value
emilmont 27:7110ebee3484 246 */
emilmont 27:7110ebee3484 247 #define __USAT __usat
emilmont 27:7110ebee3484 248
emilmont 27:7110ebee3484 249
emilmont 27:7110ebee3484 250 /** \brief Count leading zeros
emilmont 27:7110ebee3484 251
emilmont 27:7110ebee3484 252 This function counts the number of leading zeros of a data value.
emilmont 27:7110ebee3484 253
emilmont 27:7110ebee3484 254 \param [in] value Value to count the leading zeros
emilmont 27:7110ebee3484 255 \return number of leading zeros in value
emilmont 27:7110ebee3484 256 */
emilmont 27:7110ebee3484 257 #define __CLZ __clz
emilmont 27:7110ebee3484 258
emilmont 27:7110ebee3484 259 #endif /* (__CORTEX_M >= 0x03) */
emilmont 27:7110ebee3484 260
emilmont 27:7110ebee3484 261
emilmont 27:7110ebee3484 262
emilmont 27:7110ebee3484 263 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
emilmont 27:7110ebee3484 264 /* IAR iccarm specific functions */
emilmont 27:7110ebee3484 265
emilmont 27:7110ebee3484 266 #include <intrinsics.h> /* IAR Intrinsics */
emilmont 27:7110ebee3484 267
emilmont 27:7110ebee3484 268 #pragma diag_suppress=Pe940
emilmont 27:7110ebee3484 269
emilmont 27:7110ebee3484 270 /** \brief No Operation
emilmont 27:7110ebee3484 271
emilmont 27:7110ebee3484 272 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 27:7110ebee3484 273 */
emilmont 27:7110ebee3484 274 #define __NOP __no_operation
emilmont 27:7110ebee3484 275
emilmont 27:7110ebee3484 276
emilmont 27:7110ebee3484 277 /** \brief Wait For Interrupt
emilmont 27:7110ebee3484 278
emilmont 27:7110ebee3484 279 Wait For Interrupt is a hint instruction that suspends execution
emilmont 27:7110ebee3484 280 until one of a number of events occurs.
emilmont 27:7110ebee3484 281 */
emilmont 27:7110ebee3484 282 static __INLINE void __WFI(void)
emilmont 27:7110ebee3484 283 {
emilmont 27:7110ebee3484 284 __ASM ("wfi");
emilmont 27:7110ebee3484 285 }
emilmont 27:7110ebee3484 286
emilmont 27:7110ebee3484 287
emilmont 27:7110ebee3484 288 /** \brief Wait For Event
emilmont 27:7110ebee3484 289
emilmont 27:7110ebee3484 290 Wait For Event is a hint instruction that permits the processor to enter
emilmont 27:7110ebee3484 291 a low-power state until one of a number of events occurs.
emilmont 27:7110ebee3484 292 */
emilmont 27:7110ebee3484 293 static __INLINE void __WFE(void)
emilmont 27:7110ebee3484 294 {
emilmont 27:7110ebee3484 295 __ASM ("wfe");
emilmont 27:7110ebee3484 296 }
emilmont 27:7110ebee3484 297
emilmont 27:7110ebee3484 298
emilmont 27:7110ebee3484 299 /** \brief Send Event
emilmont 27:7110ebee3484 300
emilmont 27:7110ebee3484 301 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 27:7110ebee3484 302 */
emilmont 27:7110ebee3484 303 static __INLINE void __SEV(void)
emilmont 27:7110ebee3484 304 {
emilmont 27:7110ebee3484 305 __ASM ("sev");
emilmont 27:7110ebee3484 306 }
emilmont 27:7110ebee3484 307
emilmont 27:7110ebee3484 308
emilmont 27:7110ebee3484 309 /* intrinsic void __ISB(void) (see intrinsics.h) */
emilmont 27:7110ebee3484 310 /* intrinsic void __DSB(void) (see intrinsics.h) */
emilmont 27:7110ebee3484 311 /* intrinsic void __DMB(void) (see intrinsics.h) */
emilmont 27:7110ebee3484 312 /* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
emilmont 27:7110ebee3484 313 /* intrinsic __SSAT (see intrinsics.h) */
emilmont 27:7110ebee3484 314 /* intrinsic __USAT (see intrinsics.h) */
emilmont 27:7110ebee3484 315
emilmont 27:7110ebee3484 316
emilmont 27:7110ebee3484 317 /** \brief Reverse byte order (16 bit)
emilmont 27:7110ebee3484 318
emilmont 27:7110ebee3484 319 This function reverses the byte order in two unsigned short values.
emilmont 27:7110ebee3484 320
emilmont 27:7110ebee3484 321 \param [in] value Value to reverse
emilmont 27:7110ebee3484 322 \return Reversed value
emilmont 27:7110ebee3484 323 */
emilmont 27:7110ebee3484 324 static uint32_t __REV16(uint32_t value)
emilmont 27:7110ebee3484 325 {
emilmont 27:7110ebee3484 326 __ASM("rev16 r0, r0");
emilmont 27:7110ebee3484 327 }
emilmont 27:7110ebee3484 328
emilmont 27:7110ebee3484 329
emilmont 27:7110ebee3484 330 /* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
emilmont 27:7110ebee3484 331
emilmont 27:7110ebee3484 332
emilmont 27:7110ebee3484 333 #if (__CORTEX_M >= 0x03)
emilmont 27:7110ebee3484 334
emilmont 27:7110ebee3484 335 /** \brief Reverse bit order of value
emilmont 27:7110ebee3484 336
emilmont 27:7110ebee3484 337 This function reverses the bit order of the given value.
emilmont 27:7110ebee3484 338
emilmont 27:7110ebee3484 339 \param [in] value Value to reverse
emilmont 27:7110ebee3484 340 \return Reversed value
emilmont 27:7110ebee3484 341 */
emilmont 27:7110ebee3484 342 static uint32_t __RBIT(uint32_t value)
emilmont 27:7110ebee3484 343 {
emilmont 27:7110ebee3484 344 __ASM("rbit r0, r0");
emilmont 27:7110ebee3484 345 }
emilmont 27:7110ebee3484 346
emilmont 27:7110ebee3484 347
emilmont 27:7110ebee3484 348 /** \brief LDR Exclusive (8 bit)
emilmont 27:7110ebee3484 349
emilmont 27:7110ebee3484 350 This function performs a exclusive LDR command for 8 bit value.
emilmont 27:7110ebee3484 351
emilmont 27:7110ebee3484 352 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 353 \return value of type uint8_t at (*ptr)
emilmont 27:7110ebee3484 354 */
emilmont 27:7110ebee3484 355 static uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 27:7110ebee3484 356 {
emilmont 27:7110ebee3484 357 __ASM("ldrexb r0, [r0]");
emilmont 27:7110ebee3484 358 }
emilmont 27:7110ebee3484 359
emilmont 27:7110ebee3484 360
emilmont 27:7110ebee3484 361 /** \brief LDR Exclusive (16 bit)
emilmont 27:7110ebee3484 362
emilmont 27:7110ebee3484 363 This function performs a exclusive LDR command for 16 bit values.
emilmont 27:7110ebee3484 364
emilmont 27:7110ebee3484 365 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 366 \return value of type uint16_t at (*ptr)
emilmont 27:7110ebee3484 367 */
emilmont 27:7110ebee3484 368 static uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 27:7110ebee3484 369 {
emilmont 27:7110ebee3484 370 __ASM("ldrexh r0, [r0]");
emilmont 27:7110ebee3484 371 }
emilmont 27:7110ebee3484 372
emilmont 27:7110ebee3484 373
emilmont 27:7110ebee3484 374 /** \brief LDR Exclusive (32 bit)
emilmont 27:7110ebee3484 375
emilmont 27:7110ebee3484 376 This function performs a exclusive LDR command for 32 bit values.
emilmont 27:7110ebee3484 377
emilmont 27:7110ebee3484 378 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 379 \return value of type uint32_t at (*ptr)
emilmont 27:7110ebee3484 380 */
emilmont 27:7110ebee3484 381 /* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
emilmont 27:7110ebee3484 382 static uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 27:7110ebee3484 383 {
emilmont 27:7110ebee3484 384 __ASM("ldrex r0, [r0]");
emilmont 27:7110ebee3484 385 }
emilmont 27:7110ebee3484 386
emilmont 27:7110ebee3484 387
emilmont 27:7110ebee3484 388 /** \brief STR Exclusive (8 bit)
emilmont 27:7110ebee3484 389
emilmont 27:7110ebee3484 390 This function performs a exclusive STR command for 8 bit values.
emilmont 27:7110ebee3484 391
emilmont 27:7110ebee3484 392 \param [in] value Value to store
emilmont 27:7110ebee3484 393 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 394 \return 0 Function succeeded
emilmont 27:7110ebee3484 395 \return 1 Function failed
emilmont 27:7110ebee3484 396 */
emilmont 27:7110ebee3484 397 static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 27:7110ebee3484 398 {
emilmont 27:7110ebee3484 399 __ASM("strexb r0, r0, [r1]");
emilmont 27:7110ebee3484 400 }
emilmont 27:7110ebee3484 401
emilmont 27:7110ebee3484 402
emilmont 27:7110ebee3484 403 /** \brief STR Exclusive (16 bit)
emilmont 27:7110ebee3484 404
emilmont 27:7110ebee3484 405 This function performs a exclusive STR command for 16 bit values.
emilmont 27:7110ebee3484 406
emilmont 27:7110ebee3484 407 \param [in] value Value to store
emilmont 27:7110ebee3484 408 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 409 \return 0 Function succeeded
emilmont 27:7110ebee3484 410 \return 1 Function failed
emilmont 27:7110ebee3484 411 */
emilmont 27:7110ebee3484 412 static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 27:7110ebee3484 413 {
emilmont 27:7110ebee3484 414 __ASM("strexh r0, r0, [r1]");
emilmont 27:7110ebee3484 415 }
emilmont 27:7110ebee3484 416
emilmont 27:7110ebee3484 417
emilmont 27:7110ebee3484 418 /** \brief STR Exclusive (32 bit)
emilmont 27:7110ebee3484 419
emilmont 27:7110ebee3484 420 This function performs a exclusive STR command for 32 bit values.
emilmont 27:7110ebee3484 421
emilmont 27:7110ebee3484 422 \param [in] value Value to store
emilmont 27:7110ebee3484 423 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 424 \return 0 Function succeeded
emilmont 27:7110ebee3484 425 \return 1 Function failed
emilmont 27:7110ebee3484 426 */
emilmont 27:7110ebee3484 427 /* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
emilmont 27:7110ebee3484 428 static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 27:7110ebee3484 429 {
emilmont 27:7110ebee3484 430 __ASM("strex r0, r0, [r1]");
emilmont 27:7110ebee3484 431 }
emilmont 27:7110ebee3484 432
emilmont 27:7110ebee3484 433
emilmont 27:7110ebee3484 434 /** \brief Remove the exclusive lock
emilmont 27:7110ebee3484 435
emilmont 27:7110ebee3484 436 This function removes the exclusive lock which is created by LDREX.
emilmont 27:7110ebee3484 437
emilmont 27:7110ebee3484 438 */
emilmont 27:7110ebee3484 439 static __INLINE void __CLREX(void)
emilmont 27:7110ebee3484 440 {
emilmont 27:7110ebee3484 441 __ASM ("clrex");
emilmont 27:7110ebee3484 442 }
emilmont 27:7110ebee3484 443
emilmont 27:7110ebee3484 444 /* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
emilmont 27:7110ebee3484 445
emilmont 27:7110ebee3484 446 #endif /* (__CORTEX_M >= 0x03) */
emilmont 27:7110ebee3484 447
emilmont 27:7110ebee3484 448 #pragma diag_default=Pe940
emilmont 27:7110ebee3484 449
emilmont 27:7110ebee3484 450
emilmont 27:7110ebee3484 451
emilmont 27:7110ebee3484 452 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
emilmont 27:7110ebee3484 453 /* GNU gcc specific functions */
emilmont 27:7110ebee3484 454
emilmont 27:7110ebee3484 455 /** \brief No Operation
emilmont 27:7110ebee3484 456
emilmont 27:7110ebee3484 457 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 27:7110ebee3484 458 */
emilmont 27:7110ebee3484 459 __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
emilmont 27:7110ebee3484 460 {
emilmont 27:7110ebee3484 461 __ASM volatile ("nop");
emilmont 27:7110ebee3484 462 }
emilmont 27:7110ebee3484 463
emilmont 27:7110ebee3484 464
emilmont 27:7110ebee3484 465 /** \brief Wait For Interrupt
emilmont 27:7110ebee3484 466
emilmont 27:7110ebee3484 467 Wait For Interrupt is a hint instruction that suspends execution
emilmont 27:7110ebee3484 468 until one of a number of events occurs.
emilmont 27:7110ebee3484 469 */
emilmont 27:7110ebee3484 470 __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
emilmont 27:7110ebee3484 471 {
emilmont 27:7110ebee3484 472 __ASM volatile ("wfi");
emilmont 27:7110ebee3484 473 }
emilmont 27:7110ebee3484 474
emilmont 27:7110ebee3484 475
emilmont 27:7110ebee3484 476 /** \brief Wait For Event
emilmont 27:7110ebee3484 477
emilmont 27:7110ebee3484 478 Wait For Event is a hint instruction that permits the processor to enter
emilmont 27:7110ebee3484 479 a low-power state until one of a number of events occurs.
emilmont 27:7110ebee3484 480 */
emilmont 27:7110ebee3484 481 __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
emilmont 27:7110ebee3484 482 {
emilmont 27:7110ebee3484 483 __ASM volatile ("wfe");
emilmont 27:7110ebee3484 484 }
emilmont 27:7110ebee3484 485
emilmont 27:7110ebee3484 486
emilmont 27:7110ebee3484 487 /** \brief Send Event
emilmont 27:7110ebee3484 488
emilmont 27:7110ebee3484 489 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 27:7110ebee3484 490 */
emilmont 27:7110ebee3484 491 __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
emilmont 27:7110ebee3484 492 {
emilmont 27:7110ebee3484 493 __ASM volatile ("sev");
emilmont 27:7110ebee3484 494 }
emilmont 27:7110ebee3484 495
emilmont 27:7110ebee3484 496
emilmont 27:7110ebee3484 497 /** \brief Instruction Synchronization Barrier
emilmont 27:7110ebee3484 498
emilmont 27:7110ebee3484 499 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 27:7110ebee3484 500 so that all instructions following the ISB are fetched from cache or
emilmont 27:7110ebee3484 501 memory, after the instruction has been completed.
emilmont 27:7110ebee3484 502 */
emilmont 27:7110ebee3484 503 __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
emilmont 27:7110ebee3484 504 {
emilmont 27:7110ebee3484 505 __ASM volatile ("isb");
emilmont 27:7110ebee3484 506 }
emilmont 27:7110ebee3484 507
emilmont 27:7110ebee3484 508
emilmont 27:7110ebee3484 509 /** \brief Data Synchronization Barrier
emilmont 27:7110ebee3484 510
emilmont 27:7110ebee3484 511 This function acts as a special kind of Data Memory Barrier.
emilmont 27:7110ebee3484 512 It completes when all explicit memory accesses before this instruction complete.
emilmont 27:7110ebee3484 513 */
emilmont 27:7110ebee3484 514 __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
emilmont 27:7110ebee3484 515 {
emilmont 27:7110ebee3484 516 __ASM volatile ("dsb");
emilmont 27:7110ebee3484 517 }
emilmont 27:7110ebee3484 518
emilmont 27:7110ebee3484 519
emilmont 27:7110ebee3484 520 /** \brief Data Memory Barrier
emilmont 27:7110ebee3484 521
emilmont 27:7110ebee3484 522 This function ensures the apparent order of the explicit memory operations before
emilmont 27:7110ebee3484 523 and after the instruction, without ensuring their completion.
emilmont 27:7110ebee3484 524 */
emilmont 27:7110ebee3484 525 __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
emilmont 27:7110ebee3484 526 {
emilmont 27:7110ebee3484 527 __ASM volatile ("dmb");
emilmont 27:7110ebee3484 528 }
emilmont 27:7110ebee3484 529
emilmont 27:7110ebee3484 530
emilmont 27:7110ebee3484 531 /** \brief Reverse byte order (32 bit)
emilmont 27:7110ebee3484 532
emilmont 27:7110ebee3484 533 This function reverses the byte order in integer value.
emilmont 27:7110ebee3484 534
emilmont 27:7110ebee3484 535 \param [in] value Value to reverse
emilmont 27:7110ebee3484 536 \return Reversed value
emilmont 27:7110ebee3484 537 */
emilmont 27:7110ebee3484 538 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
emilmont 27:7110ebee3484 539 {
emilmont 27:7110ebee3484 540 uint32_t result;
emilmont 27:7110ebee3484 541
emilmont 27:7110ebee3484 542 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
emilmont 27:7110ebee3484 543 return(result);
emilmont 27:7110ebee3484 544 }
emilmont 27:7110ebee3484 545
emilmont 27:7110ebee3484 546
emilmont 27:7110ebee3484 547 /** \brief Reverse byte order (16 bit)
emilmont 27:7110ebee3484 548
emilmont 27:7110ebee3484 549 This function reverses the byte order in two unsigned short values.
emilmont 27:7110ebee3484 550
emilmont 27:7110ebee3484 551 \param [in] value Value to reverse
emilmont 27:7110ebee3484 552 \return Reversed value
emilmont 27:7110ebee3484 553 */
emilmont 27:7110ebee3484 554 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
emilmont 27:7110ebee3484 555 {
emilmont 27:7110ebee3484 556 uint32_t result;
emilmont 27:7110ebee3484 557
emilmont 27:7110ebee3484 558 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
emilmont 27:7110ebee3484 559 return(result);
emilmont 27:7110ebee3484 560 }
emilmont 27:7110ebee3484 561
emilmont 27:7110ebee3484 562
emilmont 27:7110ebee3484 563 /** \brief Reverse byte order in signed short value
emilmont 27:7110ebee3484 564
emilmont 27:7110ebee3484 565 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 27:7110ebee3484 566
emilmont 27:7110ebee3484 567 \param [in] value Value to reverse
emilmont 27:7110ebee3484 568 \return Reversed value
emilmont 27:7110ebee3484 569 */
emilmont 27:7110ebee3484 570 __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
emilmont 27:7110ebee3484 571 {
emilmont 27:7110ebee3484 572 uint32_t result;
emilmont 27:7110ebee3484 573
emilmont 27:7110ebee3484 574 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
emilmont 27:7110ebee3484 575 return(result);
emilmont 27:7110ebee3484 576 }
emilmont 27:7110ebee3484 577
emilmont 27:7110ebee3484 578
emilmont 27:7110ebee3484 579 #if (__CORTEX_M >= 0x03)
emilmont 27:7110ebee3484 580
emilmont 27:7110ebee3484 581 /** \brief Reverse bit order of value
emilmont 27:7110ebee3484 582
emilmont 27:7110ebee3484 583 This function reverses the bit order of the given value.
emilmont 27:7110ebee3484 584
emilmont 27:7110ebee3484 585 \param [in] value Value to reverse
emilmont 27:7110ebee3484 586 \return Reversed value
emilmont 27:7110ebee3484 587 */
emilmont 27:7110ebee3484 588 __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
emilmont 27:7110ebee3484 589 {
emilmont 27:7110ebee3484 590 uint32_t result;
emilmont 27:7110ebee3484 591
emilmont 27:7110ebee3484 592 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
emilmont 27:7110ebee3484 593 return(result);
emilmont 27:7110ebee3484 594 }
emilmont 27:7110ebee3484 595
emilmont 27:7110ebee3484 596
emilmont 27:7110ebee3484 597 /** \brief LDR Exclusive (8 bit)
emilmont 27:7110ebee3484 598
emilmont 27:7110ebee3484 599 This function performs a exclusive LDR command for 8 bit value.
emilmont 27:7110ebee3484 600
emilmont 27:7110ebee3484 601 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 602 \return value of type uint8_t at (*ptr)
emilmont 27:7110ebee3484 603 */
emilmont 27:7110ebee3484 604 __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 27:7110ebee3484 605 {
emilmont 27:7110ebee3484 606 uint8_t result;
emilmont 27:7110ebee3484 607
emilmont 27:7110ebee3484 608 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 27:7110ebee3484 609 return(result);
emilmont 27:7110ebee3484 610 }
emilmont 27:7110ebee3484 611
emilmont 27:7110ebee3484 612
emilmont 27:7110ebee3484 613 /** \brief LDR Exclusive (16 bit)
emilmont 27:7110ebee3484 614
emilmont 27:7110ebee3484 615 This function performs a exclusive LDR command for 16 bit values.
emilmont 27:7110ebee3484 616
emilmont 27:7110ebee3484 617 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 618 \return value of type uint16_t at (*ptr)
emilmont 27:7110ebee3484 619 */
emilmont 27:7110ebee3484 620 __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 27:7110ebee3484 621 {
emilmont 27:7110ebee3484 622 uint16_t result;
emilmont 27:7110ebee3484 623
emilmont 27:7110ebee3484 624 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 27:7110ebee3484 625 return(result);
emilmont 27:7110ebee3484 626 }
emilmont 27:7110ebee3484 627
emilmont 27:7110ebee3484 628
emilmont 27:7110ebee3484 629 /** \brief LDR Exclusive (32 bit)
emilmont 27:7110ebee3484 630
emilmont 27:7110ebee3484 631 This function performs a exclusive LDR command for 32 bit values.
emilmont 27:7110ebee3484 632
emilmont 27:7110ebee3484 633 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 634 \return value of type uint32_t at (*ptr)
emilmont 27:7110ebee3484 635 */
emilmont 27:7110ebee3484 636 __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 27:7110ebee3484 637 {
emilmont 27:7110ebee3484 638 uint32_t result;
emilmont 27:7110ebee3484 639
emilmont 27:7110ebee3484 640 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 27:7110ebee3484 641 return(result);
emilmont 27:7110ebee3484 642 }
emilmont 27:7110ebee3484 643
emilmont 27:7110ebee3484 644
emilmont 27:7110ebee3484 645 /** \brief STR Exclusive (8 bit)
emilmont 27:7110ebee3484 646
emilmont 27:7110ebee3484 647 This function performs a exclusive STR command for 8 bit values.
emilmont 27:7110ebee3484 648
emilmont 27:7110ebee3484 649 \param [in] value Value to store
emilmont 27:7110ebee3484 650 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 651 \return 0 Function succeeded
emilmont 27:7110ebee3484 652 \return 1 Function failed
emilmont 27:7110ebee3484 653 */
emilmont 27:7110ebee3484 654 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 27:7110ebee3484 655 {
emilmont 27:7110ebee3484 656 uint32_t result;
emilmont 27:7110ebee3484 657
emilmont 27:7110ebee3484 658 __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
emilmont 27:7110ebee3484 659 return(result);
emilmont 27:7110ebee3484 660 }
emilmont 27:7110ebee3484 661
emilmont 27:7110ebee3484 662
emilmont 27:7110ebee3484 663 /** \brief STR Exclusive (16 bit)
emilmont 27:7110ebee3484 664
emilmont 27:7110ebee3484 665 This function performs a exclusive STR command for 16 bit values.
emilmont 27:7110ebee3484 666
emilmont 27:7110ebee3484 667 \param [in] value Value to store
emilmont 27:7110ebee3484 668 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 669 \return 0 Function succeeded
emilmont 27:7110ebee3484 670 \return 1 Function failed
emilmont 27:7110ebee3484 671 */
emilmont 27:7110ebee3484 672 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 27:7110ebee3484 673 {
emilmont 27:7110ebee3484 674 uint32_t result;
emilmont 27:7110ebee3484 675
emilmont 27:7110ebee3484 676 __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
emilmont 27:7110ebee3484 677 return(result);
emilmont 27:7110ebee3484 678 }
emilmont 27:7110ebee3484 679
emilmont 27:7110ebee3484 680
emilmont 27:7110ebee3484 681 /** \brief STR Exclusive (32 bit)
emilmont 27:7110ebee3484 682
emilmont 27:7110ebee3484 683 This function performs a exclusive STR command for 32 bit values.
emilmont 27:7110ebee3484 684
emilmont 27:7110ebee3484 685 \param [in] value Value to store
emilmont 27:7110ebee3484 686 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 687 \return 0 Function succeeded
emilmont 27:7110ebee3484 688 \return 1 Function failed
emilmont 27:7110ebee3484 689 */
emilmont 27:7110ebee3484 690 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 27:7110ebee3484 691 {
emilmont 27:7110ebee3484 692 uint32_t result;
emilmont 27:7110ebee3484 693
emilmont 27:7110ebee3484 694 __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
emilmont 27:7110ebee3484 695 return(result);
emilmont 27:7110ebee3484 696 }
emilmont 27:7110ebee3484 697
emilmont 27:7110ebee3484 698
emilmont 27:7110ebee3484 699 /** \brief Remove the exclusive lock
emilmont 27:7110ebee3484 700
emilmont 27:7110ebee3484 701 This function removes the exclusive lock which is created by LDREX.
emilmont 27:7110ebee3484 702
emilmont 27:7110ebee3484 703 */
emilmont 27:7110ebee3484 704 __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
emilmont 27:7110ebee3484 705 {
emilmont 27:7110ebee3484 706 __ASM volatile ("clrex");
emilmont 27:7110ebee3484 707 }
emilmont 27:7110ebee3484 708
emilmont 27:7110ebee3484 709
emilmont 27:7110ebee3484 710 /** \brief Signed Saturate
emilmont 27:7110ebee3484 711
emilmont 27:7110ebee3484 712 This function saturates a signed value.
emilmont 27:7110ebee3484 713
emilmont 27:7110ebee3484 714 \param [in] value Value to be saturated
emilmont 27:7110ebee3484 715 \param [in] sat Bit position to saturate to (1..32)
emilmont 27:7110ebee3484 716 \return Saturated value
emilmont 27:7110ebee3484 717 */
emilmont 27:7110ebee3484 718 #define __SSAT(ARG1,ARG2) \
emilmont 27:7110ebee3484 719 ({ \
emilmont 27:7110ebee3484 720 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 27:7110ebee3484 721 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 27:7110ebee3484 722 __RES; \
emilmont 27:7110ebee3484 723 })
emilmont 27:7110ebee3484 724
emilmont 27:7110ebee3484 725
emilmont 27:7110ebee3484 726 /** \brief Unsigned Saturate
emilmont 27:7110ebee3484 727
emilmont 27:7110ebee3484 728 This function saturates an unsigned value.
emilmont 27:7110ebee3484 729
emilmont 27:7110ebee3484 730 \param [in] value Value to be saturated
emilmont 27:7110ebee3484 731 \param [in] sat Bit position to saturate to (0..31)
emilmont 27:7110ebee3484 732 \return Saturated value
emilmont 27:7110ebee3484 733 */
emilmont 27:7110ebee3484 734 #define __USAT(ARG1,ARG2) \
emilmont 27:7110ebee3484 735 ({ \
emilmont 27:7110ebee3484 736 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 27:7110ebee3484 737 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 27:7110ebee3484 738 __RES; \
emilmont 27:7110ebee3484 739 })
emilmont 27:7110ebee3484 740
emilmont 27:7110ebee3484 741
emilmont 27:7110ebee3484 742 /** \brief Count leading zeros
emilmont 27:7110ebee3484 743
emilmont 27:7110ebee3484 744 This function counts the number of leading zeros of a data value.
emilmont 27:7110ebee3484 745
emilmont 27:7110ebee3484 746 \param [in] value Value to count the leading zeros
emilmont 27:7110ebee3484 747 \return number of leading zeros in value
emilmont 27:7110ebee3484 748 */
emilmont 27:7110ebee3484 749 __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
emilmont 27:7110ebee3484 750 {
emilmont 27:7110ebee3484 751 uint8_t result;
emilmont 27:7110ebee3484 752
emilmont 27:7110ebee3484 753 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
emilmont 27:7110ebee3484 754 return(result);
emilmont 27:7110ebee3484 755 }
emilmont 27:7110ebee3484 756
emilmont 27:7110ebee3484 757 #endif /* (__CORTEX_M >= 0x03) */
emilmont 27:7110ebee3484 758
emilmont 27:7110ebee3484 759
emilmont 27:7110ebee3484 760
emilmont 27:7110ebee3484 761
emilmont 27:7110ebee3484 762 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
emilmont 27:7110ebee3484 763 /* TASKING carm specific functions */
emilmont 27:7110ebee3484 764
emilmont 27:7110ebee3484 765 /*
emilmont 27:7110ebee3484 766 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 27:7110ebee3484 767 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 27:7110ebee3484 768 * Including the CMSIS ones.
emilmont 27:7110ebee3484 769 */
emilmont 27:7110ebee3484 770
emilmont 27:7110ebee3484 771 #endif
emilmont 27:7110ebee3484 772
emilmont 27:7110ebee3484 773 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 27:7110ebee3484 774
emilmont 27:7110ebee3484 775 #endif /* __CORE_CMINSTR_H__ */