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LPC1768/GCC_CR/core_cm3.h@27:7110ebee3484, 2011-11-29 (annotated)

Committer:: emilmont
Date:: Tue Nov 29 14:59:27 2011 +0000
Revision:: 27:7110ebee3484
Child:: 33:5364839841bd

New Libraries 11.11

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	27:7110ebee3484	1	/************************************************************************//
emilmont	27:7110ebee3484	2	* @file core_cm3.h
emilmont	27:7110ebee3484	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
emilmont	27:7110ebee3484	4	* @version V2.01
emilmont	27:7110ebee3484	5	* @date 06. December 2010
emilmont	27:7110ebee3484	6	*
emilmont	27:7110ebee3484	7	* @note
emilmont	27:7110ebee3484	8	* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
emilmont	27:7110ebee3484	9	*
emilmont	27:7110ebee3484	10	* @par
emilmont	27:7110ebee3484	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont	27:7110ebee3484	12	* processor based microcontrollers. This file can be freely distributed
emilmont	27:7110ebee3484	13	* within development tools that are supporting such ARM based processors.
emilmont	27:7110ebee3484	14	*
emilmont	27:7110ebee3484	15	* @par
emilmont	27:7110ebee3484	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont	27:7110ebee3484	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont	27:7110ebee3484	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont	27:7110ebee3484	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont	27:7110ebee3484	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont	27:7110ebee3484	21	*
emilmont	27:7110ebee3484	22	******************************************************************************/
emilmont	27:7110ebee3484	23	#if defined ( __ICCARM__ )
emilmont	27:7110ebee3484	24	#pragma system_include /* treat file as system include file for MISRA check */
emilmont	27:7110ebee3484	25	#endif
emilmont	27:7110ebee3484	26
emilmont	27:7110ebee3484	27	#ifdef __cplusplus
emilmont	27:7110ebee3484	28	extern "C" {
emilmont	27:7110ebee3484	29	#endif
emilmont	27:7110ebee3484	30
emilmont	27:7110ebee3484	31	#ifndef __CORE_CM3_H_GENERIC
emilmont	27:7110ebee3484	32	#define __CORE_CM3_H_GENERIC
emilmont	27:7110ebee3484	33
emilmont	27:7110ebee3484	34
emilmont	27:7110ebee3484	35	/** \mainpage CMSIS Cortex-M3
emilmont	27:7110ebee3484	36
emilmont	27:7110ebee3484	37	This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
emilmont	27:7110ebee3484	38	It consists of:
emilmont	27:7110ebee3484	39
emilmont	27:7110ebee3484	40	- Cortex-M Core Register Definitions
emilmont	27:7110ebee3484	41	- Cortex-M functions
emilmont	27:7110ebee3484	42	- Cortex-M instructions
emilmont	27:7110ebee3484	43
emilmont	27:7110ebee3484	44	The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
emilmont	27:7110ebee3484	45	access to the Cortex-M Core
emilmont	27:7110ebee3484	46	*/
emilmont	27:7110ebee3484	47
emilmont	27:7110ebee3484	48	/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
emilmont	27:7110ebee3484	49	List of Lint messages which will be suppressed and not shown:
emilmont	27:7110ebee3484	50	- not yet checked
emilmont	27:7110ebee3484	51	.
emilmont	27:7110ebee3484	52	Note: To re-enable a Message, insert a space before 'lint' *
emilmont	27:7110ebee3484	53
emilmont	27:7110ebee3484	54	*/
emilmont	27:7110ebee3484	55
emilmont	27:7110ebee3484	56
emilmont	27:7110ebee3484	57	/*******************************************************************************
emilmont	27:7110ebee3484	58	* CMSIS definitions
emilmont	27:7110ebee3484	59	******************************************************************************/
emilmont	27:7110ebee3484	60	/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
emilmont	27:7110ebee3484	61	This file defines all structures and symbols for CMSIS core:
emilmont	27:7110ebee3484	62	- CMSIS version number
emilmont	27:7110ebee3484	63	- Cortex-M core
emilmont	27:7110ebee3484	64	- Cortex-M core Revision Number
emilmont	27:7110ebee3484	65	@{
emilmont	27:7110ebee3484	66	*/
emilmont	27:7110ebee3484	67
emilmont	27:7110ebee3484	68	/* CMSIS CM3 definitions */
emilmont	27:7110ebee3484	69	#define __CM3_CMSIS_VERSION_MAIN (0x02) /!< [31:16] CMSIS HAL main version /
emilmont	27:7110ebee3484	70	#define __CM3_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
emilmont	27:7110ebee3484	71	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| __CM3_CMSIS_VERSION_SUB) /!< CMSIS HAL version number /
emilmont	27:7110ebee3484	72
emilmont	27:7110ebee3484	73	#define __CORTEX_M (0x03) /!< Cortex core /
emilmont	27:7110ebee3484	74
emilmont	27:7110ebee3484	75
emilmont	27:7110ebee3484	76	#if defined ( __CC_ARM )
emilmont	27:7110ebee3484	77	#define __ASM __asm /!< asm keyword for ARM Compiler /
emilmont	27:7110ebee3484	78	#define __INLINE __inline /!< inline keyword for ARM Compiler /
emilmont	27:7110ebee3484	79
emilmont	27:7110ebee3484	80	#elif defined ( __ICCARM__ )
emilmont	27:7110ebee3484	81	#define __ASM __asm /!< asm keyword for IAR Compiler /
emilmont	27:7110ebee3484	82	#define __INLINE inline /!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! /
emilmont	27:7110ebee3484	83
emilmont	27:7110ebee3484	84	#elif defined ( __GNUC__ )
emilmont	27:7110ebee3484	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
emilmont	27:7110ebee3484	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
emilmont	27:7110ebee3484	87
emilmont	27:7110ebee3484	88	#elif defined ( __TASKING__ )
emilmont	27:7110ebee3484	89	#define __ASM __asm /!< asm keyword for TASKING Compiler /
emilmont	27:7110ebee3484	90	#define __INLINE inline /!< inline keyword for TASKING Compiler /
emilmont	27:7110ebee3484	91
emilmont	27:7110ebee3484	92	#endif
emilmont	27:7110ebee3484	93
emilmont	27:7110ebee3484	94	#include <stdint.h> /!< standard types definitions /
emilmont	27:7110ebee3484	95	#include "core_cmInstr.h" /!< Core Instruction Access /
emilmont	27:7110ebee3484	96	#include "core_cmFunc.h" /!< Core Function Access /
emilmont	27:7110ebee3484	97
emilmont	27:7110ebee3484	98	#endif /* __CORE_CM3_H_GENERIC */
emilmont	27:7110ebee3484	99
emilmont	27:7110ebee3484	100
emilmont	27:7110ebee3484	101	#ifndef __CMSIS_GENERIC
emilmont	27:7110ebee3484	102
emilmont	27:7110ebee3484	103	#ifndef __CORE_CM3_H_DEPENDANT
emilmont	27:7110ebee3484	104	#define __CORE_CM3_H_DEPENDANT
emilmont	27:7110ebee3484	105
emilmont	27:7110ebee3484	106	/* IO definitions (access restrictions to peripheral registers) */
emilmont	27:7110ebee3484	107	#ifdef __cplusplus
emilmont	27:7110ebee3484	108	#define __I volatile /!< defines 'read only' permissions /
emilmont	27:7110ebee3484	109	#else
emilmont	27:7110ebee3484	110	#define __I volatile const /!< defines 'read only' permissions /
emilmont	27:7110ebee3484	111	#endif
emilmont	27:7110ebee3484	112	#define __O volatile /!< defines 'write only' permissions /
emilmont	27:7110ebee3484	113	#define __IO volatile /!< defines 'read / write' permissions /
emilmont	27:7110ebee3484	114
emilmont	27:7110ebee3484	115	/@} end of group CMSIS_core_definitions /
emilmont	27:7110ebee3484	116
emilmont	27:7110ebee3484	117
emilmont	27:7110ebee3484	118
emilmont	27:7110ebee3484	119	/*******************************************************************************
emilmont	27:7110ebee3484	120	* Register Abstraction
emilmont	27:7110ebee3484	121	******************************************************************************/
emilmont	27:7110ebee3484	122	/** \defgroup CMSIS_core_register CMSIS Core Register
emilmont	27:7110ebee3484	123	Core Register contain:
emilmont	27:7110ebee3484	124	- Core Register
emilmont	27:7110ebee3484	125	- Core NVIC Register
emilmont	27:7110ebee3484	126	- Core SCB Register
emilmont	27:7110ebee3484	127	- Core SysTick Register
emilmont	27:7110ebee3484	128	- Core Debug Register
emilmont	27:7110ebee3484	129	- Core MPU Register
emilmont	27:7110ebee3484	130	*/
emilmont	27:7110ebee3484	131
emilmont	27:7110ebee3484	132	/** \ingroup CMSIS_core_register
emilmont	27:7110ebee3484	133	\defgroup CMSIS_CORE CMSIS Core
emilmont	27:7110ebee3484	134	Type definitions for the Cortex-M Core Registers
emilmont	27:7110ebee3484	135	@{
emilmont	27:7110ebee3484	136	*/
emilmont	27:7110ebee3484	137
emilmont	27:7110ebee3484	138	/** \brief Union type to access the Application Program Status Register (APSR).
emilmont	27:7110ebee3484	139	*/
emilmont	27:7110ebee3484	140	typedef union
emilmont	27:7110ebee3484	141	{
emilmont	27:7110ebee3484	142	struct
emilmont	27:7110ebee3484	143	{
emilmont	27:7110ebee3484	144	#if (__CORTEX_M != 0x04)
emilmont	27:7110ebee3484	145	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
emilmont	27:7110ebee3484	146	#else
emilmont	27:7110ebee3484	147	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
emilmont	27:7110ebee3484	148	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
emilmont	27:7110ebee3484	149	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
emilmont	27:7110ebee3484	150	#endif
emilmont	27:7110ebee3484	151	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	27:7110ebee3484	152	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	27:7110ebee3484	153	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	27:7110ebee3484	154	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	27:7110ebee3484	155	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	27:7110ebee3484	156	} b; /!< Structure used for bit access /
emilmont	27:7110ebee3484	157	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	158	} APSR_Type;
emilmont	27:7110ebee3484	159
emilmont	27:7110ebee3484	160
emilmont	27:7110ebee3484	161	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont	27:7110ebee3484	162	*/
emilmont	27:7110ebee3484	163	typedef union
emilmont	27:7110ebee3484	164	{
emilmont	27:7110ebee3484	165	struct
emilmont	27:7110ebee3484	166	{
emilmont	27:7110ebee3484	167	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	27:7110ebee3484	168	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
emilmont	27:7110ebee3484	169	} b; /!< Structure used for bit access /
emilmont	27:7110ebee3484	170	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	171	} IPSR_Type;
emilmont	27:7110ebee3484	172
emilmont	27:7110ebee3484	173
emilmont	27:7110ebee3484	174	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont	27:7110ebee3484	175	*/
emilmont	27:7110ebee3484	176	typedef union
emilmont	27:7110ebee3484	177	{
emilmont	27:7110ebee3484	178	struct
emilmont	27:7110ebee3484	179	{
emilmont	27:7110ebee3484	180	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	27:7110ebee3484	181	#if (__CORTEX_M != 0x04)
emilmont	27:7110ebee3484	182	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
emilmont	27:7110ebee3484	183	#else
emilmont	27:7110ebee3484	184	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
emilmont	27:7110ebee3484	185	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
emilmont	27:7110ebee3484	186	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
emilmont	27:7110ebee3484	187	#endif
emilmont	27:7110ebee3484	188	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
emilmont	27:7110ebee3484	189	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
emilmont	27:7110ebee3484	190	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	27:7110ebee3484	191	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	27:7110ebee3484	192	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	27:7110ebee3484	193	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	27:7110ebee3484	194	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	27:7110ebee3484	195	} b; /!< Structure used for bit access /
emilmont	27:7110ebee3484	196	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	197	} xPSR_Type;
emilmont	27:7110ebee3484	198
emilmont	27:7110ebee3484	199
emilmont	27:7110ebee3484	200	/** \brief Union type to access the Control Registers (CONTROL).
emilmont	27:7110ebee3484	201	*/
emilmont	27:7110ebee3484	202	typedef union
emilmont	27:7110ebee3484	203	{
emilmont	27:7110ebee3484	204	struct
emilmont	27:7110ebee3484	205	{
emilmont	27:7110ebee3484	206	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
emilmont	27:7110ebee3484	207	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
emilmont	27:7110ebee3484	208	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
emilmont	27:7110ebee3484	209	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
emilmont	27:7110ebee3484	210	} b; /!< Structure used for bit access /
emilmont	27:7110ebee3484	211	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	212	} CONTROL_Type;
emilmont	27:7110ebee3484	213
emilmont	27:7110ebee3484	214	/@} end of group CMSIS_CORE /
emilmont	27:7110ebee3484	215
emilmont	27:7110ebee3484	216
emilmont	27:7110ebee3484	217	/** \ingroup CMSIS_core_register
emilmont	27:7110ebee3484	218	\defgroup CMSIS_NVIC CMSIS NVIC
emilmont	27:7110ebee3484	219	Type definitions for the Cortex-M NVIC Registers
emilmont	27:7110ebee3484	220	@{
emilmont	27:7110ebee3484	221	*/
emilmont	27:7110ebee3484	222
emilmont	27:7110ebee3484	223	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont	27:7110ebee3484	224	*/
emilmont	27:7110ebee3484	225	typedef struct
emilmont	27:7110ebee3484	226	{
emilmont	27:7110ebee3484	227	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
emilmont	27:7110ebee3484	228	uint32_t RESERVED0[24];
emilmont	27:7110ebee3484	229	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
emilmont	27:7110ebee3484	230	uint32_t RSERVED1[24];
emilmont	27:7110ebee3484	231	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
emilmont	27:7110ebee3484	232	uint32_t RESERVED2[24];
emilmont	27:7110ebee3484	233	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
emilmont	27:7110ebee3484	234	uint32_t RESERVED3[24];
emilmont	27:7110ebee3484	235	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
emilmont	27:7110ebee3484	236	uint32_t RESERVED4[56];
emilmont	27:7110ebee3484	237	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
emilmont	27:7110ebee3484	238	uint32_t RESERVED5[644];
emilmont	27:7110ebee3484	239	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
emilmont	27:7110ebee3484	240	} NVIC_Type;
emilmont	27:7110ebee3484	241
emilmont	27:7110ebee3484	242	/@} end of group CMSIS_NVIC /
emilmont	27:7110ebee3484	243
emilmont	27:7110ebee3484	244
emilmont	27:7110ebee3484	245	/** \ingroup CMSIS_core_register
emilmont	27:7110ebee3484	246	\defgroup CMSIS_SCB CMSIS SCB
emilmont	27:7110ebee3484	247	Type definitions for the Cortex-M System Control Block Registers
emilmont	27:7110ebee3484	248	@{
emilmont	27:7110ebee3484	249	*/
emilmont	27:7110ebee3484	250
emilmont	27:7110ebee3484	251	/** \brief Structure type to access the System Control Block (SCB).
emilmont	27:7110ebee3484	252	*/
emilmont	27:7110ebee3484	253	typedef struct
emilmont	27:7110ebee3484	254	{
emilmont	27:7110ebee3484	255	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPU ID Base Register /
emilmont	27:7110ebee3484	256	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control State Register /
emilmont	27:7110ebee3484	257	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
emilmont	27:7110ebee3484	258	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register /
emilmont	27:7110ebee3484	259	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
emilmont	27:7110ebee3484	260	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
emilmont	27:7110ebee3484	261	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
emilmont	27:7110ebee3484	262	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
emilmont	27:7110ebee3484	263	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
emilmont	27:7110ebee3484	264	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) Hard Fault Status Register /
emilmont	27:7110ebee3484	265	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
emilmont	27:7110ebee3484	266	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) Mem Manage Address Register /
emilmont	27:7110ebee3484	267	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) Bus Fault Address Register /
emilmont	27:7110ebee3484	268	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
emilmont	27:7110ebee3484	269	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
emilmont	27:7110ebee3484	270	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
emilmont	27:7110ebee3484	271	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
emilmont	27:7110ebee3484	272	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
emilmont	27:7110ebee3484	273	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) ISA Feature Register /
emilmont	27:7110ebee3484	274	} SCB_Type;
emilmont	27:7110ebee3484	275
emilmont	27:7110ebee3484	276	/* SCB CPUID Register Definitions */
emilmont	27:7110ebee3484	277	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
emilmont	27:7110ebee3484	278	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
emilmont	27:7110ebee3484	279
emilmont	27:7110ebee3484	280	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
emilmont	27:7110ebee3484	281	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
emilmont	27:7110ebee3484	282
emilmont	27:7110ebee3484	283	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
emilmont	27:7110ebee3484	284	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
emilmont	27:7110ebee3484	285
emilmont	27:7110ebee3484	286	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
emilmont	27:7110ebee3484	287	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
emilmont	27:7110ebee3484	288
emilmont	27:7110ebee3484	289	/* SCB Interrupt Control State Register Definitions */
emilmont	27:7110ebee3484	290	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
emilmont	27:7110ebee3484	291	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
emilmont	27:7110ebee3484	292
emilmont	27:7110ebee3484	293	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
emilmont	27:7110ebee3484	294	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
emilmont	27:7110ebee3484	295
emilmont	27:7110ebee3484	296	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
emilmont	27:7110ebee3484	297	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
emilmont	27:7110ebee3484	298
emilmont	27:7110ebee3484	299	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
emilmont	27:7110ebee3484	300	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
emilmont	27:7110ebee3484	301
emilmont	27:7110ebee3484	302	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
emilmont	27:7110ebee3484	303	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
emilmont	27:7110ebee3484	304
emilmont	27:7110ebee3484	305	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
emilmont	27:7110ebee3484	306	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
emilmont	27:7110ebee3484	307
emilmont	27:7110ebee3484	308	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
emilmont	27:7110ebee3484	309	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
emilmont	27:7110ebee3484	310
emilmont	27:7110ebee3484	311	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
emilmont	27:7110ebee3484	312	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
emilmont	27:7110ebee3484	313
emilmont	27:7110ebee3484	314	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
emilmont	27:7110ebee3484	315	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
emilmont	27:7110ebee3484	316
emilmont	27:7110ebee3484	317	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
emilmont	27:7110ebee3484	318	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
emilmont	27:7110ebee3484	319
emilmont	27:7110ebee3484	320	/* SCB Interrupt Control State Register Definitions */
emilmont	27:7110ebee3484	321	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
emilmont	27:7110ebee3484	322	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
emilmont	27:7110ebee3484	323
emilmont	27:7110ebee3484	324	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
emilmont	27:7110ebee3484	325	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
emilmont	27:7110ebee3484	326
emilmont	27:7110ebee3484	327	/* SCB Application Interrupt and Reset Control Register Definitions */
emilmont	27:7110ebee3484	328	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
emilmont	27:7110ebee3484	329	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
emilmont	27:7110ebee3484	330
emilmont	27:7110ebee3484	331	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
emilmont	27:7110ebee3484	332	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
emilmont	27:7110ebee3484	333
emilmont	27:7110ebee3484	334	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
emilmont	27:7110ebee3484	335	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
emilmont	27:7110ebee3484	336
emilmont	27:7110ebee3484	337	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
emilmont	27:7110ebee3484	338	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
emilmont	27:7110ebee3484	339
emilmont	27:7110ebee3484	340	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
emilmont	27:7110ebee3484	341	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
emilmont	27:7110ebee3484	342
emilmont	27:7110ebee3484	343	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
emilmont	27:7110ebee3484	344	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
emilmont	27:7110ebee3484	345
emilmont	27:7110ebee3484	346	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
emilmont	27:7110ebee3484	347	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
emilmont	27:7110ebee3484	348
emilmont	27:7110ebee3484	349	/* SCB System Control Register Definitions */
emilmont	27:7110ebee3484	350	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
emilmont	27:7110ebee3484	351	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
emilmont	27:7110ebee3484	352
emilmont	27:7110ebee3484	353	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
emilmont	27:7110ebee3484	354	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
emilmont	27:7110ebee3484	355
emilmont	27:7110ebee3484	356	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
emilmont	27:7110ebee3484	357	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
emilmont	27:7110ebee3484	358
emilmont	27:7110ebee3484	359	/* SCB Configuration Control Register Definitions */
emilmont	27:7110ebee3484	360	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
emilmont	27:7110ebee3484	361	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
emilmont	27:7110ebee3484	362
emilmont	27:7110ebee3484	363	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
emilmont	27:7110ebee3484	364	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
emilmont	27:7110ebee3484	365
emilmont	27:7110ebee3484	366	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
emilmont	27:7110ebee3484	367	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
emilmont	27:7110ebee3484	368
emilmont	27:7110ebee3484	369	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
emilmont	27:7110ebee3484	370	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
emilmont	27:7110ebee3484	371
emilmont	27:7110ebee3484	372	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
emilmont	27:7110ebee3484	373	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
emilmont	27:7110ebee3484	374
emilmont	27:7110ebee3484	375	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
emilmont	27:7110ebee3484	376	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
emilmont	27:7110ebee3484	377
emilmont	27:7110ebee3484	378	/* SCB System Handler Control and State Register Definitions */
emilmont	27:7110ebee3484	379	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
emilmont	27:7110ebee3484	380	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
emilmont	27:7110ebee3484	381
emilmont	27:7110ebee3484	382	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
emilmont	27:7110ebee3484	383	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
emilmont	27:7110ebee3484	384
emilmont	27:7110ebee3484	385	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
emilmont	27:7110ebee3484	386	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
emilmont	27:7110ebee3484	387
emilmont	27:7110ebee3484	388	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
emilmont	27:7110ebee3484	389	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
emilmont	27:7110ebee3484	390
emilmont	27:7110ebee3484	391	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
emilmont	27:7110ebee3484	392	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
emilmont	27:7110ebee3484	393
emilmont	27:7110ebee3484	394	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
emilmont	27:7110ebee3484	395	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
emilmont	27:7110ebee3484	396
emilmont	27:7110ebee3484	397	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
emilmont	27:7110ebee3484	398	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
emilmont	27:7110ebee3484	399
emilmont	27:7110ebee3484	400	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
emilmont	27:7110ebee3484	401	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
emilmont	27:7110ebee3484	402
emilmont	27:7110ebee3484	403	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
emilmont	27:7110ebee3484	404	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
emilmont	27:7110ebee3484	405
emilmont	27:7110ebee3484	406	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
emilmont	27:7110ebee3484	407	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
emilmont	27:7110ebee3484	408
emilmont	27:7110ebee3484	409	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
emilmont	27:7110ebee3484	410	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
emilmont	27:7110ebee3484	411
emilmont	27:7110ebee3484	412	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
emilmont	27:7110ebee3484	413	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
emilmont	27:7110ebee3484	414
emilmont	27:7110ebee3484	415	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
emilmont	27:7110ebee3484	416	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
emilmont	27:7110ebee3484	417
emilmont	27:7110ebee3484	418	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
emilmont	27:7110ebee3484	419	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
emilmont	27:7110ebee3484	420
emilmont	27:7110ebee3484	421	/* SCB Configurable Fault Status Registers Definitions */
emilmont	27:7110ebee3484	422	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
emilmont	27:7110ebee3484	423	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
emilmont	27:7110ebee3484	424
emilmont	27:7110ebee3484	425	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
emilmont	27:7110ebee3484	426	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
emilmont	27:7110ebee3484	427
emilmont	27:7110ebee3484	428	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
emilmont	27:7110ebee3484	429	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
emilmont	27:7110ebee3484	430
emilmont	27:7110ebee3484	431	/* SCB Hard Fault Status Registers Definitions */
emilmont	27:7110ebee3484	432	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
emilmont	27:7110ebee3484	433	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
emilmont	27:7110ebee3484	434
emilmont	27:7110ebee3484	435	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
emilmont	27:7110ebee3484	436	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
emilmont	27:7110ebee3484	437
emilmont	27:7110ebee3484	438	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
emilmont	27:7110ebee3484	439	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
emilmont	27:7110ebee3484	440
emilmont	27:7110ebee3484	441	/* SCB Debug Fault Status Register Definitions */
emilmont	27:7110ebee3484	442	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
emilmont	27:7110ebee3484	443	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
emilmont	27:7110ebee3484	444
emilmont	27:7110ebee3484	445	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
emilmont	27:7110ebee3484	446	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
emilmont	27:7110ebee3484	447
emilmont	27:7110ebee3484	448	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
emilmont	27:7110ebee3484	449	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
emilmont	27:7110ebee3484	450
emilmont	27:7110ebee3484	451	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
emilmont	27:7110ebee3484	452	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
emilmont	27:7110ebee3484	453
emilmont	27:7110ebee3484	454	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
emilmont	27:7110ebee3484	455	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
emilmont	27:7110ebee3484	456
emilmont	27:7110ebee3484	457	/@} end of group CMSIS_SCB /
emilmont	27:7110ebee3484	458
emilmont	27:7110ebee3484	459
emilmont	27:7110ebee3484	460	/** \ingroup CMSIS_core_register
emilmont	27:7110ebee3484	461	\defgroup CMSIS_SysTick CMSIS SysTick
emilmont	27:7110ebee3484	462	Type definitions for the Cortex-M System Timer Registers
emilmont	27:7110ebee3484	463	@{
emilmont	27:7110ebee3484	464	*/
emilmont	27:7110ebee3484	465
emilmont	27:7110ebee3484	466	/** \brief Structure type to access the System Timer (SysTick).
emilmont	27:7110ebee3484	467	*/
emilmont	27:7110ebee3484	468	typedef struct
emilmont	27:7110ebee3484	469	{
emilmont	27:7110ebee3484	470	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
emilmont	27:7110ebee3484	471	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
emilmont	27:7110ebee3484	472	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
emilmont	27:7110ebee3484	473	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
emilmont	27:7110ebee3484	474	} SysTick_Type;
emilmont	27:7110ebee3484	475
emilmont	27:7110ebee3484	476	/* SysTick Control / Status Register Definitions */
emilmont	27:7110ebee3484	477	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
emilmont	27:7110ebee3484	478	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
emilmont	27:7110ebee3484	479
emilmont	27:7110ebee3484	480	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
emilmont	27:7110ebee3484	481	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
emilmont	27:7110ebee3484	482
emilmont	27:7110ebee3484	483	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
emilmont	27:7110ebee3484	484	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
emilmont	27:7110ebee3484	485
emilmont	27:7110ebee3484	486	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
emilmont	27:7110ebee3484	487	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
emilmont	27:7110ebee3484	488
emilmont	27:7110ebee3484	489	/* SysTick Reload Register Definitions */
emilmont	27:7110ebee3484	490	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
emilmont	27:7110ebee3484	491	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
emilmont	27:7110ebee3484	492
emilmont	27:7110ebee3484	493	/* SysTick Current Register Definitions */
emilmont	27:7110ebee3484	494	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
emilmont	27:7110ebee3484	495	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
emilmont	27:7110ebee3484	496
emilmont	27:7110ebee3484	497	/* SysTick Calibration Register Definitions */
emilmont	27:7110ebee3484	498	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
emilmont	27:7110ebee3484	499	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
emilmont	27:7110ebee3484	500
emilmont	27:7110ebee3484	501	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
emilmont	27:7110ebee3484	502	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
emilmont	27:7110ebee3484	503
emilmont	27:7110ebee3484	504	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
emilmont	27:7110ebee3484	505	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
emilmont	27:7110ebee3484	506
emilmont	27:7110ebee3484	507	/@} end of group CMSIS_SysTick /
emilmont	27:7110ebee3484	508
emilmont	27:7110ebee3484	509
emilmont	27:7110ebee3484	510	/** \ingroup CMSIS_core_register
emilmont	27:7110ebee3484	511	\defgroup CMSIS_ITM CMSIS ITM
emilmont	27:7110ebee3484	512	Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
emilmont	27:7110ebee3484	513	@{
emilmont	27:7110ebee3484	514	*/
emilmont	27:7110ebee3484	515
emilmont	27:7110ebee3484	516	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
emilmont	27:7110ebee3484	517	*/
emilmont	27:7110ebee3484	518	typedef struct
emilmont	27:7110ebee3484	519	{
emilmont	27:7110ebee3484	520	__O union
emilmont	27:7110ebee3484	521	{
emilmont	27:7110ebee3484	522	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
emilmont	27:7110ebee3484	523	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
emilmont	27:7110ebee3484	524	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
emilmont	27:7110ebee3484	525	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
emilmont	27:7110ebee3484	526	uint32_t RESERVED0[864];
emilmont	27:7110ebee3484	527	__IO uint32_t TER; /!< Offset: (R/W) ITM Trace Enable Register /
emilmont	27:7110ebee3484	528	uint32_t RESERVED1[15];
emilmont	27:7110ebee3484	529	__IO uint32_t TPR; /!< Offset: (R/W) ITM Trace Privilege Register /
emilmont	27:7110ebee3484	530	uint32_t RESERVED2[15];
emilmont	27:7110ebee3484	531	__IO uint32_t TCR; /!< Offset: (R/W) ITM Trace Control Register /
emilmont	27:7110ebee3484	532	uint32_t RESERVED3[29];
emilmont	27:7110ebee3484	533	__IO uint32_t IWR; /!< Offset: (R/W) ITM Integration Write Register /
emilmont	27:7110ebee3484	534	__IO uint32_t IRR; /!< Offset: (R/W) ITM Integration Read Register /
emilmont	27:7110ebee3484	535	__IO uint32_t IMCR; /!< Offset: (R/W) ITM Integration Mode Control Register /
emilmont	27:7110ebee3484	536	uint32_t RESERVED4[43];
emilmont	27:7110ebee3484	537	__IO uint32_t LAR; /!< Offset: (R/W) ITM Lock Access Register /
emilmont	27:7110ebee3484	538	__IO uint32_t LSR; /!< Offset: (R/W) ITM Lock Status Register /
emilmont	27:7110ebee3484	539	uint32_t RESERVED5[6];
emilmont	27:7110ebee3484	540	__I uint32_t PID4; /!< Offset: (R/ ) ITM Peripheral Identification Register #4 /
emilmont	27:7110ebee3484	541	__I uint32_t PID5; /!< Offset: (R/ ) ITM Peripheral Identification Register #5 /
emilmont	27:7110ebee3484	542	__I uint32_t PID6; /!< Offset: (R/ ) ITM Peripheral Identification Register #6 /
emilmont	27:7110ebee3484	543	__I uint32_t PID7; /!< Offset: (R/ ) ITM Peripheral Identification Register #7 /
emilmont	27:7110ebee3484	544	__I uint32_t PID0; /!< Offset: (R/ ) ITM Peripheral Identification Register #0 /
emilmont	27:7110ebee3484	545	__I uint32_t PID1; /!< Offset: (R/ ) ITM Peripheral Identification Register #1 /
emilmont	27:7110ebee3484	546	__I uint32_t PID2; /!< Offset: (R/ ) ITM Peripheral Identification Register #2 /
emilmont	27:7110ebee3484	547	__I uint32_t PID3; /!< Offset: (R/ ) ITM Peripheral Identification Register #3 /
emilmont	27:7110ebee3484	548	__I uint32_t CID0; /!< Offset: (R/ ) ITM Component Identification Register #0 /
emilmont	27:7110ebee3484	549	__I uint32_t CID1; /!< Offset: (R/ ) ITM Component Identification Register #1 /
emilmont	27:7110ebee3484	550	__I uint32_t CID2; /!< Offset: (R/ ) ITM Component Identification Register #2 /
emilmont	27:7110ebee3484	551	__I uint32_t CID3; /!< Offset: (R/ ) ITM Component Identification Register #3 /
emilmont	27:7110ebee3484	552	} ITM_Type;
emilmont	27:7110ebee3484	553
emilmont	27:7110ebee3484	554	/* ITM Trace Privilege Register Definitions */
emilmont	27:7110ebee3484	555	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
emilmont	27:7110ebee3484	556	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
emilmont	27:7110ebee3484	557
emilmont	27:7110ebee3484	558	/* ITM Trace Control Register Definitions */
emilmont	27:7110ebee3484	559	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
emilmont	27:7110ebee3484	560	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
emilmont	27:7110ebee3484	561
emilmont	27:7110ebee3484	562	#define ITM_TCR_ATBID_Pos 16 /!< ITM TCR: ATBID Position /
emilmont	27:7110ebee3484	563	#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /!< ITM TCR: ATBID Mask /
emilmont	27:7110ebee3484	564
emilmont	27:7110ebee3484	565	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
emilmont	27:7110ebee3484	566	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
emilmont	27:7110ebee3484	567
emilmont	27:7110ebee3484	568	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
emilmont	27:7110ebee3484	569	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
emilmont	27:7110ebee3484	570
emilmont	27:7110ebee3484	571	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
emilmont	27:7110ebee3484	572	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
emilmont	27:7110ebee3484	573
emilmont	27:7110ebee3484	574	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
emilmont	27:7110ebee3484	575	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
emilmont	27:7110ebee3484	576
emilmont	27:7110ebee3484	577	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
emilmont	27:7110ebee3484	578	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
emilmont	27:7110ebee3484	579
emilmont	27:7110ebee3484	580	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
emilmont	27:7110ebee3484	581	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
emilmont	27:7110ebee3484	582
emilmont	27:7110ebee3484	583	/* ITM Integration Write Register Definitions */
emilmont	27:7110ebee3484	584	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
emilmont	27:7110ebee3484	585	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
emilmont	27:7110ebee3484	586
emilmont	27:7110ebee3484	587	/* ITM Integration Read Register Definitions */
emilmont	27:7110ebee3484	588	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
emilmont	27:7110ebee3484	589	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
emilmont	27:7110ebee3484	590
emilmont	27:7110ebee3484	591	/* ITM Integration Mode Control Register Definitions */
emilmont	27:7110ebee3484	592	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
emilmont	27:7110ebee3484	593	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
emilmont	27:7110ebee3484	594
emilmont	27:7110ebee3484	595	/* ITM Lock Status Register Definitions */
emilmont	27:7110ebee3484	596	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
emilmont	27:7110ebee3484	597	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
emilmont	27:7110ebee3484	598
emilmont	27:7110ebee3484	599	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
emilmont	27:7110ebee3484	600	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
emilmont	27:7110ebee3484	601
emilmont	27:7110ebee3484	602	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
emilmont	27:7110ebee3484	603	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
emilmont	27:7110ebee3484	604
emilmont	27:7110ebee3484	605	/@}/ /* end of group CMSIS_ITM */
emilmont	27:7110ebee3484	606
emilmont	27:7110ebee3484	607
emilmont	27:7110ebee3484	608	/** \ingroup CMSIS_core_register
emilmont	27:7110ebee3484	609	\defgroup CMSIS_InterruptType CMSIS Interrupt Type
emilmont	27:7110ebee3484	610	Type definitions for the Cortex-M Interrupt Type Register
emilmont	27:7110ebee3484	611	@{
emilmont	27:7110ebee3484	612	*/
emilmont	27:7110ebee3484	613
emilmont	27:7110ebee3484	614	/** \brief Structure type to access the Interrupt Type Register.
emilmont	27:7110ebee3484	615	*/
emilmont	27:7110ebee3484	616	typedef struct
emilmont	27:7110ebee3484	617	{
emilmont	27:7110ebee3484	618	uint32_t RESERVED0;
emilmont	27:7110ebee3484	619	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Control Type Register /
emilmont	27:7110ebee3484	620	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
emilmont	27:7110ebee3484	621	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
emilmont	27:7110ebee3484	622	#else
emilmont	27:7110ebee3484	623	uint32_t RESERVED1;
emilmont	27:7110ebee3484	624	#endif
emilmont	27:7110ebee3484	625	} InterruptType_Type;
emilmont	27:7110ebee3484	626
emilmont	27:7110ebee3484	627	/* Interrupt Controller Type Register Definitions */
emilmont	27:7110ebee3484	628	#define IntType_ICTR_INTLINESNUM_Pos 0 /!< InterruptType ICTR: INTLINESNUM Position /
emilmont	27:7110ebee3484	629	#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /!< InterruptType ICTR: INTLINESNUM Mask /
emilmont	27:7110ebee3484	630
emilmont	27:7110ebee3484	631	/* Auxiliary Control Register Definitions */
emilmont	27:7110ebee3484	632	#define IntType_ACTLR_DISFOLD_Pos 2 /!< InterruptType ACTLR: DISFOLD Position /
emilmont	27:7110ebee3484	633	#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /!< InterruptType ACTLR: DISFOLD Mask /
emilmont	27:7110ebee3484	634
emilmont	27:7110ebee3484	635	#define IntType_ACTLR_DISDEFWBUF_Pos 1 /!< InterruptType ACTLR: DISDEFWBUF Position /
emilmont	27:7110ebee3484	636	#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /!< InterruptType ACTLR: DISDEFWBUF Mask /
emilmont	27:7110ebee3484	637
emilmont	27:7110ebee3484	638	#define IntType_ACTLR_DISMCYCINT_Pos 0 /!< InterruptType ACTLR: DISMCYCINT Position /
emilmont	27:7110ebee3484	639	#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /!< InterruptType ACTLR: DISMCYCINT Mask /
emilmont	27:7110ebee3484	640
emilmont	27:7110ebee3484	641	/@}/ /* end of group CMSIS_InterruptType */
emilmont	27:7110ebee3484	642
emilmont	27:7110ebee3484	643
emilmont	27:7110ebee3484	644	#if (__MPU_PRESENT == 1)
emilmont	27:7110ebee3484	645	/** \ingroup CMSIS_core_register
emilmont	27:7110ebee3484	646	\defgroup CMSIS_MPU CMSIS MPU
emilmont	27:7110ebee3484	647	Type definitions for the Cortex-M Memory Protection Unit (MPU)
emilmont	27:7110ebee3484	648	@{
emilmont	27:7110ebee3484	649	*/
emilmont	27:7110ebee3484	650
emilmont	27:7110ebee3484	651	/** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont	27:7110ebee3484	652	*/
emilmont	27:7110ebee3484	653	typedef struct
emilmont	27:7110ebee3484	654	{
emilmont	27:7110ebee3484	655	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
emilmont	27:7110ebee3484	656	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
emilmont	27:7110ebee3484	657	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
emilmont	27:7110ebee3484	658	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
emilmont	27:7110ebee3484	659	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
emilmont	27:7110ebee3484	660	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
emilmont	27:7110ebee3484	661	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
emilmont	27:7110ebee3484	662	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
emilmont	27:7110ebee3484	663	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
emilmont	27:7110ebee3484	664	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
emilmont	27:7110ebee3484	665	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
emilmont	27:7110ebee3484	666	} MPU_Type;
emilmont	27:7110ebee3484	667
emilmont	27:7110ebee3484	668	/* MPU Type Register */
emilmont	27:7110ebee3484	669	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
emilmont	27:7110ebee3484	670	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
emilmont	27:7110ebee3484	671
emilmont	27:7110ebee3484	672	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
emilmont	27:7110ebee3484	673	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
emilmont	27:7110ebee3484	674
emilmont	27:7110ebee3484	675	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
emilmont	27:7110ebee3484	676	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
emilmont	27:7110ebee3484	677
emilmont	27:7110ebee3484	678	/* MPU Control Register */
emilmont	27:7110ebee3484	679	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
emilmont	27:7110ebee3484	680	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
emilmont	27:7110ebee3484	681
emilmont	27:7110ebee3484	682	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
emilmont	27:7110ebee3484	683	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
emilmont	27:7110ebee3484	684
emilmont	27:7110ebee3484	685	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
emilmont	27:7110ebee3484	686	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
emilmont	27:7110ebee3484	687
emilmont	27:7110ebee3484	688	/* MPU Region Number Register */
emilmont	27:7110ebee3484	689	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
emilmont	27:7110ebee3484	690	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
emilmont	27:7110ebee3484	691
emilmont	27:7110ebee3484	692	/* MPU Region Base Address Register */
emilmont	27:7110ebee3484	693	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
emilmont	27:7110ebee3484	694	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
emilmont	27:7110ebee3484	695
emilmont	27:7110ebee3484	696	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
emilmont	27:7110ebee3484	697	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
emilmont	27:7110ebee3484	698
emilmont	27:7110ebee3484	699	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
emilmont	27:7110ebee3484	700	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
emilmont	27:7110ebee3484	701
emilmont	27:7110ebee3484	702	/* MPU Region Attribute and Size Register */
emilmont	27:7110ebee3484	703	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: XN Position /
emilmont	27:7110ebee3484	704	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: XN Mask /
emilmont	27:7110ebee3484	705
emilmont	27:7110ebee3484	706	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: AP Position /
emilmont	27:7110ebee3484	707	#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /!< MPU RASR: AP Mask /
emilmont	27:7110ebee3484	708
emilmont	27:7110ebee3484	709	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: TEX Position /
emilmont	27:7110ebee3484	710	#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: TEX Mask /
emilmont	27:7110ebee3484	711
emilmont	27:7110ebee3484	712	#define MPU_RASR_S_Pos 18 /!< MPU RASR: Shareable bit Position /
emilmont	27:7110ebee3484	713	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: Shareable bit Mask /
emilmont	27:7110ebee3484	714
emilmont	27:7110ebee3484	715	#define MPU_RASR_C_Pos 17 /!< MPU RASR: Cacheable bit Position /
emilmont	27:7110ebee3484	716	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: Cacheable bit Mask /
emilmont	27:7110ebee3484	717
emilmont	27:7110ebee3484	718	#define MPU_RASR_B_Pos 16 /!< MPU RASR: Bufferable bit Position /
emilmont	27:7110ebee3484	719	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: Bufferable bit Mask /
emilmont	27:7110ebee3484	720
emilmont	27:7110ebee3484	721	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
emilmont	27:7110ebee3484	722	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
emilmont	27:7110ebee3484	723
emilmont	27:7110ebee3484	724	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
emilmont	27:7110ebee3484	725	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
emilmont	27:7110ebee3484	726
emilmont	27:7110ebee3484	727	#define MPU_RASR_ENA_Pos 0 /!< MPU RASR: Region enable bit Position /
emilmont	27:7110ebee3484	728	#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /!< MPU RASR: Region enable bit Disable Mask /
emilmont	27:7110ebee3484	729
emilmont	27:7110ebee3484	730	/@} end of group CMSIS_MPU /
emilmont	27:7110ebee3484	731	#endif
emilmont	27:7110ebee3484	732
emilmont	27:7110ebee3484	733
emilmont	27:7110ebee3484	734	/** \ingroup CMSIS_core_register
emilmont	27:7110ebee3484	735	\defgroup CMSIS_CoreDebug CMSIS Core Debug
emilmont	27:7110ebee3484	736	Type definitions for the Cortex-M Core Debug Registers
emilmont	27:7110ebee3484	737	@{
emilmont	27:7110ebee3484	738	*/
emilmont	27:7110ebee3484	739
emilmont	27:7110ebee3484	740	/** \brief Structure type to access the Core Debug Register (CoreDebug).
emilmont	27:7110ebee3484	741	*/
emilmont	27:7110ebee3484	742	typedef struct
emilmont	27:7110ebee3484	743	{
emilmont	27:7110ebee3484	744	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
emilmont	27:7110ebee3484	745	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
emilmont	27:7110ebee3484	746	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
emilmont	27:7110ebee3484	747	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
emilmont	27:7110ebee3484	748	} CoreDebug_Type;
emilmont	27:7110ebee3484	749
emilmont	27:7110ebee3484	750	/* Debug Halting Control and Status Register */
emilmont	27:7110ebee3484	751	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
emilmont	27:7110ebee3484	752	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
emilmont	27:7110ebee3484	753
emilmont	27:7110ebee3484	754	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
emilmont	27:7110ebee3484	755	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
emilmont	27:7110ebee3484	756
emilmont	27:7110ebee3484	757	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
emilmont	27:7110ebee3484	758	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
emilmont	27:7110ebee3484	759
emilmont	27:7110ebee3484	760	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
emilmont	27:7110ebee3484	761	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
emilmont	27:7110ebee3484	762
emilmont	27:7110ebee3484	763	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
emilmont	27:7110ebee3484	764	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
emilmont	27:7110ebee3484	765
emilmont	27:7110ebee3484	766	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
emilmont	27:7110ebee3484	767	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
emilmont	27:7110ebee3484	768
emilmont	27:7110ebee3484	769	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
emilmont	27:7110ebee3484	770	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
emilmont	27:7110ebee3484	771
emilmont	27:7110ebee3484	772	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
emilmont	27:7110ebee3484	773	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
emilmont	27:7110ebee3484	774
emilmont	27:7110ebee3484	775	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
emilmont	27:7110ebee3484	776	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
emilmont	27:7110ebee3484	777
emilmont	27:7110ebee3484	778	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
emilmont	27:7110ebee3484	779	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
emilmont	27:7110ebee3484	780
emilmont	27:7110ebee3484	781	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
emilmont	27:7110ebee3484	782	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
emilmont	27:7110ebee3484	783
emilmont	27:7110ebee3484	784	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
emilmont	27:7110ebee3484	785	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
emilmont	27:7110ebee3484	786
emilmont	27:7110ebee3484	787	/* Debug Core Register Selector Register */
emilmont	27:7110ebee3484	788	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
emilmont	27:7110ebee3484	789	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
emilmont	27:7110ebee3484	790
emilmont	27:7110ebee3484	791	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
emilmont	27:7110ebee3484	792	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
emilmont	27:7110ebee3484	793
emilmont	27:7110ebee3484	794	/* Debug Exception and Monitor Control Register */
emilmont	27:7110ebee3484	795	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
emilmont	27:7110ebee3484	796	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
emilmont	27:7110ebee3484	797
emilmont	27:7110ebee3484	798	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
emilmont	27:7110ebee3484	799	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
emilmont	27:7110ebee3484	800
emilmont	27:7110ebee3484	801	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
emilmont	27:7110ebee3484	802	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
emilmont	27:7110ebee3484	803
emilmont	27:7110ebee3484	804	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
emilmont	27:7110ebee3484	805	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
emilmont	27:7110ebee3484	806
emilmont	27:7110ebee3484	807	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
emilmont	27:7110ebee3484	808	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
emilmont	27:7110ebee3484	809
emilmont	27:7110ebee3484	810	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
emilmont	27:7110ebee3484	811	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
emilmont	27:7110ebee3484	812
emilmont	27:7110ebee3484	813	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
emilmont	27:7110ebee3484	814	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
emilmont	27:7110ebee3484	815
emilmont	27:7110ebee3484	816	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
emilmont	27:7110ebee3484	817	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
emilmont	27:7110ebee3484	818
emilmont	27:7110ebee3484	819	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
emilmont	27:7110ebee3484	820	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
emilmont	27:7110ebee3484	821
emilmont	27:7110ebee3484	822	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
emilmont	27:7110ebee3484	823	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
emilmont	27:7110ebee3484	824
emilmont	27:7110ebee3484	825	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
emilmont	27:7110ebee3484	826	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
emilmont	27:7110ebee3484	827
emilmont	27:7110ebee3484	828	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
emilmont	27:7110ebee3484	829	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
emilmont	27:7110ebee3484	830
emilmont	27:7110ebee3484	831	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
emilmont	27:7110ebee3484	832	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
emilmont	27:7110ebee3484	833
emilmont	27:7110ebee3484	834	/@} end of group CMSIS_CoreDebug /
emilmont	27:7110ebee3484	835
emilmont	27:7110ebee3484	836
emilmont	27:7110ebee3484	837	/** \ingroup CMSIS_core_register
emilmont	27:7110ebee3484	838	@{
emilmont	27:7110ebee3484	839	*/
emilmont	27:7110ebee3484	840
emilmont	27:7110ebee3484	841	/* Memory mapping of Cortex-M3 Hardware */
emilmont	27:7110ebee3484	842	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
emilmont	27:7110ebee3484	843	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
emilmont	27:7110ebee3484	844	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
emilmont	27:7110ebee3484	845	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
emilmont	27:7110ebee3484	846	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
emilmont	27:7110ebee3484	847	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
emilmont	27:7110ebee3484	848
emilmont	27:7110ebee3484	849	#define InterruptType ((InterruptType_Type ) SCS_BASE) /!< Interrupt Type Register */
emilmont	27:7110ebee3484	850	#define SCB ((SCB_Type ) SCB_BASE) /!< SCB configuration struct */
emilmont	27:7110ebee3484	851	#define SysTick ((SysTick_Type ) SysTick_BASE) /!< SysTick configuration struct */
emilmont	27:7110ebee3484	852	#define NVIC ((NVIC_Type ) NVIC_BASE) /!< NVIC configuration struct */
emilmont	27:7110ebee3484	853	#define ITM ((ITM_Type ) ITM_BASE) /!< ITM configuration struct */
emilmont	27:7110ebee3484	854	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
emilmont	27:7110ebee3484	855
emilmont	27:7110ebee3484	856	#if (__MPU_PRESENT == 1)
emilmont	27:7110ebee3484	857	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
emilmont	27:7110ebee3484	858	#define MPU ((MPU_Type) MPU_BASE) /!< Memory Protection Unit */
emilmont	27:7110ebee3484	859	#endif
emilmont	27:7110ebee3484	860
emilmont	27:7110ebee3484	861	/@} /
emilmont	27:7110ebee3484	862
emilmont	27:7110ebee3484	863
emilmont	27:7110ebee3484	864
emilmont	27:7110ebee3484	865	/*******************************************************************************
emilmont	27:7110ebee3484	866	* Hardware Abstraction Layer
emilmont	27:7110ebee3484	867	******************************************************************************/
emilmont	27:7110ebee3484	868	/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
emilmont	27:7110ebee3484	869	Core Function Interface contains:
emilmont	27:7110ebee3484	870	- Core NVIC Functions
emilmont	27:7110ebee3484	871	- Core SysTick Functions
emilmont	27:7110ebee3484	872	- Core Debug Functions
emilmont	27:7110ebee3484	873	- Core Register Access Functions
emilmont	27:7110ebee3484	874	*/
emilmont	27:7110ebee3484	875
emilmont	27:7110ebee3484	876
emilmont	27:7110ebee3484	877
emilmont	27:7110ebee3484	878	/* ########################## NVIC functions #################################### */
emilmont	27:7110ebee3484	879	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	27:7110ebee3484	880	\defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
emilmont	27:7110ebee3484	881	@{
emilmont	27:7110ebee3484	882	*/
emilmont	27:7110ebee3484	883
emilmont	27:7110ebee3484	884	/** \brief Set Priority Grouping
emilmont	27:7110ebee3484	885
emilmont	27:7110ebee3484	886	This function sets the priority grouping field using the required unlock sequence.
emilmont	27:7110ebee3484	887	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
emilmont	27:7110ebee3484	888	Only values from 0..7 are used.
emilmont	27:7110ebee3484	889	In case of a conflict between priority grouping and available
emilmont	27:7110ebee3484	890	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
emilmont	27:7110ebee3484	891
emilmont	27:7110ebee3484	892	\param [in] PriorityGroup Priority grouping field
emilmont	27:7110ebee3484	893	*/
emilmont	27:7110ebee3484	894	static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
emilmont	27:7110ebee3484	895	{
emilmont	27:7110ebee3484	896	uint32_t reg_value;
emilmont	27:7110ebee3484	897	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont	27:7110ebee3484	898
emilmont	27:7110ebee3484	899	reg_value = SCB->AIRCR; /* read old register configuration */
emilmont	27:7110ebee3484	900	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
emilmont	27:7110ebee3484	901	reg_value = (reg_value \|
emilmont	27:7110ebee3484	902	(0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
emilmont	27:7110ebee3484	903	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
emilmont	27:7110ebee3484	904	SCB->AIRCR = reg_value;
emilmont	27:7110ebee3484	905	}
emilmont	27:7110ebee3484	906
emilmont	27:7110ebee3484	907
emilmont	27:7110ebee3484	908	/** \brief Get Priority Grouping
emilmont	27:7110ebee3484	909
emilmont	27:7110ebee3484	910	This function gets the priority grouping from NVIC Interrupt Controller.
emilmont	27:7110ebee3484	911	Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
emilmont	27:7110ebee3484	912
emilmont	27:7110ebee3484	913	\return Priority grouping field
emilmont	27:7110ebee3484	914	*/
emilmont	27:7110ebee3484	915	static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
emilmont	27:7110ebee3484	916	{
emilmont	27:7110ebee3484	917	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
emilmont	27:7110ebee3484	918	}
emilmont	27:7110ebee3484	919
emilmont	27:7110ebee3484	920
emilmont	27:7110ebee3484	921	/** \brief Enable External Interrupt
emilmont	27:7110ebee3484	922
emilmont	27:7110ebee3484	923	This function enables a device specific interupt in the NVIC interrupt controller.
emilmont	27:7110ebee3484	924	The interrupt number cannot be a negative value.
emilmont	27:7110ebee3484	925
emilmont	27:7110ebee3484	926	\param [in] IRQn Number of the external interrupt to enable
emilmont	27:7110ebee3484	927	*/
emilmont	27:7110ebee3484	928	static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	929	{
emilmont	27:7110ebee3484	930	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
emilmont	27:7110ebee3484	931	}
emilmont	27:7110ebee3484	932
emilmont	27:7110ebee3484	933
emilmont	27:7110ebee3484	934	/** \brief Disable External Interrupt
emilmont	27:7110ebee3484	935
emilmont	27:7110ebee3484	936	This function disables a device specific interupt in the NVIC interrupt controller.
emilmont	27:7110ebee3484	937	The interrupt number cannot be a negative value.
emilmont	27:7110ebee3484	938
emilmont	27:7110ebee3484	939	\param [in] IRQn Number of the external interrupt to disable
emilmont	27:7110ebee3484	940	*/
emilmont	27:7110ebee3484	941	static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	942	{
emilmont	27:7110ebee3484	943	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
emilmont	27:7110ebee3484	944	}
emilmont	27:7110ebee3484	945
emilmont	27:7110ebee3484	946
emilmont	27:7110ebee3484	947	/** \brief Get Pending Interrupt
emilmont	27:7110ebee3484	948
emilmont	27:7110ebee3484	949	This function reads the pending register in the NVIC and returns the pending bit
emilmont	27:7110ebee3484	950	for the specified interrupt.
emilmont	27:7110ebee3484	951
emilmont	27:7110ebee3484	952	\param [in] IRQn Number of the interrupt for get pending
emilmont	27:7110ebee3484	953	\return 0 Interrupt status is not pending
emilmont	27:7110ebee3484	954	\return 1 Interrupt status is pending
emilmont	27:7110ebee3484	955	*/
emilmont	27:7110ebee3484	956	static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	957	{
emilmont	27:7110ebee3484	958	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
emilmont	27:7110ebee3484	959	}
emilmont	27:7110ebee3484	960
emilmont	27:7110ebee3484	961
emilmont	27:7110ebee3484	962	/** \brief Set Pending Interrupt
emilmont	27:7110ebee3484	963
emilmont	27:7110ebee3484	964	This function sets the pending bit for the specified interrupt.
emilmont	27:7110ebee3484	965	The interrupt number cannot be a negative value.
emilmont	27:7110ebee3484	966
emilmont	27:7110ebee3484	967	\param [in] IRQn Number of the interrupt for set pending
emilmont	27:7110ebee3484	968	*/
emilmont	27:7110ebee3484	969	static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	970	{
emilmont	27:7110ebee3484	971	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
emilmont	27:7110ebee3484	972	}
emilmont	27:7110ebee3484	973
emilmont	27:7110ebee3484	974
emilmont	27:7110ebee3484	975	/** \brief Clear Pending Interrupt
emilmont	27:7110ebee3484	976
emilmont	27:7110ebee3484	977	This function clears the pending bit for the specified interrupt.
emilmont	27:7110ebee3484	978	The interrupt number cannot be a negative value.
emilmont	27:7110ebee3484	979
emilmont	27:7110ebee3484	980	\param [in] IRQn Number of the interrupt for clear pending
emilmont	27:7110ebee3484	981	*/
emilmont	27:7110ebee3484	982	static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	983	{
emilmont	27:7110ebee3484	984	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont	27:7110ebee3484	985	}
emilmont	27:7110ebee3484	986
emilmont	27:7110ebee3484	987
emilmont	27:7110ebee3484	988	/** \brief Get Active Interrupt
emilmont	27:7110ebee3484	989
emilmont	27:7110ebee3484	990	This function reads the active register in NVIC and returns the active bit.
emilmont	27:7110ebee3484	991	\param [in] IRQn Number of the interrupt for get active
emilmont	27:7110ebee3484	992	\return 0 Interrupt status is not active
emilmont	27:7110ebee3484	993	\return 1 Interrupt status is active
emilmont	27:7110ebee3484	994	*/
emilmont	27:7110ebee3484	995	static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
emilmont	27:7110ebee3484	996	{
emilmont	27:7110ebee3484	997	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
emilmont	27:7110ebee3484	998	}
emilmont	27:7110ebee3484	999
emilmont	27:7110ebee3484	1000
emilmont	27:7110ebee3484	1001	/** \brief Set Interrupt Priority
emilmont	27:7110ebee3484	1002
emilmont	27:7110ebee3484	1003	This function sets the priority for the specified interrupt. The interrupt
emilmont	27:7110ebee3484	1004	number can be positive to specify an external (device specific)
emilmont	27:7110ebee3484	1005	interrupt, or negative to specify an internal (core) interrupt.
emilmont	27:7110ebee3484	1006
emilmont	27:7110ebee3484	1007	Note: The priority cannot be set for every core interrupt.
emilmont	27:7110ebee3484	1008
emilmont	27:7110ebee3484	1009	\param [in] IRQn Number of the interrupt for set priority
emilmont	27:7110ebee3484	1010	\param [in] priority Priority to set
emilmont	27:7110ebee3484	1011	*/
emilmont	27:7110ebee3484	1012	static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont	27:7110ebee3484	1013	{
emilmont	27:7110ebee3484	1014	if(IRQn < 0) {
emilmont	27:7110ebee3484	1015	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
emilmont	27:7110ebee3484	1016	else {
emilmont	27:7110ebee3484	1017	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
emilmont	27:7110ebee3484	1018	}
emilmont	27:7110ebee3484	1019
emilmont	27:7110ebee3484	1020
emilmont	27:7110ebee3484	1021	/** \brief Get Interrupt Priority
emilmont	27:7110ebee3484	1022
emilmont	27:7110ebee3484	1023	This function reads the priority for the specified interrupt. The interrupt
emilmont	27:7110ebee3484	1024	number can be positive to specify an external (device specific)
emilmont	27:7110ebee3484	1025	interrupt, or negative to specify an internal (core) interrupt.
emilmont	27:7110ebee3484	1026
emilmont	27:7110ebee3484	1027	The returned priority value is automatically aligned to the implemented
emilmont	27:7110ebee3484	1028	priority bits of the microcontroller.
emilmont	27:7110ebee3484	1029
emilmont	27:7110ebee3484	1030	\param [in] IRQn Number of the interrupt for get priority
emilmont	27:7110ebee3484	1031	\return Interrupt Priority
emilmont	27:7110ebee3484	1032	*/
emilmont	27:7110ebee3484	1033	static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont	27:7110ebee3484	1034	{
emilmont	27:7110ebee3484	1035
emilmont	27:7110ebee3484	1036	if(IRQn < 0) {
emilmont	27:7110ebee3484	1037	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
emilmont	27:7110ebee3484	1038	else {
emilmont	27:7110ebee3484	1039	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont	27:7110ebee3484	1040	}
emilmont	27:7110ebee3484	1041
emilmont	27:7110ebee3484	1042
emilmont	27:7110ebee3484	1043	/** \brief Encode Priority
emilmont	27:7110ebee3484	1044
emilmont	27:7110ebee3484	1045	This function encodes the priority for an interrupt with the given priority group,
emilmont	27:7110ebee3484	1046	preemptive priority value and sub priority value.
emilmont	27:7110ebee3484	1047	In case of a conflict between priority grouping and available
emilmont	27:7110ebee3484	1048	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
emilmont	27:7110ebee3484	1049
emilmont	27:7110ebee3484	1050	The returned priority value can be used for NVIC_SetPriority(...) function
emilmont	27:7110ebee3484	1051
emilmont	27:7110ebee3484	1052	\param [in] PriorityGroup Used priority group
emilmont	27:7110ebee3484	1053	\param [in] PreemptPriority Preemptive priority value (starting from 0)
emilmont	27:7110ebee3484	1054	\param [in] SubPriority Sub priority value (starting from 0)
emilmont	27:7110ebee3484	1055	\return Encoded priority for the interrupt
emilmont	27:7110ebee3484	1056	*/
emilmont	27:7110ebee3484	1057	static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
emilmont	27:7110ebee3484	1058	{
emilmont	27:7110ebee3484	1059	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont	27:7110ebee3484	1060	uint32_t PreemptPriorityBits;
emilmont	27:7110ebee3484	1061	uint32_t SubPriorityBits;
emilmont	27:7110ebee3484	1062
emilmont	27:7110ebee3484	1063	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont	27:7110ebee3484	1064	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont	27:7110ebee3484	1065
emilmont	27:7110ebee3484	1066	return (
emilmont	27:7110ebee3484	1067	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
emilmont	27:7110ebee3484	1068	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
emilmont	27:7110ebee3484	1069	);
emilmont	27:7110ebee3484	1070	}
emilmont	27:7110ebee3484	1071
emilmont	27:7110ebee3484	1072
emilmont	27:7110ebee3484	1073	/** \brief Decode Priority
emilmont	27:7110ebee3484	1074
emilmont	27:7110ebee3484	1075	This function decodes an interrupt priority value with the given priority group to
emilmont	27:7110ebee3484	1076	preemptive priority value and sub priority value.
emilmont	27:7110ebee3484	1077	In case of a conflict between priority grouping and available
emilmont	27:7110ebee3484	1078	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
emilmont	27:7110ebee3484	1079
emilmont	27:7110ebee3484	1080	The priority value can be retrieved with NVIC_GetPriority(...) function
emilmont	27:7110ebee3484	1081
emilmont	27:7110ebee3484	1082	\param [in] Priority Priority value
emilmont	27:7110ebee3484	1083	\param [in] PriorityGroup Used priority group
emilmont	27:7110ebee3484	1084	\param [out] pPreemptPriority Preemptive priority value (starting from 0)
emilmont	27:7110ebee3484	1085	\param [out] pSubPriority Sub priority value (starting from 0)
emilmont	27:7110ebee3484	1086	*/
emilmont	27:7110ebee3484	1087	static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
emilmont	27:7110ebee3484	1088	{
emilmont	27:7110ebee3484	1089	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont	27:7110ebee3484	1090	uint32_t PreemptPriorityBits;
emilmont	27:7110ebee3484	1091	uint32_t SubPriorityBits;
emilmont	27:7110ebee3484	1092
emilmont	27:7110ebee3484	1093	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont	27:7110ebee3484	1094	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont	27:7110ebee3484	1095
emilmont	27:7110ebee3484	1096	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
emilmont	27:7110ebee3484	1097	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
emilmont	27:7110ebee3484	1098	}
emilmont	27:7110ebee3484	1099
emilmont	27:7110ebee3484	1100
emilmont	27:7110ebee3484	1101	/** \brief System Reset
emilmont	27:7110ebee3484	1102
emilmont	27:7110ebee3484	1103	This function initiate a system reset request to reset the MCU.
emilmont	27:7110ebee3484	1104	*/
emilmont	27:7110ebee3484	1105	static __INLINE void NVIC_SystemReset(void)
emilmont	27:7110ebee3484	1106	{
emilmont	27:7110ebee3484	1107	__DSB(); /* Ensure all outstanding memory accesses included
emilmont	27:7110ebee3484	1108	buffered write are completed before reset */
emilmont	27:7110ebee3484	1109	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
emilmont	27:7110ebee3484	1110	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
emilmont	27:7110ebee3484	1111	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
emilmont	27:7110ebee3484	1112	__DSB(); /* Ensure completion of memory access */
emilmont	27:7110ebee3484	1113	while(1); /* wait until reset */
emilmont	27:7110ebee3484	1114	}
emilmont	27:7110ebee3484	1115
emilmont	27:7110ebee3484	1116	/@} end of CMSIS_Core_NVICFunctions /
emilmont	27:7110ebee3484	1117
emilmont	27:7110ebee3484	1118
emilmont	27:7110ebee3484	1119
emilmont	27:7110ebee3484	1120	/* ################################## SysTick function ############################################ */
emilmont	27:7110ebee3484	1121	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	27:7110ebee3484	1122	\defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
emilmont	27:7110ebee3484	1123	@{
emilmont	27:7110ebee3484	1124	*/
emilmont	27:7110ebee3484	1125
emilmont	27:7110ebee3484	1126	#if (__Vendor_SysTickConfig == 0)
emilmont	27:7110ebee3484	1127
emilmont	27:7110ebee3484	1128	/** \brief System Tick Configuration
emilmont	27:7110ebee3484	1129
emilmont	27:7110ebee3484	1130	This function initialises the system tick timer and its interrupt and start the system tick timer.
emilmont	27:7110ebee3484	1131	Counter is in free running mode to generate periodical interrupts.
emilmont	27:7110ebee3484	1132
emilmont	27:7110ebee3484	1133	\param [in] ticks Number of ticks between two interrupts
emilmont	27:7110ebee3484	1134	\return 0 Function succeeded
emilmont	27:7110ebee3484	1135	\return 1 Function failed
emilmont	27:7110ebee3484	1136	*/
emilmont	27:7110ebee3484	1137	static __INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont	27:7110ebee3484	1138	{
emilmont	27:7110ebee3484	1139	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont	27:7110ebee3484	1140
emilmont	27:7110ebee3484	1141	SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
emilmont	27:7110ebee3484	1142	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
emilmont	27:7110ebee3484	1143	SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont	27:7110ebee3484	1144	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
emilmont	27:7110ebee3484	1145	SysTick_CTRL_TICKINT_Msk \|
emilmont	27:7110ebee3484	1146	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont	27:7110ebee3484	1147	return (0); /* Function successful */
emilmont	27:7110ebee3484	1148	}
emilmont	27:7110ebee3484	1149
emilmont	27:7110ebee3484	1150	#endif
emilmont	27:7110ebee3484	1151
emilmont	27:7110ebee3484	1152	/@} end of CMSIS_Core_SysTickFunctions /
emilmont	27:7110ebee3484	1153
emilmont	27:7110ebee3484	1154
emilmont	27:7110ebee3484	1155
emilmont	27:7110ebee3484	1156	/* ##################################### Debug In/Output function ########################################### */
emilmont	27:7110ebee3484	1157	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	27:7110ebee3484	1158	\defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
emilmont	27:7110ebee3484	1159	@{
emilmont	27:7110ebee3484	1160	*/
emilmont	27:7110ebee3484	1161
emilmont	27:7110ebee3484	1162	extern volatile int32_t ITM_RxBuffer; /!< external variable to receive characters /
emilmont	27:7110ebee3484	1163	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< value identifying ITM_RxBuffer is ready for next character /
emilmont	27:7110ebee3484	1164
emilmont	27:7110ebee3484	1165
emilmont	27:7110ebee3484	1166	/** \brief ITM Send Character
emilmont	27:7110ebee3484	1167
emilmont	27:7110ebee3484	1168	This function transmits a character via the ITM channel 0.
emilmont	27:7110ebee3484	1169	It just returns when no debugger is connected that has booked the output.
emilmont	27:7110ebee3484	1170	It is blocking when a debugger is connected, but the previous character send is not transmitted.
emilmont	27:7110ebee3484	1171
emilmont	27:7110ebee3484	1172	\param [in] ch Character to transmit
emilmont	27:7110ebee3484	1173	\return Character to transmit
emilmont	27:7110ebee3484	1174	*/
emilmont	27:7110ebee3484	1175	static __INLINE uint32_t ITM_SendChar (uint32_t ch)
emilmont	27:7110ebee3484	1176	{
emilmont	27:7110ebee3484	1177	if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
emilmont	27:7110ebee3484	1178	(ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
emilmont	27:7110ebee3484	1179	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
emilmont	27:7110ebee3484	1180	{
emilmont	27:7110ebee3484	1181	while (ITM->PORT[0].u32 == 0);
emilmont	27:7110ebee3484	1182	ITM->PORT[0].u8 = (uint8_t) ch;
emilmont	27:7110ebee3484	1183	}
emilmont	27:7110ebee3484	1184	return (ch);
emilmont	27:7110ebee3484	1185	}
emilmont	27:7110ebee3484	1186
emilmont	27:7110ebee3484	1187
emilmont	27:7110ebee3484	1188	/** \brief ITM Receive Character
emilmont	27:7110ebee3484	1189
emilmont	27:7110ebee3484	1190	This function inputs a character via external variable ITM_RxBuffer.
emilmont	27:7110ebee3484	1191	It just returns when no debugger is connected that has booked the output.
emilmont	27:7110ebee3484	1192	It is blocking when a debugger is connected, but the previous character send is not transmitted.
emilmont	27:7110ebee3484	1193
emilmont	27:7110ebee3484	1194	\return Received character
emilmont	27:7110ebee3484	1195	\return -1 No character received
emilmont	27:7110ebee3484	1196	*/
emilmont	27:7110ebee3484	1197	static __INLINE int32_t ITM_ReceiveChar (void) {
emilmont	27:7110ebee3484	1198	int32_t ch = -1; /* no character available */
emilmont	27:7110ebee3484	1199
emilmont	27:7110ebee3484	1200	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
emilmont	27:7110ebee3484	1201	ch = ITM_RxBuffer;
emilmont	27:7110ebee3484	1202	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
emilmont	27:7110ebee3484	1203	}
emilmont	27:7110ebee3484	1204
emilmont	27:7110ebee3484	1205	return (ch);
emilmont	27:7110ebee3484	1206	}
emilmont	27:7110ebee3484	1207
emilmont	27:7110ebee3484	1208
emilmont	27:7110ebee3484	1209	/** \brief ITM Check Character
emilmont	27:7110ebee3484	1210
emilmont	27:7110ebee3484	1211	This function checks external variable ITM_RxBuffer whether a character is available or not.
emilmont	27:7110ebee3484	1212	It returns '1' if a character is available and '0' if no character is available.
emilmont	27:7110ebee3484	1213
emilmont	27:7110ebee3484	1214	\return 0 No character available
emilmont	27:7110ebee3484	1215	\return 1 Character available
emilmont	27:7110ebee3484	1216	*/
emilmont	27:7110ebee3484	1217	static __INLINE int32_t ITM_CheckChar (void) {
emilmont	27:7110ebee3484	1218
emilmont	27:7110ebee3484	1219	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
emilmont	27:7110ebee3484	1220	return (0); /* no character available */
emilmont	27:7110ebee3484	1221	} else {
emilmont	27:7110ebee3484	1222	return (1); /* character available */
emilmont	27:7110ebee3484	1223	}
emilmont	27:7110ebee3484	1224	}
emilmont	27:7110ebee3484	1225
emilmont	27:7110ebee3484	1226	/@} end of CMSIS_core_DebugFunctions /
emilmont	27:7110ebee3484	1227
emilmont	27:7110ebee3484	1228	#endif /* __CORE_CM3_H_DEPENDANT */
emilmont	27:7110ebee3484	1229
emilmont	27:7110ebee3484	1230	#endif /* __CMSIS_GENERIC */
emilmont	27:7110ebee3484	1231
emilmont	27:7110ebee3484	1232	#ifdef __cplusplus
emilmont	27:7110ebee3484	1233	}
emilmont	27:7110ebee3484	1234	#endif
emilmont	27:7110ebee3484	1235
emilmont	27:7110ebee3484	1236	/lint -restore /

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Type:	Library
Created:	24 Oct 2012
Imports:	3167
Forks:	4
Commits:	44
Dependents:	17
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Followers:	59

LPC1768/GCC_CR/core_cm3.h@27:7110ebee3484, 2011-11-29 (annotated)

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