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LPC11U24/GCC_CR/core_cm0.h@27:7110ebee3484, 2011-11-29 (annotated)

Committer:
emilmont
Date:
Tue Nov 29 14:59:27 2011 +0000
Revision:
27:7110ebee3484
Child:
31:a7ef757f598c
New Libraries 11.11

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1 /**************************************************************************//**
emilmont 27:7110ebee3484 2 * @file core_cm0.h
emilmont 27:7110ebee3484 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
emilmont 27:7110ebee3484 4 * @version V2.03
emilmont 27:7110ebee3484 5 * @date 23. May 2011
emilmont 27:7110ebee3484 6 *
emilmont 27:7110ebee3484 7 * @note
emilmont 27:7110ebee3484 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
emilmont 27:7110ebee3484 9 *
emilmont 27:7110ebee3484 10 * @par
emilmont 27:7110ebee3484 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 27:7110ebee3484 12 * processor based microcontrollers. This file can be freely distributed
emilmont 27:7110ebee3484 13 * within development tools that are supporting such ARM based processors.
emilmont 27:7110ebee3484 14 *
emilmont 27:7110ebee3484 15 * @par
emilmont 27:7110ebee3484 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 27:7110ebee3484 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 27:7110ebee3484 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 27:7110ebee3484 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 27:7110ebee3484 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 27:7110ebee3484 21 *
emilmont 27:7110ebee3484 22 ******************************************************************************/
emilmont 27:7110ebee3484 23 #if defined ( __ICCARM__ )
emilmont 27:7110ebee3484 24 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 27:7110ebee3484 25 #endif
emilmont 27:7110ebee3484 26
emilmont 27:7110ebee3484 27 #ifdef __cplusplus
emilmont 27:7110ebee3484 28 extern "C" {
emilmont 27:7110ebee3484 29 #endif
emilmont 27:7110ebee3484 30
emilmont 27:7110ebee3484 31 #ifndef __CORE_CM0_H_GENERIC
emilmont 27:7110ebee3484 32 #define __CORE_CM0_H_GENERIC
emilmont 27:7110ebee3484 33
emilmont 27:7110ebee3484 34
emilmont 27:7110ebee3484 35 /** \mainpage CMSIS Cortex-M0
emilmont 27:7110ebee3484 36
emilmont 27:7110ebee3484 37 This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
emilmont 27:7110ebee3484 38 It consists of:
emilmont 27:7110ebee3484 39
emilmont 27:7110ebee3484 40 - Cortex-M Core Register Definitions
emilmont 27:7110ebee3484 41 - Cortex-M functions
emilmont 27:7110ebee3484 42 - Cortex-M instructions
emilmont 27:7110ebee3484 43
emilmont 27:7110ebee3484 44 The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
emilmont 27:7110ebee3484 45 access to the Cortex-M Core
emilmont 27:7110ebee3484 46 */
emilmont 27:7110ebee3484 47
emilmont 27:7110ebee3484 48 /** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
emilmont 27:7110ebee3484 49 List of Lint messages which will be suppressed and not shown:
emilmont 27:7110ebee3484 50 - not yet checked
emilmont 27:7110ebee3484 51 .
emilmont 27:7110ebee3484 52 Note: To re-enable a Message, insert a space before 'lint' *
emilmont 27:7110ebee3484 53
emilmont 27:7110ebee3484 54 */
emilmont 27:7110ebee3484 55
emilmont 27:7110ebee3484 56
emilmont 27:7110ebee3484 57 /*******************************************************************************
emilmont 27:7110ebee3484 58 * CMSIS definitions
emilmont 27:7110ebee3484 59 ******************************************************************************/
emilmont 27:7110ebee3484 60 /** \defgroup CMSIS_core_definitions CMSIS Core Definitions
emilmont 27:7110ebee3484 61 This file defines all structures and symbols for CMSIS core:
emilmont 27:7110ebee3484 62 - CMSIS version number
emilmont 27:7110ebee3484 63 - Cortex-M core
emilmont 27:7110ebee3484 64 - Cortex-M core Revision Number
emilmont 27:7110ebee3484 65 @{
emilmont 27:7110ebee3484 66 */
emilmont 27:7110ebee3484 67
emilmont 27:7110ebee3484 68 /* CMSIS CM0 definitions */
emilmont 27:7110ebee3484 69 #define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
emilmont 27:7110ebee3484 70 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
emilmont 27:7110ebee3484 71 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
emilmont 27:7110ebee3484 72
emilmont 27:7110ebee3484 73 #define __CORTEX_M (0x00) /*!< Cortex core */
emilmont 27:7110ebee3484 74
emilmont 27:7110ebee3484 75
emilmont 27:7110ebee3484 76 #if defined ( __CC_ARM )
emilmont 27:7110ebee3484 77 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 27:7110ebee3484 78 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 27:7110ebee3484 79
emilmont 27:7110ebee3484 80 #elif defined ( __ICCARM__ )
emilmont 27:7110ebee3484 81 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 27:7110ebee3484 82 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 27:7110ebee3484 83
emilmont 27:7110ebee3484 84 #elif defined ( __GNUC__ )
emilmont 27:7110ebee3484 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 27:7110ebee3484 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 27:7110ebee3484 87
emilmont 27:7110ebee3484 88 #elif defined ( __TASKING__ )
emilmont 27:7110ebee3484 89 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 27:7110ebee3484 90 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 27:7110ebee3484 91
emilmont 27:7110ebee3484 92 #endif
emilmont 27:7110ebee3484 93
emilmont 27:7110ebee3484 94 #include <stdint.h> /*!< standard types definitions */
emilmont 27:7110ebee3484 95 #include "core_cmInstr.h" /*!< Core Instruction Access */
emilmont 27:7110ebee3484 96 #include "core_cmFunc.h" /*!< Core Function Access */
emilmont 27:7110ebee3484 97
emilmont 27:7110ebee3484 98 #endif /* __CORE_CM0_H_GENERIC */
emilmont 27:7110ebee3484 99
emilmont 27:7110ebee3484 100
emilmont 27:7110ebee3484 101 #ifndef __CMSIS_GENERIC
emilmont 27:7110ebee3484 102
emilmont 27:7110ebee3484 103 #ifndef __CORE_CM0_H_DEPENDANT
emilmont 27:7110ebee3484 104 #define __CORE_CM0_H_DEPENDANT
emilmont 27:7110ebee3484 105
emilmont 27:7110ebee3484 106 /* IO definitions (access restrictions to peripheral registers) */
emilmont 27:7110ebee3484 107 #ifdef __cplusplus
emilmont 27:7110ebee3484 108 #define __I volatile /*!< defines 'read only' permissions */
emilmont 27:7110ebee3484 109 #else
emilmont 27:7110ebee3484 110 #define __I volatile const /*!< defines 'read only' permissions */
emilmont 27:7110ebee3484 111 #endif
emilmont 27:7110ebee3484 112 #define __O volatile /*!< defines 'write only' permissions */
emilmont 27:7110ebee3484 113 #define __IO volatile /*!< defines 'read / write' permissions */
emilmont 27:7110ebee3484 114
emilmont 27:7110ebee3484 115 /*@} end of group CMSIS_core_definitions */
emilmont 27:7110ebee3484 116
emilmont 27:7110ebee3484 117
emilmont 27:7110ebee3484 118
emilmont 27:7110ebee3484 119 /*******************************************************************************
emilmont 27:7110ebee3484 120 * Register Abstraction
emilmont 27:7110ebee3484 121 ******************************************************************************/
emilmont 27:7110ebee3484 122 /** \defgroup CMSIS_core_register CMSIS Core Register
emilmont 27:7110ebee3484 123 Core Register contain:
emilmont 27:7110ebee3484 124 - Core Register
emilmont 27:7110ebee3484 125 - Core NVIC Register
emilmont 27:7110ebee3484 126 - Core SCB Register
emilmont 27:7110ebee3484 127 - Core SysTick Register
emilmont 27:7110ebee3484 128 */
emilmont 27:7110ebee3484 129
emilmont 27:7110ebee3484 130 /** \ingroup CMSIS_core_register
emilmont 27:7110ebee3484 131 \defgroup CMSIS_CORE CMSIS Core
emilmont 27:7110ebee3484 132 Type definitions for the Cortex-M Core Registers
emilmont 27:7110ebee3484 133 @{
emilmont 27:7110ebee3484 134 */
emilmont 27:7110ebee3484 135
emilmont 27:7110ebee3484 136 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 27:7110ebee3484 137 */
emilmont 27:7110ebee3484 138 typedef union
emilmont 27:7110ebee3484 139 {
emilmont 27:7110ebee3484 140 struct
emilmont 27:7110ebee3484 141 {
emilmont 27:7110ebee3484 142 #if (__CORTEX_M != 0x04)
emilmont 27:7110ebee3484 143 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 27:7110ebee3484 144 #else
emilmont 27:7110ebee3484 145 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 27:7110ebee3484 146 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 27:7110ebee3484 147 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 27:7110ebee3484 148 #endif
emilmont 27:7110ebee3484 149 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 27:7110ebee3484 150 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 27:7110ebee3484 151 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 27:7110ebee3484 152 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 27:7110ebee3484 153 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 27:7110ebee3484 154 } b; /*!< Structure used for bit access */
emilmont 27:7110ebee3484 155 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 156 } APSR_Type;
emilmont 27:7110ebee3484 157
emilmont 27:7110ebee3484 158
emilmont 27:7110ebee3484 159 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 27:7110ebee3484 160 */
emilmont 27:7110ebee3484 161 typedef union
emilmont 27:7110ebee3484 162 {
emilmont 27:7110ebee3484 163 struct
emilmont 27:7110ebee3484 164 {
emilmont 27:7110ebee3484 165 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 27:7110ebee3484 166 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 27:7110ebee3484 167 } b; /*!< Structure used for bit access */
emilmont 27:7110ebee3484 168 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 169 } IPSR_Type;
emilmont 27:7110ebee3484 170
emilmont 27:7110ebee3484 171
emilmont 27:7110ebee3484 172 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 27:7110ebee3484 173 */
emilmont 27:7110ebee3484 174 typedef union
emilmont 27:7110ebee3484 175 {
emilmont 27:7110ebee3484 176 struct
emilmont 27:7110ebee3484 177 {
emilmont 27:7110ebee3484 178 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 27:7110ebee3484 179 #if (__CORTEX_M != 0x04)
emilmont 27:7110ebee3484 180 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 27:7110ebee3484 181 #else
emilmont 27:7110ebee3484 182 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 27:7110ebee3484 183 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 27:7110ebee3484 184 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 27:7110ebee3484 185 #endif
emilmont 27:7110ebee3484 186 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 27:7110ebee3484 187 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 27:7110ebee3484 188 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 27:7110ebee3484 189 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 27:7110ebee3484 190 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 27:7110ebee3484 191 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 27:7110ebee3484 192 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 27:7110ebee3484 193 } b; /*!< Structure used for bit access */
emilmont 27:7110ebee3484 194 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 195 } xPSR_Type;
emilmont 27:7110ebee3484 196
emilmont 27:7110ebee3484 197
emilmont 27:7110ebee3484 198 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 27:7110ebee3484 199 */
emilmont 27:7110ebee3484 200 typedef union
emilmont 27:7110ebee3484 201 {
emilmont 27:7110ebee3484 202 struct
emilmont 27:7110ebee3484 203 {
emilmont 27:7110ebee3484 204 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 27:7110ebee3484 205 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 27:7110ebee3484 206 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 27:7110ebee3484 207 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 27:7110ebee3484 208 } b; /*!< Structure used for bit access */
emilmont 27:7110ebee3484 209 uint32_t w; /*!< Type used for word access */
emilmont 27:7110ebee3484 210 } CONTROL_Type;
emilmont 27:7110ebee3484 211
emilmont 27:7110ebee3484 212 /*@} end of group CMSIS_CORE */
emilmont 27:7110ebee3484 213
emilmont 27:7110ebee3484 214
emilmont 27:7110ebee3484 215 /** \ingroup CMSIS_core_register
emilmont 27:7110ebee3484 216 \defgroup CMSIS_NVIC CMSIS NVIC
emilmont 27:7110ebee3484 217 Type definitions for the Cortex-M NVIC Registers
emilmont 27:7110ebee3484 218 @{
emilmont 27:7110ebee3484 219 */
emilmont 27:7110ebee3484 220
emilmont 27:7110ebee3484 221 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 27:7110ebee3484 222 */
emilmont 27:7110ebee3484 223 typedef struct
emilmont 27:7110ebee3484 224 {
emilmont 27:7110ebee3484 225 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 27:7110ebee3484 226 uint32_t RESERVED0[31];
emilmont 27:7110ebee3484 227 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 27:7110ebee3484 228 uint32_t RSERVED1[31];
emilmont 27:7110ebee3484 229 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 27:7110ebee3484 230 uint32_t RESERVED2[31];
emilmont 27:7110ebee3484 231 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 27:7110ebee3484 232 uint32_t RESERVED3[31];
emilmont 27:7110ebee3484 233 uint32_t RESERVED4[64];
emilmont 27:7110ebee3484 234 __IO uint32_t IPR[8]; /*!< Offset: 0x3EC (R/W) Interrupt Priority Register */
emilmont 27:7110ebee3484 235 } NVIC_Type;
emilmont 27:7110ebee3484 236
emilmont 27:7110ebee3484 237 /*@} end of group CMSIS_NVIC */
emilmont 27:7110ebee3484 238
emilmont 27:7110ebee3484 239
emilmont 27:7110ebee3484 240 /** \ingroup CMSIS_core_register
emilmont 27:7110ebee3484 241 \defgroup CMSIS_SCB CMSIS SCB
emilmont 27:7110ebee3484 242 Type definitions for the Cortex-M System Control Block Registers
emilmont 27:7110ebee3484 243 @{
emilmont 27:7110ebee3484 244 */
emilmont 27:7110ebee3484 245
emilmont 27:7110ebee3484 246 /** \brief Structure type to access the System Control Block (SCB).
emilmont 27:7110ebee3484 247 */
emilmont 27:7110ebee3484 248 typedef struct
emilmont 27:7110ebee3484 249 {
emilmont 27:7110ebee3484 250 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */
emilmont 27:7110ebee3484 251 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */
emilmont 27:7110ebee3484 252 uint32_t RESERVED0;
emilmont 27:7110ebee3484 253 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */
emilmont 27:7110ebee3484 254 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 27:7110ebee3484 255 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 27:7110ebee3484 256 uint32_t RESERVED1;
emilmont 27:7110ebee3484 257 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 27:7110ebee3484 258 } SCB_Type;
emilmont 27:7110ebee3484 259
emilmont 27:7110ebee3484 260 /* SCB CPUID Register Definitions */
emilmont 27:7110ebee3484 261 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 27:7110ebee3484 262 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 27:7110ebee3484 263
emilmont 27:7110ebee3484 264 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 27:7110ebee3484 265 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 27:7110ebee3484 266
emilmont 27:7110ebee3484 267 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 27:7110ebee3484 268 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 27:7110ebee3484 269
emilmont 27:7110ebee3484 270 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 27:7110ebee3484 271 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 27:7110ebee3484 272
emilmont 27:7110ebee3484 273 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emilmont 27:7110ebee3484 274 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emilmont 27:7110ebee3484 275
emilmont 27:7110ebee3484 276 /* SCB Interrupt Control State Register Definitions */
emilmont 27:7110ebee3484 277 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 27:7110ebee3484 278 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 27:7110ebee3484 279
emilmont 27:7110ebee3484 280 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 27:7110ebee3484 281 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 27:7110ebee3484 282
emilmont 27:7110ebee3484 283 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 27:7110ebee3484 284 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 27:7110ebee3484 285
emilmont 27:7110ebee3484 286 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 27:7110ebee3484 287 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 27:7110ebee3484 288
emilmont 27:7110ebee3484 289 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 27:7110ebee3484 290 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 27:7110ebee3484 291
emilmont 27:7110ebee3484 292 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 27:7110ebee3484 293 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 27:7110ebee3484 294
emilmont 27:7110ebee3484 295 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 27:7110ebee3484 296 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 27:7110ebee3484 297
emilmont 27:7110ebee3484 298 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 27:7110ebee3484 299 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 27:7110ebee3484 300
emilmont 27:7110ebee3484 301 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emilmont 27:7110ebee3484 302 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 27:7110ebee3484 303
emilmont 27:7110ebee3484 304 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 27:7110ebee3484 305 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 27:7110ebee3484 306 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 27:7110ebee3484 307
emilmont 27:7110ebee3484 308 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 27:7110ebee3484 309 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 27:7110ebee3484 310
emilmont 27:7110ebee3484 311 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 27:7110ebee3484 312 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 27:7110ebee3484 313
emilmont 27:7110ebee3484 314 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 27:7110ebee3484 315 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 27:7110ebee3484 316
emilmont 27:7110ebee3484 317 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 27:7110ebee3484 318 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 27:7110ebee3484 319
emilmont 27:7110ebee3484 320 /* SCB System Control Register Definitions */
emilmont 27:7110ebee3484 321 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 27:7110ebee3484 322 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 27:7110ebee3484 323
emilmont 27:7110ebee3484 324 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 27:7110ebee3484 325 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 27:7110ebee3484 326
emilmont 27:7110ebee3484 327 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 27:7110ebee3484 328 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 27:7110ebee3484 329
emilmont 27:7110ebee3484 330 /* SCB Configuration Control Register Definitions */
emilmont 27:7110ebee3484 331 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 27:7110ebee3484 332 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 27:7110ebee3484 333
emilmont 27:7110ebee3484 334 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 27:7110ebee3484 335 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 27:7110ebee3484 336
emilmont 27:7110ebee3484 337 /*@} end of group CMSIS_SCB */
emilmont 27:7110ebee3484 338
emilmont 27:7110ebee3484 339
emilmont 27:7110ebee3484 340 /** \ingroup CMSIS_core_register
emilmont 27:7110ebee3484 341 \defgroup CMSIS_SysTick CMSIS SysTick
emilmont 27:7110ebee3484 342 Type definitions for the Cortex-M System Timer Registers
emilmont 27:7110ebee3484 343 @{
emilmont 27:7110ebee3484 344 */
emilmont 27:7110ebee3484 345
emilmont 27:7110ebee3484 346 /** \brief Structure type to access the System Timer (SysTick).
emilmont 27:7110ebee3484 347 */
emilmont 27:7110ebee3484 348 typedef struct
emilmont 27:7110ebee3484 349 {
emilmont 27:7110ebee3484 350 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 27:7110ebee3484 351 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 27:7110ebee3484 352 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 27:7110ebee3484 353 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 27:7110ebee3484 354 } SysTick_Type;
emilmont 27:7110ebee3484 355
emilmont 27:7110ebee3484 356 /* SysTick Control / Status Register Definitions */
emilmont 27:7110ebee3484 357 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 27:7110ebee3484 358 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 27:7110ebee3484 359
emilmont 27:7110ebee3484 360 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 27:7110ebee3484 361 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 27:7110ebee3484 362
emilmont 27:7110ebee3484 363 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 27:7110ebee3484 364 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 27:7110ebee3484 365
emilmont 27:7110ebee3484 366 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emilmont 27:7110ebee3484 367 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emilmont 27:7110ebee3484 368
emilmont 27:7110ebee3484 369 /* SysTick Reload Register Definitions */
emilmont 27:7110ebee3484 370 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emilmont 27:7110ebee3484 371 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emilmont 27:7110ebee3484 372
emilmont 27:7110ebee3484 373 /* SysTick Current Register Definitions */
emilmont 27:7110ebee3484 374 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emilmont 27:7110ebee3484 375 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emilmont 27:7110ebee3484 376
emilmont 27:7110ebee3484 377 /* SysTick Calibration Register Definitions */
emilmont 27:7110ebee3484 378 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 27:7110ebee3484 379 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 27:7110ebee3484 380
emilmont 27:7110ebee3484 381 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 27:7110ebee3484 382 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 27:7110ebee3484 383
emilmont 27:7110ebee3484 384 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emilmont 27:7110ebee3484 385 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
emilmont 27:7110ebee3484 386
emilmont 27:7110ebee3484 387 /*@} end of group CMSIS_SysTick */
emilmont 27:7110ebee3484 388
emilmont 27:7110ebee3484 389
emilmont 27:7110ebee3484 390 /** \ingroup CMSIS_core_register
emilmont 27:7110ebee3484 391 \defgroup CMSIS_CoreDebug CMSIS Core Debug
emilmont 27:7110ebee3484 392 Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
emilmont 27:7110ebee3484 393 and not via processor. Therefore they are not covered by the Cortex-M0 header file.
emilmont 27:7110ebee3484 394 @{
emilmont 27:7110ebee3484 395 */
emilmont 27:7110ebee3484 396
emilmont 27:7110ebee3484 397 /*@} end of group CMSIS_CoreDebug */
emilmont 27:7110ebee3484 398
emilmont 27:7110ebee3484 399
emilmont 27:7110ebee3484 400 /** \ingroup CMSIS_core_register
emilmont 27:7110ebee3484 401 @{
emilmont 27:7110ebee3484 402 */
emilmont 27:7110ebee3484 403
emilmont 27:7110ebee3484 404 /* Memory mapping of Cortex-M0 Hardware */
emilmont 27:7110ebee3484 405 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 27:7110ebee3484 406 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
emilmont 27:7110ebee3484 407 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 27:7110ebee3484 408 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 27:7110ebee3484 409 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 27:7110ebee3484 410
emilmont 27:7110ebee3484 411 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
emilmont 27:7110ebee3484 412 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
emilmont 27:7110ebee3484 413 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
emilmont 27:7110ebee3484 414
emilmont 27:7110ebee3484 415 /*@} */
emilmont 27:7110ebee3484 416
emilmont 27:7110ebee3484 417
emilmont 27:7110ebee3484 418
emilmont 27:7110ebee3484 419 /*******************************************************************************
emilmont 27:7110ebee3484 420 * Hardware Abstraction Layer
emilmont 27:7110ebee3484 421 ******************************************************************************/
emilmont 27:7110ebee3484 422 /** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
emilmont 27:7110ebee3484 423 Core Function Interface contains:
emilmont 27:7110ebee3484 424 - Core NVIC Functions
emilmont 27:7110ebee3484 425 - Core SysTick Functions
emilmont 27:7110ebee3484 426 - Core Register Access Functions
emilmont 27:7110ebee3484 427 */
emilmont 27:7110ebee3484 428
emilmont 27:7110ebee3484 429
emilmont 27:7110ebee3484 430
emilmont 27:7110ebee3484 431 /* ########################## NVIC functions #################################### */
emilmont 27:7110ebee3484 432 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 27:7110ebee3484 433 \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
emilmont 27:7110ebee3484 434 @{
emilmont 27:7110ebee3484 435 */
emilmont 27:7110ebee3484 436
emilmont 27:7110ebee3484 437 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 27:7110ebee3484 438 /* The following MACROS handle generation of the register offset and byte masks */
emilmont 27:7110ebee3484 439 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
emilmont 27:7110ebee3484 440 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
emilmont 27:7110ebee3484 441 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
emilmont 27:7110ebee3484 442
emilmont 27:7110ebee3484 443
emilmont 27:7110ebee3484 444 /** \brief Enable External Interrupt
emilmont 27:7110ebee3484 445
emilmont 27:7110ebee3484 446 This function enables a device specific interrupt in the NVIC interrupt controller.
emilmont 27:7110ebee3484 447 The interrupt number cannot be a negative value.
emilmont 27:7110ebee3484 448
emilmont 27:7110ebee3484 449 \param [in] IRQn Number of the external interrupt to enable
emilmont 27:7110ebee3484 450 */
emilmont 27:7110ebee3484 451 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 452 {
emilmont 27:7110ebee3484 453 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 27:7110ebee3484 454 }
emilmont 27:7110ebee3484 455
emilmont 27:7110ebee3484 456
emilmont 27:7110ebee3484 457 /** \brief Disable External Interrupt
emilmont 27:7110ebee3484 458
emilmont 27:7110ebee3484 459 This function disables a device specific interupt in the NVIC interrupt controller.
emilmont 27:7110ebee3484 460 The interrupt number cannot be a negative value.
emilmont 27:7110ebee3484 461
emilmont 27:7110ebee3484 462 \param [in] IRQn Number of the external interrupt to disable
emilmont 27:7110ebee3484 463 */
emilmont 27:7110ebee3484 464 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 465 {
emilmont 27:7110ebee3484 466 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 27:7110ebee3484 467 }
emilmont 27:7110ebee3484 468
emilmont 27:7110ebee3484 469
emilmont 27:7110ebee3484 470 /** \brief Get Pending Interrupt
emilmont 27:7110ebee3484 471
emilmont 27:7110ebee3484 472 This function reads the pending register in the NVIC and returns the pending bit
emilmont 27:7110ebee3484 473 for the specified interrupt.
emilmont 27:7110ebee3484 474
emilmont 27:7110ebee3484 475 \param [in] IRQn Number of the interrupt for get pending
emilmont 27:7110ebee3484 476 \return 0 Interrupt status is not pending
emilmont 27:7110ebee3484 477 \return 1 Interrupt status is pending
emilmont 27:7110ebee3484 478 */
emilmont 27:7110ebee3484 479 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 480 {
emilmont 27:7110ebee3484 481 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
emilmont 27:7110ebee3484 482 }
emilmont 27:7110ebee3484 483
emilmont 27:7110ebee3484 484
emilmont 27:7110ebee3484 485 /** \brief Set Pending Interrupt
emilmont 27:7110ebee3484 486
emilmont 27:7110ebee3484 487 This function sets the pending bit for the specified interrupt.
emilmont 27:7110ebee3484 488 The interrupt number cannot be a negative value.
emilmont 27:7110ebee3484 489
emilmont 27:7110ebee3484 490 \param [in] IRQn Number of the interrupt for set pending
emilmont 27:7110ebee3484 491 */
emilmont 27:7110ebee3484 492 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 493 {
emilmont 27:7110ebee3484 494 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 27:7110ebee3484 495 }
emilmont 27:7110ebee3484 496
emilmont 27:7110ebee3484 497
emilmont 27:7110ebee3484 498 /** \brief Clear Pending Interrupt
emilmont 27:7110ebee3484 499
emilmont 27:7110ebee3484 500 This function clears the pending bit for the specified interrupt.
emilmont 27:7110ebee3484 501 The interrupt number cannot be a negative value.
emilmont 27:7110ebee3484 502
emilmont 27:7110ebee3484 503 \param [in] IRQn Number of the interrupt for clear pending
emilmont 27:7110ebee3484 504 */
emilmont 27:7110ebee3484 505 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 27:7110ebee3484 506 {
emilmont 27:7110ebee3484 507 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont 27:7110ebee3484 508 }
emilmont 27:7110ebee3484 509
emilmont 27:7110ebee3484 510
emilmont 27:7110ebee3484 511 /** \brief Set Interrupt Priority
emilmont 27:7110ebee3484 512
emilmont 27:7110ebee3484 513 This function sets the priority for the specified interrupt. The interrupt
emilmont 27:7110ebee3484 514 number can be positive to specify an external (device specific)
emilmont 27:7110ebee3484 515 interrupt, or negative to specify an internal (core) interrupt.
emilmont 27:7110ebee3484 516
emilmont 27:7110ebee3484 517 Note: The priority cannot be set for every core interrupt.
emilmont 27:7110ebee3484 518
emilmont 27:7110ebee3484 519 \param [in] IRQn Number of the interrupt for set priority
emilmont 27:7110ebee3484 520 \param [in] priority Priority to set
emilmont 27:7110ebee3484 521 */
emilmont 27:7110ebee3484 522 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 27:7110ebee3484 523 {
emilmont 27:7110ebee3484 524 if(IRQn < 0) {
emilmont 27:7110ebee3484 525 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 27:7110ebee3484 526 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 27:7110ebee3484 527 else {
emilmont 27:7110ebee3484 528 NVIC->IPR[_IP_IDX(IRQn)] = (NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 27:7110ebee3484 529 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 27:7110ebee3484 530 }
emilmont 27:7110ebee3484 531
emilmont 27:7110ebee3484 532
emilmont 27:7110ebee3484 533 /** \brief Get Interrupt Priority
emilmont 27:7110ebee3484 534
emilmont 27:7110ebee3484 535 This function reads the priority for the specified interrupt. The interrupt
emilmont 27:7110ebee3484 536 number can be positive to specify an external (device specific)
emilmont 27:7110ebee3484 537 interrupt, or negative to specify an internal (core) interrupt.
emilmont 27:7110ebee3484 538
emilmont 27:7110ebee3484 539 The returned priority value is automatically aligned to the implemented
emilmont 27:7110ebee3484 540 priority bits of the microcontroller.
emilmont 27:7110ebee3484 541
emilmont 27:7110ebee3484 542 \param [in] IRQn Number of the interrupt for get priority
emilmont 27:7110ebee3484 543 \return Interrupt Priority
emilmont 27:7110ebee3484 544 */
emilmont 27:7110ebee3484 545 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 27:7110ebee3484 546 {
emilmont 27:7110ebee3484 547
emilmont 27:7110ebee3484 548 if(IRQn < 0) {
emilmont 27:7110ebee3484 549 return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
emilmont 27:7110ebee3484 550 else {
emilmont 27:7110ebee3484 551 return((uint32_t)((NVIC->IPR[_IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont 27:7110ebee3484 552 }
emilmont 27:7110ebee3484 553
emilmont 27:7110ebee3484 554
emilmont 27:7110ebee3484 555 /** \brief System Reset
emilmont 27:7110ebee3484 556
emilmont 27:7110ebee3484 557 This function initiate a system reset request to reset the MCU.
emilmont 27:7110ebee3484 558 */
emilmont 27:7110ebee3484 559 static __INLINE void NVIC_SystemReset(void)
emilmont 27:7110ebee3484 560 {
emilmont 27:7110ebee3484 561 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 27:7110ebee3484 562 buffered write are completed before reset */
emilmont 27:7110ebee3484 563 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 27:7110ebee3484 564 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 27:7110ebee3484 565 __DSB(); /* Ensure completion of memory access */
emilmont 27:7110ebee3484 566 while(1); /* wait until reset */
emilmont 27:7110ebee3484 567 }
emilmont 27:7110ebee3484 568
emilmont 27:7110ebee3484 569 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 27:7110ebee3484 570
emilmont 27:7110ebee3484 571
emilmont 27:7110ebee3484 572
emilmont 27:7110ebee3484 573 /* ################################## SysTick function ############################################ */
emilmont 27:7110ebee3484 574 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 27:7110ebee3484 575 \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
emilmont 27:7110ebee3484 576 @{
emilmont 27:7110ebee3484 577 */
emilmont 27:7110ebee3484 578
emilmont 27:7110ebee3484 579 #if (__Vendor_SysTickConfig == 0)
emilmont 27:7110ebee3484 580
emilmont 27:7110ebee3484 581 /** \brief System Tick Configuration
emilmont 27:7110ebee3484 582
emilmont 27:7110ebee3484 583 This function initialises the system tick timer and its interrupt and start the system tick timer.
emilmont 27:7110ebee3484 584 Counter is in free running mode to generate periodical interrupts.
emilmont 27:7110ebee3484 585
emilmont 27:7110ebee3484 586 \param [in] ticks Number of ticks between two interrupts
emilmont 27:7110ebee3484 587 \return 0 Function succeeded
emilmont 27:7110ebee3484 588 \return 1 Function failed
emilmont 27:7110ebee3484 589 */
emilmont 27:7110ebee3484 590 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 27:7110ebee3484 591 {
emilmont 27:7110ebee3484 592 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont 27:7110ebee3484 593
emilmont 27:7110ebee3484 594 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
emilmont 27:7110ebee3484 595 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
emilmont 27:7110ebee3484 596 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont 27:7110ebee3484 597 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 27:7110ebee3484 598 SysTick_CTRL_TICKINT_Msk |
emilmont 27:7110ebee3484 599 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont 27:7110ebee3484 600 return (0); /* Function successful */
emilmont 27:7110ebee3484 601 }
emilmont 27:7110ebee3484 602
emilmont 27:7110ebee3484 603 #endif
emilmont 27:7110ebee3484 604
emilmont 27:7110ebee3484 605 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 27:7110ebee3484 606
emilmont 27:7110ebee3484 607
emilmont 27:7110ebee3484 608
emilmont 27:7110ebee3484 609
emilmont 27:7110ebee3484 610 #endif /* __CORE_CM0_H_DEPENDANT */
emilmont 27:7110ebee3484 611
emilmont 27:7110ebee3484 612 #endif /* __CMSIS_GENERIC */
emilmont 27:7110ebee3484 613
emilmont 27:7110ebee3484 614 #ifdef __cplusplus
emilmont 27:7110ebee3484 615 }
emilmont 27:7110ebee3484 616 #endif
emilmont 27:7110ebee3484 617
emilmont 27:7110ebee3484 618 /*lint -restore */