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LPC1768/GCC_ARM/core_cm3.h@33:5364839841bd, 2012-01-10 (annotated)

Committer:: emilmont
Date:: Tue Jan 10 12:00:50 2012 +0000
Revision:: 33:5364839841bd
Parent:: 27:7110ebee3484

[10 January 2012] CAN::attach template. CMSIS updates.

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	27:7110ebee3484	1	/************************************************************************//
emilmont	27:7110ebee3484	2	* @file core_cm3.h
emilmont	27:7110ebee3484	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
emilmont	33:5364839841bd	4	* @version V3.00
emilmont	33:5364839841bd	5	* @date 09. December 2011
emilmont	27:7110ebee3484	6	*
emilmont	27:7110ebee3484	7	* @note
emilmont	33:5364839841bd	8	* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
emilmont	27:7110ebee3484	9	*
emilmont	27:7110ebee3484	10	* @par
emilmont	33:5364839841bd	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont	33:5364839841bd	12	* processor based microcontrollers. This file can be freely distributed
emilmont	33:5364839841bd	13	* within development tools that are supporting such ARM based processors.
emilmont	27:7110ebee3484	14	*
emilmont	27:7110ebee3484	15	* @par
emilmont	27:7110ebee3484	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont	27:7110ebee3484	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont	27:7110ebee3484	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont	27:7110ebee3484	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont	27:7110ebee3484	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont	27:7110ebee3484	21	*
emilmont	27:7110ebee3484	22	******************************************************************************/
emilmont	33:5364839841bd	23	#if defined ( __ICCARM__ )
emilmont	27:7110ebee3484	24	#pragma system_include /* treat file as system include file for MISRA check */
emilmont	27:7110ebee3484	25	#endif
emilmont	27:7110ebee3484	26
emilmont	27:7110ebee3484	27	#ifdef __cplusplus
emilmont	27:7110ebee3484	28	extern "C" {
emilmont	33:5364839841bd	29	#endif
emilmont	27:7110ebee3484	30
emilmont	27:7110ebee3484	31	#ifndef __CORE_CM3_H_GENERIC
emilmont	27:7110ebee3484	32	#define __CORE_CM3_H_GENERIC
emilmont	27:7110ebee3484	33
emilmont	33:5364839841bd	34	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont	33:5364839841bd	35	CMSIS violates the following MISRA-C:2004 rules:
emilmont	33:5364839841bd	36
emilmont	33:5364839841bd	37	\li Required Rule 8.5, object/function definition in header file.<br>
emilmont	33:5364839841bd	38	Function definitions in header files are used to allow 'inlining'.
emilmont	27:7110ebee3484	39
emilmont	33:5364839841bd	40	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont	33:5364839841bd	41	Unions are used for effective representation of core registers.
emilmont	27:7110ebee3484	42
emilmont	33:5364839841bd	43	\li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont	33:5364839841bd	44	Function-like macros are used to allow more efficient code.
emilmont	27:7110ebee3484	45	*/
emilmont	27:7110ebee3484	46
emilmont	27:7110ebee3484	47
emilmont	27:7110ebee3484	48	/*******************************************************************************
emilmont	27:7110ebee3484	49	* CMSIS definitions
emilmont	27:7110ebee3484	50	******************************************************************************/
emilmont	33:5364839841bd	51	/** \ingroup Cortex_M3
emilmont	27:7110ebee3484	52	@{
emilmont	27:7110ebee3484	53	*/
emilmont	27:7110ebee3484	54
emilmont	27:7110ebee3484	55	/* CMSIS CM3 definitions */
emilmont	33:5364839841bd	56	#define __CM3_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
emilmont	33:5364839841bd	57	#define __CM3_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
emilmont	33:5364839841bd	58	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
emilmont	33:5364839841bd	59	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
emilmont	27:7110ebee3484	60
emilmont	33:5364839841bd	61	#define __CORTEX_M (0x03) /!< Cortex-M Core /
emilmont	27:7110ebee3484	62
emilmont	27:7110ebee3484	63
emilmont	33:5364839841bd	64	#if defined ( __CC_ARM )
emilmont	27:7110ebee3484	65	#define __ASM __asm /!< asm keyword for ARM Compiler /
emilmont	27:7110ebee3484	66	#define __INLINE __inline /!< inline keyword for ARM Compiler /
emilmont	27:7110ebee3484	67
emilmont	27:7110ebee3484	68	#elif defined ( __ICCARM__ )
emilmont	27:7110ebee3484	69	#define __ASM __asm /!< asm keyword for IAR Compiler /
emilmont	33:5364839841bd	70	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
emilmont	27:7110ebee3484	71
emilmont	33:5364839841bd	72	#elif defined ( __GNUC__ )
emilmont	27:7110ebee3484	73	#define __ASM __asm /!< asm keyword for GNU Compiler /
emilmont	27:7110ebee3484	74	#define __INLINE inline /!< inline keyword for GNU Compiler /
emilmont	27:7110ebee3484	75
emilmont	33:5364839841bd	76	#elif defined ( __TASKING__ )
emilmont	27:7110ebee3484	77	#define __ASM __asm /!< asm keyword for TASKING Compiler /
emilmont	27:7110ebee3484	78	#define __INLINE inline /!< inline keyword for TASKING Compiler /
emilmont	27:7110ebee3484	79
emilmont	27:7110ebee3484	80	#endif
emilmont	27:7110ebee3484	81
emilmont	33:5364839841bd	82	/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont	33:5364839841bd	83	*/
emilmont	33:5364839841bd	84	#define __FPU_USED 0
emilmont	33:5364839841bd	85
emilmont	33:5364839841bd	86	#if defined ( __CC_ARM )
emilmont	33:5364839841bd	87	#if defined __TARGET_FPU_VFP
emilmont	33:5364839841bd	88	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	33:5364839841bd	89	#endif
emilmont	33:5364839841bd	90
emilmont	33:5364839841bd	91	#elif defined ( __ICCARM__ )
emilmont	33:5364839841bd	92	#if defined __ARMVFP__
emilmont	33:5364839841bd	93	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	33:5364839841bd	94	#endif
emilmont	33:5364839841bd	95
emilmont	33:5364839841bd	96	#elif defined ( __GNUC__ )
emilmont	33:5364839841bd	97	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont	33:5364839841bd	98	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont	33:5364839841bd	99	#endif
emilmont	33:5364839841bd	100
emilmont	33:5364839841bd	101	#elif defined ( __TASKING__ )
emilmont	33:5364839841bd	102	/* add preprocessor checks */
emilmont	33:5364839841bd	103	#endif
emilmont	33:5364839841bd	104
emilmont	33:5364839841bd	105	#include <stdint.h> /* standard types definitions */
emilmont	33:5364839841bd	106	#include <core_cmInstr.h> /* Core Instruction Access */
emilmont	33:5364839841bd	107	#include <core_cmFunc.h> /* Core Function Access */
emilmont	27:7110ebee3484	108
emilmont	27:7110ebee3484	109	#endif /* __CORE_CM3_H_GENERIC */
emilmont	27:7110ebee3484	110
emilmont	27:7110ebee3484	111	#ifndef __CMSIS_GENERIC
emilmont	27:7110ebee3484	112
emilmont	27:7110ebee3484	113	#ifndef __CORE_CM3_H_DEPENDANT
emilmont	27:7110ebee3484	114	#define __CORE_CM3_H_DEPENDANT
emilmont	27:7110ebee3484	115
emilmont	33:5364839841bd	116	/* check device defines and use defaults */
emilmont	33:5364839841bd	117	#if defined __CHECK_DEVICE_DEFINES
emilmont	33:5364839841bd	118	#ifndef __CM3_REV
emilmont	33:5364839841bd	119	#define __CM3_REV 0x0200
emilmont	33:5364839841bd	120	#warning "__CM3_REV not defined in device header file; using default!"
emilmont	33:5364839841bd	121	#endif
emilmont	33:5364839841bd	122
emilmont	33:5364839841bd	123	#ifndef __MPU_PRESENT
emilmont	33:5364839841bd	124	#define __MPU_PRESENT 0
emilmont	33:5364839841bd	125	#warning "__MPU_PRESENT not defined in device header file; using default!"
emilmont	33:5364839841bd	126	#endif
emilmont	33:5364839841bd	127
emilmont	33:5364839841bd	128	#ifndef __NVIC_PRIO_BITS
emilmont	33:5364839841bd	129	#define __NVIC_PRIO_BITS 4
emilmont	33:5364839841bd	130	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont	33:5364839841bd	131	#endif
emilmont	33:5364839841bd	132
emilmont	33:5364839841bd	133	#ifndef __Vendor_SysTickConfig
emilmont	33:5364839841bd	134	#define __Vendor_SysTickConfig 0
emilmont	33:5364839841bd	135	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont	33:5364839841bd	136	#endif
emilmont	33:5364839841bd	137	#endif
emilmont	33:5364839841bd	138
emilmont	27:7110ebee3484	139	/* IO definitions (access restrictions to peripheral registers) */
emilmont	33:5364839841bd	140	/**
emilmont	33:5364839841bd	141	\defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont	33:5364839841bd	142
emilmont	33:5364839841bd	143	<strong>IO Type Qualifiers</strong> are used
emilmont	33:5364839841bd	144	\li to specify the access to peripheral variables.
emilmont	33:5364839841bd	145	\li for automatic generation of peripheral register debug information.
emilmont	33:5364839841bd	146	*/
emilmont	27:7110ebee3484	147	#ifdef __cplusplus
emilmont	33:5364839841bd	148	#define __I volatile /!< Defines 'read only' permissions /
emilmont	27:7110ebee3484	149	#else
emilmont	33:5364839841bd	150	#define __I volatile const /!< Defines 'read only' permissions /
emilmont	27:7110ebee3484	151	#endif
emilmont	33:5364839841bd	152	#define __O volatile /!< Defines 'write only' permissions /
emilmont	33:5364839841bd	153	#define __IO volatile /!< Defines 'read / write' permissions /
emilmont	27:7110ebee3484	154
emilmont	33:5364839841bd	155	/@} end of group Cortex_M3 /
emilmont	27:7110ebee3484	156
emilmont	27:7110ebee3484	157
emilmont	27:7110ebee3484	158
emilmont	27:7110ebee3484	159	/*******************************************************************************
emilmont	27:7110ebee3484	160	* Register Abstraction
emilmont	27:7110ebee3484	161	Core Register contain:
emilmont	27:7110ebee3484	162	- Core Register
emilmont	27:7110ebee3484	163	- Core NVIC Register
emilmont	27:7110ebee3484	164	- Core SCB Register
emilmont	27:7110ebee3484	165	- Core SysTick Register
emilmont	27:7110ebee3484	166	- Core Debug Register
emilmont	27:7110ebee3484	167	- Core MPU Register
emilmont	33:5364839841bd	168	******************************************************************************/
emilmont	33:5364839841bd	169	/** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont	33:5364839841bd	170	\brief Type definitions and defines for Cortex-M processor based devices.
emilmont	27:7110ebee3484	171	*/
emilmont	27:7110ebee3484	172
emilmont	33:5364839841bd	173	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	174	\defgroup CMSIS_CORE Status and Control Registers
emilmont	33:5364839841bd	175	\brief Core Register type definitions.
emilmont	27:7110ebee3484	176	@{
emilmont	27:7110ebee3484	177	*/
emilmont	27:7110ebee3484	178
emilmont	27:7110ebee3484	179	/** \brief Union type to access the Application Program Status Register (APSR).
emilmont	27:7110ebee3484	180	*/
emilmont	27:7110ebee3484	181	typedef union
emilmont	27:7110ebee3484	182	{
emilmont	27:7110ebee3484	183	struct
emilmont	27:7110ebee3484	184	{
emilmont	27:7110ebee3484	185	#if (__CORTEX_M != 0x04)
emilmont	27:7110ebee3484	186	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
emilmont	27:7110ebee3484	187	#else
emilmont	27:7110ebee3484	188	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
emilmont	27:7110ebee3484	189	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
emilmont	27:7110ebee3484	190	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
emilmont	27:7110ebee3484	191	#endif
emilmont	27:7110ebee3484	192	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	27:7110ebee3484	193	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	27:7110ebee3484	194	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	27:7110ebee3484	195	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	27:7110ebee3484	196	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	27:7110ebee3484	197	} b; /!< Structure used for bit access /
emilmont	33:5364839841bd	198	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	199	} APSR_Type;
emilmont	27:7110ebee3484	200
emilmont	27:7110ebee3484	201
emilmont	27:7110ebee3484	202	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont	27:7110ebee3484	203	*/
emilmont	27:7110ebee3484	204	typedef union
emilmont	27:7110ebee3484	205	{
emilmont	27:7110ebee3484	206	struct
emilmont	27:7110ebee3484	207	{
emilmont	27:7110ebee3484	208	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	27:7110ebee3484	209	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
emilmont	27:7110ebee3484	210	} b; /!< Structure used for bit access /
emilmont	27:7110ebee3484	211	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	212	} IPSR_Type;
emilmont	27:7110ebee3484	213
emilmont	27:7110ebee3484	214
emilmont	27:7110ebee3484	215	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont	27:7110ebee3484	216	*/
emilmont	27:7110ebee3484	217	typedef union
emilmont	27:7110ebee3484	218	{
emilmont	27:7110ebee3484	219	struct
emilmont	27:7110ebee3484	220	{
emilmont	27:7110ebee3484	221	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
emilmont	27:7110ebee3484	222	#if (__CORTEX_M != 0x04)
emilmont	27:7110ebee3484	223	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
emilmont	27:7110ebee3484	224	#else
emilmont	27:7110ebee3484	225	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
emilmont	27:7110ebee3484	226	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
emilmont	27:7110ebee3484	227	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
emilmont	27:7110ebee3484	228	#endif
emilmont	27:7110ebee3484	229	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
emilmont	27:7110ebee3484	230	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
emilmont	27:7110ebee3484	231	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
emilmont	27:7110ebee3484	232	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
emilmont	27:7110ebee3484	233	uint32_t C:1; /!< bit: 29 Carry condition code flag /
emilmont	27:7110ebee3484	234	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
emilmont	27:7110ebee3484	235	uint32_t N:1; /!< bit: 31 Negative condition code flag /
emilmont	27:7110ebee3484	236	} b; /!< Structure used for bit access /
emilmont	27:7110ebee3484	237	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	238	} xPSR_Type;
emilmont	27:7110ebee3484	239
emilmont	27:7110ebee3484	240
emilmont	27:7110ebee3484	241	/** \brief Union type to access the Control Registers (CONTROL).
emilmont	27:7110ebee3484	242	*/
emilmont	27:7110ebee3484	243	typedef union
emilmont	27:7110ebee3484	244	{
emilmont	27:7110ebee3484	245	struct
emilmont	27:7110ebee3484	246	{
emilmont	27:7110ebee3484	247	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
emilmont	27:7110ebee3484	248	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
emilmont	27:7110ebee3484	249	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
emilmont	27:7110ebee3484	250	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
emilmont	27:7110ebee3484	251	} b; /!< Structure used for bit access /
emilmont	27:7110ebee3484	252	uint32_t w; /!< Type used for word access /
emilmont	27:7110ebee3484	253	} CONTROL_Type;
emilmont	27:7110ebee3484	254
emilmont	27:7110ebee3484	255	/@} end of group CMSIS_CORE /
emilmont	27:7110ebee3484	256
emilmont	27:7110ebee3484	257
emilmont	33:5364839841bd	258	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	259	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont	33:5364839841bd	260	\brief Type definitions for the NVIC Registers
emilmont	27:7110ebee3484	261	@{
emilmont	27:7110ebee3484	262	*/
emilmont	27:7110ebee3484	263
emilmont	27:7110ebee3484	264	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont	27:7110ebee3484	265	*/
emilmont	27:7110ebee3484	266	typedef struct
emilmont	27:7110ebee3484	267	{
emilmont	27:7110ebee3484	268	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
emilmont	33:5364839841bd	269	uint32_t RESERVED0[24];
emilmont	27:7110ebee3484	270	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
emilmont	33:5364839841bd	271	uint32_t RSERVED1[24];
emilmont	27:7110ebee3484	272	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
emilmont	33:5364839841bd	273	uint32_t RESERVED2[24];
emilmont	27:7110ebee3484	274	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
emilmont	33:5364839841bd	275	uint32_t RESERVED3[24];
emilmont	27:7110ebee3484	276	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
emilmont	33:5364839841bd	277	uint32_t RESERVED4[56];
emilmont	27:7110ebee3484	278	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
emilmont	33:5364839841bd	279	uint32_t RESERVED5[644];
emilmont	27:7110ebee3484	280	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
emilmont	33:5364839841bd	281	} NVIC_Type;
emilmont	33:5364839841bd	282
emilmont	33:5364839841bd	283	/* Software Triggered Interrupt Register Definitions */
emilmont	33:5364839841bd	284	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
emilmont	33:5364839841bd	285	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
emilmont	27:7110ebee3484	286
emilmont	27:7110ebee3484	287	/@} end of group CMSIS_NVIC /
emilmont	27:7110ebee3484	288
emilmont	27:7110ebee3484	289
emilmont	33:5364839841bd	290	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	291	\defgroup CMSIS_SCB System Control Block (SCB)
emilmont	33:5364839841bd	292	\brief Type definitions for the System Control Block Registers
emilmont	27:7110ebee3484	293	@{
emilmont	27:7110ebee3484	294	*/
emilmont	27:7110ebee3484	295
emilmont	27:7110ebee3484	296	/** \brief Structure type to access the System Control Block (SCB).
emilmont	27:7110ebee3484	297	*/
emilmont	27:7110ebee3484	298	typedef struct
emilmont	27:7110ebee3484	299	{
emilmont	33:5364839841bd	300	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
emilmont	33:5364839841bd	301	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
emilmont	27:7110ebee3484	302	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
emilmont	33:5364839841bd	303	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
emilmont	27:7110ebee3484	304	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
emilmont	27:7110ebee3484	305	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
emilmont	27:7110ebee3484	306	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
emilmont	27:7110ebee3484	307	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
emilmont	27:7110ebee3484	308	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
emilmont	33:5364839841bd	309	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
emilmont	27:7110ebee3484	310	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
emilmont	33:5364839841bd	311	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
emilmont	33:5364839841bd	312	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
emilmont	27:7110ebee3484	313	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
emilmont	27:7110ebee3484	314	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
emilmont	27:7110ebee3484	315	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
emilmont	27:7110ebee3484	316	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
emilmont	27:7110ebee3484	317	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
emilmont	33:5364839841bd	318	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
emilmont	33:5364839841bd	319	uint32_t RESERVED0[5];
emilmont	33:5364839841bd	320	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
emilmont	33:5364839841bd	321	} SCB_Type;
emilmont	27:7110ebee3484	322
emilmont	27:7110ebee3484	323	/* SCB CPUID Register Definitions */
emilmont	27:7110ebee3484	324	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
emilmont	27:7110ebee3484	325	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
emilmont	27:7110ebee3484	326
emilmont	27:7110ebee3484	327	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
emilmont	27:7110ebee3484	328	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
emilmont	27:7110ebee3484	329
emilmont	33:5364839841bd	330	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
emilmont	33:5364839841bd	331	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
emilmont	33:5364839841bd	332
emilmont	27:7110ebee3484	333	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
emilmont	27:7110ebee3484	334	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
emilmont	27:7110ebee3484	335
emilmont	27:7110ebee3484	336	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
emilmont	27:7110ebee3484	337	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
emilmont	27:7110ebee3484	338
emilmont	27:7110ebee3484	339	/* SCB Interrupt Control State Register Definitions */
emilmont	27:7110ebee3484	340	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
emilmont	27:7110ebee3484	341	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
emilmont	27:7110ebee3484	342
emilmont	27:7110ebee3484	343	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
emilmont	27:7110ebee3484	344	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
emilmont	27:7110ebee3484	345
emilmont	27:7110ebee3484	346	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
emilmont	27:7110ebee3484	347	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
emilmont	27:7110ebee3484	348
emilmont	27:7110ebee3484	349	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
emilmont	27:7110ebee3484	350	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
emilmont	27:7110ebee3484	351
emilmont	27:7110ebee3484	352	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
emilmont	27:7110ebee3484	353	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
emilmont	27:7110ebee3484	354
emilmont	27:7110ebee3484	355	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
emilmont	27:7110ebee3484	356	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
emilmont	27:7110ebee3484	357
emilmont	27:7110ebee3484	358	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
emilmont	27:7110ebee3484	359	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
emilmont	27:7110ebee3484	360
emilmont	27:7110ebee3484	361	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
emilmont	27:7110ebee3484	362	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
emilmont	27:7110ebee3484	363
emilmont	27:7110ebee3484	364	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
emilmont	27:7110ebee3484	365	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
emilmont	27:7110ebee3484	366
emilmont	27:7110ebee3484	367	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
emilmont	27:7110ebee3484	368	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
emilmont	27:7110ebee3484	369
emilmont	33:5364839841bd	370	/* SCB Vector Table Offset Register Definitions */
emilmont	33:5364839841bd	371	#if (__CM3_REV < 0x0201) /* core r2p1 */
emilmont	27:7110ebee3484	372	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
emilmont	27:7110ebee3484	373	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
emilmont	27:7110ebee3484	374
emilmont	27:7110ebee3484	375	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
emilmont	27:7110ebee3484	376	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
emilmont	33:5364839841bd	377	#else
emilmont	33:5364839841bd	378	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
emilmont	33:5364839841bd	379	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
emilmont	33:5364839841bd	380	#endif
emilmont	27:7110ebee3484	381
emilmont	27:7110ebee3484	382	/* SCB Application Interrupt and Reset Control Register Definitions */
emilmont	27:7110ebee3484	383	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
emilmont	27:7110ebee3484	384	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
emilmont	27:7110ebee3484	385
emilmont	27:7110ebee3484	386	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
emilmont	27:7110ebee3484	387	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
emilmont	27:7110ebee3484	388
emilmont	27:7110ebee3484	389	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
emilmont	27:7110ebee3484	390	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
emilmont	27:7110ebee3484	391
emilmont	27:7110ebee3484	392	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
emilmont	27:7110ebee3484	393	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
emilmont	27:7110ebee3484	394
emilmont	27:7110ebee3484	395	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
emilmont	27:7110ebee3484	396	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
emilmont	27:7110ebee3484	397
emilmont	27:7110ebee3484	398	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
emilmont	27:7110ebee3484	399	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
emilmont	27:7110ebee3484	400
emilmont	27:7110ebee3484	401	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
emilmont	27:7110ebee3484	402	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
emilmont	27:7110ebee3484	403
emilmont	27:7110ebee3484	404	/* SCB System Control Register Definitions */
emilmont	27:7110ebee3484	405	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
emilmont	27:7110ebee3484	406	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
emilmont	27:7110ebee3484	407
emilmont	27:7110ebee3484	408	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
emilmont	27:7110ebee3484	409	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
emilmont	27:7110ebee3484	410
emilmont	27:7110ebee3484	411	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
emilmont	27:7110ebee3484	412	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
emilmont	27:7110ebee3484	413
emilmont	27:7110ebee3484	414	/* SCB Configuration Control Register Definitions */
emilmont	27:7110ebee3484	415	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
emilmont	27:7110ebee3484	416	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
emilmont	27:7110ebee3484	417
emilmont	27:7110ebee3484	418	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
emilmont	27:7110ebee3484	419	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
emilmont	27:7110ebee3484	420
emilmont	27:7110ebee3484	421	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
emilmont	27:7110ebee3484	422	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
emilmont	27:7110ebee3484	423
emilmont	27:7110ebee3484	424	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
emilmont	27:7110ebee3484	425	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
emilmont	27:7110ebee3484	426
emilmont	27:7110ebee3484	427	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
emilmont	27:7110ebee3484	428	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
emilmont	27:7110ebee3484	429
emilmont	27:7110ebee3484	430	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
emilmont	27:7110ebee3484	431	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
emilmont	27:7110ebee3484	432
emilmont	27:7110ebee3484	433	/* SCB System Handler Control and State Register Definitions */
emilmont	27:7110ebee3484	434	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
emilmont	27:7110ebee3484	435	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
emilmont	27:7110ebee3484	436
emilmont	27:7110ebee3484	437	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
emilmont	27:7110ebee3484	438	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
emilmont	27:7110ebee3484	439
emilmont	27:7110ebee3484	440	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
emilmont	27:7110ebee3484	441	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
emilmont	27:7110ebee3484	442
emilmont	27:7110ebee3484	443	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
emilmont	27:7110ebee3484	444	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
emilmont	27:7110ebee3484	445
emilmont	27:7110ebee3484	446	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
emilmont	27:7110ebee3484	447	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
emilmont	27:7110ebee3484	448
emilmont	27:7110ebee3484	449	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
emilmont	27:7110ebee3484	450	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
emilmont	27:7110ebee3484	451
emilmont	27:7110ebee3484	452	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
emilmont	27:7110ebee3484	453	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
emilmont	27:7110ebee3484	454
emilmont	27:7110ebee3484	455	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
emilmont	27:7110ebee3484	456	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
emilmont	27:7110ebee3484	457
emilmont	27:7110ebee3484	458	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
emilmont	27:7110ebee3484	459	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
emilmont	27:7110ebee3484	460
emilmont	27:7110ebee3484	461	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
emilmont	27:7110ebee3484	462	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
emilmont	27:7110ebee3484	463
emilmont	27:7110ebee3484	464	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
emilmont	27:7110ebee3484	465	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
emilmont	33:5364839841bd	466
emilmont	27:7110ebee3484	467	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
emilmont	27:7110ebee3484	468	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
emilmont	27:7110ebee3484	469
emilmont	27:7110ebee3484	470	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
emilmont	27:7110ebee3484	471	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
emilmont	27:7110ebee3484	472
emilmont	27:7110ebee3484	473	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
emilmont	27:7110ebee3484	474	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
emilmont	27:7110ebee3484	475
emilmont	27:7110ebee3484	476	/* SCB Configurable Fault Status Registers Definitions */
emilmont	27:7110ebee3484	477	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
emilmont	27:7110ebee3484	478	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
emilmont	27:7110ebee3484	479
emilmont	27:7110ebee3484	480	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
emilmont	27:7110ebee3484	481	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
emilmont	27:7110ebee3484	482
emilmont	27:7110ebee3484	483	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
emilmont	27:7110ebee3484	484	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
emilmont	27:7110ebee3484	485
emilmont	27:7110ebee3484	486	/* SCB Hard Fault Status Registers Definitions */
emilmont	27:7110ebee3484	487	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
emilmont	27:7110ebee3484	488	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
emilmont	27:7110ebee3484	489
emilmont	27:7110ebee3484	490	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
emilmont	27:7110ebee3484	491	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
emilmont	27:7110ebee3484	492
emilmont	27:7110ebee3484	493	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
emilmont	27:7110ebee3484	494	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
emilmont	27:7110ebee3484	495
emilmont	27:7110ebee3484	496	/* SCB Debug Fault Status Register Definitions */
emilmont	27:7110ebee3484	497	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
emilmont	27:7110ebee3484	498	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
emilmont	27:7110ebee3484	499
emilmont	27:7110ebee3484	500	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
emilmont	27:7110ebee3484	501	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
emilmont	27:7110ebee3484	502
emilmont	27:7110ebee3484	503	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
emilmont	27:7110ebee3484	504	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
emilmont	27:7110ebee3484	505
emilmont	27:7110ebee3484	506	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
emilmont	27:7110ebee3484	507	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
emilmont	27:7110ebee3484	508
emilmont	27:7110ebee3484	509	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
emilmont	27:7110ebee3484	510	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
emilmont	27:7110ebee3484	511
emilmont	27:7110ebee3484	512	/@} end of group CMSIS_SCB /
emilmont	27:7110ebee3484	513
emilmont	27:7110ebee3484	514
emilmont	33:5364839841bd	515	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	516	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
emilmont	33:5364839841bd	517	\brief Type definitions for the System Control and ID Register not in the SCB
emilmont	33:5364839841bd	518	@{
emilmont	33:5364839841bd	519	*/
emilmont	33:5364839841bd	520
emilmont	33:5364839841bd	521	/** \brief Structure type to access the System Control and ID Register not in the SCB.
emilmont	33:5364839841bd	522	*/
emilmont	33:5364839841bd	523	typedef struct
emilmont	33:5364839841bd	524	{
emilmont	33:5364839841bd	525	uint32_t RESERVED0[1];
emilmont	33:5364839841bd	526	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
emilmont	33:5364839841bd	527	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
emilmont	33:5364839841bd	528	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
emilmont	33:5364839841bd	529	#else
emilmont	33:5364839841bd	530	uint32_t RESERVED1[1];
emilmont	33:5364839841bd	531	#endif
emilmont	33:5364839841bd	532	} SCnSCB_Type;
emilmont	33:5364839841bd	533
emilmont	33:5364839841bd	534	/* Interrupt Controller Type Register Definitions */
emilmont	33:5364839841bd	535	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
emilmont	33:5364839841bd	536	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
emilmont	33:5364839841bd	537
emilmont	33:5364839841bd	538	/* Auxiliary Control Register Definitions */
emilmont	33:5364839841bd	539
emilmont	33:5364839841bd	540	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
emilmont	33:5364839841bd	541	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
emilmont	33:5364839841bd	542
emilmont	33:5364839841bd	543	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
emilmont	33:5364839841bd	544	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
emilmont	33:5364839841bd	545
emilmont	33:5364839841bd	546	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
emilmont	33:5364839841bd	547	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
emilmont	33:5364839841bd	548
emilmont	33:5364839841bd	549	/@} end of group CMSIS_SCnotSCB /
emilmont	33:5364839841bd	550
emilmont	33:5364839841bd	551
emilmont	33:5364839841bd	552	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	553	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont	33:5364839841bd	554	\brief Type definitions for the System Timer Registers.
emilmont	27:7110ebee3484	555	@{
emilmont	27:7110ebee3484	556	*/
emilmont	27:7110ebee3484	557
emilmont	27:7110ebee3484	558	/** \brief Structure type to access the System Timer (SysTick).
emilmont	27:7110ebee3484	559	*/
emilmont	27:7110ebee3484	560	typedef struct
emilmont	27:7110ebee3484	561	{
emilmont	27:7110ebee3484	562	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
emilmont	27:7110ebee3484	563	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
emilmont	27:7110ebee3484	564	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
emilmont	27:7110ebee3484	565	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
emilmont	27:7110ebee3484	566	} SysTick_Type;
emilmont	27:7110ebee3484	567
emilmont	27:7110ebee3484	568	/* SysTick Control / Status Register Definitions */
emilmont	27:7110ebee3484	569	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
emilmont	27:7110ebee3484	570	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
emilmont	27:7110ebee3484	571
emilmont	27:7110ebee3484	572	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
emilmont	27:7110ebee3484	573	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
emilmont	27:7110ebee3484	574
emilmont	27:7110ebee3484	575	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
emilmont	27:7110ebee3484	576	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
emilmont	27:7110ebee3484	577
emilmont	27:7110ebee3484	578	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
emilmont	27:7110ebee3484	579	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
emilmont	27:7110ebee3484	580
emilmont	27:7110ebee3484	581	/* SysTick Reload Register Definitions */
emilmont	27:7110ebee3484	582	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
emilmont	27:7110ebee3484	583	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
emilmont	27:7110ebee3484	584
emilmont	27:7110ebee3484	585	/* SysTick Current Register Definitions */
emilmont	27:7110ebee3484	586	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
emilmont	27:7110ebee3484	587	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
emilmont	27:7110ebee3484	588
emilmont	27:7110ebee3484	589	/* SysTick Calibration Register Definitions */
emilmont	27:7110ebee3484	590	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
emilmont	27:7110ebee3484	591	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
emilmont	27:7110ebee3484	592
emilmont	27:7110ebee3484	593	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
emilmont	27:7110ebee3484	594	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
emilmont	27:7110ebee3484	595
emilmont	27:7110ebee3484	596	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
emilmont	27:7110ebee3484	597	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
emilmont	27:7110ebee3484	598
emilmont	27:7110ebee3484	599	/@} end of group CMSIS_SysTick /
emilmont	27:7110ebee3484	600
emilmont	27:7110ebee3484	601
emilmont	33:5364839841bd	602	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	603	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
emilmont	33:5364839841bd	604	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
emilmont	27:7110ebee3484	605	@{
emilmont	27:7110ebee3484	606	*/
emilmont	27:7110ebee3484	607
emilmont	27:7110ebee3484	608	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
emilmont	27:7110ebee3484	609	*/
emilmont	27:7110ebee3484	610	typedef struct
emilmont	27:7110ebee3484	611	{
emilmont	33:5364839841bd	612	__O union
emilmont	27:7110ebee3484	613	{
emilmont	27:7110ebee3484	614	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
emilmont	27:7110ebee3484	615	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
emilmont	27:7110ebee3484	616	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
emilmont	27:7110ebee3484	617	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
emilmont	33:5364839841bd	618	uint32_t RESERVED0[864];
emilmont	33:5364839841bd	619	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
emilmont	33:5364839841bd	620	uint32_t RESERVED1[15];
emilmont	33:5364839841bd	621	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
emilmont	33:5364839841bd	622	uint32_t RESERVED2[15];
emilmont	33:5364839841bd	623	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
emilmont	33:5364839841bd	624	} ITM_Type;
emilmont	27:7110ebee3484	625
emilmont	27:7110ebee3484	626	/* ITM Trace Privilege Register Definitions */
emilmont	33:5364839841bd	627	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
emilmont	33:5364839841bd	628	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
emilmont	27:7110ebee3484	629
emilmont	27:7110ebee3484	630	/* ITM Trace Control Register Definitions */
emilmont	33:5364839841bd	631	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
emilmont	33:5364839841bd	632	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
emilmont	27:7110ebee3484	633
emilmont	33:5364839841bd	634	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
emilmont	33:5364839841bd	635	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
emilmont	27:7110ebee3484	636
emilmont	33:5364839841bd	637	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
emilmont	33:5364839841bd	638	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
emilmont	27:7110ebee3484	639
emilmont	33:5364839841bd	640	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
emilmont	33:5364839841bd	641	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
emilmont	27:7110ebee3484	642
emilmont	33:5364839841bd	643	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
emilmont	33:5364839841bd	644	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
emilmont	27:7110ebee3484	645
emilmont	33:5364839841bd	646	#define ITM_TCR_TXENA_Pos 3 /!< ITM TCR: TXENA Position /
emilmont	33:5364839841bd	647	#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /!< ITM TCR: TXENA Mask /
emilmont	27:7110ebee3484	648
emilmont	33:5364839841bd	649	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
emilmont	33:5364839841bd	650	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
emilmont	27:7110ebee3484	651
emilmont	33:5364839841bd	652	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
emilmont	33:5364839841bd	653	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
emilmont	27:7110ebee3484	654
emilmont	33:5364839841bd	655	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
emilmont	33:5364839841bd	656	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
emilmont	27:7110ebee3484	657
emilmont	27:7110ebee3484	658	/@}/ /* end of group CMSIS_ITM */
emilmont	27:7110ebee3484	659
emilmont	27:7110ebee3484	660
emilmont	27:7110ebee3484	661	#if (__MPU_PRESENT == 1)
emilmont	33:5364839841bd	662	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	663	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
emilmont	33:5364839841bd	664	\brief Type definitions for the Memory Protection Unit (MPU)
emilmont	27:7110ebee3484	665	@{
emilmont	27:7110ebee3484	666	*/
emilmont	27:7110ebee3484	667
emilmont	27:7110ebee3484	668	/** \brief Structure type to access the Memory Protection Unit (MPU).
emilmont	27:7110ebee3484	669	*/
emilmont	27:7110ebee3484	670	typedef struct
emilmont	27:7110ebee3484	671	{
emilmont	27:7110ebee3484	672	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
emilmont	27:7110ebee3484	673	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
emilmont	27:7110ebee3484	674	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
emilmont	27:7110ebee3484	675	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
emilmont	27:7110ebee3484	676	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
emilmont	27:7110ebee3484	677	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
emilmont	27:7110ebee3484	678	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
emilmont	27:7110ebee3484	679	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
emilmont	27:7110ebee3484	680	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
emilmont	27:7110ebee3484	681	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
emilmont	27:7110ebee3484	682	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
emilmont	33:5364839841bd	683	} MPU_Type;
emilmont	27:7110ebee3484	684
emilmont	27:7110ebee3484	685	/* MPU Type Register */
emilmont	27:7110ebee3484	686	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
emilmont	27:7110ebee3484	687	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
emilmont	27:7110ebee3484	688
emilmont	27:7110ebee3484	689	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
emilmont	27:7110ebee3484	690	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
emilmont	27:7110ebee3484	691
emilmont	27:7110ebee3484	692	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
emilmont	27:7110ebee3484	693	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
emilmont	27:7110ebee3484	694
emilmont	27:7110ebee3484	695	/* MPU Control Register */
emilmont	27:7110ebee3484	696	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
emilmont	27:7110ebee3484	697	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
emilmont	27:7110ebee3484	698
emilmont	27:7110ebee3484	699	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
emilmont	27:7110ebee3484	700	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
emilmont	27:7110ebee3484	701
emilmont	27:7110ebee3484	702	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
emilmont	27:7110ebee3484	703	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
emilmont	27:7110ebee3484	704
emilmont	27:7110ebee3484	705	/* MPU Region Number Register */
emilmont	27:7110ebee3484	706	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
emilmont	27:7110ebee3484	707	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
emilmont	27:7110ebee3484	708
emilmont	27:7110ebee3484	709	/* MPU Region Base Address Register */
emilmont	27:7110ebee3484	710	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
emilmont	27:7110ebee3484	711	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
emilmont	27:7110ebee3484	712
emilmont	27:7110ebee3484	713	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
emilmont	27:7110ebee3484	714	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
emilmont	27:7110ebee3484	715
emilmont	27:7110ebee3484	716	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
emilmont	27:7110ebee3484	717	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
emilmont	27:7110ebee3484	718
emilmont	27:7110ebee3484	719	/* MPU Region Attribute and Size Register */
emilmont	33:5364839841bd	720	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
emilmont	33:5364839841bd	721	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
emilmont	27:7110ebee3484	722
emilmont	27:7110ebee3484	723	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
emilmont	27:7110ebee3484	724	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
emilmont	27:7110ebee3484	725
emilmont	27:7110ebee3484	726	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
emilmont	27:7110ebee3484	727	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
emilmont	27:7110ebee3484	728
emilmont	33:5364839841bd	729	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
emilmont	33:5364839841bd	730	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
emilmont	27:7110ebee3484	731
emilmont	27:7110ebee3484	732	/@} end of group CMSIS_MPU /
emilmont	27:7110ebee3484	733	#endif
emilmont	27:7110ebee3484	734
emilmont	27:7110ebee3484	735
emilmont	33:5364839841bd	736	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	737	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont	33:5364839841bd	738	\brief Type definitions for the Core Debug Registers
emilmont	27:7110ebee3484	739	@{
emilmont	27:7110ebee3484	740	*/
emilmont	27:7110ebee3484	741
emilmont	27:7110ebee3484	742	/** \brief Structure type to access the Core Debug Register (CoreDebug).
emilmont	27:7110ebee3484	743	*/
emilmont	27:7110ebee3484	744	typedef struct
emilmont	27:7110ebee3484	745	{
emilmont	27:7110ebee3484	746	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
emilmont	27:7110ebee3484	747	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
emilmont	27:7110ebee3484	748	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
emilmont	27:7110ebee3484	749	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
emilmont	27:7110ebee3484	750	} CoreDebug_Type;
emilmont	27:7110ebee3484	751
emilmont	27:7110ebee3484	752	/* Debug Halting Control and Status Register */
emilmont	27:7110ebee3484	753	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
emilmont	27:7110ebee3484	754	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
emilmont	27:7110ebee3484	755
emilmont	27:7110ebee3484	756	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
emilmont	27:7110ebee3484	757	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
emilmont	27:7110ebee3484	758
emilmont	27:7110ebee3484	759	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
emilmont	27:7110ebee3484	760	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
emilmont	27:7110ebee3484	761
emilmont	27:7110ebee3484	762	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
emilmont	27:7110ebee3484	763	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
emilmont	27:7110ebee3484	764
emilmont	27:7110ebee3484	765	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
emilmont	27:7110ebee3484	766	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
emilmont	27:7110ebee3484	767
emilmont	27:7110ebee3484	768	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
emilmont	27:7110ebee3484	769	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
emilmont	27:7110ebee3484	770
emilmont	27:7110ebee3484	771	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
emilmont	27:7110ebee3484	772	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
emilmont	27:7110ebee3484	773
emilmont	27:7110ebee3484	774	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
emilmont	27:7110ebee3484	775	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
emilmont	27:7110ebee3484	776
emilmont	27:7110ebee3484	777	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
emilmont	27:7110ebee3484	778	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
emilmont	27:7110ebee3484	779
emilmont	27:7110ebee3484	780	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
emilmont	27:7110ebee3484	781	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
emilmont	27:7110ebee3484	782
emilmont	27:7110ebee3484	783	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
emilmont	27:7110ebee3484	784	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
emilmont	27:7110ebee3484	785
emilmont	27:7110ebee3484	786	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
emilmont	27:7110ebee3484	787	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
emilmont	27:7110ebee3484	788
emilmont	27:7110ebee3484	789	/* Debug Core Register Selector Register */
emilmont	27:7110ebee3484	790	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
emilmont	27:7110ebee3484	791	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
emilmont	27:7110ebee3484	792
emilmont	27:7110ebee3484	793	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
emilmont	27:7110ebee3484	794	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
emilmont	27:7110ebee3484	795
emilmont	27:7110ebee3484	796	/* Debug Exception and Monitor Control Register */
emilmont	27:7110ebee3484	797	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
emilmont	27:7110ebee3484	798	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
emilmont	27:7110ebee3484	799
emilmont	27:7110ebee3484	800	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
emilmont	27:7110ebee3484	801	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
emilmont	27:7110ebee3484	802
emilmont	27:7110ebee3484	803	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
emilmont	27:7110ebee3484	804	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
emilmont	27:7110ebee3484	805
emilmont	27:7110ebee3484	806	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
emilmont	27:7110ebee3484	807	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
emilmont	27:7110ebee3484	808
emilmont	27:7110ebee3484	809	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
emilmont	27:7110ebee3484	810	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
emilmont	27:7110ebee3484	811
emilmont	27:7110ebee3484	812	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
emilmont	27:7110ebee3484	813	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
emilmont	27:7110ebee3484	814
emilmont	27:7110ebee3484	815	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
emilmont	27:7110ebee3484	816	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
emilmont	27:7110ebee3484	817
emilmont	27:7110ebee3484	818	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
emilmont	27:7110ebee3484	819	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
emilmont	27:7110ebee3484	820
emilmont	27:7110ebee3484	821	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
emilmont	27:7110ebee3484	822	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
emilmont	27:7110ebee3484	823
emilmont	27:7110ebee3484	824	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
emilmont	27:7110ebee3484	825	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
emilmont	27:7110ebee3484	826
emilmont	27:7110ebee3484	827	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
emilmont	27:7110ebee3484	828	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
emilmont	27:7110ebee3484	829
emilmont	27:7110ebee3484	830	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
emilmont	27:7110ebee3484	831	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
emilmont	27:7110ebee3484	832
emilmont	27:7110ebee3484	833	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
emilmont	27:7110ebee3484	834	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
emilmont	27:7110ebee3484	835
emilmont	27:7110ebee3484	836	/@} end of group CMSIS_CoreDebug /
emilmont	27:7110ebee3484	837
emilmont	27:7110ebee3484	838
emilmont	33:5364839841bd	839	/** \ingroup CMSIS_core_register
emilmont	33:5364839841bd	840	\defgroup CMSIS_core_base Core Definitions
emilmont	33:5364839841bd	841	\brief Definitions for base addresses, unions, and structures.
emilmont	27:7110ebee3484	842	@{
emilmont	27:7110ebee3484	843	*/
emilmont	33:5364839841bd	844
emilmont	27:7110ebee3484	845	/* Memory mapping of Cortex-M3 Hardware */
emilmont	33:5364839841bd	846	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
emilmont	33:5364839841bd	847	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
emilmont	33:5364839841bd	848	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
emilmont	33:5364839841bd	849	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
emilmont	33:5364839841bd	850	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
emilmont	33:5364839841bd	851	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
emilmont	27:7110ebee3484	852
emilmont	33:5364839841bd	853	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
emilmont	33:5364839841bd	854	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
emilmont	33:5364839841bd	855	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
emilmont	33:5364839841bd	856	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
emilmont	33:5364839841bd	857	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
emilmont	33:5364839841bd	858	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
emilmont	27:7110ebee3484	859
emilmont	27:7110ebee3484	860	#if (__MPU_PRESENT == 1)
emilmont	33:5364839841bd	861	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
emilmont	33:5364839841bd	862	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
emilmont	27:7110ebee3484	863	#endif
emilmont	27:7110ebee3484	864
emilmont	27:7110ebee3484	865	/@} /
emilmont	27:7110ebee3484	866
emilmont	27:7110ebee3484	867
emilmont	27:7110ebee3484	868
emilmont	27:7110ebee3484	869	/*******************************************************************************
emilmont	27:7110ebee3484	870	* Hardware Abstraction Layer
emilmont	27:7110ebee3484	871	Core Function Interface contains:
emilmont	27:7110ebee3484	872	- Core NVIC Functions
emilmont	27:7110ebee3484	873	- Core SysTick Functions
emilmont	27:7110ebee3484	874	- Core Debug Functions
emilmont	27:7110ebee3484	875	- Core Register Access Functions
emilmont	33:5364839841bd	876	******************************************************************************/
emilmont	33:5364839841bd	877	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont	27:7110ebee3484	878	*/
emilmont	27:7110ebee3484	879
emilmont	27:7110ebee3484	880
emilmont	27:7110ebee3484	881
emilmont	27:7110ebee3484	882	/* ########################## NVIC functions #################################### */
emilmont	33:5364839841bd	883	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	33:5364839841bd	884	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont	33:5364839841bd	885	\brief Functions that manage interrupts and exceptions via the NVIC.
emilmont	33:5364839841bd	886	@{
emilmont	27:7110ebee3484	887	*/
emilmont	27:7110ebee3484	888
emilmont	27:7110ebee3484	889	/** \brief Set Priority Grouping
emilmont	27:7110ebee3484	890
emilmont	33:5364839841bd	891	The function sets the priority grouping field using the required unlock sequence.
emilmont	27:7110ebee3484	892	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
emilmont	27:7110ebee3484	893	Only values from 0..7 are used.
emilmont	27:7110ebee3484	894	In case of a conflict between priority grouping and available
emilmont	33:5364839841bd	895	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
emilmont	27:7110ebee3484	896
emilmont	33:5364839841bd	897	\param [in] PriorityGroup Priority grouping field.
emilmont	27:7110ebee3484	898	*/
emilmont	27:7110ebee3484	899	static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
emilmont	27:7110ebee3484	900	{
emilmont	27:7110ebee3484	901	uint32_t reg_value;
emilmont	33:5364839841bd	902	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
emilmont	33:5364839841bd	903
emilmont	27:7110ebee3484	904	reg_value = SCB->AIRCR; /* read old register configuration */
emilmont	27:7110ebee3484	905	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
emilmont	33:5364839841bd	906	reg_value = (reg_value \|
emilmont	33:5364839841bd	907	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
emilmont	27:7110ebee3484	908	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
emilmont	27:7110ebee3484	909	SCB->AIRCR = reg_value;
emilmont	27:7110ebee3484	910	}
emilmont	27:7110ebee3484	911
emilmont	27:7110ebee3484	912
emilmont	27:7110ebee3484	913	/** \brief Get Priority Grouping
emilmont	27:7110ebee3484	914
emilmont	33:5364839841bd	915	The function reads the priority grouping field from the NVIC Interrupt Controller.
emilmont	27:7110ebee3484	916
emilmont	33:5364839841bd	917	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
emilmont	27:7110ebee3484	918	*/
emilmont	27:7110ebee3484	919	static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
emilmont	27:7110ebee3484	920	{
emilmont	27:7110ebee3484	921	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
emilmont	27:7110ebee3484	922	}
emilmont	27:7110ebee3484	923
emilmont	27:7110ebee3484	924
emilmont	27:7110ebee3484	925	/** \brief Enable External Interrupt
emilmont	27:7110ebee3484	926
emilmont	33:5364839841bd	927	The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont	27:7110ebee3484	928
emilmont	33:5364839841bd	929	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	27:7110ebee3484	930	*/
emilmont	27:7110ebee3484	931	static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	932	{
emilmont	27:7110ebee3484	933	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
emilmont	27:7110ebee3484	934	}
emilmont	27:7110ebee3484	935
emilmont	27:7110ebee3484	936
emilmont	27:7110ebee3484	937	/** \brief Disable External Interrupt
emilmont	27:7110ebee3484	938
emilmont	33:5364839841bd	939	The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont	27:7110ebee3484	940
emilmont	33:5364839841bd	941	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	27:7110ebee3484	942	*/
emilmont	27:7110ebee3484	943	static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	944	{
emilmont	27:7110ebee3484	945	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
emilmont	27:7110ebee3484	946	}
emilmont	27:7110ebee3484	947
emilmont	27:7110ebee3484	948
emilmont	27:7110ebee3484	949	/** \brief Get Pending Interrupt
emilmont	27:7110ebee3484	950
emilmont	33:5364839841bd	951	The function reads the pending register in the NVIC and returns the pending bit
emilmont	33:5364839841bd	952	for the specified interrupt.
emilmont	27:7110ebee3484	953
emilmont	33:5364839841bd	954	\param [in] IRQn Interrupt number.
emilmont	33:5364839841bd	955
emilmont	33:5364839841bd	956	\return 0 Interrupt status is not pending.
emilmont	33:5364839841bd	957	\return 1 Interrupt status is pending.
emilmont	27:7110ebee3484	958	*/
emilmont	27:7110ebee3484	959	static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	960	{
emilmont	27:7110ebee3484	961	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
emilmont	27:7110ebee3484	962	}
emilmont	27:7110ebee3484	963
emilmont	27:7110ebee3484	964
emilmont	27:7110ebee3484	965	/** \brief Set Pending Interrupt
emilmont	27:7110ebee3484	966
emilmont	33:5364839841bd	967	The function sets the pending bit of an external interrupt.
emilmont	27:7110ebee3484	968
emilmont	33:5364839841bd	969	\param [in] IRQn Interrupt number. Value cannot be negative.
emilmont	27:7110ebee3484	970	*/
emilmont	27:7110ebee3484	971	static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	972	{
emilmont	27:7110ebee3484	973	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
emilmont	27:7110ebee3484	974	}
emilmont	27:7110ebee3484	975
emilmont	27:7110ebee3484	976
emilmont	27:7110ebee3484	977	/** \brief Clear Pending Interrupt
emilmont	27:7110ebee3484	978
emilmont	33:5364839841bd	979	The function clears the pending bit of an external interrupt.
emilmont	27:7110ebee3484	980
emilmont	33:5364839841bd	981	\param [in] IRQn External interrupt number. Value cannot be negative.
emilmont	27:7110ebee3484	982	*/
emilmont	27:7110ebee3484	983	static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont	27:7110ebee3484	984	{
emilmont	27:7110ebee3484	985	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont	27:7110ebee3484	986	}
emilmont	27:7110ebee3484	987
emilmont	27:7110ebee3484	988
emilmont	27:7110ebee3484	989	/** \brief Get Active Interrupt
emilmont	27:7110ebee3484	990
emilmont	33:5364839841bd	991	The function reads the active register in NVIC and returns the active bit.
emilmont	33:5364839841bd	992
emilmont	33:5364839841bd	993	\param [in] IRQn Interrupt number.
emilmont	33:5364839841bd	994
emilmont	33:5364839841bd	995	\return 0 Interrupt status is not active.
emilmont	33:5364839841bd	996	\return 1 Interrupt status is active.
emilmont	27:7110ebee3484	997	*/
emilmont	27:7110ebee3484	998	static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
emilmont	27:7110ebee3484	999	{
emilmont	27:7110ebee3484	1000	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
emilmont	27:7110ebee3484	1001	}
emilmont	27:7110ebee3484	1002
emilmont	27:7110ebee3484	1003
emilmont	27:7110ebee3484	1004	/** \brief Set Interrupt Priority
emilmont	27:7110ebee3484	1005
emilmont	33:5364839841bd	1006	The function sets the priority of an interrupt.
emilmont	27:7110ebee3484	1007
emilmont	33:5364839841bd	1008	\note The priority cannot be set for every core interrupt.
emilmont	27:7110ebee3484	1009
emilmont	33:5364839841bd	1010	\param [in] IRQn Interrupt number.
emilmont	33:5364839841bd	1011	\param [in] priority Priority to set.
emilmont	27:7110ebee3484	1012	*/
emilmont	27:7110ebee3484	1013	static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont	27:7110ebee3484	1014	{
emilmont	27:7110ebee3484	1015	if(IRQn < 0) {
emilmont	27:7110ebee3484	1016	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
emilmont	27:7110ebee3484	1017	else {
emilmont	27:7110ebee3484	1018	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
emilmont	27:7110ebee3484	1019	}
emilmont	27:7110ebee3484	1020
emilmont	27:7110ebee3484	1021
emilmont	27:7110ebee3484	1022	/** \brief Get Interrupt Priority
emilmont	27:7110ebee3484	1023
emilmont	33:5364839841bd	1024	The function reads the priority of an interrupt. The interrupt
emilmont	33:5364839841bd	1025	number can be positive to specify an external (device specific)
emilmont	27:7110ebee3484	1026	interrupt, or negative to specify an internal (core) interrupt.
emilmont	27:7110ebee3484	1027
emilmont	27:7110ebee3484	1028
emilmont	33:5364839841bd	1029	\param [in] IRQn Interrupt number.
emilmont	33:5364839841bd	1030	\return Interrupt Priority. Value is aligned automatically to the implemented
emilmont	33:5364839841bd	1031	priority bits of the microcontroller.
emilmont	27:7110ebee3484	1032	*/
emilmont	27:7110ebee3484	1033	static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont	27:7110ebee3484	1034	{
emilmont	27:7110ebee3484	1035
emilmont	27:7110ebee3484	1036	if(IRQn < 0) {
emilmont	27:7110ebee3484	1037	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
emilmont	27:7110ebee3484	1038	else {
emilmont	27:7110ebee3484	1039	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont	27:7110ebee3484	1040	}
emilmont	27:7110ebee3484	1041
emilmont	27:7110ebee3484	1042
emilmont	27:7110ebee3484	1043	/** \brief Encode Priority
emilmont	27:7110ebee3484	1044
emilmont	33:5364839841bd	1045	The function encodes the priority for an interrupt with the given priority group,
emilmont	33:5364839841bd	1046	preemptive priority value, and subpriority value.
emilmont	27:7110ebee3484	1047	In case of a conflict between priority grouping and available
emilmont	33:5364839841bd	1048	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
emilmont	27:7110ebee3484	1049
emilmont	33:5364839841bd	1050	\param [in] PriorityGroup Used priority group.
emilmont	33:5364839841bd	1051	\param [in] PreemptPriority Preemptive priority value (starting from 0).
emilmont	33:5364839841bd	1052	\param [in] SubPriority Subpriority value (starting from 0).
emilmont	33:5364839841bd	1053	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
emilmont	27:7110ebee3484	1054	*/
emilmont	27:7110ebee3484	1055	static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
emilmont	27:7110ebee3484	1056	{
emilmont	27:7110ebee3484	1057	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont	27:7110ebee3484	1058	uint32_t PreemptPriorityBits;
emilmont	27:7110ebee3484	1059	uint32_t SubPriorityBits;
emilmont	27:7110ebee3484	1060
emilmont	27:7110ebee3484	1061	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont	27:7110ebee3484	1062	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont	33:5364839841bd	1063
emilmont	27:7110ebee3484	1064	return (
emilmont	27:7110ebee3484	1065	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
emilmont	27:7110ebee3484	1066	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
emilmont	27:7110ebee3484	1067	);
emilmont	27:7110ebee3484	1068	}
emilmont	27:7110ebee3484	1069
emilmont	27:7110ebee3484	1070
emilmont	27:7110ebee3484	1071	/** \brief Decode Priority
emilmont	27:7110ebee3484	1072
emilmont	33:5364839841bd	1073	The function decodes an interrupt priority value with a given priority group to
emilmont	33:5364839841bd	1074	preemptive priority value and subpriority value.
emilmont	27:7110ebee3484	1075	In case of a conflict between priority grouping and available
emilmont	27:7110ebee3484	1076	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
emilmont	33:5364839841bd	1077
emilmont	33:5364839841bd	1078	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
emilmont	33:5364839841bd	1079	\param [in] PriorityGroup Used priority group.
emilmont	33:5364839841bd	1080	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
emilmont	33:5364839841bd	1081	\param [out] pSubPriority Subpriority value (starting from 0).
emilmont	27:7110ebee3484	1082	*/
emilmont	27:7110ebee3484	1083	static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
emilmont	27:7110ebee3484	1084	{
emilmont	27:7110ebee3484	1085	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
emilmont	27:7110ebee3484	1086	uint32_t PreemptPriorityBits;
emilmont	27:7110ebee3484	1087	uint32_t SubPriorityBits;
emilmont	27:7110ebee3484	1088
emilmont	27:7110ebee3484	1089	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
emilmont	27:7110ebee3484	1090	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
emilmont	33:5364839841bd	1091
emilmont	27:7110ebee3484	1092	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
emilmont	27:7110ebee3484	1093	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
emilmont	27:7110ebee3484	1094	}
emilmont	27:7110ebee3484	1095
emilmont	27:7110ebee3484	1096
emilmont	27:7110ebee3484	1097	/** \brief System Reset
emilmont	27:7110ebee3484	1098
emilmont	33:5364839841bd	1099	The function initiates a system reset request to reset the MCU.
emilmont	27:7110ebee3484	1100	*/
emilmont	27:7110ebee3484	1101	static __INLINE void NVIC_SystemReset(void)
emilmont	27:7110ebee3484	1102	{
emilmont	27:7110ebee3484	1103	__DSB(); /* Ensure all outstanding memory accesses included
emilmont	33:5364839841bd	1104	buffered write are completed before reset */
emilmont	33:5364839841bd	1105	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
emilmont	33:5364839841bd	1106	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
emilmont	27:7110ebee3484	1107	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
emilmont	33:5364839841bd	1108	__DSB(); /* Ensure completion of memory access */
emilmont	27:7110ebee3484	1109	while(1); /* wait until reset */
emilmont	27:7110ebee3484	1110	}
emilmont	27:7110ebee3484	1111
emilmont	27:7110ebee3484	1112	/@} end of CMSIS_Core_NVICFunctions /
emilmont	27:7110ebee3484	1113
emilmont	27:7110ebee3484	1114
emilmont	27:7110ebee3484	1115
emilmont	27:7110ebee3484	1116	/* ################################## SysTick function ############################################ */
emilmont	33:5364839841bd	1117	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	33:5364839841bd	1118	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont	33:5364839841bd	1119	\brief Functions that configure the System.
emilmont	27:7110ebee3484	1120	@{
emilmont	27:7110ebee3484	1121	*/
emilmont	27:7110ebee3484	1122
emilmont	27:7110ebee3484	1123	#if (__Vendor_SysTickConfig == 0)
emilmont	27:7110ebee3484	1124
emilmont	27:7110ebee3484	1125	/** \brief System Tick Configuration
emilmont	27:7110ebee3484	1126
emilmont	33:5364839841bd	1127	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont	33:5364839841bd	1128	Counter is in free running mode to generate periodic interrupts.
emilmont	27:7110ebee3484	1129
emilmont	33:5364839841bd	1130	\param [in] ticks Number of ticks between two interrupts.
emilmont	33:5364839841bd	1131
emilmont	33:5364839841bd	1132	\return 0 Function succeeded.
emilmont	33:5364839841bd	1133	\return 1 Function failed.
emilmont	33:5364839841bd	1134
emilmont	33:5364839841bd	1135	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont	33:5364839841bd	1136	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont	33:5364839841bd	1137	must contain a vendor-specific implementation of this function.
emilmont	33:5364839841bd	1138
emilmont	27:7110ebee3484	1139	*/
emilmont	27:7110ebee3484	1140	static __INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont	33:5364839841bd	1141	{
emilmont	27:7110ebee3484	1142	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont	33:5364839841bd	1143
emilmont	27:7110ebee3484	1144	SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
emilmont	33:5364839841bd	1145	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont	27:7110ebee3484	1146	SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont	33:5364839841bd	1147	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
emilmont	33:5364839841bd	1148	SysTick_CTRL_TICKINT_Msk \|
emilmont	27:7110ebee3484	1149	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont	27:7110ebee3484	1150	return (0); /* Function successful */
emilmont	27:7110ebee3484	1151	}
emilmont	27:7110ebee3484	1152
emilmont	27:7110ebee3484	1153	#endif
emilmont	27:7110ebee3484	1154
emilmont	27:7110ebee3484	1155	/@} end of CMSIS_Core_SysTickFunctions /
emilmont	27:7110ebee3484	1156
emilmont	27:7110ebee3484	1157
emilmont	27:7110ebee3484	1158
emilmont	27:7110ebee3484	1159	/* ##################################### Debug In/Output function ########################################### */
emilmont	33:5364839841bd	1160	/** \ingroup CMSIS_Core_FunctionInterface
emilmont	33:5364839841bd	1161	\defgroup CMSIS_core_DebugFunctions ITM Functions
emilmont	33:5364839841bd	1162	\brief Functions that access the ITM debug interface.
emilmont	27:7110ebee3484	1163	@{
emilmont	27:7110ebee3484	1164	*/
emilmont	27:7110ebee3484	1165
emilmont	33:5364839841bd	1166	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
emilmont	33:5364839841bd	1167	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
emilmont	27:7110ebee3484	1168
emilmont	27:7110ebee3484	1169
emilmont	27:7110ebee3484	1170	/** \brief ITM Send Character
emilmont	27:7110ebee3484	1171
emilmont	33:5364839841bd	1172	The function transmits a character via the ITM channel 0, and
emilmont	33:5364839841bd	1173	\li Just returns when no debugger is connected that has booked the output.
emilmont	33:5364839841bd	1174	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
emilmont	27:7110ebee3484	1175
emilmont	33:5364839841bd	1176	\param [in] ch Character to transmit.
emilmont	33:5364839841bd	1177
emilmont	33:5364839841bd	1178	\returns Character to transmit.
emilmont	27:7110ebee3484	1179	*/
emilmont	27:7110ebee3484	1180	static __INLINE uint32_t ITM_SendChar (uint32_t ch)
emilmont	27:7110ebee3484	1181	{
emilmont	33:5364839841bd	1182	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
emilmont	27:7110ebee3484	1183	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
emilmont	27:7110ebee3484	1184	{
emilmont	27:7110ebee3484	1185	while (ITM->PORT[0].u32 == 0);
emilmont	27:7110ebee3484	1186	ITM->PORT[0].u8 = (uint8_t) ch;
emilmont	33:5364839841bd	1187	}
emilmont	27:7110ebee3484	1188	return (ch);
emilmont	27:7110ebee3484	1189	}
emilmont	27:7110ebee3484	1190
emilmont	27:7110ebee3484	1191
emilmont	27:7110ebee3484	1192	/** \brief ITM Receive Character
emilmont	27:7110ebee3484	1193
emilmont	33:5364839841bd	1194	The function inputs a character via the external variable \ref ITM_RxBuffer.
emilmont	27:7110ebee3484	1195
emilmont	33:5364839841bd	1196	\return Received character.
emilmont	33:5364839841bd	1197	\return -1 No character pending.
emilmont	27:7110ebee3484	1198	*/
emilmont	27:7110ebee3484	1199	static __INLINE int32_t ITM_ReceiveChar (void) {
emilmont	27:7110ebee3484	1200	int32_t ch = -1; /* no character available */
emilmont	27:7110ebee3484	1201
emilmont	27:7110ebee3484	1202	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
emilmont	27:7110ebee3484	1203	ch = ITM_RxBuffer;
emilmont	27:7110ebee3484	1204	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
emilmont	27:7110ebee3484	1205	}
emilmont	33:5364839841bd	1206
emilmont	33:5364839841bd	1207	return (ch);
emilmont	27:7110ebee3484	1208	}
emilmont	27:7110ebee3484	1209
emilmont	27:7110ebee3484	1210
emilmont	27:7110ebee3484	1211	/** \brief ITM Check Character
emilmont	27:7110ebee3484	1212
emilmont	33:5364839841bd	1213	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
emilmont	27:7110ebee3484	1214
emilmont	33:5364839841bd	1215	\return 0 No character available.
emilmont	33:5364839841bd	1216	\return 1 Character available.
emilmont	27:7110ebee3484	1217	*/
emilmont	27:7110ebee3484	1218	static __INLINE int32_t ITM_CheckChar (void) {
emilmont	27:7110ebee3484	1219
emilmont	27:7110ebee3484	1220	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
emilmont	27:7110ebee3484	1221	return (0); /* no character available */
emilmont	27:7110ebee3484	1222	} else {
emilmont	27:7110ebee3484	1223	return (1); /* character available */
emilmont	27:7110ebee3484	1224	}
emilmont	27:7110ebee3484	1225	}
emilmont	27:7110ebee3484	1226
emilmont	27:7110ebee3484	1227	/@} end of CMSIS_core_DebugFunctions /
emilmont	27:7110ebee3484	1228
emilmont	27:7110ebee3484	1229	#endif /* __CORE_CM3_H_DEPENDANT */
emilmont	27:7110ebee3484	1230
emilmont	27:7110ebee3484	1231	#endif /* __CMSIS_GENERIC */
emilmont	27:7110ebee3484	1232
emilmont	27:7110ebee3484	1233	#ifdef __cplusplus
emilmont	27:7110ebee3484	1234	}
emilmont	27:7110ebee3484	1235	#endif

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Type:	Library
Created:	24 Oct 2012
Imports:	3167
Forks:	4
Commits:	44
Dependents:	17
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Followers:	59

LPC1768/GCC_ARM/core_cm3.h@33:5364839841bd, 2012-01-10 (annotated)

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