Mihail Stoyanov / mbed

Fork of the official mbed C/C++ SDK provides the software platform and libraries to build your applications. The fork has the documentation converted to Doxygen format

Dependents:   NervousPuppySprintOne NervousPuppySprint2602 Robot WarehouseBot1 ... more

Fork of mbed by mbed official

LPC11U24/GCC_CS/core_cmInstr.h@33:5364839841bd, 2012-01-10 (annotated)

Committer:
emilmont
Date:
Tue Jan 10 12:00:50 2012 +0000
Revision:
33:5364839841bd
Parent:
27:7110ebee3484 
[10 January 2012] CAN::attach template. CMSIS updates.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 27:7110ebee3484 1 /**************************************************************************//**
emilmont 27:7110ebee3484 2 * @file core_cmInstr.h
emilmont 27:7110ebee3484 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
emilmont 33:5364839841bd 4 * @version V3.00
emilmont 33:5364839841bd 5 * @date 09. December 2011
emilmont 27:7110ebee3484 6 *
emilmont 27:7110ebee3484 7 * @note
emilmont 33:5364839841bd 8 * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
emilmont 27:7110ebee3484 9 *
emilmont 27:7110ebee3484 10 * @par
emilmont 27:7110ebee3484 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 27:7110ebee3484 12 * processor based microcontrollers. This file can be freely distributed
emilmont 27:7110ebee3484 13 * within development tools that are supporting such ARM based processors.
emilmont 27:7110ebee3484 14 *
emilmont 27:7110ebee3484 15 * @par
emilmont 27:7110ebee3484 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 27:7110ebee3484 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 27:7110ebee3484 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 27:7110ebee3484 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 27:7110ebee3484 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 27:7110ebee3484 21 *
emilmont 27:7110ebee3484 22 ******************************************************************************/
emilmont 27:7110ebee3484 23
emilmont 33:5364839841bd 24 #ifndef __CORE_CMINSTR_H
emilmont 33:5364839841bd 25 #define __CORE_CMINSTR_H
emilmont 27:7110ebee3484 26
emilmont 27:7110ebee3484 27
emilmont 27:7110ebee3484 28 /* ########################## Core Instruction Access ######################### */
emilmont 27:7110ebee3484 29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 27:7110ebee3484 30 Access to dedicated instructions
emilmont 27:7110ebee3484 31 @{
emilmont 27:7110ebee3484 32 */
emilmont 27:7110ebee3484 33
emilmont 33:5364839841bd 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 27:7110ebee3484 35 /* ARM armcc specific functions */
emilmont 27:7110ebee3484 36
emilmont 33:5364839841bd 37 #if (__ARMCC_VERSION < 400677)
emilmont 33:5364839841bd 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 33:5364839841bd 39 #endif
emilmont 33:5364839841bd 40
emilmont 33:5364839841bd 41
emilmont 27:7110ebee3484 42 /** \brief No Operation
emilmont 27:7110ebee3484 43
emilmont 27:7110ebee3484 44 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 27:7110ebee3484 45 */
emilmont 27:7110ebee3484 46 #define __NOP __nop
emilmont 27:7110ebee3484 47
emilmont 27:7110ebee3484 48
emilmont 27:7110ebee3484 49 /** \brief Wait For Interrupt
emilmont 27:7110ebee3484 50
emilmont 27:7110ebee3484 51 Wait For Interrupt is a hint instruction that suspends execution
emilmont 27:7110ebee3484 52 until one of a number of events occurs.
emilmont 27:7110ebee3484 53 */
emilmont 27:7110ebee3484 54 #define __WFI __wfi
emilmont 27:7110ebee3484 55
emilmont 27:7110ebee3484 56
emilmont 27:7110ebee3484 57 /** \brief Wait For Event
emilmont 27:7110ebee3484 58
emilmont 27:7110ebee3484 59 Wait For Event is a hint instruction that permits the processor to enter
emilmont 27:7110ebee3484 60 a low-power state until one of a number of events occurs.
emilmont 27:7110ebee3484 61 */
emilmont 27:7110ebee3484 62 #define __WFE __wfe
emilmont 27:7110ebee3484 63
emilmont 27:7110ebee3484 64
emilmont 27:7110ebee3484 65 /** \brief Send Event
emilmont 27:7110ebee3484 66
emilmont 27:7110ebee3484 67 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 27:7110ebee3484 68 */
emilmont 27:7110ebee3484 69 #define __SEV __sev
emilmont 27:7110ebee3484 70
emilmont 27:7110ebee3484 71
emilmont 27:7110ebee3484 72 /** \brief Instruction Synchronization Barrier
emilmont 27:7110ebee3484 73
emilmont 27:7110ebee3484 74 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 27:7110ebee3484 75 so that all instructions following the ISB are fetched from cache or
emilmont 27:7110ebee3484 76 memory, after the instruction has been completed.
emilmont 27:7110ebee3484 77 */
emilmont 27:7110ebee3484 78 #define __ISB() __isb(0xF)
emilmont 27:7110ebee3484 79
emilmont 27:7110ebee3484 80
emilmont 27:7110ebee3484 81 /** \brief Data Synchronization Barrier
emilmont 27:7110ebee3484 82
emilmont 27:7110ebee3484 83 This function acts as a special kind of Data Memory Barrier.
emilmont 27:7110ebee3484 84 It completes when all explicit memory accesses before this instruction complete.
emilmont 27:7110ebee3484 85 */
emilmont 27:7110ebee3484 86 #define __DSB() __dsb(0xF)
emilmont 27:7110ebee3484 87
emilmont 27:7110ebee3484 88
emilmont 27:7110ebee3484 89 /** \brief Data Memory Barrier
emilmont 27:7110ebee3484 90
emilmont 27:7110ebee3484 91 This function ensures the apparent order of the explicit memory operations before
emilmont 27:7110ebee3484 92 and after the instruction, without ensuring their completion.
emilmont 27:7110ebee3484 93 */
emilmont 27:7110ebee3484 94 #define __DMB() __dmb(0xF)
emilmont 27:7110ebee3484 95
emilmont 27:7110ebee3484 96
emilmont 27:7110ebee3484 97 /** \brief Reverse byte order (32 bit)
emilmont 27:7110ebee3484 98
emilmont 27:7110ebee3484 99 This function reverses the byte order in integer value.
emilmont 27:7110ebee3484 100
emilmont 27:7110ebee3484 101 \param [in] value Value to reverse
emilmont 27:7110ebee3484 102 \return Reversed value
emilmont 27:7110ebee3484 103 */
emilmont 27:7110ebee3484 104 #define __REV __rev
emilmont 27:7110ebee3484 105
emilmont 27:7110ebee3484 106
emilmont 27:7110ebee3484 107 /** \brief Reverse byte order (16 bit)
emilmont 27:7110ebee3484 108
emilmont 27:7110ebee3484 109 This function reverses the byte order in two unsigned short values.
emilmont 27:7110ebee3484 110
emilmont 27:7110ebee3484 111 \param [in] value Value to reverse
emilmont 27:7110ebee3484 112 \return Reversed value
emilmont 27:7110ebee3484 113 */
emilmont 33:5364839841bd 114 static __attribute__((section(".rev16_text"))) __INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 27:7110ebee3484 115 {
emilmont 27:7110ebee3484 116 rev16 r0, r0
emilmont 27:7110ebee3484 117 bx lr
emilmont 27:7110ebee3484 118 }
emilmont 27:7110ebee3484 119
emilmont 27:7110ebee3484 120
emilmont 27:7110ebee3484 121 /** \brief Reverse byte order in signed short value
emilmont 27:7110ebee3484 122
emilmont 27:7110ebee3484 123 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 27:7110ebee3484 124
emilmont 27:7110ebee3484 125 \param [in] value Value to reverse
emilmont 27:7110ebee3484 126 \return Reversed value
emilmont 27:7110ebee3484 127 */
emilmont 33:5364839841bd 128 static __attribute__((section(".revsh_text"))) __INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 27:7110ebee3484 129 {
emilmont 27:7110ebee3484 130 revsh r0, r0
emilmont 27:7110ebee3484 131 bx lr
emilmont 27:7110ebee3484 132 }
emilmont 27:7110ebee3484 133
emilmont 27:7110ebee3484 134
emilmont 27:7110ebee3484 135 #if (__CORTEX_M >= 0x03)
emilmont 27:7110ebee3484 136
emilmont 27:7110ebee3484 137 /** \brief Reverse bit order of value
emilmont 27:7110ebee3484 138
emilmont 27:7110ebee3484 139 This function reverses the bit order of the given value.
emilmont 27:7110ebee3484 140
emilmont 27:7110ebee3484 141 \param [in] value Value to reverse
emilmont 27:7110ebee3484 142 \return Reversed value
emilmont 27:7110ebee3484 143 */
emilmont 27:7110ebee3484 144 #define __RBIT __rbit
emilmont 27:7110ebee3484 145
emilmont 27:7110ebee3484 146
emilmont 27:7110ebee3484 147 /** \brief LDR Exclusive (8 bit)
emilmont 27:7110ebee3484 148
emilmont 27:7110ebee3484 149 This function performs a exclusive LDR command for 8 bit value.
emilmont 27:7110ebee3484 150
emilmont 27:7110ebee3484 151 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 152 \return value of type uint8_t at (*ptr)
emilmont 27:7110ebee3484 153 */
emilmont 27:7110ebee3484 154 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 27:7110ebee3484 155
emilmont 27:7110ebee3484 156
emilmont 27:7110ebee3484 157 /** \brief LDR Exclusive (16 bit)
emilmont 27:7110ebee3484 158
emilmont 27:7110ebee3484 159 This function performs a exclusive LDR command for 16 bit values.
emilmont 27:7110ebee3484 160
emilmont 27:7110ebee3484 161 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 162 \return value of type uint16_t at (*ptr)
emilmont 27:7110ebee3484 163 */
emilmont 27:7110ebee3484 164 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 27:7110ebee3484 165
emilmont 27:7110ebee3484 166
emilmont 27:7110ebee3484 167 /** \brief LDR Exclusive (32 bit)
emilmont 27:7110ebee3484 168
emilmont 27:7110ebee3484 169 This function performs a exclusive LDR command for 32 bit values.
emilmont 27:7110ebee3484 170
emilmont 27:7110ebee3484 171 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 172 \return value of type uint32_t at (*ptr)
emilmont 27:7110ebee3484 173 */
emilmont 27:7110ebee3484 174 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 27:7110ebee3484 175
emilmont 27:7110ebee3484 176
emilmont 27:7110ebee3484 177 /** \brief STR Exclusive (8 bit)
emilmont 27:7110ebee3484 178
emilmont 27:7110ebee3484 179 This function performs a exclusive STR command for 8 bit values.
emilmont 27:7110ebee3484 180
emilmont 27:7110ebee3484 181 \param [in] value Value to store
emilmont 27:7110ebee3484 182 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 183 \return 0 Function succeeded
emilmont 27:7110ebee3484 184 \return 1 Function failed
emilmont 27:7110ebee3484 185 */
emilmont 27:7110ebee3484 186 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 27:7110ebee3484 187
emilmont 27:7110ebee3484 188
emilmont 27:7110ebee3484 189 /** \brief STR Exclusive (16 bit)
emilmont 27:7110ebee3484 190
emilmont 27:7110ebee3484 191 This function performs a exclusive STR command for 16 bit values.
emilmont 27:7110ebee3484 192
emilmont 27:7110ebee3484 193 \param [in] value Value to store
emilmont 27:7110ebee3484 194 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 195 \return 0 Function succeeded
emilmont 27:7110ebee3484 196 \return 1 Function failed
emilmont 27:7110ebee3484 197 */
emilmont 27:7110ebee3484 198 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 27:7110ebee3484 199
emilmont 27:7110ebee3484 200
emilmont 27:7110ebee3484 201 /** \brief STR Exclusive (32 bit)
emilmont 27:7110ebee3484 202
emilmont 27:7110ebee3484 203 This function performs a exclusive STR command for 32 bit values.
emilmont 27:7110ebee3484 204
emilmont 27:7110ebee3484 205 \param [in] value Value to store
emilmont 27:7110ebee3484 206 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 207 \return 0 Function succeeded
emilmont 27:7110ebee3484 208 \return 1 Function failed
emilmont 27:7110ebee3484 209 */
emilmont 27:7110ebee3484 210 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 27:7110ebee3484 211
emilmont 27:7110ebee3484 212
emilmont 27:7110ebee3484 213 /** \brief Remove the exclusive lock
emilmont 27:7110ebee3484 214
emilmont 27:7110ebee3484 215 This function removes the exclusive lock which is created by LDREX.
emilmont 27:7110ebee3484 216
emilmont 27:7110ebee3484 217 */
emilmont 27:7110ebee3484 218 #define __CLREX __clrex
emilmont 27:7110ebee3484 219
emilmont 27:7110ebee3484 220
emilmont 27:7110ebee3484 221 /** \brief Signed Saturate
emilmont 27:7110ebee3484 222
emilmont 27:7110ebee3484 223 This function saturates a signed value.
emilmont 27:7110ebee3484 224
emilmont 27:7110ebee3484 225 \param [in] value Value to be saturated
emilmont 27:7110ebee3484 226 \param [in] sat Bit position to saturate to (1..32)
emilmont 27:7110ebee3484 227 \return Saturated value
emilmont 27:7110ebee3484 228 */
emilmont 27:7110ebee3484 229 #define __SSAT __ssat
emilmont 27:7110ebee3484 230
emilmont 27:7110ebee3484 231
emilmont 27:7110ebee3484 232 /** \brief Unsigned Saturate
emilmont 27:7110ebee3484 233
emilmont 27:7110ebee3484 234 This function saturates an unsigned value.
emilmont 27:7110ebee3484 235
emilmont 27:7110ebee3484 236 \param [in] value Value to be saturated
emilmont 27:7110ebee3484 237 \param [in] sat Bit position to saturate to (0..31)
emilmont 27:7110ebee3484 238 \return Saturated value
emilmont 27:7110ebee3484 239 */
emilmont 27:7110ebee3484 240 #define __USAT __usat
emilmont 27:7110ebee3484 241
emilmont 27:7110ebee3484 242
emilmont 27:7110ebee3484 243 /** \brief Count leading zeros
emilmont 27:7110ebee3484 244
emilmont 27:7110ebee3484 245 This function counts the number of leading zeros of a data value.
emilmont 27:7110ebee3484 246
emilmont 27:7110ebee3484 247 \param [in] value Value to count the leading zeros
emilmont 27:7110ebee3484 248 \return number of leading zeros in value
emilmont 27:7110ebee3484 249 */
emilmont 27:7110ebee3484 250 #define __CLZ __clz
emilmont 27:7110ebee3484 251
emilmont 27:7110ebee3484 252 #endif /* (__CORTEX_M >= 0x03) */
emilmont 27:7110ebee3484 253
emilmont 27:7110ebee3484 254
emilmont 27:7110ebee3484 255
emilmont 33:5364839841bd 256 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 27:7110ebee3484 257 /* IAR iccarm specific functions */
emilmont 27:7110ebee3484 258
emilmont 33:5364839841bd 259 #include <cmsis_iar.h>
emilmont 27:7110ebee3484 260
emilmont 27:7110ebee3484 261
emilmont 33:5364839841bd 262 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 27:7110ebee3484 263 /* GNU gcc specific functions */
emilmont 27:7110ebee3484 264
emilmont 27:7110ebee3484 265 /** \brief No Operation
emilmont 27:7110ebee3484 266
emilmont 27:7110ebee3484 267 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 27:7110ebee3484 268 */
emilmont 27:7110ebee3484 269 __attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
emilmont 27:7110ebee3484 270 {
emilmont 27:7110ebee3484 271 __ASM volatile ("nop");
emilmont 27:7110ebee3484 272 }
emilmont 27:7110ebee3484 273
emilmont 27:7110ebee3484 274
emilmont 27:7110ebee3484 275 /** \brief Wait For Interrupt
emilmont 27:7110ebee3484 276
emilmont 27:7110ebee3484 277 Wait For Interrupt is a hint instruction that suspends execution
emilmont 27:7110ebee3484 278 until one of a number of events occurs.
emilmont 27:7110ebee3484 279 */
emilmont 27:7110ebee3484 280 __attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
emilmont 27:7110ebee3484 281 {
emilmont 27:7110ebee3484 282 __ASM volatile ("wfi");
emilmont 27:7110ebee3484 283 }
emilmont 27:7110ebee3484 284
emilmont 27:7110ebee3484 285
emilmont 27:7110ebee3484 286 /** \brief Wait For Event
emilmont 27:7110ebee3484 287
emilmont 27:7110ebee3484 288 Wait For Event is a hint instruction that permits the processor to enter
emilmont 27:7110ebee3484 289 a low-power state until one of a number of events occurs.
emilmont 27:7110ebee3484 290 */
emilmont 27:7110ebee3484 291 __attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
emilmont 27:7110ebee3484 292 {
emilmont 27:7110ebee3484 293 __ASM volatile ("wfe");
emilmont 27:7110ebee3484 294 }
emilmont 27:7110ebee3484 295
emilmont 27:7110ebee3484 296
emilmont 27:7110ebee3484 297 /** \brief Send Event
emilmont 27:7110ebee3484 298
emilmont 27:7110ebee3484 299 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 27:7110ebee3484 300 */
emilmont 27:7110ebee3484 301 __attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
emilmont 27:7110ebee3484 302 {
emilmont 27:7110ebee3484 303 __ASM volatile ("sev");
emilmont 27:7110ebee3484 304 }
emilmont 27:7110ebee3484 305
emilmont 27:7110ebee3484 306
emilmont 27:7110ebee3484 307 /** \brief Instruction Synchronization Barrier
emilmont 27:7110ebee3484 308
emilmont 27:7110ebee3484 309 Instruction Synchronization Barrier flushes the pipeline in the processor,
emilmont 27:7110ebee3484 310 so that all instructions following the ISB are fetched from cache or
emilmont 27:7110ebee3484 311 memory, after the instruction has been completed.
emilmont 27:7110ebee3484 312 */
emilmont 27:7110ebee3484 313 __attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
emilmont 27:7110ebee3484 314 {
emilmont 27:7110ebee3484 315 __ASM volatile ("isb");
emilmont 27:7110ebee3484 316 }
emilmont 27:7110ebee3484 317
emilmont 27:7110ebee3484 318
emilmont 27:7110ebee3484 319 /** \brief Data Synchronization Barrier
emilmont 27:7110ebee3484 320
emilmont 27:7110ebee3484 321 This function acts as a special kind of Data Memory Barrier.
emilmont 27:7110ebee3484 322 It completes when all explicit memory accesses before this instruction complete.
emilmont 27:7110ebee3484 323 */
emilmont 27:7110ebee3484 324 __attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
emilmont 27:7110ebee3484 325 {
emilmont 27:7110ebee3484 326 __ASM volatile ("dsb");
emilmont 27:7110ebee3484 327 }
emilmont 27:7110ebee3484 328
emilmont 27:7110ebee3484 329
emilmont 27:7110ebee3484 330 /** \brief Data Memory Barrier
emilmont 27:7110ebee3484 331
emilmont 27:7110ebee3484 332 This function ensures the apparent order of the explicit memory operations before
emilmont 27:7110ebee3484 333 and after the instruction, without ensuring their completion.
emilmont 27:7110ebee3484 334 */
emilmont 27:7110ebee3484 335 __attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
emilmont 27:7110ebee3484 336 {
emilmont 27:7110ebee3484 337 __ASM volatile ("dmb");
emilmont 27:7110ebee3484 338 }
emilmont 27:7110ebee3484 339
emilmont 27:7110ebee3484 340
emilmont 27:7110ebee3484 341 /** \brief Reverse byte order (32 bit)
emilmont 27:7110ebee3484 342
emilmont 27:7110ebee3484 343 This function reverses the byte order in integer value.
emilmont 27:7110ebee3484 344
emilmont 27:7110ebee3484 345 \param [in] value Value to reverse
emilmont 27:7110ebee3484 346 \return Reversed value
emilmont 27:7110ebee3484 347 */
emilmont 27:7110ebee3484 348 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
emilmont 27:7110ebee3484 349 {
emilmont 27:7110ebee3484 350 uint32_t result;
emilmont 27:7110ebee3484 351
emilmont 27:7110ebee3484 352 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
emilmont 27:7110ebee3484 353 return(result);
emilmont 27:7110ebee3484 354 }
emilmont 27:7110ebee3484 355
emilmont 27:7110ebee3484 356
emilmont 27:7110ebee3484 357 /** \brief Reverse byte order (16 bit)
emilmont 27:7110ebee3484 358
emilmont 27:7110ebee3484 359 This function reverses the byte order in two unsigned short values.
emilmont 27:7110ebee3484 360
emilmont 27:7110ebee3484 361 \param [in] value Value to reverse
emilmont 27:7110ebee3484 362 \return Reversed value
emilmont 27:7110ebee3484 363 */
emilmont 27:7110ebee3484 364 __attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
emilmont 27:7110ebee3484 365 {
emilmont 27:7110ebee3484 366 uint32_t result;
emilmont 27:7110ebee3484 367
emilmont 27:7110ebee3484 368 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
emilmont 27:7110ebee3484 369 return(result);
emilmont 27:7110ebee3484 370 }
emilmont 27:7110ebee3484 371
emilmont 27:7110ebee3484 372
emilmont 27:7110ebee3484 373 /** \brief Reverse byte order in signed short value
emilmont 27:7110ebee3484 374
emilmont 27:7110ebee3484 375 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 27:7110ebee3484 376
emilmont 27:7110ebee3484 377 \param [in] value Value to reverse
emilmont 27:7110ebee3484 378 \return Reversed value
emilmont 27:7110ebee3484 379 */
emilmont 27:7110ebee3484 380 __attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
emilmont 27:7110ebee3484 381 {
emilmont 27:7110ebee3484 382 uint32_t result;
emilmont 27:7110ebee3484 383
emilmont 27:7110ebee3484 384 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
emilmont 27:7110ebee3484 385 return(result);
emilmont 27:7110ebee3484 386 }
emilmont 27:7110ebee3484 387
emilmont 27:7110ebee3484 388
emilmont 27:7110ebee3484 389 #if (__CORTEX_M >= 0x03)
emilmont 27:7110ebee3484 390
emilmont 27:7110ebee3484 391 /** \brief Reverse bit order of value
emilmont 27:7110ebee3484 392
emilmont 27:7110ebee3484 393 This function reverses the bit order of the given value.
emilmont 27:7110ebee3484 394
emilmont 27:7110ebee3484 395 \param [in] value Value to reverse
emilmont 27:7110ebee3484 396 \return Reversed value
emilmont 27:7110ebee3484 397 */
emilmont 27:7110ebee3484 398 __attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
emilmont 27:7110ebee3484 399 {
emilmont 27:7110ebee3484 400 uint32_t result;
emilmont 27:7110ebee3484 401
emilmont 27:7110ebee3484 402 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
emilmont 27:7110ebee3484 403 return(result);
emilmont 27:7110ebee3484 404 }
emilmont 27:7110ebee3484 405
emilmont 27:7110ebee3484 406
emilmont 27:7110ebee3484 407 /** \brief LDR Exclusive (8 bit)
emilmont 27:7110ebee3484 408
emilmont 27:7110ebee3484 409 This function performs a exclusive LDR command for 8 bit value.
emilmont 27:7110ebee3484 410
emilmont 27:7110ebee3484 411 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 412 \return value of type uint8_t at (*ptr)
emilmont 27:7110ebee3484 413 */
emilmont 27:7110ebee3484 414 __attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 27:7110ebee3484 415 {
emilmont 27:7110ebee3484 416 uint8_t result;
emilmont 27:7110ebee3484 417
emilmont 27:7110ebee3484 418 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 27:7110ebee3484 419 return(result);
emilmont 27:7110ebee3484 420 }
emilmont 27:7110ebee3484 421
emilmont 27:7110ebee3484 422
emilmont 27:7110ebee3484 423 /** \brief LDR Exclusive (16 bit)
emilmont 27:7110ebee3484 424
emilmont 27:7110ebee3484 425 This function performs a exclusive LDR command for 16 bit values.
emilmont 27:7110ebee3484 426
emilmont 27:7110ebee3484 427 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 428 \return value of type uint16_t at (*ptr)
emilmont 27:7110ebee3484 429 */
emilmont 27:7110ebee3484 430 __attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 27:7110ebee3484 431 {
emilmont 27:7110ebee3484 432 uint16_t result;
emilmont 27:7110ebee3484 433
emilmont 27:7110ebee3484 434 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 27:7110ebee3484 435 return(result);
emilmont 27:7110ebee3484 436 }
emilmont 27:7110ebee3484 437
emilmont 27:7110ebee3484 438
emilmont 27:7110ebee3484 439 /** \brief LDR Exclusive (32 bit)
emilmont 27:7110ebee3484 440
emilmont 27:7110ebee3484 441 This function performs a exclusive LDR command for 32 bit values.
emilmont 27:7110ebee3484 442
emilmont 27:7110ebee3484 443 \param [in] ptr Pointer to data
emilmont 27:7110ebee3484 444 \return value of type uint32_t at (*ptr)
emilmont 27:7110ebee3484 445 */
emilmont 27:7110ebee3484 446 __attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 27:7110ebee3484 447 {
emilmont 27:7110ebee3484 448 uint32_t result;
emilmont 27:7110ebee3484 449
emilmont 27:7110ebee3484 450 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 27:7110ebee3484 451 return(result);
emilmont 27:7110ebee3484 452 }
emilmont 27:7110ebee3484 453
emilmont 27:7110ebee3484 454
emilmont 27:7110ebee3484 455 /** \brief STR Exclusive (8 bit)
emilmont 27:7110ebee3484 456
emilmont 27:7110ebee3484 457 This function performs a exclusive STR command for 8 bit values.
emilmont 27:7110ebee3484 458
emilmont 27:7110ebee3484 459 \param [in] value Value to store
emilmont 27:7110ebee3484 460 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 461 \return 0 Function succeeded
emilmont 27:7110ebee3484 462 \return 1 Function failed
emilmont 27:7110ebee3484 463 */
emilmont 27:7110ebee3484 464 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 27:7110ebee3484 465 {
emilmont 27:7110ebee3484 466 uint32_t result;
emilmont 27:7110ebee3484 467
emilmont 33:5364839841bd 468 __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 27:7110ebee3484 469 return(result);
emilmont 27:7110ebee3484 470 }
emilmont 27:7110ebee3484 471
emilmont 27:7110ebee3484 472
emilmont 27:7110ebee3484 473 /** \brief STR Exclusive (16 bit)
emilmont 27:7110ebee3484 474
emilmont 27:7110ebee3484 475 This function performs a exclusive STR command for 16 bit values.
emilmont 27:7110ebee3484 476
emilmont 27:7110ebee3484 477 \param [in] value Value to store
emilmont 27:7110ebee3484 478 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 479 \return 0 Function succeeded
emilmont 27:7110ebee3484 480 \return 1 Function failed
emilmont 27:7110ebee3484 481 */
emilmont 27:7110ebee3484 482 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 27:7110ebee3484 483 {
emilmont 27:7110ebee3484 484 uint32_t result;
emilmont 27:7110ebee3484 485
emilmont 33:5364839841bd 486 __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 27:7110ebee3484 487 return(result);
emilmont 27:7110ebee3484 488 }
emilmont 27:7110ebee3484 489
emilmont 27:7110ebee3484 490
emilmont 27:7110ebee3484 491 /** \brief STR Exclusive (32 bit)
emilmont 27:7110ebee3484 492
emilmont 27:7110ebee3484 493 This function performs a exclusive STR command for 32 bit values.
emilmont 27:7110ebee3484 494
emilmont 27:7110ebee3484 495 \param [in] value Value to store
emilmont 27:7110ebee3484 496 \param [in] ptr Pointer to location
emilmont 27:7110ebee3484 497 \return 0 Function succeeded
emilmont 27:7110ebee3484 498 \return 1 Function failed
emilmont 27:7110ebee3484 499 */
emilmont 27:7110ebee3484 500 __attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 27:7110ebee3484 501 {
emilmont 27:7110ebee3484 502 uint32_t result;
emilmont 27:7110ebee3484 503
emilmont 33:5364839841bd 504 __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 27:7110ebee3484 505 return(result);
emilmont 27:7110ebee3484 506 }
emilmont 27:7110ebee3484 507
emilmont 27:7110ebee3484 508
emilmont 27:7110ebee3484 509 /** \brief Remove the exclusive lock
emilmont 27:7110ebee3484 510
emilmont 27:7110ebee3484 511 This function removes the exclusive lock which is created by LDREX.
emilmont 27:7110ebee3484 512
emilmont 27:7110ebee3484 513 */
emilmont 27:7110ebee3484 514 __attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
emilmont 27:7110ebee3484 515 {
emilmont 27:7110ebee3484 516 __ASM volatile ("clrex");
emilmont 27:7110ebee3484 517 }
emilmont 27:7110ebee3484 518
emilmont 27:7110ebee3484 519
emilmont 27:7110ebee3484 520 /** \brief Signed Saturate
emilmont 27:7110ebee3484 521
emilmont 27:7110ebee3484 522 This function saturates a signed value.
emilmont 27:7110ebee3484 523
emilmont 27:7110ebee3484 524 \param [in] value Value to be saturated
emilmont 27:7110ebee3484 525 \param [in] sat Bit position to saturate to (1..32)
emilmont 27:7110ebee3484 526 \return Saturated value
emilmont 27:7110ebee3484 527 */
emilmont 27:7110ebee3484 528 #define __SSAT(ARG1,ARG2) \
emilmont 27:7110ebee3484 529 ({ \
emilmont 27:7110ebee3484 530 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 27:7110ebee3484 531 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 27:7110ebee3484 532 __RES; \
emilmont 27:7110ebee3484 533 })
emilmont 27:7110ebee3484 534
emilmont 27:7110ebee3484 535
emilmont 27:7110ebee3484 536 /** \brief Unsigned Saturate
emilmont 27:7110ebee3484 537
emilmont 27:7110ebee3484 538 This function saturates an unsigned value.
emilmont 27:7110ebee3484 539
emilmont 27:7110ebee3484 540 \param [in] value Value to be saturated
emilmont 27:7110ebee3484 541 \param [in] sat Bit position to saturate to (0..31)
emilmont 27:7110ebee3484 542 \return Saturated value
emilmont 27:7110ebee3484 543 */
emilmont 27:7110ebee3484 544 #define __USAT(ARG1,ARG2) \
emilmont 27:7110ebee3484 545 ({ \
emilmont 27:7110ebee3484 546 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 27:7110ebee3484 547 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 27:7110ebee3484 548 __RES; \
emilmont 27:7110ebee3484 549 })
emilmont 27:7110ebee3484 550
emilmont 27:7110ebee3484 551
emilmont 27:7110ebee3484 552 /** \brief Count leading zeros
emilmont 27:7110ebee3484 553
emilmont 27:7110ebee3484 554 This function counts the number of leading zeros of a data value.
emilmont 27:7110ebee3484 555
emilmont 27:7110ebee3484 556 \param [in] value Value to count the leading zeros
emilmont 27:7110ebee3484 557 \return number of leading zeros in value
emilmont 27:7110ebee3484 558 */
emilmont 27:7110ebee3484 559 __attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
emilmont 27:7110ebee3484 560 {
emilmont 27:7110ebee3484 561 uint8_t result;
emilmont 27:7110ebee3484 562
emilmont 27:7110ebee3484 563 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
emilmont 27:7110ebee3484 564 return(result);
emilmont 27:7110ebee3484 565 }
emilmont 27:7110ebee3484 566
emilmont 27:7110ebee3484 567 #endif /* (__CORTEX_M >= 0x03) */
emilmont 27:7110ebee3484 568
emilmont 27:7110ebee3484 569
emilmont 27:7110ebee3484 570
emilmont 27:7110ebee3484 571
emilmont 33:5364839841bd 572 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 27:7110ebee3484 573 /* TASKING carm specific functions */
emilmont 27:7110ebee3484 574
emilmont 27:7110ebee3484 575 /*
emilmont 27:7110ebee3484 576 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 33:5364839841bd 577 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 27:7110ebee3484 578 * Including the CMSIS ones.
emilmont 27:7110ebee3484 579 */
emilmont 27:7110ebee3484 580
emilmont 27:7110ebee3484 581 #endif
emilmont 27:7110ebee3484 582
emilmont 27:7110ebee3484 583 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 27:7110ebee3484 584
emilmont 33:5364839841bd 585 #endif /* __CORE_CMINSTR_H */