sai kiran
Watchdog Timer
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mbed-src
by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32L4/TARGET_NUCLEO_L476RG/stm32l476xx.h@623:db79ecd649d0, 2015-09-16 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Sep 16 11:15:09 2015 +0100
- Revision:
- 623:db79ecd649d0
Synchronized with git revision 45d00c36b3132acdfcb75bda6258bd8444ac5392
Full URL: https://github.com/mbedmicro/mbed/commit/45d00c36b3132acdfcb75bda6258bd8444ac5392/
[NUCLEO_L476RG] add hal and target files
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 623:db79ecd649d0 | 1 | /** |
| mbed_official | 623:db79ecd649d0 | 2 | ****************************************************************************** |
| mbed_official | 623:db79ecd649d0 | 3 | * @file stm32l476xx.h |
| mbed_official | 623:db79ecd649d0 | 4 | * @author MCD Application Team |
| mbed_official | 623:db79ecd649d0 | 5 | * @version V1.0.0 |
| mbed_official | 623:db79ecd649d0 | 6 | * @date 26-June-2015 |
| mbed_official | 623:db79ecd649d0 | 7 | * @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File. |
| mbed_official | 623:db79ecd649d0 | 8 | * |
| mbed_official | 623:db79ecd649d0 | 9 | * This file contains: |
| mbed_official | 623:db79ecd649d0 | 10 | * - Data structures and the address mapping for all peripherals |
| mbed_official | 623:db79ecd649d0 | 11 | * - Peripheral's registers declarations and bits definition |
| mbed_official | 623:db79ecd649d0 | 12 | * - Macros to access peripherals registers hardware |
| mbed_official | 623:db79ecd649d0 | 13 | * |
| mbed_official | 623:db79ecd649d0 | 14 | ****************************************************************************** |
| mbed_official | 623:db79ecd649d0 | 15 | * @attention |
| mbed_official | 623:db79ecd649d0 | 16 | * |
| mbed_official | 623:db79ecd649d0 | 17 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| mbed_official | 623:db79ecd649d0 | 18 | * |
| mbed_official | 623:db79ecd649d0 | 19 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 623:db79ecd649d0 | 20 | * are permitted provided that the following conditions are met: |
| mbed_official | 623:db79ecd649d0 | 21 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 623:db79ecd649d0 | 22 | * this list of conditions and the following disclaimer. |
| mbed_official | 623:db79ecd649d0 | 23 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 623:db79ecd649d0 | 24 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 623:db79ecd649d0 | 25 | * and/or other materials provided with the distribution. |
| mbed_official | 623:db79ecd649d0 | 26 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 623:db79ecd649d0 | 27 | * may be used to endorse or promote products derived from this software |
| mbed_official | 623:db79ecd649d0 | 28 | * without specific prior written permission. |
| mbed_official | 623:db79ecd649d0 | 29 | * |
| mbed_official | 623:db79ecd649d0 | 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 623:db79ecd649d0 | 31 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 623:db79ecd649d0 | 32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 623:db79ecd649d0 | 33 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 623:db79ecd649d0 | 34 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 623:db79ecd649d0 | 35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 623:db79ecd649d0 | 36 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 623:db79ecd649d0 | 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 623:db79ecd649d0 | 38 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 623:db79ecd649d0 | 39 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 623:db79ecd649d0 | 40 | * |
| mbed_official | 623:db79ecd649d0 | 41 | ****************************************************************************** |
| mbed_official | 623:db79ecd649d0 | 42 | */ |
| mbed_official | 623:db79ecd649d0 | 43 | |
| mbed_official | 623:db79ecd649d0 | 44 | /** @addtogroup CMSIS_Device |
| mbed_official | 623:db79ecd649d0 | 45 | * @{ |
| mbed_official | 623:db79ecd649d0 | 46 | */ |
| mbed_official | 623:db79ecd649d0 | 47 | |
| mbed_official | 623:db79ecd649d0 | 48 | /** @addtogroup stm32l476xx |
| mbed_official | 623:db79ecd649d0 | 49 | * @{ |
| mbed_official | 623:db79ecd649d0 | 50 | */ |
| mbed_official | 623:db79ecd649d0 | 51 | |
| mbed_official | 623:db79ecd649d0 | 52 | #ifndef __STM32L476xx_H |
| mbed_official | 623:db79ecd649d0 | 53 | #define __STM32L476xx_H |
| mbed_official | 623:db79ecd649d0 | 54 | |
| mbed_official | 623:db79ecd649d0 | 55 | #ifdef __cplusplus |
| mbed_official | 623:db79ecd649d0 | 56 | extern "C" { |
| mbed_official | 623:db79ecd649d0 | 57 | #endif /* __cplusplus */ |
| mbed_official | 623:db79ecd649d0 | 58 | |
| mbed_official | 623:db79ecd649d0 | 59 | /** @addtogroup Configuration_section_for_CMSIS |
| mbed_official | 623:db79ecd649d0 | 60 | * @{ |
| mbed_official | 623:db79ecd649d0 | 61 | */ |
| mbed_official | 623:db79ecd649d0 | 62 | |
| mbed_official | 623:db79ecd649d0 | 63 | /** |
| mbed_official | 623:db79ecd649d0 | 64 | * @brief Configuration of the Cortex-M4 Processor and Core Peripherals |
| mbed_official | 623:db79ecd649d0 | 65 | */ |
| mbed_official | 623:db79ecd649d0 | 66 | #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */ |
| mbed_official | 623:db79ecd649d0 | 67 | #define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */ |
| mbed_official | 623:db79ecd649d0 | 68 | #define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */ |
| mbed_official | 623:db79ecd649d0 | 69 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| mbed_official | 623:db79ecd649d0 | 70 | #define __FPU_PRESENT 1 /*!< FPU present */ |
| mbed_official | 623:db79ecd649d0 | 71 | |
| mbed_official | 623:db79ecd649d0 | 72 | /** |
| mbed_official | 623:db79ecd649d0 | 73 | * @} |
| mbed_official | 623:db79ecd649d0 | 74 | */ |
| mbed_official | 623:db79ecd649d0 | 75 | |
| mbed_official | 623:db79ecd649d0 | 76 | /** @addtogroup Peripheral_interrupt_number_definition |
| mbed_official | 623:db79ecd649d0 | 77 | * @{ |
| mbed_official | 623:db79ecd649d0 | 78 | */ |
| mbed_official | 623:db79ecd649d0 | 79 | |
| mbed_official | 623:db79ecd649d0 | 80 | /** |
| mbed_official | 623:db79ecd649d0 | 81 | * @brief STM32L4XX Interrupt Number Definition, according to the selected device |
| mbed_official | 623:db79ecd649d0 | 82 | * in @ref Library_configuration_section |
| mbed_official | 623:db79ecd649d0 | 83 | */ |
| mbed_official | 623:db79ecd649d0 | 84 | typedef enum |
| mbed_official | 623:db79ecd649d0 | 85 | { |
| mbed_official | 623:db79ecd649d0 | 86 | /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 87 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 88 | HardFault_IRQn = -13, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 89 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 90 | BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 91 | UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 92 | SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 93 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 94 | PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 95 | SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 96 | /****** STM32 specific Interrupt Numbers **********************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 97 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 98 | PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */ |
| mbed_official | 623:db79ecd649d0 | 99 | TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ |
| mbed_official | 623:db79ecd649d0 | 100 | RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ |
| mbed_official | 623:db79ecd649d0 | 101 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 102 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 103 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 104 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 105 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 106 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 107 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 108 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 109 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 110 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 111 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 112 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 113 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 114 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 115 | ADC1_2_IRQn = 18, /*!< ADC1, ADC2 SAR global Interrupts */ |
| mbed_official | 623:db79ecd649d0 | 116 | CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 117 | CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 118 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 119 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 120 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| mbed_official | 623:db79ecd649d0 | 121 | TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 122 | TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 123 | TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 124 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 125 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 126 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 127 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 128 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 129 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 130 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 131 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 132 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 133 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 134 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 135 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 136 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 137 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| mbed_official | 623:db79ecd649d0 | 138 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 139 | DFSDM3_IRQn = 42, /*!< SD Filter 3 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 140 | TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 141 | TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 142 | TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 143 | TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 144 | ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 145 | FMC_IRQn = 48, /*!< FMC global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 146 | SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 147 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 148 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 149 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 150 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 151 | TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ |
| mbed_official | 623:db79ecd649d0 | 152 | TIM7_IRQn = 55, /*!< TIM7 global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 153 | DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 154 | DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 155 | DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 156 | DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 157 | DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 158 | DFSDM0_IRQn = 61, /*!< SD Filter 0 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 159 | DFSDM1_IRQn = 62, /*!< SD Filter 1 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 160 | DFSDM2_IRQn = 63, /*!< SD Filter 2 global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 161 | COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */ |
| mbed_official | 623:db79ecd649d0 | 162 | LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */ |
| mbed_official | 623:db79ecd649d0 | 163 | LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */ |
| mbed_official | 623:db79ecd649d0 | 164 | OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 165 | DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 166 | DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 167 | LPUART1_IRQn = 70, /*!< LP UART1 interrupt */ |
| mbed_official | 623:db79ecd649d0 | 168 | QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 169 | I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ |
| mbed_official | 623:db79ecd649d0 | 170 | I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ |
| mbed_official | 623:db79ecd649d0 | 171 | SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 172 | SAI2_IRQn = 75, /*!< Serial Audio Interface 2 global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 173 | SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 174 | TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 175 | LCD_IRQn = 78, /*!< LCD global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 176 | RNG_IRQn = 80, /*!< RNG global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 177 | FPU_IRQn = 81 /*!< FPU global interrupt */ |
| mbed_official | 623:db79ecd649d0 | 178 | } IRQn_Type; |
| mbed_official | 623:db79ecd649d0 | 179 | |
| mbed_official | 623:db79ecd649d0 | 180 | /** |
| mbed_official | 623:db79ecd649d0 | 181 | * @} |
| mbed_official | 623:db79ecd649d0 | 182 | */ |
| mbed_official | 623:db79ecd649d0 | 183 | |
| mbed_official | 623:db79ecd649d0 | 184 | #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ |
| mbed_official | 623:db79ecd649d0 | 185 | #include "system_stm32l4xx.h" |
| mbed_official | 623:db79ecd649d0 | 186 | #include <stdint.h> |
| mbed_official | 623:db79ecd649d0 | 187 | |
| mbed_official | 623:db79ecd649d0 | 188 | /** @addtogroup Peripheral_registers_structures |
| mbed_official | 623:db79ecd649d0 | 189 | * @{ |
| mbed_official | 623:db79ecd649d0 | 190 | */ |
| mbed_official | 623:db79ecd649d0 | 191 | |
| mbed_official | 623:db79ecd649d0 | 192 | /** |
| mbed_official | 623:db79ecd649d0 | 193 | * @brief Analog to Digital Converter |
| mbed_official | 623:db79ecd649d0 | 194 | */ |
| mbed_official | 623:db79ecd649d0 | 195 | |
| mbed_official | 623:db79ecd649d0 | 196 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 197 | { |
| mbed_official | 623:db79ecd649d0 | 198 | __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 199 | __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 200 | __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 201 | __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 202 | __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 203 | __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 204 | __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 205 | uint32_t RESERVED1; /*!< Reserved, 0x01C */ |
| mbed_official | 623:db79ecd649d0 | 206 | __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 207 | __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 208 | __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 209 | uint32_t RESERVED2; /*!< Reserved, 0x02C */ |
| mbed_official | 623:db79ecd649d0 | 210 | __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 211 | __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ |
| mbed_official | 623:db79ecd649d0 | 212 | __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ |
| mbed_official | 623:db79ecd649d0 | 213 | __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ |
| mbed_official | 623:db79ecd649d0 | 214 | __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ |
| mbed_official | 623:db79ecd649d0 | 215 | uint32_t RESERVED3; /*!< Reserved, 0x044 */ |
| mbed_official | 623:db79ecd649d0 | 216 | uint32_t RESERVED4; /*!< Reserved, 0x048 */ |
| mbed_official | 623:db79ecd649d0 | 217 | __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ |
| mbed_official | 623:db79ecd649d0 | 218 | uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */ |
| mbed_official | 623:db79ecd649d0 | 219 | __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ |
| mbed_official | 623:db79ecd649d0 | 220 | __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ |
| mbed_official | 623:db79ecd649d0 | 221 | __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ |
| mbed_official | 623:db79ecd649d0 | 222 | __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ |
| mbed_official | 623:db79ecd649d0 | 223 | uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */ |
| mbed_official | 623:db79ecd649d0 | 224 | __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ |
| mbed_official | 623:db79ecd649d0 | 225 | __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ |
| mbed_official | 623:db79ecd649d0 | 226 | __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ |
| mbed_official | 623:db79ecd649d0 | 227 | __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ |
| mbed_official | 623:db79ecd649d0 | 228 | uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */ |
| mbed_official | 623:db79ecd649d0 | 229 | __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ |
| mbed_official | 623:db79ecd649d0 | 230 | __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ |
| mbed_official | 623:db79ecd649d0 | 231 | uint32_t RESERVED8; /*!< Reserved, 0x0A8 */ |
| mbed_official | 623:db79ecd649d0 | 232 | uint32_t RESERVED9; /*!< Reserved, 0x0AC */ |
| mbed_official | 623:db79ecd649d0 | 233 | __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */ |
| mbed_official | 623:db79ecd649d0 | 234 | __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */ |
| mbed_official | 623:db79ecd649d0 | 235 | |
| mbed_official | 623:db79ecd649d0 | 236 | } ADC_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 237 | |
| mbed_official | 623:db79ecd649d0 | 238 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 239 | { |
| mbed_official | 623:db79ecd649d0 | 240 | __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ |
| mbed_official | 623:db79ecd649d0 | 241 | uint32_t RESERVED; /*!< Reserved, ADC1 base address + 0x304 */ |
| mbed_official | 623:db79ecd649d0 | 242 | __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x308 */ |
| mbed_official | 623:db79ecd649d0 | 243 | __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1 base address + 0x30C */ |
| mbed_official | 623:db79ecd649d0 | 244 | } ADC_Common_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 245 | |
| mbed_official | 623:db79ecd649d0 | 246 | |
| mbed_official | 623:db79ecd649d0 | 247 | /** |
| mbed_official | 623:db79ecd649d0 | 248 | * @brief Controller Area Network TxMailBox |
| mbed_official | 623:db79ecd649d0 | 249 | */ |
| mbed_official | 623:db79ecd649d0 | 250 | |
| mbed_official | 623:db79ecd649d0 | 251 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 252 | { |
| mbed_official | 623:db79ecd649d0 | 253 | __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ |
| mbed_official | 623:db79ecd649d0 | 254 | __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ |
| mbed_official | 623:db79ecd649d0 | 255 | __IO uint32_t TDLR; /*!< CAN mailbox data low register */ |
| mbed_official | 623:db79ecd649d0 | 256 | __IO uint32_t TDHR; /*!< CAN mailbox data high register */ |
| mbed_official | 623:db79ecd649d0 | 257 | } CAN_TxMailBox_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 258 | |
| mbed_official | 623:db79ecd649d0 | 259 | /** |
| mbed_official | 623:db79ecd649d0 | 260 | * @brief Controller Area Network FIFOMailBox |
| mbed_official | 623:db79ecd649d0 | 261 | */ |
| mbed_official | 623:db79ecd649d0 | 262 | |
| mbed_official | 623:db79ecd649d0 | 263 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 264 | { |
| mbed_official | 623:db79ecd649d0 | 265 | __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ |
| mbed_official | 623:db79ecd649d0 | 266 | __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ |
| mbed_official | 623:db79ecd649d0 | 267 | __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ |
| mbed_official | 623:db79ecd649d0 | 268 | __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ |
| mbed_official | 623:db79ecd649d0 | 269 | } CAN_FIFOMailBox_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 270 | |
| mbed_official | 623:db79ecd649d0 | 271 | /** |
| mbed_official | 623:db79ecd649d0 | 272 | * @brief Controller Area Network FilterRegister |
| mbed_official | 623:db79ecd649d0 | 273 | */ |
| mbed_official | 623:db79ecd649d0 | 274 | |
| mbed_official | 623:db79ecd649d0 | 275 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 276 | { |
| mbed_official | 623:db79ecd649d0 | 277 | __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ |
| mbed_official | 623:db79ecd649d0 | 278 | __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ |
| mbed_official | 623:db79ecd649d0 | 279 | } CAN_FilterRegister_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 280 | |
| mbed_official | 623:db79ecd649d0 | 281 | /** |
| mbed_official | 623:db79ecd649d0 | 282 | * @brief Controller Area Network |
| mbed_official | 623:db79ecd649d0 | 283 | */ |
| mbed_official | 623:db79ecd649d0 | 284 | |
| mbed_official | 623:db79ecd649d0 | 285 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 286 | { |
| mbed_official | 623:db79ecd649d0 | 287 | __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 288 | __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 289 | __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 290 | __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 291 | __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 292 | __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 293 | __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 294 | __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 295 | uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ |
| mbed_official | 623:db79ecd649d0 | 296 | CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ |
| mbed_official | 623:db79ecd649d0 | 297 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ |
| mbed_official | 623:db79ecd649d0 | 298 | uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ |
| mbed_official | 623:db79ecd649d0 | 299 | __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ |
| mbed_official | 623:db79ecd649d0 | 300 | __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ |
| mbed_official | 623:db79ecd649d0 | 301 | uint32_t RESERVED2; /*!< Reserved, 0x208 */ |
| mbed_official | 623:db79ecd649d0 | 302 | __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ |
| mbed_official | 623:db79ecd649d0 | 303 | uint32_t RESERVED3; /*!< Reserved, 0x210 */ |
| mbed_official | 623:db79ecd649d0 | 304 | __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ |
| mbed_official | 623:db79ecd649d0 | 305 | uint32_t RESERVED4; /*!< Reserved, 0x218 */ |
| mbed_official | 623:db79ecd649d0 | 306 | __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ |
| mbed_official | 623:db79ecd649d0 | 307 | uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ |
| mbed_official | 623:db79ecd649d0 | 308 | CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ |
| mbed_official | 623:db79ecd649d0 | 309 | } CAN_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 310 | |
| mbed_official | 623:db79ecd649d0 | 311 | |
| mbed_official | 623:db79ecd649d0 | 312 | /** |
| mbed_official | 623:db79ecd649d0 | 313 | * @brief Comparator |
| mbed_official | 623:db79ecd649d0 | 314 | */ |
| mbed_official | 623:db79ecd649d0 | 315 | |
| mbed_official | 623:db79ecd649d0 | 316 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 317 | { |
| mbed_official | 623:db79ecd649d0 | 318 | __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 319 | } COMP_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 320 | |
| mbed_official | 623:db79ecd649d0 | 321 | |
| mbed_official | 623:db79ecd649d0 | 322 | /** |
| mbed_official | 623:db79ecd649d0 | 323 | * @brief CRC calculation unit |
| mbed_official | 623:db79ecd649d0 | 324 | */ |
| mbed_official | 623:db79ecd649d0 | 325 | |
| mbed_official | 623:db79ecd649d0 | 326 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 327 | { |
| mbed_official | 623:db79ecd649d0 | 328 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 329 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 330 | uint8_t RESERVED0; /*!< Reserved, 0x05 */ |
| mbed_official | 623:db79ecd649d0 | 331 | uint16_t RESERVED1; /*!< Reserved, 0x06 */ |
| mbed_official | 623:db79ecd649d0 | 332 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 333 | uint32_t RESERVED2; /*!< Reserved, 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 334 | __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 335 | __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 336 | } CRC_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 337 | |
| mbed_official | 623:db79ecd649d0 | 338 | /** |
| mbed_official | 623:db79ecd649d0 | 339 | * @brief Digital to Analog Converter |
| mbed_official | 623:db79ecd649d0 | 340 | */ |
| mbed_official | 623:db79ecd649d0 | 341 | |
| mbed_official | 623:db79ecd649d0 | 342 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 343 | { |
| mbed_official | 623:db79ecd649d0 | 344 | __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 345 | __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 346 | __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 347 | __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 348 | __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 349 | __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 350 | __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 351 | __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 352 | __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 353 | __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 354 | __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 355 | __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 356 | __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 357 | __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ |
| mbed_official | 623:db79ecd649d0 | 358 | __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ |
| mbed_official | 623:db79ecd649d0 | 359 | __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ |
| mbed_official | 623:db79ecd649d0 | 360 | __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ |
| mbed_official | 623:db79ecd649d0 | 361 | __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ |
| mbed_official | 623:db79ecd649d0 | 362 | __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ |
| mbed_official | 623:db79ecd649d0 | 363 | __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ |
| mbed_official | 623:db79ecd649d0 | 364 | } DAC_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 365 | |
| mbed_official | 623:db79ecd649d0 | 366 | /** |
| mbed_official | 623:db79ecd649d0 | 367 | * @brief DFSDM module registers |
| mbed_official | 623:db79ecd649d0 | 368 | */ |
| mbed_official | 623:db79ecd649d0 | 369 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 370 | { |
| mbed_official | 623:db79ecd649d0 | 371 | __IO uint32_t CR1; /*!< DFSDM control register1, Address offset: 0x100 */ |
| mbed_official | 623:db79ecd649d0 | 372 | __IO uint32_t CR2; /*!< DFSDM control register2, Address offset: 0x104 */ |
| mbed_official | 623:db79ecd649d0 | 373 | __IO uint32_t ISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ |
| mbed_official | 623:db79ecd649d0 | 374 | __IO uint32_t ICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ |
| mbed_official | 623:db79ecd649d0 | 375 | __IO uint32_t JCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ |
| mbed_official | 623:db79ecd649d0 | 376 | __IO uint32_t FCR; /*!< DFSDM filter control register, Address offset: 0x114 */ |
| mbed_official | 623:db79ecd649d0 | 377 | __IO uint32_t JDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ |
| mbed_official | 623:db79ecd649d0 | 378 | __IO uint32_t RDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ |
| mbed_official | 623:db79ecd649d0 | 379 | __IO uint32_t AWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ |
| mbed_official | 623:db79ecd649d0 | 380 | __IO uint32_t AWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ |
| mbed_official | 623:db79ecd649d0 | 381 | __IO uint32_t AWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ |
| mbed_official | 623:db79ecd649d0 | 382 | __IO uint32_t AWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ |
| mbed_official | 623:db79ecd649d0 | 383 | __IO uint32_t EXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ |
| mbed_official | 623:db79ecd649d0 | 384 | __IO uint32_t EXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ |
| mbed_official | 623:db79ecd649d0 | 385 | __IO uint32_t CNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ |
| mbed_official | 623:db79ecd649d0 | 386 | } DFSDM_Filter_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 387 | |
| mbed_official | 623:db79ecd649d0 | 388 | /** |
| mbed_official | 623:db79ecd649d0 | 389 | * @brief DFSDM channel configuration registers |
| mbed_official | 623:db79ecd649d0 | 390 | */ |
| mbed_official | 623:db79ecd649d0 | 391 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 392 | { |
| mbed_official | 623:db79ecd649d0 | 393 | __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 394 | __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 395 | __IO uint32_t AWSCDR; /*!< DFSDM channel analog watchdog and |
| mbed_official | 623:db79ecd649d0 | 396 | short circuit detector register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 397 | __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 398 | __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 399 | } DFSDM_Channel_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 400 | |
| mbed_official | 623:db79ecd649d0 | 401 | /** |
| mbed_official | 623:db79ecd649d0 | 402 | * @brief Debug MCU |
| mbed_official | 623:db79ecd649d0 | 403 | */ |
| mbed_official | 623:db79ecd649d0 | 404 | |
| mbed_official | 623:db79ecd649d0 | 405 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 406 | { |
| mbed_official | 623:db79ecd649d0 | 407 | __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 408 | __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 409 | __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 410 | __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 411 | __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 412 | } DBGMCU_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 413 | |
| mbed_official | 623:db79ecd649d0 | 414 | |
| mbed_official | 623:db79ecd649d0 | 415 | /** |
| mbed_official | 623:db79ecd649d0 | 416 | * @brief DMA Controller |
| mbed_official | 623:db79ecd649d0 | 417 | */ |
| mbed_official | 623:db79ecd649d0 | 418 | |
| mbed_official | 623:db79ecd649d0 | 419 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 420 | { |
| mbed_official | 623:db79ecd649d0 | 421 | __IO uint32_t CCR; /*!< DMA channel x configuration register */ |
| mbed_official | 623:db79ecd649d0 | 422 | __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ |
| mbed_official | 623:db79ecd649d0 | 423 | __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ |
| mbed_official | 623:db79ecd649d0 | 424 | __IO uint32_t CMAR; /*!< DMA channel x memory address register */ |
| mbed_official | 623:db79ecd649d0 | 425 | } DMA_Channel_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 426 | |
| mbed_official | 623:db79ecd649d0 | 427 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 428 | { |
| mbed_official | 623:db79ecd649d0 | 429 | __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 430 | __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 431 | } DMA_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 432 | |
| mbed_official | 623:db79ecd649d0 | 433 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 434 | { |
| mbed_official | 623:db79ecd649d0 | 435 | __IO uint32_t CSELR; /*!< DMA option register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 436 | } DMA_request_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 437 | |
| mbed_official | 623:db79ecd649d0 | 438 | |
| mbed_official | 623:db79ecd649d0 | 439 | /** |
| mbed_official | 623:db79ecd649d0 | 440 | * @brief External Interrupt/Event Controller |
| mbed_official | 623:db79ecd649d0 | 441 | */ |
| mbed_official | 623:db79ecd649d0 | 442 | |
| mbed_official | 623:db79ecd649d0 | 443 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 444 | { |
| mbed_official | 623:db79ecd649d0 | 445 | __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 446 | __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 447 | __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 448 | __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 449 | __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 450 | __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 451 | uint32_t RESERVED1; /*!< Reserved, 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 452 | uint32_t RESERVED2; /*!< Reserved, 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 453 | __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 454 | __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 455 | __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 456 | __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 457 | __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 458 | __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */ |
| mbed_official | 623:db79ecd649d0 | 459 | } EXTI_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 460 | |
| mbed_official | 623:db79ecd649d0 | 461 | |
| mbed_official | 623:db79ecd649d0 | 462 | /** |
| mbed_official | 623:db79ecd649d0 | 463 | * @brief Firewall |
| mbed_official | 623:db79ecd649d0 | 464 | */ |
| mbed_official | 623:db79ecd649d0 | 465 | |
| mbed_official | 623:db79ecd649d0 | 466 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 467 | { |
| mbed_official | 623:db79ecd649d0 | 468 | __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 469 | __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 470 | __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 471 | __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 472 | __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 473 | __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 474 | uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 475 | uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 476 | __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 477 | } FIREWALL_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 478 | |
| mbed_official | 623:db79ecd649d0 | 479 | |
| mbed_official | 623:db79ecd649d0 | 480 | /** |
| mbed_official | 623:db79ecd649d0 | 481 | * @brief FLASH Registers |
| mbed_official | 623:db79ecd649d0 | 482 | */ |
| mbed_official | 623:db79ecd649d0 | 483 | |
| mbed_official | 623:db79ecd649d0 | 484 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 485 | { |
| mbed_official | 623:db79ecd649d0 | 486 | __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 487 | __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 488 | __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 489 | __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 490 | __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 491 | __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 492 | __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 493 | __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 494 | __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 495 | __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 496 | __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 497 | __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 498 | __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 499 | uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */ |
| mbed_official | 623:db79ecd649d0 | 500 | __IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */ |
| mbed_official | 623:db79ecd649d0 | 501 | __IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */ |
| mbed_official | 623:db79ecd649d0 | 502 | __IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */ |
| mbed_official | 623:db79ecd649d0 | 503 | __IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */ |
| mbed_official | 623:db79ecd649d0 | 504 | } FLASH_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 505 | |
| mbed_official | 623:db79ecd649d0 | 506 | |
| mbed_official | 623:db79ecd649d0 | 507 | /** |
| mbed_official | 623:db79ecd649d0 | 508 | * @brief Flexible Memory Controller |
| mbed_official | 623:db79ecd649d0 | 509 | */ |
| mbed_official | 623:db79ecd649d0 | 510 | |
| mbed_official | 623:db79ecd649d0 | 511 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 512 | { |
| mbed_official | 623:db79ecd649d0 | 513 | __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ |
| mbed_official | 623:db79ecd649d0 | 514 | } FMC_Bank1_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 515 | |
| mbed_official | 623:db79ecd649d0 | 516 | /** |
| mbed_official | 623:db79ecd649d0 | 517 | * @brief Flexible Memory Controller Bank1E |
| mbed_official | 623:db79ecd649d0 | 518 | */ |
| mbed_official | 623:db79ecd649d0 | 519 | |
| mbed_official | 623:db79ecd649d0 | 520 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 521 | { |
| mbed_official | 623:db79ecd649d0 | 522 | __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ |
| mbed_official | 623:db79ecd649d0 | 523 | } FMC_Bank1E_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 524 | |
| mbed_official | 623:db79ecd649d0 | 525 | /** |
| mbed_official | 623:db79ecd649d0 | 526 | * @brief Flexible Memory Controller Bank3 |
| mbed_official | 623:db79ecd649d0 | 527 | */ |
| mbed_official | 623:db79ecd649d0 | 528 | |
| mbed_official | 623:db79ecd649d0 | 529 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 530 | { |
| mbed_official | 623:db79ecd649d0 | 531 | __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ |
| mbed_official | 623:db79ecd649d0 | 532 | __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ |
| mbed_official | 623:db79ecd649d0 | 533 | __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ |
| mbed_official | 623:db79ecd649d0 | 534 | __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ |
| mbed_official | 623:db79ecd649d0 | 535 | uint32_t RESERVED0; /*!< Reserved, 0x90 */ |
| mbed_official | 623:db79ecd649d0 | 536 | __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ |
| mbed_official | 623:db79ecd649d0 | 537 | } FMC_Bank3_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 538 | |
| mbed_official | 623:db79ecd649d0 | 539 | /** |
| mbed_official | 623:db79ecd649d0 | 540 | * @brief General Purpose I/O |
| mbed_official | 623:db79ecd649d0 | 541 | */ |
| mbed_official | 623:db79ecd649d0 | 542 | |
| mbed_official | 623:db79ecd649d0 | 543 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 544 | { |
| mbed_official | 623:db79ecd649d0 | 545 | __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 546 | __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 547 | __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 548 | __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 549 | __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 550 | __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 551 | __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 552 | __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 553 | __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ |
| mbed_official | 623:db79ecd649d0 | 554 | __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 555 | __IO uint32_t ASCR; /*!< GPIO analog switch control register, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 556 | |
| mbed_official | 623:db79ecd649d0 | 557 | } GPIO_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 558 | |
| mbed_official | 623:db79ecd649d0 | 559 | |
| mbed_official | 623:db79ecd649d0 | 560 | /** |
| mbed_official | 623:db79ecd649d0 | 561 | * @brief Inter-integrated Circuit Interface |
| mbed_official | 623:db79ecd649d0 | 562 | */ |
| mbed_official | 623:db79ecd649d0 | 563 | |
| mbed_official | 623:db79ecd649d0 | 564 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 565 | { |
| mbed_official | 623:db79ecd649d0 | 566 | __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 567 | __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 568 | __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 569 | __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 570 | __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 571 | __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 572 | __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 573 | __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 574 | __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 575 | __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 576 | __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 577 | } I2C_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 578 | |
| mbed_official | 623:db79ecd649d0 | 579 | /** |
| mbed_official | 623:db79ecd649d0 | 580 | * @brief Independent WATCHDOG |
| mbed_official | 623:db79ecd649d0 | 581 | */ |
| mbed_official | 623:db79ecd649d0 | 582 | |
| mbed_official | 623:db79ecd649d0 | 583 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 584 | { |
| mbed_official | 623:db79ecd649d0 | 585 | __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 586 | __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 587 | __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 588 | __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 589 | __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 590 | } IWDG_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 591 | |
| mbed_official | 623:db79ecd649d0 | 592 | /** |
| mbed_official | 623:db79ecd649d0 | 593 | * @brief LCD |
| mbed_official | 623:db79ecd649d0 | 594 | */ |
| mbed_official | 623:db79ecd649d0 | 595 | |
| mbed_official | 623:db79ecd649d0 | 596 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 597 | { |
| mbed_official | 623:db79ecd649d0 | 598 | __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 599 | __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 600 | __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 601 | __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 602 | uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 603 | __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ |
| mbed_official | 623:db79ecd649d0 | 604 | } LCD_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 605 | |
| mbed_official | 623:db79ecd649d0 | 606 | /** |
| mbed_official | 623:db79ecd649d0 | 607 | * @brief LPTIMER |
| mbed_official | 623:db79ecd649d0 | 608 | */ |
| mbed_official | 623:db79ecd649d0 | 609 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 610 | { |
| mbed_official | 623:db79ecd649d0 | 611 | __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 612 | __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 613 | __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 614 | __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 615 | __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 616 | __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 617 | __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 618 | __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 619 | __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 620 | } LPTIM_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 621 | |
| mbed_official | 623:db79ecd649d0 | 622 | |
| mbed_official | 623:db79ecd649d0 | 623 | /** |
| mbed_official | 623:db79ecd649d0 | 624 | * @brief Operational Amplifier (OPAMP) |
| mbed_official | 623:db79ecd649d0 | 625 | */ |
| mbed_official | 623:db79ecd649d0 | 626 | |
| mbed_official | 623:db79ecd649d0 | 627 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 628 | { |
| mbed_official | 623:db79ecd649d0 | 629 | __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 630 | __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 631 | __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 632 | } OPAMP_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 633 | |
| mbed_official | 623:db79ecd649d0 | 634 | |
| mbed_official | 623:db79ecd649d0 | 635 | /** |
| mbed_official | 623:db79ecd649d0 | 636 | * @brief Power Control |
| mbed_official | 623:db79ecd649d0 | 637 | */ |
| mbed_official | 623:db79ecd649d0 | 638 | |
| mbed_official | 623:db79ecd649d0 | 639 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 640 | { |
| mbed_official | 623:db79ecd649d0 | 641 | __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 642 | __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 643 | __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 644 | __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 645 | __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 646 | __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 647 | __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 648 | uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 649 | __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 650 | __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 651 | __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 652 | __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 653 | __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 654 | __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */ |
| mbed_official | 623:db79ecd649d0 | 655 | __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */ |
| mbed_official | 623:db79ecd649d0 | 656 | __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */ |
| mbed_official | 623:db79ecd649d0 | 657 | __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */ |
| mbed_official | 623:db79ecd649d0 | 658 | __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */ |
| mbed_official | 623:db79ecd649d0 | 659 | __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */ |
| mbed_official | 623:db79ecd649d0 | 660 | __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */ |
| mbed_official | 623:db79ecd649d0 | 661 | __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */ |
| mbed_official | 623:db79ecd649d0 | 662 | __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */ |
| mbed_official | 623:db79ecd649d0 | 663 | __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */ |
| mbed_official | 623:db79ecd649d0 | 664 | __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */ |
| mbed_official | 623:db79ecd649d0 | 665 | } PWR_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 666 | |
| mbed_official | 623:db79ecd649d0 | 667 | |
| mbed_official | 623:db79ecd649d0 | 668 | /** |
| mbed_official | 623:db79ecd649d0 | 669 | * @brief QUAD Serial Peripheral Interface |
| mbed_official | 623:db79ecd649d0 | 670 | */ |
| mbed_official | 623:db79ecd649d0 | 671 | |
| mbed_official | 623:db79ecd649d0 | 672 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 673 | { |
| mbed_official | 623:db79ecd649d0 | 674 | __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 675 | __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 676 | __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 677 | __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 678 | __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 679 | __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 680 | __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 681 | __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 682 | __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 683 | __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 684 | __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 685 | __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 686 | __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 687 | } QUADSPI_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 688 | |
| mbed_official | 623:db79ecd649d0 | 689 | |
| mbed_official | 623:db79ecd649d0 | 690 | /** |
| mbed_official | 623:db79ecd649d0 | 691 | * @brief Reset and Clock Control |
| mbed_official | 623:db79ecd649d0 | 692 | */ |
| mbed_official | 623:db79ecd649d0 | 693 | |
| mbed_official | 623:db79ecd649d0 | 694 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 695 | { |
| mbed_official | 623:db79ecd649d0 | 696 | __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 697 | __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 698 | __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 699 | __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 700 | __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 Configuration Register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 701 | __IO uint32_t PLLSAI2CFGR; /*!< RCC PLL SAI2 Configuration Register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 702 | __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 703 | __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 704 | __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 705 | uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 706 | __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 707 | __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 708 | __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 709 | uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */ |
| mbed_official | 623:db79ecd649d0 | 710 | __IO uint32_t APB1RSTR1; /*!< RCC LowSpeed APB1 macrocells resets Low Word, Address offset: 0x38 */ |
| mbed_official | 623:db79ecd649d0 | 711 | __IO uint32_t APB1RSTR2; /*!< RCC LowSpeed APB1 macrocells resets High Word, Address offset: 0x3C */ |
| mbed_official | 623:db79ecd649d0 | 712 | __IO uint32_t APB2RSTR; /*!< RCC High Speed APB macrocells resets, Address offset: 0x40 */ |
| mbed_official | 623:db79ecd649d0 | 713 | uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */ |
| mbed_official | 623:db79ecd649d0 | 714 | __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock enable register, Address offset: 0x48 */ |
| mbed_official | 623:db79ecd649d0 | 715 | __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock enable register, Address offset: 0x4C */ |
| mbed_official | 623:db79ecd649d0 | 716 | __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock enable register, Address offset: 0x50 */ |
| mbed_official | 623:db79ecd649d0 | 717 | uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */ |
| mbed_official | 623:db79ecd649d0 | 718 | __IO uint32_t APB1ENR1; /*!< RCC LowSpeed APB1 macrocells clock enables Low Word, Address offset: 0x58 */ |
| mbed_official | 623:db79ecd649d0 | 719 | __IO uint32_t APB1ENR2; /*!< RCC LowSpeed APB1 macrocells clock enables High Word, Address offset: 0x5C */ |
| mbed_official | 623:db79ecd649d0 | 720 | __IO uint32_t APB2ENR; /*!< RCC High Speed APB macrocells clock enabled, Address offset: 0x60 */ |
| mbed_official | 623:db79ecd649d0 | 721 | uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */ |
| mbed_official | 623:db79ecd649d0 | 722 | __IO uint32_t AHB1SMENR; /*!< RCC AHB1 macrocells clocks enables in sleep mode, Address offset: 0x60 */ |
| mbed_official | 623:db79ecd649d0 | 723 | __IO uint32_t AHB2SMENR; /*!< RCC AHB2 macrocells clock enables in sleep mode, Address offset: 0x64 */ |
| mbed_official | 623:db79ecd649d0 | 724 | __IO uint32_t AHB3SMENR; /*!< RCC AHB3 macrocells clock enables in sleep mode, Address offset: 0x70 */ |
| mbed_official | 623:db79ecd649d0 | 725 | uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */ |
| mbed_official | 623:db79ecd649d0 | 726 | __IO uint32_t APB1SMENR1; /*!< RCC LowSpeed APB1 macrocells clock enables in sleep mode Low Word, Address offset: 0x78 */ |
| mbed_official | 623:db79ecd649d0 | 727 | __IO uint32_t APB1SMENR2; /*!< RCC LowSpeed APB1 macrocells clock enables in sleep mode High Word, Address offset: 0x7C */ |
| mbed_official | 623:db79ecd649d0 | 728 | __IO uint32_t APB2SMENR; /*!< RCC High Speed APB macrocells clock enabled in sleep mode, Address offset: 0x80 */ |
| mbed_official | 623:db79ecd649d0 | 729 | uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */ |
| mbed_official | 623:db79ecd649d0 | 730 | __IO uint32_t CCIPR; /*!< RCC IPs Clocks Configuration Register, Address offset: 0x88 */ |
| mbed_official | 623:db79ecd649d0 | 731 | __IO uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */ |
| mbed_official | 623:db79ecd649d0 | 732 | __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x90 */ |
| mbed_official | 623:db79ecd649d0 | 733 | __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */ |
| mbed_official | 623:db79ecd649d0 | 734 | } RCC_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 735 | |
| mbed_official | 623:db79ecd649d0 | 736 | /** |
| mbed_official | 623:db79ecd649d0 | 737 | * @brief Real-Time Clock |
| mbed_official | 623:db79ecd649d0 | 738 | */ |
| mbed_official | 623:db79ecd649d0 | 739 | |
| mbed_official | 623:db79ecd649d0 | 740 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 741 | { |
| mbed_official | 623:db79ecd649d0 | 742 | __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 743 | __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 744 | __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 745 | __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 746 | __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 747 | __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 748 | uint32_t reserved; /*!< Reserved */ |
| mbed_official | 623:db79ecd649d0 | 749 | __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 750 | __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 751 | __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 752 | __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 753 | __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 754 | __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 755 | __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ |
| mbed_official | 623:db79ecd649d0 | 756 | __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ |
| mbed_official | 623:db79ecd649d0 | 757 | __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ |
| mbed_official | 623:db79ecd649d0 | 758 | __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ |
| mbed_official | 623:db79ecd649d0 | 759 | __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ |
| mbed_official | 623:db79ecd649d0 | 760 | __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ |
| mbed_official | 623:db79ecd649d0 | 761 | __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ |
| mbed_official | 623:db79ecd649d0 | 762 | __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ |
| mbed_official | 623:db79ecd649d0 | 763 | __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ |
| mbed_official | 623:db79ecd649d0 | 764 | __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ |
| mbed_official | 623:db79ecd649d0 | 765 | __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ |
| mbed_official | 623:db79ecd649d0 | 766 | __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ |
| mbed_official | 623:db79ecd649d0 | 767 | __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ |
| mbed_official | 623:db79ecd649d0 | 768 | __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ |
| mbed_official | 623:db79ecd649d0 | 769 | __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ |
| mbed_official | 623:db79ecd649d0 | 770 | __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ |
| mbed_official | 623:db79ecd649d0 | 771 | __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ |
| mbed_official | 623:db79ecd649d0 | 772 | __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ |
| mbed_official | 623:db79ecd649d0 | 773 | __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ |
| mbed_official | 623:db79ecd649d0 | 774 | __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ |
| mbed_official | 623:db79ecd649d0 | 775 | __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ |
| mbed_official | 623:db79ecd649d0 | 776 | __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ |
| mbed_official | 623:db79ecd649d0 | 777 | __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ |
| mbed_official | 623:db79ecd649d0 | 778 | __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ |
| mbed_official | 623:db79ecd649d0 | 779 | __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ |
| mbed_official | 623:db79ecd649d0 | 780 | __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ |
| mbed_official | 623:db79ecd649d0 | 781 | __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ |
| mbed_official | 623:db79ecd649d0 | 782 | __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ |
| mbed_official | 623:db79ecd649d0 | 783 | __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ |
| mbed_official | 623:db79ecd649d0 | 784 | __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ |
| mbed_official | 623:db79ecd649d0 | 785 | __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ |
| mbed_official | 623:db79ecd649d0 | 786 | __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ |
| mbed_official | 623:db79ecd649d0 | 787 | __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ |
| mbed_official | 623:db79ecd649d0 | 788 | __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ |
| mbed_official | 623:db79ecd649d0 | 789 | __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ |
| mbed_official | 623:db79ecd649d0 | 790 | __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ |
| mbed_official | 623:db79ecd649d0 | 791 | __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ |
| mbed_official | 623:db79ecd649d0 | 792 | __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ |
| mbed_official | 623:db79ecd649d0 | 793 | __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ |
| mbed_official | 623:db79ecd649d0 | 794 | } RTC_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 795 | |
| mbed_official | 623:db79ecd649d0 | 796 | |
| mbed_official | 623:db79ecd649d0 | 797 | /** |
| mbed_official | 623:db79ecd649d0 | 798 | * @brief Serial Audio Interface |
| mbed_official | 623:db79ecd649d0 | 799 | */ |
| mbed_official | 623:db79ecd649d0 | 800 | |
| mbed_official | 623:db79ecd649d0 | 801 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 802 | { |
| mbed_official | 623:db79ecd649d0 | 803 | __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 804 | } SAI_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 805 | |
| mbed_official | 623:db79ecd649d0 | 806 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 807 | { |
| mbed_official | 623:db79ecd649d0 | 808 | __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 809 | __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 810 | __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 811 | __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 812 | __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 813 | __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 814 | __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 815 | __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 816 | } SAI_Block_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 817 | |
| mbed_official | 623:db79ecd649d0 | 818 | |
| mbed_official | 623:db79ecd649d0 | 819 | /** |
| mbed_official | 623:db79ecd649d0 | 820 | * @brief Secure digital input/output Interface |
| mbed_official | 623:db79ecd649d0 | 821 | */ |
| mbed_official | 623:db79ecd649d0 | 822 | |
| mbed_official | 623:db79ecd649d0 | 823 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 824 | { |
| mbed_official | 623:db79ecd649d0 | 825 | __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 826 | __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 827 | __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 828 | __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 829 | __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 830 | __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 831 | __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 832 | __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 833 | __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 834 | __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 835 | __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 836 | __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 837 | __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 838 | __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ |
| mbed_official | 623:db79ecd649d0 | 839 | __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ |
| mbed_official | 623:db79ecd649d0 | 840 | __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ |
| mbed_official | 623:db79ecd649d0 | 841 | uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ |
| mbed_official | 623:db79ecd649d0 | 842 | __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ |
| mbed_official | 623:db79ecd649d0 | 843 | uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ |
| mbed_official | 623:db79ecd649d0 | 844 | __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ |
| mbed_official | 623:db79ecd649d0 | 845 | } SDMMC_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 846 | |
| mbed_official | 623:db79ecd649d0 | 847 | |
| mbed_official | 623:db79ecd649d0 | 848 | /** |
| mbed_official | 623:db79ecd649d0 | 849 | * @brief Serial Peripheral Interface |
| mbed_official | 623:db79ecd649d0 | 850 | */ |
| mbed_official | 623:db79ecd649d0 | 851 | |
| mbed_official | 623:db79ecd649d0 | 852 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 853 | { |
| mbed_official | 623:db79ecd649d0 | 854 | __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 855 | __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 856 | __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 857 | __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 858 | __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 859 | __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 860 | __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 861 | uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 862 | uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 863 | } SPI_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 864 | |
| mbed_official | 623:db79ecd649d0 | 865 | |
| mbed_official | 623:db79ecd649d0 | 866 | /** |
| mbed_official | 623:db79ecd649d0 | 867 | * @brief Single Wire Protocol Master Interface SPWMI |
| mbed_official | 623:db79ecd649d0 | 868 | */ |
| mbed_official | 623:db79ecd649d0 | 869 | |
| mbed_official | 623:db79ecd649d0 | 870 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 871 | { |
| mbed_official | 623:db79ecd649d0 | 872 | __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 873 | __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 874 | uint32_t RESERVED1; /*!< Reserved, 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 875 | __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 876 | __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 877 | __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 878 | __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 879 | __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 880 | __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 881 | __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 882 | } SWPMI_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 883 | |
| mbed_official | 623:db79ecd649d0 | 884 | |
| mbed_official | 623:db79ecd649d0 | 885 | /** |
| mbed_official | 623:db79ecd649d0 | 886 | * @brief System configuration controller |
| mbed_official | 623:db79ecd649d0 | 887 | */ |
| mbed_official | 623:db79ecd649d0 | 888 | |
| mbed_official | 623:db79ecd649d0 | 889 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 890 | { |
| mbed_official | 623:db79ecd649d0 | 891 | __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 892 | __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 893 | __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ |
| mbed_official | 623:db79ecd649d0 | 894 | __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 895 | __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 896 | __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 897 | __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 898 | } SYSCFG_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 899 | |
| mbed_official | 623:db79ecd649d0 | 900 | |
| mbed_official | 623:db79ecd649d0 | 901 | /** |
| mbed_official | 623:db79ecd649d0 | 902 | * @brief TIM |
| mbed_official | 623:db79ecd649d0 | 903 | */ |
| mbed_official | 623:db79ecd649d0 | 904 | |
| mbed_official | 623:db79ecd649d0 | 905 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 906 | { |
| mbed_official | 623:db79ecd649d0 | 907 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 908 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 909 | __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 910 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 911 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 912 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 913 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 914 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 915 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 916 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 917 | __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 918 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 919 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 920 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| mbed_official | 623:db79ecd649d0 | 921 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| mbed_official | 623:db79ecd649d0 | 922 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| mbed_official | 623:db79ecd649d0 | 923 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| mbed_official | 623:db79ecd649d0 | 924 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| mbed_official | 623:db79ecd649d0 | 925 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| mbed_official | 623:db79ecd649d0 | 926 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ |
| mbed_official | 623:db79ecd649d0 | 927 | __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */ |
| mbed_official | 623:db79ecd649d0 | 928 | __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ |
| mbed_official | 623:db79ecd649d0 | 929 | __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */ |
| mbed_official | 623:db79ecd649d0 | 930 | __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */ |
| mbed_official | 623:db79ecd649d0 | 931 | __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */ |
| mbed_official | 623:db79ecd649d0 | 932 | __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */ |
| mbed_official | 623:db79ecd649d0 | 933 | } TIM_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 934 | |
| mbed_official | 623:db79ecd649d0 | 935 | |
| mbed_official | 623:db79ecd649d0 | 936 | /** |
| mbed_official | 623:db79ecd649d0 | 937 | * @brief Touch Sensing Controller (TSC) |
| mbed_official | 623:db79ecd649d0 | 938 | */ |
| mbed_official | 623:db79ecd649d0 | 939 | |
| mbed_official | 623:db79ecd649d0 | 940 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 941 | { |
| mbed_official | 623:db79ecd649d0 | 942 | __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 943 | __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 944 | __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 945 | __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 946 | __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 947 | uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 948 | __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 949 | uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 950 | __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 951 | uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 952 | __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 953 | uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ |
| mbed_official | 623:db79ecd649d0 | 954 | __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ |
| mbed_official | 623:db79ecd649d0 | 955 | __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ |
| mbed_official | 623:db79ecd649d0 | 956 | } TSC_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 957 | |
| mbed_official | 623:db79ecd649d0 | 958 | |
| mbed_official | 623:db79ecd649d0 | 959 | /** |
| mbed_official | 623:db79ecd649d0 | 960 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| mbed_official | 623:db79ecd649d0 | 961 | */ |
| mbed_official | 623:db79ecd649d0 | 962 | |
| mbed_official | 623:db79ecd649d0 | 963 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 964 | { |
| mbed_official | 623:db79ecd649d0 | 965 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 966 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 967 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 968 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ |
| mbed_official | 623:db79ecd649d0 | 969 | __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ |
| mbed_official | 623:db79ecd649d0 | 970 | uint16_t RESERVED2; /*!< Reserved, 0x12 */ |
| mbed_official | 623:db79ecd649d0 | 971 | __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ |
| mbed_official | 623:db79ecd649d0 | 972 | __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */ |
| mbed_official | 623:db79ecd649d0 | 973 | uint16_t RESERVED3; /*!< Reserved, 0x1A */ |
| mbed_official | 623:db79ecd649d0 | 974 | __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ |
| mbed_official | 623:db79ecd649d0 | 975 | __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ |
| mbed_official | 623:db79ecd649d0 | 976 | __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ |
| mbed_official | 623:db79ecd649d0 | 977 | uint16_t RESERVED4; /*!< Reserved, 0x26 */ |
| mbed_official | 623:db79ecd649d0 | 978 | __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ |
| mbed_official | 623:db79ecd649d0 | 979 | uint16_t RESERVED5; /*!< Reserved, 0x2A */ |
| mbed_official | 623:db79ecd649d0 | 980 | } USART_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 981 | |
| mbed_official | 623:db79ecd649d0 | 982 | |
| mbed_official | 623:db79ecd649d0 | 983 | /** |
| mbed_official | 623:db79ecd649d0 | 984 | * @brief VREFBUF |
| mbed_official | 623:db79ecd649d0 | 985 | */ |
| mbed_official | 623:db79ecd649d0 | 986 | |
| mbed_official | 623:db79ecd649d0 | 987 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 988 | { |
| mbed_official | 623:db79ecd649d0 | 989 | __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 990 | __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 991 | } VREFBUF_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 992 | |
| mbed_official | 623:db79ecd649d0 | 993 | /** |
| mbed_official | 623:db79ecd649d0 | 994 | * @brief Window WATCHDOG |
| mbed_official | 623:db79ecd649d0 | 995 | */ |
| mbed_official | 623:db79ecd649d0 | 996 | |
| mbed_official | 623:db79ecd649d0 | 997 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 998 | { |
| mbed_official | 623:db79ecd649d0 | 999 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 1000 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 1001 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 1002 | } WWDG_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 1003 | |
| mbed_official | 623:db79ecd649d0 | 1004 | |
| mbed_official | 623:db79ecd649d0 | 1005 | |
| mbed_official | 623:db79ecd649d0 | 1006 | /** |
| mbed_official | 623:db79ecd649d0 | 1007 | * @brief RNG |
| mbed_official | 623:db79ecd649d0 | 1008 | */ |
| mbed_official | 623:db79ecd649d0 | 1009 | |
| mbed_official | 623:db79ecd649d0 | 1010 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 1011 | { |
| mbed_official | 623:db79ecd649d0 | 1012 | __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ |
| mbed_official | 623:db79ecd649d0 | 1013 | __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ |
| mbed_official | 623:db79ecd649d0 | 1014 | __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ |
| mbed_official | 623:db79ecd649d0 | 1015 | } RNG_TypeDef; |
| mbed_official | 623:db79ecd649d0 | 1016 | |
| mbed_official | 623:db79ecd649d0 | 1017 | /** |
| mbed_official | 623:db79ecd649d0 | 1018 | * @brief USB_OTG_Core_register |
| mbed_official | 623:db79ecd649d0 | 1019 | */ |
| mbed_official | 623:db79ecd649d0 | 1020 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 1021 | { |
| mbed_official | 623:db79ecd649d0 | 1022 | __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h*/ |
| mbed_official | 623:db79ecd649d0 | 1023 | __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h*/ |
| mbed_official | 623:db79ecd649d0 | 1024 | __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h*/ |
| mbed_official | 623:db79ecd649d0 | 1025 | __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1026 | __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h*/ |
| mbed_official | 623:db79ecd649d0 | 1027 | __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h*/ |
| mbed_official | 623:db79ecd649d0 | 1028 | __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h*/ |
| mbed_official | 623:db79ecd649d0 | 1029 | __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1030 | __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h*/ |
| mbed_official | 623:db79ecd649d0 | 1031 | __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ |
| mbed_official | 623:db79ecd649d0 | 1032 | __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h*/ |
| mbed_official | 623:db79ecd649d0 | 1033 | __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1034 | uint32_t Reserved30[2]; /* Reserved 030h*/ |
| mbed_official | 623:db79ecd649d0 | 1035 | __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ |
| mbed_official | 623:db79ecd649d0 | 1036 | __IO uint32_t CID; /* User ID Register 03Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1037 | uint32_t Reserved5[3]; /* Reserved 040h-048h*/ |
| mbed_official | 623:db79ecd649d0 | 1038 | __IO uint32_t GHWCFG3; /* User HW config3 04Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1039 | uint32_t Reserved6; /* Reserved 050h*/ |
| mbed_official | 623:db79ecd649d0 | 1040 | __IO uint32_t GLPMCFG; /* LPM Register 054h*/ |
| mbed_official | 623:db79ecd649d0 | 1041 | __IO uint32_t GPWRDN; /* Power Down Register 058h*/ |
| mbed_official | 623:db79ecd649d0 | 1042 | __IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1043 | __IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1044 | uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/ |
| mbed_official | 623:db79ecd649d0 | 1045 | __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ |
| mbed_official | 623:db79ecd649d0 | 1046 | __IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */ |
| mbed_official | 623:db79ecd649d0 | 1047 | } USB_OTG_GlobalTypeDef; |
| mbed_official | 623:db79ecd649d0 | 1048 | |
| mbed_official | 623:db79ecd649d0 | 1049 | /** |
| mbed_official | 623:db79ecd649d0 | 1050 | * @brief USB_OTG_device_Registers |
| mbed_official | 623:db79ecd649d0 | 1051 | */ |
| mbed_official | 623:db79ecd649d0 | 1052 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 1053 | { |
| mbed_official | 623:db79ecd649d0 | 1054 | __IO uint32_t DCFG; /* dev Configuration Register 800h*/ |
| mbed_official | 623:db79ecd649d0 | 1055 | __IO uint32_t DCTL; /* dev Control Register 804h*/ |
| mbed_official | 623:db79ecd649d0 | 1056 | __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ |
| mbed_official | 623:db79ecd649d0 | 1057 | uint32_t Reserved0C; /* Reserved 80Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1058 | __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ |
| mbed_official | 623:db79ecd649d0 | 1059 | __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ |
| mbed_official | 623:db79ecd649d0 | 1060 | __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ |
| mbed_official | 623:db79ecd649d0 | 1061 | __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1062 | uint32_t Reserved20; /* Reserved 820h*/ |
| mbed_official | 623:db79ecd649d0 | 1063 | uint32_t Reserved9; /* Reserved 824h*/ |
| mbed_official | 623:db79ecd649d0 | 1064 | __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ |
| mbed_official | 623:db79ecd649d0 | 1065 | __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1066 | __IO uint32_t DTHRCTL; /* dev thr 830h*/ |
| mbed_official | 623:db79ecd649d0 | 1067 | __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ |
| mbed_official | 623:db79ecd649d0 | 1068 | __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ |
| mbed_official | 623:db79ecd649d0 | 1069 | __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1070 | uint32_t Reserved40; /* dedicated EP mask 840h*/ |
| mbed_official | 623:db79ecd649d0 | 1071 | __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ |
| mbed_official | 623:db79ecd649d0 | 1072 | uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1073 | __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ |
| mbed_official | 623:db79ecd649d0 | 1074 | } USB_OTG_DeviceTypeDef; |
| mbed_official | 623:db79ecd649d0 | 1075 | |
| mbed_official | 623:db79ecd649d0 | 1076 | /** |
| mbed_official | 623:db79ecd649d0 | 1077 | * @brief USB_OTG_IN_Endpoint-Specific_Register |
| mbed_official | 623:db79ecd649d0 | 1078 | */ |
| mbed_official | 623:db79ecd649d0 | 1079 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 1080 | { |
| mbed_official | 623:db79ecd649d0 | 1081 | __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ |
| mbed_official | 623:db79ecd649d0 | 1082 | uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ |
| mbed_official | 623:db79ecd649d0 | 1083 | __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ |
| mbed_official | 623:db79ecd649d0 | 1084 | uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1085 | __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ |
| mbed_official | 623:db79ecd649d0 | 1086 | __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ |
| mbed_official | 623:db79ecd649d0 | 1087 | __IO uint32_t DTXFSTS; /*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ |
| mbed_official | 623:db79ecd649d0 | 1088 | uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1089 | } USB_OTG_INEndpointTypeDef; |
| mbed_official | 623:db79ecd649d0 | 1090 | |
| mbed_official | 623:db79ecd649d0 | 1091 | /** |
| mbed_official | 623:db79ecd649d0 | 1092 | * @brief USB_OTG_OUT_Endpoint-Specific_Registers |
| mbed_official | 623:db79ecd649d0 | 1093 | */ |
| mbed_official | 623:db79ecd649d0 | 1094 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 1095 | { |
| mbed_official | 623:db79ecd649d0 | 1096 | __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ |
| mbed_official | 623:db79ecd649d0 | 1097 | uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/ |
| mbed_official | 623:db79ecd649d0 | 1098 | __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ |
| mbed_official | 623:db79ecd649d0 | 1099 | uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1100 | __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ |
| mbed_official | 623:db79ecd649d0 | 1101 | __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ |
| mbed_official | 623:db79ecd649d0 | 1102 | uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1103 | } USB_OTG_OUTEndpointTypeDef; |
| mbed_official | 623:db79ecd649d0 | 1104 | |
| mbed_official | 623:db79ecd649d0 | 1105 | /** |
| mbed_official | 623:db79ecd649d0 | 1106 | * @brief USB_OTG_Host_Mode_Register_Structures |
| mbed_official | 623:db79ecd649d0 | 1107 | */ |
| mbed_official | 623:db79ecd649d0 | 1108 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 1109 | { |
| mbed_official | 623:db79ecd649d0 | 1110 | __IO uint32_t HCFG; /* Host Configuration Register 400h*/ |
| mbed_official | 623:db79ecd649d0 | 1111 | __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ |
| mbed_official | 623:db79ecd649d0 | 1112 | __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ |
| mbed_official | 623:db79ecd649d0 | 1113 | uint32_t Reserved40C; /* Reserved 40Ch*/ |
| mbed_official | 623:db79ecd649d0 | 1114 | __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ |
| mbed_official | 623:db79ecd649d0 | 1115 | __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ |
| mbed_official | 623:db79ecd649d0 | 1116 | __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ |
| mbed_official | 623:db79ecd649d0 | 1117 | } USB_OTG_HostTypeDef; |
| mbed_official | 623:db79ecd649d0 | 1118 | |
| mbed_official | 623:db79ecd649d0 | 1119 | /** |
| mbed_official | 623:db79ecd649d0 | 1120 | * @brief USB_OTG_Host_Channel_Specific_Registers |
| mbed_official | 623:db79ecd649d0 | 1121 | */ |
| mbed_official | 623:db79ecd649d0 | 1122 | typedef struct |
| mbed_official | 623:db79ecd649d0 | 1123 | { |
| mbed_official | 623:db79ecd649d0 | 1124 | __IO uint32_t HCCHAR; |
| mbed_official | 623:db79ecd649d0 | 1125 | __IO uint32_t HCSPLT; |
| mbed_official | 623:db79ecd649d0 | 1126 | __IO uint32_t HCINT; |
| mbed_official | 623:db79ecd649d0 | 1127 | __IO uint32_t HCINTMSK; |
| mbed_official | 623:db79ecd649d0 | 1128 | __IO uint32_t HCTSIZ; |
| mbed_official | 623:db79ecd649d0 | 1129 | __IO uint32_t HCDMA; |
| mbed_official | 623:db79ecd649d0 | 1130 | uint32_t Reserved[2]; |
| mbed_official | 623:db79ecd649d0 | 1131 | } USB_OTG_HostChannelTypeDef; |
| mbed_official | 623:db79ecd649d0 | 1132 | |
| mbed_official | 623:db79ecd649d0 | 1133 | /** |
| mbed_official | 623:db79ecd649d0 | 1134 | * @} |
| mbed_official | 623:db79ecd649d0 | 1135 | */ |
| mbed_official | 623:db79ecd649d0 | 1136 | |
| mbed_official | 623:db79ecd649d0 | 1137 | /** @addtogroup Peripheral_memory_map |
| mbed_official | 623:db79ecd649d0 | 1138 | * @{ |
| mbed_official | 623:db79ecd649d0 | 1139 | */ |
| mbed_official | 623:db79ecd649d0 | 1140 | #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address */ |
| mbed_official | 623:db79ecd649d0 | 1141 | #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(96 KB) base address*/ |
| mbed_official | 623:db79ecd649d0 | 1142 | #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address */ |
| mbed_official | 623:db79ecd649d0 | 1143 | #define FMC_BASE ((uint32_t)0x60000000) /*!< FMC base address */ |
| mbed_official | 623:db79ecd649d0 | 1144 | #define SRAM2_BASE ((uint32_t)0x10000000) /*!< SRAM2(32 KB) base address*/ |
| mbed_official | 623:db79ecd649d0 | 1145 | #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC control registers base address */ |
| mbed_official | 623:db79ecd649d0 | 1146 | #define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QUADSPI control registers base address */ |
| mbed_official | 623:db79ecd649d0 | 1147 | #define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(96 KB) base address in the bit-band region */ |
| mbed_official | 623:db79ecd649d0 | 1148 | #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ |
| mbed_official | 623:db79ecd649d0 | 1149 | #define SRAM2_BB_BASE ((uint32_t)0x12000000) /*!< SRAM2(32 KB) base address in the bit-band region */ |
| mbed_official | 623:db79ecd649d0 | 1150 | |
| mbed_official | 623:db79ecd649d0 | 1151 | /* Legacy defines */ |
| mbed_official | 623:db79ecd649d0 | 1152 | #define SRAM_BASE SRAM1_BASE |
| mbed_official | 623:db79ecd649d0 | 1153 | #define SRAM_BB_BASE SRAM1_BB_BASE |
| mbed_official | 623:db79ecd649d0 | 1154 | |
| mbed_official | 623:db79ecd649d0 | 1155 | #define SRAM1_SIZE_MAX ((uint32_t)0x00018000) /*!< maximum SRAM1 size (up to 96 KBytes) */ |
| mbed_official | 623:db79ecd649d0 | 1156 | #define SRAM2_SIZE ((uint32_t)0x00008000) /*!< SRAM2 size (32 KBytes) */ |
| mbed_official | 623:db79ecd649d0 | 1157 | |
| mbed_official | 623:db79ecd649d0 | 1158 | /*!< Peripheral memory map */ |
| mbed_official | 623:db79ecd649d0 | 1159 | #define APB1PERIPH_BASE PERIPH_BASE |
| mbed_official | 623:db79ecd649d0 | 1160 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) |
| mbed_official | 623:db79ecd649d0 | 1161 | #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) |
| mbed_official | 623:db79ecd649d0 | 1162 | #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000) |
| mbed_official | 623:db79ecd649d0 | 1163 | |
| mbed_official | 623:db79ecd649d0 | 1164 | #define FMC_BANK1 FMC_BASE |
| mbed_official | 623:db79ecd649d0 | 1165 | #define FMC_BANK1_1 FMC_BANK1 |
| mbed_official | 623:db79ecd649d0 | 1166 | #define FMC_BANK1_2 (FMC_BANK1 + 0x04000000) |
| mbed_official | 623:db79ecd649d0 | 1167 | #define FMC_BANK1_3 (FMC_BANK1 + 0x08000000) |
| mbed_official | 623:db79ecd649d0 | 1168 | #define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000) |
| mbed_official | 623:db79ecd649d0 | 1169 | #define FMC_BANK3 (FMC_BASE + 0x20000000) |
| mbed_official | 623:db79ecd649d0 | 1170 | |
| mbed_official | 623:db79ecd649d0 | 1171 | /*!< APB1 peripherals */ |
| mbed_official | 623:db79ecd649d0 | 1172 | #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| mbed_official | 623:db79ecd649d0 | 1173 | #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| mbed_official | 623:db79ecd649d0 | 1174 | #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| mbed_official | 623:db79ecd649d0 | 1175 | #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| mbed_official | 623:db79ecd649d0 | 1176 | #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| mbed_official | 623:db79ecd649d0 | 1177 | #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| mbed_official | 623:db79ecd649d0 | 1178 | #define LCD_BASE (APB1PERIPH_BASE + 0x2400) |
| mbed_official | 623:db79ecd649d0 | 1179 | #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| mbed_official | 623:db79ecd649d0 | 1180 | #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| mbed_official | 623:db79ecd649d0 | 1181 | #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| mbed_official | 623:db79ecd649d0 | 1182 | #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| mbed_official | 623:db79ecd649d0 | 1183 | #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| mbed_official | 623:db79ecd649d0 | 1184 | #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| mbed_official | 623:db79ecd649d0 | 1185 | #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| mbed_official | 623:db79ecd649d0 | 1186 | #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| mbed_official | 623:db79ecd649d0 | 1187 | #define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| mbed_official | 623:db79ecd649d0 | 1188 | #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| mbed_official | 623:db79ecd649d0 | 1189 | #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| mbed_official | 623:db79ecd649d0 | 1190 | #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) |
| mbed_official | 623:db79ecd649d0 | 1191 | #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
| mbed_official | 623:db79ecd649d0 | 1192 | #define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00) |
| mbed_official | 623:db79ecd649d0 | 1193 | #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| mbed_official | 623:db79ecd649d0 | 1194 | #define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
| mbed_official | 623:db79ecd649d0 | 1195 | #define DAC1_BASE (APB1PERIPH_BASE + 0x7400) |
| mbed_official | 623:db79ecd649d0 | 1196 | #define OPAMP_BASE (APB1PERIPH_BASE + 0x7800) |
| mbed_official | 623:db79ecd649d0 | 1197 | #define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800) |
| mbed_official | 623:db79ecd649d0 | 1198 | #define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810) |
| mbed_official | 623:db79ecd649d0 | 1199 | #define LPUART1_BASE (APB1PERIPH_BASE + 0x8000) |
| mbed_official | 623:db79ecd649d0 | 1200 | #define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800) |
| mbed_official | 623:db79ecd649d0 | 1201 | #define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400) |
| mbed_official | 623:db79ecd649d0 | 1202 | |
| mbed_official | 623:db79ecd649d0 | 1203 | |
| mbed_official | 623:db79ecd649d0 | 1204 | /*!< APB2 peripherals */ |
| mbed_official | 623:db79ecd649d0 | 1205 | #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) |
| mbed_official | 623:db79ecd649d0 | 1206 | #define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030) |
| mbed_official | 623:db79ecd649d0 | 1207 | #define COMP1_BASE (APB2PERIPH_BASE + 0x0200) |
| mbed_official | 623:db79ecd649d0 | 1208 | #define COMP2_BASE (APB2PERIPH_BASE + 0x0204) |
| mbed_official | 623:db79ecd649d0 | 1209 | #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
| mbed_official | 623:db79ecd649d0 | 1210 | #define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00) |
| mbed_official | 623:db79ecd649d0 | 1211 | #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800) |
| mbed_official | 623:db79ecd649d0 | 1212 | #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
| mbed_official | 623:db79ecd649d0 | 1213 | #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| mbed_official | 623:db79ecd649d0 | 1214 | #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
| mbed_official | 623:db79ecd649d0 | 1215 | #define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
| mbed_official | 623:db79ecd649d0 | 1216 | #define TIM15_BASE (APB2PERIPH_BASE + 0x4000) |
| mbed_official | 623:db79ecd649d0 | 1217 | #define TIM16_BASE (APB2PERIPH_BASE + 0x4400) |
| mbed_official | 623:db79ecd649d0 | 1218 | #define TIM17_BASE (APB2PERIPH_BASE + 0x4800) |
| mbed_official | 623:db79ecd649d0 | 1219 | #define SAI1_BASE (APB2PERIPH_BASE + 0x5400) |
| mbed_official | 623:db79ecd649d0 | 1220 | #define SAI1_Block_A_BASE (SAI1_BASE + 0x004) |
| mbed_official | 623:db79ecd649d0 | 1221 | #define SAI1_Block_B_BASE (SAI1_BASE + 0x024) |
| mbed_official | 623:db79ecd649d0 | 1222 | #define SAI2_BASE (APB2PERIPH_BASE + 0x5800) |
| mbed_official | 623:db79ecd649d0 | 1223 | #define SAI2_Block_A_BASE (SAI2_BASE + 0x004) |
| mbed_official | 623:db79ecd649d0 | 1224 | #define SAI2_Block_B_BASE (SAI2_BASE + 0x024) |
| mbed_official | 623:db79ecd649d0 | 1225 | #define DFSDM_BASE (APB2PERIPH_BASE + 0x6000) |
| mbed_official | 623:db79ecd649d0 | 1226 | #define DFSDM_Channel0_BASE (DFSDM_BASE + 0x00) |
| mbed_official | 623:db79ecd649d0 | 1227 | #define DFSDM_Channel1_BASE (DFSDM_BASE + 0x20) |
| mbed_official | 623:db79ecd649d0 | 1228 | #define DFSDM_Channel2_BASE (DFSDM_BASE + 0x40) |
| mbed_official | 623:db79ecd649d0 | 1229 | #define DFSDM_Channel3_BASE (DFSDM_BASE + 0x60) |
| mbed_official | 623:db79ecd649d0 | 1230 | #define DFSDM_Channel4_BASE (DFSDM_BASE + 0x80) |
| mbed_official | 623:db79ecd649d0 | 1231 | #define DFSDM_Channel5_BASE (DFSDM_BASE + 0xA0) |
| mbed_official | 623:db79ecd649d0 | 1232 | #define DFSDM_Channel6_BASE (DFSDM_BASE + 0xC0) |
| mbed_official | 623:db79ecd649d0 | 1233 | #define DFSDM_Channel7_BASE (DFSDM_BASE + 0xE0) |
| mbed_official | 623:db79ecd649d0 | 1234 | #define DFSDM_Filter0_BASE (DFSDM_BASE + 0x100) |
| mbed_official | 623:db79ecd649d0 | 1235 | #define DFSDM_Filter1_BASE (DFSDM_BASE + 0x180) |
| mbed_official | 623:db79ecd649d0 | 1236 | #define DFSDM_Filter2_BASE (DFSDM_BASE + 0x200) |
| mbed_official | 623:db79ecd649d0 | 1237 | #define DFSDM_Filter3_BASE (DFSDM_BASE + 0x280) |
| mbed_official | 623:db79ecd649d0 | 1238 | |
| mbed_official | 623:db79ecd649d0 | 1239 | /*!< AHB1 peripherals */ |
| mbed_official | 623:db79ecd649d0 | 1240 | #define DMA1_BASE (AHB1PERIPH_BASE) |
| mbed_official | 623:db79ecd649d0 | 1241 | #define DMA2_BASE (AHB1PERIPH_BASE + 0x0400) |
| mbed_official | 623:db79ecd649d0 | 1242 | #define RCC_BASE (AHB1PERIPH_BASE + 0x1000) |
| mbed_official | 623:db79ecd649d0 | 1243 | #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000) |
| mbed_official | 623:db79ecd649d0 | 1244 | #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) |
| mbed_official | 623:db79ecd649d0 | 1245 | #define TSC_BASE (AHB1PERIPH_BASE + 0x4000) |
| mbed_official | 623:db79ecd649d0 | 1246 | |
| mbed_official | 623:db79ecd649d0 | 1247 | |
| mbed_official | 623:db79ecd649d0 | 1248 | #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) |
| mbed_official | 623:db79ecd649d0 | 1249 | #define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) |
| mbed_official | 623:db79ecd649d0 | 1250 | #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) |
| mbed_official | 623:db79ecd649d0 | 1251 | #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) |
| mbed_official | 623:db79ecd649d0 | 1252 | #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) |
| mbed_official | 623:db79ecd649d0 | 1253 | #define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) |
| mbed_official | 623:db79ecd649d0 | 1254 | #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) |
| mbed_official | 623:db79ecd649d0 | 1255 | #define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8) |
| mbed_official | 623:db79ecd649d0 | 1256 | |
| mbed_official | 623:db79ecd649d0 | 1257 | |
| mbed_official | 623:db79ecd649d0 | 1258 | #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008) |
| mbed_official | 623:db79ecd649d0 | 1259 | #define DMA2_Channel2_BASE (DMA2_BASE + 0x001C) |
| mbed_official | 623:db79ecd649d0 | 1260 | #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030) |
| mbed_official | 623:db79ecd649d0 | 1261 | #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044) |
| mbed_official | 623:db79ecd649d0 | 1262 | #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058) |
| mbed_official | 623:db79ecd649d0 | 1263 | #define DMA2_Channel6_BASE (DMA2_BASE + 0x006C) |
| mbed_official | 623:db79ecd649d0 | 1264 | #define DMA2_Channel7_BASE (DMA2_BASE + 0x0080) |
| mbed_official | 623:db79ecd649d0 | 1265 | #define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8) |
| mbed_official | 623:db79ecd649d0 | 1266 | |
| mbed_official | 623:db79ecd649d0 | 1267 | |
| mbed_official | 623:db79ecd649d0 | 1268 | /*!< AHB2 peripherals */ |
| mbed_official | 623:db79ecd649d0 | 1269 | #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000) |
| mbed_official | 623:db79ecd649d0 | 1270 | #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400) |
| mbed_official | 623:db79ecd649d0 | 1271 | #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800) |
| mbed_official | 623:db79ecd649d0 | 1272 | #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00) |
| mbed_official | 623:db79ecd649d0 | 1273 | #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000) |
| mbed_official | 623:db79ecd649d0 | 1274 | #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400) |
| mbed_official | 623:db79ecd649d0 | 1275 | #define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800) |
| mbed_official | 623:db79ecd649d0 | 1276 | #define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00) |
| mbed_official | 623:db79ecd649d0 | 1277 | |
| mbed_official | 623:db79ecd649d0 | 1278 | #define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000) |
| mbed_official | 623:db79ecd649d0 | 1279 | |
| mbed_official | 623:db79ecd649d0 | 1280 | #define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000) |
| mbed_official | 623:db79ecd649d0 | 1281 | #define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100) |
| mbed_official | 623:db79ecd649d0 | 1282 | #define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200) |
| mbed_official | 623:db79ecd649d0 | 1283 | #define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300) |
| mbed_official | 623:db79ecd649d0 | 1284 | |
| mbed_official | 623:db79ecd649d0 | 1285 | #define RNG_BASE (AHB2PERIPH_BASE + 0x08060800) |
| mbed_official | 623:db79ecd649d0 | 1286 | |
| mbed_official | 623:db79ecd649d0 | 1287 | /*!< FMC Banks registers base address */ |
| mbed_official | 623:db79ecd649d0 | 1288 | #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) |
| mbed_official | 623:db79ecd649d0 | 1289 | #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) |
| mbed_official | 623:db79ecd649d0 | 1290 | #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) |
| mbed_official | 623:db79ecd649d0 | 1291 | #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) |
| mbed_official | 623:db79ecd649d0 | 1292 | #define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) |
| mbed_official | 623:db79ecd649d0 | 1293 | |
| mbed_official | 623:db79ecd649d0 | 1294 | /* Debug MCU registers base address */ |
| mbed_official | 623:db79ecd649d0 | 1295 | #define DBGMCU_BASE ((uint32_t )0xE0042000) |
| mbed_official | 623:db79ecd649d0 | 1296 | |
| mbed_official | 623:db79ecd649d0 | 1297 | /*!< USB registers base address */ |
| mbed_official | 623:db79ecd649d0 | 1298 | #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000) |
| mbed_official | 623:db79ecd649d0 | 1299 | |
| mbed_official | 623:db79ecd649d0 | 1300 | #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000) |
| mbed_official | 623:db79ecd649d0 | 1301 | #define USB_OTG_DEVICE_BASE ((uint32_t )0x800) |
| mbed_official | 623:db79ecd649d0 | 1302 | #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900) |
| mbed_official | 623:db79ecd649d0 | 1303 | #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00) |
| mbed_official | 623:db79ecd649d0 | 1304 | #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20) |
| mbed_official | 623:db79ecd649d0 | 1305 | #define USB_OTG_HOST_BASE ((uint32_t )0x400) |
| mbed_official | 623:db79ecd649d0 | 1306 | #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440) |
| mbed_official | 623:db79ecd649d0 | 1307 | #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500) |
| mbed_official | 623:db79ecd649d0 | 1308 | #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20) |
| mbed_official | 623:db79ecd649d0 | 1309 | #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00) |
| mbed_official | 623:db79ecd649d0 | 1310 | #define USB_OTG_FIFO_BASE ((uint32_t )0x1000) |
| mbed_official | 623:db79ecd649d0 | 1311 | #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000) |
| mbed_official | 623:db79ecd649d0 | 1312 | |
| mbed_official | 623:db79ecd649d0 | 1313 | /** |
| mbed_official | 623:db79ecd649d0 | 1314 | * @} |
| mbed_official | 623:db79ecd649d0 | 1315 | */ |
| mbed_official | 623:db79ecd649d0 | 1316 | |
| mbed_official | 623:db79ecd649d0 | 1317 | /** @addtogroup Peripheral_declaration |
| mbed_official | 623:db79ecd649d0 | 1318 | * @{ |
| mbed_official | 623:db79ecd649d0 | 1319 | */ |
| mbed_official | 623:db79ecd649d0 | 1320 | #define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1321 | #define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
| mbed_official | 623:db79ecd649d0 | 1322 | #define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
| mbed_official | 623:db79ecd649d0 | 1323 | #define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
| mbed_official | 623:db79ecd649d0 | 1324 | #define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
| mbed_official | 623:db79ecd649d0 | 1325 | #define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
| mbed_official | 623:db79ecd649d0 | 1326 | #define LCD ((LCD_TypeDef *) LCD_BASE) |
| mbed_official | 623:db79ecd649d0 | 1327 | #define RTC ((RTC_TypeDef *) RTC_BASE) |
| mbed_official | 623:db79ecd649d0 | 1328 | #define WWDG ((WWDG_TypeDef *) WWDG_BASE) |
| mbed_official | 623:db79ecd649d0 | 1329 | #define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
| mbed_official | 623:db79ecd649d0 | 1330 | #define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1331 | #define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
| mbed_official | 623:db79ecd649d0 | 1332 | #define USART2 ((USART_TypeDef *) USART2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1333 | #define USART3 ((USART_TypeDef *) USART3_BASE) |
| mbed_official | 623:db79ecd649d0 | 1334 | #define UART4 ((USART_TypeDef *) UART4_BASE) |
| mbed_official | 623:db79ecd649d0 | 1335 | #define UART5 ((USART_TypeDef *) UART5_BASE) |
| mbed_official | 623:db79ecd649d0 | 1336 | #define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1337 | #define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1338 | #define I2C3 ((I2C_TypeDef *) I2C3_BASE) |
| mbed_official | 623:db79ecd649d0 | 1339 | #define CAN ((CAN_TypeDef *) CAN1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1340 | #define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1341 | #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1342 | #define PWR ((PWR_TypeDef *) PWR_BASE) |
| mbed_official | 623:db79ecd649d0 | 1343 | #define DAC ((DAC_TypeDef *) DAC1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1344 | #define DAC1 ((DAC_TypeDef *) DAC1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1345 | #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) |
| mbed_official | 623:db79ecd649d0 | 1346 | #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1347 | #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1348 | #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1349 | #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1350 | #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1351 | |
| mbed_official | 623:db79ecd649d0 | 1352 | #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
| mbed_official | 623:db79ecd649d0 | 1353 | #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) |
| mbed_official | 623:db79ecd649d0 | 1354 | #define COMP1 ((COMP_TypeDef *) COMP1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1355 | #define COMP2 ((COMP_TypeDef *) COMP2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1356 | #define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
| mbed_official | 623:db79ecd649d0 | 1357 | #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) |
| mbed_official | 623:db79ecd649d0 | 1358 | #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1359 | #define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1360 | #define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1361 | #define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
| mbed_official | 623:db79ecd649d0 | 1362 | #define USART1 ((USART_TypeDef *) USART1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1363 | #define TIM15 ((TIM_TypeDef *) TIM15_BASE) |
| mbed_official | 623:db79ecd649d0 | 1364 | #define TIM16 ((TIM_TypeDef *) TIM16_BASE) |
| mbed_official | 623:db79ecd649d0 | 1365 | #define TIM17 ((TIM_TypeDef *) TIM17_BASE) |
| mbed_official | 623:db79ecd649d0 | 1366 | #define SAI1 ((SAI_TypeDef *) SAI1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1367 | #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) |
| mbed_official | 623:db79ecd649d0 | 1368 | #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) |
| mbed_official | 623:db79ecd649d0 | 1369 | #define SAI2 ((SAI_TypeDef *) SAI2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1370 | #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) |
| mbed_official | 623:db79ecd649d0 | 1371 | #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) |
| mbed_official | 623:db79ecd649d0 | 1372 | #define DFSDM_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE) |
| mbed_official | 623:db79ecd649d0 | 1373 | #define DFSDM_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1374 | #define DFSDM_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM_Channel2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1375 | #define DFSDM_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM_Channel3_BASE) |
| mbed_official | 623:db79ecd649d0 | 1376 | #define DFSDM_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM_Channel4_BASE) |
| mbed_official | 623:db79ecd649d0 | 1377 | #define DFSDM_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM_Channel5_BASE) |
| mbed_official | 623:db79ecd649d0 | 1378 | #define DFSDM_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM_Channel6_BASE) |
| mbed_official | 623:db79ecd649d0 | 1379 | #define DFSDM_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM_Channel7_BASE) |
| mbed_official | 623:db79ecd649d0 | 1380 | #define DFSDM_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM_Filter0_BASE) |
| mbed_official | 623:db79ecd649d0 | 1381 | #define DFSDM_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM_Filter1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1382 | #define DFSDM_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM_Filter2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1383 | #define DFSDM_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM_Filter3_BASE) |
| mbed_official | 623:db79ecd649d0 | 1384 | #define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1385 | #define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1386 | #define RCC ((RCC_TypeDef *) RCC_BASE) |
| mbed_official | 623:db79ecd649d0 | 1387 | #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
| mbed_official | 623:db79ecd649d0 | 1388 | #define CRC ((CRC_TypeDef *) CRC_BASE) |
| mbed_official | 623:db79ecd649d0 | 1389 | #define TSC ((TSC_TypeDef *) TSC_BASE) |
| mbed_official | 623:db79ecd649d0 | 1390 | |
| mbed_official | 623:db79ecd649d0 | 1391 | #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
| mbed_official | 623:db79ecd649d0 | 1392 | #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
| mbed_official | 623:db79ecd649d0 | 1393 | #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
| mbed_official | 623:db79ecd649d0 | 1394 | #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
| mbed_official | 623:db79ecd649d0 | 1395 | #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
| mbed_official | 623:db79ecd649d0 | 1396 | #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
| mbed_official | 623:db79ecd649d0 | 1397 | #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
| mbed_official | 623:db79ecd649d0 | 1398 | #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
| mbed_official | 623:db79ecd649d0 | 1399 | #define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1400 | #define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1401 | #define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
| mbed_official | 623:db79ecd649d0 | 1402 | #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) |
| mbed_official | 623:db79ecd649d0 | 1403 | #define RNG ((RNG_TypeDef *) RNG_BASE) |
| mbed_official | 623:db79ecd649d0 | 1404 | |
| mbed_official | 623:db79ecd649d0 | 1405 | |
| mbed_official | 623:db79ecd649d0 | 1406 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1407 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1408 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) |
| mbed_official | 623:db79ecd649d0 | 1409 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) |
| mbed_official | 623:db79ecd649d0 | 1410 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) |
| mbed_official | 623:db79ecd649d0 | 1411 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) |
| mbed_official | 623:db79ecd649d0 | 1412 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) |
| mbed_official | 623:db79ecd649d0 | 1413 | #define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE) |
| mbed_official | 623:db79ecd649d0 | 1414 | |
| mbed_official | 623:db79ecd649d0 | 1415 | |
| mbed_official | 623:db79ecd649d0 | 1416 | #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) |
| mbed_official | 623:db79ecd649d0 | 1417 | #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) |
| mbed_official | 623:db79ecd649d0 | 1418 | #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) |
| mbed_official | 623:db79ecd649d0 | 1419 | #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) |
| mbed_official | 623:db79ecd649d0 | 1420 | #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) |
| mbed_official | 623:db79ecd649d0 | 1421 | #define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) |
| mbed_official | 623:db79ecd649d0 | 1422 | #define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) |
| mbed_official | 623:db79ecd649d0 | 1423 | #define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE) |
| mbed_official | 623:db79ecd649d0 | 1424 | |
| mbed_official | 623:db79ecd649d0 | 1425 | |
| mbed_official | 623:db79ecd649d0 | 1426 | #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) |
| mbed_official | 623:db79ecd649d0 | 1427 | #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) |
| mbed_official | 623:db79ecd649d0 | 1428 | #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) |
| mbed_official | 623:db79ecd649d0 | 1429 | |
| mbed_official | 623:db79ecd649d0 | 1430 | #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) |
| mbed_official | 623:db79ecd649d0 | 1431 | |
| mbed_official | 623:db79ecd649d0 | 1432 | #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| mbed_official | 623:db79ecd649d0 | 1433 | |
| mbed_official | 623:db79ecd649d0 | 1434 | #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) |
| mbed_official | 623:db79ecd649d0 | 1435 | /** |
| mbed_official | 623:db79ecd649d0 | 1436 | * @} |
| mbed_official | 623:db79ecd649d0 | 1437 | */ |
| mbed_official | 623:db79ecd649d0 | 1438 | |
| mbed_official | 623:db79ecd649d0 | 1439 | /** @addtogroup Exported_constants |
| mbed_official | 623:db79ecd649d0 | 1440 | * @{ |
| mbed_official | 623:db79ecd649d0 | 1441 | */ |
| mbed_official | 623:db79ecd649d0 | 1442 | |
| mbed_official | 623:db79ecd649d0 | 1443 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| mbed_official | 623:db79ecd649d0 | 1444 | * @{ |
| mbed_official | 623:db79ecd649d0 | 1445 | */ |
| mbed_official | 623:db79ecd649d0 | 1446 | |
| mbed_official | 623:db79ecd649d0 | 1447 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 1448 | /* Peripheral Registers_Bits_Definition */ |
| mbed_official | 623:db79ecd649d0 | 1449 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 1450 | |
| mbed_official | 623:db79ecd649d0 | 1451 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 1452 | /* */ |
| mbed_official | 623:db79ecd649d0 | 1453 | /* Analog to Digital Converter */ |
| mbed_official | 623:db79ecd649d0 | 1454 | /* */ |
| mbed_official | 623:db79ecd649d0 | 1455 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 1456 | /******************** Bit definition for ADC_ISR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1457 | #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */ |
| mbed_official | 623:db79ecd649d0 | 1458 | #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */ |
| mbed_official | 623:db79ecd649d0 | 1459 | #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */ |
| mbed_official | 623:db79ecd649d0 | 1460 | #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */ |
| mbed_official | 623:db79ecd649d0 | 1461 | #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */ |
| mbed_official | 623:db79ecd649d0 | 1462 | #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */ |
| mbed_official | 623:db79ecd649d0 | 1463 | #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */ |
| mbed_official | 623:db79ecd649d0 | 1464 | #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */ |
| mbed_official | 623:db79ecd649d0 | 1465 | #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */ |
| mbed_official | 623:db79ecd649d0 | 1466 | #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */ |
| mbed_official | 623:db79ecd649d0 | 1467 | #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */ |
| mbed_official | 623:db79ecd649d0 | 1468 | |
| mbed_official | 623:db79ecd649d0 | 1469 | /******************** Bit definition for ADC_IER register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1470 | #define ADC_IER_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1471 | #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1472 | #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1473 | #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1474 | #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1475 | #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1476 | #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1477 | #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1478 | #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1479 | #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1480 | #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */ |
| mbed_official | 623:db79ecd649d0 | 1481 | |
| mbed_official | 623:db79ecd649d0 | 1482 | /******************** Bit definition for ADC_CR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1483 | #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */ |
| mbed_official | 623:db79ecd649d0 | 1484 | #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */ |
| mbed_official | 623:db79ecd649d0 | 1485 | #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */ |
| mbed_official | 623:db79ecd649d0 | 1486 | #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */ |
| mbed_official | 623:db79ecd649d0 | 1487 | #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */ |
| mbed_official | 623:db79ecd649d0 | 1488 | #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */ |
| mbed_official | 623:db79ecd649d0 | 1489 | #define ADC_CR_ADVREGEN ((uint32_t)0x10000000) /*!< ADC Voltage regulator Enable */ |
| mbed_official | 623:db79ecd649d0 | 1490 | #define ADC_CR_DEEPPWD ((uint32_t)0x20000000) /*!< ADC Deep power down Enable */ |
| mbed_official | 623:db79ecd649d0 | 1491 | #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */ |
| mbed_official | 623:db79ecd649d0 | 1492 | #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */ |
| mbed_official | 623:db79ecd649d0 | 1493 | |
| mbed_official | 623:db79ecd649d0 | 1494 | /******************** Bit definition for ADC_CFGR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1495 | #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */ |
| mbed_official | 623:db79ecd649d0 | 1496 | #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */ |
| mbed_official | 623:db79ecd649d0 | 1497 | |
| mbed_official | 623:db79ecd649d0 | 1498 | #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */ |
| mbed_official | 623:db79ecd649d0 | 1499 | #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1500 | #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1501 | |
| mbed_official | 623:db79ecd649d0 | 1502 | #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */ |
| mbed_official | 623:db79ecd649d0 | 1503 | |
| mbed_official | 623:db79ecd649d0 | 1504 | #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */ |
| mbed_official | 623:db79ecd649d0 | 1505 | #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1506 | #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1507 | #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1508 | #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1509 | |
| mbed_official | 623:db79ecd649d0 | 1510 | #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */ |
| mbed_official | 623:db79ecd649d0 | 1511 | #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1512 | #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1513 | |
| mbed_official | 623:db79ecd649d0 | 1514 | #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */ |
| mbed_official | 623:db79ecd649d0 | 1515 | #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */ |
| mbed_official | 623:db79ecd649d0 | 1516 | #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */ |
| mbed_official | 623:db79ecd649d0 | 1517 | |
| mbed_official | 623:db79ecd649d0 | 1518 | #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */ |
| mbed_official | 623:db79ecd649d0 | 1519 | |
| mbed_official | 623:db79ecd649d0 | 1520 | #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */ |
| mbed_official | 623:db79ecd649d0 | 1521 | #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1522 | #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1523 | #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1524 | |
| mbed_official | 623:db79ecd649d0 | 1525 | #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinuous mode on injected channels */ |
| mbed_official | 623:db79ecd649d0 | 1526 | #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */ |
| mbed_official | 623:db79ecd649d0 | 1527 | #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Enable the watchdog 1 on a single channel or on all channels */ |
| mbed_official | 623:db79ecd649d0 | 1528 | #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */ |
| mbed_official | 623:db79ecd649d0 | 1529 | #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */ |
| mbed_official | 623:db79ecd649d0 | 1530 | #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */ |
| mbed_official | 623:db79ecd649d0 | 1531 | |
| mbed_official | 623:db79ecd649d0 | 1532 | #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */ |
| mbed_official | 623:db79ecd649d0 | 1533 | #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1534 | #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1535 | #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1536 | #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1537 | #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1538 | |
| mbed_official | 623:db79ecd649d0 | 1539 | #define ADC_CFGR_JQDIS ((uint32_t)0x80000000) /*!< ADC Injected queue disable */ |
| mbed_official | 623:db79ecd649d0 | 1540 | |
| mbed_official | 623:db79ecd649d0 | 1541 | /******************** Bit definition for ADC_CFGR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1542 | #define ADC_CFGR2_ROVSE ((uint32_t)0x00000001) /*!< ADC Regular group oversampler enable */ |
| mbed_official | 623:db79ecd649d0 | 1543 | #define ADC_CFGR2_JOVSE ((uint32_t)0x00000002) /*!< ADC Injected group oversampler enable */ |
| mbed_official | 623:db79ecd649d0 | 1544 | |
| mbed_official | 623:db79ecd649d0 | 1545 | #define ADC_CFGR2_OVSR ((uint32_t)0x0000001C) /*!< ADC Regular group oversampler enable */ |
| mbed_official | 623:db79ecd649d0 | 1546 | #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004) /*!< ADC OVSR bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1547 | #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008) /*!< ADC OVSR bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1548 | #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010) /*!< ADC OVSR bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1549 | |
| mbed_official | 623:db79ecd649d0 | 1550 | #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0) /*!< ADC Regular Oversampling shift */ |
| mbed_official | 623:db79ecd649d0 | 1551 | #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020) /*!< ADC OVSS bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1552 | #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040) /*!< ADC OVSS bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1553 | #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080) /*!< ADC OVSS bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1554 | #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100) /*!< ADC OVSS bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1555 | |
| mbed_official | 623:db79ecd649d0 | 1556 | #define ADC_CFGR2_TROVS ((uint32_t)0x00000200) /*!< ADC Triggered regular Oversampling */ |
| mbed_official | 623:db79ecd649d0 | 1557 | #define ADC_CFGR2_ROVSM ((uint32_t)0x00000400) /*!< ADC Regular oversampling mode */ |
| mbed_official | 623:db79ecd649d0 | 1558 | |
| mbed_official | 623:db79ecd649d0 | 1559 | /******************** Bit definition for ADC_SMPR1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1560 | #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1561 | #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1562 | #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1563 | #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1564 | |
| mbed_official | 623:db79ecd649d0 | 1565 | #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1566 | #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1567 | #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1568 | #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1569 | |
| mbed_official | 623:db79ecd649d0 | 1570 | #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1571 | #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1572 | #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1573 | #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1574 | |
| mbed_official | 623:db79ecd649d0 | 1575 | #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1576 | #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1577 | #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1578 | #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1579 | |
| mbed_official | 623:db79ecd649d0 | 1580 | #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1581 | #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1582 | #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1583 | #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1584 | |
| mbed_official | 623:db79ecd649d0 | 1585 | #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1586 | #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1587 | #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1588 | #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1589 | |
| mbed_official | 623:db79ecd649d0 | 1590 | #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1591 | #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1592 | #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1593 | #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1594 | |
| mbed_official | 623:db79ecd649d0 | 1595 | #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1596 | #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1597 | #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1598 | #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1599 | |
| mbed_official | 623:db79ecd649d0 | 1600 | #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1601 | #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1602 | #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1603 | #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1604 | |
| mbed_official | 623:db79ecd649d0 | 1605 | #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1606 | #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1607 | #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1608 | #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1609 | |
| mbed_official | 623:db79ecd649d0 | 1610 | /******************** Bit definition for ADC_SMPR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1611 | #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1612 | #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1613 | #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1614 | #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1615 | |
| mbed_official | 623:db79ecd649d0 | 1616 | #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1617 | #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1618 | #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1619 | #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1620 | |
| mbed_official | 623:db79ecd649d0 | 1621 | #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1622 | #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1623 | #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1624 | #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1625 | |
| mbed_official | 623:db79ecd649d0 | 1626 | #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1627 | #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1628 | #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1629 | #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1630 | |
| mbed_official | 623:db79ecd649d0 | 1631 | #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1632 | #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1633 | #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1634 | #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1635 | |
| mbed_official | 623:db79ecd649d0 | 1636 | #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1637 | #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1638 | #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1639 | #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1640 | |
| mbed_official | 623:db79ecd649d0 | 1641 | #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1642 | #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1643 | #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1644 | #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1645 | |
| mbed_official | 623:db79ecd649d0 | 1646 | #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1647 | #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1648 | #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1649 | #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1650 | |
| mbed_official | 623:db79ecd649d0 | 1651 | #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */ |
| mbed_official | 623:db79ecd649d0 | 1652 | #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1653 | #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1654 | #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1655 | |
| mbed_official | 623:db79ecd649d0 | 1656 | /******************** Bit definition for ADC_TR1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1657 | #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */ |
| mbed_official | 623:db79ecd649d0 | 1658 | #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1659 | #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1660 | #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1661 | #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1662 | #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1663 | #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1664 | #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1665 | #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1666 | #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 1667 | #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 1668 | #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 1669 | #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 1670 | |
| mbed_official | 623:db79ecd649d0 | 1671 | #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */ |
| mbed_official | 623:db79ecd649d0 | 1672 | #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1673 | #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1674 | #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1675 | #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1676 | #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1677 | #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1678 | #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1679 | #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1680 | #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 1681 | #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 1682 | #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 1683 | #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 1684 | |
| mbed_official | 623:db79ecd649d0 | 1685 | /******************** Bit definition for ADC_TR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1686 | #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */ |
| mbed_official | 623:db79ecd649d0 | 1687 | #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1688 | #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1689 | #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1690 | #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1691 | #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1692 | #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1693 | #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1694 | #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1695 | |
| mbed_official | 623:db79ecd649d0 | 1696 | #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */ |
| mbed_official | 623:db79ecd649d0 | 1697 | #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1698 | #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1699 | #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1700 | #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1701 | #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1702 | #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1703 | #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1704 | #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1705 | |
| mbed_official | 623:db79ecd649d0 | 1706 | /******************** Bit definition for ADC_TR3 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1707 | #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */ |
| mbed_official | 623:db79ecd649d0 | 1708 | #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1709 | #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1710 | #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1711 | #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1712 | #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1713 | #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1714 | #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1715 | #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1716 | |
| mbed_official | 623:db79ecd649d0 | 1717 | #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */ |
| mbed_official | 623:db79ecd649d0 | 1718 | #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1719 | #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1720 | #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1721 | #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1722 | #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1723 | #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1724 | #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1725 | #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1726 | |
| mbed_official | 623:db79ecd649d0 | 1727 | /******************** Bit definition for ADC_SQR1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1728 | #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */ |
| mbed_official | 623:db79ecd649d0 | 1729 | #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1730 | #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1731 | #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1732 | #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1733 | |
| mbed_official | 623:db79ecd649d0 | 1734 | #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1735 | #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1736 | #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1737 | #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1738 | #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1739 | #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1740 | |
| mbed_official | 623:db79ecd649d0 | 1741 | #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1742 | #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1743 | #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1744 | #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1745 | #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1746 | #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1747 | |
| mbed_official | 623:db79ecd649d0 | 1748 | #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1749 | #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1750 | #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1751 | #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1752 | #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1753 | #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1754 | |
| mbed_official | 623:db79ecd649d0 | 1755 | #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1756 | #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1757 | #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1758 | #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1759 | #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1760 | #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1761 | |
| mbed_official | 623:db79ecd649d0 | 1762 | /******************** Bit definition for ADC_SQR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1763 | #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1764 | #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1765 | #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1766 | #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1767 | #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1768 | #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1769 | |
| mbed_official | 623:db79ecd649d0 | 1770 | #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1771 | #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1772 | #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1773 | #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1774 | #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1775 | #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1776 | |
| mbed_official | 623:db79ecd649d0 | 1777 | #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1778 | #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1779 | #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1780 | #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1781 | #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1782 | #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1783 | |
| mbed_official | 623:db79ecd649d0 | 1784 | #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1785 | #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1786 | #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1787 | #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1788 | #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1789 | #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1790 | |
| mbed_official | 623:db79ecd649d0 | 1791 | #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1792 | #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1793 | #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1794 | #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1795 | #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1796 | #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1797 | |
| mbed_official | 623:db79ecd649d0 | 1798 | /******************** Bit definition for ADC_SQR3 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1799 | #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1800 | #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1801 | #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1802 | #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1803 | #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1804 | #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1805 | |
| mbed_official | 623:db79ecd649d0 | 1806 | #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1807 | #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1808 | #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1809 | #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1810 | #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1811 | #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1812 | |
| mbed_official | 623:db79ecd649d0 | 1813 | #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1814 | #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1815 | #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1816 | #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1817 | #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1818 | #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1819 | |
| mbed_official | 623:db79ecd649d0 | 1820 | #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1821 | #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1822 | #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1823 | #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1824 | #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1825 | #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1826 | |
| mbed_official | 623:db79ecd649d0 | 1827 | #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1828 | #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1829 | #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1830 | #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1831 | #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1832 | #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1833 | |
| mbed_official | 623:db79ecd649d0 | 1834 | /******************** Bit definition for ADC_SQR4 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1835 | #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1836 | #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1837 | #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1838 | #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1839 | #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1840 | #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1841 | |
| mbed_official | 623:db79ecd649d0 | 1842 | #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */ |
| mbed_official | 623:db79ecd649d0 | 1843 | #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1844 | #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1845 | #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1846 | #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1847 | #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1848 | |
| mbed_official | 623:db79ecd649d0 | 1849 | /******************** Bit definition for ADC_DR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1850 | #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */ |
| mbed_official | 623:db79ecd649d0 | 1851 | #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1852 | #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1853 | #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1854 | #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1855 | #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1856 | #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1857 | #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1858 | #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1859 | #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 1860 | #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 1861 | #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 1862 | #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 1863 | #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 1864 | #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 1865 | #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 1866 | #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 1867 | |
| mbed_official | 623:db79ecd649d0 | 1868 | /******************** Bit definition for ADC_JSQR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1869 | #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */ |
| mbed_official | 623:db79ecd649d0 | 1870 | #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1871 | #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1872 | |
| mbed_official | 623:db79ecd649d0 | 1873 | #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */ |
| mbed_official | 623:db79ecd649d0 | 1874 | #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1875 | #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1876 | #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1877 | #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1878 | |
| mbed_official | 623:db79ecd649d0 | 1879 | #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */ |
| mbed_official | 623:db79ecd649d0 | 1880 | #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1881 | #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1882 | |
| mbed_official | 623:db79ecd649d0 | 1883 | #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */ |
| mbed_official | 623:db79ecd649d0 | 1884 | #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1885 | #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1886 | #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1887 | #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1888 | #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1889 | |
| mbed_official | 623:db79ecd649d0 | 1890 | #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */ |
| mbed_official | 623:db79ecd649d0 | 1891 | #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1892 | #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1893 | #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1894 | #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1895 | #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1896 | |
| mbed_official | 623:db79ecd649d0 | 1897 | #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */ |
| mbed_official | 623:db79ecd649d0 | 1898 | #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1899 | #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1900 | #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1901 | #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1902 | #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1903 | |
| mbed_official | 623:db79ecd649d0 | 1904 | #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */ |
| mbed_official | 623:db79ecd649d0 | 1905 | #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1906 | #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1907 | #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1908 | #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1909 | #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1910 | |
| mbed_official | 623:db79ecd649d0 | 1911 | |
| mbed_official | 623:db79ecd649d0 | 1912 | /******************** Bit definition for ADC_OFR1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1913 | #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ |
| mbed_official | 623:db79ecd649d0 | 1914 | #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1915 | #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1916 | #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1917 | #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1918 | #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1919 | #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1920 | #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1921 | #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1922 | #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 1923 | #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 1924 | #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 1925 | #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 1926 | |
| mbed_official | 623:db79ecd649d0 | 1927 | #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */ |
| mbed_official | 623:db79ecd649d0 | 1928 | #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1929 | #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1930 | #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1931 | #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1932 | #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1933 | |
| mbed_official | 623:db79ecd649d0 | 1934 | #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */ |
| mbed_official | 623:db79ecd649d0 | 1935 | |
| mbed_official | 623:db79ecd649d0 | 1936 | /******************** Bit definition for ADC_OFR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1937 | #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ |
| mbed_official | 623:db79ecd649d0 | 1938 | #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1939 | #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1940 | #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1941 | #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1942 | #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1943 | #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1944 | #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1945 | #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1946 | #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 1947 | #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 1948 | #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 1949 | #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 1950 | |
| mbed_official | 623:db79ecd649d0 | 1951 | #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */ |
| mbed_official | 623:db79ecd649d0 | 1952 | #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1953 | #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1954 | #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1955 | #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1956 | #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1957 | |
| mbed_official | 623:db79ecd649d0 | 1958 | #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */ |
| mbed_official | 623:db79ecd649d0 | 1959 | |
| mbed_official | 623:db79ecd649d0 | 1960 | /******************** Bit definition for ADC_OFR3 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1961 | #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ |
| mbed_official | 623:db79ecd649d0 | 1962 | #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1963 | #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1964 | #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1965 | #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1966 | #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1967 | #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1968 | #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1969 | #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1970 | #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 1971 | #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 1972 | #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 1973 | #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 1974 | |
| mbed_official | 623:db79ecd649d0 | 1975 | #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */ |
| mbed_official | 623:db79ecd649d0 | 1976 | #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1977 | #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1978 | #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1979 | #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1980 | #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1981 | |
| mbed_official | 623:db79ecd649d0 | 1982 | #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */ |
| mbed_official | 623:db79ecd649d0 | 1983 | |
| mbed_official | 623:db79ecd649d0 | 1984 | /******************** Bit definition for ADC_OFR4 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 1985 | #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ |
| mbed_official | 623:db79ecd649d0 | 1986 | #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 1987 | #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 1988 | #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 1989 | #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 1990 | #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 1991 | #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 1992 | #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 1993 | #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 1994 | #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 1995 | #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 1996 | #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 1997 | #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 1998 | |
| mbed_official | 623:db79ecd649d0 | 1999 | #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */ |
| mbed_official | 623:db79ecd649d0 | 2000 | #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2001 | #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2002 | #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2003 | #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2004 | #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2005 | |
| mbed_official | 623:db79ecd649d0 | 2006 | #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */ |
| mbed_official | 623:db79ecd649d0 | 2007 | |
| mbed_official | 623:db79ecd649d0 | 2008 | /******************** Bit definition for ADC_JDR1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2009 | #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ |
| mbed_official | 623:db79ecd649d0 | 2010 | #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2011 | #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2012 | #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2013 | #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2014 | #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2015 | #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2016 | #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2017 | #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2018 | #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2019 | #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2020 | #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2021 | #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2022 | #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2023 | #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2024 | #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2025 | #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2026 | |
| mbed_official | 623:db79ecd649d0 | 2027 | /******************** Bit definition for ADC_JDR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2028 | #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ |
| mbed_official | 623:db79ecd649d0 | 2029 | #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2030 | #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2031 | #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2032 | #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2033 | #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2034 | #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2035 | #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2036 | #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2037 | #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2038 | #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2039 | #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2040 | #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2041 | #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2042 | #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2043 | #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2044 | #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2045 | |
| mbed_official | 623:db79ecd649d0 | 2046 | /******************** Bit definition for ADC_JDR3 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2047 | #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ |
| mbed_official | 623:db79ecd649d0 | 2048 | #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2049 | #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2050 | #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2051 | #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2052 | #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2053 | #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2054 | #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2055 | #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2056 | #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2057 | #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2058 | #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2059 | #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2060 | #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2061 | #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2062 | #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2063 | #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2064 | |
| mbed_official | 623:db79ecd649d0 | 2065 | /******************** Bit definition for ADC_JDR4 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2066 | #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */ |
| mbed_official | 623:db79ecd649d0 | 2067 | #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2068 | #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2069 | #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2070 | #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2071 | #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2072 | #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2073 | #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2074 | #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2075 | #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2076 | #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2077 | #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2078 | #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2079 | #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2080 | #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2081 | #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2082 | #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2083 | |
| mbed_official | 623:db79ecd649d0 | 2084 | /******************** Bit definition for ADC_AWD2CR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2085 | #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFF) /*!< ADC Analog watchdog 2 channel selection */ |
| mbed_official | 623:db79ecd649d0 | 2086 | #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000001) /*!< ADC AWD2CH bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2087 | #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2088 | #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2089 | #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2090 | #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2091 | #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2092 | #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2093 | #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2094 | #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2095 | #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2096 | #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2097 | #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2098 | #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2099 | #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2100 | #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2101 | #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2102 | #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2103 | #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2104 | #define ADC_AWD2CR_AWD2CH_18 ((uint32_t)0x00040000) /*!< ADC AWD2CH bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2105 | |
| mbed_official | 623:db79ecd649d0 | 2106 | /******************** Bit definition for ADC_AWD3CR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2107 | #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFF) /*!< ADC Analog watchdog 3 channel selection */ |
| mbed_official | 623:db79ecd649d0 | 2108 | #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000001) /*!< ADC AWD3CH bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2109 | #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2110 | #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2111 | #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2112 | #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2113 | #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2114 | #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2115 | #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2116 | #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2117 | #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2118 | #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2119 | #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2120 | #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2121 | #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2122 | #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2123 | #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2124 | #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2125 | #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2126 | #define ADC_AWD3CR_AWD3CH_18 ((uint32_t)0x00040000) /*!< ADC AWD3CH bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2127 | |
| mbed_official | 623:db79ecd649d0 | 2128 | /******************** Bit definition for ADC_DIFSEL register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2129 | #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFF) /*!< ADC differential modes for channels 1 to 18 */ |
| mbed_official | 623:db79ecd649d0 | 2130 | #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000001) /*!< ADC DIFSEL bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2131 | #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2132 | #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2133 | #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2134 | #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2135 | #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2136 | #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2137 | #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2138 | #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2139 | #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2140 | #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2141 | #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2142 | #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2143 | #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2144 | #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2145 | #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2146 | #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2147 | #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2148 | #define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00040000) /*!< ADC DIFSEL bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2149 | |
| mbed_official | 623:db79ecd649d0 | 2150 | /******************** Bit definition for ADC_CALFACT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2151 | #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */ |
| mbed_official | 623:db79ecd649d0 | 2152 | #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2153 | #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2154 | #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2155 | #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2156 | #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2157 | #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2158 | #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2159 | |
| mbed_official | 623:db79ecd649d0 | 2160 | #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */ |
| mbed_official | 623:db79ecd649d0 | 2161 | #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2162 | #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2163 | #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2164 | #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2165 | #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2166 | #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2167 | #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2168 | |
| mbed_official | 623:db79ecd649d0 | 2169 | /************************* ADC Common registers *****************************/ |
| mbed_official | 623:db79ecd649d0 | 2170 | /******************** Bit definition for ADC_CSR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2171 | #define ADC_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */ |
| mbed_official | 623:db79ecd649d0 | 2172 | #define ADC_CSR_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2173 | #define ADC_CSR_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2174 | #define ADC_CSR_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2175 | #define ADC_CSR_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2176 | #define ADC_CSR_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2177 | #define ADC_CSR_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2178 | #define ADC_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2179 | #define ADC_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2180 | #define ADC_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2181 | #define ADC_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2182 | |
| mbed_official | 623:db79ecd649d0 | 2183 | #define ADC_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */ |
| mbed_official | 623:db79ecd649d0 | 2184 | #define ADC_CSR_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */ |
| mbed_official | 623:db79ecd649d0 | 2185 | #define ADC_CSR_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */ |
| mbed_official | 623:db79ecd649d0 | 2186 | #define ADC_CSR_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */ |
| mbed_official | 623:db79ecd649d0 | 2187 | #define ADC_CSR_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */ |
| mbed_official | 623:db79ecd649d0 | 2188 | #define ADC_CSR_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */ |
| mbed_official | 623:db79ecd649d0 | 2189 | #define ADC_CSR_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */ |
| mbed_official | 623:db79ecd649d0 | 2190 | #define ADC_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */ |
| mbed_official | 623:db79ecd649d0 | 2191 | #define ADC_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */ |
| mbed_official | 623:db79ecd649d0 | 2192 | #define ADC_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */ |
| mbed_official | 623:db79ecd649d0 | 2193 | #define ADC_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */ |
| mbed_official | 623:db79ecd649d0 | 2194 | |
| mbed_official | 623:db79ecd649d0 | 2195 | /******************** Bit definition for ADC_CCR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2196 | #define ADC_CCR_DUAL ((uint32_t)0x0000001F) /*!< Dual ADC mode selection */ |
| mbed_official | 623:db79ecd649d0 | 2197 | #define ADC_CCR_DUAL_0 ((uint32_t)0x00000001) /*!< Dual bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2198 | #define ADC_CCR_DUAL_1 ((uint32_t)0x00000002) /*!< Dual bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2199 | #define ADC_CCR_DUAL_2 ((uint32_t)0x00000004) /*!< Dual bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2200 | #define ADC_CCR_DUAL_3 ((uint32_t)0x00000008) /*!< Dual bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2201 | #define ADC_CCR_DUAL_4 ((uint32_t)0x00000010) /*!< Dual bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2202 | |
| mbed_official | 623:db79ecd649d0 | 2203 | #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */ |
| mbed_official | 623:db79ecd649d0 | 2204 | #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2205 | #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2206 | #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2207 | #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2208 | |
| mbed_official | 623:db79ecd649d0 | 2209 | #define ADC_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */ |
| mbed_official | 623:db79ecd649d0 | 2210 | |
| mbed_official | 623:db79ecd649d0 | 2211 | #define ADC_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */ |
| mbed_official | 623:db79ecd649d0 | 2212 | #define ADC_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2213 | #define ADC_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2214 | |
| mbed_official | 623:db79ecd649d0 | 2215 | #define ADC_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */ |
| mbed_official | 623:db79ecd649d0 | 2216 | #define ADC_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2217 | #define ADC_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2218 | |
| mbed_official | 623:db79ecd649d0 | 2219 | #define ADC_CCR_PRESC ((uint32_t)0x003C0000) /*!< ADC prescaler */ |
| mbed_official | 623:db79ecd649d0 | 2220 | #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000) /*!< ADC prescaler bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2221 | #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000) /*!< ADC prescaler bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2222 | #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000) /*!< ADC prescaler bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2223 | #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000) /*!< ADC prescaler bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2224 | |
| mbed_official | 623:db79ecd649d0 | 2225 | #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */ |
| mbed_official | 623:db79ecd649d0 | 2226 | #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */ |
| mbed_official | 623:db79ecd649d0 | 2227 | #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */ |
| mbed_official | 623:db79ecd649d0 | 2228 | |
| mbed_official | 623:db79ecd649d0 | 2229 | /******************** Bit definition for ADC_CDR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2230 | #define ADC_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2231 | #define ADC_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2232 | #define ADC_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2233 | #define ADC_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2234 | #define ADC_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2235 | #define ADC_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2236 | #define ADC_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2237 | #define ADC_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2238 | #define ADC_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2239 | #define ADC_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2240 | #define ADC_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2241 | #define ADC_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2242 | #define ADC_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2243 | #define ADC_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2244 | #define ADC_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2245 | #define ADC_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2246 | #define ADC_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2247 | |
| mbed_official | 623:db79ecd649d0 | 2248 | #define ADC_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */ |
| mbed_official | 623:db79ecd649d0 | 2249 | #define ADC_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2250 | #define ADC_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2251 | #define ADC_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2252 | #define ADC_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2253 | #define ADC_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2254 | #define ADC_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2255 | #define ADC_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2256 | #define ADC_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2257 | #define ADC_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2258 | #define ADC_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2259 | #define ADC_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2260 | #define ADC_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2261 | #define ADC_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2262 | #define ADC_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2263 | #define ADC_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2264 | #define ADC_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2265 | |
| mbed_official | 623:db79ecd649d0 | 2266 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 2267 | /* */ |
| mbed_official | 623:db79ecd649d0 | 2268 | /* Controller Area Network */ |
| mbed_official | 623:db79ecd649d0 | 2269 | /* */ |
| mbed_official | 623:db79ecd649d0 | 2270 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 2271 | /*!<CAN control and status registers */ |
| mbed_official | 623:db79ecd649d0 | 2272 | /******************* Bit definition for CAN_MCR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2273 | #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */ |
| mbed_official | 623:db79ecd649d0 | 2274 | #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */ |
| mbed_official | 623:db79ecd649d0 | 2275 | #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */ |
| mbed_official | 623:db79ecd649d0 | 2276 | #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */ |
| mbed_official | 623:db79ecd649d0 | 2277 | #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */ |
| mbed_official | 623:db79ecd649d0 | 2278 | #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */ |
| mbed_official | 623:db79ecd649d0 | 2279 | #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */ |
| mbed_official | 623:db79ecd649d0 | 2280 | #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */ |
| mbed_official | 623:db79ecd649d0 | 2281 | #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */ |
| mbed_official | 623:db79ecd649d0 | 2282 | |
| mbed_official | 623:db79ecd649d0 | 2283 | /******************* Bit definition for CAN_MSR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2284 | #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */ |
| mbed_official | 623:db79ecd649d0 | 2285 | #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */ |
| mbed_official | 623:db79ecd649d0 | 2286 | #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 2287 | #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 2288 | #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 2289 | #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */ |
| mbed_official | 623:db79ecd649d0 | 2290 | #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */ |
| mbed_official | 623:db79ecd649d0 | 2291 | #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */ |
| mbed_official | 623:db79ecd649d0 | 2292 | #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */ |
| mbed_official | 623:db79ecd649d0 | 2293 | |
| mbed_official | 623:db79ecd649d0 | 2294 | /******************* Bit definition for CAN_TSR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2295 | #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */ |
| mbed_official | 623:db79ecd649d0 | 2296 | #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */ |
| mbed_official | 623:db79ecd649d0 | 2297 | #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */ |
| mbed_official | 623:db79ecd649d0 | 2298 | #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */ |
| mbed_official | 623:db79ecd649d0 | 2299 | #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */ |
| mbed_official | 623:db79ecd649d0 | 2300 | #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */ |
| mbed_official | 623:db79ecd649d0 | 2301 | #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */ |
| mbed_official | 623:db79ecd649d0 | 2302 | #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */ |
| mbed_official | 623:db79ecd649d0 | 2303 | #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */ |
| mbed_official | 623:db79ecd649d0 | 2304 | #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */ |
| mbed_official | 623:db79ecd649d0 | 2305 | #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */ |
| mbed_official | 623:db79ecd649d0 | 2306 | #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */ |
| mbed_official | 623:db79ecd649d0 | 2307 | #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */ |
| mbed_official | 623:db79ecd649d0 | 2308 | #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */ |
| mbed_official | 623:db79ecd649d0 | 2309 | #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */ |
| mbed_official | 623:db79ecd649d0 | 2310 | #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */ |
| mbed_official | 623:db79ecd649d0 | 2311 | |
| mbed_official | 623:db79ecd649d0 | 2312 | #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */ |
| mbed_official | 623:db79ecd649d0 | 2313 | #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */ |
| mbed_official | 623:db79ecd649d0 | 2314 | #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */ |
| mbed_official | 623:db79ecd649d0 | 2315 | #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */ |
| mbed_official | 623:db79ecd649d0 | 2316 | |
| mbed_official | 623:db79ecd649d0 | 2317 | #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */ |
| mbed_official | 623:db79ecd649d0 | 2318 | #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */ |
| mbed_official | 623:db79ecd649d0 | 2319 | #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */ |
| mbed_official | 623:db79ecd649d0 | 2320 | #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */ |
| mbed_official | 623:db79ecd649d0 | 2321 | |
| mbed_official | 623:db79ecd649d0 | 2322 | /******************* Bit definition for CAN_RF0R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2323 | #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */ |
| mbed_official | 623:db79ecd649d0 | 2324 | #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */ |
| mbed_official | 623:db79ecd649d0 | 2325 | #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */ |
| mbed_official | 623:db79ecd649d0 | 2326 | #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */ |
| mbed_official | 623:db79ecd649d0 | 2327 | |
| mbed_official | 623:db79ecd649d0 | 2328 | /******************* Bit definition for CAN_RF1R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2329 | #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */ |
| mbed_official | 623:db79ecd649d0 | 2330 | #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */ |
| mbed_official | 623:db79ecd649d0 | 2331 | #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */ |
| mbed_official | 623:db79ecd649d0 | 2332 | #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */ |
| mbed_official | 623:db79ecd649d0 | 2333 | |
| mbed_official | 623:db79ecd649d0 | 2334 | /******************** Bit definition for CAN_IER register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2335 | #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2336 | #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2337 | #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2338 | #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2339 | #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2340 | #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2341 | #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2342 | #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2343 | #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2344 | #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2345 | #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2346 | #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2347 | #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2348 | #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 2349 | |
| mbed_official | 623:db79ecd649d0 | 2350 | /******************** Bit definition for CAN_ESR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2351 | #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */ |
| mbed_official | 623:db79ecd649d0 | 2352 | #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */ |
| mbed_official | 623:db79ecd649d0 | 2353 | #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */ |
| mbed_official | 623:db79ecd649d0 | 2354 | |
| mbed_official | 623:db79ecd649d0 | 2355 | #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */ |
| mbed_official | 623:db79ecd649d0 | 2356 | #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2357 | #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2358 | #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2359 | |
| mbed_official | 623:db79ecd649d0 | 2360 | #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */ |
| mbed_official | 623:db79ecd649d0 | 2361 | #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */ |
| mbed_official | 623:db79ecd649d0 | 2362 | |
| mbed_official | 623:db79ecd649d0 | 2363 | /******************* Bit definition for CAN_BTR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2364 | #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */ |
| mbed_official | 623:db79ecd649d0 | 2365 | #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */ |
| mbed_official | 623:db79ecd649d0 | 2366 | #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */ |
| mbed_official | 623:db79ecd649d0 | 2367 | #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */ |
| mbed_official | 623:db79ecd649d0 | 2368 | #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */ |
| mbed_official | 623:db79ecd649d0 | 2369 | #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */ |
| mbed_official | 623:db79ecd649d0 | 2370 | #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */ |
| mbed_official | 623:db79ecd649d0 | 2371 | #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */ |
| mbed_official | 623:db79ecd649d0 | 2372 | #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */ |
| mbed_official | 623:db79ecd649d0 | 2373 | #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */ |
| mbed_official | 623:db79ecd649d0 | 2374 | #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */ |
| mbed_official | 623:db79ecd649d0 | 2375 | #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */ |
| mbed_official | 623:db79ecd649d0 | 2376 | #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */ |
| mbed_official | 623:db79ecd649d0 | 2377 | #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */ |
| mbed_official | 623:db79ecd649d0 | 2378 | #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */ |
| mbed_official | 623:db79ecd649d0 | 2379 | |
| mbed_official | 623:db79ecd649d0 | 2380 | /*!<Mailbox registers */ |
| mbed_official | 623:db79ecd649d0 | 2381 | /****************** Bit definition for CAN_TI0R register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2382 | #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
| mbed_official | 623:db79ecd649d0 | 2383 | #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
| mbed_official | 623:db79ecd649d0 | 2384 | #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
| mbed_official | 623:db79ecd649d0 | 2385 | #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
| mbed_official | 623:db79ecd649d0 | 2386 | #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 623:db79ecd649d0 | 2387 | |
| mbed_official | 623:db79ecd649d0 | 2388 | /****************** Bit definition for CAN_TDT0R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2389 | #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
| mbed_official | 623:db79ecd649d0 | 2390 | #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
| mbed_official | 623:db79ecd649d0 | 2391 | #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
| mbed_official | 623:db79ecd649d0 | 2392 | |
| mbed_official | 623:db79ecd649d0 | 2393 | /****************** Bit definition for CAN_TDL0R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2394 | #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
| mbed_official | 623:db79ecd649d0 | 2395 | #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
| mbed_official | 623:db79ecd649d0 | 2396 | #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
| mbed_official | 623:db79ecd649d0 | 2397 | #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
| mbed_official | 623:db79ecd649d0 | 2398 | |
| mbed_official | 623:db79ecd649d0 | 2399 | /****************** Bit definition for CAN_TDH0R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2400 | #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
| mbed_official | 623:db79ecd649d0 | 2401 | #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
| mbed_official | 623:db79ecd649d0 | 2402 | #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
| mbed_official | 623:db79ecd649d0 | 2403 | #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
| mbed_official | 623:db79ecd649d0 | 2404 | |
| mbed_official | 623:db79ecd649d0 | 2405 | /******************* Bit definition for CAN_TI1R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2406 | #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
| mbed_official | 623:db79ecd649d0 | 2407 | #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
| mbed_official | 623:db79ecd649d0 | 2408 | #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
| mbed_official | 623:db79ecd649d0 | 2409 | #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
| mbed_official | 623:db79ecd649d0 | 2410 | #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 623:db79ecd649d0 | 2411 | |
| mbed_official | 623:db79ecd649d0 | 2412 | /******************* Bit definition for CAN_TDT1R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2413 | #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
| mbed_official | 623:db79ecd649d0 | 2414 | #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
| mbed_official | 623:db79ecd649d0 | 2415 | #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
| mbed_official | 623:db79ecd649d0 | 2416 | |
| mbed_official | 623:db79ecd649d0 | 2417 | /******************* Bit definition for CAN_TDL1R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2418 | #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
| mbed_official | 623:db79ecd649d0 | 2419 | #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
| mbed_official | 623:db79ecd649d0 | 2420 | #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
| mbed_official | 623:db79ecd649d0 | 2421 | #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
| mbed_official | 623:db79ecd649d0 | 2422 | |
| mbed_official | 623:db79ecd649d0 | 2423 | /******************* Bit definition for CAN_TDH1R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2424 | #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
| mbed_official | 623:db79ecd649d0 | 2425 | #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
| mbed_official | 623:db79ecd649d0 | 2426 | #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
| mbed_official | 623:db79ecd649d0 | 2427 | #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
| mbed_official | 623:db79ecd649d0 | 2428 | |
| mbed_official | 623:db79ecd649d0 | 2429 | /******************* Bit definition for CAN_TI2R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2430 | #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */ |
| mbed_official | 623:db79ecd649d0 | 2431 | #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
| mbed_official | 623:db79ecd649d0 | 2432 | #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
| mbed_official | 623:db79ecd649d0 | 2433 | #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
| mbed_official | 623:db79ecd649d0 | 2434 | #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 623:db79ecd649d0 | 2435 | |
| mbed_official | 623:db79ecd649d0 | 2436 | /******************* Bit definition for CAN_TDT2R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2437 | #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
| mbed_official | 623:db79ecd649d0 | 2438 | #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */ |
| mbed_official | 623:db79ecd649d0 | 2439 | #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
| mbed_official | 623:db79ecd649d0 | 2440 | |
| mbed_official | 623:db79ecd649d0 | 2441 | /******************* Bit definition for CAN_TDL2R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2442 | #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
| mbed_official | 623:db79ecd649d0 | 2443 | #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
| mbed_official | 623:db79ecd649d0 | 2444 | #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
| mbed_official | 623:db79ecd649d0 | 2445 | #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
| mbed_official | 623:db79ecd649d0 | 2446 | |
| mbed_official | 623:db79ecd649d0 | 2447 | /******************* Bit definition for CAN_TDH2R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2448 | #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
| mbed_official | 623:db79ecd649d0 | 2449 | #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
| mbed_official | 623:db79ecd649d0 | 2450 | #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
| mbed_official | 623:db79ecd649d0 | 2451 | #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
| mbed_official | 623:db79ecd649d0 | 2452 | |
| mbed_official | 623:db79ecd649d0 | 2453 | /******************* Bit definition for CAN_RI0R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2454 | #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
| mbed_official | 623:db79ecd649d0 | 2455 | #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
| mbed_official | 623:db79ecd649d0 | 2456 | #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */ |
| mbed_official | 623:db79ecd649d0 | 2457 | #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 623:db79ecd649d0 | 2458 | |
| mbed_official | 623:db79ecd649d0 | 2459 | /******************* Bit definition for CAN_RDT0R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2460 | #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
| mbed_official | 623:db79ecd649d0 | 2461 | #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
| mbed_official | 623:db79ecd649d0 | 2462 | #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
| mbed_official | 623:db79ecd649d0 | 2463 | |
| mbed_official | 623:db79ecd649d0 | 2464 | /******************* Bit definition for CAN_RDL0R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2465 | #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
| mbed_official | 623:db79ecd649d0 | 2466 | #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
| mbed_official | 623:db79ecd649d0 | 2467 | #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
| mbed_official | 623:db79ecd649d0 | 2468 | #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
| mbed_official | 623:db79ecd649d0 | 2469 | |
| mbed_official | 623:db79ecd649d0 | 2470 | /******************* Bit definition for CAN_RDH0R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2471 | #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
| mbed_official | 623:db79ecd649d0 | 2472 | #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
| mbed_official | 623:db79ecd649d0 | 2473 | #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
| mbed_official | 623:db79ecd649d0 | 2474 | #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
| mbed_official | 623:db79ecd649d0 | 2475 | |
| mbed_official | 623:db79ecd649d0 | 2476 | /******************* Bit definition for CAN_RI1R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2477 | #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */ |
| mbed_official | 623:db79ecd649d0 | 2478 | #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */ |
| mbed_official | 623:db79ecd649d0 | 2479 | #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */ |
| mbed_official | 623:db79ecd649d0 | 2480 | #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */ |
| mbed_official | 623:db79ecd649d0 | 2481 | |
| mbed_official | 623:db79ecd649d0 | 2482 | /******************* Bit definition for CAN_RDT1R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2483 | #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */ |
| mbed_official | 623:db79ecd649d0 | 2484 | #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */ |
| mbed_official | 623:db79ecd649d0 | 2485 | #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */ |
| mbed_official | 623:db79ecd649d0 | 2486 | |
| mbed_official | 623:db79ecd649d0 | 2487 | /******************* Bit definition for CAN_RDL1R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2488 | #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */ |
| mbed_official | 623:db79ecd649d0 | 2489 | #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */ |
| mbed_official | 623:db79ecd649d0 | 2490 | #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */ |
| mbed_official | 623:db79ecd649d0 | 2491 | #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */ |
| mbed_official | 623:db79ecd649d0 | 2492 | |
| mbed_official | 623:db79ecd649d0 | 2493 | /******************* Bit definition for CAN_RDH1R register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2494 | #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */ |
| mbed_official | 623:db79ecd649d0 | 2495 | #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */ |
| mbed_official | 623:db79ecd649d0 | 2496 | #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */ |
| mbed_official | 623:db79ecd649d0 | 2497 | #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */ |
| mbed_official | 623:db79ecd649d0 | 2498 | |
| mbed_official | 623:db79ecd649d0 | 2499 | /*!<CAN filter registers */ |
| mbed_official | 623:db79ecd649d0 | 2500 | /******************* Bit definition for CAN_FMR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 2501 | #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */ |
| mbed_official | 623:db79ecd649d0 | 2502 | |
| mbed_official | 623:db79ecd649d0 | 2503 | /******************* Bit definition for CAN_FM1R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2504 | #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */ |
| mbed_official | 623:db79ecd649d0 | 2505 | #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2506 | #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2507 | #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2508 | #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2509 | #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2510 | #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2511 | #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2512 | #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2513 | #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2514 | #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2515 | #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2516 | #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2517 | #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2518 | #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2519 | |
| mbed_official | 623:db79ecd649d0 | 2520 | /******************* Bit definition for CAN_FS1R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2521 | #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */ |
| mbed_official | 623:db79ecd649d0 | 2522 | #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2523 | #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2524 | #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2525 | #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2526 | #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2527 | #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2528 | #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2529 | #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2530 | #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2531 | #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2532 | #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2533 | #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2534 | #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2535 | #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2536 | |
| mbed_official | 623:db79ecd649d0 | 2537 | /****************** Bit definition for CAN_FFA1R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2538 | #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */ |
| mbed_official | 623:db79ecd649d0 | 2539 | #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */ |
| mbed_official | 623:db79ecd649d0 | 2540 | #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */ |
| mbed_official | 623:db79ecd649d0 | 2541 | #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */ |
| mbed_official | 623:db79ecd649d0 | 2542 | #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */ |
| mbed_official | 623:db79ecd649d0 | 2543 | #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */ |
| mbed_official | 623:db79ecd649d0 | 2544 | #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */ |
| mbed_official | 623:db79ecd649d0 | 2545 | #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */ |
| mbed_official | 623:db79ecd649d0 | 2546 | #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */ |
| mbed_official | 623:db79ecd649d0 | 2547 | #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */ |
| mbed_official | 623:db79ecd649d0 | 2548 | #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */ |
| mbed_official | 623:db79ecd649d0 | 2549 | #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */ |
| mbed_official | 623:db79ecd649d0 | 2550 | #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */ |
| mbed_official | 623:db79ecd649d0 | 2551 | #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */ |
| mbed_official | 623:db79ecd649d0 | 2552 | #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */ |
| mbed_official | 623:db79ecd649d0 | 2553 | |
| mbed_official | 623:db79ecd649d0 | 2554 | /******************* Bit definition for CAN_FA1R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2555 | #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */ |
| mbed_official | 623:db79ecd649d0 | 2556 | #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */ |
| mbed_official | 623:db79ecd649d0 | 2557 | #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */ |
| mbed_official | 623:db79ecd649d0 | 2558 | #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */ |
| mbed_official | 623:db79ecd649d0 | 2559 | #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */ |
| mbed_official | 623:db79ecd649d0 | 2560 | #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */ |
| mbed_official | 623:db79ecd649d0 | 2561 | #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */ |
| mbed_official | 623:db79ecd649d0 | 2562 | #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */ |
| mbed_official | 623:db79ecd649d0 | 2563 | #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */ |
| mbed_official | 623:db79ecd649d0 | 2564 | #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */ |
| mbed_official | 623:db79ecd649d0 | 2565 | #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */ |
| mbed_official | 623:db79ecd649d0 | 2566 | #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */ |
| mbed_official | 623:db79ecd649d0 | 2567 | #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */ |
| mbed_official | 623:db79ecd649d0 | 2568 | #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */ |
| mbed_official | 623:db79ecd649d0 | 2569 | #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */ |
| mbed_official | 623:db79ecd649d0 | 2570 | |
| mbed_official | 623:db79ecd649d0 | 2571 | /******************* Bit definition for CAN_F0R1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2572 | #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2573 | #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2574 | #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2575 | #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2576 | #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2577 | #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2578 | #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2579 | #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2580 | #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2581 | #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2582 | #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2583 | #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2584 | #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2585 | #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2586 | #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2587 | #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2588 | #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2589 | #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2590 | #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2591 | #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2592 | #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2593 | #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2594 | #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2595 | #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2596 | #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2597 | #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2598 | #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2599 | #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2600 | #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2601 | #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2602 | #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2603 | #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2604 | |
| mbed_official | 623:db79ecd649d0 | 2605 | /******************* Bit definition for CAN_F1R1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2606 | #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2607 | #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2608 | #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2609 | #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2610 | #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2611 | #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2612 | #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2613 | #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2614 | #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2615 | #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2616 | #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2617 | #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2618 | #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2619 | #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2620 | #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2621 | #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2622 | #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2623 | #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2624 | #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2625 | #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2626 | #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2627 | #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2628 | #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2629 | #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2630 | #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2631 | #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2632 | #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2633 | #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2634 | #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2635 | #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2636 | #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2637 | #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2638 | |
| mbed_official | 623:db79ecd649d0 | 2639 | /******************* Bit definition for CAN_F2R1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2640 | #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2641 | #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2642 | #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2643 | #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2644 | #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2645 | #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2646 | #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2647 | #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2648 | #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2649 | #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2650 | #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2651 | #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2652 | #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2653 | #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2654 | #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2655 | #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2656 | #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2657 | #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2658 | #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2659 | #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2660 | #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2661 | #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2662 | #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2663 | #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2664 | #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2665 | #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2666 | #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2667 | #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2668 | #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2669 | #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2670 | #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2671 | #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2672 | |
| mbed_official | 623:db79ecd649d0 | 2673 | /******************* Bit definition for CAN_F3R1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2674 | #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2675 | #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2676 | #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2677 | #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2678 | #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2679 | #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2680 | #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2681 | #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2682 | #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2683 | #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2684 | #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2685 | #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2686 | #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2687 | #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2688 | #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2689 | #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2690 | #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2691 | #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2692 | #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2693 | #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2694 | #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2695 | #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2696 | #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2697 | #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2698 | #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2699 | #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2700 | #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2701 | #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2702 | #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2703 | #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2704 | #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2705 | #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2706 | |
| mbed_official | 623:db79ecd649d0 | 2707 | /******************* Bit definition for CAN_F4R1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2708 | #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2709 | #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2710 | #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2711 | #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2712 | #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2713 | #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2714 | #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2715 | #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2716 | #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2717 | #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2718 | #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2719 | #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2720 | #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2721 | #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2722 | #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2723 | #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2724 | #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2725 | #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2726 | #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2727 | #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2728 | #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2729 | #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2730 | #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2731 | #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2732 | #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2733 | #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2734 | #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2735 | #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2736 | #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2737 | #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2738 | #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2739 | #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2740 | |
| mbed_official | 623:db79ecd649d0 | 2741 | /******************* Bit definition for CAN_F5R1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2742 | #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2743 | #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2744 | #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2745 | #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2746 | #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2747 | #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2748 | #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2749 | #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2750 | #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2751 | #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2752 | #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2753 | #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2754 | #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2755 | #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2756 | #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2757 | #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2758 | #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2759 | #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2760 | #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2761 | #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2762 | #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2763 | #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2764 | #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2765 | #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2766 | #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2767 | #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2768 | #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2769 | #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2770 | #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2771 | #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2772 | #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2773 | #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2774 | |
| mbed_official | 623:db79ecd649d0 | 2775 | /******************* Bit definition for CAN_F6R1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2776 | #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2777 | #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2778 | #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2779 | #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2780 | #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2781 | #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2782 | #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2783 | #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2784 | #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2785 | #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2786 | #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2787 | #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2788 | #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2789 | #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2790 | #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2791 | #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2792 | #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2793 | #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2794 | #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2795 | #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2796 | #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2797 | #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2798 | #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2799 | #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2800 | #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2801 | #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2802 | #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2803 | #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2804 | #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2805 | #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2806 | #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2807 | #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2808 | |
| mbed_official | 623:db79ecd649d0 | 2809 | /******************* Bit definition for CAN_F7R1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2810 | #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2811 | #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2812 | #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2813 | #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2814 | #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2815 | #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2816 | #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2817 | #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2818 | #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2819 | #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2820 | #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2821 | #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2822 | #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2823 | #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2824 | #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2825 | #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2826 | #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2827 | #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2828 | #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2829 | #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2830 | #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2831 | #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2832 | #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2833 | #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2834 | #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2835 | #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2836 | #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2837 | #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2838 | #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2839 | #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2840 | #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2841 | #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2842 | |
| mbed_official | 623:db79ecd649d0 | 2843 | /******************* Bit definition for CAN_F8R1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2844 | #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2845 | #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2846 | #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2847 | #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2848 | #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2849 | #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2850 | #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2851 | #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2852 | #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2853 | #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2854 | #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2855 | #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2856 | #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2857 | #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2858 | #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2859 | #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2860 | #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2861 | #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2862 | #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2863 | #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2864 | #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2865 | #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2866 | #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2867 | #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2868 | #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2869 | #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2870 | #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2871 | #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2872 | #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2873 | #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2874 | #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2875 | #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2876 | |
| mbed_official | 623:db79ecd649d0 | 2877 | /******************* Bit definition for CAN_F9R1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 2878 | #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2879 | #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2880 | #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2881 | #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2882 | #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2883 | #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2884 | #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2885 | #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2886 | #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2887 | #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2888 | #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2889 | #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2890 | #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2891 | #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2892 | #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2893 | #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2894 | #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2895 | #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2896 | #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2897 | #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2898 | #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2899 | #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2900 | #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2901 | #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2902 | #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2903 | #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2904 | #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2905 | #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2906 | #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2907 | #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2908 | #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2909 | #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2910 | |
| mbed_official | 623:db79ecd649d0 | 2911 | /******************* Bit definition for CAN_F10R1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2912 | #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2913 | #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2914 | #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2915 | #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2916 | #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2917 | #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2918 | #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2919 | #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2920 | #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2921 | #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2922 | #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2923 | #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2924 | #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2925 | #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2926 | #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2927 | #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2928 | #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2929 | #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2930 | #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2931 | #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2932 | #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2933 | #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2934 | #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2935 | #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2936 | #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2937 | #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2938 | #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2939 | #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2940 | #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2941 | #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2942 | #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2943 | #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2944 | |
| mbed_official | 623:db79ecd649d0 | 2945 | /******************* Bit definition for CAN_F11R1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2946 | #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2947 | #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2948 | #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2949 | #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2950 | #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2951 | #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2952 | #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2953 | #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2954 | #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2955 | #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2956 | #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2957 | #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2958 | #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2959 | #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2960 | #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2961 | #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2962 | #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2963 | #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2964 | #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2965 | #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 2966 | #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 2967 | #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 2968 | #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 2969 | #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 2970 | #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 2971 | #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 2972 | #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 2973 | #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 2974 | #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 2975 | #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 2976 | #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 2977 | #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 2978 | |
| mbed_official | 623:db79ecd649d0 | 2979 | /******************* Bit definition for CAN_F12R1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 2980 | #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 2981 | #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 2982 | #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 2983 | #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 2984 | #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 2985 | #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 2986 | #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 2987 | #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 2988 | #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 2989 | #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 2990 | #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 2991 | #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 2992 | #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 2993 | #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 2994 | #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 2995 | #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 2996 | #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 2997 | #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 2998 | #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 2999 | #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3000 | #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3001 | #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3002 | #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3003 | #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3004 | #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3005 | #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3006 | #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3007 | #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3008 | #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3009 | #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3010 | #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3011 | #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3012 | |
| mbed_official | 623:db79ecd649d0 | 3013 | /******************* Bit definition for CAN_F13R1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3014 | #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3015 | #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3016 | #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3017 | #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3018 | #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3019 | #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3020 | #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3021 | #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3022 | #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3023 | #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3024 | #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3025 | #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3026 | #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3027 | #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3028 | #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3029 | #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3030 | #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3031 | #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3032 | #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3033 | #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3034 | #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3035 | #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3036 | #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3037 | #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3038 | #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3039 | #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3040 | #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3041 | #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3042 | #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3043 | #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3044 | #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3045 | #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3046 | |
| mbed_official | 623:db79ecd649d0 | 3047 | /******************* Bit definition for CAN_F0R2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3048 | #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3049 | #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3050 | #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3051 | #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3052 | #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3053 | #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3054 | #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3055 | #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3056 | #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3057 | #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3058 | #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3059 | #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3060 | #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3061 | #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3062 | #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3063 | #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3064 | #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3065 | #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3066 | #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3067 | #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3068 | #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3069 | #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3070 | #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3071 | #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3072 | #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3073 | #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3074 | #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3075 | #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3076 | #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3077 | #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3078 | #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3079 | #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3080 | |
| mbed_official | 623:db79ecd649d0 | 3081 | /******************* Bit definition for CAN_F1R2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3082 | #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3083 | #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3084 | #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3085 | #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3086 | #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3087 | #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3088 | #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3089 | #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3090 | #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3091 | #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3092 | #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3093 | #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3094 | #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3095 | #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3096 | #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3097 | #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3098 | #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3099 | #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3100 | #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3101 | #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3102 | #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3103 | #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3104 | #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3105 | #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3106 | #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3107 | #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3108 | #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3109 | #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3110 | #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3111 | #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3112 | #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3113 | #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3114 | |
| mbed_official | 623:db79ecd649d0 | 3115 | /******************* Bit definition for CAN_F2R2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3116 | #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3117 | #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3118 | #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3119 | #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3120 | #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3121 | #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3122 | #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3123 | #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3124 | #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3125 | #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3126 | #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3127 | #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3128 | #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3129 | #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3130 | #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3131 | #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3132 | #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3133 | #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3134 | #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3135 | #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3136 | #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3137 | #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3138 | #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3139 | #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3140 | #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3141 | #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3142 | #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3143 | #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3144 | #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3145 | #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3146 | #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3147 | #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3148 | |
| mbed_official | 623:db79ecd649d0 | 3149 | /******************* Bit definition for CAN_F3R2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3150 | #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3151 | #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3152 | #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3153 | #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3154 | #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3155 | #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3156 | #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3157 | #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3158 | #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3159 | #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3160 | #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3161 | #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3162 | #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3163 | #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3164 | #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3165 | #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3166 | #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3167 | #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3168 | #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3169 | #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3170 | #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3171 | #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3172 | #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3173 | #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3174 | #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3175 | #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3176 | #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3177 | #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3178 | #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3179 | #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3180 | #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3181 | #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3182 | |
| mbed_official | 623:db79ecd649d0 | 3183 | /******************* Bit definition for CAN_F4R2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3184 | #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3185 | #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3186 | #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3187 | #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3188 | #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3189 | #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3190 | #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3191 | #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3192 | #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3193 | #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3194 | #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3195 | #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3196 | #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3197 | #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3198 | #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3199 | #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3200 | #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3201 | #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3202 | #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3203 | #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3204 | #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3205 | #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3206 | #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3207 | #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3208 | #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3209 | #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3210 | #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3211 | #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3212 | #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3213 | #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3214 | #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3215 | #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3216 | |
| mbed_official | 623:db79ecd649d0 | 3217 | /******************* Bit definition for CAN_F5R2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3218 | #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3219 | #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3220 | #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3221 | #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3222 | #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3223 | #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3224 | #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3225 | #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3226 | #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3227 | #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3228 | #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3229 | #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3230 | #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3231 | #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3232 | #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3233 | #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3234 | #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3235 | #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3236 | #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3237 | #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3238 | #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3239 | #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3240 | #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3241 | #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3242 | #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3243 | #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3244 | #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3245 | #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3246 | #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3247 | #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3248 | #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3249 | #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3250 | |
| mbed_official | 623:db79ecd649d0 | 3251 | /******************* Bit definition for CAN_F6R2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3252 | #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3253 | #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3254 | #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3255 | #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3256 | #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3257 | #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3258 | #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3259 | #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3260 | #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3261 | #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3262 | #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3263 | #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3264 | #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3265 | #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3266 | #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3267 | #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3268 | #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3269 | #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3270 | #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3271 | #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3272 | #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3273 | #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3274 | #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3275 | #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3276 | #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3277 | #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3278 | #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3279 | #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3280 | #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3281 | #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3282 | #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3283 | #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3284 | |
| mbed_official | 623:db79ecd649d0 | 3285 | /******************* Bit definition for CAN_F7R2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3286 | #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3287 | #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3288 | #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3289 | #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3290 | #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3291 | #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3292 | #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3293 | #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3294 | #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3295 | #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3296 | #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3297 | #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3298 | #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3299 | #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3300 | #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3301 | #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3302 | #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3303 | #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3304 | #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3305 | #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3306 | #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3307 | #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3308 | #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3309 | #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3310 | #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3311 | #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3312 | #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3313 | #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3314 | #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3315 | #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3316 | #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3317 | #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3318 | |
| mbed_official | 623:db79ecd649d0 | 3319 | /******************* Bit definition for CAN_F8R2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3320 | #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3321 | #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3322 | #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3323 | #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3324 | #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3325 | #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3326 | #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3327 | #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3328 | #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3329 | #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3330 | #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3331 | #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3332 | #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3333 | #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3334 | #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3335 | #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3336 | #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3337 | #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3338 | #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3339 | #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3340 | #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3341 | #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3342 | #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3343 | #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3344 | #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3345 | #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3346 | #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3347 | #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3348 | #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3349 | #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3350 | #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3351 | #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3352 | |
| mbed_official | 623:db79ecd649d0 | 3353 | /******************* Bit definition for CAN_F9R2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3354 | #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3355 | #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3356 | #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3357 | #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3358 | #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3359 | #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3360 | #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3361 | #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3362 | #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3363 | #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3364 | #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3365 | #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3366 | #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3367 | #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3368 | #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3369 | #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3370 | #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3371 | #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3372 | #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3373 | #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3374 | #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3375 | #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3376 | #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3377 | #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3378 | #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3379 | #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3380 | #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3381 | #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3382 | #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3383 | #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3384 | #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3385 | #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3386 | |
| mbed_official | 623:db79ecd649d0 | 3387 | /******************* Bit definition for CAN_F10R2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3388 | #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3389 | #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3390 | #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3391 | #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3392 | #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3393 | #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3394 | #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3395 | #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3396 | #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3397 | #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3398 | #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3399 | #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3400 | #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3401 | #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3402 | #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3403 | #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3404 | #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3405 | #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3406 | #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3407 | #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3408 | #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3409 | #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3410 | #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3411 | #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3412 | #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3413 | #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3414 | #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3415 | #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3416 | #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3417 | #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3418 | #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3419 | #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3420 | |
| mbed_official | 623:db79ecd649d0 | 3421 | /******************* Bit definition for CAN_F11R2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3422 | #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3423 | #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3424 | #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3425 | #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3426 | #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3427 | #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3428 | #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3429 | #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3430 | #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3431 | #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3432 | #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3433 | #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3434 | #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3435 | #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3436 | #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3437 | #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3438 | #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3439 | #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3440 | #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3441 | #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3442 | #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3443 | #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3444 | #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3445 | #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3446 | #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3447 | #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3448 | #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3449 | #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3450 | #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3451 | #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3452 | #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3453 | #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3454 | |
| mbed_official | 623:db79ecd649d0 | 3455 | /******************* Bit definition for CAN_F12R2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3456 | #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3457 | #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3458 | #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3459 | #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3460 | #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3461 | #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3462 | #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3463 | #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3464 | #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3465 | #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3466 | #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3467 | #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3468 | #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3469 | #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3470 | #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3471 | #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3472 | #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3473 | #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3474 | #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3475 | #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3476 | #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3477 | #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3478 | #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3479 | #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3480 | #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3481 | #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3482 | #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3483 | #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3484 | #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3485 | #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3486 | #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3487 | #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3488 | |
| mbed_official | 623:db79ecd649d0 | 3489 | /******************* Bit definition for CAN_F13R2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3490 | #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3491 | #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3492 | #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3493 | #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3494 | #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 3495 | #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 3496 | #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 3497 | #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 3498 | #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 3499 | #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */ |
| mbed_official | 623:db79ecd649d0 | 3500 | #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */ |
| mbed_official | 623:db79ecd649d0 | 3501 | #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */ |
| mbed_official | 623:db79ecd649d0 | 3502 | #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */ |
| mbed_official | 623:db79ecd649d0 | 3503 | #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */ |
| mbed_official | 623:db79ecd649d0 | 3504 | #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */ |
| mbed_official | 623:db79ecd649d0 | 3505 | #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */ |
| mbed_official | 623:db79ecd649d0 | 3506 | #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */ |
| mbed_official | 623:db79ecd649d0 | 3507 | #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */ |
| mbed_official | 623:db79ecd649d0 | 3508 | #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */ |
| mbed_official | 623:db79ecd649d0 | 3509 | #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */ |
| mbed_official | 623:db79ecd649d0 | 3510 | #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */ |
| mbed_official | 623:db79ecd649d0 | 3511 | #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */ |
| mbed_official | 623:db79ecd649d0 | 3512 | #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */ |
| mbed_official | 623:db79ecd649d0 | 3513 | #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */ |
| mbed_official | 623:db79ecd649d0 | 3514 | #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */ |
| mbed_official | 623:db79ecd649d0 | 3515 | #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */ |
| mbed_official | 623:db79ecd649d0 | 3516 | #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */ |
| mbed_official | 623:db79ecd649d0 | 3517 | #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */ |
| mbed_official | 623:db79ecd649d0 | 3518 | #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */ |
| mbed_official | 623:db79ecd649d0 | 3519 | #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */ |
| mbed_official | 623:db79ecd649d0 | 3520 | #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */ |
| mbed_official | 623:db79ecd649d0 | 3521 | #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */ |
| mbed_official | 623:db79ecd649d0 | 3522 | |
| mbed_official | 623:db79ecd649d0 | 3523 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 3524 | /* */ |
| mbed_official | 623:db79ecd649d0 | 3525 | /* CRC calculation unit */ |
| mbed_official | 623:db79ecd649d0 | 3526 | /* */ |
| mbed_official | 623:db79ecd649d0 | 3527 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 3528 | /******************* Bit definition for CRC_DR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 3529 | #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ |
| mbed_official | 623:db79ecd649d0 | 3530 | |
| mbed_official | 623:db79ecd649d0 | 3531 | /******************* Bit definition for CRC_IDR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 3532 | #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ |
| mbed_official | 623:db79ecd649d0 | 3533 | |
| mbed_official | 623:db79ecd649d0 | 3534 | /******************** Bit definition for CRC_CR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 3535 | #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */ |
| mbed_official | 623:db79ecd649d0 | 3536 | #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */ |
| mbed_official | 623:db79ecd649d0 | 3537 | #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3538 | #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3539 | #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */ |
| mbed_official | 623:db79ecd649d0 | 3540 | #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3541 | #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3542 | #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */ |
| mbed_official | 623:db79ecd649d0 | 3543 | |
| mbed_official | 623:db79ecd649d0 | 3544 | /******************* Bit definition for CRC_INIT register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3545 | #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */ |
| mbed_official | 623:db79ecd649d0 | 3546 | |
| mbed_official | 623:db79ecd649d0 | 3547 | /******************* Bit definition for CRC_POL register ********************/ |
| mbed_official | 623:db79ecd649d0 | 3548 | #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */ |
| mbed_official | 623:db79ecd649d0 | 3549 | |
| mbed_official | 623:db79ecd649d0 | 3550 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 3551 | /* */ |
| mbed_official | 623:db79ecd649d0 | 3552 | /* Digital to Analog Converter */ |
| mbed_official | 623:db79ecd649d0 | 3553 | /* */ |
| mbed_official | 623:db79ecd649d0 | 3554 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 3555 | /******************** Bit definition for DAC_CR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 3556 | #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */ |
| mbed_official | 623:db79ecd649d0 | 3557 | #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */ |
| mbed_official | 623:db79ecd649d0 | 3558 | |
| mbed_official | 623:db79ecd649d0 | 3559 | #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ |
| mbed_official | 623:db79ecd649d0 | 3560 | #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3561 | #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3562 | #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3563 | |
| mbed_official | 623:db79ecd649d0 | 3564 | #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
| mbed_official | 623:db79ecd649d0 | 3565 | #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3566 | #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3567 | |
| mbed_official | 623:db79ecd649d0 | 3568 | #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
| mbed_official | 623:db79ecd649d0 | 3569 | #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3570 | #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3571 | #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3572 | #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3573 | |
| mbed_official | 623:db79ecd649d0 | 3574 | #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */ |
| mbed_official | 623:db79ecd649d0 | 3575 | #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel 1 DMA underrun interrupt enable >*/ |
| mbed_official | 623:db79ecd649d0 | 3576 | #define DAC_CR_CEN1 ((uint32_t)0x00004000) /*!<DAC channel 1 calibration enable >*/ |
| mbed_official | 623:db79ecd649d0 | 3577 | |
| mbed_official | 623:db79ecd649d0 | 3578 | #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */ |
| mbed_official | 623:db79ecd649d0 | 3579 | #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */ |
| mbed_official | 623:db79ecd649d0 | 3580 | |
| mbed_official | 623:db79ecd649d0 | 3581 | #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ |
| mbed_official | 623:db79ecd649d0 | 3582 | #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3583 | #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3584 | #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3585 | |
| mbed_official | 623:db79ecd649d0 | 3586 | #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
| mbed_official | 623:db79ecd649d0 | 3587 | #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3588 | #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3589 | |
| mbed_official | 623:db79ecd649d0 | 3590 | #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
| mbed_official | 623:db79ecd649d0 | 3591 | #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3592 | #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3593 | #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3594 | #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 3595 | |
| mbed_official | 623:db79ecd649d0 | 3596 | #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */ |
| mbed_official | 623:db79ecd649d0 | 3597 | #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable >*/ |
| mbed_official | 623:db79ecd649d0 | 3598 | #define DAC_CR_CEN2 ((uint32_t)0x40000000) /*!<DAC channel2 calibration enable >*/ |
| mbed_official | 623:db79ecd649d0 | 3599 | |
| mbed_official | 623:db79ecd649d0 | 3600 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3601 | #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */ |
| mbed_official | 623:db79ecd649d0 | 3602 | #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!<DAC channel2 software trigger */ |
| mbed_official | 623:db79ecd649d0 | 3603 | |
| mbed_official | 623:db79ecd649d0 | 3604 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3605 | #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3606 | |
| mbed_official | 623:db79ecd649d0 | 3607 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3608 | #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3609 | |
| mbed_official | 623:db79ecd649d0 | 3610 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3611 | #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3612 | |
| mbed_official | 623:db79ecd649d0 | 3613 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3614 | #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!<DAC channel2 12-bit Right aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3615 | |
| mbed_official | 623:db79ecd649d0 | 3616 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3617 | #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!<DAC channel2 12-bit Left aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3618 | |
| mbed_official | 623:db79ecd649d0 | 3619 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3620 | #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!<DAC channel2 8-bit Right aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3621 | |
| mbed_official | 623:db79ecd649d0 | 3622 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3623 | #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3624 | #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3625 | |
| mbed_official | 623:db79ecd649d0 | 3626 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3627 | #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3628 | #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3629 | |
| mbed_official | 623:db79ecd649d0 | 3630 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3631 | #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3632 | #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!<DAC channel2 8-bit Right aligned data */ |
| mbed_official | 623:db79ecd649d0 | 3633 | |
| mbed_official | 623:db79ecd649d0 | 3634 | /******************* Bit definition for DAC_DOR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3635 | #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */ |
| mbed_official | 623:db79ecd649d0 | 3636 | |
| mbed_official | 623:db79ecd649d0 | 3637 | /******************* Bit definition for DAC_DOR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3638 | #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!<DAC channel2 data output */ |
| mbed_official | 623:db79ecd649d0 | 3639 | |
| mbed_official | 623:db79ecd649d0 | 3640 | /******************** Bit definition for DAC_SR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 3641 | #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */ |
| mbed_official | 623:db79ecd649d0 | 3642 | #define DAC_SR_CAL_FLAG1 ((uint32_t)0x00004000) /*!<DAC channel1 calibration offset status */ |
| mbed_official | 623:db79ecd649d0 | 3643 | #define DAC_SR_BWST1 ((uint32_t)0x20008000) /*!<DAC channel1 busy writing sample time flag */ |
| mbed_official | 623:db79ecd649d0 | 3644 | |
| mbed_official | 623:db79ecd649d0 | 3645 | #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */ |
| mbed_official | 623:db79ecd649d0 | 3646 | #define DAC_SR_CAL_FLAG2 ((uint32_t)0x40000000) /*!<DAC channel2 calibration offset status */ |
| mbed_official | 623:db79ecd649d0 | 3647 | #define DAC_SR_BWST2 ((uint32_t)0x80000000) /*!<DAC channel2 busy writing sample time flag */ |
| mbed_official | 623:db79ecd649d0 | 3648 | |
| mbed_official | 623:db79ecd649d0 | 3649 | /******************* Bit definition for DAC_CCR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 3650 | #define DAC_CCR_OTRIM1 ((uint32_t)0x0000001F) /*!<DAC channel1 offset trimming value */ |
| mbed_official | 623:db79ecd649d0 | 3651 | #define DAC_CCR_OTRIM2 ((uint32_t)0x001F0000) /*!<DAC channel2 offset trimming value */ |
| mbed_official | 623:db79ecd649d0 | 3652 | |
| mbed_official | 623:db79ecd649d0 | 3653 | /******************* Bit definition for DAC_MCR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3654 | #define DAC_MCR_MODE1 ((uint32_t)0x00000007) /*!<MODE1[2:0] (DAC channel1 mode) */ |
| mbed_official | 623:db79ecd649d0 | 3655 | #define DAC_MCR_MODE1_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3656 | #define DAC_MCR_MODE1_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3657 | #define DAC_MCR_MODE1_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3658 | |
| mbed_official | 623:db79ecd649d0 | 3659 | #define DAC_MCR_MODE2 ((uint32_t)0x00070000) /*!<MODE2[2:0] (DAC channel2 mode) */ |
| mbed_official | 623:db79ecd649d0 | 3660 | #define DAC_MCR_MODE2_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3661 | #define DAC_MCR_MODE2_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3662 | #define DAC_MCR_MODE2_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3663 | |
| mbed_official | 623:db79ecd649d0 | 3664 | /****************** Bit definition for DAC_SHSR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3665 | #define DAC_SHSR1_TSAMPLE1 ((uint32_t)0x000003FF) /*!<DAC channel1 sample time */ |
| mbed_official | 623:db79ecd649d0 | 3666 | |
| mbed_official | 623:db79ecd649d0 | 3667 | /****************** Bit definition for DAC_SHSR2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3668 | #define DAC_SHSR2_TSAMPLE2 ((uint32_t)0x000003FF) /*!<DAC channel2 sample time */ |
| mbed_official | 623:db79ecd649d0 | 3669 | |
| mbed_official | 623:db79ecd649d0 | 3670 | /****************** Bit definition for DAC_SHHR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3671 | #define DAC_SHHR_THOLD1 ((uint32_t)0x000003FF) /*!<DAC channel1 hold time */ |
| mbed_official | 623:db79ecd649d0 | 3672 | #define DAC_SHHR_THOLD2 ((uint32_t)0x03FF0000) /*!<DAC channel2 hold time */ |
| mbed_official | 623:db79ecd649d0 | 3673 | |
| mbed_official | 623:db79ecd649d0 | 3674 | /****************** Bit definition for DAC_SHRR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3675 | #define DAC_SHRR_TREFRESH1 ((uint32_t)0x000000FF) /*!<DAC channel1 refresh time */ |
| mbed_official | 623:db79ecd649d0 | 3676 | #define DAC_SHRR_TREFRESH2 ((uint32_t)0x00FF0000) /*!<DAC channel2 refresh time */ |
| mbed_official | 623:db79ecd649d0 | 3677 | |
| mbed_official | 623:db79ecd649d0 | 3678 | |
| mbed_official | 623:db79ecd649d0 | 3679 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 3680 | /* */ |
| mbed_official | 623:db79ecd649d0 | 3681 | /* Digital Filter for Sigma Delta Modulators */ |
| mbed_official | 623:db79ecd649d0 | 3682 | /* */ |
| mbed_official | 623:db79ecd649d0 | 3683 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 3684 | |
| mbed_official | 623:db79ecd649d0 | 3685 | /**************** DFSDM channel configuration registers ********************/ |
| mbed_official | 623:db79ecd649d0 | 3686 | |
| mbed_official | 623:db79ecd649d0 | 3687 | /*************** Bit definition for DFSDM_CHCFGR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3688 | #define DFSDM_CHCFGR1_DFSDMEN ((uint32_t)0x80000000) /*!< Global enable for DFSDM interface */ |
| mbed_official | 623:db79ecd649d0 | 3689 | #define DFSDM_CHCFGR1_CKOUTSRC ((uint32_t)0x40000000) /*!< Output serial clock source selection */ |
| mbed_official | 623:db79ecd649d0 | 3690 | #define DFSDM_CHCFGR1_CKOUTDIV ((uint32_t)0x00FF0000) /*!< CKOUTDIV[7:0] output serial clock divider */ |
| mbed_official | 623:db79ecd649d0 | 3691 | #define DFSDM_CHCFGR1_DATPACK ((uint32_t)0x0000C000) /*!< DATPACK[1:0] Data packing mode */ |
| mbed_official | 623:db79ecd649d0 | 3692 | #define DFSDM_CHCFGR1_DATPACK_1 ((uint32_t)0x00008000) /*!< Data packing mode, Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3693 | #define DFSDM_CHCFGR1_DATPACK_0 ((uint32_t)0x00004000) /*!< Data packing mode, Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3694 | #define DFSDM_CHCFGR1_DATMPX ((uint32_t)0x00003000) /*!< DATMPX[1:0] Input data multiplexer for channel y */ |
| mbed_official | 623:db79ecd649d0 | 3695 | #define DFSDM_CHCFGR1_DATMPX_1 ((uint32_t)0x00002000) /*!< Input data multiplexer for channel y, Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3696 | #define DFSDM_CHCFGR1_DATMPX_0 ((uint32_t)0x00001000) /*!< Input data multiplexer for channel y, Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3697 | #define DFSDM_CHCFGR1_CHINSEL ((uint32_t)0x00000100) /*!< Serial inputs selection for channel y */ |
| mbed_official | 623:db79ecd649d0 | 3698 | #define DFSDM_CHCFGR1_CHEN ((uint32_t)0x00000080) /*!< Channel y enable */ |
| mbed_official | 623:db79ecd649d0 | 3699 | #define DFSDM_CHCFGR1_CKABEN ((uint32_t)0x00000040) /*!< Clock absence detector enable on channel y */ |
| mbed_official | 623:db79ecd649d0 | 3700 | #define DFSDM_CHCFGR1_SCDEN ((uint32_t)0x00000020) /*!< Short circuit detector enable on channel y */ |
| mbed_official | 623:db79ecd649d0 | 3701 | #define DFSDM_CHCFGR1_SPICKSEL ((uint32_t)0x0000000C) /*!< SPICKSEL[1:0] SPI clock select for channel y */ |
| mbed_official | 623:db79ecd649d0 | 3702 | #define DFSDM_CHCFGR1_SPICKSEL_1 ((uint32_t)0x00000008) /*!< SPI clock select for channel y, Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3703 | #define DFSDM_CHCFGR1_SPICKSEL_0 ((uint32_t)0x00000004) /*!< SPI clock select for channel y, Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3704 | #define DFSDM_CHCFGR1_SITP ((uint32_t)0x00000003) /*!< SITP[1:0] Serial interface type for channel y */ |
| mbed_official | 623:db79ecd649d0 | 3705 | #define DFSDM_CHCFGR1_SITP_1 ((uint32_t)0x00000002) /*!< Serial interface type for channel y, Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3706 | #define DFSDM_CHCFGR1_SITP_0 ((uint32_t)0x00000001) /*!< Serial interface type for channel y, Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3707 | |
| mbed_official | 623:db79ecd649d0 | 3708 | /*************** Bit definition for DFSDM_CHCFGR2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3709 | #define DFSDM_CHCFGR2_OFFSET ((uint32_t)0xFFFFFF00) /*!< OFFSET[23:0] 24-bit calibration offset for channel y */ |
| mbed_official | 623:db79ecd649d0 | 3710 | #define DFSDM_CHCFGR2_DTRBS ((uint32_t)0x000000F8) /*!< DTRBS[4:0] Data right bit-shift for channel y */ |
| mbed_official | 623:db79ecd649d0 | 3711 | |
| mbed_official | 623:db79ecd649d0 | 3712 | /****************** Bit definition for DFSDM_AWSCDR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 3713 | #define DFSDM_AWSCDR_AWFORD ((uint32_t)0x00C00000) /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */ |
| mbed_official | 623:db79ecd649d0 | 3714 | #define DFSDM_AWSCDR_AWFORD_1 ((uint32_t)0x00800000) /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3715 | #define DFSDM_AWSCDR_AWFORD_0 ((uint32_t)0x00400000) /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3716 | #define DFSDM_AWSCDR_AWFOSR ((uint32_t)0x001F0000) /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */ |
| mbed_official | 623:db79ecd649d0 | 3717 | #define DFSDM_AWSCDR_BKSCD ((uint32_t)0x0000F000) /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */ |
| mbed_official | 623:db79ecd649d0 | 3718 | #define DFSDM_AWSCDR_SCDT ((uint32_t)0x000000FF) /*!< SCDT[7:0] Short circuit detector threshold for channel y */ |
| mbed_official | 623:db79ecd649d0 | 3719 | |
| mbed_official | 623:db79ecd649d0 | 3720 | /**************** Bit definition for DFSDM_CHWDATR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3721 | #define DFSDM_AWSCDR_WDATA ((uint32_t)0x0000FFFF) /*!< WDATA[15:0] Input channel y watchdog data */ |
| mbed_official | 623:db79ecd649d0 | 3722 | |
| mbed_official | 623:db79ecd649d0 | 3723 | /**************** Bit definition for DFSDM_CHDATINR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 3724 | #define DFSDM_AWSCDR_INDAT0 ((uint32_t)0x0000FFFF) /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */ |
| mbed_official | 623:db79ecd649d0 | 3725 | #define DFSDM_AWSCDR_INDAT1 ((uint32_t)0xFFFF0000) /*!< INDAT0[15:0] Input data for channel y */ |
| mbed_official | 623:db79ecd649d0 | 3726 | |
| mbed_official | 623:db79ecd649d0 | 3727 | /************************ DFSDM module registers ****************************/ |
| mbed_official | 623:db79ecd649d0 | 3728 | |
| mbed_official | 623:db79ecd649d0 | 3729 | /******************** Bit definition for DFSDM_CR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3730 | #define DFSDM_CR1_AWFSEL ((uint32_t)0x40000000) /*!< Analog watchdog fast mode select */ |
| mbed_official | 623:db79ecd649d0 | 3731 | #define DFSDM_CR1_FAST ((uint32_t)0x20000000) /*!< Fast conversion mode selection */ |
| mbed_official | 623:db79ecd649d0 | 3732 | #define DFSDM_CR1_RCH ((uint32_t)0x07000000) /*!< RCH[2:0] Regular channel selection */ |
| mbed_official | 623:db79ecd649d0 | 3733 | #define DFSDM_CR1_RDMAEN ((uint32_t)0x00200000) /*!< DMA channel enabled to read data for the regular conversion */ |
| mbed_official | 623:db79ecd649d0 | 3734 | #define DFSDM_CR1_RSYNC ((uint32_t)0x00080000) /*!< Launch regular conversion synchronously with DFSDMx */ |
| mbed_official | 623:db79ecd649d0 | 3735 | #define DFSDM_CR1_RCONT ((uint32_t)0x00040000) /*!< Continuous mode selection for regular conversions */ |
| mbed_official | 623:db79ecd649d0 | 3736 | #define DFSDM_CR1_RSWSTART ((uint32_t)0x00020000) /*!< Software start of a conversion on the regular channel */ |
| mbed_official | 623:db79ecd649d0 | 3737 | #define DFSDM_CR1_JEXTEN ((uint32_t)0x00006000) /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */ |
| mbed_official | 623:db79ecd649d0 | 3738 | #define DFSDM_CR1_JEXTEN_1 ((uint32_t)0x00004000) /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3739 | #define DFSDM_CR1_JEXTEN_0 ((uint32_t)0x00002000) /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3740 | #define DFSDM_CR1_JEXTSEL ((uint32_t)0x00000700) /*!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions */ |
| mbed_official | 623:db79ecd649d0 | 3741 | #define DFSDM_CR1_JEXTSEL_2 ((uint32_t)0x00000400) /*!< Trigger signal selection for launching injected conversions, Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3742 | #define DFSDM_CR1_JEXTSEL_1 ((uint32_t)0x00000200) /*!< Trigger signal selection for launching injected conversions, Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3743 | #define DFSDM_CR1_JEXTSEL_0 ((uint32_t)0x00000100) /*!< Trigger signal selection for launching injected conversions, Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3744 | #define DFSDM_CR1_JDMAEN ((uint32_t)0x00000020) /*!< DMA channel enabled to read data for the injected channel group */ |
| mbed_official | 623:db79ecd649d0 | 3745 | #define DFSDM_CR1_JSCAN ((uint32_t)0x00000010) /*!< Scanning conversion in continuous mode selection for injected conversions */ |
| mbed_official | 623:db79ecd649d0 | 3746 | #define DFSDM_CR1_JSYNC ((uint32_t)0x00000008) /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */ |
| mbed_official | 623:db79ecd649d0 | 3747 | #define DFSDM_CR1_JSWSTART ((uint32_t)0x00000002) /*!< Start the conversion of the injected group of channels */ |
| mbed_official | 623:db79ecd649d0 | 3748 | #define DFSDM_CR1_DFEN ((uint32_t)0x00000001) /*!< DFSDM enable */ |
| mbed_official | 623:db79ecd649d0 | 3749 | |
| mbed_official | 623:db79ecd649d0 | 3750 | /******************** Bit definition for DFSDM_CR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3751 | #define DFSDM_CR2_AWDCH ((uint32_t)0x00FF0000) /*!< AWDCH[7:0] Analog watchdog channel selection */ |
| mbed_official | 623:db79ecd649d0 | 3752 | #define DFSDM_CR2_EXCH ((uint32_t)0x0000FF00) /*!< EXCH[7:0] Extreme detector channel selection */ |
| mbed_official | 623:db79ecd649d0 | 3753 | #define DFSDM_CR2_CKABIE ((uint32_t)0x00000040) /*!< Clock absence interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 3754 | #define DFSDM_CR2_SCDIE ((uint32_t)0x00000020) /*!< Short circuit detector interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 3755 | #define DFSDM_CR2_AWDIE ((uint32_t)0x00000010) /*!< Analog watchdog interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 3756 | #define DFSDM_CR2_ROVRIE ((uint32_t)0x00000008) /*!< Regular data overrun interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 3757 | #define DFSDM_CR2_JOVRIE ((uint32_t)0x00000004) /*!< Injected data overrun interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 3758 | #define DFSDM_CR2_REOCIE ((uint32_t)0x00000002) /*!< Regular end of conversion interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 3759 | #define DFSDM_CR2_JEOCIE ((uint32_t)0x00000001) /*!< Injected end of conversion interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 3760 | |
| mbed_official | 623:db79ecd649d0 | 3761 | /******************** Bit definition for DFSDM_ISR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3762 | #define DFSDM_ISR_SCDF ((uint32_t)0xFF000000) /*!< SCDF[7:0] Short circuit detector flag */ |
| mbed_official | 623:db79ecd649d0 | 3763 | #define DFSDM_ISR_CKABF ((uint32_t)0x00FF0000) /*!< CKABF[7:0] Clock absence flag */ |
| mbed_official | 623:db79ecd649d0 | 3764 | #define DFSDM_ISR_RCIP ((uint32_t)0x00004000) /*!< Regular conversion in progress status */ |
| mbed_official | 623:db79ecd649d0 | 3765 | #define DFSDM_ISR_JCIP ((uint32_t)0x00002000) /*!< Injected conversion in progress status */ |
| mbed_official | 623:db79ecd649d0 | 3766 | #define DFSDM_ISR_AWDF ((uint32_t)0x00000010) /*!< Analog watchdog */ |
| mbed_official | 623:db79ecd649d0 | 3767 | #define DFSDM_ISR_ROVRF ((uint32_t)0x00000008) /*!< Regular conversion overrun flag */ |
| mbed_official | 623:db79ecd649d0 | 3768 | #define DFSDM_ISR_JOVRF ((uint32_t)0x00000004) /*!< Injected conversion overrun flag */ |
| mbed_official | 623:db79ecd649d0 | 3769 | #define DFSDM_ISR_REOCF ((uint32_t)0x00000002) /*!< End of regular conversion flag */ |
| mbed_official | 623:db79ecd649d0 | 3770 | #define DFSDM_ISR_JEOCF ((uint32_t)0x00000001) /*!< End of injected conversion flag */ |
| mbed_official | 623:db79ecd649d0 | 3771 | |
| mbed_official | 623:db79ecd649d0 | 3772 | /******************** Bit definition for DFSDM_ICR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3773 | #define DFSDM_ICR_CLRSCSDF ((uint32_t)0xFF000000) /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */ |
| mbed_official | 623:db79ecd649d0 | 3774 | #define DFSDM_ICR_CLRCKABF ((uint32_t)0x00FF0000) /*!< CLRCKABF[7:0] Clear the clock absence flag */ |
| mbed_official | 623:db79ecd649d0 | 3775 | #define DFSDM_ICR_CLRROVRF ((uint32_t)0x00000008) /*!< Clear the regular conversion overrun flag */ |
| mbed_official | 623:db79ecd649d0 | 3776 | #define DFSDM_ICR_CLRJOVRF ((uint32_t)0x00000004) /*!< Clear the injected conversion overrun flag */ |
| mbed_official | 623:db79ecd649d0 | 3777 | |
| mbed_official | 623:db79ecd649d0 | 3778 | /******************* Bit definition for DFSDM_JCHGR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3779 | #define DFSDM_JCHGR_JCHG ((uint32_t)0x000000FF) /*!< JCHG[7:0] Injected channel group selection */ |
| mbed_official | 623:db79ecd649d0 | 3780 | |
| mbed_official | 623:db79ecd649d0 | 3781 | /******************** Bit definition for DFSDM_FCR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3782 | #define DFSDM_FCR_FORD ((uint32_t)0xE0000000) /*!< FORD[2:0] Sinc filter order */ |
| mbed_official | 623:db79ecd649d0 | 3783 | #define DFSDM_FCR_FORD_2 ((uint32_t)0x80000000) /*!< Sinc filter order, Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 3784 | #define DFSDM_FCR_FORD_1 ((uint32_t)0x40000000) /*!< Sinc filter order, Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3785 | #define DFSDM_FCR_FORD_0 ((uint32_t)0x20000000) /*!< Sinc filter order, Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3786 | #define DFSDM_FCR_FOSR ((uint32_t)0x03FF0000) /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */ |
| mbed_official | 623:db79ecd649d0 | 3787 | #define DFSDM_FCR_IOSR ((uint32_t)0x000000FF) /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */ |
| mbed_official | 623:db79ecd649d0 | 3788 | |
| mbed_official | 623:db79ecd649d0 | 3789 | /****************** Bit definition for DFSDM_JDATAR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 3790 | #define DFSDM_JDATAR_JDATA ((uint32_t)0xFFFFFF00) /*!< JDATA[23:0] Injected group conversion data */ |
| mbed_official | 623:db79ecd649d0 | 3791 | #define DFSDM_JDATAR_JDATACH ((uint32_t)0x00000007) /*!< JDATACH[2:0] Injected channel most recently converted */ |
| mbed_official | 623:db79ecd649d0 | 3792 | |
| mbed_official | 623:db79ecd649d0 | 3793 | /****************** Bit definition for DFSDM_RDATAR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 3794 | #define DFSDM_RDATAR_RDATA ((uint32_t)0xFFFFFF00) /*!< RDATA[23:0] Regular channel conversion data */ |
| mbed_official | 623:db79ecd649d0 | 3795 | #define DFSDM_RDATAR_RPEND ((uint32_t)0x00000010) /*!< RPEND Regular channel pending data */ |
| mbed_official | 623:db79ecd649d0 | 3796 | #define DFSDM_RDATAR_RDATACH ((uint32_t)0x00000007) /*!< RDATACH[2:0] Regular channel most recently converted */ |
| mbed_official | 623:db79ecd649d0 | 3797 | |
| mbed_official | 623:db79ecd649d0 | 3798 | /****************** Bit definition for DFSDM_AWHTR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3799 | #define DFSDM_AWHTR_AWHT ((uint32_t)0xFFFFFF00) /*!< AWHT[23:0] Analog watchdog high threshold */ |
| mbed_official | 623:db79ecd649d0 | 3800 | #define DFSDM_AWHTR_BKAWH ((uint32_t)0x0000000F) /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */ |
| mbed_official | 623:db79ecd649d0 | 3801 | |
| mbed_official | 623:db79ecd649d0 | 3802 | /****************** Bit definition for DFSDM_AWLTR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3803 | #define DFSDM_AWLTR_AWLT ((uint32_t)0xFFFFFF00) /*!< AWHT[23:0] Analog watchdog low threshold */ |
| mbed_official | 623:db79ecd649d0 | 3804 | #define DFSDM_AWLTR_BKAWL ((uint32_t)0x0000000F) /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */ |
| mbed_official | 623:db79ecd649d0 | 3805 | |
| mbed_official | 623:db79ecd649d0 | 3806 | /****************** Bit definition for DFSDM_AWSR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3807 | #define DFSDM_AWSR_AWHTF ((uint32_t)0x0000FF00) /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */ |
| mbed_official | 623:db79ecd649d0 | 3808 | #define DFSDM_AWSR_AWLTF ((uint32_t)0x000000FF) /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */ |
| mbed_official | 623:db79ecd649d0 | 3809 | |
| mbed_official | 623:db79ecd649d0 | 3810 | /****************** Bit definition for DFSDM_AWCFR) register *****************/ |
| mbed_official | 623:db79ecd649d0 | 3811 | #define DFSDM_AWCFR_CLRAWHTF ((uint32_t)0x0000FF00) /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */ |
| mbed_official | 623:db79ecd649d0 | 3812 | #define DFSDM_AWCFR_CLRAWLTF ((uint32_t)0x000000FF) /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */ |
| mbed_official | 623:db79ecd649d0 | 3813 | |
| mbed_official | 623:db79ecd649d0 | 3814 | /****************** Bit definition for DFSDM_EXMAX register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3815 | #define DFSDM_EXMAX_EXMAX ((uint32_t)0xFFFFFF00) /*!< EXMAX[23:0] Extreme detector maximum value */ |
| mbed_official | 623:db79ecd649d0 | 3816 | #define DFSDM_EXMAX_EXMAXCH ((uint32_t)0x00000007) /*!< EXMAXCH[2:0] Extreme detector maximum data channel */ |
| mbed_official | 623:db79ecd649d0 | 3817 | |
| mbed_official | 623:db79ecd649d0 | 3818 | /****************** Bit definition for DFSDM_EXMIN register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3819 | #define DFSDM_EXMIN_EXMIN ((uint32_t)0xFFFFFF00) /*!< EXMIN[23:0] Extreme detector minimum value */ |
| mbed_official | 623:db79ecd649d0 | 3820 | #define DFSDM_EXMIN_EXMINCH ((uint32_t)0x00000007) /*!< EXMINCH[2:0] Extreme detector minimum data channel */ |
| mbed_official | 623:db79ecd649d0 | 3821 | |
| mbed_official | 623:db79ecd649d0 | 3822 | /****************** Bit definition for DFSDM_EXMIN register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3823 | #define DFSDM_CNVTIMR_CNVCNT ((uint32_t)0xFFFFFFF0) /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */ |
| mbed_official | 623:db79ecd649d0 | 3824 | |
| mbed_official | 623:db79ecd649d0 | 3825 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 3826 | /* */ |
| mbed_official | 623:db79ecd649d0 | 3827 | /* DMA Controller (DMA) */ |
| mbed_official | 623:db79ecd649d0 | 3828 | /* */ |
| mbed_official | 623:db79ecd649d0 | 3829 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 3830 | |
| mbed_official | 623:db79ecd649d0 | 3831 | /******************* Bit definition for DMA_ISR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 3832 | #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ |
| mbed_official | 623:db79ecd649d0 | 3833 | #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ |
| mbed_official | 623:db79ecd649d0 | 3834 | #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ |
| mbed_official | 623:db79ecd649d0 | 3835 | #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ |
| mbed_official | 623:db79ecd649d0 | 3836 | #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ |
| mbed_official | 623:db79ecd649d0 | 3837 | #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ |
| mbed_official | 623:db79ecd649d0 | 3838 | #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ |
| mbed_official | 623:db79ecd649d0 | 3839 | #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ |
| mbed_official | 623:db79ecd649d0 | 3840 | #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ |
| mbed_official | 623:db79ecd649d0 | 3841 | #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ |
| mbed_official | 623:db79ecd649d0 | 3842 | #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ |
| mbed_official | 623:db79ecd649d0 | 3843 | #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ |
| mbed_official | 623:db79ecd649d0 | 3844 | #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ |
| mbed_official | 623:db79ecd649d0 | 3845 | #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ |
| mbed_official | 623:db79ecd649d0 | 3846 | #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ |
| mbed_official | 623:db79ecd649d0 | 3847 | #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ |
| mbed_official | 623:db79ecd649d0 | 3848 | #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ |
| mbed_official | 623:db79ecd649d0 | 3849 | #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ |
| mbed_official | 623:db79ecd649d0 | 3850 | #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ |
| mbed_official | 623:db79ecd649d0 | 3851 | #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ |
| mbed_official | 623:db79ecd649d0 | 3852 | #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ |
| mbed_official | 623:db79ecd649d0 | 3853 | #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ |
| mbed_official | 623:db79ecd649d0 | 3854 | #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ |
| mbed_official | 623:db79ecd649d0 | 3855 | #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ |
| mbed_official | 623:db79ecd649d0 | 3856 | #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ |
| mbed_official | 623:db79ecd649d0 | 3857 | #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ |
| mbed_official | 623:db79ecd649d0 | 3858 | #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ |
| mbed_official | 623:db79ecd649d0 | 3859 | #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ |
| mbed_official | 623:db79ecd649d0 | 3860 | |
| mbed_official | 623:db79ecd649d0 | 3861 | /******************* Bit definition for DMA_IFCR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3862 | #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ |
| mbed_official | 623:db79ecd649d0 | 3863 | #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ |
| mbed_official | 623:db79ecd649d0 | 3864 | #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ |
| mbed_official | 623:db79ecd649d0 | 3865 | #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ |
| mbed_official | 623:db79ecd649d0 | 3866 | #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ |
| mbed_official | 623:db79ecd649d0 | 3867 | #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ |
| mbed_official | 623:db79ecd649d0 | 3868 | #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ |
| mbed_official | 623:db79ecd649d0 | 3869 | #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ |
| mbed_official | 623:db79ecd649d0 | 3870 | #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ |
| mbed_official | 623:db79ecd649d0 | 3871 | #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ |
| mbed_official | 623:db79ecd649d0 | 3872 | #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ |
| mbed_official | 623:db79ecd649d0 | 3873 | #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ |
| mbed_official | 623:db79ecd649d0 | 3874 | #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ |
| mbed_official | 623:db79ecd649d0 | 3875 | #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ |
| mbed_official | 623:db79ecd649d0 | 3876 | #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ |
| mbed_official | 623:db79ecd649d0 | 3877 | #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ |
| mbed_official | 623:db79ecd649d0 | 3878 | #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ |
| mbed_official | 623:db79ecd649d0 | 3879 | #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ |
| mbed_official | 623:db79ecd649d0 | 3880 | #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ |
| mbed_official | 623:db79ecd649d0 | 3881 | #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ |
| mbed_official | 623:db79ecd649d0 | 3882 | #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ |
| mbed_official | 623:db79ecd649d0 | 3883 | #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ |
| mbed_official | 623:db79ecd649d0 | 3884 | #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ |
| mbed_official | 623:db79ecd649d0 | 3885 | #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ |
| mbed_official | 623:db79ecd649d0 | 3886 | #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ |
| mbed_official | 623:db79ecd649d0 | 3887 | #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ |
| mbed_official | 623:db79ecd649d0 | 3888 | #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ |
| mbed_official | 623:db79ecd649d0 | 3889 | #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ |
| mbed_official | 623:db79ecd649d0 | 3890 | |
| mbed_official | 623:db79ecd649d0 | 3891 | /******************* Bit definition for DMA_CCR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 3892 | #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */ |
| mbed_official | 623:db79ecd649d0 | 3893 | #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 3894 | #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 3895 | #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 3896 | #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */ |
| mbed_official | 623:db79ecd649d0 | 3897 | #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */ |
| mbed_official | 623:db79ecd649d0 | 3898 | #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */ |
| mbed_official | 623:db79ecd649d0 | 3899 | #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */ |
| mbed_official | 623:db79ecd649d0 | 3900 | |
| mbed_official | 623:db79ecd649d0 | 3901 | #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */ |
| mbed_official | 623:db79ecd649d0 | 3902 | #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3903 | #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3904 | |
| mbed_official | 623:db79ecd649d0 | 3905 | #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */ |
| mbed_official | 623:db79ecd649d0 | 3906 | #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3907 | #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3908 | |
| mbed_official | 623:db79ecd649d0 | 3909 | #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/ |
| mbed_official | 623:db79ecd649d0 | 3910 | #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 3911 | #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 3912 | |
| mbed_official | 623:db79ecd649d0 | 3913 | #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */ |
| mbed_official | 623:db79ecd649d0 | 3914 | |
| mbed_official | 623:db79ecd649d0 | 3915 | /****************** Bit definition for DMA_CNDTR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3916 | #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */ |
| mbed_official | 623:db79ecd649d0 | 3917 | |
| mbed_official | 623:db79ecd649d0 | 3918 | /****************** Bit definition for DMA_CPAR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 3919 | #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */ |
| mbed_official | 623:db79ecd649d0 | 3920 | |
| mbed_official | 623:db79ecd649d0 | 3921 | /****************** Bit definition for DMA_CMAR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 3922 | #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */ |
| mbed_official | 623:db79ecd649d0 | 3923 | |
| mbed_official | 623:db79ecd649d0 | 3924 | |
| mbed_official | 623:db79ecd649d0 | 3925 | /******************* Bit definition for DMA_CSELR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 3926 | #define DMA_CSELR_C1S ((uint32_t)0x0000000F) /*!< Channel 1 Selection */ |
| mbed_official | 623:db79ecd649d0 | 3927 | #define DMA_CSELR_C2S ((uint32_t)0x000000F0) /*!< Channel 2 Selection */ |
| mbed_official | 623:db79ecd649d0 | 3928 | #define DMA_CSELR_C3S ((uint32_t)0x00000F00) /*!< Channel 3 Selection */ |
| mbed_official | 623:db79ecd649d0 | 3929 | #define DMA_CSELR_C4S ((uint32_t)0x0000F000) /*!< Channel 4 Selection */ |
| mbed_official | 623:db79ecd649d0 | 3930 | #define DMA_CSELR_C5S ((uint32_t)0x000F0000) /*!< Channel 5 Selection */ |
| mbed_official | 623:db79ecd649d0 | 3931 | #define DMA_CSELR_C6S ((uint32_t)0x00F00000) /*!< Channel 6 Selection */ |
| mbed_official | 623:db79ecd649d0 | 3932 | #define DMA_CSELR_C7S ((uint32_t)0x0F000000) /*!< Channel 7 Selection */ |
| mbed_official | 623:db79ecd649d0 | 3933 | |
| mbed_official | 623:db79ecd649d0 | 3934 | |
| mbed_official | 623:db79ecd649d0 | 3935 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 3936 | /* */ |
| mbed_official | 623:db79ecd649d0 | 3937 | /* External Interrupt/Event Controller */ |
| mbed_official | 623:db79ecd649d0 | 3938 | /* */ |
| mbed_official | 623:db79ecd649d0 | 3939 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 3940 | /******************* Bit definition for EXTI_IMR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3941 | #define EXTI_IMR1_IM0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ |
| mbed_official | 623:db79ecd649d0 | 3942 | #define EXTI_IMR1_IM1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ |
| mbed_official | 623:db79ecd649d0 | 3943 | #define EXTI_IMR1_IM2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ |
| mbed_official | 623:db79ecd649d0 | 3944 | #define EXTI_IMR1_IM3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ |
| mbed_official | 623:db79ecd649d0 | 3945 | #define EXTI_IMR1_IM4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ |
| mbed_official | 623:db79ecd649d0 | 3946 | #define EXTI_IMR1_IM5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ |
| mbed_official | 623:db79ecd649d0 | 3947 | #define EXTI_IMR1_IM6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ |
| mbed_official | 623:db79ecd649d0 | 3948 | #define EXTI_IMR1_IM7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ |
| mbed_official | 623:db79ecd649d0 | 3949 | #define EXTI_IMR1_IM8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ |
| mbed_official | 623:db79ecd649d0 | 3950 | #define EXTI_IMR1_IM9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ |
| mbed_official | 623:db79ecd649d0 | 3951 | #define EXTI_IMR1_IM10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ |
| mbed_official | 623:db79ecd649d0 | 3952 | #define EXTI_IMR1_IM11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ |
| mbed_official | 623:db79ecd649d0 | 3953 | #define EXTI_IMR1_IM12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ |
| mbed_official | 623:db79ecd649d0 | 3954 | #define EXTI_IMR1_IM13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ |
| mbed_official | 623:db79ecd649d0 | 3955 | #define EXTI_IMR1_IM14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ |
| mbed_official | 623:db79ecd649d0 | 3956 | #define EXTI_IMR1_IM15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ |
| mbed_official | 623:db79ecd649d0 | 3957 | #define EXTI_IMR1_IM16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ |
| mbed_official | 623:db79ecd649d0 | 3958 | #define EXTI_IMR1_IM17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ |
| mbed_official | 623:db79ecd649d0 | 3959 | #define EXTI_IMR1_IM18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ |
| mbed_official | 623:db79ecd649d0 | 3960 | #define EXTI_IMR1_IM19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ |
| mbed_official | 623:db79ecd649d0 | 3961 | #define EXTI_IMR1_IM20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */ |
| mbed_official | 623:db79ecd649d0 | 3962 | #define EXTI_IMR1_IM21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */ |
| mbed_official | 623:db79ecd649d0 | 3963 | #define EXTI_IMR1_IM22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */ |
| mbed_official | 623:db79ecd649d0 | 3964 | #define EXTI_IMR1_IM23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */ |
| mbed_official | 623:db79ecd649d0 | 3965 | #define EXTI_IMR1_IM24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */ |
| mbed_official | 623:db79ecd649d0 | 3966 | #define EXTI_IMR1_IM25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */ |
| mbed_official | 623:db79ecd649d0 | 3967 | #define EXTI_IMR1_IM26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */ |
| mbed_official | 623:db79ecd649d0 | 3968 | #define EXTI_IMR1_IM27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */ |
| mbed_official | 623:db79ecd649d0 | 3969 | #define EXTI_IMR1_IM28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */ |
| mbed_official | 623:db79ecd649d0 | 3970 | #define EXTI_IMR1_IM29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */ |
| mbed_official | 623:db79ecd649d0 | 3971 | #define EXTI_IMR1_IM30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */ |
| mbed_official | 623:db79ecd649d0 | 3972 | #define EXTI_IMR1_IM31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */ |
| mbed_official | 623:db79ecd649d0 | 3973 | |
| mbed_official | 623:db79ecd649d0 | 3974 | /******************* Bit definition for EXTI_EMR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 3975 | #define EXTI_EMR1_EM0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ |
| mbed_official | 623:db79ecd649d0 | 3976 | #define EXTI_EMR1_EM1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ |
| mbed_official | 623:db79ecd649d0 | 3977 | #define EXTI_EMR1_EM2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ |
| mbed_official | 623:db79ecd649d0 | 3978 | #define EXTI_EMR1_EM3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ |
| mbed_official | 623:db79ecd649d0 | 3979 | #define EXTI_EMR1_EM4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ |
| mbed_official | 623:db79ecd649d0 | 3980 | #define EXTI_EMR1_EM5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ |
| mbed_official | 623:db79ecd649d0 | 3981 | #define EXTI_EMR1_EM6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ |
| mbed_official | 623:db79ecd649d0 | 3982 | #define EXTI_EMR1_EM7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ |
| mbed_official | 623:db79ecd649d0 | 3983 | #define EXTI_EMR1_EM8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ |
| mbed_official | 623:db79ecd649d0 | 3984 | #define EXTI_EMR1_EM9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ |
| mbed_official | 623:db79ecd649d0 | 3985 | #define EXTI_EMR1_EM10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ |
| mbed_official | 623:db79ecd649d0 | 3986 | #define EXTI_EMR1_EM11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ |
| mbed_official | 623:db79ecd649d0 | 3987 | #define EXTI_EMR1_EM12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ |
| mbed_official | 623:db79ecd649d0 | 3988 | #define EXTI_EMR1_EM13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ |
| mbed_official | 623:db79ecd649d0 | 3989 | #define EXTI_EMR1_EM14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ |
| mbed_official | 623:db79ecd649d0 | 3990 | #define EXTI_EMR1_EM15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ |
| mbed_official | 623:db79ecd649d0 | 3991 | #define EXTI_EMR1_EM16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ |
| mbed_official | 623:db79ecd649d0 | 3992 | #define EXTI_EMR1_EM17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ |
| mbed_official | 623:db79ecd649d0 | 3993 | #define EXTI_EMR1_EM18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ |
| mbed_official | 623:db79ecd649d0 | 3994 | #define EXTI_EMR1_EM19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ |
| mbed_official | 623:db79ecd649d0 | 3995 | #define EXTI_EMR1_EM20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */ |
| mbed_official | 623:db79ecd649d0 | 3996 | #define EXTI_EMR1_EM21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */ |
| mbed_official | 623:db79ecd649d0 | 3997 | #define EXTI_EMR1_EM22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */ |
| mbed_official | 623:db79ecd649d0 | 3998 | #define EXTI_EMR1_EM23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */ |
| mbed_official | 623:db79ecd649d0 | 3999 | #define EXTI_EMR1_EM24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */ |
| mbed_official | 623:db79ecd649d0 | 4000 | #define EXTI_EMR1_EM25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */ |
| mbed_official | 623:db79ecd649d0 | 4001 | #define EXTI_EMR1_EM26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */ |
| mbed_official | 623:db79ecd649d0 | 4002 | #define EXTI_EMR1_EM27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */ |
| mbed_official | 623:db79ecd649d0 | 4003 | #define EXTI_EMR1_EM28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */ |
| mbed_official | 623:db79ecd649d0 | 4004 | #define EXTI_EMR1_EM29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */ |
| mbed_official | 623:db79ecd649d0 | 4005 | #define EXTI_EMR1_EM30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */ |
| mbed_official | 623:db79ecd649d0 | 4006 | #define EXTI_EMR1_EM31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */ |
| mbed_official | 623:db79ecd649d0 | 4007 | |
| mbed_official | 623:db79ecd649d0 | 4008 | /****************** Bit definition for EXTI_RTSR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4009 | #define EXTI_RTSR1_RT0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ |
| mbed_official | 623:db79ecd649d0 | 4010 | #define EXTI_RTSR1_RT1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ |
| mbed_official | 623:db79ecd649d0 | 4011 | #define EXTI_RTSR1_RT2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ |
| mbed_official | 623:db79ecd649d0 | 4012 | #define EXTI_RTSR1_RT3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ |
| mbed_official | 623:db79ecd649d0 | 4013 | #define EXTI_RTSR1_RT4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ |
| mbed_official | 623:db79ecd649d0 | 4014 | #define EXTI_RTSR1_RT5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ |
| mbed_official | 623:db79ecd649d0 | 4015 | #define EXTI_RTSR1_RT6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ |
| mbed_official | 623:db79ecd649d0 | 4016 | #define EXTI_RTSR1_RT7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ |
| mbed_official | 623:db79ecd649d0 | 4017 | #define EXTI_RTSR1_RT8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ |
| mbed_official | 623:db79ecd649d0 | 4018 | #define EXTI_RTSR1_RT9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ |
| mbed_official | 623:db79ecd649d0 | 4019 | #define EXTI_RTSR1_RT10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ |
| mbed_official | 623:db79ecd649d0 | 4020 | #define EXTI_RTSR1_RT11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ |
| mbed_official | 623:db79ecd649d0 | 4021 | #define EXTI_RTSR1_RT12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ |
| mbed_official | 623:db79ecd649d0 | 4022 | #define EXTI_RTSR1_RT13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ |
| mbed_official | 623:db79ecd649d0 | 4023 | #define EXTI_RTSR1_RT14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ |
| mbed_official | 623:db79ecd649d0 | 4024 | #define EXTI_RTSR1_RT15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ |
| mbed_official | 623:db79ecd649d0 | 4025 | #define EXTI_RTSR1_RT16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ |
| mbed_official | 623:db79ecd649d0 | 4026 | #define EXTI_RTSR1_RT18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ |
| mbed_official | 623:db79ecd649d0 | 4027 | #define EXTI_RTSR1_RT19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ |
| mbed_official | 623:db79ecd649d0 | 4028 | #define EXTI_RTSR1_RT20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */ |
| mbed_official | 623:db79ecd649d0 | 4029 | #define EXTI_RTSR1_RT21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */ |
| mbed_official | 623:db79ecd649d0 | 4030 | #define EXTI_RTSR1_RT22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */ |
| mbed_official | 623:db79ecd649d0 | 4031 | |
| mbed_official | 623:db79ecd649d0 | 4032 | /****************** Bit definition for EXTI_FTSR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4033 | #define EXTI_FTSR1_FT0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ |
| mbed_official | 623:db79ecd649d0 | 4034 | #define EXTI_FTSR1_FT1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ |
| mbed_official | 623:db79ecd649d0 | 4035 | #define EXTI_FTSR1_FT2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ |
| mbed_official | 623:db79ecd649d0 | 4036 | #define EXTI_FTSR1_FT3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ |
| mbed_official | 623:db79ecd649d0 | 4037 | #define EXTI_FTSR1_FT4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ |
| mbed_official | 623:db79ecd649d0 | 4038 | #define EXTI_FTSR1_FT5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ |
| mbed_official | 623:db79ecd649d0 | 4039 | #define EXTI_FTSR1_FT6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ |
| mbed_official | 623:db79ecd649d0 | 4040 | #define EXTI_FTSR1_FT7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ |
| mbed_official | 623:db79ecd649d0 | 4041 | #define EXTI_FTSR1_FT8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ |
| mbed_official | 623:db79ecd649d0 | 4042 | #define EXTI_FTSR1_FT9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ |
| mbed_official | 623:db79ecd649d0 | 4043 | #define EXTI_FTSR1_FT10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ |
| mbed_official | 623:db79ecd649d0 | 4044 | #define EXTI_FTSR1_FT11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ |
| mbed_official | 623:db79ecd649d0 | 4045 | #define EXTI_FTSR1_FT12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ |
| mbed_official | 623:db79ecd649d0 | 4046 | #define EXTI_FTSR1_FT13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ |
| mbed_official | 623:db79ecd649d0 | 4047 | #define EXTI_FTSR1_FT14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ |
| mbed_official | 623:db79ecd649d0 | 4048 | #define EXTI_FTSR1_FT15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ |
| mbed_official | 623:db79ecd649d0 | 4049 | #define EXTI_FTSR1_FT16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ |
| mbed_official | 623:db79ecd649d0 | 4050 | #define EXTI_FTSR1_FT18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ |
| mbed_official | 623:db79ecd649d0 | 4051 | #define EXTI_FTSR1_FT19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ |
| mbed_official | 623:db79ecd649d0 | 4052 | #define EXTI_FTSR1_FT20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */ |
| mbed_official | 623:db79ecd649d0 | 4053 | #define EXTI_FTSR1_FT21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */ |
| mbed_official | 623:db79ecd649d0 | 4054 | #define EXTI_FTSR1_FT22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */ |
| mbed_official | 623:db79ecd649d0 | 4055 | |
| mbed_official | 623:db79ecd649d0 | 4056 | /****************** Bit definition for EXTI_SWIER1 register *****************/ |
| mbed_official | 623:db79ecd649d0 | 4057 | #define EXTI_SWIER1_SWI0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ |
| mbed_official | 623:db79ecd649d0 | 4058 | #define EXTI_SWIER1_SWI1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ |
| mbed_official | 623:db79ecd649d0 | 4059 | #define EXTI_SWIER1_SWI2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ |
| mbed_official | 623:db79ecd649d0 | 4060 | #define EXTI_SWIER1_SWI3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ |
| mbed_official | 623:db79ecd649d0 | 4061 | #define EXTI_SWIER1_SWI4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ |
| mbed_official | 623:db79ecd649d0 | 4062 | #define EXTI_SWIER1_SWI5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ |
| mbed_official | 623:db79ecd649d0 | 4063 | #define EXTI_SWIER1_SWI6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ |
| mbed_official | 623:db79ecd649d0 | 4064 | #define EXTI_SWIER1_SWI7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ |
| mbed_official | 623:db79ecd649d0 | 4065 | #define EXTI_SWIER1_SWI8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ |
| mbed_official | 623:db79ecd649d0 | 4066 | #define EXTI_SWIER1_SWI9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ |
| mbed_official | 623:db79ecd649d0 | 4067 | #define EXTI_SWIER1_SWI10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ |
| mbed_official | 623:db79ecd649d0 | 4068 | #define EXTI_SWIER1_SWI11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ |
| mbed_official | 623:db79ecd649d0 | 4069 | #define EXTI_SWIER1_SWI12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ |
| mbed_official | 623:db79ecd649d0 | 4070 | #define EXTI_SWIER1_SWI13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ |
| mbed_official | 623:db79ecd649d0 | 4071 | #define EXTI_SWIER1_SWI14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ |
| mbed_official | 623:db79ecd649d0 | 4072 | #define EXTI_SWIER1_SWI15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ |
| mbed_official | 623:db79ecd649d0 | 4073 | #define EXTI_SWIER1_SWI16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ |
| mbed_official | 623:db79ecd649d0 | 4074 | #define EXTI_SWIER1_SWI18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ |
| mbed_official | 623:db79ecd649d0 | 4075 | #define EXTI_SWIER1_SWI19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ |
| mbed_official | 623:db79ecd649d0 | 4076 | #define EXTI_SWIER1_SWI20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */ |
| mbed_official | 623:db79ecd649d0 | 4077 | #define EXTI_SWIER1_SWI21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */ |
| mbed_official | 623:db79ecd649d0 | 4078 | #define EXTI_SWIER1_SWI22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */ |
| mbed_official | 623:db79ecd649d0 | 4079 | |
| mbed_official | 623:db79ecd649d0 | 4080 | /******************* Bit definition for EXTI_PR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4081 | #define EXTI_PR1_PIF0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ |
| mbed_official | 623:db79ecd649d0 | 4082 | #define EXTI_PR1_PIF1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ |
| mbed_official | 623:db79ecd649d0 | 4083 | #define EXTI_PR1_PIF2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ |
| mbed_official | 623:db79ecd649d0 | 4084 | #define EXTI_PR1_PIF3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ |
| mbed_official | 623:db79ecd649d0 | 4085 | #define EXTI_PR1_PIF4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ |
| mbed_official | 623:db79ecd649d0 | 4086 | #define EXTI_PR1_PIF5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ |
| mbed_official | 623:db79ecd649d0 | 4087 | #define EXTI_PR1_PIF6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ |
| mbed_official | 623:db79ecd649d0 | 4088 | #define EXTI_PR1_PIF7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ |
| mbed_official | 623:db79ecd649d0 | 4089 | #define EXTI_PR1_PIF8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ |
| mbed_official | 623:db79ecd649d0 | 4090 | #define EXTI_PR1_PIF9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ |
| mbed_official | 623:db79ecd649d0 | 4091 | #define EXTI_PR1_PIF10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ |
| mbed_official | 623:db79ecd649d0 | 4092 | #define EXTI_PR1_PIF11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ |
| mbed_official | 623:db79ecd649d0 | 4093 | #define EXTI_PR1_PIF12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ |
| mbed_official | 623:db79ecd649d0 | 4094 | #define EXTI_PR1_PIF13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ |
| mbed_official | 623:db79ecd649d0 | 4095 | #define EXTI_PR1_PIF14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ |
| mbed_official | 623:db79ecd649d0 | 4096 | #define EXTI_PR1_PIF15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ |
| mbed_official | 623:db79ecd649d0 | 4097 | #define EXTI_PR1_PIF16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ |
| mbed_official | 623:db79ecd649d0 | 4098 | #define EXTI_PR1_PIF18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ |
| mbed_official | 623:db79ecd649d0 | 4099 | #define EXTI_PR1_PIF19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ |
| mbed_official | 623:db79ecd649d0 | 4100 | #define EXTI_PR1_PIF20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */ |
| mbed_official | 623:db79ecd649d0 | 4101 | #define EXTI_PR1_PIF21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */ |
| mbed_official | 623:db79ecd649d0 | 4102 | #define EXTI_PR1_PIF22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */ |
| mbed_official | 623:db79ecd649d0 | 4103 | |
| mbed_official | 623:db79ecd649d0 | 4104 | /******************* Bit definition for EXTI_IMR2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4105 | #define EXTI_IMR2_IM32 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 32 */ |
| mbed_official | 623:db79ecd649d0 | 4106 | #define EXTI_IMR2_IM33 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 33 */ |
| mbed_official | 623:db79ecd649d0 | 4107 | #define EXTI_IMR2_IM34 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 34 */ |
| mbed_official | 623:db79ecd649d0 | 4108 | #define EXTI_IMR2_IM35 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 35 */ |
| mbed_official | 623:db79ecd649d0 | 4109 | #define EXTI_IMR2_IM36 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 36 */ |
| mbed_official | 623:db79ecd649d0 | 4110 | #define EXTI_IMR2_IM37 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 37 */ |
| mbed_official | 623:db79ecd649d0 | 4111 | #define EXTI_IMR2_IM38 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 38 */ |
| mbed_official | 623:db79ecd649d0 | 4112 | #define EXTI_IMR2_IM39 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 39 */ |
| mbed_official | 623:db79ecd649d0 | 4113 | |
| mbed_official | 623:db79ecd649d0 | 4114 | /******************* Bit definition for EXTI_EMR2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4115 | #define EXTI_EMR2_EM32 ((uint32_t)0x00000001) /*!< Event Mask on line 32 */ |
| mbed_official | 623:db79ecd649d0 | 4116 | #define EXTI_EMR2_EM33 ((uint32_t)0x00000002) /*!< Event Mask on line 33 */ |
| mbed_official | 623:db79ecd649d0 | 4117 | #define EXTI_EMR2_EM34 ((uint32_t)0x00000004) /*!< Event Mask on line 34 */ |
| mbed_official | 623:db79ecd649d0 | 4118 | #define EXTI_EMR2_EM35 ((uint32_t)0x00000008) /*!< Event Mask on line 35 */ |
| mbed_official | 623:db79ecd649d0 | 4119 | #define EXTI_EMR2_EM36 ((uint32_t)0x00000010) /*!< Event Mask on line 36 */ |
| mbed_official | 623:db79ecd649d0 | 4120 | #define EXTI_EMR2_EM37 ((uint32_t)0x00000020) /*!< Event Mask on line 37 */ |
| mbed_official | 623:db79ecd649d0 | 4121 | #define EXTI_EMR2_EM38 ((uint32_t)0x00000040) /*!< Event Mask on line 38 */ |
| mbed_official | 623:db79ecd649d0 | 4122 | #define EXTI_EMR2_EM39 ((uint32_t)0x00000080) /*!< Event Mask on line 39 */ |
| mbed_official | 623:db79ecd649d0 | 4123 | |
| mbed_official | 623:db79ecd649d0 | 4124 | /****************** Bit definition for EXTI_RTSR2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4125 | #define EXTI_RTSR2_RT35 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 35 */ |
| mbed_official | 623:db79ecd649d0 | 4126 | #define EXTI_RTSR2_RT36 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 36 */ |
| mbed_official | 623:db79ecd649d0 | 4127 | #define EXTI_RTSR2_RT37 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 37 */ |
| mbed_official | 623:db79ecd649d0 | 4128 | #define EXTI_RTSR2_RT38 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 38 */ |
| mbed_official | 623:db79ecd649d0 | 4129 | |
| mbed_official | 623:db79ecd649d0 | 4130 | /****************** Bit definition for EXTI_FTSR2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4131 | #define EXTI_FTSR2_FT35 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 35 */ |
| mbed_official | 623:db79ecd649d0 | 4132 | #define EXTI_FTSR2_FT36 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 36 */ |
| mbed_official | 623:db79ecd649d0 | 4133 | #define EXTI_FTSR2_FT37 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 37 */ |
| mbed_official | 623:db79ecd649d0 | 4134 | #define EXTI_FTSR2_FT38 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 38 */ |
| mbed_official | 623:db79ecd649d0 | 4135 | |
| mbed_official | 623:db79ecd649d0 | 4136 | /****************** Bit definition for EXTI_SWIER2 register *****************/ |
| mbed_official | 623:db79ecd649d0 | 4137 | #define EXTI_SWIER2_SWI35 ((uint32_t)0x00000008) /*!< Software Interrupt on line 35 */ |
| mbed_official | 623:db79ecd649d0 | 4138 | #define EXTI_SWIER2_SWI36 ((uint32_t)0x00000010) /*!< Software Interrupt on line 36 */ |
| mbed_official | 623:db79ecd649d0 | 4139 | #define EXTI_SWIER2_SWI37 ((uint32_t)0x00000020) /*!< Software Interrupt on line 37 */ |
| mbed_official | 623:db79ecd649d0 | 4140 | #define EXTI_SWIER2_SWI38 ((uint32_t)0x00000040) /*!< Software Interrupt on line 38 */ |
| mbed_official | 623:db79ecd649d0 | 4141 | |
| mbed_official | 623:db79ecd649d0 | 4142 | /******************* Bit definition for EXTI_PR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4143 | #define EXTI_PR2_PIF35 ((uint32_t)0x00000008) /*!< Pending bit for line 35 */ |
| mbed_official | 623:db79ecd649d0 | 4144 | #define EXTI_PR2_PIF36 ((uint32_t)0x00000010) /*!< Pending bit for line 36 */ |
| mbed_official | 623:db79ecd649d0 | 4145 | #define EXTI_PR2_PIF37 ((uint32_t)0x00000020) /*!< Pending bit for line 37 */ |
| mbed_official | 623:db79ecd649d0 | 4146 | #define EXTI_PR2_PIF38 ((uint32_t)0x00000040) /*!< Pending bit for line 38 */ |
| mbed_official | 623:db79ecd649d0 | 4147 | |
| mbed_official | 623:db79ecd649d0 | 4148 | |
| mbed_official | 623:db79ecd649d0 | 4149 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 4150 | /* */ |
| mbed_official | 623:db79ecd649d0 | 4151 | /* FLASH */ |
| mbed_official | 623:db79ecd649d0 | 4152 | /* */ |
| mbed_official | 623:db79ecd649d0 | 4153 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 4154 | /******************* Bits definition for FLASH_ACR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 4155 | #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) |
| mbed_official | 623:db79ecd649d0 | 4156 | #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) |
| mbed_official | 623:db79ecd649d0 | 4157 | #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4158 | #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4159 | #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) |
| mbed_official | 623:db79ecd649d0 | 4160 | #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4161 | #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4162 | #define FLASH_ACR_ICEN ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4163 | #define FLASH_ACR_DCEN ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4164 | #define FLASH_ACR_ICRST ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4165 | #define FLASH_ACR_DCRST ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4166 | #define FLASH_ACR_RUN_PD ((uint32_t)0x00002000) /*!< Flash power down mode during run */ |
| mbed_official | 623:db79ecd649d0 | 4167 | #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00004000) /*!< Flash power down mode during sleep */ |
| mbed_official | 623:db79ecd649d0 | 4168 | |
| mbed_official | 623:db79ecd649d0 | 4169 | /******************* Bits definition for FLASH_SR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4170 | #define FLASH_SR_EOP ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4171 | #define FLASH_SR_OPERR ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4172 | #define FLASH_SR_PROGERR ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4173 | #define FLASH_SR_WRPERR ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4174 | #define FLASH_SR_PGAERR ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4175 | #define FLASH_SR_SIZERR ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4176 | #define FLASH_SR_PGSERR ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4177 | #define FLASH_SR_MISERR ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4178 | #define FLASH_SR_FASTERR ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4179 | #define FLASH_SR_RDERR ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4180 | #define FLASH_SR_OPTVERR ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4181 | #define FLASH_SR_BSY ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 4182 | |
| mbed_official | 623:db79ecd649d0 | 4183 | /******************* Bits definition for FLASH_CR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4184 | #define FLASH_CR_PG ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4185 | #define FLASH_CR_PER ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4186 | #define FLASH_CR_MER1 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4187 | #define FLASH_CR_PNB ((uint32_t)0x000007F8) |
| mbed_official | 623:db79ecd649d0 | 4188 | /*#define FLASH_CR_PNB_0 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4189 | #define FLASH_CR_PNB_1 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4190 | #define FLASH_CR_PNB_2 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4191 | #define FLASH_CR_PNB_3 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4192 | #define FLASH_CR_PNB_4 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4193 | #define FLASH_CR_PNB_5 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4194 | #define FLASH_CR_PNB_6 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4195 | #define FLASH_CR_PNB_7 ((uint32_t)0x00000400)*/ |
| mbed_official | 623:db79ecd649d0 | 4196 | #define FLASH_CR_BKER ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4197 | #define FLASH_CR_MER2 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4198 | #define FLASH_CR_STRT ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 4199 | #define FLASH_CR_OPTSTRT ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 4200 | #define FLASH_CR_FSTPG ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 4201 | #define FLASH_CR_EOPIE ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 4202 | #define FLASH_CR_ERRIE ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 4203 | #define FLASH_CR_RDERRIE ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 4204 | #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 4205 | #define FLASH_CR_OPTLOCK ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 4206 | #define FLASH_CR_LOCK ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 4207 | |
| mbed_official | 623:db79ecd649d0 | 4208 | /******************* Bits definition for FLASH_ECCR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 4209 | #define FLASH_ECCR_ADDR_ECC ((uint32_t)0x0007FFFF) |
| mbed_official | 623:db79ecd649d0 | 4210 | /*#define FLASH_ECCR_ADDR_ECC_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4211 | #define FLASH_ECCR_ADDR_ECC_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4212 | #define FLASH_ECCR_ADDR_ECC_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4213 | #define FLASH_ECCR_ADDR_ECC_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4214 | #define FLASH_ECCR_ADDR_ECC_4 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4215 | #define FLASH_ECCR_ADDR_ECC_5 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4216 | #define FLASH_ECCR_ADDR_ECC_6 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4217 | #define FLASH_ECCR_ADDR_ECC_7 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4218 | #define FLASH_ECCR_ADDR_ECC_8 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4219 | #define FLASH_ECCR_ADDR_ECC_9 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4220 | #define FLASH_ECCR_ADDR_ECC_10 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4221 | #define FLASH_ECCR_ADDR_ECC_11 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4222 | #define FLASH_ECCR_ADDR_ECC_12 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4223 | #define FLASH_ECCR_ADDR_ECC_13 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4224 | #define FLASH_ECCR_ADDR_ECC_14 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4225 | #define FLASH_ECCR_ADDR_ECC_15 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4226 | #define FLASH_ECCR_ADDR_ECC_16 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 4227 | #define FLASH_ECCR_ADDR_ECC_17 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 4228 | #define FLASH_ECCR_ADDR_ECC_18 ((uint32_t)0x00040000)*/ |
| mbed_official | 623:db79ecd649d0 | 4229 | #define FLASH_ECCR_BK_ECC ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 4230 | #define FLASH_ECCR_SYSF_ECC ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 4231 | #define FLASH_ECCR_ECCIE ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 4232 | #define FLASH_ECCR_ECCC ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 4233 | #define FLASH_ECCR_ECCD ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 4234 | |
| mbed_official | 623:db79ecd649d0 | 4235 | /******************* Bits definition for FLASH_OPTR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 4236 | #define FLASH_OPTR_RDP ((uint32_t)0x000000FF) |
| mbed_official | 623:db79ecd649d0 | 4237 | /*#define FLASH_OPTR_RDP_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4238 | #define FLASH_OPTR_RDP_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4239 | #define FLASH_OPTR_RDP_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4240 | #define FLASH_OPTR_RDP_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4241 | #define FLASH_OPTR_RDP_4 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4242 | #define FLASH_OPTR_RDP_5 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4243 | #define FLASH_OPTR_RDP_6 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4244 | #define FLASH_OPTR_RDP_7 ((uint32_t)0x00000080)*/ |
| mbed_official | 623:db79ecd649d0 | 4245 | #define FLASH_OPTR_BOR_LEV ((uint32_t)0x00000700) |
| mbed_official | 623:db79ecd649d0 | 4246 | #define FLASH_OPTR_BOR_LEV_0 ((uint32_t)0x00000000) |
| mbed_official | 623:db79ecd649d0 | 4247 | #define FLASH_OPTR_BOR_LEV_1 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4248 | #define FLASH_OPTR_BOR_LEV_2 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4249 | #define FLASH_OPTR_BOR_LEV_3 ((uint32_t)0x00000300) |
| mbed_official | 623:db79ecd649d0 | 4250 | #define FLASH_OPTR_BOR_LEV_4 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4251 | #define FLASH_OPTR_nRST_STOP ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4252 | #define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4253 | #define FLASH_OPTR_IWDG_SW ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 4254 | #define FLASH_OPTR_IWDG_STOP ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 4255 | #define FLASH_OPTR_IWDG_STDBY ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 4256 | #define FLASH_OPTR_WWDG_SW ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 4257 | #define FLASH_OPTR_BFB2 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 4258 | #define FLASH_OPTR_DUALBANK ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 4259 | #define FLASH_OPTR_nBOOT1 ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 4260 | #define FLASH_OPTR_SRAM2_PE ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 4261 | #define FLASH_OPTR_SRAM2_RST ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 4262 | |
| mbed_official | 623:db79ecd649d0 | 4263 | /****************** Bits definition for FLASH_PCROP1SR register **********/ |
| mbed_official | 623:db79ecd649d0 | 4264 | #define FLASH_PCROP1SR_PCROP1_STRT ((uint32_t)0x0000FFFF) |
| mbed_official | 623:db79ecd649d0 | 4265 | |
| mbed_official | 623:db79ecd649d0 | 4266 | /****************** Bits definition for FLASH_PCROP1ER register ***********/ |
| mbed_official | 623:db79ecd649d0 | 4267 | #define FLASH_PCROP1ER_PCROP1_END ((uint32_t)0x0000FFFF) |
| mbed_official | 623:db79ecd649d0 | 4268 | #define FLASH_PCROP1ER_PCROP_RDP ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 4269 | |
| mbed_official | 623:db79ecd649d0 | 4270 | /****************** Bits definition for FLASH_WRP1AR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 4271 | #define FLASH_WRP1AR_WRP1A_STRT ((uint32_t)0x000000FF) |
| mbed_official | 623:db79ecd649d0 | 4272 | #define FLASH_WRP1AR_WRP1A_END ((uint32_t)0x00FF0000) |
| mbed_official | 623:db79ecd649d0 | 4273 | |
| mbed_official | 623:db79ecd649d0 | 4274 | /****************** Bits definition for FLASH_WRPB1R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 4275 | #define FLASH_WRP1BR_WRP1B_STRT ((uint32_t)0x000000FF) |
| mbed_official | 623:db79ecd649d0 | 4276 | #define FLASH_WRP1BR_WRP1B_END ((uint32_t)0x00FF0000) |
| mbed_official | 623:db79ecd649d0 | 4277 | |
| mbed_official | 623:db79ecd649d0 | 4278 | /****************** Bits definition for FLASH_PCROP2SR register **********/ |
| mbed_official | 623:db79ecd649d0 | 4279 | #define FLASH_PCROP2SR_PCROP2_STRT ((uint32_t)0x0000FFFF) |
| mbed_official | 623:db79ecd649d0 | 4280 | |
| mbed_official | 623:db79ecd649d0 | 4281 | /****************** Bits definition for FLASH_PCROP2ER register ***********/ |
| mbed_official | 623:db79ecd649d0 | 4282 | #define FLASH_PCROP2ER_PCROP2_END ((uint32_t)0x0000FFFF) |
| mbed_official | 623:db79ecd649d0 | 4283 | |
| mbed_official | 623:db79ecd649d0 | 4284 | /****************** Bits definition for FLASH_WRP2AR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 4285 | #define FLASH_WRP2AR_WRP2A_STRT ((uint32_t)0x000000FF) |
| mbed_official | 623:db79ecd649d0 | 4286 | #define FLASH_WRP2AR_WRP2A_END ((uint32_t)0x00FF0000) |
| mbed_official | 623:db79ecd649d0 | 4287 | |
| mbed_official | 623:db79ecd649d0 | 4288 | /****************** Bits definition for FLASH_WRP2BR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 4289 | #define FLASH_WRP2BR_WRP2B_STRT ((uint32_t)0x000000FF) |
| mbed_official | 623:db79ecd649d0 | 4290 | #define FLASH_WRP2BR_WRP2B_END ((uint32_t)0x00FF0000) |
| mbed_official | 623:db79ecd649d0 | 4291 | |
| mbed_official | 623:db79ecd649d0 | 4292 | |
| mbed_official | 623:db79ecd649d0 | 4293 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 4294 | /* */ |
| mbed_official | 623:db79ecd649d0 | 4295 | /* Flexible Memory Controller */ |
| mbed_official | 623:db79ecd649d0 | 4296 | /* */ |
| mbed_official | 623:db79ecd649d0 | 4297 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 4298 | /****************** Bit definition for FMC_BCR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4299 | #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */ |
| mbed_official | 623:db79ecd649d0 | 4300 | #define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */ |
| mbed_official | 623:db79ecd649d0 | 4301 | |
| mbed_official | 623:db79ecd649d0 | 4302 | /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/ |
| mbed_official | 623:db79ecd649d0 | 4303 | #define FMC_BCRx_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4304 | #define FMC_BCRx_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4305 | |
| mbed_official | 623:db79ecd649d0 | 4306 | #define FMC_BCRx_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */ |
| mbed_official | 623:db79ecd649d0 | 4307 | #define FMC_BCRx_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4308 | #define FMC_BCRx_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4309 | |
| mbed_official | 623:db79ecd649d0 | 4310 | #define FMC_BCRx_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */ |
| mbed_official | 623:db79ecd649d0 | 4311 | #define FMC_BCRx_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4312 | #define FMC_BCRx_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4313 | |
| mbed_official | 623:db79ecd649d0 | 4314 | #define FMC_BCRx_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */ |
| mbed_official | 623:db79ecd649d0 | 4315 | #define FMC_BCRx_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4316 | #define FMC_BCRx_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */ |
| mbed_official | 623:db79ecd649d0 | 4317 | #define FMC_BCRx_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */ |
| mbed_official | 623:db79ecd649d0 | 4318 | #define FMC_BCRx_WREN ((uint32_t)0x00001000) /*!<Write enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4319 | #define FMC_BCRx_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4320 | #define FMC_BCRx_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */ |
| mbed_official | 623:db79ecd649d0 | 4321 | #define FMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */ |
| mbed_official | 623:db79ecd649d0 | 4322 | |
| mbed_official | 623:db79ecd649d0 | 4323 | #define FMC_BCRx_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */ |
| mbed_official | 623:db79ecd649d0 | 4324 | #define FMC_BCRx_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4325 | #define FMC_BCRx_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4326 | #define FMC_BCRx_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4327 | |
| mbed_official | 623:db79ecd649d0 | 4328 | #define FMC_BCRx_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */ |
| mbed_official | 623:db79ecd649d0 | 4329 | |
| mbed_official | 623:db79ecd649d0 | 4330 | /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/ |
| mbed_official | 623:db79ecd649d0 | 4331 | #define FMC_BTRx_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 623:db79ecd649d0 | 4332 | #define FMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4333 | #define FMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4334 | #define FMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4335 | #define FMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4336 | |
| mbed_official | 623:db79ecd649d0 | 4337 | #define FMC_BTRx_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 623:db79ecd649d0 | 4338 | #define FMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4339 | #define FMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4340 | #define FMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4341 | #define FMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4342 | |
| mbed_official | 623:db79ecd649d0 | 4343 | #define FMC_BTRx_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 623:db79ecd649d0 | 4344 | #define FMC_BTRx_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4345 | #define FMC_BTRx_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4346 | #define FMC_BTRx_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4347 | #define FMC_BTRx_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4348 | #define FMC_BTRx_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 4349 | #define FMC_BTRx_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 4350 | #define FMC_BTRx_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 4351 | #define FMC_BTRx_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 4352 | |
| mbed_official | 623:db79ecd649d0 | 4353 | #define FMC_BTRx_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ |
| mbed_official | 623:db79ecd649d0 | 4354 | #define FMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4355 | #define FMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4356 | #define FMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4357 | #define FMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4358 | |
| mbed_official | 623:db79ecd649d0 | 4359 | #define FMC_BTRx_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */ |
| mbed_official | 623:db79ecd649d0 | 4360 | #define FMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4361 | #define FMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4362 | #define FMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4363 | #define FMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4364 | |
| mbed_official | 623:db79ecd649d0 | 4365 | #define FMC_BTRx_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */ |
| mbed_official | 623:db79ecd649d0 | 4366 | #define FMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4367 | #define FMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4368 | #define FMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4369 | #define FMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4370 | |
| mbed_official | 623:db79ecd649d0 | 4371 | #define FMC_BTRx_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 623:db79ecd649d0 | 4372 | #define FMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4373 | #define FMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4374 | |
| mbed_official | 623:db79ecd649d0 | 4375 | /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/ |
| mbed_official | 623:db79ecd649d0 | 4376 | #define FMC_BWTRx_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */ |
| mbed_official | 623:db79ecd649d0 | 4377 | #define FMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4378 | #define FMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4379 | #define FMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4380 | #define FMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4381 | |
| mbed_official | 623:db79ecd649d0 | 4382 | #define FMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ |
| mbed_official | 623:db79ecd649d0 | 4383 | #define FMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4384 | #define FMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4385 | #define FMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4386 | #define FMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4387 | |
| mbed_official | 623:db79ecd649d0 | 4388 | #define FMC_BWTRx_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */ |
| mbed_official | 623:db79ecd649d0 | 4389 | #define FMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4390 | #define FMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4391 | #define FMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4392 | #define FMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4393 | #define FMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 4394 | #define FMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 4395 | #define FMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 4396 | #define FMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 4397 | |
| mbed_official | 623:db79ecd649d0 | 4398 | #define FMC_BWTRx_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */ |
| mbed_official | 623:db79ecd649d0 | 4399 | #define FMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4400 | #define FMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4401 | |
| mbed_official | 623:db79ecd649d0 | 4402 | /****************** Bit definition for FMC_PCR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 4403 | #define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4404 | #define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<NAND Flash memory bank enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4405 | #define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */ |
| mbed_official | 623:db79ecd649d0 | 4406 | |
| mbed_official | 623:db79ecd649d0 | 4407 | #define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */ |
| mbed_official | 623:db79ecd649d0 | 4408 | #define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4409 | #define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4410 | |
| mbed_official | 623:db79ecd649d0 | 4411 | #define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4412 | |
| mbed_official | 623:db79ecd649d0 | 4413 | #define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */ |
| mbed_official | 623:db79ecd649d0 | 4414 | #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4415 | #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4416 | #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4417 | #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4418 | |
| mbed_official | 623:db79ecd649d0 | 4419 | #define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */ |
| mbed_official | 623:db79ecd649d0 | 4420 | #define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4421 | #define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4422 | #define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4423 | #define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4424 | |
| mbed_official | 623:db79ecd649d0 | 4425 | #define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */ |
| mbed_official | 623:db79ecd649d0 | 4426 | #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4427 | #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4428 | #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4429 | |
| mbed_official | 623:db79ecd649d0 | 4430 | /******************* Bit definition for FMC_SR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 4431 | #define FMC_SR_IRS ((uint32_t)0x00000001) /*!<Interrupt Rising Edge status */ |
| mbed_official | 623:db79ecd649d0 | 4432 | #define FMC_SR_ILS ((uint32_t)0x00000002) /*!<Interrupt Level status */ |
| mbed_official | 623:db79ecd649d0 | 4433 | #define FMC_SR_IFS ((uint32_t)0x00000004) /*!<Interrupt Falling Edge status */ |
| mbed_official | 623:db79ecd649d0 | 4434 | #define FMC_SR_IREN ((uint32_t)0x00000008) /*!<Interrupt Rising Edge detection Enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4435 | #define FMC_SR_ILEN ((uint32_t)0x00000010) /*!<Interrupt Level detection Enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4436 | #define FMC_SR_IFEN ((uint32_t)0x00000020) /*!<Interrupt Falling Edge detection Enable bit */ |
| mbed_official | 623:db79ecd649d0 | 4437 | #define FMC_SR_FEMPT ((uint32_t)0x00000040) /*!<FIFO empty */ |
| mbed_official | 623:db79ecd649d0 | 4438 | |
| mbed_official | 623:db79ecd649d0 | 4439 | /****************** Bit definition for FMC_PMEM register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4440 | #define FMC_PMEM_MEMSET ((uint32_t)0x000000FF) /*!<MEMSET[7:0] bits (Common memory setup time) */ |
| mbed_official | 623:db79ecd649d0 | 4441 | #define FMC_PMEM_MEMSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4442 | #define FMC_PMEM_MEMSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4443 | #define FMC_PMEM_MEMSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4444 | #define FMC_PMEM_MEMSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4445 | #define FMC_PMEM_MEMSET_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 4446 | #define FMC_PMEM_MEMSET_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 4447 | #define FMC_PMEM_MEMSET_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 4448 | #define FMC_PMEM_MEMSET_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 4449 | |
| mbed_official | 623:db79ecd649d0 | 4450 | #define FMC_PMEM_MEMWAIT ((uint32_t)0x0000FF00) /*!<MEMWAIT[7:0] bits (Common memory wait time) */ |
| mbed_official | 623:db79ecd649d0 | 4451 | #define FMC_PMEM_MEMWAIT_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4452 | #define FMC_PMEM_MEMWAIT_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4453 | #define FMC_PMEM_MEMWAIT_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4454 | #define FMC_PMEM_MEMWAIT_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4455 | #define FMC_PMEM_MEMWAIT_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 4456 | #define FMC_PMEM_MEMWAIT_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 4457 | #define FMC_PMEM_MEMWAIT_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 4458 | #define FMC_PMEM_MEMWAIT_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 4459 | |
| mbed_official | 623:db79ecd649d0 | 4460 | #define FMC_PMEM_MEMHOLD ((uint32_t)0x00FF0000) /*!<MEMHOLD[7:0] bits (Common memory hold time) */ |
| mbed_official | 623:db79ecd649d0 | 4461 | #define FMC_PMEM_MEMHOLD_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4462 | #define FMC_PMEM_MEMHOLD_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4463 | #define FMC_PMEM_MEMHOLD_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4464 | #define FMC_PMEM_MEMHOLD_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4465 | #define FMC_PMEM_MEMHOLD_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 4466 | #define FMC_PMEM_MEMHOLD_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 4467 | #define FMC_PMEM_MEMHOLD_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 4468 | #define FMC_PMEM_MEMHOLD_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 4469 | |
| mbed_official | 623:db79ecd649d0 | 4470 | #define FMC_PMEM_MEMHIZ ((uint32_t)0xFF000000) /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */ |
| mbed_official | 623:db79ecd649d0 | 4471 | #define FMC_PMEM_MEMHIZ_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4472 | #define FMC_PMEM_MEMHIZ_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4473 | #define FMC_PMEM_MEMHIZ_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4474 | #define FMC_PMEM_MEMHIZ_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4475 | #define FMC_PMEM_MEMHIZ_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 4476 | #define FMC_PMEM_MEMHIZ_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 4477 | #define FMC_PMEM_MEMHIZ_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 4478 | #define FMC_PMEM_MEMHIZ_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 4479 | |
| mbed_official | 623:db79ecd649d0 | 4480 | /****************** Bit definition for FMC_PATT register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4481 | #define FMC_PATT_ATTSET ((uint32_t)0x000000FF) /*!<ATTSET[7:0] bits (Attribute memory setup time) */ |
| mbed_official | 623:db79ecd649d0 | 4482 | #define FMC_PATT_ATTSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4483 | #define FMC_PATT_ATTSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4484 | #define FMC_PATT_ATTSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4485 | #define FMC_PATT_ATTSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4486 | #define FMC_PATT_ATTSET_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 4487 | #define FMC_PATT_ATTSET_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 4488 | #define FMC_PATT_ATTSET_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 4489 | #define FMC_PATT_ATTSET_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 4490 | |
| mbed_official | 623:db79ecd649d0 | 4491 | #define FMC_PATT_ATTWAIT ((uint32_t)0x0000FF00) /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */ |
| mbed_official | 623:db79ecd649d0 | 4492 | #define FMC_PATT_ATTWAIT_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4493 | #define FMC_PATT_ATTWAIT_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4494 | #define FMC_PATT_ATTWAIT_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4495 | #define FMC_PATT_ATTWAIT_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4496 | #define FMC_PATT_ATTWAIT_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 4497 | #define FMC_PATT_ATTWAIT_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 4498 | #define FMC_PATT_ATTWAIT_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 4499 | #define FMC_PATT_ATTWAIT_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 4500 | |
| mbed_official | 623:db79ecd649d0 | 4501 | #define FMC_PATT_ATTHOLD ((uint32_t)0x00FF0000) /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */ |
| mbed_official | 623:db79ecd649d0 | 4502 | #define FMC_PATT_ATTHOLD_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4503 | #define FMC_PATT_ATTHOLD_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4504 | #define FMC_PATT_ATTHOLD_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4505 | #define FMC_PATT_ATTHOLD_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4506 | #define FMC_PATT_ATTHOLD_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 4507 | #define FMC_PATT_ATTHOLD_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 4508 | #define FMC_PATT_ATTHOLD_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 4509 | #define FMC_PATT_ATTHOLD_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 4510 | |
| mbed_official | 623:db79ecd649d0 | 4511 | #define FMC_PATT_ATTHIZ ((uint32_t)0xFF000000) /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */ |
| mbed_official | 623:db79ecd649d0 | 4512 | #define FMC_PATT_ATTHIZ_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 4513 | #define FMC_PATT_ATTHIZ_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 4514 | #define FMC_PATT_ATTHIZ_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 4515 | #define FMC_PATT_ATTHIZ_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 4516 | #define FMC_PATT_ATTHIZ_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 4517 | #define FMC_PATT_ATTHIZ_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 4518 | #define FMC_PATT_ATTHIZ_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 4519 | #define FMC_PATT_ATTHIZ_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 4520 | |
| mbed_official | 623:db79ecd649d0 | 4521 | /****************** Bit definition for FMC_ECCR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4522 | #define FMC_ECCR_ECC ((uint32_t)0xFFFFFFFF) /*!<ECC result */ |
| mbed_official | 623:db79ecd649d0 | 4523 | |
| mbed_official | 623:db79ecd649d0 | 4524 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 4525 | /* */ |
| mbed_official | 623:db79ecd649d0 | 4526 | /* General Purpose I/O */ |
| mbed_official | 623:db79ecd649d0 | 4527 | /* */ |
| mbed_official | 623:db79ecd649d0 | 4528 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 4529 | /****************** Bits definition for GPIO_MODER register *****************/ |
| mbed_official | 623:db79ecd649d0 | 4530 | #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) |
| mbed_official | 623:db79ecd649d0 | 4531 | #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4532 | #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4533 | #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) |
| mbed_official | 623:db79ecd649d0 | 4534 | #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4535 | #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4536 | #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) |
| mbed_official | 623:db79ecd649d0 | 4537 | #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4538 | #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4539 | #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) |
| mbed_official | 623:db79ecd649d0 | 4540 | #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4541 | #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4542 | #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) |
| mbed_official | 623:db79ecd649d0 | 4543 | #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4544 | #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4545 | #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) |
| mbed_official | 623:db79ecd649d0 | 4546 | #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4547 | #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4548 | #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) |
| mbed_official | 623:db79ecd649d0 | 4549 | #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4550 | #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4551 | #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) |
| mbed_official | 623:db79ecd649d0 | 4552 | #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4553 | #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4554 | #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) |
| mbed_official | 623:db79ecd649d0 | 4555 | #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 4556 | #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 4557 | #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) |
| mbed_official | 623:db79ecd649d0 | 4558 | #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 4559 | #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 4560 | #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) |
| mbed_official | 623:db79ecd649d0 | 4561 | #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 4562 | #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 4563 | #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) |
| mbed_official | 623:db79ecd649d0 | 4564 | #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 4565 | #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 4566 | #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) |
| mbed_official | 623:db79ecd649d0 | 4567 | #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 4568 | #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 4569 | #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) |
| mbed_official | 623:db79ecd649d0 | 4570 | #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 4571 | #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 4572 | #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) |
| mbed_official | 623:db79ecd649d0 | 4573 | #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 4574 | #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 4575 | #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) |
| mbed_official | 623:db79ecd649d0 | 4576 | #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 4577 | #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 4578 | |
| mbed_official | 623:db79ecd649d0 | 4579 | /****************** Bits definition for GPIO_OTYPER register ****************/ |
| mbed_official | 623:db79ecd649d0 | 4580 | #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4581 | #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4582 | #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4583 | #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4584 | #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4585 | #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4586 | #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4587 | #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4588 | #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4589 | #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4590 | #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4591 | #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4592 | #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4593 | #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4594 | #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4595 | #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4596 | |
| mbed_official | 623:db79ecd649d0 | 4597 | /****************** Bits definition for GPIO_OSPEEDR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 4598 | #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) |
| mbed_official | 623:db79ecd649d0 | 4599 | #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4600 | #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4601 | #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) |
| mbed_official | 623:db79ecd649d0 | 4602 | #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4603 | #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4604 | #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) |
| mbed_official | 623:db79ecd649d0 | 4605 | #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4606 | #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4607 | #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) |
| mbed_official | 623:db79ecd649d0 | 4608 | #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4609 | #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4610 | #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) |
| mbed_official | 623:db79ecd649d0 | 4611 | #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4612 | #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4613 | #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) |
| mbed_official | 623:db79ecd649d0 | 4614 | #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4615 | #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4616 | #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) |
| mbed_official | 623:db79ecd649d0 | 4617 | #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4618 | #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4619 | #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) |
| mbed_official | 623:db79ecd649d0 | 4620 | #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4621 | #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4622 | #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) |
| mbed_official | 623:db79ecd649d0 | 4623 | #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 4624 | #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 4625 | #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) |
| mbed_official | 623:db79ecd649d0 | 4626 | #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 4627 | #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 4628 | #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) |
| mbed_official | 623:db79ecd649d0 | 4629 | #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 4630 | #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 4631 | #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) |
| mbed_official | 623:db79ecd649d0 | 4632 | #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 4633 | #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 4634 | #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) |
| mbed_official | 623:db79ecd649d0 | 4635 | #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 4636 | #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 4637 | #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) |
| mbed_official | 623:db79ecd649d0 | 4638 | #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 4639 | #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 4640 | #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) |
| mbed_official | 623:db79ecd649d0 | 4641 | #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 4642 | #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 4643 | #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) |
| mbed_official | 623:db79ecd649d0 | 4644 | #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 4645 | #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 4646 | |
| mbed_official | 623:db79ecd649d0 | 4647 | /****************** Bits definition for GPIO_PUPDR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 4648 | #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) |
| mbed_official | 623:db79ecd649d0 | 4649 | #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4650 | #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4651 | #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) |
| mbed_official | 623:db79ecd649d0 | 4652 | #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4653 | #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4654 | #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) |
| mbed_official | 623:db79ecd649d0 | 4655 | #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4656 | #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4657 | #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) |
| mbed_official | 623:db79ecd649d0 | 4658 | #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4659 | #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4660 | #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) |
| mbed_official | 623:db79ecd649d0 | 4661 | #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4662 | #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4663 | #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) |
| mbed_official | 623:db79ecd649d0 | 4664 | #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4665 | #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4666 | #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) |
| mbed_official | 623:db79ecd649d0 | 4667 | #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4668 | #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4669 | #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) |
| mbed_official | 623:db79ecd649d0 | 4670 | #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4671 | #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4672 | #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) |
| mbed_official | 623:db79ecd649d0 | 4673 | #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 4674 | #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 4675 | #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) |
| mbed_official | 623:db79ecd649d0 | 4676 | #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 4677 | #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 4678 | #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) |
| mbed_official | 623:db79ecd649d0 | 4679 | #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 4680 | #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 4681 | #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) |
| mbed_official | 623:db79ecd649d0 | 4682 | #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 4683 | #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 4684 | #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) |
| mbed_official | 623:db79ecd649d0 | 4685 | #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 4686 | #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 4687 | #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) |
| mbed_official | 623:db79ecd649d0 | 4688 | #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 4689 | #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 4690 | #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) |
| mbed_official | 623:db79ecd649d0 | 4691 | #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 4692 | #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 4693 | #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) |
| mbed_official | 623:db79ecd649d0 | 4694 | #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 4695 | #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 4696 | |
| mbed_official | 623:db79ecd649d0 | 4697 | /****************** Bits definition for GPIO_IDR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4698 | #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4699 | #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4700 | #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4701 | #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4702 | #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4703 | #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4704 | #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4705 | #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4706 | #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4707 | #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4708 | #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4709 | #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4710 | #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4711 | #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4712 | #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4713 | #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4714 | |
| mbed_official | 623:db79ecd649d0 | 4715 | /* Old GPIO_IDR register bits definition, maintained for legacy purpose */ |
| mbed_official | 623:db79ecd649d0 | 4716 | #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 |
| mbed_official | 623:db79ecd649d0 | 4717 | #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 |
| mbed_official | 623:db79ecd649d0 | 4718 | #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 |
| mbed_official | 623:db79ecd649d0 | 4719 | #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 |
| mbed_official | 623:db79ecd649d0 | 4720 | #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 |
| mbed_official | 623:db79ecd649d0 | 4721 | #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 |
| mbed_official | 623:db79ecd649d0 | 4722 | #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 |
| mbed_official | 623:db79ecd649d0 | 4723 | #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 |
| mbed_official | 623:db79ecd649d0 | 4724 | #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 |
| mbed_official | 623:db79ecd649d0 | 4725 | #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 |
| mbed_official | 623:db79ecd649d0 | 4726 | #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 |
| mbed_official | 623:db79ecd649d0 | 4727 | #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 |
| mbed_official | 623:db79ecd649d0 | 4728 | #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 |
| mbed_official | 623:db79ecd649d0 | 4729 | #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 |
| mbed_official | 623:db79ecd649d0 | 4730 | #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 |
| mbed_official | 623:db79ecd649d0 | 4731 | #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 |
| mbed_official | 623:db79ecd649d0 | 4732 | |
| mbed_official | 623:db79ecd649d0 | 4733 | /****************** Bits definition for GPIO_ODR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4734 | #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4735 | #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4736 | #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4737 | #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4738 | #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4739 | #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4740 | #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4741 | #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4742 | #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4743 | #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4744 | #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4745 | #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4746 | #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4747 | #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4748 | #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4749 | #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4750 | |
| mbed_official | 623:db79ecd649d0 | 4751 | /* Old GPIO_ODR register bits definition, maintained for legacy purpose */ |
| mbed_official | 623:db79ecd649d0 | 4752 | #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 |
| mbed_official | 623:db79ecd649d0 | 4753 | #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 |
| mbed_official | 623:db79ecd649d0 | 4754 | #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 |
| mbed_official | 623:db79ecd649d0 | 4755 | #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 |
| mbed_official | 623:db79ecd649d0 | 4756 | #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 |
| mbed_official | 623:db79ecd649d0 | 4757 | #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 |
| mbed_official | 623:db79ecd649d0 | 4758 | #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 |
| mbed_official | 623:db79ecd649d0 | 4759 | #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 |
| mbed_official | 623:db79ecd649d0 | 4760 | #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 |
| mbed_official | 623:db79ecd649d0 | 4761 | #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 |
| mbed_official | 623:db79ecd649d0 | 4762 | #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 |
| mbed_official | 623:db79ecd649d0 | 4763 | #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 |
| mbed_official | 623:db79ecd649d0 | 4764 | #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 |
| mbed_official | 623:db79ecd649d0 | 4765 | #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 |
| mbed_official | 623:db79ecd649d0 | 4766 | #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 |
| mbed_official | 623:db79ecd649d0 | 4767 | #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 |
| mbed_official | 623:db79ecd649d0 | 4768 | |
| mbed_official | 623:db79ecd649d0 | 4769 | /****************** Bits definition for GPIO_BSRR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4770 | #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4771 | #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4772 | #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4773 | #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4774 | #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4775 | #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4776 | #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4777 | #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4778 | #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4779 | #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4780 | #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4781 | #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4782 | #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4783 | #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4784 | #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4785 | #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4786 | #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 4787 | #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 4788 | #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 4789 | #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 4790 | #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 4791 | #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 4792 | #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 4793 | #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 4794 | #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 4795 | #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 4796 | #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 4797 | #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 4798 | #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 4799 | #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 4800 | #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 4801 | #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 4802 | |
| mbed_official | 623:db79ecd649d0 | 4803 | /****************** Bits definition for GPIO_BRR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4804 | #define GPIO_BRR_BR_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4805 | #define GPIO_BRR_BR_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4806 | #define GPIO_BRR_BR_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4807 | #define GPIO_BRR_BR_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4808 | #define GPIO_BRR_BR_4 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4809 | #define GPIO_BRR_BR_5 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4810 | #define GPIO_BRR_BR_6 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4811 | #define GPIO_BRR_BR_7 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4812 | #define GPIO_BRR_BR_8 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4813 | #define GPIO_BRR_BR_9 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4814 | #define GPIO_BRR_BR_10 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4815 | #define GPIO_BRR_BR_11 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4816 | #define GPIO_BRR_BR_12 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4817 | #define GPIO_BRR_BR_13 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4818 | #define GPIO_BRR_BR_14 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4819 | #define GPIO_BRR_BR_15 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4820 | |
| mbed_official | 623:db79ecd649d0 | 4821 | /****************** Bit definition for GPIO_LCKR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 4822 | #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4823 | #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4824 | #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4825 | #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4826 | #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4827 | #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4828 | #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4829 | #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4830 | #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4831 | #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4832 | #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4833 | #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4834 | #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4835 | #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4836 | #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4837 | #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4838 | #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 4839 | |
| mbed_official | 623:db79ecd649d0 | 4840 | /****************** Bit definition for GPIO_AFRL register ********************/ |
| mbed_official | 623:db79ecd649d0 | 4841 | #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) |
| mbed_official | 623:db79ecd649d0 | 4842 | #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) |
| mbed_official | 623:db79ecd649d0 | 4843 | #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) |
| mbed_official | 623:db79ecd649d0 | 4844 | #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) |
| mbed_official | 623:db79ecd649d0 | 4845 | #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) |
| mbed_official | 623:db79ecd649d0 | 4846 | #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) |
| mbed_official | 623:db79ecd649d0 | 4847 | #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) |
| mbed_official | 623:db79ecd649d0 | 4848 | #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) |
| mbed_official | 623:db79ecd649d0 | 4849 | |
| mbed_official | 623:db79ecd649d0 | 4850 | /****************** Bit definition for GPIO_AFRH register ********************/ |
| mbed_official | 623:db79ecd649d0 | 4851 | #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F) |
| mbed_official | 623:db79ecd649d0 | 4852 | #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0) |
| mbed_official | 623:db79ecd649d0 | 4853 | #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00) |
| mbed_official | 623:db79ecd649d0 | 4854 | #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000) |
| mbed_official | 623:db79ecd649d0 | 4855 | #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000) |
| mbed_official | 623:db79ecd649d0 | 4856 | #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000) |
| mbed_official | 623:db79ecd649d0 | 4857 | #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000) |
| mbed_official | 623:db79ecd649d0 | 4858 | #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000) |
| mbed_official | 623:db79ecd649d0 | 4859 | |
| mbed_official | 623:db79ecd649d0 | 4860 | /****************** Bits definition for GPIO_ASCR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4861 | #define GPIO_ASCR_EN_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 4862 | #define GPIO_ASCR_EN_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 4863 | #define GPIO_ASCR_EN_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 4864 | #define GPIO_ASCR_EN_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 4865 | #define GPIO_ASCR_EN_4 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 4866 | #define GPIO_ASCR_EN_5 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 4867 | #define GPIO_ASCR_EN_6 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 4868 | #define GPIO_ASCR_EN_7 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 4869 | #define GPIO_ASCR_EN_8 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 4870 | #define GPIO_ASCR_EN_9 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 4871 | #define GPIO_ASCR_EN_10 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 4872 | #define GPIO_ASCR_EN_11 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 4873 | #define GPIO_ASCR_EN_12 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 4874 | #define GPIO_ASCR_EN_13 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 4875 | #define GPIO_ASCR_EN_14 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 4876 | #define GPIO_ASCR_EN_15 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 4877 | |
| mbed_official | 623:db79ecd649d0 | 4878 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 4879 | /* */ |
| mbed_official | 623:db79ecd649d0 | 4880 | /* Inter-integrated Circuit Interface (I2C) */ |
| mbed_official | 623:db79ecd649d0 | 4881 | /* */ |
| mbed_official | 623:db79ecd649d0 | 4882 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 4883 | /******************* Bit definition for I2C_CR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4884 | #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */ |
| mbed_official | 623:db79ecd649d0 | 4885 | #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 4886 | #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 4887 | #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 4888 | #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 4889 | #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 4890 | #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 4891 | #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 4892 | #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */ |
| mbed_official | 623:db79ecd649d0 | 4893 | #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */ |
| mbed_official | 623:db79ecd649d0 | 4894 | #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */ |
| mbed_official | 623:db79ecd649d0 | 4895 | #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */ |
| mbed_official | 623:db79ecd649d0 | 4896 | #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */ |
| mbed_official | 623:db79ecd649d0 | 4897 | #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */ |
| mbed_official | 623:db79ecd649d0 | 4898 | #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */ |
| mbed_official | 623:db79ecd649d0 | 4899 | #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */ |
| mbed_official | 623:db79ecd649d0 | 4900 | #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */ |
| mbed_official | 623:db79ecd649d0 | 4901 | #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */ |
| mbed_official | 623:db79ecd649d0 | 4902 | #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */ |
| mbed_official | 623:db79ecd649d0 | 4903 | #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */ |
| mbed_official | 623:db79ecd649d0 | 4904 | #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */ |
| mbed_official | 623:db79ecd649d0 | 4905 | |
| mbed_official | 623:db79ecd649d0 | 4906 | /****************** Bit definition for I2C_CR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 4907 | #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */ |
| mbed_official | 623:db79ecd649d0 | 4908 | #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */ |
| mbed_official | 623:db79ecd649d0 | 4909 | #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */ |
| mbed_official | 623:db79ecd649d0 | 4910 | #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */ |
| mbed_official | 623:db79ecd649d0 | 4911 | #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */ |
| mbed_official | 623:db79ecd649d0 | 4912 | #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */ |
| mbed_official | 623:db79ecd649d0 | 4913 | #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */ |
| mbed_official | 623:db79ecd649d0 | 4914 | #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */ |
| mbed_official | 623:db79ecd649d0 | 4915 | #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */ |
| mbed_official | 623:db79ecd649d0 | 4916 | #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */ |
| mbed_official | 623:db79ecd649d0 | 4917 | #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */ |
| mbed_official | 623:db79ecd649d0 | 4918 | |
| mbed_official | 623:db79ecd649d0 | 4919 | /******************* Bit definition for I2C_OAR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4920 | #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */ |
| mbed_official | 623:db79ecd649d0 | 4921 | #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */ |
| mbed_official | 623:db79ecd649d0 | 4922 | #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */ |
| mbed_official | 623:db79ecd649d0 | 4923 | |
| mbed_official | 623:db79ecd649d0 | 4924 | /******************* Bit definition for I2C_OAR2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 4925 | #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */ |
| mbed_official | 623:db79ecd649d0 | 4926 | #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */ |
| mbed_official | 623:db79ecd649d0 | 4927 | #define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */ |
| mbed_official | 623:db79ecd649d0 | 4928 | #define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */ |
| mbed_official | 623:db79ecd649d0 | 4929 | #define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ |
| mbed_official | 623:db79ecd649d0 | 4930 | #define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ |
| mbed_official | 623:db79ecd649d0 | 4931 | #define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ |
| mbed_official | 623:db79ecd649d0 | 4932 | #define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ |
| mbed_official | 623:db79ecd649d0 | 4933 | #define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */ |
| mbed_official | 623:db79ecd649d0 | 4934 | #define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */ |
| mbed_official | 623:db79ecd649d0 | 4935 | #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */ |
| mbed_official | 623:db79ecd649d0 | 4936 | |
| mbed_official | 623:db79ecd649d0 | 4937 | /******************* Bit definition for I2C_TIMINGR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4938 | #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */ |
| mbed_official | 623:db79ecd649d0 | 4939 | #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */ |
| mbed_official | 623:db79ecd649d0 | 4940 | #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */ |
| mbed_official | 623:db79ecd649d0 | 4941 | #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */ |
| mbed_official | 623:db79ecd649d0 | 4942 | #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */ |
| mbed_official | 623:db79ecd649d0 | 4943 | |
| mbed_official | 623:db79ecd649d0 | 4944 | /******************* Bit definition for I2C_TIMEOUTR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 4945 | #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */ |
| mbed_official | 623:db79ecd649d0 | 4946 | #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */ |
| mbed_official | 623:db79ecd649d0 | 4947 | #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */ |
| mbed_official | 623:db79ecd649d0 | 4948 | #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */ |
| mbed_official | 623:db79ecd649d0 | 4949 | #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */ |
| mbed_official | 623:db79ecd649d0 | 4950 | |
| mbed_official | 623:db79ecd649d0 | 4951 | /****************** Bit definition for I2C_ISR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 4952 | #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */ |
| mbed_official | 623:db79ecd649d0 | 4953 | #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */ |
| mbed_official | 623:db79ecd649d0 | 4954 | #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */ |
| mbed_official | 623:db79ecd649d0 | 4955 | #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */ |
| mbed_official | 623:db79ecd649d0 | 4956 | #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */ |
| mbed_official | 623:db79ecd649d0 | 4957 | #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */ |
| mbed_official | 623:db79ecd649d0 | 4958 | #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */ |
| mbed_official | 623:db79ecd649d0 | 4959 | #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */ |
| mbed_official | 623:db79ecd649d0 | 4960 | #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */ |
| mbed_official | 623:db79ecd649d0 | 4961 | #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */ |
| mbed_official | 623:db79ecd649d0 | 4962 | #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */ |
| mbed_official | 623:db79ecd649d0 | 4963 | #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */ |
| mbed_official | 623:db79ecd649d0 | 4964 | #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */ |
| mbed_official | 623:db79ecd649d0 | 4965 | #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */ |
| mbed_official | 623:db79ecd649d0 | 4966 | #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */ |
| mbed_official | 623:db79ecd649d0 | 4967 | #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */ |
| mbed_official | 623:db79ecd649d0 | 4968 | #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */ |
| mbed_official | 623:db79ecd649d0 | 4969 | |
| mbed_official | 623:db79ecd649d0 | 4970 | /****************** Bit definition for I2C_ICR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 4971 | #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */ |
| mbed_official | 623:db79ecd649d0 | 4972 | #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */ |
| mbed_official | 623:db79ecd649d0 | 4973 | #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */ |
| mbed_official | 623:db79ecd649d0 | 4974 | #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */ |
| mbed_official | 623:db79ecd649d0 | 4975 | #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */ |
| mbed_official | 623:db79ecd649d0 | 4976 | #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */ |
| mbed_official | 623:db79ecd649d0 | 4977 | #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */ |
| mbed_official | 623:db79ecd649d0 | 4978 | #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */ |
| mbed_official | 623:db79ecd649d0 | 4979 | #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */ |
| mbed_official | 623:db79ecd649d0 | 4980 | |
| mbed_official | 623:db79ecd649d0 | 4981 | /****************** Bit definition for I2C_PECR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 4982 | #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */ |
| mbed_official | 623:db79ecd649d0 | 4983 | |
| mbed_official | 623:db79ecd649d0 | 4984 | /****************** Bit definition for I2C_RXDR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 4985 | #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */ |
| mbed_official | 623:db79ecd649d0 | 4986 | |
| mbed_official | 623:db79ecd649d0 | 4987 | /****************** Bit definition for I2C_TXDR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 4988 | #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */ |
| mbed_official | 623:db79ecd649d0 | 4989 | |
| mbed_official | 623:db79ecd649d0 | 4990 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 4991 | /* */ |
| mbed_official | 623:db79ecd649d0 | 4992 | /* Independent WATCHDOG */ |
| mbed_official | 623:db79ecd649d0 | 4993 | /* */ |
| mbed_official | 623:db79ecd649d0 | 4994 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 4995 | /******************* Bit definition for IWDG_KR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 4996 | #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!<Key value (write only, read 0000h) */ |
| mbed_official | 623:db79ecd649d0 | 4997 | |
| mbed_official | 623:db79ecd649d0 | 4998 | /******************* Bit definition for IWDG_PR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 4999 | #define IWDG_PR_PR ((uint32_t)0x00000007) /*!<PR[2:0] (Prescaler divider) */ |
| mbed_official | 623:db79ecd649d0 | 5000 | #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5001 | #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5002 | #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 5003 | |
| mbed_official | 623:db79ecd649d0 | 5004 | /******************* Bit definition for IWDG_RLR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 5005 | #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!<Watchdog counter reload value */ |
| mbed_official | 623:db79ecd649d0 | 5006 | |
| mbed_official | 623:db79ecd649d0 | 5007 | /******************* Bit definition for IWDG_SR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5008 | #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */ |
| mbed_official | 623:db79ecd649d0 | 5009 | #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */ |
| mbed_official | 623:db79ecd649d0 | 5010 | #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */ |
| mbed_official | 623:db79ecd649d0 | 5011 | |
| mbed_official | 623:db79ecd649d0 | 5012 | /******************* Bit definition for IWDG_KR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5013 | #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */ |
| mbed_official | 623:db79ecd649d0 | 5014 | |
| mbed_official | 623:db79ecd649d0 | 5015 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 5016 | /* */ |
| mbed_official | 623:db79ecd649d0 | 5017 | /* Firewall */ |
| mbed_official | 623:db79ecd649d0 | 5018 | /* */ |
| mbed_official | 623:db79ecd649d0 | 5019 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 5020 | |
| mbed_official | 623:db79ecd649d0 | 5021 | /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register */ |
| mbed_official | 623:db79ecd649d0 | 5022 | #define FW_CSSA_ADD ((uint32_t)0x00FFFF00) /*!< Code Segment Start Address */ |
| mbed_official | 623:db79ecd649d0 | 5023 | #define FW_CSL_LENG ((uint32_t)0x003FFF00) /*!< Code Segment Length */ |
| mbed_official | 623:db79ecd649d0 | 5024 | #define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00) /*!< Non Volatile Dat Segment Start Address */ |
| mbed_official | 623:db79ecd649d0 | 5025 | #define FW_NVDSL_LENG ((uint32_t)0x003FFF00) /*!< Non Volatile Data Segment Length */ |
| mbed_official | 623:db79ecd649d0 | 5026 | #define FW_VDSSA_ADD ((uint32_t)0x0001FFC0) /*!< Volatile Data Segment Start Address */ |
| mbed_official | 623:db79ecd649d0 | 5027 | #define FW_VDSL_LENG ((uint32_t)0x0001FFC0) /*!< Volatile Data Segment Length */ |
| mbed_official | 623:db79ecd649d0 | 5028 | #define FW_LSSA_ADD ((uint32_t)0x0007FF80) /*!< Library Segment Start Address*/ |
| mbed_official | 623:db79ecd649d0 | 5029 | #define FW_LSL_LENG ((uint32_t)0x0007FF80) /*!< Library Segment Length*/ |
| mbed_official | 623:db79ecd649d0 | 5030 | |
| mbed_official | 623:db79ecd649d0 | 5031 | /**************************Bit definition for CR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 5032 | #define FW_CR_FPA ((uint32_t)0x00000001) /*!< Firewall Pre Arm*/ |
| mbed_official | 623:db79ecd649d0 | 5033 | #define FW_CR_VDS ((uint32_t)0x00000002) /*!< Volatile Data Sharing*/ |
| mbed_official | 623:db79ecd649d0 | 5034 | #define FW_CR_VDE ((uint32_t)0x00000004) /*!< Volatile Data Execution*/ |
| mbed_official | 623:db79ecd649d0 | 5035 | |
| mbed_official | 623:db79ecd649d0 | 5036 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 5037 | /* */ |
| mbed_official | 623:db79ecd649d0 | 5038 | /* Power Control */ |
| mbed_official | 623:db79ecd649d0 | 5039 | /* */ |
| mbed_official | 623:db79ecd649d0 | 5040 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 5041 | |
| mbed_official | 623:db79ecd649d0 | 5042 | /******************** Bit definition for PWR_CR1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5043 | |
| mbed_official | 623:db79ecd649d0 | 5044 | #define PWR_CR1_LPR ((uint32_t)0x00004000) /*!< Regulator low-power mode */ |
| mbed_official | 623:db79ecd649d0 | 5045 | #define PWR_CR1_VOS ((uint32_t)0x00000600) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ |
| mbed_official | 623:db79ecd649d0 | 5046 | #define PWR_CR1_VOS_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5047 | #define PWR_CR1_VOS_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5048 | #define PWR_CR1_DBP ((uint32_t)0x00000100) /*!< Disable Back-up domain Protection */ |
| mbed_official | 623:db79ecd649d0 | 5049 | #define PWR_CR1_LPMS ((uint32_t)0x00000007) /*!< Low-power mode selection field */ |
| mbed_official | 623:db79ecd649d0 | 5050 | #define PWR_CR1_LPMS_STOP1MR ((uint32_t)0x00000000) /*!< Stop 1 mode with Main Regulator */ |
| mbed_official | 623:db79ecd649d0 | 5051 | #define PWR_CR1_LPMS_STOP1LPR ((uint32_t)0x00000001) /*!< Stop 1 mode with Low-Power Regulator */ |
| mbed_official | 623:db79ecd649d0 | 5052 | #define PWR_CR1_LPMS_STOP2 ((uint32_t)0x00000002) /*!< Stop 2 mode */ |
| mbed_official | 623:db79ecd649d0 | 5053 | #define PWR_CR1_LPMS_STANDBY ((uint32_t)0x00000003) /*!< Stand-by mode */ |
| mbed_official | 623:db79ecd649d0 | 5054 | #define PWR_CR1_LPMS_SHUTDOWN ((uint32_t)0x00000004) /*!< Shut-down mode */ |
| mbed_official | 623:db79ecd649d0 | 5055 | |
| mbed_official | 623:db79ecd649d0 | 5056 | |
| mbed_official | 623:db79ecd649d0 | 5057 | /******************** Bit definition for PWR_CR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5058 | #define PWR_CR2_USV ((uint32_t)0x00000400) /*!< VDD USB Supply Valid */ |
| mbed_official | 623:db79ecd649d0 | 5059 | #define PWR_CR2_IOSV ((uint32_t)0x00000200) /*!< VDD IO2 independent I/Os Supply Valid */ |
| mbed_official | 623:db79ecd649d0 | 5060 | /*!< PVME Peripheral Voltage Monitor Enable */ |
| mbed_official | 623:db79ecd649d0 | 5061 | #define PWR_CR2_PVME ((uint32_t)0x000000F0) /*!< PVM bits field */ |
| mbed_official | 623:db79ecd649d0 | 5062 | #define PWR_CR2_PVME4 ((uint32_t)0x00000080) /*!< PVM 4 Enable */ |
| mbed_official | 623:db79ecd649d0 | 5063 | #define PWR_CR2_PVME3 ((uint32_t)0x00000040) /*!< PVM 3 Enable */ |
| mbed_official | 623:db79ecd649d0 | 5064 | #define PWR_CR2_PVME2 ((uint32_t)0x00000020) /*!< PVM 2 Enable */ |
| mbed_official | 623:db79ecd649d0 | 5065 | #define PWR_CR2_PVME1 ((uint32_t)0x00000010) /*!< PVM 1 Enable */ |
| mbed_official | 623:db79ecd649d0 | 5066 | /*!< PVD level configuration */ |
| mbed_official | 623:db79ecd649d0 | 5067 | #define PWR_CR2_PLS ((uint32_t)0x0000000E) /*!< PVD level selection */ |
| mbed_official | 623:db79ecd649d0 | 5068 | #define PWR_CR2_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */ |
| mbed_official | 623:db79ecd649d0 | 5069 | #define PWR_CR2_PLS_LEV1 ((uint32_t)0x00000002) /*!< PVD level 1 */ |
| mbed_official | 623:db79ecd649d0 | 5070 | #define PWR_CR2_PLS_LEV2 ((uint32_t)0x00000004) /*!< PVD level 2 */ |
| mbed_official | 623:db79ecd649d0 | 5071 | #define PWR_CR2_PLS_LEV3 ((uint32_t)0x00000006) /*!< PVD level 3 */ |
| mbed_official | 623:db79ecd649d0 | 5072 | #define PWR_CR2_PLS_LEV4 ((uint32_t)0x00000008) /*!< PVD level 4 */ |
| mbed_official | 623:db79ecd649d0 | 5073 | #define PWR_CR2_PLS_LEV5 ((uint32_t)0x0000000A) /*!< PVD level 5 */ |
| mbed_official | 623:db79ecd649d0 | 5074 | #define PWR_CR2_PLS_LEV6 ((uint32_t)0x0000000C) /*!< PVD level 6 */ |
| mbed_official | 623:db79ecd649d0 | 5075 | #define PWR_CR2_PLS_LEV7 ((uint32_t)0x0000000E) /*!< PVD level 7 */ |
| mbed_official | 623:db79ecd649d0 | 5076 | #define PWR_CR2_PVDE ((uint32_t)0x00000001) /*!< Power Voltage Detector Enable */ |
| mbed_official | 623:db79ecd649d0 | 5077 | |
| mbed_official | 623:db79ecd649d0 | 5078 | /******************** Bit definition for PWR_CR3 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5079 | #define PWR_CR3_EIWF ((uint32_t)0x00008000) /*!< Enable Internal Wake-up line */ |
| mbed_official | 623:db79ecd649d0 | 5080 | #define PWR_CR3_APC ((uint32_t)0x00000400) /*!< Apply pull-up and pull-down configuration */ |
| mbed_official | 623:db79ecd649d0 | 5081 | #define PWR_CR3_RRS ((uint32_t)0x00000100) /*!< SRAM2 Retention in Stand-by mode */ |
| mbed_official | 623:db79ecd649d0 | 5082 | #define PWR_CR3_EWUP5 ((uint32_t)0x00000010) /*!< Enable Wake-Up Pin 5 */ |
| mbed_official | 623:db79ecd649d0 | 5083 | #define PWR_CR3_EWUP4 ((uint32_t)0x00000008) /*!< Enable Wake-Up Pin 4 */ |
| mbed_official | 623:db79ecd649d0 | 5084 | #define PWR_CR3_EWUP3 ((uint32_t)0x00000004) /*!< Enable Wake-Up Pin 3 */ |
| mbed_official | 623:db79ecd649d0 | 5085 | #define PWR_CR3_EWUP2 ((uint32_t)0x00000002) /*!< Enable Wake-Up Pin 2 */ |
| mbed_official | 623:db79ecd649d0 | 5086 | #define PWR_CR3_EWUP1 ((uint32_t)0x00000001) /*!< Enable Wake-Up Pin 1 */ |
| mbed_official | 623:db79ecd649d0 | 5087 | #define PWR_CR3_EWUP ((uint32_t)0x0000001F) /*!< Enable Wake-Up Pins */ |
| mbed_official | 623:db79ecd649d0 | 5088 | |
| mbed_official | 623:db79ecd649d0 | 5089 | /******************** Bit definition for PWR_CR4 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5090 | #define PWR_CR4_VBRS ((uint32_t)0x00000200) /*!< VBAT Battery charging Resistor Selection */ |
| mbed_official | 623:db79ecd649d0 | 5091 | #define PWR_CR4_VBE ((uint32_t)0x00000100) /*!< VBAT Battery charging Enable */ |
| mbed_official | 623:db79ecd649d0 | 5092 | #define PWR_CR4_WP5 ((uint32_t)0x00000010) /*!< Wake-Up Pin 5 polarity */ |
| mbed_official | 623:db79ecd649d0 | 5093 | #define PWR_CR4_WP4 ((uint32_t)0x00000008) /*!< Wake-Up Pin 4 polarity */ |
| mbed_official | 623:db79ecd649d0 | 5094 | #define PWR_CR4_WP3 ((uint32_t)0x00000004) /*!< Wake-Up Pin 3 polarity */ |
| mbed_official | 623:db79ecd649d0 | 5095 | #define PWR_CR4_WP2 ((uint32_t)0x00000002) /*!< Wake-Up Pin 2 polarity */ |
| mbed_official | 623:db79ecd649d0 | 5096 | #define PWR_CR4_WP1 ((uint32_t)0x00000001) /*!< Wake-Up Pin 1 polarity */ |
| mbed_official | 623:db79ecd649d0 | 5097 | |
| mbed_official | 623:db79ecd649d0 | 5098 | /******************** Bit definition for PWR_SR1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5099 | #define PWR_SR1_WUFI ((uint32_t)0x00008000) /*!< Wake-Up Flag Internal */ |
| mbed_official | 623:db79ecd649d0 | 5100 | #define PWR_SR1_SBF ((uint32_t)0x00000100) /*!< Stand-By Flag */ |
| mbed_official | 623:db79ecd649d0 | 5101 | #define PWR_SR1_WUF ((uint32_t)0x0000001F) /*!< Wake-up Flags */ |
| mbed_official | 623:db79ecd649d0 | 5102 | #define PWR_SR1_WUF5 ((uint32_t)0x00000010) /*!< Wake-up Flag 5 */ |
| mbed_official | 623:db79ecd649d0 | 5103 | #define PWR_SR1_WUF4 ((uint32_t)0x00000008) /*!< Wake-up Flag 4 */ |
| mbed_official | 623:db79ecd649d0 | 5104 | #define PWR_SR1_WUF3 ((uint32_t)0x00000004) /*!< Wake-up Flag 3 */ |
| mbed_official | 623:db79ecd649d0 | 5105 | #define PWR_SR1_WUF2 ((uint32_t)0x00000002) /*!< Wake-up Flag 2 */ |
| mbed_official | 623:db79ecd649d0 | 5106 | #define PWR_SR1_WUF1 ((uint32_t)0x00000001) /*!< Wake-up Flag 1 */ |
| mbed_official | 623:db79ecd649d0 | 5107 | |
| mbed_official | 623:db79ecd649d0 | 5108 | /******************** Bit definition for PWR_SR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5109 | #define PWR_SR2_PVMO4 ((uint32_t)0x00008000) /*!< Peripheral Voltage Monitoring Output 4 */ |
| mbed_official | 623:db79ecd649d0 | 5110 | #define PWR_SR2_PVMO3 ((uint32_t)0x00004000) /*!< Peripheral Voltage Monitoring Output 3 */ |
| mbed_official | 623:db79ecd649d0 | 5111 | #define PWR_SR2_PVMO2 ((uint32_t)0x00002000) /*!< Peripheral Voltage Monitoring Output 2 */ |
| mbed_official | 623:db79ecd649d0 | 5112 | #define PWR_SR2_PVMO1 ((uint32_t)0x00001000) /*!< Peripheral Voltage Monitoring Output 1 */ |
| mbed_official | 623:db79ecd649d0 | 5113 | #define PWR_SR2_PVDO ((uint32_t)0x00000800) /*!< Power Voltage Detector Output */ |
| mbed_official | 623:db79ecd649d0 | 5114 | #define PWR_SR2_VOSF ((uint32_t)0x00000400) /*!< Voltage Scaling Flag */ |
| mbed_official | 623:db79ecd649d0 | 5115 | #define PWR_SR2_REGLPF ((uint32_t)0x00000200) /*!< Low-power Regulator Flag */ |
| mbed_official | 623:db79ecd649d0 | 5116 | #define PWR_SR2_REGLPS ((uint32_t)0x00000100) /*!< Low-power Regulator Started */ |
| mbed_official | 623:db79ecd649d0 | 5117 | |
| mbed_official | 623:db79ecd649d0 | 5118 | /******************** Bit definition for PWR_SCR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5119 | #define PWR_SCR_CSBF ((uint32_t)0x00000100) /*!< Clear Stand-By Flag */ |
| mbed_official | 623:db79ecd649d0 | 5120 | #define PWR_SCR_CWUF ((uint32_t)0x0000001F) /*!< Clear Wake-up Flags */ |
| mbed_official | 623:db79ecd649d0 | 5121 | #define PWR_SCR_CWUF5 ((uint32_t)0x00000010) /*!< Clear Wake-up Flag 5 */ |
| mbed_official | 623:db79ecd649d0 | 5122 | #define PWR_SCR_CWUF4 ((uint32_t)0x00000008) /*!< Clear Wake-up Flag 4 */ |
| mbed_official | 623:db79ecd649d0 | 5123 | #define PWR_SCR_CWUF3 ((uint32_t)0x00000004) /*!< Clear Wake-up Flag 3 */ |
| mbed_official | 623:db79ecd649d0 | 5124 | #define PWR_SCR_CWUF2 ((uint32_t)0x00000002) /*!< Clear Wake-up Flag 2 */ |
| mbed_official | 623:db79ecd649d0 | 5125 | #define PWR_SCR_CWUF1 ((uint32_t)0x00000001) /*!< Clear Wake-up Flag 1 */ |
| mbed_official | 623:db79ecd649d0 | 5126 | |
| mbed_official | 623:db79ecd649d0 | 5127 | /******************** Bit definition for PWR_PUCRA register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5128 | #define PWR_PUCRA_PA15 ((uint32_t)0x00008000) /*!< Port PA15 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5129 | #define PWR_PUCRA_PA13 ((uint32_t)0x00002000) /*!< Port PA13 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5130 | #define PWR_PUCRA_PA12 ((uint32_t)0x00001000) /*!< Port PA12 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5131 | #define PWR_PUCRA_PA11 ((uint32_t)0x00000800) /*!< Port PA11 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5132 | #define PWR_PUCRA_PA10 ((uint32_t)0x00000400) /*!< Port PA10 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5133 | #define PWR_PUCRA_PA9 ((uint32_t)0x00000200) /*!< Port PA9 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5134 | #define PWR_PUCRA_PA8 ((uint32_t)0x00000100) /*!< Port PA8 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5135 | #define PWR_PUCRA_PA7 ((uint32_t)0x00000080) /*!< Port PA7 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5136 | #define PWR_PUCRA_PA6 ((uint32_t)0x00000040) /*!< Port PA6 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5137 | #define PWR_PUCRA_PA5 ((uint32_t)0x00000020) /*!< Port PA5 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5138 | #define PWR_PUCRA_PA4 ((uint32_t)0x00000010) /*!< Port PA4 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5139 | #define PWR_PUCRA_PA3 ((uint32_t)0x00000008) /*!< Port PA3 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5140 | #define PWR_PUCRA_PA2 ((uint32_t)0x00000004) /*!< Port PA2 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5141 | #define PWR_PUCRA_PA1 ((uint32_t)0x00000002) /*!< Port PA1 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5142 | #define PWR_PUCRA_PA0 ((uint32_t)0x00000001) /*!< Port PA0 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5143 | |
| mbed_official | 623:db79ecd649d0 | 5144 | /******************** Bit definition for PWR_PDCRA register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5145 | #define PWR_PDCRA_PA14 ((uint32_t)0x00004000) /*!< Port PA14 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5146 | #define PWR_PDCRA_PA12 ((uint32_t)0x00001000) /*!< Port PA12 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5147 | #define PWR_PDCRA_PA11 ((uint32_t)0x00000800) /*!< Port PA11 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5148 | #define PWR_PDCRA_PA10 ((uint32_t)0x00000400) /*!< Port PA10 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5149 | #define PWR_PDCRA_PA9 ((uint32_t)0x00000200) /*!< Port PA9 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5150 | #define PWR_PDCRA_PA8 ((uint32_t)0x00000100) /*!< Port PA8 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5151 | #define PWR_PDCRA_PA7 ((uint32_t)0x00000080) /*!< Port PA7 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5152 | #define PWR_PDCRA_PA6 ((uint32_t)0x00000040) /*!< Port PA6 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5153 | #define PWR_PDCRA_PA5 ((uint32_t)0x00000020) /*!< Port PA5 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5154 | #define PWR_PDCRA_PA4 ((uint32_t)0x00000010) /*!< Port PA4 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5155 | #define PWR_PDCRA_PA3 ((uint32_t)0x00000008) /*!< Port PA3 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5156 | #define PWR_PDCRA_PA2 ((uint32_t)0x00000004) /*!< Port PA2 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5157 | #define PWR_PDCRA_PA1 ((uint32_t)0x00000002) /*!< Port PA1 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5158 | #define PWR_PDCRA_PA0 ((uint32_t)0x00000001) /*!< Port PA0 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5159 | |
| mbed_official | 623:db79ecd649d0 | 5160 | /******************** Bit definition for PWR_PUCRB register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5161 | #define PWR_PUCRB_PB15 ((uint32_t)0x00008000) /*!< Port PB15 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5162 | #define PWR_PUCRB_PB14 ((uint32_t)0x00004000) /*!< Port PB14 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5163 | #define PWR_PUCRB_PB13 ((uint32_t)0x00002000) /*!< Port PB13 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5164 | #define PWR_PUCRB_PB12 ((uint32_t)0x00001000) /*!< Port PB12 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5165 | #define PWR_PUCRB_PB11 ((uint32_t)0x00000800) /*!< Port PB11 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5166 | #define PWR_PUCRB_PB10 ((uint32_t)0x00000400) /*!< Port PB10 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5167 | #define PWR_PUCRB_PB9 ((uint32_t)0x00000200) /*!< Port PB9 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5168 | #define PWR_PUCRB_PB8 ((uint32_t)0x00000100) /*!< Port PB8 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5169 | #define PWR_PUCRB_PB7 ((uint32_t)0x00000080) /*!< Port PB7 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5170 | #define PWR_PUCRB_PB6 ((uint32_t)0x00000040) /*!< Port PB6 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5171 | #define PWR_PUCRB_PB5 ((uint32_t)0x00000020) /*!< Port PB5 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5172 | #define PWR_PUCRB_PB4 ((uint32_t)0x00000010) /*!< Port PB4 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5173 | #define PWR_PUCRB_PB3 ((uint32_t)0x00000008) /*!< Port PB3 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5174 | #define PWR_PUCRB_PB2 ((uint32_t)0x00000004) /*!< Port PB2 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5175 | #define PWR_PUCRB_PB1 ((uint32_t)0x00000002) /*!< Port PB1 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5176 | #define PWR_PUCRB_PB0 ((uint32_t)0x00000001) /*!< Port PB0 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5177 | |
| mbed_official | 623:db79ecd649d0 | 5178 | /******************** Bit definition for PWR_PDCRB register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5179 | #define PWR_PDCRB_PB15 ((uint32_t)0x00008000) /*!< Port PB15 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5180 | #define PWR_PDCRB_PB14 ((uint32_t)0x00004000) /*!< Port PB14 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5181 | #define PWR_PDCRB_PB13 ((uint32_t)0x00002000) /*!< Port PB13 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5182 | #define PWR_PDCRB_PB12 ((uint32_t)0x00001000) /*!< Port PB12 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5183 | #define PWR_PDCRB_PB11 ((uint32_t)0x00000800) /*!< Port PB11 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5184 | #define PWR_PDCRB_PB10 ((uint32_t)0x00000400) /*!< Port PB10 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5185 | #define PWR_PDCRB_PB9 ((uint32_t)0x00000200) /*!< Port PB9 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5186 | #define PWR_PDCRB_PB8 ((uint32_t)0x00000100) /*!< Port PB8 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5187 | #define PWR_PDCRB_PB7 ((uint32_t)0x00000080) /*!< Port PB7 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5188 | #define PWR_PDCRB_PB6 ((uint32_t)0x00000040) /*!< Port PB6 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5189 | #define PWR_PDCRB_PB5 ((uint32_t)0x00000020) /*!< Port PB5 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5190 | #define PWR_PDCRB_PB3 ((uint32_t)0x00000008) /*!< Port PB3 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5191 | #define PWR_PDCRB_PB2 ((uint32_t)0x00000004) /*!< Port PB2 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5192 | #define PWR_PDCRB_PB1 ((uint32_t)0x00000002) /*!< Port PB1 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5193 | #define PWR_PDCRB_PB0 ((uint32_t)0x00000001) /*!< Port PB0 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5194 | |
| mbed_official | 623:db79ecd649d0 | 5195 | /******************** Bit definition for PWR_PUCRC register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5196 | #define PWR_PUCRC_PC15 ((uint32_t)0x00008000) /*!< Port PC15 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5197 | #define PWR_PUCRC_PC14 ((uint32_t)0x00004000) /*!< Port PC14 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5198 | #define PWR_PUCRC_PC13 ((uint32_t)0x00002000) /*!< Port PC13 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5199 | #define PWR_PUCRC_PC12 ((uint32_t)0x00001000) /*!< Port PC12 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5200 | #define PWR_PUCRC_PC11 ((uint32_t)0x00000800) /*!< Port PC11 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5201 | #define PWR_PUCRC_PC10 ((uint32_t)0x00000400) /*!< Port PC10 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5202 | #define PWR_PUCRC_PC9 ((uint32_t)0x00000200) /*!< Port PC9 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5203 | #define PWR_PUCRC_PC8 ((uint32_t)0x00000100) /*!< Port PC8 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5204 | #define PWR_PUCRC_PC7 ((uint32_t)0x00000080) /*!< Port PC7 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5205 | #define PWR_PUCRC_PC6 ((uint32_t)0x00000040) /*!< Port PC6 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5206 | #define PWR_PUCRC_PC5 ((uint32_t)0x00000020) /*!< Port PC5 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5207 | #define PWR_PUCRC_PC4 ((uint32_t)0x00000010) /*!< Port PC4 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5208 | #define PWR_PUCRC_PC3 ((uint32_t)0x00000008) /*!< Port PC3 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5209 | #define PWR_PUCRC_PC2 ((uint32_t)0x00000004) /*!< Port PC2 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5210 | #define PWR_PUCRC_PC1 ((uint32_t)0x00000002) /*!< Port PC1 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5211 | #define PWR_PUCRC_PC0 ((uint32_t)0x00000001) /*!< Port PC0 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5212 | |
| mbed_official | 623:db79ecd649d0 | 5213 | /******************** Bit definition for PWR_PDCRC register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5214 | #define PWR_PDCRC_PC15 ((uint32_t)0x00008000) /*!< Port PC15 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5215 | #define PWR_PDCRC_PC14 ((uint32_t)0x00004000) /*!< Port PC14 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5216 | #define PWR_PDCRC_PC13 ((uint32_t)0x00002000) /*!< Port PC13 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5217 | #define PWR_PDCRC_PC12 ((uint32_t)0x00001000) /*!< Port PC12 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5218 | #define PWR_PDCRC_PC11 ((uint32_t)0x00000800) /*!< Port PC11 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5219 | #define PWR_PDCRC_PC10 ((uint32_t)0x00000400) /*!< Port PC10 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5220 | #define PWR_PDCRC_PC9 ((uint32_t)0x00000200) /*!< Port PC9 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5221 | #define PWR_PDCRC_PC8 ((uint32_t)0x00000100) /*!< Port PC8 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5222 | #define PWR_PDCRC_PC7 ((uint32_t)0x00000080) /*!< Port PC7 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5223 | #define PWR_PDCRC_PC6 ((uint32_t)0x00000040) /*!< Port PC6 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5224 | #define PWR_PDCRC_PC5 ((uint32_t)0x00000020) /*!< Port PC5 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5225 | #define PWR_PDCRC_PC4 ((uint32_t)0x00000010) /*!< Port PC4 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5226 | #define PWR_PDCRC_PC3 ((uint32_t)0x00000008) /*!< Port PC3 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5227 | #define PWR_PDCRC_PC2 ((uint32_t)0x00000004) /*!< Port PC2 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5228 | #define PWR_PDCRC_PC1 ((uint32_t)0x00000002) /*!< Port PC1 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5229 | #define PWR_PDCRC_PC0 ((uint32_t)0x00000001) /*!< Port PC0 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5230 | |
| mbed_official | 623:db79ecd649d0 | 5231 | /******************** Bit definition for PWR_PUCRD register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5232 | #define PWR_PUCRD_PD15 ((uint32_t)0x00008000) /*!< Port PD15 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5233 | #define PWR_PUCRD_PD14 ((uint32_t)0x00004000) /*!< Port PD14 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5234 | #define PWR_PUCRD_PD13 ((uint32_t)0x00002000) /*!< Port PD13 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5235 | #define PWR_PUCRD_PD12 ((uint32_t)0x00001000) /*!< Port PD12 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5236 | #define PWR_PUCRD_PD11 ((uint32_t)0x00000800) /*!< Port PD11 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5237 | #define PWR_PUCRD_PD10 ((uint32_t)0x00000400) /*!< Port PD10 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5238 | #define PWR_PUCRD_PD9 ((uint32_t)0x00000200) /*!< Port PD9 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5239 | #define PWR_PUCRD_PD8 ((uint32_t)0x00000100) /*!< Port PD8 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5240 | #define PWR_PUCRD_PD7 ((uint32_t)0x00000080) /*!< Port PD7 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5241 | #define PWR_PUCRD_PD6 ((uint32_t)0x00000040) /*!< Port PD6 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5242 | #define PWR_PUCRD_PD5 ((uint32_t)0x00000020) /*!< Port PD5 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5243 | #define PWR_PUCRD_PD4 ((uint32_t)0x00000010) /*!< Port PD4 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5244 | #define PWR_PUCRD_PD3 ((uint32_t)0x00000008) /*!< Port PD3 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5245 | #define PWR_PUCRD_PD2 ((uint32_t)0x00000004) /*!< Port PD2 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5246 | #define PWR_PUCRD_PD1 ((uint32_t)0x00000002) /*!< Port PD1 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5247 | #define PWR_PUCRD_PD0 ((uint32_t)0x00000001) /*!< Port PD0 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5248 | |
| mbed_official | 623:db79ecd649d0 | 5249 | /******************** Bit definition for PWR_PDCRD register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5250 | #define PWR_PDCRD_PD15 ((uint32_t)0x00008000) /*!< Port PD15 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5251 | #define PWR_PDCRD_PD14 ((uint32_t)0x00004000) /*!< Port PD14 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5252 | #define PWR_PDCRD_PD13 ((uint32_t)0x00002000) /*!< Port PD13 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5253 | #define PWR_PDCRD_PD12 ((uint32_t)0x00001000) /*!< Port PD12 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5254 | #define PWR_PDCRD_PD11 ((uint32_t)0x00000800) /*!< Port PD11 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5255 | #define PWR_PDCRD_PD10 ((uint32_t)0x00000400) /*!< Port PD10 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5256 | #define PWR_PDCRD_PD9 ((uint32_t)0x00000200) /*!< Port PD9 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5257 | #define PWR_PDCRD_PD8 ((uint32_t)0x00000100) /*!< Port PD8 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5258 | #define PWR_PDCRD_PD7 ((uint32_t)0x00000080) /*!< Port PD7 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5259 | #define PWR_PDCRD_PD6 ((uint32_t)0x00000040) /*!< Port PD6 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5260 | #define PWR_PDCRD_PD5 ((uint32_t)0x00000020) /*!< Port PD5 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5261 | #define PWR_PDCRD_PD4 ((uint32_t)0x00000010) /*!< Port PD4 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5262 | #define PWR_PDCRD_PD3 ((uint32_t)0x00000008) /*!< Port PD3 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5263 | #define PWR_PDCRD_PD2 ((uint32_t)0x00000004) /*!< Port PD2 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5264 | #define PWR_PDCRD_PD1 ((uint32_t)0x00000002) /*!< Port PD1 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5265 | #define PWR_PDCRD_PD0 ((uint32_t)0x00000001) /*!< Port PD0 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5266 | |
| mbed_official | 623:db79ecd649d0 | 5267 | /******************** Bit definition for PWR_PUCRE register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5268 | #define PWR_PUCRE_PE15 ((uint32_t)0x00008000) /*!< Port PE15 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5269 | #define PWR_PUCRE_PE14 ((uint32_t)0x00004000) /*!< Port PE14 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5270 | #define PWR_PUCRE_PE13 ((uint32_t)0x00002000) /*!< Port PE13 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5271 | #define PWR_PUCRE_PE12 ((uint32_t)0x00001000) /*!< Port PE12 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5272 | #define PWR_PUCRE_PE11 ((uint32_t)0x00000800) /*!< Port PE11 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5273 | #define PWR_PUCRE_PE10 ((uint32_t)0x00000400) /*!< Port PE10 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5274 | #define PWR_PUCRE_PE9 ((uint32_t)0x00000200) /*!< Port PE9 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5275 | #define PWR_PUCRE_PE8 ((uint32_t)0x00000100) /*!< Port PE8 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5276 | #define PWR_PUCRE_PE7 ((uint32_t)0x00000080) /*!< Port PE7 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5277 | #define PWR_PUCRE_PE6 ((uint32_t)0x00000040) /*!< Port PE6 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5278 | #define PWR_PUCRE_PE5 ((uint32_t)0x00000020) /*!< Port PE5 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5279 | #define PWR_PUCRE_PE4 ((uint32_t)0x00000010) /*!< Port PE4 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5280 | #define PWR_PUCRE_PE3 ((uint32_t)0x00000008) /*!< Port PE3 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5281 | #define PWR_PUCRE_PE2 ((uint32_t)0x00000004) /*!< Port PE2 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5282 | #define PWR_PUCRE_PE1 ((uint32_t)0x00000002) /*!< Port PE1 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5283 | #define PWR_PUCRE_PE0 ((uint32_t)0x00000001) /*!< Port PE0 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5284 | |
| mbed_official | 623:db79ecd649d0 | 5285 | /******************** Bit definition for PWR_PDCRE register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5286 | #define PWR_PDCRE_PE15 ((uint32_t)0x00008000) /*!< Port PE15 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5287 | #define PWR_PDCRE_PE14 ((uint32_t)0x00004000) /*!< Port PE14 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5288 | #define PWR_PDCRE_PE13 ((uint32_t)0x00002000) /*!< Port PE13 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5289 | #define PWR_PDCRE_PE12 ((uint32_t)0x00001000) /*!< Port PE12 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5290 | #define PWR_PDCRE_PE11 ((uint32_t)0x00000800) /*!< Port PE11 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5291 | #define PWR_PDCRE_PE10 ((uint32_t)0x00000400) /*!< Port PE10 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5292 | #define PWR_PDCRE_PE9 ((uint32_t)0x00000200) /*!< Port PE9 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5293 | #define PWR_PDCRE_PE8 ((uint32_t)0x00000100) /*!< Port PE8 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5294 | #define PWR_PDCRE_PE7 ((uint32_t)0x00000080) /*!< Port PE7 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5295 | #define PWR_PDCRE_PE6 ((uint32_t)0x00000040) /*!< Port PE6 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5296 | #define PWR_PDCRE_PE5 ((uint32_t)0x00000020) /*!< Port PE5 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5297 | #define PWR_PDCRE_PE4 ((uint32_t)0x00000010) /*!< Port PE4 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5298 | #define PWR_PDCRE_PE3 ((uint32_t)0x00000008) /*!< Port PE3 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5299 | #define PWR_PDCRE_PE2 ((uint32_t)0x00000004) /*!< Port PE2 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5300 | #define PWR_PDCRE_PE1 ((uint32_t)0x00000002) /*!< Port PE1 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5301 | #define PWR_PDCRE_PE0 ((uint32_t)0x00000001) /*!< Port PE0 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5302 | |
| mbed_official | 623:db79ecd649d0 | 5303 | /******************** Bit definition for PWR_PUCRF register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5304 | #define PWR_PUCRF_PF15 ((uint32_t)0x00008000) /*!< Port PF15 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5305 | #define PWR_PUCRF_PF14 ((uint32_t)0x00004000) /*!< Port PF14 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5306 | #define PWR_PUCRF_PF13 ((uint32_t)0x00002000) /*!< Port PF13 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5307 | #define PWR_PUCRF_PF12 ((uint32_t)0x00001000) /*!< Port PF12 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5308 | #define PWR_PUCRF_PF11 ((uint32_t)0x00000800) /*!< Port PF11 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5309 | #define PWR_PUCRF_PF10 ((uint32_t)0x00000400) /*!< Port PF10 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5310 | #define PWR_PUCRF_PF9 ((uint32_t)0x00000200) /*!< Port PF9 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5311 | #define PWR_PUCRF_PF8 ((uint32_t)0x00000100) /*!< Port PF8 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5312 | #define PWR_PUCRF_PF7 ((uint32_t)0x00000080) /*!< Port PF7 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5313 | #define PWR_PUCRF_PF6 ((uint32_t)0x00000040) /*!< Port PF6 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5314 | #define PWR_PUCRF_PF5 ((uint32_t)0x00000020) /*!< Port PF5 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5315 | #define PWR_PUCRF_PF4 ((uint32_t)0x00000010) /*!< Port PF4 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5316 | #define PWR_PUCRF_PF3 ((uint32_t)0x00000008) /*!< Port PF3 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5317 | #define PWR_PUCRF_PF2 ((uint32_t)0x00000004) /*!< Port PF2 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5318 | #define PWR_PUCRF_PF1 ((uint32_t)0x00000002) /*!< Port PF1 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5319 | #define PWR_PUCRF_PF0 ((uint32_t)0x00000001) /*!< Port PF0 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5320 | |
| mbed_official | 623:db79ecd649d0 | 5321 | /******************** Bit definition for PWR_PDCRF register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5322 | #define PWR_PDCRF_PF15 ((uint32_t)0x00008000) /*!< Port PF15 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5323 | #define PWR_PDCRF_PF14 ((uint32_t)0x00004000) /*!< Port PF14 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5324 | #define PWR_PDCRF_PF13 ((uint32_t)0x00002000) /*!< Port PF13 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5325 | #define PWR_PDCRF_PF12 ((uint32_t)0x00001000) /*!< Port PF12 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5326 | #define PWR_PDCRF_PF11 ((uint32_t)0x00000800) /*!< Port PF11 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5327 | #define PWR_PDCRF_PF10 ((uint32_t)0x00000400) /*!< Port PF10 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5328 | #define PWR_PDCRF_PF9 ((uint32_t)0x00000200) /*!< Port PF9 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5329 | #define PWR_PDCRF_PF8 ((uint32_t)0x00000100) /*!< Port PF8 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5330 | #define PWR_PDCRF_PF7 ((uint32_t)0x00000080) /*!< Port PF7 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5331 | #define PWR_PDCRF_PF6 ((uint32_t)0x00000040) /*!< Port PF6 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5332 | #define PWR_PDCRF_PF5 ((uint32_t)0x00000020) /*!< Port PF5 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5333 | #define PWR_PDCRF_PF4 ((uint32_t)0x00000010) /*!< Port PF4 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5334 | #define PWR_PDCRF_PF3 ((uint32_t)0x00000008) /*!< Port PF3 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5335 | #define PWR_PDCRF_PF2 ((uint32_t)0x00000004) /*!< Port PF2 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5336 | #define PWR_PDCRF_PF1 ((uint32_t)0x00000002) /*!< Port PF1 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5337 | #define PWR_PDCRF_PF0 ((uint32_t)0x00000001) /*!< Port PF0 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5338 | |
| mbed_official | 623:db79ecd649d0 | 5339 | /******************** Bit definition for PWR_PUCRG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5340 | #define PWR_PUCRG_PG15 ((uint32_t)0x00008000) /*!< Port PG15 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5341 | #define PWR_PUCRG_PG14 ((uint32_t)0x00004000) /*!< Port PG14 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5342 | #define PWR_PUCRG_PG13 ((uint32_t)0x00002000) /*!< Port PG13 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5343 | #define PWR_PUCRG_PG12 ((uint32_t)0x00001000) /*!< Port PG12 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5344 | #define PWR_PUCRG_PG11 ((uint32_t)0x00000800) /*!< Port PG11 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5345 | #define PWR_PUCRG_PG10 ((uint32_t)0x00000400) /*!< Port PG10 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5346 | #define PWR_PUCRG_PG9 ((uint32_t)0x00000200) /*!< Port PG9 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5347 | #define PWR_PUCRG_PG8 ((uint32_t)0x00000100) /*!< Port PG8 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5348 | #define PWR_PUCRG_PG7 ((uint32_t)0x00000080) /*!< Port PG7 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5349 | #define PWR_PUCRG_PG6 ((uint32_t)0x00000040) /*!< Port PG6 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5350 | #define PWR_PUCRG_PG5 ((uint32_t)0x00000020) /*!< Port PG5 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5351 | #define PWR_PUCRG_PG4 ((uint32_t)0x00000010) /*!< Port PG4 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5352 | #define PWR_PUCRG_PG3 ((uint32_t)0x00000008) /*!< Port PG3 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5353 | #define PWR_PUCRG_PG2 ((uint32_t)0x00000004) /*!< Port PG2 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5354 | #define PWR_PUCRG_PG1 ((uint32_t)0x00000002) /*!< Port PG1 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5355 | #define PWR_PUCRG_PG0 ((uint32_t)0x00000001) /*!< Port PG0 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5356 | |
| mbed_official | 623:db79ecd649d0 | 5357 | /******************** Bit definition for PWR_PDCRG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5358 | #define PWR_PDCRG_PG15 ((uint32_t)0x00008000) /*!< Port PG15 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5359 | #define PWR_PDCRG_PG14 ((uint32_t)0x00004000) /*!< Port PG14 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5360 | #define PWR_PDCRG_PG13 ((uint32_t)0x00002000) /*!< Port PG13 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5361 | #define PWR_PDCRG_PG12 ((uint32_t)0x00001000) /*!< Port PG12 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5362 | #define PWR_PDCRG_PG11 ((uint32_t)0x00000800) /*!< Port PG11 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5363 | #define PWR_PDCRG_PG10 ((uint32_t)0x00000400) /*!< Port PG10 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5364 | #define PWR_PDCRG_PG9 ((uint32_t)0x00000200) /*!< Port PG9 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5365 | #define PWR_PDCRG_PG8 ((uint32_t)0x00000100) /*!< Port PG8 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5366 | #define PWR_PDCRG_PG7 ((uint32_t)0x00000080) /*!< Port PG7 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5367 | #define PWR_PDCRG_PG6 ((uint32_t)0x00000040) /*!< Port PG6 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5368 | #define PWR_PDCRG_PG5 ((uint32_t)0x00000020) /*!< Port PG5 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5369 | #define PWR_PDCRG_PG4 ((uint32_t)0x00000010) /*!< Port PG4 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5370 | #define PWR_PDCRG_PG3 ((uint32_t)0x00000008) /*!< Port PG3 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5371 | #define PWR_PDCRG_PG2 ((uint32_t)0x00000004) /*!< Port PG2 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5372 | #define PWR_PDCRG_PG1 ((uint32_t)0x00000002) /*!< Port PG1 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5373 | #define PWR_PDCRG_PG0 ((uint32_t)0x00000001) /*!< Port PG0 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5374 | |
| mbed_official | 623:db79ecd649d0 | 5375 | /******************** Bit definition for PWR_PUCRH register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5376 | #define PWR_PUCRH_PH1 ((uint32_t)0x00000002) /*!< Port PH1 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5377 | #define PWR_PUCRH_PH0 ((uint32_t)0x00000001) /*!< Port PH0 Pull-Up set */ |
| mbed_official | 623:db79ecd649d0 | 5378 | |
| mbed_official | 623:db79ecd649d0 | 5379 | /******************** Bit definition for PWR_PDCRH register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5380 | #define PWR_PDCRH_PH1 ((uint32_t)0x00000002) /*!< Port PH1 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5381 | #define PWR_PDCRH_PH0 ((uint32_t)0x00000001) /*!< Port PH0 Pull-Down set */ |
| mbed_official | 623:db79ecd649d0 | 5382 | |
| mbed_official | 623:db79ecd649d0 | 5383 | |
| mbed_official | 623:db79ecd649d0 | 5384 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 5385 | /* */ |
| mbed_official | 623:db79ecd649d0 | 5386 | /* Reset and Clock Control */ |
| mbed_official | 623:db79ecd649d0 | 5387 | /* */ |
| mbed_official | 623:db79ecd649d0 | 5388 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 5389 | /******************** Bit definition for RCC_CR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 5390 | #define RCC_CR_MSION ((uint32_t)0x00000001) /*!< Internal Multi Speed clock enable */ |
| mbed_official | 623:db79ecd649d0 | 5391 | #define RCC_CR_MSIRDY ((uint32_t)0x00000002) /*!< Internal Multi Speed clock ready flag */ |
| mbed_official | 623:db79ecd649d0 | 5392 | #define RCC_CR_MSIPLLEN ((uint32_t)0x00000004) /*!< Internal Multi Speed PLL enable */ |
| mbed_official | 623:db79ecd649d0 | 5393 | #define RCC_CR_MSIRGSEL ((uint32_t)0x00000008) /*!< Internal Multi Speed range selection */ |
| mbed_official | 623:db79ecd649d0 | 5394 | |
| mbed_official | 623:db79ecd649d0 | 5395 | /*!< MSIRANGE configuration : 12 frequency ranges available */ |
| mbed_official | 623:db79ecd649d0 | 5396 | #define RCC_CR_MSIRANGE ((uint32_t)0x000000F0) /*!< Internal Multi Speed clock Range */ |
| mbed_official | 623:db79ecd649d0 | 5397 | #define RCC_CR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 100 KHz */ |
| mbed_official | 623:db79ecd649d0 | 5398 | #define RCC_CR_MSIRANGE_1 ((uint32_t)0x00000010) /*!< Internal Multi Speed clock Range 200 KHz */ |
| mbed_official | 623:db79ecd649d0 | 5399 | #define RCC_CR_MSIRANGE_2 ((uint32_t)0x00000020) /*!< Internal Multi Speed clock Range 400 KHz */ |
| mbed_official | 623:db79ecd649d0 | 5400 | #define RCC_CR_MSIRANGE_3 ((uint32_t)0x00000030) /*!< Internal Multi Speed clock Range 800 KHz */ |
| mbed_official | 623:db79ecd649d0 | 5401 | #define RCC_CR_MSIRANGE_4 ((uint32_t)0x00000040) /*!< Internal Multi Speed clock Range 1 MHz */ |
| mbed_official | 623:db79ecd649d0 | 5402 | #define RCC_CR_MSIRANGE_5 ((uint32_t)0x00000050) /*!< Internal Multi Speed clock Range 2 MHz */ |
| mbed_official | 623:db79ecd649d0 | 5403 | #define RCC_CR_MSIRANGE_6 ((uint32_t)0x00000060) /*!< Internal Multi Speed clock Range 4 MHz */ |
| mbed_official | 623:db79ecd649d0 | 5404 | #define RCC_CR_MSIRANGE_7 ((uint32_t)0x00000070) /*!< Internal Multi Speed clock Range 8 KHz */ |
| mbed_official | 623:db79ecd649d0 | 5405 | #define RCC_CR_MSIRANGE_8 ((uint32_t)0x00000080) /*!< Internal Multi Speed clock Range 16 MHz */ |
| mbed_official | 623:db79ecd649d0 | 5406 | #define RCC_CR_MSIRANGE_9 ((uint32_t)0x00000090) /*!< Internal Multi Speed clock Range 24 MHz */ |
| mbed_official | 623:db79ecd649d0 | 5407 | #define RCC_CR_MSIRANGE_10 ((uint32_t)0x000000A0) /*!< Internal Multi Speed clock Range 32 MHz */ |
| mbed_official | 623:db79ecd649d0 | 5408 | #define RCC_CR_MSIRANGE_11 ((uint32_t)0x000000B0) /*!< Internal Multi Speed clock Range 48 MHz */ |
| mbed_official | 623:db79ecd649d0 | 5409 | |
| mbed_official | 623:db79ecd649d0 | 5410 | #define RCC_CR_HSION ((uint32_t)0x00000100) /*!< Internal High Speed clock enable */ |
| mbed_official | 623:db79ecd649d0 | 5411 | #define RCC_CR_HSIKERON ((uint32_t)0x00000200) /*!< Internal High Speed clock enable for some IPs Kernel */ |
| mbed_official | 623:db79ecd649d0 | 5412 | #define RCC_CR_HSIRDY ((uint32_t)0x00000400) /*!< Internal High Speed clock ready flag */ |
| mbed_official | 623:db79ecd649d0 | 5413 | #define RCC_CR_HSIASFS ((uint32_t)0x00000800) /*!< HSI Automatic Start from Stop */ |
| mbed_official | 623:db79ecd649d0 | 5414 | |
| mbed_official | 623:db79ecd649d0 | 5415 | #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ |
| mbed_official | 623:db79ecd649d0 | 5416 | #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready */ |
| mbed_official | 623:db79ecd649d0 | 5417 | #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ |
| mbed_official | 623:db79ecd649d0 | 5418 | #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< HSE Clock Security System enable */ |
| mbed_official | 623:db79ecd649d0 | 5419 | |
| mbed_official | 623:db79ecd649d0 | 5420 | #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< System PLL clock enable */ |
| mbed_official | 623:db79ecd649d0 | 5421 | #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< System PLL clock ready */ |
| mbed_official | 623:db79ecd649d0 | 5422 | #define RCC_CR_PLLSAI1ON ((uint32_t)0x04000000) /*!< SAI1 PLL enable */ |
| mbed_official | 623:db79ecd649d0 | 5423 | #define RCC_CR_PLLSAI1RDY ((uint32_t)0x08000000) /*!< SAI1 PLL ready */ |
| mbed_official | 623:db79ecd649d0 | 5424 | #define RCC_CR_PLLSAI2ON ((uint32_t)0x10000000) /*!< SAI2 PLL enable */ |
| mbed_official | 623:db79ecd649d0 | 5425 | #define RCC_CR_PLLSAI2RDY ((uint32_t)0x20000000) /*!< SAI2 PLL ready */ |
| mbed_official | 623:db79ecd649d0 | 5426 | |
| mbed_official | 623:db79ecd649d0 | 5427 | /******************** Bit definition for RCC_ICSCR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 5428 | /*!< MSICAL configuration */ |
| mbed_official | 623:db79ecd649d0 | 5429 | #define RCC_ICSCR_MSICAL ((uint32_t)0x000000FF) /*!< MSICAL[7:0] bits */ |
| mbed_official | 623:db79ecd649d0 | 5430 | #define RCC_ICSCR_MSICAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5431 | #define RCC_ICSCR_MSICAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5432 | #define RCC_ICSCR_MSICAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 5433 | #define RCC_ICSCR_MSICAL_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 5434 | #define RCC_ICSCR_MSICAL_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 5435 | #define RCC_ICSCR_MSICAL_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 5436 | #define RCC_ICSCR_MSICAL_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 5437 | #define RCC_ICSCR_MSICAL_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 5438 | |
| mbed_official | 623:db79ecd649d0 | 5439 | /*!< MSITRIM configuration */ |
| mbed_official | 623:db79ecd649d0 | 5440 | #define RCC_ICSCR_MSITRIM ((uint32_t)0x0000FF00) /*!< MSITRIM[7:0] bits */ |
| mbed_official | 623:db79ecd649d0 | 5441 | #define RCC_ICSCR_MSITRIM_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5442 | #define RCC_ICSCR_MSITRIM_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5443 | #define RCC_ICSCR_MSITRIM_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 5444 | #define RCC_ICSCR_MSITRIM_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 5445 | #define RCC_ICSCR_MSITRIM_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 5446 | #define RCC_ICSCR_MSITRIM_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 5447 | #define RCC_ICSCR_MSITRIM_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 5448 | #define RCC_ICSCR_MSITRIM_7 ((uint32_t)0x00008000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 5449 | |
| mbed_official | 623:db79ecd649d0 | 5450 | /*!< HSICAL configuration */ |
| mbed_official | 623:db79ecd649d0 | 5451 | #define RCC_ICSCR_HSICAL ((uint32_t)0x00FF0000) /*!< HSICAL[7:0] bits */ |
| mbed_official | 623:db79ecd649d0 | 5452 | #define RCC_ICSCR_HSICAL_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5453 | #define RCC_ICSCR_HSICAL_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5454 | #define RCC_ICSCR_HSICAL_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 5455 | #define RCC_ICSCR_HSICAL_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 5456 | #define RCC_ICSCR_HSICAL_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 5457 | #define RCC_ICSCR_HSICAL_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 5458 | #define RCC_ICSCR_HSICAL_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 5459 | #define RCC_ICSCR_HSICAL_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 5460 | |
| mbed_official | 623:db79ecd649d0 | 5461 | /*!< HSITRIM configuration */ |
| mbed_official | 623:db79ecd649d0 | 5462 | #define RCC_ICSCR_HSITRIM ((uint32_t)0x1F000000) /*!< HSITRIM[7:0] bits */ |
| mbed_official | 623:db79ecd649d0 | 5463 | #define RCC_ICSCR_HSITRIM_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5464 | #define RCC_ICSCR_HSITRIM_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5465 | #define RCC_ICSCR_HSITRIM_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 5466 | #define RCC_ICSCR_HSITRIM_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 5467 | #define RCC_ICSCR_HSITRIM_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 5468 | |
| mbed_official | 623:db79ecd649d0 | 5469 | /******************** Bit definition for RCC_PLLCFGR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 5470 | #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00000003) |
| mbed_official | 623:db79ecd649d0 | 5471 | |
| mbed_official | 623:db79ecd649d0 | 5472 | #define RCC_PLLCFGR_PLLSRC_MSI ((uint32_t)0x00000001) /*!< MSI source clock selected */ |
| mbed_official | 623:db79ecd649d0 | 5473 | #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000002) /*!< HSI source clock selected */ |
| mbed_official | 623:db79ecd649d0 | 5474 | #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00000003) /*!< HSE source clock selected */ |
| mbed_official | 623:db79ecd649d0 | 5475 | |
| mbed_official | 623:db79ecd649d0 | 5476 | #define RCC_PLLCFGR_PLLM ((uint32_t)0x00000070) |
| mbed_official | 623:db79ecd649d0 | 5477 | #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5478 | #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5479 | #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 5480 | |
| mbed_official | 623:db79ecd649d0 | 5481 | #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007F00) |
| mbed_official | 623:db79ecd649d0 | 5482 | #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5483 | #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5484 | #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 5485 | #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 5486 | #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5487 | #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5488 | #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5489 | |
| mbed_official | 623:db79ecd649d0 | 5490 | #define RCC_PLLCFGR_PLLPEN ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5491 | #define RCC_PLLCFGR_PLLP ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5492 | #define RCC_PLLCFGR_PLLQEN ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 5493 | |
| mbed_official | 623:db79ecd649d0 | 5494 | #define RCC_PLLCFGR_PLLQ ((uint32_t)0x00600000) |
| mbed_official | 623:db79ecd649d0 | 5495 | #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 5496 | #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 5497 | |
| mbed_official | 623:db79ecd649d0 | 5498 | #define RCC_PLLCFGR_PLLREN ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 5499 | #define RCC_PLLCFGR_PLLR ((uint32_t)0x06000000) |
| mbed_official | 623:db79ecd649d0 | 5500 | #define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 5501 | #define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 5502 | |
| mbed_official | 623:db79ecd649d0 | 5503 | /******************** Bit definition for RCC_CFGR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 5504 | /*!< SW configuration */ |
| mbed_official | 623:db79ecd649d0 | 5505 | #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ |
| mbed_official | 623:db79ecd649d0 | 5506 | #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5507 | #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5508 | |
| mbed_official | 623:db79ecd649d0 | 5509 | #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selection as system clock */ |
| mbed_official | 623:db79ecd649d0 | 5510 | #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selection as system clock */ |
| mbed_official | 623:db79ecd649d0 | 5511 | #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selection as system clock */ |
| mbed_official | 623:db79ecd649d0 | 5512 | #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selection as system clock */ |
| mbed_official | 623:db79ecd649d0 | 5513 | |
| mbed_official | 623:db79ecd649d0 | 5514 | #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI used as system clock */ |
| mbed_official | 623:db79ecd649d0 | 5515 | #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI used as system clock */ |
| mbed_official | 623:db79ecd649d0 | 5516 | #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE used as system clock */ |
| mbed_official | 623:db79ecd649d0 | 5517 | #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */ |
| mbed_official | 623:db79ecd649d0 | 5518 | |
| mbed_official | 623:db79ecd649d0 | 5519 | /*!< SWS configuration */ |
| mbed_official | 623:db79ecd649d0 | 5520 | #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ |
| mbed_official | 623:db79ecd649d0 | 5521 | #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5522 | #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5523 | |
| mbed_official | 623:db79ecd649d0 | 5524 | /*!< HPRE configuration */ |
| mbed_official | 623:db79ecd649d0 | 5525 | #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 5526 | #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5527 | #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5528 | #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 5529 | #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 5530 | |
| mbed_official | 623:db79ecd649d0 | 5531 | #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ |
| mbed_official | 623:db79ecd649d0 | 5532 | #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ |
| mbed_official | 623:db79ecd649d0 | 5533 | #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ |
| mbed_official | 623:db79ecd649d0 | 5534 | #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ |
| mbed_official | 623:db79ecd649d0 | 5535 | #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ |
| mbed_official | 623:db79ecd649d0 | 5536 | #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ |
| mbed_official | 623:db79ecd649d0 | 5537 | #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ |
| mbed_official | 623:db79ecd649d0 | 5538 | #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ |
| mbed_official | 623:db79ecd649d0 | 5539 | #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ |
| mbed_official | 623:db79ecd649d0 | 5540 | |
| mbed_official | 623:db79ecd649d0 | 5541 | /*!< PPRE1 configuration */ |
| mbed_official | 623:db79ecd649d0 | 5542 | #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB2 prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 5543 | #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5544 | #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5545 | #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 5546 | |
| mbed_official | 623:db79ecd649d0 | 5547 | #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
| mbed_official | 623:db79ecd649d0 | 5548 | #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ |
| mbed_official | 623:db79ecd649d0 | 5549 | #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ |
| mbed_official | 623:db79ecd649d0 | 5550 | #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ |
| mbed_official | 623:db79ecd649d0 | 5551 | #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ |
| mbed_official | 623:db79ecd649d0 | 5552 | |
| mbed_official | 623:db79ecd649d0 | 5553 | /*!< PPRE2 configuration */ |
| mbed_official | 623:db79ecd649d0 | 5554 | #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 5555 | #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5556 | #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5557 | #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 5558 | |
| mbed_official | 623:db79ecd649d0 | 5559 | #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ |
| mbed_official | 623:db79ecd649d0 | 5560 | #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ |
| mbed_official | 623:db79ecd649d0 | 5561 | #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ |
| mbed_official | 623:db79ecd649d0 | 5562 | #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ |
| mbed_official | 623:db79ecd649d0 | 5563 | #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ |
| mbed_official | 623:db79ecd649d0 | 5564 | |
| mbed_official | 623:db79ecd649d0 | 5565 | #define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000) /*!< Wake Up from stop and CSS backup clock selection */ |
| mbed_official | 623:db79ecd649d0 | 5566 | |
| mbed_official | 623:db79ecd649d0 | 5567 | /*!< MCOSEL configuration */ |
| mbed_official | 623:db79ecd649d0 | 5568 | #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCOSEL [2:0] bits (Clock output selection) */ |
| mbed_official | 623:db79ecd649d0 | 5569 | #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 5570 | #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 5571 | #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 5572 | |
| mbed_official | 623:db79ecd649d0 | 5573 | #define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */ |
| mbed_official | 623:db79ecd649d0 | 5574 | #define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */ |
| mbed_official | 623:db79ecd649d0 | 5575 | #define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */ |
| mbed_official | 623:db79ecd649d0 | 5576 | #define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */ |
| mbed_official | 623:db79ecd649d0 | 5577 | #define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */ |
| mbed_official | 623:db79ecd649d0 | 5578 | #define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */ |
| mbed_official | 623:db79ecd649d0 | 5579 | |
| mbed_official | 623:db79ecd649d0 | 5580 | /******************** Bit definition for RCC_CIER register ******************/ |
| mbed_official | 623:db79ecd649d0 | 5581 | #define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5582 | #define RCC_CIER_LSERDYIE ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5583 | #define RCC_CIER_MSIRDYIE ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5584 | #define RCC_CIER_HSIRDYIE ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5585 | #define RCC_CIER_HSERDYIE ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5586 | #define RCC_CIER_PLLRDYIE ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5587 | #define RCC_CIER_PLLSAI1RDYIE ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 5588 | #define RCC_CIER_PLLSAI2RDYIE ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 5589 | #define RCC_CIER_LSECSSIE ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5590 | |
| mbed_official | 623:db79ecd649d0 | 5591 | /******************** Bit definition for RCC_CIFR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 5592 | #define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5593 | #define RCC_CIFR_LSERDYF ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5594 | #define RCC_CIFR_MSIRDYF ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5595 | #define RCC_CIFR_HSIRDYF ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5596 | #define RCC_CIFR_HSERDYF ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5597 | #define RCC_CIFR_PLLRDYF ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5598 | #define RCC_CIFR_PLLSAI1RDYF ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 5599 | #define RCC_CIFR_PLLSAI2RDYF ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 5600 | #define RCC_CIFR_CSSF ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5601 | #define RCC_CIFR_LSECSSF ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5602 | |
| mbed_official | 623:db79ecd649d0 | 5603 | /******************** Bit definition for RCC_CICR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 5604 | #define RCC_CICR_LSIRDYC ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5605 | #define RCC_CICR_LSERDYC ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5606 | #define RCC_CICR_MSIRDYC ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5607 | #define RCC_CICR_HSIRDYC ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5608 | #define RCC_CICR_HSERDYC ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5609 | #define RCC_CICR_PLLRDYC ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5610 | #define RCC_CICR_PLLSAI1RDYC ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 5611 | #define RCC_CICR_PLLSAI2RDYC ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 5612 | #define RCC_CICR_CSSC ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5613 | #define RCC_CICR_LSECSSC ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5614 | |
| mbed_official | 623:db79ecd649d0 | 5615 | /******************** Bit definition for RCC_AHB1RSTR register **************/ |
| mbed_official | 623:db79ecd649d0 | 5616 | #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5617 | #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5618 | #define RCC_AHB1RSTR_FLASHRST ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5619 | #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5620 | #define RCC_AHB1RSTR_TSCRST ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5621 | |
| mbed_official | 623:db79ecd649d0 | 5622 | /******************** Bit definition for RCC_AHB2RSTR register **************/ |
| mbed_official | 623:db79ecd649d0 | 5623 | #define RCC_AHB2RSTR_GPIOARST ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5624 | #define RCC_AHB2RSTR_GPIOBRST ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5625 | #define RCC_AHB2RSTR_GPIOCRST ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5626 | #define RCC_AHB2RSTR_GPIODRST ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5627 | #define RCC_AHB2RSTR_GPIOERST ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5628 | #define RCC_AHB2RSTR_GPIOFRST ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5629 | #define RCC_AHB2RSTR_GPIOGRST ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 5630 | #define RCC_AHB2RSTR_GPIOHRST ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 5631 | #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5632 | #define RCC_AHB2RSTR_ADCRST ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5633 | #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5634 | |
| mbed_official | 623:db79ecd649d0 | 5635 | /******************** Bit definition for RCC_AHB3RSTR register **************/ |
| mbed_official | 623:db79ecd649d0 | 5636 | #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5637 | #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5638 | |
| mbed_official | 623:db79ecd649d0 | 5639 | /******************** Bit definition for RCC_APB1RSTR1 register **************/ |
| mbed_official | 623:db79ecd649d0 | 5640 | #define RCC_APB1RSTR1_TIM2RST ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5641 | #define RCC_APB1RSTR1_TIM3RST ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5642 | #define RCC_APB1RSTR1_TIM4RST ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5643 | #define RCC_APB1RSTR1_TIM5RST ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5644 | #define RCC_APB1RSTR1_TIM6RST ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5645 | #define RCC_APB1RSTR1_TIM7RST ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5646 | #define RCC_APB1RSTR1_LCDRST ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5647 | #define RCC_APB1RSTR1_SPI2RST ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5648 | #define RCC_APB1RSTR1_SPI3RST ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 5649 | #define RCC_APB1RSTR1_USART2RST ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5650 | #define RCC_APB1RSTR1_USART3RST ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5651 | #define RCC_APB1RSTR1_UART4RST ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 5652 | #define RCC_APB1RSTR1_UART5RST ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 5653 | #define RCC_APB1RSTR1_I2C1RST ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 5654 | #define RCC_APB1RSTR1_I2C2RST ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 5655 | #define RCC_APB1RSTR1_I2C3RST ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 5656 | #define RCC_APB1RSTR1_CAN1RST ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 5657 | #define RCC_APB1RSTR1_PWRRST ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 5658 | #define RCC_APB1RSTR1_DAC1RST ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 5659 | #define RCC_APB1RSTR1_OPAMPRST ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 5660 | #define RCC_APB1RSTR1_LPTIM1RST ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 5661 | |
| mbed_official | 623:db79ecd649d0 | 5662 | /******************** Bit definition for RCC_APB1RSTR2 register **************/ |
| mbed_official | 623:db79ecd649d0 | 5663 | #define RCC_APB1RSTR2_LPUART1RST ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5664 | #define RCC_APB1RSTR2_SWPMI1RST ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5665 | #define RCC_APB1RSTR2_LPTIM2RST ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5666 | |
| mbed_official | 623:db79ecd649d0 | 5667 | /******************** Bit definition for RCC_APB2RSTR register **************/ |
| mbed_official | 623:db79ecd649d0 | 5668 | #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5669 | #define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 5670 | #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 5671 | #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5672 | #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5673 | #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5674 | #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5675 | #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5676 | #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5677 | #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 5678 | #define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 5679 | #define RCC_APB2RSTR_DFSDMRST ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 5680 | |
| mbed_official | 623:db79ecd649d0 | 5681 | /******************** Bit definition for RCC_AHB1ENR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 5682 | #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5683 | #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5684 | #define RCC_AHB1ENR_FLASHEN ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5685 | #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5686 | #define RCC_AHB1ENR_TSCEN ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5687 | |
| mbed_official | 623:db79ecd649d0 | 5688 | /******************** Bit definition for RCC_AHB2ENR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 5689 | #define RCC_AHB2ENR_GPIOAEN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5690 | #define RCC_AHB2ENR_GPIOBEN ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5691 | #define RCC_AHB2ENR_GPIOCEN ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5692 | #define RCC_AHB2ENR_GPIODEN ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5693 | #define RCC_AHB2ENR_GPIOEEN ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5694 | #define RCC_AHB2ENR_GPIOFEN ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5695 | #define RCC_AHB2ENR_GPIOGEN ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 5696 | #define RCC_AHB2ENR_GPIOHEN ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 5697 | #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5698 | #define RCC_AHB2ENR_ADCEN ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5699 | #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5700 | |
| mbed_official | 623:db79ecd649d0 | 5701 | /******************** Bit definition for RCC_AHB3ENR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 5702 | #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5703 | #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5704 | |
| mbed_official | 623:db79ecd649d0 | 5705 | /******************** Bit definition for RCC_APB1ENR1 register ***************/ |
| mbed_official | 623:db79ecd649d0 | 5706 | #define RCC_APB1ENR1_TIM2EN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5707 | #define RCC_APB1ENR1_TIM3EN ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5708 | #define RCC_APB1ENR1_TIM4EN ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5709 | #define RCC_APB1ENR1_TIM5EN ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5710 | #define RCC_APB1ENR1_TIM6EN ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5711 | #define RCC_APB1ENR1_TIM7EN ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5712 | #define RCC_APB1ENR1_LCDEN ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5713 | #define RCC_APB1ENR1_WWDGEN ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 5714 | #define RCC_APB1ENR1_SPI2EN ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5715 | #define RCC_APB1ENR1_SPI3EN ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 5716 | #define RCC_APB1ENR1_USART2EN ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5717 | #define RCC_APB1ENR1_USART3EN ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5718 | #define RCC_APB1ENR1_UART4EN ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 5719 | #define RCC_APB1ENR1_UART5EN ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 5720 | #define RCC_APB1ENR1_I2C1EN ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 5721 | #define RCC_APB1ENR1_I2C2EN ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 5722 | #define RCC_APB1ENR1_I2C3EN ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 5723 | #define RCC_APB1ENR1_CAN1EN ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 5724 | #define RCC_APB1ENR1_PWREN ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 5725 | #define RCC_APB1ENR1_DAC1EN ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 5726 | #define RCC_APB1ENR1_OPAMPEN ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 5727 | #define RCC_APB1ENR1_LPTIM1EN ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 5728 | |
| mbed_official | 623:db79ecd649d0 | 5729 | /******************** Bit definition for RCC_APB1RSTR2 register **************/ |
| mbed_official | 623:db79ecd649d0 | 5730 | #define RCC_APB1ENR2_LPUART1EN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5731 | #define RCC_APB1ENR2_SWPMI1EN ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5732 | #define RCC_APB1ENR2_LPTIM2EN ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5733 | |
| mbed_official | 623:db79ecd649d0 | 5734 | /******************** Bit definition for RCC_APB2ENR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 5735 | #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5736 | #define RCC_APB2ENR_FWEN ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 5737 | #define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 5738 | #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 5739 | #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5740 | #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5741 | #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5742 | #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5743 | #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5744 | #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5745 | #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 5746 | #define RCC_APB2ENR_SAI2EN ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 5747 | #define RCC_APB2ENR_DFSDMEN ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 5748 | |
| mbed_official | 623:db79ecd649d0 | 5749 | /******************** Bit definition for RCC_AHB1SMENR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 5750 | #define RCC_AHB1SMENR_DMA1SMEN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5751 | #define RCC_AHB1SMENR_DMA2SMEN ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5752 | #define RCC_AHB1SMENR_FLASHSMEN ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5753 | #define RCC_AHB1SMENR_SRAM1SMEN ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5754 | #define RCC_AHB1SMENR_CRCSMEN ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5755 | #define RCC_AHB1SMENR_TSCSMEN ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5756 | |
| mbed_official | 623:db79ecd649d0 | 5757 | /******************** Bit definition for RCC_AHB2SMENR register *************/ |
| mbed_official | 623:db79ecd649d0 | 5758 | #define RCC_AHB2SMENR_GPIOASMEN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5759 | #define RCC_AHB2SMENR_GPIOBSMEN ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5760 | #define RCC_AHB2SMENR_GPIOCSMEN ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5761 | #define RCC_AHB2SMENR_GPIODSMEN ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5762 | #define RCC_AHB2SMENR_GPIOESMEN ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5763 | #define RCC_AHB2SMENR_GPIOFSMEN ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5764 | #define RCC_AHB2SMENR_GPIOGSMEN ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 5765 | #define RCC_AHB2SMENR_GPIOHSMEN ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 5766 | #define RCC_AHB2SMENR_SRAM2SMEN ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5767 | #define RCC_AHB2SMENR_OTGFSSMEN ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5768 | #define RCC_AHB2SMENR_ADCSMEN ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5769 | #define RCC_AHB2SMENR_RNGSMEN ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5770 | |
| mbed_official | 623:db79ecd649d0 | 5771 | /******************** Bit definition for RCC_AHB3SMENR register *************/ |
| mbed_official | 623:db79ecd649d0 | 5772 | #define RCC_AHB3SMENR_FMCSMEN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5773 | #define RCC_AHB3SMENR_QSPISMEN ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5774 | |
| mbed_official | 623:db79ecd649d0 | 5775 | /******************** Bit definition for RCC_APB1SMENR1 register *************/ |
| mbed_official | 623:db79ecd649d0 | 5776 | #define RCC_APB1SMENR1_TIM2SMEN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5777 | #define RCC_APB1SMENR1_TIM3SMEN ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5778 | #define RCC_APB1SMENR1_TIM4SMEN ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5779 | #define RCC_APB1SMENR1_TIM5SMEN ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5780 | #define RCC_APB1SMENR1_TIM6SMEN ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5781 | #define RCC_APB1SMENR1_TIM7SMEN ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5782 | #define RCC_APB1SMENR1_LCDSMEN ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5783 | #define RCC_APB1SMENR1_WWDGSMEN ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 5784 | #define RCC_APB1SMENR1_SPI2SMEN ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5785 | #define RCC_APB1SMENR1_SPI3SMEN ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 5786 | #define RCC_APB1SMENR1_USART2SMEN ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5787 | #define RCC_APB1SMENR1_USART3SMEN ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5788 | #define RCC_APB1SMENR1_UART4SMEN ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 5789 | #define RCC_APB1SMENR1_UART5SMEN ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 5790 | #define RCC_APB1SMENR1_I2C1SMEN ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 5791 | #define RCC_APB1SMENR1_I2C2SMEN ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 5792 | #define RCC_APB1SMENR1_I2C3SMEN ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 5793 | #define RCC_APB1SMENR1_CAN1SMEN ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 5794 | #define RCC_APB1SMENR1_PWRSMEN ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 5795 | #define RCC_APB1SMENR1_DAC1SMEN ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 5796 | #define RCC_APB1SMENR1_OPAMPSMEN ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 5797 | #define RCC_APB1SMENR1_LPTIM1SMEN ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 5798 | |
| mbed_official | 623:db79ecd649d0 | 5799 | /******************** Bit definition for RCC_APB1SMENR2 register *************/ |
| mbed_official | 623:db79ecd649d0 | 5800 | #define RCC_APB1SMENR2_LPUART1SMEN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5801 | #define RCC_APB1SMENR2_SWPMI1SMEN ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5802 | #define RCC_APB1SMENR2_LPTIM2SMEN ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5803 | |
| mbed_official | 623:db79ecd649d0 | 5804 | /******************** Bit definition for RCC_APB2SMENR register *************/ |
| mbed_official | 623:db79ecd649d0 | 5805 | #define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5806 | #define RCC_APB2SMENR_SDMMC1SMEN ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 5807 | #define RCC_APB2SMENR_TIM1SMEN ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 5808 | #define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5809 | #define RCC_APB2SMENR_TIM8SMEN ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5810 | #define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5811 | #define RCC_APB2SMENR_TIM15SMEN ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5812 | #define RCC_APB2SMENR_TIM16SMEN ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5813 | #define RCC_APB2SMENR_TIM17SMEN ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5814 | #define RCC_APB2SMENR_SAI1SMEN ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 5815 | #define RCC_APB2SMENR_SAI2SMEN ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 5816 | #define RCC_APB2SMENR_DFSDMSMEN ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 5817 | |
| mbed_official | 623:db79ecd649d0 | 5818 | /******************** Bit definition for RCC_CCIPR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 5819 | #define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003) |
| mbed_official | 623:db79ecd649d0 | 5820 | #define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5821 | #define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5822 | |
| mbed_official | 623:db79ecd649d0 | 5823 | #define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000C) |
| mbed_official | 623:db79ecd649d0 | 5824 | #define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5825 | #define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5826 | |
| mbed_official | 623:db79ecd649d0 | 5827 | #define RCC_CCIPR_USART3SEL ((uint32_t)0x00000030) |
| mbed_official | 623:db79ecd649d0 | 5828 | #define RCC_CCIPR_USART3SEL_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5829 | #define RCC_CCIPR_USART3SEL_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5830 | |
| mbed_official | 623:db79ecd649d0 | 5831 | #define RCC_CCIPR_UART4SEL ((uint32_t)0x000000C0) |
| mbed_official | 623:db79ecd649d0 | 5832 | #define RCC_CCIPR_UART4SEL_0 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 5833 | #define RCC_CCIPR_UART4SEL_1 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 5834 | |
| mbed_official | 623:db79ecd649d0 | 5835 | #define RCC_CCIPR_UART5SEL ((uint32_t)0x00000300) |
| mbed_official | 623:db79ecd649d0 | 5836 | #define RCC_CCIPR_UART5SEL_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5837 | #define RCC_CCIPR_UART5SEL_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5838 | |
| mbed_official | 623:db79ecd649d0 | 5839 | #define RCC_CCIPR_LPUART1SEL ((uint32_t)0x00000C00) |
| mbed_official | 623:db79ecd649d0 | 5840 | #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 5841 | #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 5842 | |
| mbed_official | 623:db79ecd649d0 | 5843 | #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000) |
| mbed_official | 623:db79ecd649d0 | 5844 | #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5845 | #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5846 | |
| mbed_official | 623:db79ecd649d0 | 5847 | #define RCC_CCIPR_I2C2SEL ((uint32_t)0x0000C000) |
| mbed_official | 623:db79ecd649d0 | 5848 | #define RCC_CCIPR_I2C2SEL_0 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5849 | #define RCC_CCIPR_I2C2SEL_1 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 5850 | |
| mbed_official | 623:db79ecd649d0 | 5851 | #define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000) |
| mbed_official | 623:db79ecd649d0 | 5852 | #define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5853 | #define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5854 | |
| mbed_official | 623:db79ecd649d0 | 5855 | #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000) |
| mbed_official | 623:db79ecd649d0 | 5856 | #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5857 | #define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 5858 | |
| mbed_official | 623:db79ecd649d0 | 5859 | #define RCC_CCIPR_LPTIM2SEL ((uint32_t)0x00300000) |
| mbed_official | 623:db79ecd649d0 | 5860 | #define RCC_CCIPR_LPTIM2SEL_0 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 5861 | #define RCC_CCIPR_LPTIM2SEL_1 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 5862 | |
| mbed_official | 623:db79ecd649d0 | 5863 | #define RCC_CCIPR_SAI1SEL ((uint32_t)0x00C00000) |
| mbed_official | 623:db79ecd649d0 | 5864 | #define RCC_CCIPR_SAI1SEL_0 ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 5865 | #define RCC_CCIPR_SAI1SEL_1 ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 5866 | |
| mbed_official | 623:db79ecd649d0 | 5867 | #define RCC_CCIPR_SAI2SEL ((uint32_t)0x03000000) |
| mbed_official | 623:db79ecd649d0 | 5868 | #define RCC_CCIPR_SAI2SEL_0 ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 5869 | #define RCC_CCIPR_SAI2SEL_1 ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 5870 | |
| mbed_official | 623:db79ecd649d0 | 5871 | #define RCC_CCIPR_CLK48SEL ((uint32_t)0x0C000000) |
| mbed_official | 623:db79ecd649d0 | 5872 | #define RCC_CCIPR_CLK48SEL_0 ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 5873 | #define RCC_CCIPR_CLK48SEL_1 ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 5874 | |
| mbed_official | 623:db79ecd649d0 | 5875 | #define RCC_CCIPR_ADCSEL ((uint32_t)0x30000000) |
| mbed_official | 623:db79ecd649d0 | 5876 | #define RCC_CCIPR_ADCSEL_0 ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 5877 | #define RCC_CCIPR_ADCSEL_1 ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 5878 | |
| mbed_official | 623:db79ecd649d0 | 5879 | #define RCC_CCIPR_SWPMI1SEL ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 5880 | #define RCC_CCIPR_DFSDMSEL ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 5881 | |
| mbed_official | 623:db79ecd649d0 | 5882 | /******************** Bit definition for RCC_BDCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 5883 | #define RCC_BDCR_LSEON ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5884 | #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5885 | #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5886 | |
| mbed_official | 623:db79ecd649d0 | 5887 | #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) |
| mbed_official | 623:db79ecd649d0 | 5888 | #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5889 | #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5890 | |
| mbed_official | 623:db79ecd649d0 | 5891 | #define RCC_BDCR_LSECSSON ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5892 | #define RCC_BDCR_LSECSSD ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 5893 | |
| mbed_official | 623:db79ecd649d0 | 5894 | #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) |
| mbed_official | 623:db79ecd649d0 | 5895 | #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5896 | #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5897 | |
| mbed_official | 623:db79ecd649d0 | 5898 | #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 5899 | #define RCC_BDCR_BDRST ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5900 | #define RCC_BDCR_LSCOEN ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 5901 | #define RCC_BDCR_LSCOSEL ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 5902 | |
| mbed_official | 623:db79ecd649d0 | 5903 | /******************** Bit definition for RCC_CSR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 5904 | #define RCC_CSR_LSION ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5905 | #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5906 | |
| mbed_official | 623:db79ecd649d0 | 5907 | #define RCC_CSR_MSISRANGE ((uint32_t)0x00000F00) |
| mbed_official | 623:db79ecd649d0 | 5908 | #define RCC_CSR_MSISRANGE_1 ((uint32_t)0x00000400) /*!< MSI frequency 1MHZ */ |
| mbed_official | 623:db79ecd649d0 | 5909 | #define RCC_CSR_MSISRANGE_2 ((uint32_t)0x00000500) /*!< MSI frequency 2MHZ */ |
| mbed_official | 623:db79ecd649d0 | 5910 | #define RCC_CSR_MSISRANGE_4 ((uint32_t)0x00000600) /*!< The default frequency 4MHZ */ |
| mbed_official | 623:db79ecd649d0 | 5911 | #define RCC_CSR_MSISRANGE_8 ((uint32_t)0x00000700) /*!< MSI frequency 8MHZ */ |
| mbed_official | 623:db79ecd649d0 | 5912 | |
| mbed_official | 623:db79ecd649d0 | 5913 | #define RCC_CSR_RMVF ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 5914 | #define RCC_CSR_FWRSTF ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 5915 | #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 5916 | #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 5917 | #define RCC_CSR_BORRSTF ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 5918 | #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 5919 | #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 5920 | #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 5921 | #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 5922 | |
| mbed_official | 623:db79ecd649d0 | 5923 | /******************** Bit definition for RCC_PLLSAI1CFGR register ************/ |
| mbed_official | 623:db79ecd649d0 | 5924 | #define RCC_PLLSAI1CFGR_PLLSAI1N ((uint32_t)0x00007F00) |
| mbed_official | 623:db79ecd649d0 | 5925 | #define RCC_PLLSAI1CFGR_PLLSAI1N_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5926 | #define RCC_PLLSAI1CFGR_PLLSAI1N_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5927 | #define RCC_PLLSAI1CFGR_PLLSAI1N_2 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 5928 | #define RCC_PLLSAI1CFGR_PLLSAI1N_3 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 5929 | #define RCC_PLLSAI1CFGR_PLLSAI1N_4 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5930 | #define RCC_PLLSAI1CFGR_PLLSAI1N_5 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5931 | #define RCC_PLLSAI1CFGR_PLLSAI1N_6 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5932 | |
| mbed_official | 623:db79ecd649d0 | 5933 | #define RCC_PLLSAI1CFGR_PLLSAI1PEN ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5934 | #define RCC_PLLSAI1CFGR_PLLSAI1P ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5935 | #define RCC_PLLSAI1CFGR_PLLSAI1QEN ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 5936 | #define RCC_PLLSAI1CFGR_PLLSAI1Q ((uint32_t)0x00600000) |
| mbed_official | 623:db79ecd649d0 | 5937 | #define RCC_PLLSAI1CFGR_PLLSAI1REN ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 5938 | #define RCC_PLLSAI1CFGR_PLLSAI1R ((uint32_t)0x06000000) |
| mbed_official | 623:db79ecd649d0 | 5939 | |
| mbed_official | 623:db79ecd649d0 | 5940 | /******************** Bit definition for RCC_PLLSAI2CFGR register ************/ |
| mbed_official | 623:db79ecd649d0 | 5941 | #define RCC_PLLSAI2CFGR_PLLSAI2N ((uint32_t)0x00007F00) |
| mbed_official | 623:db79ecd649d0 | 5942 | #define RCC_PLLSAI2CFGR_PLLSAI2N_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5943 | #define RCC_PLLSAI2CFGR_PLLSAI2N_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5944 | #define RCC_PLLSAI2CFGR_PLLSAI2N_2 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 5945 | #define RCC_PLLSAI2CFGR_PLLSAI2N_3 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 5946 | #define RCC_PLLSAI2CFGR_PLLSAI2N_4 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5947 | #define RCC_PLLSAI2CFGR_PLLSAI2N_5 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5948 | #define RCC_PLLSAI2CFGR_PLLSAI2N_6 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5949 | |
| mbed_official | 623:db79ecd649d0 | 5950 | #define RCC_PLLSAI2CFGR_PLLSAI2PEN ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5951 | #define RCC_PLLSAI2CFGR_PLLSAI2P ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5952 | #define RCC_PLLSAI2CFGR_PLLSAI2REN ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 5953 | #define RCC_PLLSAI2CFGR_PLLSAI2R ((uint32_t)0x06000000) |
| mbed_official | 623:db79ecd649d0 | 5954 | |
| mbed_official | 623:db79ecd649d0 | 5955 | |
| mbed_official | 623:db79ecd649d0 | 5956 | |
| mbed_official | 623:db79ecd649d0 | 5957 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 5958 | /* */ |
| mbed_official | 623:db79ecd649d0 | 5959 | /* RNG */ |
| mbed_official | 623:db79ecd649d0 | 5960 | /* */ |
| mbed_official | 623:db79ecd649d0 | 5961 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 5962 | /******************** Bits definition for RNG_CR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 5963 | #define RNG_CR_RNGEN ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5964 | #define RNG_CR_IE ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 5965 | |
| mbed_official | 623:db79ecd649d0 | 5966 | /******************** Bits definition for RNG_SR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 5967 | #define RNG_SR_DRDY ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 5968 | #define RNG_SR_CECS ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 5969 | #define RNG_SR_SECS ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 5970 | #define RNG_SR_CEIS ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 5971 | #define RNG_SR_SEIS ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 5972 | |
| mbed_official | 623:db79ecd649d0 | 5973 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 5974 | /* */ |
| mbed_official | 623:db79ecd649d0 | 5975 | /* Real-Time Clock (RTC) */ |
| mbed_official | 623:db79ecd649d0 | 5976 | /* */ |
| mbed_official | 623:db79ecd649d0 | 5977 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 5978 | /******************** Bits definition for RTC_TR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 5979 | #define RTC_TR_PM ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 5980 | #define RTC_TR_HT ((uint32_t)0x00300000) |
| mbed_official | 623:db79ecd649d0 | 5981 | #define RTC_TR_HT_0 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 5982 | #define RTC_TR_HT_1 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 5983 | #define RTC_TR_HU ((uint32_t)0x000F0000) |
| mbed_official | 623:db79ecd649d0 | 5984 | #define RTC_TR_HU_0 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 5985 | #define RTC_TR_HU_1 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 5986 | #define RTC_TR_HU_2 ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 5987 | #define RTC_TR_HU_3 ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 5988 | #define RTC_TR_MNT ((uint32_t)0x00007000) |
| mbed_official | 623:db79ecd649d0 | 5989 | #define RTC_TR_MNT_0 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 5990 | #define RTC_TR_MNT_1 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 5991 | #define RTC_TR_MNT_2 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 5992 | #define RTC_TR_MNU ((uint32_t)0x00000F00) |
| mbed_official | 623:db79ecd649d0 | 5993 | #define RTC_TR_MNU_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 5994 | #define RTC_TR_MNU_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 5995 | #define RTC_TR_MNU_2 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 5996 | #define RTC_TR_MNU_3 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 5997 | #define RTC_TR_ST ((uint32_t)0x00000070) |
| mbed_official | 623:db79ecd649d0 | 5998 | #define RTC_TR_ST_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 5999 | #define RTC_TR_ST_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6000 | #define RTC_TR_ST_2 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 6001 | #define RTC_TR_SU ((uint32_t)0x0000000F) |
| mbed_official | 623:db79ecd649d0 | 6002 | #define RTC_TR_SU_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6003 | #define RTC_TR_SU_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6004 | #define RTC_TR_SU_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6005 | #define RTC_TR_SU_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 6006 | |
| mbed_official | 623:db79ecd649d0 | 6007 | /******************** Bits definition for RTC_DR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6008 | #define RTC_DR_YT ((uint32_t)0x00F00000) |
| mbed_official | 623:db79ecd649d0 | 6009 | #define RTC_DR_YT_0 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 6010 | #define RTC_DR_YT_1 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 6011 | #define RTC_DR_YT_2 ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 6012 | #define RTC_DR_YT_3 ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 6013 | #define RTC_DR_YU ((uint32_t)0x000F0000) |
| mbed_official | 623:db79ecd649d0 | 6014 | #define RTC_DR_YU_0 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 6015 | #define RTC_DR_YU_1 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 6016 | #define RTC_DR_YU_2 ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 6017 | #define RTC_DR_YU_3 ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 6018 | #define RTC_DR_WDU ((uint32_t)0x0000E000) |
| mbed_official | 623:db79ecd649d0 | 6019 | #define RTC_DR_WDU_0 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 6020 | #define RTC_DR_WDU_1 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 6021 | #define RTC_DR_WDU_2 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 6022 | #define RTC_DR_MT ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 6023 | #define RTC_DR_MU ((uint32_t)0x00000F00) |
| mbed_official | 623:db79ecd649d0 | 6024 | #define RTC_DR_MU_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 6025 | #define RTC_DR_MU_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 6026 | #define RTC_DR_MU_2 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 6027 | #define RTC_DR_MU_3 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 6028 | #define RTC_DR_DT ((uint32_t)0x00000030) |
| mbed_official | 623:db79ecd649d0 | 6029 | #define RTC_DR_DT_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 6030 | #define RTC_DR_DT_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6031 | #define RTC_DR_DU ((uint32_t)0x0000000F) |
| mbed_official | 623:db79ecd649d0 | 6032 | #define RTC_DR_DU_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6033 | #define RTC_DR_DU_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6034 | #define RTC_DR_DU_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6035 | #define RTC_DR_DU_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 6036 | |
| mbed_official | 623:db79ecd649d0 | 6037 | /******************** Bits definition for RTC_CR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6038 | #define RTC_CR_ITSE ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 6039 | #define RTC_CR_COE ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 6040 | #define RTC_CR_OSEL ((uint32_t)0x00600000) |
| mbed_official | 623:db79ecd649d0 | 6041 | #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 6042 | #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 6043 | #define RTC_CR_POL ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 6044 | #define RTC_CR_COSEL ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 6045 | #define RTC_CR_BCK ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 6046 | #define RTC_CR_SUB1H ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 6047 | #define RTC_CR_ADD1H ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 6048 | #define RTC_CR_TSIE ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 6049 | #define RTC_CR_WUTIE ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 6050 | #define RTC_CR_ALRBIE ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 6051 | #define RTC_CR_ALRAIE ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 6052 | #define RTC_CR_TSE ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 6053 | #define RTC_CR_WUTE ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 6054 | #define RTC_CR_ALRBE ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 6055 | #define RTC_CR_ALRAE ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 6056 | #define RTC_CR_FMT ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 6057 | #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6058 | #define RTC_CR_REFCKON ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 6059 | #define RTC_CR_TSEDGE ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 6060 | #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) |
| mbed_official | 623:db79ecd649d0 | 6061 | #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6062 | #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6063 | #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6064 | |
| mbed_official | 623:db79ecd649d0 | 6065 | /******************** Bits definition for RTC_ISR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6066 | #define RTC_ISR_ITSF ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 6067 | #define RTC_ISR_RECALPF ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 6068 | #define RTC_ISR_TAMP3F ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 6069 | #define RTC_ISR_TAMP2F ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 6070 | #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 6071 | #define RTC_ISR_TSOVF ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 6072 | #define RTC_ISR_TSF ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 6073 | #define RTC_ISR_WUTF ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 6074 | #define RTC_ISR_ALRBF ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 6075 | #define RTC_ISR_ALRAF ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 6076 | #define RTC_ISR_INIT ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 6077 | #define RTC_ISR_INITF ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 6078 | #define RTC_ISR_RSF ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6079 | #define RTC_ISR_INITS ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 6080 | #define RTC_ISR_SHPF ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 6081 | #define RTC_ISR_WUTWF ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6082 | #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6083 | #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6084 | |
| mbed_official | 623:db79ecd649d0 | 6085 | /******************** Bits definition for RTC_PRER register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6086 | #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) |
| mbed_official | 623:db79ecd649d0 | 6087 | #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) |
| mbed_official | 623:db79ecd649d0 | 6088 | |
| mbed_official | 623:db79ecd649d0 | 6089 | /******************** Bits definition for RTC_WUTR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6090 | #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) |
| mbed_official | 623:db79ecd649d0 | 6091 | |
| mbed_official | 623:db79ecd649d0 | 6092 | /******************** Bits definition for RTC_ALRMAR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6093 | #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 6094 | #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 6095 | #define RTC_ALRMAR_DT ((uint32_t)0x30000000) |
| mbed_official | 623:db79ecd649d0 | 6096 | #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 6097 | #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 6098 | #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) |
| mbed_official | 623:db79ecd649d0 | 6099 | #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 6100 | #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 6101 | #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 6102 | #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 6103 | #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 6104 | #define RTC_ALRMAR_PM ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 6105 | #define RTC_ALRMAR_HT ((uint32_t)0x00300000) |
| mbed_official | 623:db79ecd649d0 | 6106 | #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 6107 | #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 6108 | #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) |
| mbed_official | 623:db79ecd649d0 | 6109 | #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 6110 | #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 6111 | #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 6112 | #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 6113 | #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 6114 | #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) |
| mbed_official | 623:db79ecd649d0 | 6115 | #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 6116 | #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 6117 | #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 6118 | #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) |
| mbed_official | 623:db79ecd649d0 | 6119 | #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 6120 | #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 6121 | #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 6122 | #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 6123 | #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 6124 | #define RTC_ALRMAR_ST ((uint32_t)0x00000070) |
| mbed_official | 623:db79ecd649d0 | 6125 | #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 6126 | #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6127 | #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 6128 | #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) |
| mbed_official | 623:db79ecd649d0 | 6129 | #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6130 | #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6131 | #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6132 | #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 6133 | |
| mbed_official | 623:db79ecd649d0 | 6134 | /******************** Bits definition for RTC_ALRMBR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6135 | #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 6136 | #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) |
| mbed_official | 623:db79ecd649d0 | 6137 | #define RTC_ALRMBR_DT ((uint32_t)0x30000000) |
| mbed_official | 623:db79ecd649d0 | 6138 | #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) |
| mbed_official | 623:db79ecd649d0 | 6139 | #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) |
| mbed_official | 623:db79ecd649d0 | 6140 | #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) |
| mbed_official | 623:db79ecd649d0 | 6141 | #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 6142 | #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 6143 | #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 6144 | #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 6145 | #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 6146 | #define RTC_ALRMBR_PM ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 6147 | #define RTC_ALRMBR_HT ((uint32_t)0x00300000) |
| mbed_official | 623:db79ecd649d0 | 6148 | #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 6149 | #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 6150 | #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) |
| mbed_official | 623:db79ecd649d0 | 6151 | #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 6152 | #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 6153 | #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 6154 | #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 6155 | #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 6156 | #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) |
| mbed_official | 623:db79ecd649d0 | 6157 | #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 6158 | #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 6159 | #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 6160 | #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) |
| mbed_official | 623:db79ecd649d0 | 6161 | #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 6162 | #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 6163 | #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 6164 | #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 6165 | #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 6166 | #define RTC_ALRMBR_ST ((uint32_t)0x00000070) |
| mbed_official | 623:db79ecd649d0 | 6167 | #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 6168 | #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6169 | #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 6170 | #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) |
| mbed_official | 623:db79ecd649d0 | 6171 | #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6172 | #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6173 | #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6174 | #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 6175 | |
| mbed_official | 623:db79ecd649d0 | 6176 | /******************** Bits definition for RTC_WPR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6177 | #define RTC_WPR_KEY ((uint32_t)0x000000FF) |
| mbed_official | 623:db79ecd649d0 | 6178 | |
| mbed_official | 623:db79ecd649d0 | 6179 | /******************** Bits definition for RTC_SSR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6180 | #define RTC_SSR_SS ((uint32_t)0x0000FFFF) |
| mbed_official | 623:db79ecd649d0 | 6181 | |
| mbed_official | 623:db79ecd649d0 | 6182 | /******************** Bits definition for RTC_SHIFTR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6183 | #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) |
| mbed_official | 623:db79ecd649d0 | 6184 | #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 6185 | |
| mbed_official | 623:db79ecd649d0 | 6186 | /******************** Bits definition for RTC_TSTR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6187 | #define RTC_TSTR_PM ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 6188 | #define RTC_TSTR_HT ((uint32_t)0x00300000) |
| mbed_official | 623:db79ecd649d0 | 6189 | #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 6190 | #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 6191 | #define RTC_TSTR_HU ((uint32_t)0x000F0000) |
| mbed_official | 623:db79ecd649d0 | 6192 | #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 6193 | #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 6194 | #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 6195 | #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 6196 | #define RTC_TSTR_MNT ((uint32_t)0x00007000) |
| mbed_official | 623:db79ecd649d0 | 6197 | #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 6198 | #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 6199 | #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 6200 | #define RTC_TSTR_MNU ((uint32_t)0x00000F00) |
| mbed_official | 623:db79ecd649d0 | 6201 | #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 6202 | #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 6203 | #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 6204 | #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 6205 | #define RTC_TSTR_ST ((uint32_t)0x00000070) |
| mbed_official | 623:db79ecd649d0 | 6206 | #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 6207 | #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6208 | #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 6209 | #define RTC_TSTR_SU ((uint32_t)0x0000000F) |
| mbed_official | 623:db79ecd649d0 | 6210 | #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6211 | #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6212 | #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6213 | #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 6214 | |
| mbed_official | 623:db79ecd649d0 | 6215 | /******************** Bits definition for RTC_TSDR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6216 | #define RTC_TSDR_WDU ((uint32_t)0x0000E000) |
| mbed_official | 623:db79ecd649d0 | 6217 | #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 6218 | #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 6219 | #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 6220 | #define RTC_TSDR_MT ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 6221 | #define RTC_TSDR_MU ((uint32_t)0x00000F00) |
| mbed_official | 623:db79ecd649d0 | 6222 | #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 6223 | #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 6224 | #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 6225 | #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 6226 | #define RTC_TSDR_DT ((uint32_t)0x00000030) |
| mbed_official | 623:db79ecd649d0 | 6227 | #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 6228 | #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6229 | #define RTC_TSDR_DU ((uint32_t)0x0000000F) |
| mbed_official | 623:db79ecd649d0 | 6230 | #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6231 | #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6232 | #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6233 | #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 6234 | |
| mbed_official | 623:db79ecd649d0 | 6235 | /******************** Bits definition for RTC_TSSSR register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6236 | #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) |
| mbed_official | 623:db79ecd649d0 | 6237 | |
| mbed_official | 623:db79ecd649d0 | 6238 | /******************** Bits definition for RTC_CAL register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6239 | #define RTC_CALR_CALP ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 6240 | #define RTC_CALR_CALW8 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 6241 | #define RTC_CALR_CALW16 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 6242 | #define RTC_CALR_CALM ((uint32_t)0x000001FF) |
| mbed_official | 623:db79ecd649d0 | 6243 | #define RTC_CALR_CALM_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6244 | #define RTC_CALR_CALM_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6245 | #define RTC_CALR_CALM_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6246 | #define RTC_CALR_CALM_3 ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 6247 | #define RTC_CALR_CALM_4 ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 6248 | #define RTC_CALR_CALM_5 ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6249 | #define RTC_CALR_CALM_6 ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 6250 | #define RTC_CALR_CALM_7 ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 6251 | #define RTC_CALR_CALM_8 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 6252 | |
| mbed_official | 623:db79ecd649d0 | 6253 | /******************** Bits definition for RTC_TAMPCR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6254 | #define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 6255 | #define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 6256 | #define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 6257 | #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 6258 | #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000) |
| mbed_official | 623:db79ecd649d0 | 6259 | #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000) |
| mbed_official | 623:db79ecd649d0 | 6260 | #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 6261 | #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 6262 | #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 6263 | #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000) |
| mbed_official | 623:db79ecd649d0 | 6264 | #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000) |
| mbed_official | 623:db79ecd649d0 | 6265 | #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 6266 | #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000) |
| mbed_official | 623:db79ecd649d0 | 6267 | #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800) |
| mbed_official | 623:db79ecd649d0 | 6268 | #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 6269 | #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 6270 | #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700) |
| mbed_official | 623:db79ecd649d0 | 6271 | #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100) |
| mbed_official | 623:db79ecd649d0 | 6272 | #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200) |
| mbed_official | 623:db79ecd649d0 | 6273 | #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 6274 | #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080) |
| mbed_official | 623:db79ecd649d0 | 6275 | #define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040) |
| mbed_official | 623:db79ecd649d0 | 6276 | #define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6277 | #define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 6278 | #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 6279 | #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6280 | #define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6281 | #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6282 | |
| mbed_official | 623:db79ecd649d0 | 6283 | /******************** Bits definition for RTC_ALRMASSR register *************/ |
| mbed_official | 623:db79ecd649d0 | 6284 | #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) |
| mbed_official | 623:db79ecd649d0 | 6285 | #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 6286 | #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 6287 | #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 6288 | #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 6289 | #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) |
| mbed_official | 623:db79ecd649d0 | 6290 | |
| mbed_official | 623:db79ecd649d0 | 6291 | /******************** Bits definition for RTC_ALRMBSSR register *************/ |
| mbed_official | 623:db79ecd649d0 | 6292 | #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) |
| mbed_official | 623:db79ecd649d0 | 6293 | #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) |
| mbed_official | 623:db79ecd649d0 | 6294 | #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 6295 | #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) |
| mbed_official | 623:db79ecd649d0 | 6296 | #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) |
| mbed_official | 623:db79ecd649d0 | 6297 | #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) |
| mbed_official | 623:db79ecd649d0 | 6298 | |
| mbed_official | 623:db79ecd649d0 | 6299 | /******************** Bits definition for RTC_0R register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6300 | #define RTC_OR_OUT_RMP ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6301 | #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6302 | |
| mbed_official | 623:db79ecd649d0 | 6303 | |
| mbed_official | 623:db79ecd649d0 | 6304 | /******************** Bits definition for RTC_BKP0R register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6305 | #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6306 | |
| mbed_official | 623:db79ecd649d0 | 6307 | /******************** Bits definition for RTC_BKP1R register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6308 | #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6309 | |
| mbed_official | 623:db79ecd649d0 | 6310 | /******************** Bits definition for RTC_BKP2R register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6311 | #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6312 | |
| mbed_official | 623:db79ecd649d0 | 6313 | /******************** Bits definition for RTC_BKP3R register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6314 | #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6315 | |
| mbed_official | 623:db79ecd649d0 | 6316 | /******************** Bits definition for RTC_BKP4R register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6317 | #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6318 | |
| mbed_official | 623:db79ecd649d0 | 6319 | /******************** Bits definition for RTC_BKP5R register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6320 | #define RTC_BKP5R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6321 | |
| mbed_official | 623:db79ecd649d0 | 6322 | /******************** Bits definition for RTC_BKP6R register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6323 | #define RTC_BKP6R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6324 | |
| mbed_official | 623:db79ecd649d0 | 6325 | /******************** Bits definition for RTC_BKP7R register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6326 | #define RTC_BKP7R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6327 | |
| mbed_official | 623:db79ecd649d0 | 6328 | /******************** Bits definition for RTC_BKP8R register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6329 | #define RTC_BKP8R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6330 | |
| mbed_official | 623:db79ecd649d0 | 6331 | /******************** Bits definition for RTC_BKP9R register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6332 | #define RTC_BKP9R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6333 | |
| mbed_official | 623:db79ecd649d0 | 6334 | /******************** Bits definition for RTC_BKP10R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6335 | #define RTC_BKP10R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6336 | |
| mbed_official | 623:db79ecd649d0 | 6337 | /******************** Bits definition for RTC_BKP11R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6338 | #define RTC_BKP11R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6339 | |
| mbed_official | 623:db79ecd649d0 | 6340 | /******************** Bits definition for RTC_BKP12R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6341 | #define RTC_BKP12R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6342 | |
| mbed_official | 623:db79ecd649d0 | 6343 | /******************** Bits definition for RTC_BKP13R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6344 | #define RTC_BKP13R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6345 | |
| mbed_official | 623:db79ecd649d0 | 6346 | /******************** Bits definition for RTC_BKP14R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6347 | #define RTC_BKP14R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6348 | |
| mbed_official | 623:db79ecd649d0 | 6349 | /******************** Bits definition for RTC_BKP15R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6350 | #define RTC_BKP15R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6351 | |
| mbed_official | 623:db79ecd649d0 | 6352 | /******************** Bits definition for RTC_BKP16R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6353 | #define RTC_BKP16R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6354 | |
| mbed_official | 623:db79ecd649d0 | 6355 | /******************** Bits definition for RTC_BKP17R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6356 | #define RTC_BKP17R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6357 | |
| mbed_official | 623:db79ecd649d0 | 6358 | /******************** Bits definition for RTC_BKP18R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6359 | #define RTC_BKP18R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6360 | |
| mbed_official | 623:db79ecd649d0 | 6361 | /******************** Bits definition for RTC_BKP19R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6362 | #define RTC_BKP19R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6363 | |
| mbed_official | 623:db79ecd649d0 | 6364 | /******************** Bits definition for RTC_BKP20R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6365 | #define RTC_BKP20R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6366 | |
| mbed_official | 623:db79ecd649d0 | 6367 | /******************** Bits definition for RTC_BKP21R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6368 | #define RTC_BKP21R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6369 | |
| mbed_official | 623:db79ecd649d0 | 6370 | /******************** Bits definition for RTC_BKP22R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6371 | #define RTC_BKP22R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6372 | |
| mbed_official | 623:db79ecd649d0 | 6373 | /******************** Bits definition for RTC_BKP23R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6374 | #define RTC_BKP23R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6375 | |
| mbed_official | 623:db79ecd649d0 | 6376 | /******************** Bits definition for RTC_BKP24R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6377 | #define RTC_BKP24R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6378 | |
| mbed_official | 623:db79ecd649d0 | 6379 | /******************** Bits definition for RTC_BKP25R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6380 | #define RTC_BKP25R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6381 | |
| mbed_official | 623:db79ecd649d0 | 6382 | /******************** Bits definition for RTC_BKP26R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6383 | #define RTC_BKP26R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6384 | |
| mbed_official | 623:db79ecd649d0 | 6385 | /******************** Bits definition for RTC_BKP27R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6386 | #define RTC_BKP27R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6387 | |
| mbed_official | 623:db79ecd649d0 | 6388 | /******************** Bits definition for RTC_BKP28R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6389 | #define RTC_BKP28R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6390 | |
| mbed_official | 623:db79ecd649d0 | 6391 | /******************** Bits definition for RTC_BKP29R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6392 | #define RTC_BKP29R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6393 | |
| mbed_official | 623:db79ecd649d0 | 6394 | /******************** Bits definition for RTC_BKP30R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6395 | #define RTC_BKP30R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6396 | |
| mbed_official | 623:db79ecd649d0 | 6397 | /******************** Bits definition for RTC_BKP31R register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6398 | #define RTC_BKP31R ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6399 | |
| mbed_official | 623:db79ecd649d0 | 6400 | /******************** Number of backup registers ******************************/ |
| mbed_official | 623:db79ecd649d0 | 6401 | #define RTC_BKP_NUMBER ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 6402 | |
| mbed_official | 623:db79ecd649d0 | 6403 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6404 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6405 | /* Serial Audio Interface */ |
| mbed_official | 623:db79ecd649d0 | 6406 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6407 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6408 | /******************** Bit definition for SAI_GCR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6409 | #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ |
| mbed_official | 623:db79ecd649d0 | 6410 | #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6411 | #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6412 | |
| mbed_official | 623:db79ecd649d0 | 6413 | #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ |
| mbed_official | 623:db79ecd649d0 | 6414 | #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6415 | #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6416 | |
| mbed_official | 623:db79ecd649d0 | 6417 | /******************* Bit definition for SAI_xCR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6418 | #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */ |
| mbed_official | 623:db79ecd649d0 | 6419 | #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6420 | #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6421 | |
| mbed_official | 623:db79ecd649d0 | 6422 | #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */ |
| mbed_official | 623:db79ecd649d0 | 6423 | #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6424 | #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6425 | |
| mbed_official | 623:db79ecd649d0 | 6426 | #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */ |
| mbed_official | 623:db79ecd649d0 | 6427 | #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6428 | #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6429 | #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6430 | |
| mbed_official | 623:db79ecd649d0 | 6431 | #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */ |
| mbed_official | 623:db79ecd649d0 | 6432 | #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */ |
| mbed_official | 623:db79ecd649d0 | 6433 | |
| mbed_official | 623:db79ecd649d0 | 6434 | #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */ |
| mbed_official | 623:db79ecd649d0 | 6435 | #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6436 | #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6437 | |
| mbed_official | 623:db79ecd649d0 | 6438 | #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */ |
| mbed_official | 623:db79ecd649d0 | 6439 | #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */ |
| mbed_official | 623:db79ecd649d0 | 6440 | #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */ |
| mbed_official | 623:db79ecd649d0 | 6441 | #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */ |
| mbed_official | 623:db79ecd649d0 | 6442 | #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */ |
| mbed_official | 623:db79ecd649d0 | 6443 | |
| mbed_official | 623:db79ecd649d0 | 6444 | #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */ |
| mbed_official | 623:db79ecd649d0 | 6445 | #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6446 | #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6447 | #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6448 | #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6449 | |
| mbed_official | 623:db79ecd649d0 | 6450 | /******************* Bit definition for SAI_xCR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6451 | #define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */ |
| mbed_official | 623:db79ecd649d0 | 6452 | #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6453 | #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6454 | #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6455 | |
| mbed_official | 623:db79ecd649d0 | 6456 | #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */ |
| mbed_official | 623:db79ecd649d0 | 6457 | #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */ |
| mbed_official | 623:db79ecd649d0 | 6458 | #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */ |
| mbed_official | 623:db79ecd649d0 | 6459 | #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */ |
| mbed_official | 623:db79ecd649d0 | 6460 | |
| mbed_official | 623:db79ecd649d0 | 6461 | |
| mbed_official | 623:db79ecd649d0 | 6462 | #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */ |
| mbed_official | 623:db79ecd649d0 | 6463 | #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6464 | #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6465 | #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6466 | #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6467 | #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 6468 | #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 6469 | |
| mbed_official | 623:db79ecd649d0 | 6470 | #define SAI_xCR2_CPL ((uint32_t)0x00002000) /*!<CPL mode */ |
| mbed_official | 623:db79ecd649d0 | 6471 | #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */ |
| mbed_official | 623:db79ecd649d0 | 6472 | #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6473 | #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6474 | |
| mbed_official | 623:db79ecd649d0 | 6475 | |
| mbed_official | 623:db79ecd649d0 | 6476 | /****************** Bit definition for SAI_xFRCR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6477 | #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[7:0](Frame length) */ |
| mbed_official | 623:db79ecd649d0 | 6478 | #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6479 | #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6480 | #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6481 | #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6482 | #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 6483 | #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 6484 | #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 6485 | #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 6486 | |
| mbed_official | 623:db79ecd649d0 | 6487 | #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[6:0] (Frame synchronization active level length) */ |
| mbed_official | 623:db79ecd649d0 | 6488 | #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6489 | #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6490 | #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6491 | #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6492 | #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 6493 | #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 6494 | #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 6495 | |
| mbed_official | 623:db79ecd649d0 | 6496 | #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */ |
| mbed_official | 623:db79ecd649d0 | 6497 | #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */ |
| mbed_official | 623:db79ecd649d0 | 6498 | #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */ |
| mbed_official | 623:db79ecd649d0 | 6499 | |
| mbed_official | 623:db79ecd649d0 | 6500 | /****************** Bit definition for SAI_xSLOTR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6501 | #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */ |
| mbed_official | 623:db79ecd649d0 | 6502 | #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6503 | #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6504 | #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6505 | #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6506 | #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 6507 | |
| mbed_official | 623:db79ecd649d0 | 6508 | #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */ |
| mbed_official | 623:db79ecd649d0 | 6509 | #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6510 | #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6511 | |
| mbed_official | 623:db79ecd649d0 | 6512 | #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */ |
| mbed_official | 623:db79ecd649d0 | 6513 | #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6514 | #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6515 | #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6516 | #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6517 | |
| mbed_official | 623:db79ecd649d0 | 6518 | #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */ |
| mbed_official | 623:db79ecd649d0 | 6519 | |
| mbed_official | 623:db79ecd649d0 | 6520 | /******************* Bit definition for SAI_xIMR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6521 | #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 6522 | #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 6523 | #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 6524 | #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 6525 | #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 6526 | #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 6527 | #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 6528 | |
| mbed_official | 623:db79ecd649d0 | 6529 | /******************** Bit definition for SAI_xSR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6530 | #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */ |
| mbed_official | 623:db79ecd649d0 | 6531 | #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */ |
| mbed_official | 623:db79ecd649d0 | 6532 | #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */ |
| mbed_official | 623:db79ecd649d0 | 6533 | #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */ |
| mbed_official | 623:db79ecd649d0 | 6534 | #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */ |
| mbed_official | 623:db79ecd649d0 | 6535 | #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */ |
| mbed_official | 623:db79ecd649d0 | 6536 | #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */ |
| mbed_official | 623:db79ecd649d0 | 6537 | |
| mbed_official | 623:db79ecd649d0 | 6538 | #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */ |
| mbed_official | 623:db79ecd649d0 | 6539 | #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6540 | #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6541 | #define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6542 | |
| mbed_official | 623:db79ecd649d0 | 6543 | /****************** Bit definition for SAI_xCLRFR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6544 | #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */ |
| mbed_official | 623:db79ecd649d0 | 6545 | #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */ |
| mbed_official | 623:db79ecd649d0 | 6546 | #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */ |
| mbed_official | 623:db79ecd649d0 | 6547 | #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */ |
| mbed_official | 623:db79ecd649d0 | 6548 | #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */ |
| mbed_official | 623:db79ecd649d0 | 6549 | #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */ |
| mbed_official | 623:db79ecd649d0 | 6550 | #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */ |
| mbed_official | 623:db79ecd649d0 | 6551 | |
| mbed_official | 623:db79ecd649d0 | 6552 | /****************** Bit definition for SAI_xDR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6553 | #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF) |
| mbed_official | 623:db79ecd649d0 | 6554 | |
| mbed_official | 623:db79ecd649d0 | 6555 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6556 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6557 | /* LCD Controller (LCD) */ |
| mbed_official | 623:db79ecd649d0 | 6558 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6559 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6560 | |
| mbed_official | 623:db79ecd649d0 | 6561 | /******************* Bit definition for LCD_CR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 6562 | #define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */ |
| mbed_official | 623:db79ecd649d0 | 6563 | #define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */ |
| mbed_official | 623:db79ecd649d0 | 6564 | |
| mbed_official | 623:db79ecd649d0 | 6565 | #define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */ |
| mbed_official | 623:db79ecd649d0 | 6566 | #define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6567 | #define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6568 | #define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6569 | |
| mbed_official | 623:db79ecd649d0 | 6570 | #define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */ |
| mbed_official | 623:db79ecd649d0 | 6571 | #define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6572 | #define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6573 | |
| mbed_official | 623:db79ecd649d0 | 6574 | #define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */ |
| mbed_official | 623:db79ecd649d0 | 6575 | #define LCD_CR_BUFEN ((uint32_t)0x00000100) /*!< Voltage output buffer enable */ |
| mbed_official | 623:db79ecd649d0 | 6576 | |
| mbed_official | 623:db79ecd649d0 | 6577 | /******************* Bit definition for LCD_FCR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 6578 | #define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */ |
| mbed_official | 623:db79ecd649d0 | 6579 | #define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */ |
| mbed_official | 623:db79ecd649d0 | 6580 | #define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */ |
| mbed_official | 623:db79ecd649d0 | 6581 | |
| mbed_official | 623:db79ecd649d0 | 6582 | #define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Pulse ON Duration) */ |
| mbed_official | 623:db79ecd649d0 | 6583 | #define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6584 | #define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6585 | #define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6586 | |
| mbed_official | 623:db79ecd649d0 | 6587 | #define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */ |
| mbed_official | 623:db79ecd649d0 | 6588 | #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6589 | #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6590 | #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6591 | |
| mbed_official | 623:db79ecd649d0 | 6592 | #define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */ |
| mbed_official | 623:db79ecd649d0 | 6593 | #define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6594 | #define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6595 | #define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6596 | |
| mbed_official | 623:db79ecd649d0 | 6597 | #define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */ |
| mbed_official | 623:db79ecd649d0 | 6598 | #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6599 | #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6600 | #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6601 | |
| mbed_official | 623:db79ecd649d0 | 6602 | #define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */ |
| mbed_official | 623:db79ecd649d0 | 6603 | #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6604 | #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6605 | |
| mbed_official | 623:db79ecd649d0 | 6606 | #define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */ |
| mbed_official | 623:db79ecd649d0 | 6607 | #define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 6608 | |
| mbed_official | 623:db79ecd649d0 | 6609 | /******************* Bit definition for LCD_SR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 6610 | #define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */ |
| mbed_official | 623:db79ecd649d0 | 6611 | #define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */ |
| mbed_official | 623:db79ecd649d0 | 6612 | #define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */ |
| mbed_official | 623:db79ecd649d0 | 6613 | #define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */ |
| mbed_official | 623:db79ecd649d0 | 6614 | #define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */ |
| mbed_official | 623:db79ecd649d0 | 6615 | #define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */ |
| mbed_official | 623:db79ecd649d0 | 6616 | |
| mbed_official | 623:db79ecd649d0 | 6617 | /******************* Bit definition for LCD_CLR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 6618 | #define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */ |
| mbed_official | 623:db79ecd649d0 | 6619 | #define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */ |
| mbed_official | 623:db79ecd649d0 | 6620 | |
| mbed_official | 623:db79ecd649d0 | 6621 | /******************* Bit definition for LCD_RAM register ********************/ |
| mbed_official | 623:db79ecd649d0 | 6622 | #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */ |
| mbed_official | 623:db79ecd649d0 | 6623 | |
| mbed_official | 623:db79ecd649d0 | 6624 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6625 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6626 | /* SDMMC Interface */ |
| mbed_official | 623:db79ecd649d0 | 6627 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6628 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6629 | /****************** Bit definition for SDMMC_POWER register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6630 | #define SDMMC_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */ |
| mbed_official | 623:db79ecd649d0 | 6631 | #define SDMMC_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6632 | #define SDMMC_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6633 | |
| mbed_official | 623:db79ecd649d0 | 6634 | /****************** Bit definition for SDMMC_CLKCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6635 | #define SDMMC_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */ |
| mbed_official | 623:db79ecd649d0 | 6636 | #define SDMMC_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */ |
| mbed_official | 623:db79ecd649d0 | 6637 | #define SDMMC_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */ |
| mbed_official | 623:db79ecd649d0 | 6638 | #define SDMMC_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */ |
| mbed_official | 623:db79ecd649d0 | 6639 | |
| mbed_official | 623:db79ecd649d0 | 6640 | #define SDMMC_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ |
| mbed_official | 623:db79ecd649d0 | 6641 | #define SDMMC_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6642 | #define SDMMC_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6643 | |
| mbed_official | 623:db79ecd649d0 | 6644 | #define SDMMC_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDMMC_CK dephasing selection bit */ |
| mbed_official | 623:db79ecd649d0 | 6645 | #define SDMMC_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */ |
| mbed_official | 623:db79ecd649d0 | 6646 | |
| mbed_official | 623:db79ecd649d0 | 6647 | /******************* Bit definition for SDMMC_ARG register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6648 | #define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */ |
| mbed_official | 623:db79ecd649d0 | 6649 | |
| mbed_official | 623:db79ecd649d0 | 6650 | /******************* Bit definition for SDMMC_CMD register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6651 | #define SDMMC_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */ |
| mbed_official | 623:db79ecd649d0 | 6652 | |
| mbed_official | 623:db79ecd649d0 | 6653 | #define SDMMC_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */ |
| mbed_official | 623:db79ecd649d0 | 6654 | #define SDMMC_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6655 | #define SDMMC_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6656 | |
| mbed_official | 623:db79ecd649d0 | 6657 | #define SDMMC_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */ |
| mbed_official | 623:db79ecd649d0 | 6658 | #define SDMMC_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ |
| mbed_official | 623:db79ecd649d0 | 6659 | #define SDMMC_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */ |
| mbed_official | 623:db79ecd649d0 | 6660 | #define SDMMC_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */ |
| mbed_official | 623:db79ecd649d0 | 6661 | |
| mbed_official | 623:db79ecd649d0 | 6662 | /***************** Bit definition for SDMMC_RESPCMD register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6663 | #define SDMMC_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */ |
| mbed_official | 623:db79ecd649d0 | 6664 | |
| mbed_official | 623:db79ecd649d0 | 6665 | /****************** Bit definition for SDMMC_RESP0 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6666 | #define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
| mbed_official | 623:db79ecd649d0 | 6667 | |
| mbed_official | 623:db79ecd649d0 | 6668 | /****************** Bit definition for SDMMC_RESP1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6669 | #define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
| mbed_official | 623:db79ecd649d0 | 6670 | |
| mbed_official | 623:db79ecd649d0 | 6671 | /****************** Bit definition for SDMMC_RESP2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6672 | #define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
| mbed_official | 623:db79ecd649d0 | 6673 | |
| mbed_official | 623:db79ecd649d0 | 6674 | /****************** Bit definition for SDMMC_RESP3 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6675 | #define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
| mbed_official | 623:db79ecd649d0 | 6676 | |
| mbed_official | 623:db79ecd649d0 | 6677 | /****************** Bit definition for SDMMC_RESP4 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6678 | #define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */ |
| mbed_official | 623:db79ecd649d0 | 6679 | |
| mbed_official | 623:db79ecd649d0 | 6680 | /****************** Bit definition for SDMMC_DTIMER register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6681 | #define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */ |
| mbed_official | 623:db79ecd649d0 | 6682 | |
| mbed_official | 623:db79ecd649d0 | 6683 | /****************** Bit definition for SDMMC_DLEN register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6684 | #define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */ |
| mbed_official | 623:db79ecd649d0 | 6685 | |
| mbed_official | 623:db79ecd649d0 | 6686 | /****************** Bit definition for SDMMC_DCTRL register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6687 | #define SDMMC_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */ |
| mbed_official | 623:db79ecd649d0 | 6688 | #define SDMMC_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */ |
| mbed_official | 623:db79ecd649d0 | 6689 | #define SDMMC_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */ |
| mbed_official | 623:db79ecd649d0 | 6690 | #define SDMMC_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */ |
| mbed_official | 623:db79ecd649d0 | 6691 | |
| mbed_official | 623:db79ecd649d0 | 6692 | #define SDMMC_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */ |
| mbed_official | 623:db79ecd649d0 | 6693 | #define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6694 | #define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6695 | #define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6696 | #define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6697 | |
| mbed_official | 623:db79ecd649d0 | 6698 | #define SDMMC_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */ |
| mbed_official | 623:db79ecd649d0 | 6699 | #define SDMMC_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */ |
| mbed_official | 623:db79ecd649d0 | 6700 | #define SDMMC_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */ |
| mbed_official | 623:db79ecd649d0 | 6701 | #define SDMMC_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */ |
| mbed_official | 623:db79ecd649d0 | 6702 | |
| mbed_official | 623:db79ecd649d0 | 6703 | /****************** Bit definition for SDMMC_DCOUNT register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6704 | #define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */ |
| mbed_official | 623:db79ecd649d0 | 6705 | |
| mbed_official | 623:db79ecd649d0 | 6706 | /****************** Bit definition for SDMMC_STA register ********************/ |
| mbed_official | 623:db79ecd649d0 | 6707 | #define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */ |
| mbed_official | 623:db79ecd649d0 | 6708 | #define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */ |
| mbed_official | 623:db79ecd649d0 | 6709 | #define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */ |
| mbed_official | 623:db79ecd649d0 | 6710 | #define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */ |
| mbed_official | 623:db79ecd649d0 | 6711 | #define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */ |
| mbed_official | 623:db79ecd649d0 | 6712 | #define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */ |
| mbed_official | 623:db79ecd649d0 | 6713 | #define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */ |
| mbed_official | 623:db79ecd649d0 | 6714 | #define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */ |
| mbed_official | 623:db79ecd649d0 | 6715 | #define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */ |
| mbed_official | 623:db79ecd649d0 | 6716 | #define SDMMC_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */ |
| mbed_official | 623:db79ecd649d0 | 6717 | #define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */ |
| mbed_official | 623:db79ecd649d0 | 6718 | #define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */ |
| mbed_official | 623:db79ecd649d0 | 6719 | #define SDMMC_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */ |
| mbed_official | 623:db79ecd649d0 | 6720 | #define SDMMC_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */ |
| mbed_official | 623:db79ecd649d0 | 6721 | #define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ |
| mbed_official | 623:db79ecd649d0 | 6722 | #define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ |
| mbed_official | 623:db79ecd649d0 | 6723 | #define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */ |
| mbed_official | 623:db79ecd649d0 | 6724 | #define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */ |
| mbed_official | 623:db79ecd649d0 | 6725 | #define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */ |
| mbed_official | 623:db79ecd649d0 | 6726 | #define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */ |
| mbed_official | 623:db79ecd649d0 | 6727 | #define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */ |
| mbed_official | 623:db79ecd649d0 | 6728 | #define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */ |
| mbed_official | 623:db79ecd649d0 | 6729 | #define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */ |
| mbed_official | 623:db79ecd649d0 | 6730 | |
| mbed_official | 623:db79ecd649d0 | 6731 | /******************* Bit definition for SDMMC_ICR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6732 | #define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6733 | #define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6734 | #define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6735 | #define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6736 | #define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6737 | #define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6738 | #define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6739 | #define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6740 | #define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6741 | #define SDMMC_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6742 | #define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6743 | #define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */ |
| mbed_official | 623:db79ecd649d0 | 6744 | |
| mbed_official | 623:db79ecd649d0 | 6745 | /****************** Bit definition for SDMMC_MASK register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6746 | #define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6747 | #define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6748 | #define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6749 | #define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6750 | #define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6751 | #define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6752 | #define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6753 | #define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6754 | #define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6755 | #define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6756 | #define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6757 | #define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6758 | #define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */ |
| mbed_official | 623:db79ecd649d0 | 6759 | #define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6760 | #define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6761 | #define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6762 | #define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6763 | #define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6764 | #define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6765 | #define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6766 | #define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6767 | #define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6768 | |
| mbed_official | 623:db79ecd649d0 | 6769 | /***************** Bit definition for SDMMC_FIFOCNT register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6770 | #define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */ |
| mbed_official | 623:db79ecd649d0 | 6771 | |
| mbed_official | 623:db79ecd649d0 | 6772 | /****************** Bit definition for SDMMC_FIFO register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6773 | #define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */ |
| mbed_official | 623:db79ecd649d0 | 6774 | |
| mbed_official | 623:db79ecd649d0 | 6775 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6776 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6777 | /* Serial Peripheral Interface (SPI) */ |
| mbed_official | 623:db79ecd649d0 | 6778 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6779 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6780 | /******************* Bit definition for SPI_CR1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 6781 | #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!<Clock Phase */ |
| mbed_official | 623:db79ecd649d0 | 6782 | #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!<Clock Polarity */ |
| mbed_official | 623:db79ecd649d0 | 6783 | #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!<Master Selection */ |
| mbed_official | 623:db79ecd649d0 | 6784 | |
| mbed_official | 623:db79ecd649d0 | 6785 | #define SPI_CR1_BR ((uint32_t)0x00000038) /*!<BR[2:0] bits (Baud Rate Control) */ |
| mbed_official | 623:db79ecd649d0 | 6786 | #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6787 | #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6788 | #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6789 | |
| mbed_official | 623:db79ecd649d0 | 6790 | #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!<SPI Enable */ |
| mbed_official | 623:db79ecd649d0 | 6791 | #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!<Frame Format */ |
| mbed_official | 623:db79ecd649d0 | 6792 | #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!<Internal slave select */ |
| mbed_official | 623:db79ecd649d0 | 6793 | #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!<Software slave management */ |
| mbed_official | 623:db79ecd649d0 | 6794 | #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!<Receive only */ |
| mbed_official | 623:db79ecd649d0 | 6795 | #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */ |
| mbed_official | 623:db79ecd649d0 | 6796 | #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!<Transmit CRC next */ |
| mbed_official | 623:db79ecd649d0 | 6797 | #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!<Hardware CRC calculation enable */ |
| mbed_official | 623:db79ecd649d0 | 6798 | #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!<Output enable in bidirectional mode */ |
| mbed_official | 623:db79ecd649d0 | 6799 | #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!<Bidirectional data mode enable */ |
| mbed_official | 623:db79ecd649d0 | 6800 | |
| mbed_official | 623:db79ecd649d0 | 6801 | /******************* Bit definition for SPI_CR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 6802 | #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */ |
| mbed_official | 623:db79ecd649d0 | 6803 | #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */ |
| mbed_official | 623:db79ecd649d0 | 6804 | #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */ |
| mbed_official | 623:db79ecd649d0 | 6805 | #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */ |
| mbed_official | 623:db79ecd649d0 | 6806 | #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */ |
| mbed_official | 623:db79ecd649d0 | 6807 | #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6808 | #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6809 | #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6810 | #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */ |
| mbed_official | 623:db79ecd649d0 | 6811 | #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6812 | #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6813 | #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6814 | #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6815 | #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */ |
| mbed_official | 623:db79ecd649d0 | 6816 | #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */ |
| mbed_official | 623:db79ecd649d0 | 6817 | #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */ |
| mbed_official | 623:db79ecd649d0 | 6818 | |
| mbed_official | 623:db79ecd649d0 | 6819 | /******************** Bit definition for SPI_SR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 6820 | #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */ |
| mbed_official | 623:db79ecd649d0 | 6821 | #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */ |
| mbed_official | 623:db79ecd649d0 | 6822 | #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */ |
| mbed_official | 623:db79ecd649d0 | 6823 | #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */ |
| mbed_official | 623:db79ecd649d0 | 6824 | #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */ |
| mbed_official | 623:db79ecd649d0 | 6825 | #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */ |
| mbed_official | 623:db79ecd649d0 | 6826 | #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */ |
| mbed_official | 623:db79ecd649d0 | 6827 | #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */ |
| mbed_official | 623:db79ecd649d0 | 6828 | #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */ |
| mbed_official | 623:db79ecd649d0 | 6829 | #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */ |
| mbed_official | 623:db79ecd649d0 | 6830 | #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6831 | #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6832 | #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */ |
| mbed_official | 623:db79ecd649d0 | 6833 | #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6834 | #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6835 | |
| mbed_official | 623:db79ecd649d0 | 6836 | /******************** Bit definition for SPI_DR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 6837 | #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!<Data Register */ |
| mbed_official | 623:db79ecd649d0 | 6838 | |
| mbed_official | 623:db79ecd649d0 | 6839 | /******************* Bit definition for SPI_CRCPR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6840 | #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!<CRC polynomial register */ |
| mbed_official | 623:db79ecd649d0 | 6841 | |
| mbed_official | 623:db79ecd649d0 | 6842 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6843 | #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!<Rx CRC Register */ |
| mbed_official | 623:db79ecd649d0 | 6844 | |
| mbed_official | 623:db79ecd649d0 | 6845 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6846 | #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!<Tx CRC Register */ |
| mbed_official | 623:db79ecd649d0 | 6847 | |
| mbed_official | 623:db79ecd649d0 | 6848 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6849 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6850 | /* QUADSPI */ |
| mbed_official | 623:db79ecd649d0 | 6851 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6852 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6853 | /***************** Bit definition for QUADSPI_CR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6854 | #define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */ |
| mbed_official | 623:db79ecd649d0 | 6855 | #define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */ |
| mbed_official | 623:db79ecd649d0 | 6856 | #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */ |
| mbed_official | 623:db79ecd649d0 | 6857 | #define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */ |
| mbed_official | 623:db79ecd649d0 | 6858 | #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< Sample Shift */ |
| mbed_official | 623:db79ecd649d0 | 6859 | #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */ |
| mbed_official | 623:db79ecd649d0 | 6860 | #define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6861 | #define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6862 | #define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6863 | #define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6864 | #define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6865 | #define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6866 | #define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6867 | #define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6868 | #define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 6869 | #define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Automatic Polling Mode Stop */ |
| mbed_official | 623:db79ecd649d0 | 6870 | #define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */ |
| mbed_official | 623:db79ecd649d0 | 6871 | #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */ |
| mbed_official | 623:db79ecd649d0 | 6872 | #define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6873 | #define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6874 | #define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6875 | #define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6876 | #define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 6877 | #define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 6878 | #define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 6879 | #define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 6880 | |
| mbed_official | 623:db79ecd649d0 | 6881 | /***************** Bit definition for QUADSPI_DCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6882 | #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */ |
| mbed_official | 623:db79ecd649d0 | 6883 | #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */ |
| mbed_official | 623:db79ecd649d0 | 6884 | #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6885 | #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6886 | #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6887 | #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */ |
| mbed_official | 623:db79ecd649d0 | 6888 | #define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6889 | #define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6890 | #define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6891 | #define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6892 | #define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 6893 | |
| mbed_official | 623:db79ecd649d0 | 6894 | /****************** Bit definition for QUADSPI_SR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6895 | #define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */ |
| mbed_official | 623:db79ecd649d0 | 6896 | #define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */ |
| mbed_official | 623:db79ecd649d0 | 6897 | #define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */ |
| mbed_official | 623:db79ecd649d0 | 6898 | #define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */ |
| mbed_official | 623:db79ecd649d0 | 6899 | #define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */ |
| mbed_official | 623:db79ecd649d0 | 6900 | #define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */ |
| mbed_official | 623:db79ecd649d0 | 6901 | #define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /*!< FIFO Threshlod Flag */ |
| mbed_official | 623:db79ecd649d0 | 6902 | #define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6903 | #define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6904 | #define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6905 | #define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6906 | #define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 6907 | |
| mbed_official | 623:db79ecd649d0 | 6908 | /****************** Bit definition for QUADSPI_FCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6909 | #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */ |
| mbed_official | 623:db79ecd649d0 | 6910 | #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */ |
| mbed_official | 623:db79ecd649d0 | 6911 | #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */ |
| mbed_official | 623:db79ecd649d0 | 6912 | #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */ |
| mbed_official | 623:db79ecd649d0 | 6913 | |
| mbed_official | 623:db79ecd649d0 | 6914 | /****************** Bit definition for QUADSPI_DLR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6915 | #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */ |
| mbed_official | 623:db79ecd649d0 | 6916 | |
| mbed_official | 623:db79ecd649d0 | 6917 | /****************** Bit definition for QUADSPI_CCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6918 | #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */ |
| mbed_official | 623:db79ecd649d0 | 6919 | #define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6920 | #define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6921 | #define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6922 | #define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6923 | #define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 6924 | #define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 6925 | #define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 6926 | #define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 6927 | #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */ |
| mbed_official | 623:db79ecd649d0 | 6928 | #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6929 | #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6930 | #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */ |
| mbed_official | 623:db79ecd649d0 | 6931 | #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6932 | #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6933 | #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */ |
| mbed_official | 623:db79ecd649d0 | 6934 | #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6935 | #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6936 | #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */ |
| mbed_official | 623:db79ecd649d0 | 6937 | #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6938 | #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6939 | #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */ |
| mbed_official | 623:db79ecd649d0 | 6940 | #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6941 | #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6942 | #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */ |
| mbed_official | 623:db79ecd649d0 | 6943 | #define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6944 | #define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6945 | #define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 6946 | #define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 6947 | #define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 6948 | #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */ |
| mbed_official | 623:db79ecd649d0 | 6949 | #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6950 | #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6951 | #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */ |
| mbed_official | 623:db79ecd649d0 | 6952 | #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 6953 | #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 6954 | #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */ |
| mbed_official | 623:db79ecd649d0 | 6955 | #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */ |
| mbed_official | 623:db79ecd649d0 | 6956 | |
| mbed_official | 623:db79ecd649d0 | 6957 | /****************** Bit definition for QUADSPI_AR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6958 | #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */ |
| mbed_official | 623:db79ecd649d0 | 6959 | |
| mbed_official | 623:db79ecd649d0 | 6960 | /****************** Bit definition for QUADSPI_ABR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6961 | #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */ |
| mbed_official | 623:db79ecd649d0 | 6962 | |
| mbed_official | 623:db79ecd649d0 | 6963 | /****************** Bit definition for QUADSPI_DR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 6964 | #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */ |
| mbed_official | 623:db79ecd649d0 | 6965 | |
| mbed_official | 623:db79ecd649d0 | 6966 | /****************** Bit definition for QUADSPI_PSMKR register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6967 | #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */ |
| mbed_official | 623:db79ecd649d0 | 6968 | |
| mbed_official | 623:db79ecd649d0 | 6969 | /****************** Bit definition for QUADSPI_PSMAR register ****************/ |
| mbed_official | 623:db79ecd649d0 | 6970 | #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */ |
| mbed_official | 623:db79ecd649d0 | 6971 | |
| mbed_official | 623:db79ecd649d0 | 6972 | /****************** Bit definition for QUADSPI_PIR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6973 | #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */ |
| mbed_official | 623:db79ecd649d0 | 6974 | |
| mbed_official | 623:db79ecd649d0 | 6975 | /****************** Bit definition for QUADSPI_LPTR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 6976 | #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */ |
| mbed_official | 623:db79ecd649d0 | 6977 | |
| mbed_official | 623:db79ecd649d0 | 6978 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6979 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6980 | /* SYSCFG */ |
| mbed_official | 623:db79ecd649d0 | 6981 | /* */ |
| mbed_official | 623:db79ecd649d0 | 6982 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 6983 | /****************** Bit definition for SYSCFG_MEMRMP register ***************/ |
| mbed_official | 623:db79ecd649d0 | 6984 | #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */ |
| mbed_official | 623:db79ecd649d0 | 6985 | #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 6986 | #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 6987 | #define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 6988 | |
| mbed_official | 623:db79ecd649d0 | 6989 | #define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100) /*!< Flash Bank mode selection */ |
| mbed_official | 623:db79ecd649d0 | 6990 | |
| mbed_official | 623:db79ecd649d0 | 6991 | |
| mbed_official | 623:db79ecd649d0 | 6992 | /****************** Bit definition for SYSCFG_CFGR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 6993 | #define SYSCFG_CFGR1_FWDIS ((uint32_t)0x00000001) /*!< FIREWALL access enable*/ |
| mbed_official | 623:db79ecd649d0 | 6994 | #define SYSCFG_CFGR1_BOOSTEN ((uint32_t)0x00000100) /*!< I/O analog switch voltage booster enable */ |
| mbed_official | 623:db79ecd649d0 | 6995 | #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */ |
| mbed_official | 623:db79ecd649d0 | 6996 | #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */ |
| mbed_official | 623:db79ecd649d0 | 6997 | #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */ |
| mbed_official | 623:db79ecd649d0 | 6998 | #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */ |
| mbed_official | 623:db79ecd649d0 | 6999 | #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */ |
| mbed_official | 623:db79ecd649d0 | 7000 | #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */ |
| mbed_official | 623:db79ecd649d0 | 7001 | #define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x00400000) /*!< I2C3 Fast mode plus */ |
| mbed_official | 623:db79ecd649d0 | 7002 | #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Invalid operation Interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7003 | #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Divide-by-zero Interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7004 | #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Underflow Interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7005 | #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Overflow Interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7006 | #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Input denormal Interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7007 | #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Inexact Interrupt enable (interrupt disabled at reset) */ |
| mbed_official | 623:db79ecd649d0 | 7008 | |
| mbed_official | 623:db79ecd649d0 | 7009 | /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ |
| mbed_official | 623:db79ecd649d0 | 7010 | #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x00000007) /*!<EXTI 0 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7011 | #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00000070) /*!<EXTI 1 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7012 | #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000700) /*!<EXTI 2 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7013 | #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x00007000) /*!<EXTI 3 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7014 | /** |
| mbed_official | 623:db79ecd649d0 | 7015 | * @brief EXTI0 configuration |
| mbed_official | 623:db79ecd649d0 | 7016 | */ |
| mbed_official | 623:db79ecd649d0 | 7017 | #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */ |
| mbed_official | 623:db79ecd649d0 | 7018 | #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */ |
| mbed_official | 623:db79ecd649d0 | 7019 | #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */ |
| mbed_official | 623:db79ecd649d0 | 7020 | #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */ |
| mbed_official | 623:db79ecd649d0 | 7021 | #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */ |
| mbed_official | 623:db79ecd649d0 | 7022 | #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */ |
| mbed_official | 623:db79ecd649d0 | 7023 | #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */ |
| mbed_official | 623:db79ecd649d0 | 7024 | #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */ |
| mbed_official | 623:db79ecd649d0 | 7025 | |
| mbed_official | 623:db79ecd649d0 | 7026 | |
| mbed_official | 623:db79ecd649d0 | 7027 | /** |
| mbed_official | 623:db79ecd649d0 | 7028 | * @brief EXTI1 configuration |
| mbed_official | 623:db79ecd649d0 | 7029 | */ |
| mbed_official | 623:db79ecd649d0 | 7030 | #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */ |
| mbed_official | 623:db79ecd649d0 | 7031 | #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */ |
| mbed_official | 623:db79ecd649d0 | 7032 | #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */ |
| mbed_official | 623:db79ecd649d0 | 7033 | #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */ |
| mbed_official | 623:db79ecd649d0 | 7034 | #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */ |
| mbed_official | 623:db79ecd649d0 | 7035 | #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */ |
| mbed_official | 623:db79ecd649d0 | 7036 | #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */ |
| mbed_official | 623:db79ecd649d0 | 7037 | #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */ |
| mbed_official | 623:db79ecd649d0 | 7038 | |
| mbed_official | 623:db79ecd649d0 | 7039 | /** |
| mbed_official | 623:db79ecd649d0 | 7040 | * @brief EXTI2 configuration |
| mbed_official | 623:db79ecd649d0 | 7041 | */ |
| mbed_official | 623:db79ecd649d0 | 7042 | #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */ |
| mbed_official | 623:db79ecd649d0 | 7043 | #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */ |
| mbed_official | 623:db79ecd649d0 | 7044 | #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */ |
| mbed_official | 623:db79ecd649d0 | 7045 | #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */ |
| mbed_official | 623:db79ecd649d0 | 7046 | #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */ |
| mbed_official | 623:db79ecd649d0 | 7047 | #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */ |
| mbed_official | 623:db79ecd649d0 | 7048 | #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */ |
| mbed_official | 623:db79ecd649d0 | 7049 | |
| mbed_official | 623:db79ecd649d0 | 7050 | |
| mbed_official | 623:db79ecd649d0 | 7051 | /** |
| mbed_official | 623:db79ecd649d0 | 7052 | * @brief EXTI3 configuration |
| mbed_official | 623:db79ecd649d0 | 7053 | */ |
| mbed_official | 623:db79ecd649d0 | 7054 | #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */ |
| mbed_official | 623:db79ecd649d0 | 7055 | #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */ |
| mbed_official | 623:db79ecd649d0 | 7056 | #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */ |
| mbed_official | 623:db79ecd649d0 | 7057 | #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */ |
| mbed_official | 623:db79ecd649d0 | 7058 | #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */ |
| mbed_official | 623:db79ecd649d0 | 7059 | #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */ |
| mbed_official | 623:db79ecd649d0 | 7060 | #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */ |
| mbed_official | 623:db79ecd649d0 | 7061 | |
| mbed_official | 623:db79ecd649d0 | 7062 | |
| mbed_official | 623:db79ecd649d0 | 7063 | /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ |
| mbed_official | 623:db79ecd649d0 | 7064 | #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x00000007) /*!<EXTI 4 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7065 | #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00000070) /*!<EXTI 5 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7066 | #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000700) /*!<EXTI 6 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7067 | #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x00007000) /*!<EXTI 7 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7068 | /** |
| mbed_official | 623:db79ecd649d0 | 7069 | * @brief EXTI4 configuration |
| mbed_official | 623:db79ecd649d0 | 7070 | */ |
| mbed_official | 623:db79ecd649d0 | 7071 | #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */ |
| mbed_official | 623:db79ecd649d0 | 7072 | #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */ |
| mbed_official | 623:db79ecd649d0 | 7073 | #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */ |
| mbed_official | 623:db79ecd649d0 | 7074 | #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */ |
| mbed_official | 623:db79ecd649d0 | 7075 | #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */ |
| mbed_official | 623:db79ecd649d0 | 7076 | #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */ |
| mbed_official | 623:db79ecd649d0 | 7077 | #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */ |
| mbed_official | 623:db79ecd649d0 | 7078 | |
| mbed_official | 623:db79ecd649d0 | 7079 | /** |
| mbed_official | 623:db79ecd649d0 | 7080 | * @brief EXTI5 configuration |
| mbed_official | 623:db79ecd649d0 | 7081 | */ |
| mbed_official | 623:db79ecd649d0 | 7082 | #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */ |
| mbed_official | 623:db79ecd649d0 | 7083 | #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */ |
| mbed_official | 623:db79ecd649d0 | 7084 | #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */ |
| mbed_official | 623:db79ecd649d0 | 7085 | #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */ |
| mbed_official | 623:db79ecd649d0 | 7086 | #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */ |
| mbed_official | 623:db79ecd649d0 | 7087 | #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */ |
| mbed_official | 623:db79ecd649d0 | 7088 | #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */ |
| mbed_official | 623:db79ecd649d0 | 7089 | |
| mbed_official | 623:db79ecd649d0 | 7090 | /** |
| mbed_official | 623:db79ecd649d0 | 7091 | * @brief EXTI6 configuration |
| mbed_official | 623:db79ecd649d0 | 7092 | */ |
| mbed_official | 623:db79ecd649d0 | 7093 | #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */ |
| mbed_official | 623:db79ecd649d0 | 7094 | #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */ |
| mbed_official | 623:db79ecd649d0 | 7095 | #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */ |
| mbed_official | 623:db79ecd649d0 | 7096 | #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */ |
| mbed_official | 623:db79ecd649d0 | 7097 | #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */ |
| mbed_official | 623:db79ecd649d0 | 7098 | #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */ |
| mbed_official | 623:db79ecd649d0 | 7099 | #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */ |
| mbed_official | 623:db79ecd649d0 | 7100 | |
| mbed_official | 623:db79ecd649d0 | 7101 | /** |
| mbed_official | 623:db79ecd649d0 | 7102 | * @brief EXTI7 configuration |
| mbed_official | 623:db79ecd649d0 | 7103 | */ |
| mbed_official | 623:db79ecd649d0 | 7104 | #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */ |
| mbed_official | 623:db79ecd649d0 | 7105 | #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */ |
| mbed_official | 623:db79ecd649d0 | 7106 | #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */ |
| mbed_official | 623:db79ecd649d0 | 7107 | #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */ |
| mbed_official | 623:db79ecd649d0 | 7108 | #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */ |
| mbed_official | 623:db79ecd649d0 | 7109 | #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */ |
| mbed_official | 623:db79ecd649d0 | 7110 | #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */ |
| mbed_official | 623:db79ecd649d0 | 7111 | |
| mbed_official | 623:db79ecd649d0 | 7112 | |
| mbed_official | 623:db79ecd649d0 | 7113 | /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ |
| mbed_official | 623:db79ecd649d0 | 7114 | #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x00000007) /*!<EXTI 8 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7115 | #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00000070) /*!<EXTI 9 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7116 | #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000700) /*!<EXTI 10 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7117 | #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x00007000) /*!<EXTI 11 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7118 | |
| mbed_official | 623:db79ecd649d0 | 7119 | /** |
| mbed_official | 623:db79ecd649d0 | 7120 | * @brief EXTI8 configuration |
| mbed_official | 623:db79ecd649d0 | 7121 | */ |
| mbed_official | 623:db79ecd649d0 | 7122 | #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */ |
| mbed_official | 623:db79ecd649d0 | 7123 | #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */ |
| mbed_official | 623:db79ecd649d0 | 7124 | #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */ |
| mbed_official | 623:db79ecd649d0 | 7125 | #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */ |
| mbed_official | 623:db79ecd649d0 | 7126 | #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */ |
| mbed_official | 623:db79ecd649d0 | 7127 | #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */ |
| mbed_official | 623:db79ecd649d0 | 7128 | #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */ |
| mbed_official | 623:db79ecd649d0 | 7129 | |
| mbed_official | 623:db79ecd649d0 | 7130 | /** |
| mbed_official | 623:db79ecd649d0 | 7131 | * @brief EXTI9 configuration |
| mbed_official | 623:db79ecd649d0 | 7132 | */ |
| mbed_official | 623:db79ecd649d0 | 7133 | #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */ |
| mbed_official | 623:db79ecd649d0 | 7134 | #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */ |
| mbed_official | 623:db79ecd649d0 | 7135 | #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */ |
| mbed_official | 623:db79ecd649d0 | 7136 | #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */ |
| mbed_official | 623:db79ecd649d0 | 7137 | #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */ |
| mbed_official | 623:db79ecd649d0 | 7138 | #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */ |
| mbed_official | 623:db79ecd649d0 | 7139 | #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */ |
| mbed_official | 623:db79ecd649d0 | 7140 | |
| mbed_official | 623:db79ecd649d0 | 7141 | /** |
| mbed_official | 623:db79ecd649d0 | 7142 | * @brief EXTI10 configuration |
| mbed_official | 623:db79ecd649d0 | 7143 | */ |
| mbed_official | 623:db79ecd649d0 | 7144 | #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */ |
| mbed_official | 623:db79ecd649d0 | 7145 | #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */ |
| mbed_official | 623:db79ecd649d0 | 7146 | #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */ |
| mbed_official | 623:db79ecd649d0 | 7147 | #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */ |
| mbed_official | 623:db79ecd649d0 | 7148 | #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */ |
| mbed_official | 623:db79ecd649d0 | 7149 | #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */ |
| mbed_official | 623:db79ecd649d0 | 7150 | #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */ |
| mbed_official | 623:db79ecd649d0 | 7151 | |
| mbed_official | 623:db79ecd649d0 | 7152 | /** |
| mbed_official | 623:db79ecd649d0 | 7153 | * @brief EXTI11 configuration |
| mbed_official | 623:db79ecd649d0 | 7154 | */ |
| mbed_official | 623:db79ecd649d0 | 7155 | #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */ |
| mbed_official | 623:db79ecd649d0 | 7156 | #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */ |
| mbed_official | 623:db79ecd649d0 | 7157 | #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */ |
| mbed_official | 623:db79ecd649d0 | 7158 | #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */ |
| mbed_official | 623:db79ecd649d0 | 7159 | #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */ |
| mbed_official | 623:db79ecd649d0 | 7160 | #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */ |
| mbed_official | 623:db79ecd649d0 | 7161 | #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */ |
| mbed_official | 623:db79ecd649d0 | 7162 | |
| mbed_official | 623:db79ecd649d0 | 7163 | /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ |
| mbed_official | 623:db79ecd649d0 | 7164 | #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x00000007) /*!<EXTI 12 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7165 | #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00000070) /*!<EXTI 13 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7166 | #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000700) /*!<EXTI 14 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7167 | #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x00007000) /*!<EXTI 15 configuration */ |
| mbed_official | 623:db79ecd649d0 | 7168 | /** |
| mbed_official | 623:db79ecd649d0 | 7169 | * @brief EXTI12 configuration |
| mbed_official | 623:db79ecd649d0 | 7170 | */ |
| mbed_official | 623:db79ecd649d0 | 7171 | #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */ |
| mbed_official | 623:db79ecd649d0 | 7172 | #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */ |
| mbed_official | 623:db79ecd649d0 | 7173 | #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */ |
| mbed_official | 623:db79ecd649d0 | 7174 | #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */ |
| mbed_official | 623:db79ecd649d0 | 7175 | #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */ |
| mbed_official | 623:db79ecd649d0 | 7176 | #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */ |
| mbed_official | 623:db79ecd649d0 | 7177 | #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */ |
| mbed_official | 623:db79ecd649d0 | 7178 | |
| mbed_official | 623:db79ecd649d0 | 7179 | /** |
| mbed_official | 623:db79ecd649d0 | 7180 | * @brief EXTI13 configuration |
| mbed_official | 623:db79ecd649d0 | 7181 | */ |
| mbed_official | 623:db79ecd649d0 | 7182 | #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */ |
| mbed_official | 623:db79ecd649d0 | 7183 | #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */ |
| mbed_official | 623:db79ecd649d0 | 7184 | #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */ |
| mbed_official | 623:db79ecd649d0 | 7185 | #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */ |
| mbed_official | 623:db79ecd649d0 | 7186 | #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */ |
| mbed_official | 623:db79ecd649d0 | 7187 | #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */ |
| mbed_official | 623:db79ecd649d0 | 7188 | #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */ |
| mbed_official | 623:db79ecd649d0 | 7189 | |
| mbed_official | 623:db79ecd649d0 | 7190 | /** |
| mbed_official | 623:db79ecd649d0 | 7191 | * @brief EXTI14 configuration |
| mbed_official | 623:db79ecd649d0 | 7192 | */ |
| mbed_official | 623:db79ecd649d0 | 7193 | #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */ |
| mbed_official | 623:db79ecd649d0 | 7194 | #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */ |
| mbed_official | 623:db79ecd649d0 | 7195 | #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */ |
| mbed_official | 623:db79ecd649d0 | 7196 | #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */ |
| mbed_official | 623:db79ecd649d0 | 7197 | #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */ |
| mbed_official | 623:db79ecd649d0 | 7198 | #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */ |
| mbed_official | 623:db79ecd649d0 | 7199 | #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */ |
| mbed_official | 623:db79ecd649d0 | 7200 | |
| mbed_official | 623:db79ecd649d0 | 7201 | /** |
| mbed_official | 623:db79ecd649d0 | 7202 | * @brief EXTI15 configuration |
| mbed_official | 623:db79ecd649d0 | 7203 | */ |
| mbed_official | 623:db79ecd649d0 | 7204 | #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */ |
| mbed_official | 623:db79ecd649d0 | 7205 | #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */ |
| mbed_official | 623:db79ecd649d0 | 7206 | #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */ |
| mbed_official | 623:db79ecd649d0 | 7207 | #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */ |
| mbed_official | 623:db79ecd649d0 | 7208 | #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */ |
| mbed_official | 623:db79ecd649d0 | 7209 | #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */ |
| mbed_official | 623:db79ecd649d0 | 7210 | #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */ |
| mbed_official | 623:db79ecd649d0 | 7211 | |
| mbed_official | 623:db79ecd649d0 | 7212 | /****************** Bit definition for SYSCFG_SCSR register ****************/ |
| mbed_official | 623:db79ecd649d0 | 7213 | #define SYSCFG_SCSR_SRAM2ER ((uint32_t)0x00000001) /*!< SRAM2 Erase Request */ |
| mbed_official | 623:db79ecd649d0 | 7214 | #define SYSCFG_SCSR_SRAM2BSY ((uint32_t)0x00000002) /*!< SRAM2 Erase Ongoing */ |
| mbed_official | 623:db79ecd649d0 | 7215 | |
| mbed_official | 623:db79ecd649d0 | 7216 | /****************** Bit definition for SYSCFG_CFGR2 register ****************/ |
| mbed_official | 623:db79ecd649d0 | 7217 | #define SYSCFG_CFGR2_CLL ((uint32_t)0x00000001) /*!< Core Lockup Lock */ |
| mbed_official | 623:db79ecd649d0 | 7218 | #define SYSCFG_CFGR2_SPL ((uint32_t)0x00000002) /*!< SRAM Parity Lock*/ |
| mbed_official | 623:db79ecd649d0 | 7219 | #define SYSCFG_CFGR2_PVDL ((uint32_t)0x00000004) /*!< PVD Lock */ |
| mbed_official | 623:db79ecd649d0 | 7220 | #define SYSCFG_CFGR2_ECCL ((uint32_t)0x00000008) /*!< ECC Lock*/ |
| mbed_official | 623:db79ecd649d0 | 7221 | #define SYSCFG_CFGR2_SPF ((uint32_t)0x00000100) /*!< SRAM Parity Flag */ |
| mbed_official | 623:db79ecd649d0 | 7222 | |
| mbed_official | 623:db79ecd649d0 | 7223 | /****************** Bit definition for SYSCFG_SWPR register ****************/ |
| mbed_official | 623:db79ecd649d0 | 7224 | #define SYSCFG_SWPR_PAGE0 ((uint32_t)0x00000001) /*!< SRAM2 Write protection page 0 */ |
| mbed_official | 623:db79ecd649d0 | 7225 | #define SYSCFG_SWPR_PAGE1 ((uint32_t)0x00000002) /*!< SRAM2 Write protection page 1 */ |
| mbed_official | 623:db79ecd649d0 | 7226 | #define SYSCFG_SWPR_PAGE2 ((uint32_t)0x00000004) /*!< SRAM2 Write protection page 2 */ |
| mbed_official | 623:db79ecd649d0 | 7227 | #define SYSCFG_SWPR_PAGE3 ((uint32_t)0x00000008) /*!< SRAM2 Write protection page 3 */ |
| mbed_official | 623:db79ecd649d0 | 7228 | #define SYSCFG_SWPR_PAGE4 ((uint32_t)0x00000010) /*!< SRAM2 Write protection page 4 */ |
| mbed_official | 623:db79ecd649d0 | 7229 | #define SYSCFG_SWPR_PAGE5 ((uint32_t)0x00000020) /*!< SRAM2 Write protection page 5 */ |
| mbed_official | 623:db79ecd649d0 | 7230 | #define SYSCFG_SWPR_PAGE6 ((uint32_t)0x00000040) /*!< SRAM2 Write protection page 6 */ |
| mbed_official | 623:db79ecd649d0 | 7231 | #define SYSCFG_SWPR_PAGE7 ((uint32_t)0x00000080) /*!< SRAM2 Write protection page 7 */ |
| mbed_official | 623:db79ecd649d0 | 7232 | #define SYSCFG_SWPR_PAGE8 ((uint32_t)0x00000100) /*!< SRAM2 Write protection page 8 */ |
| mbed_official | 623:db79ecd649d0 | 7233 | #define SYSCFG_SWPR_PAGE9 ((uint32_t)0x00000200) /*!< SRAM2 Write protection page 9 */ |
| mbed_official | 623:db79ecd649d0 | 7234 | #define SYSCFG_SWPR_PAGE10 ((uint32_t)0x00000400) /*!< SRAM2 Write protection page 10*/ |
| mbed_official | 623:db79ecd649d0 | 7235 | #define SYSCFG_SWPR_PAGE11 ((uint32_t)0x00000800) /*!< SRAM2 Write protection page 11*/ |
| mbed_official | 623:db79ecd649d0 | 7236 | #define SYSCFG_SWPR_PAGE12 ((uint32_t)0x00001000) /*!< SRAM2 Write protection page 12*/ |
| mbed_official | 623:db79ecd649d0 | 7237 | #define SYSCFG_SWPR_PAGE13 ((uint32_t)0x00002000) /*!< SRAM2 Write protection page 13*/ |
| mbed_official | 623:db79ecd649d0 | 7238 | #define SYSCFG_SWPR_PAGE14 ((uint32_t)0x00004000) /*!< SRAM2 Write protection page 14*/ |
| mbed_official | 623:db79ecd649d0 | 7239 | #define SYSCFG_SWPR_PAGE15 ((uint32_t)0x00008000) /*!< SRAM2 Write protection page 15*/ |
| mbed_official | 623:db79ecd649d0 | 7240 | #define SYSCFG_SWPR_PAGE16 ((uint32_t)0x00010000) /*!< SRAM2 Write protection page 16*/ |
| mbed_official | 623:db79ecd649d0 | 7241 | #define SYSCFG_SWPR_PAGE17 ((uint32_t)0x00020000) /*!< SRAM2 Write protection page 17*/ |
| mbed_official | 623:db79ecd649d0 | 7242 | #define SYSCFG_SWPR_PAGE18 ((uint32_t)0x00040000) /*!< SRAM2 Write protection page 18*/ |
| mbed_official | 623:db79ecd649d0 | 7243 | #define SYSCFG_SWPR_PAGE19 ((uint32_t)0x00080000) /*!< SRAM2 Write protection page 19*/ |
| mbed_official | 623:db79ecd649d0 | 7244 | #define SYSCFG_SWPR_PAGE20 ((uint32_t)0x00100000) /*!< SRAM2 Write protection page 20*/ |
| mbed_official | 623:db79ecd649d0 | 7245 | #define SYSCFG_SWPR_PAGE21 ((uint32_t)0x00200000) /*!< SRAM2 Write protection page 21*/ |
| mbed_official | 623:db79ecd649d0 | 7246 | #define SYSCFG_SWPR_PAGE22 ((uint32_t)0x00400000) /*!< SRAM2 Write protection page 22*/ |
| mbed_official | 623:db79ecd649d0 | 7247 | #define SYSCFG_SWPR_PAGE23 ((uint32_t)0x00800000) /*!< SRAM2 Write protection page 23*/ |
| mbed_official | 623:db79ecd649d0 | 7248 | #define SYSCFG_SWPR_PAGE24 ((uint32_t)0x01000000) /*!< SRAM2 Write protection page 24*/ |
| mbed_official | 623:db79ecd649d0 | 7249 | #define SYSCFG_SWPR_PAGE25 ((uint32_t)0x02000000) /*!< SRAM2 Write protection page 25*/ |
| mbed_official | 623:db79ecd649d0 | 7250 | #define SYSCFG_SWPR_PAGE26 ((uint32_t)0x04000000) /*!< SRAM2 Write protection page 26*/ |
| mbed_official | 623:db79ecd649d0 | 7251 | #define SYSCFG_SWPR_PAGE27 ((uint32_t)0x08000000) /*!< SRAM2 Write protection page 27*/ |
| mbed_official | 623:db79ecd649d0 | 7252 | #define SYSCFG_SWPR_PAGE28 ((uint32_t)0x10000000) /*!< SRAM2 Write protection page 28*/ |
| mbed_official | 623:db79ecd649d0 | 7253 | #define SYSCFG_SWPR_PAGE29 ((uint32_t)0x20000000) /*!< SRAM2 Write protection page 29*/ |
| mbed_official | 623:db79ecd649d0 | 7254 | #define SYSCFG_SWPR_PAGE30 ((uint32_t)0x40000000) /*!< SRAM2 Write protection page 30*/ |
| mbed_official | 623:db79ecd649d0 | 7255 | #define SYSCFG_SWPR_PAGE31 ((uint32_t)0x80000000) /*!< SRAM2 Write protection page 31*/ |
| mbed_official | 623:db79ecd649d0 | 7256 | |
| mbed_official | 623:db79ecd649d0 | 7257 | /****************** Bit definition for SYSCFG_SKR register ****************/ |
| mbed_official | 623:db79ecd649d0 | 7258 | #define SYSCFG_SKR_KEY ((uint32_t)0x000000FF) /*!< SRAM2 write protection key for software erase */ |
| mbed_official | 623:db79ecd649d0 | 7259 | |
| mbed_official | 623:db79ecd649d0 | 7260 | |
| mbed_official | 623:db79ecd649d0 | 7261 | |
| mbed_official | 623:db79ecd649d0 | 7262 | |
| mbed_official | 623:db79ecd649d0 | 7263 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 7264 | /* */ |
| mbed_official | 623:db79ecd649d0 | 7265 | /* TIM */ |
| mbed_official | 623:db79ecd649d0 | 7266 | /* */ |
| mbed_official | 623:db79ecd649d0 | 7267 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 7268 | /******************* Bit definition for TIM_CR1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7269 | #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */ |
| mbed_official | 623:db79ecd649d0 | 7270 | #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */ |
| mbed_official | 623:db79ecd649d0 | 7271 | #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */ |
| mbed_official | 623:db79ecd649d0 | 7272 | #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */ |
| mbed_official | 623:db79ecd649d0 | 7273 | #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */ |
| mbed_official | 623:db79ecd649d0 | 7274 | |
| mbed_official | 623:db79ecd649d0 | 7275 | #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
| mbed_official | 623:db79ecd649d0 | 7276 | #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7277 | #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7278 | |
| mbed_official | 623:db79ecd649d0 | 7279 | #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */ |
| mbed_official | 623:db79ecd649d0 | 7280 | |
| mbed_official | 623:db79ecd649d0 | 7281 | #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */ |
| mbed_official | 623:db79ecd649d0 | 7282 | #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7283 | #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7284 | |
| mbed_official | 623:db79ecd649d0 | 7285 | #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */ |
| mbed_official | 623:db79ecd649d0 | 7286 | |
| mbed_official | 623:db79ecd649d0 | 7287 | /******************* Bit definition for TIM_CR2 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7288 | #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */ |
| mbed_official | 623:db79ecd649d0 | 7289 | #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */ |
| mbed_official | 623:db79ecd649d0 | 7290 | #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */ |
| mbed_official | 623:db79ecd649d0 | 7291 | |
| mbed_official | 623:db79ecd649d0 | 7292 | #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */ |
| mbed_official | 623:db79ecd649d0 | 7293 | #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7294 | #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7295 | #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7296 | |
| mbed_official | 623:db79ecd649d0 | 7297 | #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */ |
| mbed_official | 623:db79ecd649d0 | 7298 | #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */ |
| mbed_official | 623:db79ecd649d0 | 7299 | #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */ |
| mbed_official | 623:db79ecd649d0 | 7300 | #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */ |
| mbed_official | 623:db79ecd649d0 | 7301 | #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */ |
| mbed_official | 623:db79ecd649d0 | 7302 | #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */ |
| mbed_official | 623:db79ecd649d0 | 7303 | #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */ |
| mbed_official | 623:db79ecd649d0 | 7304 | #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */ |
| mbed_official | 623:db79ecd649d0 | 7305 | #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 5 (OC5 output) */ |
| mbed_official | 623:db79ecd649d0 | 7306 | #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 6 (OC6 output) */ |
| mbed_official | 623:db79ecd649d0 | 7307 | |
| mbed_official | 623:db79ecd649d0 | 7308 | #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */ |
| mbed_official | 623:db79ecd649d0 | 7309 | #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7310 | #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7311 | #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7312 | #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7313 | |
| mbed_official | 623:db79ecd649d0 | 7314 | /******************* Bit definition for TIM_SMCR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7315 | #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */ |
| mbed_official | 623:db79ecd649d0 | 7316 | #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7317 | #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7318 | #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7319 | #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7320 | |
| mbed_official | 623:db79ecd649d0 | 7321 | #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */ |
| mbed_official | 623:db79ecd649d0 | 7322 | |
| mbed_official | 623:db79ecd649d0 | 7323 | #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */ |
| mbed_official | 623:db79ecd649d0 | 7324 | #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7325 | #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7326 | #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7327 | |
| mbed_official | 623:db79ecd649d0 | 7328 | #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */ |
| mbed_official | 623:db79ecd649d0 | 7329 | |
| mbed_official | 623:db79ecd649d0 | 7330 | #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */ |
| mbed_official | 623:db79ecd649d0 | 7331 | #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7332 | #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7333 | #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7334 | #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7335 | |
| mbed_official | 623:db79ecd649d0 | 7336 | #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 7337 | #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7338 | #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7339 | |
| mbed_official | 623:db79ecd649d0 | 7340 | #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */ |
| mbed_official | 623:db79ecd649d0 | 7341 | #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */ |
| mbed_official | 623:db79ecd649d0 | 7342 | |
| mbed_official | 623:db79ecd649d0 | 7343 | /******************* Bit definition for TIM_DIER register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7344 | #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7345 | #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7346 | #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7347 | #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7348 | #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7349 | #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7350 | #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7351 | #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 7352 | #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */ |
| mbed_official | 623:db79ecd649d0 | 7353 | #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */ |
| mbed_official | 623:db79ecd649d0 | 7354 | #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */ |
| mbed_official | 623:db79ecd649d0 | 7355 | #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */ |
| mbed_official | 623:db79ecd649d0 | 7356 | #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */ |
| mbed_official | 623:db79ecd649d0 | 7357 | #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */ |
| mbed_official | 623:db79ecd649d0 | 7358 | #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */ |
| mbed_official | 623:db79ecd649d0 | 7359 | |
| mbed_official | 623:db79ecd649d0 | 7360 | /******************** Bit definition for TIM_SR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7361 | #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7362 | #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7363 | #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7364 | #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7365 | #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7366 | #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7367 | #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7368 | #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7369 | #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break 2 interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7370 | #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */ |
| mbed_official | 623:db79ecd649d0 | 7371 | #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */ |
| mbed_official | 623:db79ecd649d0 | 7372 | #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */ |
| mbed_official | 623:db79ecd649d0 | 7373 | #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */ |
| mbed_official | 623:db79ecd649d0 | 7374 | #define TIM_SR_SBIF ((uint32_t)0x00002000) /*!<System Break interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7375 | #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7376 | #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 7377 | |
| mbed_official | 623:db79ecd649d0 | 7378 | |
| mbed_official | 623:db79ecd649d0 | 7379 | /******************* Bit definition for TIM_EGR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7380 | #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */ |
| mbed_official | 623:db79ecd649d0 | 7381 | #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */ |
| mbed_official | 623:db79ecd649d0 | 7382 | #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */ |
| mbed_official | 623:db79ecd649d0 | 7383 | #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */ |
| mbed_official | 623:db79ecd649d0 | 7384 | #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */ |
| mbed_official | 623:db79ecd649d0 | 7385 | #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */ |
| mbed_official | 623:db79ecd649d0 | 7386 | #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */ |
| mbed_official | 623:db79ecd649d0 | 7387 | #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */ |
| mbed_official | 623:db79ecd649d0 | 7388 | #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break 2 Generation */ |
| mbed_official | 623:db79ecd649d0 | 7389 | |
| mbed_official | 623:db79ecd649d0 | 7390 | |
| mbed_official | 623:db79ecd649d0 | 7391 | /****************** Bit definition for TIM_CCMR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7392 | #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
| mbed_official | 623:db79ecd649d0 | 7393 | #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7394 | #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7395 | |
| mbed_official | 623:db79ecd649d0 | 7396 | #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */ |
| mbed_official | 623:db79ecd649d0 | 7397 | #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */ |
| mbed_official | 623:db79ecd649d0 | 7398 | |
| mbed_official | 623:db79ecd649d0 | 7399 | #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
| mbed_official | 623:db79ecd649d0 | 7400 | #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7401 | #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7402 | #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7403 | #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7404 | |
| mbed_official | 623:db79ecd649d0 | 7405 | #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1 Clear Enable */ |
| mbed_official | 623:db79ecd649d0 | 7406 | |
| mbed_official | 623:db79ecd649d0 | 7407 | #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
| mbed_official | 623:db79ecd649d0 | 7408 | #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7409 | #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7410 | |
| mbed_official | 623:db79ecd649d0 | 7411 | #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */ |
| mbed_official | 623:db79ecd649d0 | 7412 | #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */ |
| mbed_official | 623:db79ecd649d0 | 7413 | |
| mbed_official | 623:db79ecd649d0 | 7414 | #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
| mbed_official | 623:db79ecd649d0 | 7415 | #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7416 | #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7417 | #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7418 | #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7419 | |
| mbed_official | 623:db79ecd649d0 | 7420 | #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */ |
| mbed_official | 623:db79ecd649d0 | 7421 | |
| mbed_official | 623:db79ecd649d0 | 7422 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 623:db79ecd649d0 | 7423 | #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 7424 | #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7425 | #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7426 | |
| mbed_official | 623:db79ecd649d0 | 7427 | #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
| mbed_official | 623:db79ecd649d0 | 7428 | #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7429 | #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7430 | #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7431 | #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7432 | |
| mbed_official | 623:db79ecd649d0 | 7433 | #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 7434 | #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7435 | #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7436 | |
| mbed_official | 623:db79ecd649d0 | 7437 | #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
| mbed_official | 623:db79ecd649d0 | 7438 | #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7439 | #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7440 | #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7441 | #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7442 | |
| mbed_official | 623:db79ecd649d0 | 7443 | /****************** Bit definition for TIM_CCMR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7444 | #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
| mbed_official | 623:db79ecd649d0 | 7445 | #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7446 | #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7447 | |
| mbed_official | 623:db79ecd649d0 | 7448 | #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */ |
| mbed_official | 623:db79ecd649d0 | 7449 | #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */ |
| mbed_official | 623:db79ecd649d0 | 7450 | |
| mbed_official | 623:db79ecd649d0 | 7451 | #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
| mbed_official | 623:db79ecd649d0 | 7452 | #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7453 | #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7454 | #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7455 | #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7456 | |
| mbed_official | 623:db79ecd649d0 | 7457 | #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */ |
| mbed_official | 623:db79ecd649d0 | 7458 | |
| mbed_official | 623:db79ecd649d0 | 7459 | #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
| mbed_official | 623:db79ecd649d0 | 7460 | #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7461 | #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7462 | |
| mbed_official | 623:db79ecd649d0 | 7463 | #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */ |
| mbed_official | 623:db79ecd649d0 | 7464 | #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */ |
| mbed_official | 623:db79ecd649d0 | 7465 | |
| mbed_official | 623:db79ecd649d0 | 7466 | #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
| mbed_official | 623:db79ecd649d0 | 7467 | #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7468 | #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7469 | #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7470 | #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7471 | |
| mbed_official | 623:db79ecd649d0 | 7472 | #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */ |
| mbed_official | 623:db79ecd649d0 | 7473 | |
| mbed_official | 623:db79ecd649d0 | 7474 | /*----------------------------------------------------------------------------*/ |
| mbed_official | 623:db79ecd649d0 | 7475 | #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 7476 | #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7477 | #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7478 | |
| mbed_official | 623:db79ecd649d0 | 7479 | #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
| mbed_official | 623:db79ecd649d0 | 7480 | #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7481 | #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7482 | #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7483 | #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7484 | |
| mbed_official | 623:db79ecd649d0 | 7485 | #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 7486 | #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7487 | #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7488 | |
| mbed_official | 623:db79ecd649d0 | 7489 | #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
| mbed_official | 623:db79ecd649d0 | 7490 | #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7491 | #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7492 | #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7493 | #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7494 | |
| mbed_official | 623:db79ecd649d0 | 7495 | /****************** Bit definition for TIM_CCMR3 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7496 | #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */ |
| mbed_official | 623:db79ecd649d0 | 7497 | #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */ |
| mbed_official | 623:db79ecd649d0 | 7498 | |
| mbed_official | 623:db79ecd649d0 | 7499 | #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[3:0] bits (Output Compare 5 Mode) */ |
| mbed_official | 623:db79ecd649d0 | 7500 | #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7501 | #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7502 | #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7503 | #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7504 | |
| mbed_official | 623:db79ecd649d0 | 7505 | #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */ |
| mbed_official | 623:db79ecd649d0 | 7506 | |
| mbed_official | 623:db79ecd649d0 | 7507 | #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */ |
| mbed_official | 623:db79ecd649d0 | 7508 | #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */ |
| mbed_official | 623:db79ecd649d0 | 7509 | |
| mbed_official | 623:db79ecd649d0 | 7510 | #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[3:0] bits (Output Compare 6 Mode) */ |
| mbed_official | 623:db79ecd649d0 | 7511 | #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7512 | #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7513 | #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7514 | #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7515 | |
| mbed_official | 623:db79ecd649d0 | 7516 | #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */ |
| mbed_official | 623:db79ecd649d0 | 7517 | |
| mbed_official | 623:db79ecd649d0 | 7518 | /******************* Bit definition for TIM_CCER register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7519 | #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */ |
| mbed_official | 623:db79ecd649d0 | 7520 | #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */ |
| mbed_official | 623:db79ecd649d0 | 7521 | #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */ |
| mbed_official | 623:db79ecd649d0 | 7522 | #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */ |
| mbed_official | 623:db79ecd649d0 | 7523 | #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */ |
| mbed_official | 623:db79ecd649d0 | 7524 | #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */ |
| mbed_official | 623:db79ecd649d0 | 7525 | #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */ |
| mbed_official | 623:db79ecd649d0 | 7526 | #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */ |
| mbed_official | 623:db79ecd649d0 | 7527 | #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */ |
| mbed_official | 623:db79ecd649d0 | 7528 | #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */ |
| mbed_official | 623:db79ecd649d0 | 7529 | #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */ |
| mbed_official | 623:db79ecd649d0 | 7530 | #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */ |
| mbed_official | 623:db79ecd649d0 | 7531 | #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */ |
| mbed_official | 623:db79ecd649d0 | 7532 | #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */ |
| mbed_official | 623:db79ecd649d0 | 7533 | #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */ |
| mbed_official | 623:db79ecd649d0 | 7534 | #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */ |
| mbed_official | 623:db79ecd649d0 | 7535 | #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */ |
| mbed_official | 623:db79ecd649d0 | 7536 | #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */ |
| mbed_official | 623:db79ecd649d0 | 7537 | #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */ |
| mbed_official | 623:db79ecd649d0 | 7538 | |
| mbed_official | 623:db79ecd649d0 | 7539 | /******************* Bit definition for TIM_CNT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7540 | #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */ |
| mbed_official | 623:db79ecd649d0 | 7541 | #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy (if UIFREMAP=1) */ |
| mbed_official | 623:db79ecd649d0 | 7542 | |
| mbed_official | 623:db79ecd649d0 | 7543 | /******************* Bit definition for TIM_PSC register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7544 | #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */ |
| mbed_official | 623:db79ecd649d0 | 7545 | |
| mbed_official | 623:db79ecd649d0 | 7546 | /******************* Bit definition for TIM_ARR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7547 | #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<Actual auto-reload Value */ |
| mbed_official | 623:db79ecd649d0 | 7548 | |
| mbed_official | 623:db79ecd649d0 | 7549 | /******************* Bit definition for TIM_RCR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7550 | #define TIM_RCR_REP ((uint32_t)0x0000FFFF) /*!<Repetition Counter Value */ |
| mbed_official | 623:db79ecd649d0 | 7551 | |
| mbed_official | 623:db79ecd649d0 | 7552 | /******************* Bit definition for TIM_CCR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7553 | #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */ |
| mbed_official | 623:db79ecd649d0 | 7554 | |
| mbed_official | 623:db79ecd649d0 | 7555 | /******************* Bit definition for TIM_CCR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7556 | #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */ |
| mbed_official | 623:db79ecd649d0 | 7557 | |
| mbed_official | 623:db79ecd649d0 | 7558 | /******************* Bit definition for TIM_CCR3 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7559 | #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */ |
| mbed_official | 623:db79ecd649d0 | 7560 | |
| mbed_official | 623:db79ecd649d0 | 7561 | /******************* Bit definition for TIM_CCR4 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7562 | #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */ |
| mbed_official | 623:db79ecd649d0 | 7563 | |
| mbed_official | 623:db79ecd649d0 | 7564 | /******************* Bit definition for TIM_CCR5 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7565 | #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */ |
| mbed_official | 623:db79ecd649d0 | 7566 | #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */ |
| mbed_official | 623:db79ecd649d0 | 7567 | #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */ |
| mbed_official | 623:db79ecd649d0 | 7568 | #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */ |
| mbed_official | 623:db79ecd649d0 | 7569 | |
| mbed_official | 623:db79ecd649d0 | 7570 | /******************* Bit definition for TIM_CCR6 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7571 | #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */ |
| mbed_official | 623:db79ecd649d0 | 7572 | |
| mbed_official | 623:db79ecd649d0 | 7573 | /******************* Bit definition for TIM_BDTR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7574 | #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
| mbed_official | 623:db79ecd649d0 | 7575 | #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7576 | #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7577 | #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7578 | #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7579 | #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 7580 | #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 7581 | #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 7582 | #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 7583 | |
| mbed_official | 623:db79ecd649d0 | 7584 | #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */ |
| mbed_official | 623:db79ecd649d0 | 7585 | #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7586 | #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7587 | |
| mbed_official | 623:db79ecd649d0 | 7588 | #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */ |
| mbed_official | 623:db79ecd649d0 | 7589 | #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */ |
| mbed_official | 623:db79ecd649d0 | 7590 | #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break 1 */ |
| mbed_official | 623:db79ecd649d0 | 7591 | #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break 1 */ |
| mbed_official | 623:db79ecd649d0 | 7592 | #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */ |
| mbed_official | 623:db79ecd649d0 | 7593 | #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */ |
| mbed_official | 623:db79ecd649d0 | 7594 | |
| mbed_official | 623:db79ecd649d0 | 7595 | #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break 1 */ |
| mbed_official | 623:db79ecd649d0 | 7596 | #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break 2 */ |
| mbed_official | 623:db79ecd649d0 | 7597 | |
| mbed_official | 623:db79ecd649d0 | 7598 | #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break 2 */ |
| mbed_official | 623:db79ecd649d0 | 7599 | #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break 2 */ |
| mbed_official | 623:db79ecd649d0 | 7600 | |
| mbed_official | 623:db79ecd649d0 | 7601 | /******************* Bit definition for TIM_DCR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7602 | #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */ |
| mbed_official | 623:db79ecd649d0 | 7603 | #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7604 | #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7605 | #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7606 | #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7607 | #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 7608 | |
| mbed_official | 623:db79ecd649d0 | 7609 | #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */ |
| mbed_official | 623:db79ecd649d0 | 7610 | #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7611 | #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7612 | #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7613 | #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 7614 | #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 7615 | |
| mbed_official | 623:db79ecd649d0 | 7616 | /******************* Bit definition for TIM_DMAR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7617 | #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */ |
| mbed_official | 623:db79ecd649d0 | 7618 | |
| mbed_official | 623:db79ecd649d0 | 7619 | /******************* Bit definition for TIM1_OR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7620 | #define TIM1_OR1_ETR_ADC1_RMP ((uint32_t)0x00000003) /*!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) */ |
| mbed_official | 623:db79ecd649d0 | 7621 | #define TIM1_OR1_ETR_ADC1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7622 | #define TIM1_OR1_ETR_ADC1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7623 | |
| mbed_official | 623:db79ecd649d0 | 7624 | #define TIM1_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000C) /*!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) */ |
| mbed_official | 623:db79ecd649d0 | 7625 | #define TIM1_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7626 | #define TIM1_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7627 | |
| mbed_official | 623:db79ecd649d0 | 7628 | #define TIM1_OR1_TI1_RMP ((uint32_t)0x00000010) /*!<TIM1 Input Capture 1 remap */ |
| mbed_official | 623:db79ecd649d0 | 7629 | |
| mbed_official | 623:db79ecd649d0 | 7630 | /******************* Bit definition for TIM1_OR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7631 | #define TIM1_OR2_BKINE ((uint32_t)0x00000001) /*!<BRK BKIN input enable */ |
| mbed_official | 623:db79ecd649d0 | 7632 | #define TIM1_OR2_BKCMP1E ((uint32_t)0x00000002) /*!<BRK COMP1 enable */ |
| mbed_official | 623:db79ecd649d0 | 7633 | #define TIM1_OR2_BKCMP2E ((uint32_t)0x00000004) /*!<BRK COMP2 enable */ |
| mbed_official | 623:db79ecd649d0 | 7634 | #define TIM1_OR2_BKDFBK0E ((uint32_t)0x00000100) /*!<BRK DFSDM_BREAK[0] enable */ |
| mbed_official | 623:db79ecd649d0 | 7635 | #define TIM1_OR2_BKINP ((uint32_t)0x00000200) /*!<BRK BKIN input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7636 | #define TIM1_OR2_BKCMP1P ((uint32_t)0x00000400) /*!<BRK COMP1 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7637 | #define TIM1_OR2_BKCMP2P ((uint32_t)0x00000800) /*!<BRK COMP2 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7638 | |
| mbed_official | 623:db79ecd649d0 | 7639 | #define TIM1_OR2_ETRSEL ((uint32_t)0x0001C000) /*!<ETRSEL[2:0] bits (TIM1 ETR source selection) */ |
| mbed_official | 623:db79ecd649d0 | 7640 | #define TIM1_OR2_ETRSEL_0 ((uint32_t)0x00004000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7641 | #define TIM1_OR2_ETRSEL_1 ((uint32_t)0x00008000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7642 | #define TIM1_OR2_ETRSEL_2 ((uint32_t)0x00010000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7643 | |
| mbed_official | 623:db79ecd649d0 | 7644 | /******************* Bit definition for TIM1_OR3 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7645 | #define TIM1_OR3_BK2INE ((uint32_t)0x00000001) /*!<BRK2 BKIN2 input enable */ |
| mbed_official | 623:db79ecd649d0 | 7646 | #define TIM1_OR3_BK2CMP1E ((uint32_t)0x00000002) /*!<BRK2 COMP1 enable */ |
| mbed_official | 623:db79ecd649d0 | 7647 | #define TIM1_OR3_BK2CMP2E ((uint32_t)0x00000004) /*!<BRK2 COMP2 enable */ |
| mbed_official | 623:db79ecd649d0 | 7648 | #define TIM1_OR3_BK2DFBK1E ((uint32_t)0x00000100) /*!<BRK2 DFSDM_BREAK[1] enable */ |
| mbed_official | 623:db79ecd649d0 | 7649 | #define TIM1_OR3_BK2INP ((uint32_t)0x00000200) /*!<BRK2 BKIN2 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7650 | #define TIM1_OR3_BK2CMP1P ((uint32_t)0x00000400) /*!<BRK2 COMP1 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7651 | #define TIM1_OR3_BK2CMP2P ((uint32_t)0x00000800) /*!<BRK2 COMP2 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7652 | |
| mbed_official | 623:db79ecd649d0 | 7653 | /******************* Bit definition for TIM8_OR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7654 | #define TIM8_OR1_ETR_ADC2_RMP ((uint32_t)0x00000003) /*!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) */ |
| mbed_official | 623:db79ecd649d0 | 7655 | #define TIM8_OR1_ETR_ADC2_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7656 | #define TIM8_OR1_ETR_ADC2_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7657 | |
| mbed_official | 623:db79ecd649d0 | 7658 | #define TIM8_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000C) /*!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) */ |
| mbed_official | 623:db79ecd649d0 | 7659 | #define TIM8_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7660 | #define TIM8_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7661 | |
| mbed_official | 623:db79ecd649d0 | 7662 | #define TIM8_OR1_TI1_RMP ((uint32_t)0x00000010) /*!<TIM8 Input Capture 1 remap */ |
| mbed_official | 623:db79ecd649d0 | 7663 | |
| mbed_official | 623:db79ecd649d0 | 7664 | /******************* Bit definition for TIM8_OR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7665 | #define TIM8_OR2_BKINE ((uint32_t)0x00000001) /*!<BRK BKIN input enable */ |
| mbed_official | 623:db79ecd649d0 | 7666 | #define TIM8_OR2_BKCMP1E ((uint32_t)0x00000002) /*!<BRK COMP1 enable */ |
| mbed_official | 623:db79ecd649d0 | 7667 | #define TIM8_OR2_BKCMP2E ((uint32_t)0x00000004) /*!<BRK COMP2 enable */ |
| mbed_official | 623:db79ecd649d0 | 7668 | #define TIM8_OR2_BKDFBK2E ((uint32_t)0x00000100) /*!<BRK DFSDM_BREAK[2] enable */ |
| mbed_official | 623:db79ecd649d0 | 7669 | #define TIM8_OR2_BKINP ((uint32_t)0x00000200) /*!<BRK BKIN input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7670 | #define TIM8_OR2_BKCMP1P ((uint32_t)0x00000400) /*!<BRK COMP1 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7671 | #define TIM8_OR2_BKCMP2P ((uint32_t)0x00000800) /*!<BRK COMP2 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7672 | |
| mbed_official | 623:db79ecd649d0 | 7673 | #define TIM8_OR2_ETRSEL ((uint32_t)0x0001C000) /*!<ETRSEL[2:0] bits (TIM8 ETR source selection) */ |
| mbed_official | 623:db79ecd649d0 | 7674 | #define TIM8_OR2_ETRSEL_0 ((uint32_t)0x00004000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7675 | #define TIM8_OR2_ETRSEL_1 ((uint32_t)0x00008000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7676 | #define TIM8_OR2_ETRSEL_2 ((uint32_t)0x00010000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7677 | |
| mbed_official | 623:db79ecd649d0 | 7678 | /******************* Bit definition for TIM8_OR3 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7679 | #define TIM8_OR3_BK2INE ((uint32_t)0x00000001) /*!<BRK2 BKIN2 input enable */ |
| mbed_official | 623:db79ecd649d0 | 7680 | #define TIM8_OR3_BK2CMP1E ((uint32_t)0x00000002) /*!<BRK2 COMP1 enable */ |
| mbed_official | 623:db79ecd649d0 | 7681 | #define TIM8_OR3_BK2CMP2E ((uint32_t)0x00000004) /*!<BRK2 COMP2 enable */ |
| mbed_official | 623:db79ecd649d0 | 7682 | #define TIM8_OR3_BK2DFBK3E ((uint32_t)0x00000100) /*!<BRK2 DFSDM_BREAK[3] enable */ |
| mbed_official | 623:db79ecd649d0 | 7683 | #define TIM8_OR3_BK2INP ((uint32_t)0x00000200) /*!<BRK2 BKIN2 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7684 | #define TIM8_OR3_BK2CMP1P ((uint32_t)0x00000400) /*!<BRK2 COMP1 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7685 | #define TIM8_OR3_BK2CMP2P ((uint32_t)0x00000800) /*!<BRK2 COMP2 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7686 | |
| mbed_official | 623:db79ecd649d0 | 7687 | /******************* Bit definition for TIM2_OR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7688 | #define TIM2_OR1_ITR1_RMP ((uint32_t)0x00000001) /*!<TIM2 Internal trigger 1 remap */ |
| mbed_official | 623:db79ecd649d0 | 7689 | #define TIM2_OR1_ETR1_RMP ((uint32_t)0x00000002) /*!<TIM2 External trigger 1 remap */ |
| mbed_official | 623:db79ecd649d0 | 7690 | |
| mbed_official | 623:db79ecd649d0 | 7691 | #define TIM2_OR1_TI4_RMP ((uint32_t)0x0000000C) /*!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) */ |
| mbed_official | 623:db79ecd649d0 | 7692 | #define TIM2_OR1_TI4_RMP_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7693 | #define TIM2_OR1_TI4_RMP_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7694 | |
| mbed_official | 623:db79ecd649d0 | 7695 | /******************* Bit definition for TIM2_OR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7696 | #define TIM2_OR2_ETRSEL ((uint32_t)0x0001C000) /*!<ETRSEL[2:0] bits (TIM2 ETR source selection) */ |
| mbed_official | 623:db79ecd649d0 | 7697 | #define TIM2_OR2_ETRSEL_0 ((uint32_t)0x00004000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7698 | #define TIM2_OR2_ETRSEL_1 ((uint32_t)0x00008000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7699 | #define TIM2_OR2_ETRSEL_2 ((uint32_t)0x00010000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7700 | |
| mbed_official | 623:db79ecd649d0 | 7701 | /******************* Bit definition for TIM3_OR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7702 | #define TIM3_OR1_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) */ |
| mbed_official | 623:db79ecd649d0 | 7703 | #define TIM3_OR1_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7704 | #define TIM3_OR1_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7705 | |
| mbed_official | 623:db79ecd649d0 | 7706 | /******************* Bit definition for TIM3_OR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7707 | #define TIM3_OR2_ETRSEL ((uint32_t)0x0001C000) /*!<ETRSEL[2:0] bits (TIM3 ETR source selection) */ |
| mbed_official | 623:db79ecd649d0 | 7708 | #define TIM3_OR2_ETRSEL_0 ((uint32_t)0x00004000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7709 | #define TIM3_OR2_ETRSEL_1 ((uint32_t)0x00008000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7710 | #define TIM3_OR2_ETRSEL_2 ((uint32_t)0x00010000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7711 | |
| mbed_official | 623:db79ecd649d0 | 7712 | /******************* Bit definition for TIM15_OR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 7713 | #define TIM15_OR1_TI1_RMP ((uint32_t)0x00000001) /*!<TIM15 Input Capture 1 remap */ |
| mbed_official | 623:db79ecd649d0 | 7714 | |
| mbed_official | 623:db79ecd649d0 | 7715 | #define TIM15_OR1_ENCODER_MODE ((uint32_t)0x00000006) /*!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) */ |
| mbed_official | 623:db79ecd649d0 | 7716 | #define TIM15_OR1_ENCODER_MODE_0 ((uint32_t)0x00000002) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7717 | #define TIM15_OR1_ENCODER_MODE_1 ((uint32_t)0x00000004) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7718 | |
| mbed_official | 623:db79ecd649d0 | 7719 | /******************* Bit definition for TIM15_OR2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 7720 | #define TIM15_OR2_BKINE ((uint32_t)0x00000001) /*!<BRK BKIN input enable */ |
| mbed_official | 623:db79ecd649d0 | 7721 | #define TIM15_OR2_BKCMP1E ((uint32_t)0x00000002) /*!<BRK COMP1 enable */ |
| mbed_official | 623:db79ecd649d0 | 7722 | #define TIM15_OR2_BKCMP2E ((uint32_t)0x00000004) /*!<BRK COMP2 enable */ |
| mbed_official | 623:db79ecd649d0 | 7723 | #define TIM15_OR2_BKDFBK0E ((uint32_t)0x00000100) /*!<BRK DFSDM_BREAK[0] enable */ |
| mbed_official | 623:db79ecd649d0 | 7724 | #define TIM15_OR2_BKINP ((uint32_t)0x00000200) /*!<BRK BKIN input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7725 | #define TIM15_OR2_BKCMP1P ((uint32_t)0x00000400) /*!<BRK COMP1 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7726 | #define TIM15_OR2_BKCMP2P ((uint32_t)0x00000800) /*!<BRK COMP2 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7727 | |
| mbed_official | 623:db79ecd649d0 | 7728 | /******************* Bit definition for TIM16_OR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 7729 | #define TIM16_OR1_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) */ |
| mbed_official | 623:db79ecd649d0 | 7730 | #define TIM16_OR1_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7731 | #define TIM16_OR1_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7732 | |
| mbed_official | 623:db79ecd649d0 | 7733 | /******************* Bit definition for TIM16_OR2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 7734 | #define TIM16_OR2_BKINE ((uint32_t)0x00000001) /*!<BRK BKIN input enable */ |
| mbed_official | 623:db79ecd649d0 | 7735 | #define TIM16_OR2_BKCMP1E ((uint32_t)0x00000002) /*!<BRK COMP1 enable */ |
| mbed_official | 623:db79ecd649d0 | 7736 | #define TIM16_OR2_BKCMP2E ((uint32_t)0x00000004) /*!<BRK COMP2 enable */ |
| mbed_official | 623:db79ecd649d0 | 7737 | #define TIM16_OR2_BKINP ((uint32_t)0x00000200) /*!<BRK BKIN input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7738 | #define TIM16_OR2_BKCMP1P ((uint32_t)0x00000400) /*!<BRK COMP1 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7739 | #define TIM16_OR2_BKCMP2P ((uint32_t)0x00000800) /*!<BRK COMP2 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7740 | |
| mbed_official | 623:db79ecd649d0 | 7741 | /******************* Bit definition for TIM17_OR1 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 7742 | #define TIM17_OR1_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) */ |
| mbed_official | 623:db79ecd649d0 | 7743 | #define TIM17_OR1_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7744 | #define TIM17_OR1_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7745 | |
| mbed_official | 623:db79ecd649d0 | 7746 | /******************* Bit definition for TIM17_OR2 register ******************/ |
| mbed_official | 623:db79ecd649d0 | 7747 | #define TIM17_OR2_BKINE ((uint32_t)0x00000001) /*!<BRK BKIN input enable */ |
| mbed_official | 623:db79ecd649d0 | 7748 | #define TIM17_OR2_BKCMP1E ((uint32_t)0x00000002) /*!<BRK COMP1 enable */ |
| mbed_official | 623:db79ecd649d0 | 7749 | #define TIM17_OR2_BKCMP2E ((uint32_t)0x00000004) /*!<BRK COMP2 enable */ |
| mbed_official | 623:db79ecd649d0 | 7750 | #define TIM17_OR2_BKINP ((uint32_t)0x00000200) /*!<BRK BKIN input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7751 | #define TIM17_OR2_BKCMP1P ((uint32_t)0x00000400) /*!<BRK COMP1 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7752 | #define TIM17_OR2_BKCMP2P ((uint32_t)0x00000800) /*!<BRK COMP2 input polarity */ |
| mbed_official | 623:db79ecd649d0 | 7753 | |
| mbed_official | 623:db79ecd649d0 | 7754 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 7755 | /* */ |
| mbed_official | 623:db79ecd649d0 | 7756 | /* Low Power Timer (LPTTIM) */ |
| mbed_official | 623:db79ecd649d0 | 7757 | /* */ |
| mbed_official | 623:db79ecd649d0 | 7758 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 7759 | /****************** Bit definition for LPTIM_ISR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7760 | #define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */ |
| mbed_official | 623:db79ecd649d0 | 7761 | #define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */ |
| mbed_official | 623:db79ecd649d0 | 7762 | #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */ |
| mbed_official | 623:db79ecd649d0 | 7763 | #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */ |
| mbed_official | 623:db79ecd649d0 | 7764 | #define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */ |
| mbed_official | 623:db79ecd649d0 | 7765 | #define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */ |
| mbed_official | 623:db79ecd649d0 | 7766 | #define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */ |
| mbed_official | 623:db79ecd649d0 | 7767 | |
| mbed_official | 623:db79ecd649d0 | 7768 | /****************** Bit definition for LPTIM_ICR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7769 | #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 7770 | #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 7771 | #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 7772 | #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 7773 | #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 7774 | #define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 7775 | #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 7776 | |
| mbed_official | 623:db79ecd649d0 | 7777 | /****************** Bit definition for LPTIM_IER register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7778 | #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 7779 | #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 7780 | #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 7781 | #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 7782 | #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 7783 | #define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 7784 | #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 7785 | |
| mbed_official | 623:db79ecd649d0 | 7786 | /****************** Bit definition for LPTIM_CFGR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7787 | #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */ |
| mbed_official | 623:db79ecd649d0 | 7788 | |
| mbed_official | 623:db79ecd649d0 | 7789 | #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */ |
| mbed_official | 623:db79ecd649d0 | 7790 | #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7791 | #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7792 | |
| mbed_official | 623:db79ecd649d0 | 7793 | #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ |
| mbed_official | 623:db79ecd649d0 | 7794 | #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7795 | #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7796 | |
| mbed_official | 623:db79ecd649d0 | 7797 | #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ |
| mbed_official | 623:db79ecd649d0 | 7798 | #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7799 | #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7800 | |
| mbed_official | 623:db79ecd649d0 | 7801 | #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 7802 | #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7803 | #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7804 | #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7805 | |
| mbed_official | 623:db79ecd649d0 | 7806 | #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */ |
| mbed_official | 623:db79ecd649d0 | 7807 | #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7808 | #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7809 | #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7810 | |
| mbed_official | 623:db79ecd649d0 | 7811 | #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ |
| mbed_official | 623:db79ecd649d0 | 7812 | #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7813 | #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7814 | |
| mbed_official | 623:db79ecd649d0 | 7815 | #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */ |
| mbed_official | 623:db79ecd649d0 | 7816 | #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */ |
| mbed_official | 623:db79ecd649d0 | 7817 | #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */ |
| mbed_official | 623:db79ecd649d0 | 7818 | #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */ |
| mbed_official | 623:db79ecd649d0 | 7819 | #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */ |
| mbed_official | 623:db79ecd649d0 | 7820 | #define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */ |
| mbed_official | 623:db79ecd649d0 | 7821 | |
| mbed_official | 623:db79ecd649d0 | 7822 | /****************** Bit definition for LPTIM_CR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 7823 | #define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */ |
| mbed_official | 623:db79ecd649d0 | 7824 | #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) /*!< Timer start in single mode */ |
| mbed_official | 623:db79ecd649d0 | 7825 | #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */ |
| mbed_official | 623:db79ecd649d0 | 7826 | |
| mbed_official | 623:db79ecd649d0 | 7827 | /****************** Bit definition for LPTIM_CMP register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7828 | #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */ |
| mbed_official | 623:db79ecd649d0 | 7829 | |
| mbed_official | 623:db79ecd649d0 | 7830 | /****************** Bit definition for LPTIM_ARR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7831 | #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */ |
| mbed_official | 623:db79ecd649d0 | 7832 | |
| mbed_official | 623:db79ecd649d0 | 7833 | /****************** Bit definition for LPTIM_CNT register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7834 | #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */ |
| mbed_official | 623:db79ecd649d0 | 7835 | |
| mbed_official | 623:db79ecd649d0 | 7836 | /****************** Bit definition for LPTIM_OR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 7837 | #define LPTIM_OR_OR ((uint32_t)0x00000003) /*!< LPTIMER[1:0] bits (Remap selection) */ |
| mbed_official | 623:db79ecd649d0 | 7838 | #define LPTIM_OR_OR_0 ((uint32_t)0x00000001) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7839 | #define LPTIM_OR_OR_1 ((uint32_t)0x00000002) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7840 | |
| mbed_official | 623:db79ecd649d0 | 7841 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 7842 | /* */ |
| mbed_official | 623:db79ecd649d0 | 7843 | /* Analog Comparators (COMP) */ |
| mbed_official | 623:db79ecd649d0 | 7844 | /* */ |
| mbed_official | 623:db79ecd649d0 | 7845 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 7846 | /********************** Bit definition for COMPx_CSR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 7847 | #define COMP_CSR_EN ((uint32_t)0x00000001) /*!< COMPx enable */ |
| mbed_official | 623:db79ecd649d0 | 7848 | |
| mbed_official | 623:db79ecd649d0 | 7849 | #define COMP_CSR_PWRMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */ |
| mbed_official | 623:db79ecd649d0 | 7850 | #define COMP_CSR_PWRMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7851 | #define COMP_CSR_PWRMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7852 | |
| mbed_official | 623:db79ecd649d0 | 7853 | #define COMP_CSR_INMSEL ((uint32_t)0x00000070) /*!< COMPx inverting input selection */ |
| mbed_official | 623:db79ecd649d0 | 7854 | #define COMP_CSR_INMSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input selection bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7855 | #define COMP_CSR_INMSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input selection bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7856 | #define COMP_CSR_INMSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input selection bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7857 | |
| mbed_official | 623:db79ecd649d0 | 7858 | #define COMP_CSR_INPSEL ((uint32_t)0x00000080) /*!< COMPx non inverting input selection */ |
| mbed_official | 623:db79ecd649d0 | 7859 | #define COMP_CSR_WINMODE ((uint32_t)0x00000200) /*!< COMPx window mode */ |
| mbed_official | 623:db79ecd649d0 | 7860 | #define COMP_CSR_POLARITY ((uint32_t)0x00008000) /*!< COMPx output polarity */ |
| mbed_official | 623:db79ecd649d0 | 7861 | |
| mbed_official | 623:db79ecd649d0 | 7862 | #define COMP_CSR_HYST ((uint32_t)0x00030000) /*!< COMPx hysteresis */ |
| mbed_official | 623:db79ecd649d0 | 7863 | #define COMP_CSR_HYST_0 ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7864 | #define COMP_CSR_HYST_1 ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7865 | |
| mbed_official | 623:db79ecd649d0 | 7866 | #define COMP_CSR_BLANKING ((uint32_t)0x001C0000) /*!< COMPx blanking source */ |
| mbed_official | 623:db79ecd649d0 | 7867 | #define COMP_CSR_BLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking source bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7868 | #define COMP_CSR_BLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking source bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7869 | #define COMP_CSR_BLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking source bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7870 | |
| mbed_official | 623:db79ecd649d0 | 7871 | #define COMP_CSR_BRGEN ((uint32_t)0x00400000) /*!< COMPx voltage scaler enable */ |
| mbed_official | 623:db79ecd649d0 | 7872 | #define COMP_CSR_SCALEN ((uint32_t)0x00800000) /*!< COMPx scaler bridge enable */ |
| mbed_official | 623:db79ecd649d0 | 7873 | #define COMP_CSR_VALUE ((uint32_t)0x40000000) /*!< COMPx value */ |
| mbed_official | 623:db79ecd649d0 | 7874 | #define COMP_CSR_LOCK ((uint32_t)0x80000000) /*!< COMPx lock */ |
| mbed_official | 623:db79ecd649d0 | 7875 | |
| mbed_official | 623:db79ecd649d0 | 7876 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 7877 | /* */ |
| mbed_official | 623:db79ecd649d0 | 7878 | /* Operational Amplifier (OPAMP) */ |
| mbed_official | 623:db79ecd649d0 | 7879 | /* */ |
| mbed_official | 623:db79ecd649d0 | 7880 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 7881 | /********************* Bit definition for OPAMPx_CSR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 7882 | #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */ |
| mbed_official | 623:db79ecd649d0 | 7883 | #define OPAMP_CSR_OPALPM ((uint32_t)0x00000002) /*!< Operational amplifier Low Power Mode */ |
| mbed_official | 623:db79ecd649d0 | 7884 | |
| mbed_official | 623:db79ecd649d0 | 7885 | #define OPAMP_CSR_OPAMODE ((uint32_t)0x0000000C) /*!< Operational amplifier PGA mode */ |
| mbed_official | 623:db79ecd649d0 | 7886 | #define OPAMP_CSR_OPAMODE_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7887 | #define OPAMP_CSR_OPAMODE_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7888 | |
| mbed_official | 623:db79ecd649d0 | 7889 | #define OPAMP_CSR_PGGAIN ((uint32_t)0x00000030) /*!< Operational amplifier Programmable amplifier gain value */ |
| mbed_official | 623:db79ecd649d0 | 7890 | #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7891 | #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7892 | |
| mbed_official | 623:db79ecd649d0 | 7893 | #define OPAMP_CSR_VMSEL ((uint32_t)0x00000300) /*!< Inverting input selection */ |
| mbed_official | 623:db79ecd649d0 | 7894 | #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7895 | #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7896 | |
| mbed_official | 623:db79ecd649d0 | 7897 | #define OPAMP_CSR_VPSEL ((uint32_t)0x00000400) /*!< Non inverted input selection */ |
| mbed_official | 623:db79ecd649d0 | 7898 | #define OPAMP_CSR_CALON ((uint32_t)0x00001000) /*!< Calibration mode enable */ |
| mbed_official | 623:db79ecd649d0 | 7899 | #define OPAMP_CSR_CALSEL ((uint32_t)0x00002000) /*!< Calibration selection */ |
| mbed_official | 623:db79ecd649d0 | 7900 | #define OPAMP_CSR_USERTRIM ((uint32_t)0x00004000) /*!< User trimming enable */ |
| mbed_official | 623:db79ecd649d0 | 7901 | #define OPAMP_CSR_CALOUT ((uint32_t)0x00008000) /*!< Operational amplifier1 calibration output */ |
| mbed_official | 623:db79ecd649d0 | 7902 | |
| mbed_official | 623:db79ecd649d0 | 7903 | /********************* Bit definition for OPAMP1_CSR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 7904 | #define OPAMP1_CSR_OPAEN ((uint32_t)0x00000001) /*!< Operational amplifier1 Enable */ |
| mbed_official | 623:db79ecd649d0 | 7905 | #define OPAMP1_CSR_OPALPM ((uint32_t)0x00000002) /*!< Operational amplifier1 Low Power Mode */ |
| mbed_official | 623:db79ecd649d0 | 7906 | |
| mbed_official | 623:db79ecd649d0 | 7907 | #define OPAMP1_CSR_OPAMODE ((uint32_t)0x0000000C) /*!< Operational amplifier1 PGA mode */ |
| mbed_official | 623:db79ecd649d0 | 7908 | #define OPAMP1_CSR_OPAMODE_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7909 | #define OPAMP1_CSR_OPAMODE_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7910 | |
| mbed_official | 623:db79ecd649d0 | 7911 | #define OPAMP1_CSR_PGAGAIN ((uint32_t)0x00000030) /*!< Operational amplifier1 Programmable amplifier gain value */ |
| mbed_official | 623:db79ecd649d0 | 7912 | #define OPAMP1_CSR_PGAGAIN_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7913 | #define OPAMP1_CSR_PGAGAIN_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7914 | |
| mbed_official | 623:db79ecd649d0 | 7915 | #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000300) /*!< Inverting input selection */ |
| mbed_official | 623:db79ecd649d0 | 7916 | #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7917 | #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7918 | |
| mbed_official | 623:db79ecd649d0 | 7919 | #define OPAMP1_CSR_VPSEL ((uint32_t)0x00000400) /*!< Non inverted input selection */ |
| mbed_official | 623:db79ecd649d0 | 7920 | #define OPAMP1_CSR_CALON ((uint32_t)0x00001000) /*!< Calibration mode enable */ |
| mbed_official | 623:db79ecd649d0 | 7921 | #define OPAMP1_CSR_CALSEL ((uint32_t)0x00002000) /*!< Calibration selection */ |
| mbed_official | 623:db79ecd649d0 | 7922 | #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00004000) /*!< User trimming enable */ |
| mbed_official | 623:db79ecd649d0 | 7923 | #define OPAMP1_CSR_CALOUT ((uint32_t)0x00008000) /*!< Operational amplifier1 calibration output */ |
| mbed_official | 623:db79ecd649d0 | 7924 | #define OPAMP1_CSR_OPARANGE ((uint32_t)0x80000000) /*!< Operational amplifiers power supply range for stability */ |
| mbed_official | 623:db79ecd649d0 | 7925 | |
| mbed_official | 623:db79ecd649d0 | 7926 | /********************* Bit definition for OPAMP2_CSR register ***************/ |
| mbed_official | 623:db79ecd649d0 | 7927 | #define OPAMP2_CSR_OPAEN ((uint32_t)0x00000001) /*!< Operational amplifier2 Enable */ |
| mbed_official | 623:db79ecd649d0 | 7928 | #define OPAMP2_CSR_OPALPM ((uint32_t)0x00000002) /*!< Operational amplifier2 Low Power Mode */ |
| mbed_official | 623:db79ecd649d0 | 7929 | |
| mbed_official | 623:db79ecd649d0 | 7930 | #define OPAMP2_CSR_OPAMODE ((uint32_t)0x0000000C) /*!< Operational amplifier2 PGA mode */ |
| mbed_official | 623:db79ecd649d0 | 7931 | #define OPAMP2_CSR_OPAMODE_0 ((uint32_t)0x00000004) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7932 | #define OPAMP2_CSR_OPAMODE_1 ((uint32_t)0x00000008) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7933 | |
| mbed_official | 623:db79ecd649d0 | 7934 | #define OPAMP2_CSR_PGAGAIN ((uint32_t)0x00000030) /*!< Operational amplifier2 Programmable amplifier gain value */ |
| mbed_official | 623:db79ecd649d0 | 7935 | #define OPAMP2_CSR_PGAGAIN_0 ((uint32_t)0x00000010) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7936 | #define OPAMP2_CSR_PGAGAIN_1 ((uint32_t)0x00000020) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7937 | |
| mbed_official | 623:db79ecd649d0 | 7938 | #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000300) /*!< Inverting input selection */ |
| mbed_official | 623:db79ecd649d0 | 7939 | #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7940 | #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7941 | |
| mbed_official | 623:db79ecd649d0 | 7942 | #define OPAMP2_CSR_VPSEL ((uint32_t)0x00000400) /*!< Non inverted input selection */ |
| mbed_official | 623:db79ecd649d0 | 7943 | #define OPAMP2_CSR_CALON ((uint32_t)0x00001000) /*!< Calibration mode enable */ |
| mbed_official | 623:db79ecd649d0 | 7944 | #define OPAMP2_CSR_CALSEL ((uint32_t)0x00002000) /*!< Calibration selection */ |
| mbed_official | 623:db79ecd649d0 | 7945 | #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00004000) /*!< User trimming enable */ |
| mbed_official | 623:db79ecd649d0 | 7946 | #define OPAMP2_CSR_CALOUT ((uint32_t)0x00008000) /*!< Operational amplifier2 calibration output */ |
| mbed_official | 623:db79ecd649d0 | 7947 | |
| mbed_official | 623:db79ecd649d0 | 7948 | /******************* Bit definition for OPAMP_OTR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 7949 | #define OPAMP_OTR_TRIMOFFSETN ((uint32_t)0x0000001F) /*!< Trim for NMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7950 | #define OPAMP_OTR_TRIMOFFSETP ((uint32_t)0x00001F00) /*!< Trim for PMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7951 | |
| mbed_official | 623:db79ecd649d0 | 7952 | /******************* Bit definition for OPAMP1_OTR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 7953 | #define OPAMP1_OTR_TRIMOFFSETN ((uint32_t)0x0000001F) /*!< Trim for NMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7954 | #define OPAMP1_OTR_TRIMOFFSETP ((uint32_t)0x00001F00) /*!< Trim for PMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7955 | |
| mbed_official | 623:db79ecd649d0 | 7956 | /******************* Bit definition for OPAMP2_OTR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 7957 | #define OPAMP2_OTR_TRIMOFFSETN ((uint32_t)0x0000001F) /*!< Trim for NMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7958 | #define OPAMP2_OTR_TRIMOFFSETP ((uint32_t)0x00001F00) /*!< Trim for PMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7959 | |
| mbed_official | 623:db79ecd649d0 | 7960 | /******************* Bit definition for OPAMP_LPOTR register ****************/ |
| mbed_official | 623:db79ecd649d0 | 7961 | #define OPAMP_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001F) /*!< Trim for NMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7962 | #define OPAMP_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00) /*!< Trim for PMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7963 | |
| mbed_official | 623:db79ecd649d0 | 7964 | /******************* Bit definition for OPAMP1_LPOTR register ****************/ |
| mbed_official | 623:db79ecd649d0 | 7965 | #define OPAMP1_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001F) /*!< Trim for NMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7966 | #define OPAMP1_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00) /*!< Trim for PMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7967 | |
| mbed_official | 623:db79ecd649d0 | 7968 | /******************* Bit definition for OPAMP2_LPOTR register ****************/ |
| mbed_official | 623:db79ecd649d0 | 7969 | #define OPAMP2_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001F) /*!< Trim for NMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7970 | #define OPAMP2_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00) /*!< Trim for PMOS differential pairs */ |
| mbed_official | 623:db79ecd649d0 | 7971 | |
| mbed_official | 623:db79ecd649d0 | 7972 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 7973 | /* */ |
| mbed_official | 623:db79ecd649d0 | 7974 | /* Touch Sensing Controller (TSC) */ |
| mbed_official | 623:db79ecd649d0 | 7975 | /* */ |
| mbed_official | 623:db79ecd649d0 | 7976 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 7977 | /******************* Bit definition for TSC_CR register *********************/ |
| mbed_official | 623:db79ecd649d0 | 7978 | #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */ |
| mbed_official | 623:db79ecd649d0 | 7979 | #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */ |
| mbed_official | 623:db79ecd649d0 | 7980 | #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */ |
| mbed_official | 623:db79ecd649d0 | 7981 | #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */ |
| mbed_official | 623:db79ecd649d0 | 7982 | #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */ |
| mbed_official | 623:db79ecd649d0 | 7983 | |
| mbed_official | 623:db79ecd649d0 | 7984 | #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */ |
| mbed_official | 623:db79ecd649d0 | 7985 | #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7986 | #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7987 | #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7988 | |
| mbed_official | 623:db79ecd649d0 | 7989 | #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 7990 | #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7991 | #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 7992 | #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 7993 | |
| mbed_official | 623:db79ecd649d0 | 7994 | #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */ |
| mbed_official | 623:db79ecd649d0 | 7995 | #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */ |
| mbed_official | 623:db79ecd649d0 | 7996 | |
| mbed_official | 623:db79ecd649d0 | 7997 | #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */ |
| mbed_official | 623:db79ecd649d0 | 7998 | #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 7999 | #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8000 | #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8001 | #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8002 | #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8003 | #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 8004 | #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 8005 | |
| mbed_official | 623:db79ecd649d0 | 8006 | #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */ |
| mbed_official | 623:db79ecd649d0 | 8007 | #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8008 | #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8009 | #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8010 | #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8011 | |
| mbed_official | 623:db79ecd649d0 | 8012 | #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */ |
| mbed_official | 623:db79ecd649d0 | 8013 | #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8014 | #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8015 | #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8016 | #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8017 | |
| mbed_official | 623:db79ecd649d0 | 8018 | /******************* Bit definition for TSC_IER register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8019 | #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8020 | #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8021 | |
| mbed_official | 623:db79ecd649d0 | 8022 | /******************* Bit definition for TSC_ICR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8023 | #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */ |
| mbed_official | 623:db79ecd649d0 | 8024 | #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */ |
| mbed_official | 623:db79ecd649d0 | 8025 | |
| mbed_official | 623:db79ecd649d0 | 8026 | /******************* Bit definition for TSC_ISR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8027 | #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */ |
| mbed_official | 623:db79ecd649d0 | 8028 | #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */ |
| mbed_official | 623:db79ecd649d0 | 8029 | |
| mbed_official | 623:db79ecd649d0 | 8030 | /******************* Bit definition for TSC_IOHCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 8031 | #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8032 | #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8033 | #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8034 | #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8035 | #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8036 | #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8037 | #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8038 | #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8039 | #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8040 | #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8041 | #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8042 | #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8043 | #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8044 | #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8045 | #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8046 | #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8047 | #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8048 | #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8049 | #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8050 | #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8051 | #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8052 | #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8053 | #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8054 | #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8055 | #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8056 | #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8057 | #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8058 | #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8059 | #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8060 | #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8061 | #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8062 | #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */ |
| mbed_official | 623:db79ecd649d0 | 8063 | |
| mbed_official | 623:db79ecd649d0 | 8064 | /******************* Bit definition for TSC_IOASCR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 8065 | #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8066 | #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8067 | #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8068 | #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8069 | #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8070 | #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8071 | #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8072 | #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8073 | #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8074 | #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8075 | #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8076 | #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8077 | #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8078 | #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8079 | #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8080 | #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8081 | #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8082 | #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8083 | #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8084 | #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8085 | #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8086 | #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8087 | #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8088 | #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8089 | #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8090 | #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8091 | #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8092 | #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8093 | #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8094 | #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8095 | #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8096 | #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */ |
| mbed_official | 623:db79ecd649d0 | 8097 | |
| mbed_official | 623:db79ecd649d0 | 8098 | /******************* Bit definition for TSC_IOSCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 8099 | #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8100 | #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8101 | #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8102 | #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8103 | #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8104 | #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8105 | #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8106 | #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8107 | #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8108 | #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8109 | #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8110 | #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8111 | #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8112 | #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8113 | #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8114 | #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8115 | #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8116 | #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8117 | #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8118 | #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8119 | #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8120 | #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8121 | #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8122 | #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8123 | #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8124 | #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8125 | #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8126 | #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8127 | #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8128 | #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8129 | #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8130 | #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */ |
| mbed_official | 623:db79ecd649d0 | 8131 | |
| mbed_official | 623:db79ecd649d0 | 8132 | /******************* Bit definition for TSC_IOCCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 8133 | #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8134 | #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8135 | #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8136 | #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8137 | #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8138 | #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8139 | #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8140 | #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8141 | #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8142 | #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8143 | #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8144 | #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8145 | #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8146 | #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8147 | #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8148 | #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8149 | #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8150 | #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8151 | #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8152 | #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8153 | #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8154 | #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8155 | #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8156 | #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8157 | #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8158 | #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8159 | #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8160 | #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8161 | #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8162 | #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8163 | #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8164 | #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */ |
| mbed_official | 623:db79ecd649d0 | 8165 | |
| mbed_official | 623:db79ecd649d0 | 8166 | /******************* Bit definition for TSC_IOGCSR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 8167 | #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */ |
| mbed_official | 623:db79ecd649d0 | 8168 | #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */ |
| mbed_official | 623:db79ecd649d0 | 8169 | #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */ |
| mbed_official | 623:db79ecd649d0 | 8170 | #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */ |
| mbed_official | 623:db79ecd649d0 | 8171 | #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */ |
| mbed_official | 623:db79ecd649d0 | 8172 | #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */ |
| mbed_official | 623:db79ecd649d0 | 8173 | #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */ |
| mbed_official | 623:db79ecd649d0 | 8174 | #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */ |
| mbed_official | 623:db79ecd649d0 | 8175 | #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */ |
| mbed_official | 623:db79ecd649d0 | 8176 | #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */ |
| mbed_official | 623:db79ecd649d0 | 8177 | #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */ |
| mbed_official | 623:db79ecd649d0 | 8178 | #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */ |
| mbed_official | 623:db79ecd649d0 | 8179 | #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */ |
| mbed_official | 623:db79ecd649d0 | 8180 | #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */ |
| mbed_official | 623:db79ecd649d0 | 8181 | #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */ |
| mbed_official | 623:db79ecd649d0 | 8182 | #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */ |
| mbed_official | 623:db79ecd649d0 | 8183 | |
| mbed_official | 623:db79ecd649d0 | 8184 | /******************* Bit definition for TSC_IOGXCR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 8185 | #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */ |
| mbed_official | 623:db79ecd649d0 | 8186 | |
| mbed_official | 623:db79ecd649d0 | 8187 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8188 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8189 | /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ |
| mbed_official | 623:db79ecd649d0 | 8190 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8191 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8192 | /****************** Bit definition for USART_CR1 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 8193 | #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */ |
| mbed_official | 623:db79ecd649d0 | 8194 | #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */ |
| mbed_official | 623:db79ecd649d0 | 8195 | #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */ |
| mbed_official | 623:db79ecd649d0 | 8196 | #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */ |
| mbed_official | 623:db79ecd649d0 | 8197 | #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 8198 | #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 8199 | #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 8200 | #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 8201 | #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 8202 | #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */ |
| mbed_official | 623:db79ecd649d0 | 8203 | #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */ |
| mbed_official | 623:db79ecd649d0 | 8204 | #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */ |
| mbed_official | 623:db79ecd649d0 | 8205 | #define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */ |
| mbed_official | 623:db79ecd649d0 | 8206 | #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8207 | #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */ |
| mbed_official | 623:db79ecd649d0 | 8208 | #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8209 | #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */ |
| mbed_official | 623:db79ecd649d0 | 8210 | #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ |
| mbed_official | 623:db79ecd649d0 | 8211 | #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8212 | #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8213 | #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8214 | #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8215 | #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8216 | #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ |
| mbed_official | 623:db79ecd649d0 | 8217 | #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8218 | #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8219 | #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8220 | #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8221 | #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8222 | #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8223 | #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8224 | #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8225 | |
| mbed_official | 623:db79ecd649d0 | 8226 | /****************** Bit definition for USART_CR2 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 8227 | #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */ |
| mbed_official | 623:db79ecd649d0 | 8228 | #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */ |
| mbed_official | 623:db79ecd649d0 | 8229 | #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 8230 | #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */ |
| mbed_official | 623:db79ecd649d0 | 8231 | #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */ |
| mbed_official | 623:db79ecd649d0 | 8232 | #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */ |
| mbed_official | 623:db79ecd649d0 | 8233 | #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */ |
| mbed_official | 623:db79ecd649d0 | 8234 | #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */ |
| mbed_official | 623:db79ecd649d0 | 8235 | #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8236 | #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8237 | #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */ |
| mbed_official | 623:db79ecd649d0 | 8238 | #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */ |
| mbed_official | 623:db79ecd649d0 | 8239 | #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */ |
| mbed_official | 623:db79ecd649d0 | 8240 | #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */ |
| mbed_official | 623:db79ecd649d0 | 8241 | #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */ |
| mbed_official | 623:db79ecd649d0 | 8242 | #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */ |
| mbed_official | 623:db79ecd649d0 | 8243 | #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/ |
| mbed_official | 623:db79ecd649d0 | 8244 | #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ |
| mbed_official | 623:db79ecd649d0 | 8245 | #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8246 | #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8247 | #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */ |
| mbed_official | 623:db79ecd649d0 | 8248 | #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */ |
| mbed_official | 623:db79ecd649d0 | 8249 | |
| mbed_official | 623:db79ecd649d0 | 8250 | /****************** Bit definition for USART_CR3 register *******************/ |
| mbed_official | 623:db79ecd649d0 | 8251 | #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 8252 | #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */ |
| mbed_official | 623:db79ecd649d0 | 8253 | #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */ |
| mbed_official | 623:db79ecd649d0 | 8254 | #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */ |
| mbed_official | 623:db79ecd649d0 | 8255 | #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */ |
| mbed_official | 623:db79ecd649d0 | 8256 | #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */ |
| mbed_official | 623:db79ecd649d0 | 8257 | #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */ |
| mbed_official | 623:db79ecd649d0 | 8258 | #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */ |
| mbed_official | 623:db79ecd649d0 | 8259 | #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */ |
| mbed_official | 623:db79ecd649d0 | 8260 | #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */ |
| mbed_official | 623:db79ecd649d0 | 8261 | #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 8262 | #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */ |
| mbed_official | 623:db79ecd649d0 | 8263 | #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */ |
| mbed_official | 623:db79ecd649d0 | 8264 | #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */ |
| mbed_official | 623:db79ecd649d0 | 8265 | #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */ |
| mbed_official | 623:db79ecd649d0 | 8266 | #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */ |
| mbed_official | 623:db79ecd649d0 | 8267 | #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ |
| mbed_official | 623:db79ecd649d0 | 8268 | #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8269 | #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8270 | #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8271 | #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ |
| mbed_official | 623:db79ecd649d0 | 8272 | #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8273 | #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8274 | #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */ |
| mbed_official | 623:db79ecd649d0 | 8275 | |
| mbed_official | 623:db79ecd649d0 | 8276 | /****************** Bit definition for USART_BRR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 8277 | #define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */ |
| mbed_official | 623:db79ecd649d0 | 8278 | #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */ |
| mbed_official | 623:db79ecd649d0 | 8279 | |
| mbed_official | 623:db79ecd649d0 | 8280 | /****************** Bit definition for USART_GTPR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 8281 | #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */ |
| mbed_official | 623:db79ecd649d0 | 8282 | #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */ |
| mbed_official | 623:db79ecd649d0 | 8283 | |
| mbed_official | 623:db79ecd649d0 | 8284 | |
| mbed_official | 623:db79ecd649d0 | 8285 | /******************* Bit definition for USART_RTOR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 8286 | #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */ |
| mbed_official | 623:db79ecd649d0 | 8287 | #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */ |
| mbed_official | 623:db79ecd649d0 | 8288 | |
| mbed_official | 623:db79ecd649d0 | 8289 | /******************* Bit definition for USART_RQR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 8290 | #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ |
| mbed_official | 623:db79ecd649d0 | 8291 | #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ |
| mbed_official | 623:db79ecd649d0 | 8292 | #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ |
| mbed_official | 623:db79ecd649d0 | 8293 | #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ |
| mbed_official | 623:db79ecd649d0 | 8294 | #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ |
| mbed_official | 623:db79ecd649d0 | 8295 | |
| mbed_official | 623:db79ecd649d0 | 8296 | /******************* Bit definition for USART_ISR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 8297 | #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */ |
| mbed_official | 623:db79ecd649d0 | 8298 | #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */ |
| mbed_official | 623:db79ecd649d0 | 8299 | #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */ |
| mbed_official | 623:db79ecd649d0 | 8300 | #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */ |
| mbed_official | 623:db79ecd649d0 | 8301 | #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */ |
| mbed_official | 623:db79ecd649d0 | 8302 | #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */ |
| mbed_official | 623:db79ecd649d0 | 8303 | #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */ |
| mbed_official | 623:db79ecd649d0 | 8304 | #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */ |
| mbed_official | 623:db79ecd649d0 | 8305 | #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */ |
| mbed_official | 623:db79ecd649d0 | 8306 | #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */ |
| mbed_official | 623:db79ecd649d0 | 8307 | #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */ |
| mbed_official | 623:db79ecd649d0 | 8308 | #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */ |
| mbed_official | 623:db79ecd649d0 | 8309 | #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */ |
| mbed_official | 623:db79ecd649d0 | 8310 | #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */ |
| mbed_official | 623:db79ecd649d0 | 8311 | #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */ |
| mbed_official | 623:db79ecd649d0 | 8312 | #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */ |
| mbed_official | 623:db79ecd649d0 | 8313 | #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */ |
| mbed_official | 623:db79ecd649d0 | 8314 | #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */ |
| mbed_official | 623:db79ecd649d0 | 8315 | #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */ |
| mbed_official | 623:db79ecd649d0 | 8316 | #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */ |
| mbed_official | 623:db79ecd649d0 | 8317 | #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */ |
| mbed_official | 623:db79ecd649d0 | 8318 | #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */ |
| mbed_official | 623:db79ecd649d0 | 8319 | |
| mbed_official | 623:db79ecd649d0 | 8320 | /******************* Bit definition for USART_ICR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 8321 | #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8322 | #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8323 | #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8324 | #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8325 | #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8326 | #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8327 | #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8328 | #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8329 | #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8330 | #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8331 | #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8332 | #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */ |
| mbed_official | 623:db79ecd649d0 | 8333 | |
| mbed_official | 623:db79ecd649d0 | 8334 | /******************* Bit definition for USART_RDR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 8335 | #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */ |
| mbed_official | 623:db79ecd649d0 | 8336 | |
| mbed_official | 623:db79ecd649d0 | 8337 | /******************* Bit definition for USART_TDR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 8338 | #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */ |
| mbed_official | 623:db79ecd649d0 | 8339 | |
| mbed_official | 623:db79ecd649d0 | 8340 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8341 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8342 | /* Single Wire Protocol Master Interface (SWPMI) */ |
| mbed_official | 623:db79ecd649d0 | 8343 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8344 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8345 | |
| mbed_official | 623:db79ecd649d0 | 8346 | /******************* Bit definition for SWPMI_CR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8347 | #define SWPMI_CR_RXDMA ((uint32_t)0x00000001) /*!<Reception DMA enable */ |
| mbed_official | 623:db79ecd649d0 | 8348 | #define SWPMI_CR_TXDMA ((uint32_t)0x00000002) /*!<Transmission DMA enable */ |
| mbed_official | 623:db79ecd649d0 | 8349 | #define SWPMI_CR_RXMODE ((uint32_t)0x00000004) /*!<Reception buffering mode */ |
| mbed_official | 623:db79ecd649d0 | 8350 | #define SWPMI_CR_TXMODE ((uint32_t)0x00000008) /*!<Transmission buffering mode */ |
| mbed_official | 623:db79ecd649d0 | 8351 | #define SWPMI_CR_LPBK ((uint32_t)0x00000010) /*!<Loopback mode enable */ |
| mbed_official | 623:db79ecd649d0 | 8352 | #define SWPMI_CR_SWPACT ((uint32_t)0x00000020) /*!<Single wire protocol master interface activate */ |
| mbed_official | 623:db79ecd649d0 | 8353 | #define SWPMI_CR_DEACT ((uint32_t)0x00000400) /*!<Single wire protocol master interface deactivate */ |
| mbed_official | 623:db79ecd649d0 | 8354 | |
| mbed_official | 623:db79ecd649d0 | 8355 | /******************* Bit definition for SWPMI_BRR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8356 | #define SWPMI_BRR_BR ((uint32_t)0x0000003F) /*!<BR[5:0] bits (Bitrate prescaler) */ |
| mbed_official | 623:db79ecd649d0 | 8357 | |
| mbed_official | 623:db79ecd649d0 | 8358 | /******************* Bit definition for SWPMI_ISR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8359 | #define SWPMI_ISR_RXBFF ((uint32_t)0x00000001) /*!<Receive buffer full flag */ |
| mbed_official | 623:db79ecd649d0 | 8360 | #define SWPMI_ISR_TXBEF ((uint32_t)0x00000002) /*!<Transmit buffer empty flag */ |
| mbed_official | 623:db79ecd649d0 | 8361 | #define SWPMI_ISR_RXBERF ((uint32_t)0x00000004) /*!<Receive CRC error flag */ |
| mbed_official | 623:db79ecd649d0 | 8362 | #define SWPMI_ISR_RXOVRF ((uint32_t)0x00000008) /*!<Receive overrun error flag */ |
| mbed_official | 623:db79ecd649d0 | 8363 | #define SWPMI_ISR_TXUNRF ((uint32_t)0x00000010) /*!<Transmit underrun error flag */ |
| mbed_official | 623:db79ecd649d0 | 8364 | #define SWPMI_ISR_RXNE ((uint32_t)0x00000020) /*!<Receive data register not empty */ |
| mbed_official | 623:db79ecd649d0 | 8365 | #define SWPMI_ISR_TXE ((uint32_t)0x00000040) /*!<Transmit data register empty */ |
| mbed_official | 623:db79ecd649d0 | 8366 | #define SWPMI_ISR_TCF ((uint32_t)0x00000080) /*!<Transfer complete flag */ |
| mbed_official | 623:db79ecd649d0 | 8367 | #define SWPMI_ISR_SRF ((uint32_t)0x00000100) /*!<Slave resume flag */ |
| mbed_official | 623:db79ecd649d0 | 8368 | #define SWPMI_ISR_SUSP ((uint32_t)0x00000200) /*!<SUSPEND flag */ |
| mbed_official | 623:db79ecd649d0 | 8369 | #define SWPMI_ISR_DEACTF ((uint32_t)0x00000400) /*!<DEACTIVATED flag */ |
| mbed_official | 623:db79ecd649d0 | 8370 | |
| mbed_official | 623:db79ecd649d0 | 8371 | /******************* Bit definition for SWPMI_ICR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8372 | #define SWPMI_ICR_CRXBFF ((uint32_t)0x00000001) /*!<Clear receive buffer full flag */ |
| mbed_official | 623:db79ecd649d0 | 8373 | #define SWPMI_ICR_CTXBEF ((uint32_t)0x00000002) /*!<Clear transmit buffer empty flag */ |
| mbed_official | 623:db79ecd649d0 | 8374 | #define SWPMI_ICR_CRXBERF ((uint32_t)0x00000004) /*!<Clear receive CRC error flag */ |
| mbed_official | 623:db79ecd649d0 | 8375 | #define SWPMI_ICR_CRXOVRF ((uint32_t)0x00000008) /*!<Clear receive overrun error flag */ |
| mbed_official | 623:db79ecd649d0 | 8376 | #define SWPMI_ICR_CTXUNRF ((uint32_t)0x00000010) /*!<Clear transmit underrun error flag */ |
| mbed_official | 623:db79ecd649d0 | 8377 | #define SWPMI_ICR_CTCF ((uint32_t)0x00000080) /*!<Clear transfer complete flag */ |
| mbed_official | 623:db79ecd649d0 | 8378 | #define SWPMI_ICR_CSRF ((uint32_t)0x00000100) /*!<Clear slave resume flag */ |
| mbed_official | 623:db79ecd649d0 | 8379 | |
| mbed_official | 623:db79ecd649d0 | 8380 | /******************* Bit definition for SWPMI_IER register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8381 | #define SWPMI_IER_SRIE ((uint32_t)0x00000100) /*!<Slave resume interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8382 | #define SWPMI_IER_TCIE ((uint32_t)0x00000080) /*!<Transmit complete interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8383 | #define SWPMI_IER_TIE ((uint32_t)0x00000040) /*!<Transmit interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8384 | #define SWPMI_IER_RIE ((uint32_t)0x00000020) /*!<Receive interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8385 | #define SWPMI_IER_TXUNRIE ((uint32_t)0x00000010) /*!<Transmit underrun error interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8386 | #define SWPMI_IER_RXOVRIE ((uint32_t)0x00000008) /*!<Receive overrun error interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8387 | #define SWPMI_IER_RXBERIE ((uint32_t)0x00000004) /*!<Receive CRC error interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8388 | #define SWPMI_IER_TXBEIE ((uint32_t)0x00000002) /*!<Transmit buffer empty interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8389 | #define SWPMI_IER_RXBFIE ((uint32_t)0x00000001) /*!<Receive buffer full interrupt enable */ |
| mbed_official | 623:db79ecd649d0 | 8390 | |
| mbed_official | 623:db79ecd649d0 | 8391 | /******************* Bit definition for SWPMI_RFL register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8392 | #define SWPMI_RFL_RFL ((uint32_t)0x0000001F) /*!<RFL[4:0] bits (Receive Frame length) */ |
| mbed_official | 623:db79ecd649d0 | 8393 | #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */ |
| mbed_official | 623:db79ecd649d0 | 8394 | |
| mbed_official | 623:db79ecd649d0 | 8395 | /******************* Bit definition for SWPMI_TDR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8396 | #define SWPMI_TDR_TD ((uint32_t)0xFFFFFFFF) /*!<Transmit Data Register */ |
| mbed_official | 623:db79ecd649d0 | 8397 | |
| mbed_official | 623:db79ecd649d0 | 8398 | /******************* Bit definition for SWPMI_RDR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8399 | #define SWPMI_RDR_RD ((uint32_t)0xFFFFFFFF) /*!<Receive Data Register */ |
| mbed_official | 623:db79ecd649d0 | 8400 | |
| mbed_official | 623:db79ecd649d0 | 8401 | /******************* Bit definition for SWPMI_OR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8402 | #define SWPMI_OR_TBYP ((uint32_t)0x00000001) /*!<SWP Transceiver Bypass */ |
| mbed_official | 623:db79ecd649d0 | 8403 | #define SWPMI_OR_CLASS ((uint32_t)0x00000002) /*!<SWP Voltage Class selection */ |
| mbed_official | 623:db79ecd649d0 | 8404 | |
| mbed_official | 623:db79ecd649d0 | 8405 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8406 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8407 | /* VREFBUF */ |
| mbed_official | 623:db79ecd649d0 | 8408 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8409 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8410 | /******************* Bit definition for VREFBUF_CSR register ****************/ |
| mbed_official | 623:db79ecd649d0 | 8411 | #define VREFBUF_CSR_ENVR ((uint32_t)0x00000001) /*!<Voltage reference buffer enable */ |
| mbed_official | 623:db79ecd649d0 | 8412 | #define VREFBUF_CSR_HIZ ((uint32_t)0x00000002) /*!<High impedance mode */ |
| mbed_official | 623:db79ecd649d0 | 8413 | #define VREFBUF_CSR_VRS ((uint32_t)0x00000004) /*!<Voltage reference scale */ |
| mbed_official | 623:db79ecd649d0 | 8414 | #define VREFBUF_CSR_VRR ((uint32_t)0x00000008) /*!<Voltage reference buffer ready */ |
| mbed_official | 623:db79ecd649d0 | 8415 | |
| mbed_official | 623:db79ecd649d0 | 8416 | /******************* Bit definition for VREFBUF_CCR register ******************/ |
| mbed_official | 623:db79ecd649d0 | 8417 | #define VREFBUF_CCR_TRIM ((uint32_t)0x0000003F) /*!<TRIM[5:0] bits (Trimming code) */ |
| mbed_official | 623:db79ecd649d0 | 8418 | |
| mbed_official | 623:db79ecd649d0 | 8419 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8420 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8421 | /* Window WATCHDOG */ |
| mbed_official | 623:db79ecd649d0 | 8422 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8423 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8424 | /******************* Bit definition for WWDG_CR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8425 | #define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
| mbed_official | 623:db79ecd649d0 | 8426 | #define WWDG_CR_T_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8427 | #define WWDG_CR_T_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8428 | #define WWDG_CR_T_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8429 | #define WWDG_CR_T_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8430 | #define WWDG_CR_T_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8431 | #define WWDG_CR_T_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 8432 | #define WWDG_CR_T_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 8433 | |
| mbed_official | 623:db79ecd649d0 | 8434 | #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */ |
| mbed_official | 623:db79ecd649d0 | 8435 | |
| mbed_official | 623:db79ecd649d0 | 8436 | /******************* Bit definition for WWDG_CFR register *******************/ |
| mbed_official | 623:db79ecd649d0 | 8437 | #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */ |
| mbed_official | 623:db79ecd649d0 | 8438 | #define WWDG_CFR_W_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8439 | #define WWDG_CFR_W_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8440 | #define WWDG_CFR_W_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8441 | #define WWDG_CFR_W_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8442 | #define WWDG_CFR_W_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8443 | #define WWDG_CFR_W_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 8444 | #define WWDG_CFR_W_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 8445 | |
| mbed_official | 623:db79ecd649d0 | 8446 | #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */ |
| mbed_official | 623:db79ecd649d0 | 8447 | #define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8448 | #define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8449 | |
| mbed_official | 623:db79ecd649d0 | 8450 | #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8451 | |
| mbed_official | 623:db79ecd649d0 | 8452 | /******************* Bit definition for WWDG_SR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8453 | #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */ |
| mbed_official | 623:db79ecd649d0 | 8454 | |
| mbed_official | 623:db79ecd649d0 | 8455 | |
| mbed_official | 623:db79ecd649d0 | 8456 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8457 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8458 | /* Debug MCU */ |
| mbed_official | 623:db79ecd649d0 | 8459 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8460 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8461 | /******************** Bit definition for DBGMCU_IDCODE register *************/ |
| mbed_official | 623:db79ecd649d0 | 8462 | #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x0000FFFF) |
| mbed_official | 623:db79ecd649d0 | 8463 | #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) |
| mbed_official | 623:db79ecd649d0 | 8464 | |
| mbed_official | 623:db79ecd649d0 | 8465 | /******************** Bit definition for DBGMCU_CR register *****************/ |
| mbed_official | 623:db79ecd649d0 | 8466 | #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 8467 | #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 8468 | #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 8469 | #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 8470 | |
| mbed_official | 623:db79ecd649d0 | 8471 | #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) |
| mbed_official | 623:db79ecd649d0 | 8472 | #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8473 | #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8474 | |
| mbed_official | 623:db79ecd649d0 | 8475 | /******************** Bit definition for DBGMCU_APB1FZR1 register ***********/ |
| mbed_official | 623:db79ecd649d0 | 8476 | #define DBGMCU_APB1FZR1_DBG_TIM2_STOP ((uint32_t)0x00000001) |
| mbed_official | 623:db79ecd649d0 | 8477 | #define DBGMCU_APB1FZR1_DBG_TIM3_STOP ((uint32_t)0x00000002) |
| mbed_official | 623:db79ecd649d0 | 8478 | #define DBGMCU_APB1FZR1_DBG_TIM4_STOP ((uint32_t)0x00000004) |
| mbed_official | 623:db79ecd649d0 | 8479 | #define DBGMCU_APB1FZR1_DBG_TIM5_STOP ((uint32_t)0x00000008) |
| mbed_official | 623:db79ecd649d0 | 8480 | #define DBGMCU_APB1FZR1_DBG_TIM6_STOP ((uint32_t)0x00000010) |
| mbed_official | 623:db79ecd649d0 | 8481 | #define DBGMCU_APB1FZR1_DBG_TIM7_STOP ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 8482 | #define DBGMCU_APB1FZR1_DBG_RTC_STOP ((uint32_t)0x00000400) |
| mbed_official | 623:db79ecd649d0 | 8483 | #define DBGMCU_APB1FZR1_DBG_WWDG_STOP ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 8484 | #define DBGMCU_APB1FZR1_DBG_IWDG_STOP ((uint32_t)0x00001000) |
| mbed_official | 623:db79ecd649d0 | 8485 | #define DBGMCU_APB1FZR1_DBG_I2C1_STOP ((uint32_t)0x00200000) |
| mbed_official | 623:db79ecd649d0 | 8486 | #define DBGMCU_APB1FZR1_DBG_I2C2_STOP ((uint32_t)0x00400000) |
| mbed_official | 623:db79ecd649d0 | 8487 | #define DBGMCU_APB1FZR1_DBG_I2C3_STOP ((uint32_t)0x00800000) |
| mbed_official | 623:db79ecd649d0 | 8488 | #define DBGMCU_APB1FZR1_DBG_CAN_STOP ((uint32_t)0x02000000) |
| mbed_official | 623:db79ecd649d0 | 8489 | #define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP ((uint32_t)0x80000000) |
| mbed_official | 623:db79ecd649d0 | 8490 | |
| mbed_official | 623:db79ecd649d0 | 8491 | /******************** Bit definition for DBGMCU_APB1FZR2 register **********/ |
| mbed_official | 623:db79ecd649d0 | 8492 | #define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP ((uint32_t)0x00000020) |
| mbed_official | 623:db79ecd649d0 | 8493 | |
| mbed_official | 623:db79ecd649d0 | 8494 | /******************** Bit definition for DBGMCU_APB2FZ register ************/ |
| mbed_official | 623:db79ecd649d0 | 8495 | #define DBGMCU_APB2FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) |
| mbed_official | 623:db79ecd649d0 | 8496 | #define DBGMCU_APB2FZ_DBG_TIM8_STOP ((uint32_t)0x00002000) |
| mbed_official | 623:db79ecd649d0 | 8497 | #define DBGMCU_APB2FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) |
| mbed_official | 623:db79ecd649d0 | 8498 | #define DBGMCU_APB2FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) |
| mbed_official | 623:db79ecd649d0 | 8499 | #define DBGMCU_APB2FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) |
| mbed_official | 623:db79ecd649d0 | 8500 | |
| mbed_official | 623:db79ecd649d0 | 8501 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8502 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8503 | /* USB_OTG */ |
| mbed_official | 623:db79ecd649d0 | 8504 | /* */ |
| mbed_official | 623:db79ecd649d0 | 8505 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 8506 | /******************** Bit definition for USB_OTG_GOTGCTL register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8507 | #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */ |
| mbed_official | 623:db79ecd649d0 | 8508 | #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */ |
| mbed_official | 623:db79ecd649d0 | 8509 | #define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */ |
| mbed_official | 623:db79ecd649d0 | 8510 | #define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */ |
| mbed_official | 623:db79ecd649d0 | 8511 | #define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */ |
| mbed_official | 623:db79ecd649d0 | 8512 | #define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */ |
| mbed_official | 623:db79ecd649d0 | 8513 | #define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */ |
| mbed_official | 623:db79ecd649d0 | 8514 | #define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */ |
| mbed_official | 623:db79ecd649d0 | 8515 | #define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid*/ |
| mbed_official | 623:db79ecd649d0 | 8516 | |
| mbed_official | 623:db79ecd649d0 | 8517 | /******************** Bit definition for USB_OTG_HCFG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8518 | |
| mbed_official | 623:db79ecd649d0 | 8519 | #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */ |
| mbed_official | 623:db79ecd649d0 | 8520 | #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8521 | #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8522 | #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */ |
| mbed_official | 623:db79ecd649d0 | 8523 | |
| mbed_official | 623:db79ecd649d0 | 8524 | /******************** Bit definition for USB_OTG_DCFG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8525 | |
| mbed_official | 623:db79ecd649d0 | 8526 | #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */ |
| mbed_official | 623:db79ecd649d0 | 8527 | #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8528 | #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8529 | #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */ |
| mbed_official | 623:db79ecd649d0 | 8530 | #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */ |
| mbed_official | 623:db79ecd649d0 | 8531 | #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8532 | #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8533 | #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8534 | #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8535 | #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8536 | #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 8537 | #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 8538 | #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */ |
| mbed_official | 623:db79ecd649d0 | 8539 | #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8540 | #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8541 | #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */ |
| mbed_official | 623:db79ecd649d0 | 8542 | #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8543 | #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8544 | |
| mbed_official | 623:db79ecd649d0 | 8545 | /******************** Bit definition for USB_OTG_PCGCR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8546 | #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */ |
| mbed_official | 623:db79ecd649d0 | 8547 | #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */ |
| mbed_official | 623:db79ecd649d0 | 8548 | #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */ |
| mbed_official | 623:db79ecd649d0 | 8549 | |
| mbed_official | 623:db79ecd649d0 | 8550 | /******************** Bit definition for USB_OTG_GOTGINT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8551 | #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */ |
| mbed_official | 623:db79ecd649d0 | 8552 | #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */ |
| mbed_official | 623:db79ecd649d0 | 8553 | #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */ |
| mbed_official | 623:db79ecd649d0 | 8554 | #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */ |
| mbed_official | 623:db79ecd649d0 | 8555 | #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */ |
| mbed_official | 623:db79ecd649d0 | 8556 | #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */ |
| mbed_official | 623:db79ecd649d0 | 8557 | |
| mbed_official | 623:db79ecd649d0 | 8558 | /******************** Bit definition for USB_OTG_DCTL register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8559 | #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */ |
| mbed_official | 623:db79ecd649d0 | 8560 | #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */ |
| mbed_official | 623:db79ecd649d0 | 8561 | #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */ |
| mbed_official | 623:db79ecd649d0 | 8562 | #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */ |
| mbed_official | 623:db79ecd649d0 | 8563 | |
| mbed_official | 623:db79ecd649d0 | 8564 | #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */ |
| mbed_official | 623:db79ecd649d0 | 8565 | #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8566 | #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8567 | #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8568 | #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */ |
| mbed_official | 623:db79ecd649d0 | 8569 | #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */ |
| mbed_official | 623:db79ecd649d0 | 8570 | #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */ |
| mbed_official | 623:db79ecd649d0 | 8571 | #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */ |
| mbed_official | 623:db79ecd649d0 | 8572 | #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */ |
| mbed_official | 623:db79ecd649d0 | 8573 | |
| mbed_official | 623:db79ecd649d0 | 8574 | /******************** Bit definition for USB_OTG_HFIR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8575 | #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */ |
| mbed_official | 623:db79ecd649d0 | 8576 | |
| mbed_official | 623:db79ecd649d0 | 8577 | /******************** Bit definition for USB_OTG_HFNUM register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8578 | #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */ |
| mbed_official | 623:db79ecd649d0 | 8579 | #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */ |
| mbed_official | 623:db79ecd649d0 | 8580 | |
| mbed_official | 623:db79ecd649d0 | 8581 | /******************** Bit definition for USB_OTG_DSTS register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8582 | #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */ |
| mbed_official | 623:db79ecd649d0 | 8583 | |
| mbed_official | 623:db79ecd649d0 | 8584 | #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */ |
| mbed_official | 623:db79ecd649d0 | 8585 | #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8586 | #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8587 | #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */ |
| mbed_official | 623:db79ecd649d0 | 8588 | #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */ |
| mbed_official | 623:db79ecd649d0 | 8589 | |
| mbed_official | 623:db79ecd649d0 | 8590 | /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8591 | #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8592 | #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */ |
| mbed_official | 623:db79ecd649d0 | 8593 | #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8594 | #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8595 | #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8596 | #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8597 | #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */ |
| mbed_official | 623:db79ecd649d0 | 8598 | #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */ |
| mbed_official | 623:db79ecd649d0 | 8599 | #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */ |
| mbed_official | 623:db79ecd649d0 | 8600 | |
| mbed_official | 623:db79ecd649d0 | 8601 | /******************** Bit definition for USB_OTG_GUSBCFG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8602 | |
| mbed_official | 623:db79ecd649d0 | 8603 | #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */ |
| mbed_official | 623:db79ecd649d0 | 8604 | #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8605 | #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8606 | #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8607 | #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ |
| mbed_official | 623:db79ecd649d0 | 8608 | #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */ |
| mbed_official | 623:db79ecd649d0 | 8609 | #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */ |
| mbed_official | 623:db79ecd649d0 | 8610 | #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */ |
| mbed_official | 623:db79ecd649d0 | 8611 | #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8612 | #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8613 | #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8614 | #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8615 | #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */ |
| mbed_official | 623:db79ecd649d0 | 8616 | #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */ |
| mbed_official | 623:db79ecd649d0 | 8617 | #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */ |
| mbed_official | 623:db79ecd649d0 | 8618 | #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */ |
| mbed_official | 623:db79ecd649d0 | 8619 | #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */ |
| mbed_official | 623:db79ecd649d0 | 8620 | #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */ |
| mbed_official | 623:db79ecd649d0 | 8621 | #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */ |
| mbed_official | 623:db79ecd649d0 | 8622 | #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */ |
| mbed_official | 623:db79ecd649d0 | 8623 | #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */ |
| mbed_official | 623:db79ecd649d0 | 8624 | #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */ |
| mbed_official | 623:db79ecd649d0 | 8625 | #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */ |
| mbed_official | 623:db79ecd649d0 | 8626 | #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */ |
| mbed_official | 623:db79ecd649d0 | 8627 | #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */ |
| mbed_official | 623:db79ecd649d0 | 8628 | |
| mbed_official | 623:db79ecd649d0 | 8629 | /******************** Bit definition for USB_OTG_GRSTCTL register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8630 | #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */ |
| mbed_official | 623:db79ecd649d0 | 8631 | #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */ |
| mbed_official | 623:db79ecd649d0 | 8632 | #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */ |
| mbed_official | 623:db79ecd649d0 | 8633 | #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */ |
| mbed_official | 623:db79ecd649d0 | 8634 | #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */ |
| mbed_official | 623:db79ecd649d0 | 8635 | #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */ |
| mbed_official | 623:db79ecd649d0 | 8636 | #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8637 | #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8638 | #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8639 | #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8640 | #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8641 | #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */ |
| mbed_official | 623:db79ecd649d0 | 8642 | #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */ |
| mbed_official | 623:db79ecd649d0 | 8643 | |
| mbed_official | 623:db79ecd649d0 | 8644 | /******************** Bit definition for USB_OTG_DIEPMSK register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8645 | #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8646 | #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8647 | #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */ |
| mbed_official | 623:db79ecd649d0 | 8648 | #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */ |
| mbed_official | 623:db79ecd649d0 | 8649 | #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */ |
| mbed_official | 623:db79ecd649d0 | 8650 | #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */ |
| mbed_official | 623:db79ecd649d0 | 8651 | #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */ |
| mbed_official | 623:db79ecd649d0 | 8652 | #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8653 | |
| mbed_official | 623:db79ecd649d0 | 8654 | /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8655 | #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */ |
| mbed_official | 623:db79ecd649d0 | 8656 | #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */ |
| mbed_official | 623:db79ecd649d0 | 8657 | #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8658 | #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8659 | #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8660 | #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8661 | #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8662 | #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 8663 | #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 8664 | #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 8665 | |
| mbed_official | 623:db79ecd649d0 | 8666 | #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */ |
| mbed_official | 623:db79ecd649d0 | 8667 | #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8668 | #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8669 | #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8670 | #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8671 | #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8672 | #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 8673 | #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 8674 | #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 8675 | |
| mbed_official | 623:db79ecd649d0 | 8676 | /******************** Bit definition for USB_OTG_HAINT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8677 | #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */ |
| mbed_official | 623:db79ecd649d0 | 8678 | |
| mbed_official | 623:db79ecd649d0 | 8679 | /******************** Bit definition for USB_OTG_DOEPMSK register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8680 | #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8681 | #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8682 | #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */ |
| mbed_official | 623:db79ecd649d0 | 8683 | #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */ |
| mbed_official | 623:db79ecd649d0 | 8684 | #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */ |
| mbed_official | 623:db79ecd649d0 | 8685 | #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */ |
| mbed_official | 623:db79ecd649d0 | 8686 | #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8687 | |
| mbed_official | 623:db79ecd649d0 | 8688 | /******************** Bit definition for USB_OTG_GINTSTS register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8689 | #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */ |
| mbed_official | 623:db79ecd649d0 | 8690 | #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8691 | #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8692 | #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */ |
| mbed_official | 623:db79ecd649d0 | 8693 | #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */ |
| mbed_official | 623:db79ecd649d0 | 8694 | #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */ |
| mbed_official | 623:db79ecd649d0 | 8695 | #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */ |
| mbed_official | 623:db79ecd649d0 | 8696 | #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */ |
| mbed_official | 623:db79ecd649d0 | 8697 | #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */ |
| mbed_official | 623:db79ecd649d0 | 8698 | #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */ |
| mbed_official | 623:db79ecd649d0 | 8699 | #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */ |
| mbed_official | 623:db79ecd649d0 | 8700 | #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */ |
| mbed_official | 623:db79ecd649d0 | 8701 | #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8702 | #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8703 | #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8704 | #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8705 | #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */ |
| mbed_official | 623:db79ecd649d0 | 8706 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */ |
| mbed_official | 623:db79ecd649d0 | 8707 | #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */ |
| mbed_official | 623:db79ecd649d0 | 8708 | #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8709 | #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8710 | #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */ |
| mbed_official | 623:db79ecd649d0 | 8711 | #define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8712 | #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */ |
| mbed_official | 623:db79ecd649d0 | 8713 | #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8714 | #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8715 | #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */ |
| mbed_official | 623:db79ecd649d0 | 8716 | |
| mbed_official | 623:db79ecd649d0 | 8717 | /******************** Bit definition for USB_OTG_GINTMSK register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8718 | |
| mbed_official | 623:db79ecd649d0 | 8719 | #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8720 | #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8721 | #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */ |
| mbed_official | 623:db79ecd649d0 | 8722 | #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */ |
| mbed_official | 623:db79ecd649d0 | 8723 | #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */ |
| mbed_official | 623:db79ecd649d0 | 8724 | #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */ |
| mbed_official | 623:db79ecd649d0 | 8725 | #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */ |
| mbed_official | 623:db79ecd649d0 | 8726 | #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */ |
| mbed_official | 623:db79ecd649d0 | 8727 | #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */ |
| mbed_official | 623:db79ecd649d0 | 8728 | #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */ |
| mbed_official | 623:db79ecd649d0 | 8729 | #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */ |
| mbed_official | 623:db79ecd649d0 | 8730 | #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8731 | #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8732 | #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8733 | #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8734 | #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8735 | #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */ |
| mbed_official | 623:db79ecd649d0 | 8736 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */ |
| mbed_official | 623:db79ecd649d0 | 8737 | #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */ |
| mbed_official | 623:db79ecd649d0 | 8738 | #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8739 | #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8740 | #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */ |
| mbed_official | 623:db79ecd649d0 | 8741 | #define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */ |
| mbed_official | 623:db79ecd649d0 | 8742 | #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */ |
| mbed_official | 623:db79ecd649d0 | 8743 | #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8744 | #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8745 | #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8746 | |
| mbed_official | 623:db79ecd649d0 | 8747 | /******************** Bit definition for USB_OTG_DAINT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8748 | #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */ |
| mbed_official | 623:db79ecd649d0 | 8749 | #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */ |
| mbed_official | 623:db79ecd649d0 | 8750 | |
| mbed_official | 623:db79ecd649d0 | 8751 | /******************** Bit definition for USB_OTG_HAINTMSK register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8752 | #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8753 | |
| mbed_official | 623:db79ecd649d0 | 8754 | /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8755 | #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */ |
| mbed_official | 623:db79ecd649d0 | 8756 | #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */ |
| mbed_official | 623:db79ecd649d0 | 8757 | #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */ |
| mbed_official | 623:db79ecd649d0 | 8758 | #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */ |
| mbed_official | 623:db79ecd649d0 | 8759 | |
| mbed_official | 623:db79ecd649d0 | 8760 | /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8761 | #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */ |
| mbed_official | 623:db79ecd649d0 | 8762 | #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */ |
| mbed_official | 623:db79ecd649d0 | 8763 | |
| mbed_official | 623:db79ecd649d0 | 8764 | /******************** Bit definition for OTG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8765 | |
| mbed_official | 623:db79ecd649d0 | 8766 | #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */ |
| mbed_official | 623:db79ecd649d0 | 8767 | #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8768 | #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8769 | #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8770 | #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8771 | #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */ |
| mbed_official | 623:db79ecd649d0 | 8772 | #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */ |
| mbed_official | 623:db79ecd649d0 | 8773 | #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8774 | #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8775 | #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */ |
| mbed_official | 623:db79ecd649d0 | 8776 | #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8777 | #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8778 | #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8779 | #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8780 | #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */ |
| mbed_official | 623:db79ecd649d0 | 8781 | #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8782 | #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8783 | #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8784 | #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8785 | #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */ |
| mbed_official | 623:db79ecd649d0 | 8786 | #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8787 | #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8788 | #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8789 | #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8790 | |
| mbed_official | 623:db79ecd649d0 | 8791 | /******************** Bit definition for OTG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8792 | |
| mbed_official | 623:db79ecd649d0 | 8793 | #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */ |
| mbed_official | 623:db79ecd649d0 | 8794 | #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8795 | #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8796 | #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8797 | #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8798 | #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */ |
| mbed_official | 623:db79ecd649d0 | 8799 | #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */ |
| mbed_official | 623:db79ecd649d0 | 8800 | #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8801 | #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8802 | #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */ |
| mbed_official | 623:db79ecd649d0 | 8803 | #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8804 | #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8805 | #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8806 | #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8807 | #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */ |
| mbed_official | 623:db79ecd649d0 | 8808 | #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8809 | #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8810 | #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8811 | #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8812 | #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */ |
| mbed_official | 623:db79ecd649d0 | 8813 | #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8814 | #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8815 | #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8816 | #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8817 | |
| mbed_official | 623:db79ecd649d0 | 8818 | /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8819 | #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */ |
| mbed_official | 623:db79ecd649d0 | 8820 | |
| mbed_official | 623:db79ecd649d0 | 8821 | /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8822 | #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */ |
| mbed_official | 623:db79ecd649d0 | 8823 | |
| mbed_official | 623:db79ecd649d0 | 8824 | /******************** Bit definition for OTG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8825 | #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */ |
| mbed_official | 623:db79ecd649d0 | 8826 | #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */ |
| mbed_official | 623:db79ecd649d0 | 8827 | #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */ |
| mbed_official | 623:db79ecd649d0 | 8828 | #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */ |
| mbed_official | 623:db79ecd649d0 | 8829 | |
| mbed_official | 623:db79ecd649d0 | 8830 | /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8831 | #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */ |
| mbed_official | 623:db79ecd649d0 | 8832 | |
| mbed_official | 623:db79ecd649d0 | 8833 | /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8834 | #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */ |
| mbed_official | 623:db79ecd649d0 | 8835 | |
| mbed_official | 623:db79ecd649d0 | 8836 | #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */ |
| mbed_official | 623:db79ecd649d0 | 8837 | #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8838 | #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8839 | #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8840 | #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8841 | #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8842 | #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 8843 | #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 8844 | #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 8845 | |
| mbed_official | 623:db79ecd649d0 | 8846 | #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */ |
| mbed_official | 623:db79ecd649d0 | 8847 | #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8848 | #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8849 | #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8850 | #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8851 | #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8852 | #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 8853 | #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 8854 | |
| mbed_official | 623:db79ecd649d0 | 8855 | /******************** Bit definition for USB_OTG_DTHRCTL register ***************/ |
| mbed_official | 623:db79ecd649d0 | 8856 | #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */ |
| mbed_official | 623:db79ecd649d0 | 8857 | #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */ |
| mbed_official | 623:db79ecd649d0 | 8858 | |
| mbed_official | 623:db79ecd649d0 | 8859 | #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */ |
| mbed_official | 623:db79ecd649d0 | 8860 | #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8861 | #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8862 | #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8863 | #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8864 | #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8865 | #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 8866 | #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 8867 | #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 8868 | #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 8869 | #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */ |
| mbed_official | 623:db79ecd649d0 | 8870 | |
| mbed_official | 623:db79ecd649d0 | 8871 | #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */ |
| mbed_official | 623:db79ecd649d0 | 8872 | #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8873 | #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8874 | #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8875 | #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8876 | #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 8877 | #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 8878 | #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 8879 | #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */ |
| mbed_official | 623:db79ecd649d0 | 8880 | #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */ |
| mbed_official | 623:db79ecd649d0 | 8881 | #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */ |
| mbed_official | 623:db79ecd649d0 | 8882 | |
| mbed_official | 623:db79ecd649d0 | 8883 | /******************** Bit definition for USB_OTG_DIEPEMPMSK register ***************/ |
| mbed_official | 623:db79ecd649d0 | 8884 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */ |
| mbed_official | 623:db79ecd649d0 | 8885 | |
| mbed_official | 623:db79ecd649d0 | 8886 | /******************** Bit definition for USB_OTG_DEACHINT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8887 | #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */ |
| mbed_official | 623:db79ecd649d0 | 8888 | #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */ |
| mbed_official | 623:db79ecd649d0 | 8889 | |
| mbed_official | 623:db79ecd649d0 | 8890 | /******************** Bit definition for USB_OTG_GCCFG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8891 | #define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001) /*!< Data contact detection (DCD) status */ |
| mbed_official | 623:db79ecd649d0 | 8892 | #define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002) /*!< Primary detection (PD) status */ |
| mbed_official | 623:db79ecd649d0 | 8893 | #define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004) /*!< Secondary detection (SD) status */ |
| mbed_official | 623:db79ecd649d0 | 8894 | #define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008) /*!< DM pull-up detection status */ |
| mbed_official | 623:db79ecd649d0 | 8895 | #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */ |
| mbed_official | 623:db79ecd649d0 | 8896 | #define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000) /*!< Battery charging detector (BCD) enable */ |
| mbed_official | 623:db79ecd649d0 | 8897 | #define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000) /*!< Data contact detection (DCD) mode enable*/ |
| mbed_official | 623:db79ecd649d0 | 8898 | #define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000) /*!< Primary detection (PD) mode enable*/ |
| mbed_official | 623:db79ecd649d0 | 8899 | #define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000) /*!< Secondary detection (SD) mode enable */ |
| mbed_official | 623:db79ecd649d0 | 8900 | #define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< Secondary detection (SD) mode enable */ |
| mbed_official | 623:db79ecd649d0 | 8901 | |
| mbed_official | 623:db79ecd649d0 | 8902 | /******************** Bit definition for USB_OTG_GPWRDN) register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8903 | #define USB_OTG_GPWRDN_DISABLEVBUS ((uint32_t)0x00000040) /*!< Power down */ |
| mbed_official | 623:db79ecd649d0 | 8904 | |
| mbed_official | 623:db79ecd649d0 | 8905 | /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8906 | #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */ |
| mbed_official | 623:db79ecd649d0 | 8907 | #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */ |
| mbed_official | 623:db79ecd649d0 | 8908 | |
| mbed_official | 623:db79ecd649d0 | 8909 | /******************** Bit definition for USB_OTG_CID register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8910 | #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */ |
| mbed_official | 623:db79ecd649d0 | 8911 | |
| mbed_official | 623:db79ecd649d0 | 8912 | |
| mbed_official | 623:db79ecd649d0 | 8913 | /******************** Bit definition for USB_OTG_GHWCFG3 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8914 | #define USB_OTG_GHWCFG3_LPMMode ((uint32_t)0x00004000) /* LPM mode specified for Mode of Operation */ |
| mbed_official | 623:db79ecd649d0 | 8915 | |
| mbed_official | 623:db79ecd649d0 | 8916 | /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8917 | #define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /* Enable best effort service latency */ |
| mbed_official | 623:db79ecd649d0 | 8918 | #define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /* LPM retry count status */ |
| mbed_official | 623:db79ecd649d0 | 8919 | #define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /* Send LPM transaction */ |
| mbed_official | 623:db79ecd649d0 | 8920 | #define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /* LPM retry count */ |
| mbed_official | 623:db79ecd649d0 | 8921 | #define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /* LPMCHIDX: */ |
| mbed_official | 623:db79ecd649d0 | 8922 | #define USB_OTG_GLPMCFG_L1ResumeOK ((uint32_t)0x00010000) /* Sleep State Resume OK */ |
| mbed_official | 623:db79ecd649d0 | 8923 | #define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /* Port sleep status */ |
| mbed_official | 623:db79ecd649d0 | 8924 | #define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /* LPM response */ |
| mbed_official | 623:db79ecd649d0 | 8925 | #define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /* L1 deep sleep enable */ |
| mbed_official | 623:db79ecd649d0 | 8926 | #define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /* BESL threshold */ |
| mbed_official | 623:db79ecd649d0 | 8927 | #define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /* L1 shallow sleep enable */ |
| mbed_official | 623:db79ecd649d0 | 8928 | #define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /* bRemoteWake value received with last ACKed LPM Token */ |
| mbed_official | 623:db79ecd649d0 | 8929 | #define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /* BESL value received with last ACKed LPM Token */ |
| mbed_official | 623:db79ecd649d0 | 8930 | #define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /* LPM Token acknowledge enable*/ |
| mbed_official | 623:db79ecd649d0 | 8931 | #define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /* LPM support enable */ |
| mbed_official | 623:db79ecd649d0 | 8932 | |
| mbed_official | 623:db79ecd649d0 | 8933 | |
| mbed_official | 623:db79ecd649d0 | 8934 | /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8935 | #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8936 | #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8937 | #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */ |
| mbed_official | 623:db79ecd649d0 | 8938 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */ |
| mbed_official | 623:db79ecd649d0 | 8939 | #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */ |
| mbed_official | 623:db79ecd649d0 | 8940 | #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */ |
| mbed_official | 623:db79ecd649d0 | 8941 | #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */ |
| mbed_official | 623:db79ecd649d0 | 8942 | #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8943 | #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8944 | |
| mbed_official | 623:db79ecd649d0 | 8945 | /******************** Bit definition for USB_OTG_HPRT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8946 | #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */ |
| mbed_official | 623:db79ecd649d0 | 8947 | #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */ |
| mbed_official | 623:db79ecd649d0 | 8948 | #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */ |
| mbed_official | 623:db79ecd649d0 | 8949 | #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */ |
| mbed_official | 623:db79ecd649d0 | 8950 | #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */ |
| mbed_official | 623:db79ecd649d0 | 8951 | #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */ |
| mbed_official | 623:db79ecd649d0 | 8952 | #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */ |
| mbed_official | 623:db79ecd649d0 | 8953 | #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */ |
| mbed_official | 623:db79ecd649d0 | 8954 | #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */ |
| mbed_official | 623:db79ecd649d0 | 8955 | |
| mbed_official | 623:db79ecd649d0 | 8956 | #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */ |
| mbed_official | 623:db79ecd649d0 | 8957 | #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8958 | #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8959 | #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */ |
| mbed_official | 623:db79ecd649d0 | 8960 | |
| mbed_official | 623:db79ecd649d0 | 8961 | #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */ |
| mbed_official | 623:db79ecd649d0 | 8962 | #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8963 | #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8964 | #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 8965 | #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 8966 | |
| mbed_official | 623:db79ecd649d0 | 8967 | #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */ |
| mbed_official | 623:db79ecd649d0 | 8968 | #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8969 | #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8970 | |
| mbed_official | 623:db79ecd649d0 | 8971 | /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8972 | #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8973 | #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8974 | #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */ |
| mbed_official | 623:db79ecd649d0 | 8975 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */ |
| mbed_official | 623:db79ecd649d0 | 8976 | #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */ |
| mbed_official | 623:db79ecd649d0 | 8977 | #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */ |
| mbed_official | 623:db79ecd649d0 | 8978 | #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */ |
| mbed_official | 623:db79ecd649d0 | 8979 | #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8980 | #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8981 | #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8982 | #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 8983 | |
| mbed_official | 623:db79ecd649d0 | 8984 | /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8985 | #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */ |
| mbed_official | 623:db79ecd649d0 | 8986 | #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */ |
| mbed_official | 623:db79ecd649d0 | 8987 | |
| mbed_official | 623:db79ecd649d0 | 8988 | /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ |
| mbed_official | 623:db79ecd649d0 | 8989 | #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ |
| mbed_official | 623:db79ecd649d0 | 8990 | #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */ |
| mbed_official | 623:db79ecd649d0 | 8991 | #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */ |
| mbed_official | 623:db79ecd649d0 | 8992 | #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */ |
| mbed_official | 623:db79ecd649d0 | 8993 | |
| mbed_official | 623:db79ecd649d0 | 8994 | #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */ |
| mbed_official | 623:db79ecd649d0 | 8995 | #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 8996 | #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 8997 | #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */ |
| mbed_official | 623:db79ecd649d0 | 8998 | |
| mbed_official | 623:db79ecd649d0 | 8999 | #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */ |
| mbed_official | 623:db79ecd649d0 | 9000 | #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9001 | #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9002 | #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 9003 | #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 9004 | #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */ |
| mbed_official | 623:db79ecd649d0 | 9005 | #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */ |
| mbed_official | 623:db79ecd649d0 | 9006 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */ |
| mbed_official | 623:db79ecd649d0 | 9007 | #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */ |
| mbed_official | 623:db79ecd649d0 | 9008 | #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */ |
| mbed_official | 623:db79ecd649d0 | 9009 | #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */ |
| mbed_official | 623:db79ecd649d0 | 9010 | |
| mbed_official | 623:db79ecd649d0 | 9011 | /******************** Bit definition for USB_OTG_HCCHAR register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9012 | #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ |
| mbed_official | 623:db79ecd649d0 | 9013 | |
| mbed_official | 623:db79ecd649d0 | 9014 | #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */ |
| mbed_official | 623:db79ecd649d0 | 9015 | #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9016 | #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9017 | #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 9018 | #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 9019 | #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */ |
| mbed_official | 623:db79ecd649d0 | 9020 | #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */ |
| mbed_official | 623:db79ecd649d0 | 9021 | |
| mbed_official | 623:db79ecd649d0 | 9022 | #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */ |
| mbed_official | 623:db79ecd649d0 | 9023 | #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9024 | #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9025 | |
| mbed_official | 623:db79ecd649d0 | 9026 | #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */ |
| mbed_official | 623:db79ecd649d0 | 9027 | #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9028 | #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9029 | |
| mbed_official | 623:db79ecd649d0 | 9030 | #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */ |
| mbed_official | 623:db79ecd649d0 | 9031 | #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9032 | #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9033 | #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 9034 | #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 9035 | #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 9036 | #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 9037 | #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 9038 | #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */ |
| mbed_official | 623:db79ecd649d0 | 9039 | #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */ |
| mbed_official | 623:db79ecd649d0 | 9040 | #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */ |
| mbed_official | 623:db79ecd649d0 | 9041 | |
| mbed_official | 623:db79ecd649d0 | 9042 | /******************** Bit definition for USB_OTG_HCSPLT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9043 | |
| mbed_official | 623:db79ecd649d0 | 9044 | #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */ |
| mbed_official | 623:db79ecd649d0 | 9045 | #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9046 | #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9047 | #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 9048 | #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 9049 | #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 9050 | #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 9051 | #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 9052 | |
| mbed_official | 623:db79ecd649d0 | 9053 | #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */ |
| mbed_official | 623:db79ecd649d0 | 9054 | #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9055 | #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9056 | #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */ |
| mbed_official | 623:db79ecd649d0 | 9057 | #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */ |
| mbed_official | 623:db79ecd649d0 | 9058 | #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */ |
| mbed_official | 623:db79ecd649d0 | 9059 | #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */ |
| mbed_official | 623:db79ecd649d0 | 9060 | #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */ |
| mbed_official | 623:db79ecd649d0 | 9061 | |
| mbed_official | 623:db79ecd649d0 | 9062 | #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */ |
| mbed_official | 623:db79ecd649d0 | 9063 | #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9064 | #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9065 | #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */ |
| mbed_official | 623:db79ecd649d0 | 9066 | #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */ |
| mbed_official | 623:db79ecd649d0 | 9067 | |
| mbed_official | 623:db79ecd649d0 | 9068 | /******************** Bit definition for USB_OTG_HCINT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9069 | #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */ |
| mbed_official | 623:db79ecd649d0 | 9070 | #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */ |
| mbed_official | 623:db79ecd649d0 | 9071 | #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */ |
| mbed_official | 623:db79ecd649d0 | 9072 | #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9073 | #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9074 | #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9075 | #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9076 | #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */ |
| mbed_official | 623:db79ecd649d0 | 9077 | #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */ |
| mbed_official | 623:db79ecd649d0 | 9078 | #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */ |
| mbed_official | 623:db79ecd649d0 | 9079 | #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */ |
| mbed_official | 623:db79ecd649d0 | 9080 | |
| mbed_official | 623:db79ecd649d0 | 9081 | /******************** Bit definition for USB_OTG_DIEPINT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9082 | #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9083 | #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9084 | #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */ |
| mbed_official | 623:db79ecd649d0 | 9085 | #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */ |
| mbed_official | 623:db79ecd649d0 | 9086 | #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */ |
| mbed_official | 623:db79ecd649d0 | 9087 | #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */ |
| mbed_official | 623:db79ecd649d0 | 9088 | #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */ |
| mbed_official | 623:db79ecd649d0 | 9089 | #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9090 | #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */ |
| mbed_official | 623:db79ecd649d0 | 9091 | #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9092 | #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9093 | |
| mbed_official | 623:db79ecd649d0 | 9094 | /******************** Bit definition for USB_OTG_HCINTMSK register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9095 | #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */ |
| mbed_official | 623:db79ecd649d0 | 9096 | #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */ |
| mbed_official | 623:db79ecd649d0 | 9097 | #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */ |
| mbed_official | 623:db79ecd649d0 | 9098 | #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 9099 | #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 9100 | #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 9101 | #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */ |
| mbed_official | 623:db79ecd649d0 | 9102 | #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */ |
| mbed_official | 623:db79ecd649d0 | 9103 | #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */ |
| mbed_official | 623:db79ecd649d0 | 9104 | #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */ |
| mbed_official | 623:db79ecd649d0 | 9105 | #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */ |
| mbed_official | 623:db79ecd649d0 | 9106 | |
| mbed_official | 623:db79ecd649d0 | 9107 | /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9108 | |
| mbed_official | 623:db79ecd649d0 | 9109 | #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */ |
| mbed_official | 623:db79ecd649d0 | 9110 | #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */ |
| mbed_official | 623:db79ecd649d0 | 9111 | #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */ |
| mbed_official | 623:db79ecd649d0 | 9112 | /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9113 | #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */ |
| mbed_official | 623:db79ecd649d0 | 9114 | #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */ |
| mbed_official | 623:db79ecd649d0 | 9115 | #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */ |
| mbed_official | 623:db79ecd649d0 | 9116 | #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */ |
| mbed_official | 623:db79ecd649d0 | 9117 | #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9118 | #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9119 | |
| mbed_official | 623:db79ecd649d0 | 9120 | /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9121 | #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */ |
| mbed_official | 623:db79ecd649d0 | 9122 | |
| mbed_official | 623:db79ecd649d0 | 9123 | /******************** Bit definition for USB_OTG_HCDMA register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9124 | #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */ |
| mbed_official | 623:db79ecd649d0 | 9125 | |
| mbed_official | 623:db79ecd649d0 | 9126 | /******************** Bit definition for USB_OTG_DTXFSTS register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9127 | #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space avail */ |
| mbed_official | 623:db79ecd649d0 | 9128 | |
| mbed_official | 623:db79ecd649d0 | 9129 | /******************** Bit definition for USB_OTG_DIEPTXF register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9130 | #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */ |
| mbed_official | 623:db79ecd649d0 | 9131 | #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */ |
| mbed_official | 623:db79ecd649d0 | 9132 | |
| mbed_official | 623:db79ecd649d0 | 9133 | /******************** Bit definition for USB_OTG_DOEPCTL register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9134 | |
| mbed_official | 623:db79ecd649d0 | 9135 | #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9136 | #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */ |
| mbed_official | 623:db79ecd649d0 | 9137 | #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */ |
| mbed_official | 623:db79ecd649d0 | 9138 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */ |
| mbed_official | 623:db79ecd649d0 | 9139 | #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */ |
| mbed_official | 623:db79ecd649d0 | 9140 | #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */ |
| mbed_official | 623:db79ecd649d0 | 9141 | #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9142 | #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9143 | #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */ |
| mbed_official | 623:db79ecd649d0 | 9144 | #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */ |
| mbed_official | 623:db79ecd649d0 | 9145 | #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */ |
| mbed_official | 623:db79ecd649d0 | 9146 | #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */ |
| mbed_official | 623:db79ecd649d0 | 9147 | #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */ |
| mbed_official | 623:db79ecd649d0 | 9148 | #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */ |
| mbed_official | 623:db79ecd649d0 | 9149 | |
| mbed_official | 623:db79ecd649d0 | 9150 | /******************** Bit definition for USB_OTG_DOEPINT register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9151 | #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9152 | #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9153 | #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */ |
| mbed_official | 623:db79ecd649d0 | 9154 | #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */ |
| mbed_official | 623:db79ecd649d0 | 9155 | #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */ |
| mbed_official | 623:db79ecd649d0 | 9156 | #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */ |
| mbed_official | 623:db79ecd649d0 | 9157 | |
| mbed_official | 623:db79ecd649d0 | 9158 | /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9159 | |
| mbed_official | 623:db79ecd649d0 | 9160 | #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */ |
| mbed_official | 623:db79ecd649d0 | 9161 | #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */ |
| mbed_official | 623:db79ecd649d0 | 9162 | |
| mbed_official | 623:db79ecd649d0 | 9163 | #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */ |
| mbed_official | 623:db79ecd649d0 | 9164 | #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9165 | #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9166 | |
| mbed_official | 623:db79ecd649d0 | 9167 | /******************** Bit definition for PCGCCTL register ********************/ |
| mbed_official | 623:db79ecd649d0 | 9168 | #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */ |
| mbed_official | 623:db79ecd649d0 | 9169 | #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */ |
| mbed_official | 623:db79ecd649d0 | 9170 | #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */ |
| mbed_official | 623:db79ecd649d0 | 9171 | |
| mbed_official | 623:db79ecd649d0 | 9172 | |
| mbed_official | 623:db79ecd649d0 | 9173 | /** |
| mbed_official | 623:db79ecd649d0 | 9174 | * @} |
| mbed_official | 623:db79ecd649d0 | 9175 | */ |
| mbed_official | 623:db79ecd649d0 | 9176 | |
| mbed_official | 623:db79ecd649d0 | 9177 | /** |
| mbed_official | 623:db79ecd649d0 | 9178 | * @} |
| mbed_official | 623:db79ecd649d0 | 9179 | */ |
| mbed_official | 623:db79ecd649d0 | 9180 | |
| mbed_official | 623:db79ecd649d0 | 9181 | /** @addtogroup Exported_macros |
| mbed_official | 623:db79ecd649d0 | 9182 | * @{ |
| mbed_official | 623:db79ecd649d0 | 9183 | */ |
| mbed_official | 623:db79ecd649d0 | 9184 | |
| mbed_official | 623:db79ecd649d0 | 9185 | /******************************* ADC Instances ********************************/ |
| mbed_official | 623:db79ecd649d0 | 9186 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
| mbed_official | 623:db79ecd649d0 | 9187 | ((INSTANCE) == ADC2) || \ |
| mbed_official | 623:db79ecd649d0 | 9188 | ((INSTANCE) == ADC3)) |
| mbed_official | 623:db79ecd649d0 | 9189 | |
| mbed_official | 623:db79ecd649d0 | 9190 | #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| mbed_official | 623:db79ecd649d0 | 9191 | |
| mbed_official | 623:db79ecd649d0 | 9192 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON) |
| mbed_official | 623:db79ecd649d0 | 9193 | |
| mbed_official | 623:db79ecd649d0 | 9194 | /******************************** CAN Instances ******************************/ |
| mbed_official | 623:db79ecd649d0 | 9195 | #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN) |
| mbed_official | 623:db79ecd649d0 | 9196 | |
| mbed_official | 623:db79ecd649d0 | 9197 | /******************************** COMP Instances ******************************/ |
| mbed_official | 623:db79ecd649d0 | 9198 | #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ |
| mbed_official | 623:db79ecd649d0 | 9199 | ((INSTANCE) == COMP2)) |
| mbed_official | 623:db79ecd649d0 | 9200 | |
| mbed_official | 623:db79ecd649d0 | 9201 | /******************** COMP Instances with window mode capability **************/ |
| mbed_official | 623:db79ecd649d0 | 9202 | #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| mbed_official | 623:db79ecd649d0 | 9203 | |
| mbed_official | 623:db79ecd649d0 | 9204 | /******************************* CRC Instances ********************************/ |
| mbed_official | 623:db79ecd649d0 | 9205 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| mbed_official | 623:db79ecd649d0 | 9206 | |
| mbed_official | 623:db79ecd649d0 | 9207 | /******************************* DAC Instances ********************************/ |
| mbed_official | 623:db79ecd649d0 | 9208 | #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| mbed_official | 623:db79ecd649d0 | 9209 | |
| mbed_official | 623:db79ecd649d0 | 9210 | /****************************** DFSDM Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9211 | #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Filter0) || \ |
| mbed_official | 623:db79ecd649d0 | 9212 | ((INSTANCE) == DFSDM_Filter1) || \ |
| mbed_official | 623:db79ecd649d0 | 9213 | ((INSTANCE) == DFSDM_Filter2) || \ |
| mbed_official | 623:db79ecd649d0 | 9214 | ((INSTANCE) == DFSDM_Filter3)) |
| mbed_official | 623:db79ecd649d0 | 9215 | |
| mbed_official | 623:db79ecd649d0 | 9216 | #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Channel0) || \ |
| mbed_official | 623:db79ecd649d0 | 9217 | ((INSTANCE) == DFSDM_Channel1) || \ |
| mbed_official | 623:db79ecd649d0 | 9218 | ((INSTANCE) == DFSDM_Channel2) || \ |
| mbed_official | 623:db79ecd649d0 | 9219 | ((INSTANCE) == DFSDM_Channel3) || \ |
| mbed_official | 623:db79ecd649d0 | 9220 | ((INSTANCE) == DFSDM_Channel4) || \ |
| mbed_official | 623:db79ecd649d0 | 9221 | ((INSTANCE) == DFSDM_Channel5) || \ |
| mbed_official | 623:db79ecd649d0 | 9222 | ((INSTANCE) == DFSDM_Channel6) || \ |
| mbed_official | 623:db79ecd649d0 | 9223 | ((INSTANCE) == DFSDM_Channel7)) |
| mbed_official | 623:db79ecd649d0 | 9224 | |
| mbed_official | 623:db79ecd649d0 | 9225 | /******************************** DMA Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9226 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| mbed_official | 623:db79ecd649d0 | 9227 | ((INSTANCE) == DMA1_Channel2) || \ |
| mbed_official | 623:db79ecd649d0 | 9228 | ((INSTANCE) == DMA1_Channel3) || \ |
| mbed_official | 623:db79ecd649d0 | 9229 | ((INSTANCE) == DMA1_Channel4) || \ |
| mbed_official | 623:db79ecd649d0 | 9230 | ((INSTANCE) == DMA1_Channel5) || \ |
| mbed_official | 623:db79ecd649d0 | 9231 | ((INSTANCE) == DMA1_Channel6) || \ |
| mbed_official | 623:db79ecd649d0 | 9232 | ((INSTANCE) == DMA1_Channel7) || \ |
| mbed_official | 623:db79ecd649d0 | 9233 | ((INSTANCE) == DMA2_Channel1) || \ |
| mbed_official | 623:db79ecd649d0 | 9234 | ((INSTANCE) == DMA2_Channel2) || \ |
| mbed_official | 623:db79ecd649d0 | 9235 | ((INSTANCE) == DMA2_Channel3) || \ |
| mbed_official | 623:db79ecd649d0 | 9236 | ((INSTANCE) == DMA2_Channel4) || \ |
| mbed_official | 623:db79ecd649d0 | 9237 | ((INSTANCE) == DMA2_Channel5) || \ |
| mbed_official | 623:db79ecd649d0 | 9238 | ((INSTANCE) == DMA2_Channel6) || \ |
| mbed_official | 623:db79ecd649d0 | 9239 | ((INSTANCE) == DMA2_Channel7)) |
| mbed_official | 623:db79ecd649d0 | 9240 | |
| mbed_official | 623:db79ecd649d0 | 9241 | /******************************* GPIO Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9242 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
| mbed_official | 623:db79ecd649d0 | 9243 | ((INSTANCE) == GPIOB) || \ |
| mbed_official | 623:db79ecd649d0 | 9244 | ((INSTANCE) == GPIOC) || \ |
| mbed_official | 623:db79ecd649d0 | 9245 | ((INSTANCE) == GPIOD) || \ |
| mbed_official | 623:db79ecd649d0 | 9246 | ((INSTANCE) == GPIOE) || \ |
| mbed_official | 623:db79ecd649d0 | 9247 | ((INSTANCE) == GPIOF) || \ |
| mbed_official | 623:db79ecd649d0 | 9248 | ((INSTANCE) == GPIOG) || \ |
| mbed_official | 623:db79ecd649d0 | 9249 | ((INSTANCE) == GPIOH)) |
| mbed_official | 623:db79ecd649d0 | 9250 | |
| mbed_official | 623:db79ecd649d0 | 9251 | /******************************* GPIO AF Instances ****************************/ |
| mbed_official | 623:db79ecd649d0 | 9252 | /* On L4, all GPIO Bank support AF */ |
| mbed_official | 623:db79ecd649d0 | 9253 | #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| mbed_official | 623:db79ecd649d0 | 9254 | |
| mbed_official | 623:db79ecd649d0 | 9255 | /**************************** GPIO Lock Instances *****************************/ |
| mbed_official | 623:db79ecd649d0 | 9256 | /* On L4, all GPIO Bank support the Lock mechanism */ |
| mbed_official | 623:db79ecd649d0 | 9257 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| mbed_official | 623:db79ecd649d0 | 9258 | |
| mbed_official | 623:db79ecd649d0 | 9259 | /******************************** I2C Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9260 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
| mbed_official | 623:db79ecd649d0 | 9261 | ((INSTANCE) == I2C2) || \ |
| mbed_official | 623:db79ecd649d0 | 9262 | ((INSTANCE) == I2C3)) |
| mbed_official | 623:db79ecd649d0 | 9263 | |
| mbed_official | 623:db79ecd649d0 | 9264 | /******************************* LCD Instances ********************************/ |
| mbed_official | 623:db79ecd649d0 | 9265 | #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD) |
| mbed_official | 623:db79ecd649d0 | 9266 | |
| mbed_official | 623:db79ecd649d0 | 9267 | /******************************* HCD Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9268 | #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS) |
| mbed_official | 623:db79ecd649d0 | 9269 | |
| mbed_official | 623:db79ecd649d0 | 9270 | /****************************** OPAMP Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9271 | #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \ |
| mbed_official | 623:db79ecd649d0 | 9272 | ((INSTANCE) == OPAMP2)) |
| mbed_official | 623:db79ecd649d0 | 9273 | |
| mbed_official | 623:db79ecd649d0 | 9274 | /******************************* PCD Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9275 | #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS) |
| mbed_official | 623:db79ecd649d0 | 9276 | |
| mbed_official | 623:db79ecd649d0 | 9277 | /******************************* QSPI Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9278 | #define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI) |
| mbed_official | 623:db79ecd649d0 | 9279 | |
| mbed_official | 623:db79ecd649d0 | 9280 | /******************************* RNG Instances ********************************/ |
| mbed_official | 623:db79ecd649d0 | 9281 | #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| mbed_official | 623:db79ecd649d0 | 9282 | |
| mbed_official | 623:db79ecd649d0 | 9283 | /****************************** RTC Instances *********************************/ |
| mbed_official | 623:db79ecd649d0 | 9284 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| mbed_official | 623:db79ecd649d0 | 9285 | |
| mbed_official | 623:db79ecd649d0 | 9286 | /******************************** SAI Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9287 | #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \ |
| mbed_official | 623:db79ecd649d0 | 9288 | ((INSTANCE) == SAI1_Block_B) || \ |
| mbed_official | 623:db79ecd649d0 | 9289 | ((INSTANCE) == SAI2_Block_A) || \ |
| mbed_official | 623:db79ecd649d0 | 9290 | ((INSTANCE) == SAI2_Block_B)) |
| mbed_official | 623:db79ecd649d0 | 9291 | |
| mbed_official | 623:db79ecd649d0 | 9292 | /****************************** SDMMC Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9293 | #define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1) |
| mbed_official | 623:db79ecd649d0 | 9294 | |
| mbed_official | 623:db79ecd649d0 | 9295 | /****************************** SMBUS Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9296 | #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
| mbed_official | 623:db79ecd649d0 | 9297 | ((INSTANCE) == I2C2) || \ |
| mbed_official | 623:db79ecd649d0 | 9298 | ((INSTANCE) == I2C3)) |
| mbed_official | 623:db79ecd649d0 | 9299 | |
| mbed_official | 623:db79ecd649d0 | 9300 | /******************************** SPI Instances *******************************/ |
| mbed_official | 623:db79ecd649d0 | 9301 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
| mbed_official | 623:db79ecd649d0 | 9302 | ((INSTANCE) == SPI2) || \ |
| mbed_official | 623:db79ecd649d0 | 9303 | ((INSTANCE) == SPI3)) |
| mbed_official | 623:db79ecd649d0 | 9304 | |
| mbed_official | 623:db79ecd649d0 | 9305 | /******************************** SWPMI Instances *****************************/ |
| mbed_official | 623:db79ecd649d0 | 9306 | #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| mbed_official | 623:db79ecd649d0 | 9307 | |
| mbed_official | 623:db79ecd649d0 | 9308 | /****************** LPTIM Instances : All supported instances *****************/ |
| mbed_official | 623:db79ecd649d0 | 9309 | #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9310 | ((INSTANCE) == LPTIM2)) |
| mbed_official | 623:db79ecd649d0 | 9311 | |
| mbed_official | 623:db79ecd649d0 | 9312 | /****************** TIM Instances : All supported instances *******************/ |
| mbed_official | 623:db79ecd649d0 | 9313 | #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9314 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9315 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9316 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9317 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9318 | ((INSTANCE) == TIM6) || \ |
| mbed_official | 623:db79ecd649d0 | 9319 | ((INSTANCE) == TIM7) || \ |
| mbed_official | 623:db79ecd649d0 | 9320 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9321 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9322 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9323 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9324 | |
| mbed_official | 623:db79ecd649d0 | 9325 | /****************** TIM Instances : supporting 32 bits counter ****************/ |
| mbed_official | 623:db79ecd649d0 | 9326 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9327 | ((INSTANCE) == TIM5)) |
| mbed_official | 623:db79ecd649d0 | 9328 | |
| mbed_official | 623:db79ecd649d0 | 9329 | /****************** TIM Instances : supporting the break function *************/ |
| mbed_official | 623:db79ecd649d0 | 9330 | #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9331 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9332 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9333 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9334 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9335 | |
| mbed_official | 623:db79ecd649d0 | 9336 | /************** TIM Instances : supporting Break source selection *************/ |
| mbed_official | 623:db79ecd649d0 | 9337 | #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9338 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9339 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9340 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9341 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9342 | |
| mbed_official | 623:db79ecd649d0 | 9343 | /****************** TIM Instances : supporting 2 break inputs *****************/ |
| mbed_official | 623:db79ecd649d0 | 9344 | #define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9345 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9346 | |
| mbed_official | 623:db79ecd649d0 | 9347 | /************* TIM Instances : at least 1 capture/compare channel *************/ |
| mbed_official | 623:db79ecd649d0 | 9348 | #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9349 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9350 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9351 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9352 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9353 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9354 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9355 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9356 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9357 | |
| mbed_official | 623:db79ecd649d0 | 9358 | /************ TIM Instances : at least 2 capture/compare channels *************/ |
| mbed_official | 623:db79ecd649d0 | 9359 | #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9360 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9361 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9362 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9363 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9364 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9365 | ((INSTANCE) == TIM15)) |
| mbed_official | 623:db79ecd649d0 | 9366 | |
| mbed_official | 623:db79ecd649d0 | 9367 | /************ TIM Instances : at least 3 capture/compare channels *************/ |
| mbed_official | 623:db79ecd649d0 | 9368 | #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9369 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9370 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9371 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9372 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9373 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9374 | |
| mbed_official | 623:db79ecd649d0 | 9375 | /************ TIM Instances : at least 4 capture/compare channels *************/ |
| mbed_official | 623:db79ecd649d0 | 9376 | #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9377 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9378 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9379 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9380 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9381 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9382 | |
| mbed_official | 623:db79ecd649d0 | 9383 | /****************** TIM Instances : at least 5 capture/compare channels *******/ |
| mbed_official | 623:db79ecd649d0 | 9384 | #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9385 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9386 | |
| mbed_official | 623:db79ecd649d0 | 9387 | /****************** TIM Instances : at least 6 capture/compare channels *******/ |
| mbed_official | 623:db79ecd649d0 | 9388 | #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9389 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9390 | |
| mbed_official | 623:db79ecd649d0 | 9391 | /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/ |
| mbed_official | 623:db79ecd649d0 | 9392 | #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9393 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9394 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9395 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9396 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9397 | |
| mbed_official | 623:db79ecd649d0 | 9398 | /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ |
| mbed_official | 623:db79ecd649d0 | 9399 | #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9400 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9401 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9402 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9403 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9404 | ((INSTANCE) == TIM6) || \ |
| mbed_official | 623:db79ecd649d0 | 9405 | ((INSTANCE) == TIM7) || \ |
| mbed_official | 623:db79ecd649d0 | 9406 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9407 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9408 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9409 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9410 | |
| mbed_official | 623:db79ecd649d0 | 9411 | /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ |
| mbed_official | 623:db79ecd649d0 | 9412 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9413 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9414 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9415 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9416 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9417 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9418 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9419 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9420 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9421 | |
| mbed_official | 623:db79ecd649d0 | 9422 | /******************** TIM Instances : DMA burst feature ***********************/ |
| mbed_official | 623:db79ecd649d0 | 9423 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9424 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9425 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9426 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9427 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9428 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9429 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9430 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9431 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9432 | |
| mbed_official | 623:db79ecd649d0 | 9433 | /******************* TIM Instances : output(s) available **********************/ |
| mbed_official | 623:db79ecd649d0 | 9434 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
| mbed_official | 623:db79ecd649d0 | 9435 | ((((INSTANCE) == TIM1) && \ |
| mbed_official | 623:db79ecd649d0 | 9436 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 623:db79ecd649d0 | 9437 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 623:db79ecd649d0 | 9438 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 623:db79ecd649d0 | 9439 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
| mbed_official | 623:db79ecd649d0 | 9440 | ((CHANNEL) == TIM_CHANNEL_5) || \ |
| mbed_official | 623:db79ecd649d0 | 9441 | ((CHANNEL) == TIM_CHANNEL_6))) \ |
| mbed_official | 623:db79ecd649d0 | 9442 | || \ |
| mbed_official | 623:db79ecd649d0 | 9443 | (((INSTANCE) == TIM2) && \ |
| mbed_official | 623:db79ecd649d0 | 9444 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 623:db79ecd649d0 | 9445 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 623:db79ecd649d0 | 9446 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 623:db79ecd649d0 | 9447 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 623:db79ecd649d0 | 9448 | || \ |
| mbed_official | 623:db79ecd649d0 | 9449 | (((INSTANCE) == TIM3) && \ |
| mbed_official | 623:db79ecd649d0 | 9450 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 623:db79ecd649d0 | 9451 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 623:db79ecd649d0 | 9452 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 623:db79ecd649d0 | 9453 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 623:db79ecd649d0 | 9454 | || \ |
| mbed_official | 623:db79ecd649d0 | 9455 | (((INSTANCE) == TIM4) && \ |
| mbed_official | 623:db79ecd649d0 | 9456 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 623:db79ecd649d0 | 9457 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 623:db79ecd649d0 | 9458 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 623:db79ecd649d0 | 9459 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 623:db79ecd649d0 | 9460 | || \ |
| mbed_official | 623:db79ecd649d0 | 9461 | (((INSTANCE) == TIM5) && \ |
| mbed_official | 623:db79ecd649d0 | 9462 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 623:db79ecd649d0 | 9463 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 623:db79ecd649d0 | 9464 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 623:db79ecd649d0 | 9465 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| mbed_official | 623:db79ecd649d0 | 9466 | || \ |
| mbed_official | 623:db79ecd649d0 | 9467 | (((INSTANCE) == TIM8) && \ |
| mbed_official | 623:db79ecd649d0 | 9468 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 623:db79ecd649d0 | 9469 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 623:db79ecd649d0 | 9470 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| mbed_official | 623:db79ecd649d0 | 9471 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
| mbed_official | 623:db79ecd649d0 | 9472 | ((CHANNEL) == TIM_CHANNEL_5) || \ |
| mbed_official | 623:db79ecd649d0 | 9473 | ((CHANNEL) == TIM_CHANNEL_6))) \ |
| mbed_official | 623:db79ecd649d0 | 9474 | || \ |
| mbed_official | 623:db79ecd649d0 | 9475 | (((INSTANCE) == TIM15) && \ |
| mbed_official | 623:db79ecd649d0 | 9476 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 623:db79ecd649d0 | 9477 | ((CHANNEL) == TIM_CHANNEL_2))) \ |
| mbed_official | 623:db79ecd649d0 | 9478 | || \ |
| mbed_official | 623:db79ecd649d0 | 9479 | (((INSTANCE) == TIM16) && \ |
| mbed_official | 623:db79ecd649d0 | 9480 | (((CHANNEL) == TIM_CHANNEL_1))) \ |
| mbed_official | 623:db79ecd649d0 | 9481 | || \ |
| mbed_official | 623:db79ecd649d0 | 9482 | (((INSTANCE) == TIM17) && \ |
| mbed_official | 623:db79ecd649d0 | 9483 | (((CHANNEL) == TIM_CHANNEL_1)))) |
| mbed_official | 623:db79ecd649d0 | 9484 | |
| mbed_official | 623:db79ecd649d0 | 9485 | /****************** TIM Instances : supporting complementary output(s) ********/ |
| mbed_official | 623:db79ecd649d0 | 9486 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
| mbed_official | 623:db79ecd649d0 | 9487 | ((((INSTANCE) == TIM1) && \ |
| mbed_official | 623:db79ecd649d0 | 9488 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 623:db79ecd649d0 | 9489 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 623:db79ecd649d0 | 9490 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
| mbed_official | 623:db79ecd649d0 | 9491 | || \ |
| mbed_official | 623:db79ecd649d0 | 9492 | (((INSTANCE) == TIM8) && \ |
| mbed_official | 623:db79ecd649d0 | 9493 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| mbed_official | 623:db79ecd649d0 | 9494 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| mbed_official | 623:db79ecd649d0 | 9495 | ((CHANNEL) == TIM_CHANNEL_3))) \ |
| mbed_official | 623:db79ecd649d0 | 9496 | || \ |
| mbed_official | 623:db79ecd649d0 | 9497 | (((INSTANCE) == TIM15) && \ |
| mbed_official | 623:db79ecd649d0 | 9498 | ((CHANNEL) == TIM_CHANNEL_1)) \ |
| mbed_official | 623:db79ecd649d0 | 9499 | || \ |
| mbed_official | 623:db79ecd649d0 | 9500 | (((INSTANCE) == TIM16) && \ |
| mbed_official | 623:db79ecd649d0 | 9501 | ((CHANNEL) == TIM_CHANNEL_1)) \ |
| mbed_official | 623:db79ecd649d0 | 9502 | || \ |
| mbed_official | 623:db79ecd649d0 | 9503 | (((INSTANCE) == TIM17) && \ |
| mbed_official | 623:db79ecd649d0 | 9504 | ((CHANNEL) == TIM_CHANNEL_1))) |
| mbed_official | 623:db79ecd649d0 | 9505 | |
| mbed_official | 623:db79ecd649d0 | 9506 | /****************** TIM Instances : supporting clock division *****************/ |
| mbed_official | 623:db79ecd649d0 | 9507 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9508 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9509 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9510 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9511 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9512 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9513 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9514 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9515 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9516 | |
| mbed_official | 623:db79ecd649d0 | 9517 | /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ |
| mbed_official | 623:db79ecd649d0 | 9518 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9519 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9520 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9521 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9522 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9523 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9524 | ((INSTANCE) == TIM15)) |
| mbed_official | 623:db79ecd649d0 | 9525 | |
| mbed_official | 623:db79ecd649d0 | 9526 | /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ |
| mbed_official | 623:db79ecd649d0 | 9527 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9528 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9529 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9530 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9531 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9532 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9533 | |
| mbed_official | 623:db79ecd649d0 | 9534 | /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ |
| mbed_official | 623:db79ecd649d0 | 9535 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9536 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9537 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9538 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9539 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9540 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9541 | ((INSTANCE) == TIM15)) |
| mbed_official | 623:db79ecd649d0 | 9542 | |
| mbed_official | 623:db79ecd649d0 | 9543 | /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ |
| mbed_official | 623:db79ecd649d0 | 9544 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9545 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9546 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9547 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9548 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9549 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9550 | ((INSTANCE) == TIM15)) |
| mbed_official | 623:db79ecd649d0 | 9551 | |
| mbed_official | 623:db79ecd649d0 | 9552 | /****************** TIM Instances : supporting combined 3-phase PWM mode ******/ |
| mbed_official | 623:db79ecd649d0 | 9553 | #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9554 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9555 | |
| mbed_official | 623:db79ecd649d0 | 9556 | /****************** TIM Instances : supporting commutation event generation ***/ |
| mbed_official | 623:db79ecd649d0 | 9557 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9558 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9559 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9560 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9561 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9562 | |
| mbed_official | 623:db79ecd649d0 | 9563 | /****************** TIM Instances : supporting counting mode selection ********/ |
| mbed_official | 623:db79ecd649d0 | 9564 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9565 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9566 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9567 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9568 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9569 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9570 | |
| mbed_official | 623:db79ecd649d0 | 9571 | /****************** TIM Instances : supporting encoder interface **************/ |
| mbed_official | 623:db79ecd649d0 | 9572 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9573 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9574 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9575 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9576 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9577 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9578 | |
| mbed_official | 623:db79ecd649d0 | 9579 | /**************** TIM Instances : external trigger input available ************/ |
| mbed_official | 623:db79ecd649d0 | 9580 | #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9581 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9582 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9583 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9584 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9585 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9586 | |
| mbed_official | 623:db79ecd649d0 | 9587 | /************* TIM Instances : supporting ETR source selection ***************/ |
| mbed_official | 623:db79ecd649d0 | 9588 | #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9589 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9590 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9591 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9592 | |
| mbed_official | 623:db79ecd649d0 | 9593 | /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ |
| mbed_official | 623:db79ecd649d0 | 9594 | #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9595 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9596 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9597 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9598 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9599 | ((INSTANCE) == TIM6) || \ |
| mbed_official | 623:db79ecd649d0 | 9600 | ((INSTANCE) == TIM7) || \ |
| mbed_official | 623:db79ecd649d0 | 9601 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9602 | ((INSTANCE) == TIM15)) |
| mbed_official | 623:db79ecd649d0 | 9603 | |
| mbed_official | 623:db79ecd649d0 | 9604 | /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ |
| mbed_official | 623:db79ecd649d0 | 9605 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9606 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9607 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9608 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9609 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9610 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9611 | ((INSTANCE) == TIM15)) |
| mbed_official | 623:db79ecd649d0 | 9612 | |
| mbed_official | 623:db79ecd649d0 | 9613 | /****************** TIM Instances : supporting OCxREF clear *******************/ |
| mbed_official | 623:db79ecd649d0 | 9614 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9615 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9616 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9617 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9618 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9619 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9620 | |
| mbed_official | 623:db79ecd649d0 | 9621 | /****************** TIM Instances : remapping capability **********************/ |
| mbed_official | 623:db79ecd649d0 | 9622 | #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9623 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9624 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9625 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9626 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9627 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9628 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9629 | |
| mbed_official | 623:db79ecd649d0 | 9630 | /****************** TIM Instances : supporting repetition counter *************/ |
| mbed_official | 623:db79ecd649d0 | 9631 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9632 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9633 | ((INSTANCE) == TIM15) || \ |
| mbed_official | 623:db79ecd649d0 | 9634 | ((INSTANCE) == TIM16) || \ |
| mbed_official | 623:db79ecd649d0 | 9635 | ((INSTANCE) == TIM17)) |
| mbed_official | 623:db79ecd649d0 | 9636 | |
| mbed_official | 623:db79ecd649d0 | 9637 | /****************** TIM Instances : supporting synchronization ****************/ |
| mbed_official | 623:db79ecd649d0 | 9638 | #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE) |
| mbed_official | 623:db79ecd649d0 | 9639 | |
| mbed_official | 623:db79ecd649d0 | 9640 | /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ |
| mbed_official | 623:db79ecd649d0 | 9641 | #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9642 | ((INSTANCE) == TIM8)) |
| mbed_official | 623:db79ecd649d0 | 9643 | |
| mbed_official | 623:db79ecd649d0 | 9644 | /******************* TIM Instances : Timer input XOR function *****************/ |
| mbed_official | 623:db79ecd649d0 | 9645 | #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
| mbed_official | 623:db79ecd649d0 | 9646 | ((INSTANCE) == TIM2) || \ |
| mbed_official | 623:db79ecd649d0 | 9647 | ((INSTANCE) == TIM3) || \ |
| mbed_official | 623:db79ecd649d0 | 9648 | ((INSTANCE) == TIM4) || \ |
| mbed_official | 623:db79ecd649d0 | 9649 | ((INSTANCE) == TIM5) || \ |
| mbed_official | 623:db79ecd649d0 | 9650 | ((INSTANCE) == TIM8) || \ |
| mbed_official | 623:db79ecd649d0 | 9651 | ((INSTANCE) == TIM15)) |
| mbed_official | 623:db79ecd649d0 | 9652 | |
| mbed_official | 623:db79ecd649d0 | 9653 | /****************************** TSC Instances *********************************/ |
| mbed_official | 623:db79ecd649d0 | 9654 | #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC) |
| mbed_official | 623:db79ecd649d0 | 9655 | |
| mbed_official | 623:db79ecd649d0 | 9656 | /******************** UART Instances : Asynchronous mode **********************/ |
| mbed_official | 623:db79ecd649d0 | 9657 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9658 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9659 | ((INSTANCE) == USART3) || \ |
| mbed_official | 623:db79ecd649d0 | 9660 | ((INSTANCE) == UART4) || \ |
| mbed_official | 623:db79ecd649d0 | 9661 | ((INSTANCE) == UART5) || \ |
| mbed_official | 623:db79ecd649d0 | 9662 | ((INSTANCE) == LPUART1)) |
| mbed_official | 623:db79ecd649d0 | 9663 | |
| mbed_official | 623:db79ecd649d0 | 9664 | |
| mbed_official | 623:db79ecd649d0 | 9665 | /******************** USART Instances : Synchronous mode **********************/ |
| mbed_official | 623:db79ecd649d0 | 9666 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9667 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9668 | ((INSTANCE) == USART3)) |
| mbed_official | 623:db79ecd649d0 | 9669 | |
| mbed_official | 623:db79ecd649d0 | 9670 | /****************** UART Instances : Hardware Flow control ********************/ |
| mbed_official | 623:db79ecd649d0 | 9671 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9672 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9673 | ((INSTANCE) == USART3) || \ |
| mbed_official | 623:db79ecd649d0 | 9674 | ((INSTANCE) == UART4) || \ |
| mbed_official | 623:db79ecd649d0 | 9675 | ((INSTANCE) == UART5) || \ |
| mbed_official | 623:db79ecd649d0 | 9676 | ((INSTANCE) == LPUART1)) |
| mbed_official | 623:db79ecd649d0 | 9677 | |
| mbed_official | 623:db79ecd649d0 | 9678 | |
| mbed_official | 623:db79ecd649d0 | 9679 | /********************* USART Instances : Smard card mode ***********************/ |
| mbed_official | 623:db79ecd649d0 | 9680 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9681 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9682 | ((INSTANCE) == USART3)) |
| mbed_official | 623:db79ecd649d0 | 9683 | |
| mbed_official | 623:db79ecd649d0 | 9684 | /****************** UART Instances : Auto Baud Rate detection ****************/ |
| mbed_official | 623:db79ecd649d0 | 9685 | #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9686 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9687 | ((INSTANCE) == USART3) || \ |
| mbed_official | 623:db79ecd649d0 | 9688 | ((INSTANCE) == UART4) || \ |
| mbed_official | 623:db79ecd649d0 | 9689 | ((INSTANCE) == UART5)) |
| mbed_official | 623:db79ecd649d0 | 9690 | |
| mbed_official | 623:db79ecd649d0 | 9691 | /******************** UART Instances : Half-Duplex mode **********************/ |
| mbed_official | 623:db79ecd649d0 | 9692 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9693 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9694 | ((INSTANCE) == USART3) || \ |
| mbed_official | 623:db79ecd649d0 | 9695 | ((INSTANCE) == UART4) || \ |
| mbed_official | 623:db79ecd649d0 | 9696 | ((INSTANCE) == UART5) || \ |
| mbed_official | 623:db79ecd649d0 | 9697 | ((INSTANCE) == LPUART1)) |
| mbed_official | 623:db79ecd649d0 | 9698 | |
| mbed_official | 623:db79ecd649d0 | 9699 | /******************** UART Instances : LIN mode **********************/ |
| mbed_official | 623:db79ecd649d0 | 9700 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9701 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9702 | ((INSTANCE) == USART3) || \ |
| mbed_official | 623:db79ecd649d0 | 9703 | ((INSTANCE) == UART4) || \ |
| mbed_official | 623:db79ecd649d0 | 9704 | ((INSTANCE) == UART5)) |
| mbed_official | 623:db79ecd649d0 | 9705 | |
| mbed_official | 623:db79ecd649d0 | 9706 | /******************** UART Instances : Wake-up from Stop mode **********************/ |
| mbed_official | 623:db79ecd649d0 | 9707 | #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9708 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9709 | ((INSTANCE) == USART3) || \ |
| mbed_official | 623:db79ecd649d0 | 9710 | ((INSTANCE) == UART4) || \ |
| mbed_official | 623:db79ecd649d0 | 9711 | ((INSTANCE) == UART5) || \ |
| mbed_official | 623:db79ecd649d0 | 9712 | ((INSTANCE) == LPUART1)) |
| mbed_official | 623:db79ecd649d0 | 9713 | |
| mbed_official | 623:db79ecd649d0 | 9714 | /****************** UART Instances : Driver Enable *****************/ |
| mbed_official | 623:db79ecd649d0 | 9715 | #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9716 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9717 | ((INSTANCE) == USART3) || \ |
| mbed_official | 623:db79ecd649d0 | 9718 | ((INSTANCE) == UART4) || \ |
| mbed_official | 623:db79ecd649d0 | 9719 | ((INSTANCE) == UART5) || \ |
| mbed_official | 623:db79ecd649d0 | 9720 | ((INSTANCE) == LPUART1)) |
| mbed_official | 623:db79ecd649d0 | 9721 | |
| mbed_official | 623:db79ecd649d0 | 9722 | /******************** UART Instances : Half-Duplex mode **********************/ |
| mbed_official | 623:db79ecd649d0 | 9723 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9724 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9725 | ((INSTANCE) == USART3) || \ |
| mbed_official | 623:db79ecd649d0 | 9726 | ((INSTANCE) == UART4) || \ |
| mbed_official | 623:db79ecd649d0 | 9727 | ((INSTANCE) == UART5) || \ |
| mbed_official | 623:db79ecd649d0 | 9728 | ((INSTANCE) == LPUART1)) |
| mbed_official | 623:db79ecd649d0 | 9729 | |
| mbed_official | 623:db79ecd649d0 | 9730 | /******************** UART Instances : LIN mode **********************/ |
| mbed_official | 623:db79ecd649d0 | 9731 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9732 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9733 | ((INSTANCE) == USART3) || \ |
| mbed_official | 623:db79ecd649d0 | 9734 | ((INSTANCE) == UART4) || \ |
| mbed_official | 623:db79ecd649d0 | 9735 | ((INSTANCE) == UART5)) |
| mbed_official | 623:db79ecd649d0 | 9736 | |
| mbed_official | 623:db79ecd649d0 | 9737 | /*********************** UART Instances : IRDA mode ***************************/ |
| mbed_official | 623:db79ecd649d0 | 9738 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| mbed_official | 623:db79ecd649d0 | 9739 | ((INSTANCE) == USART2) || \ |
| mbed_official | 623:db79ecd649d0 | 9740 | ((INSTANCE) == USART3) || \ |
| mbed_official | 623:db79ecd649d0 | 9741 | ((INSTANCE) == UART4) || \ |
| mbed_official | 623:db79ecd649d0 | 9742 | ((INSTANCE) == UART5)) |
| mbed_official | 623:db79ecd649d0 | 9743 | |
| mbed_official | 623:db79ecd649d0 | 9744 | /****************************** IWDG Instances ********************************/ |
| mbed_official | 623:db79ecd649d0 | 9745 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
| mbed_official | 623:db79ecd649d0 | 9746 | |
| mbed_official | 623:db79ecd649d0 | 9747 | /****************************** WWDG Instances ********************************/ |
| mbed_official | 623:db79ecd649d0 | 9748 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
| mbed_official | 623:db79ecd649d0 | 9749 | |
| mbed_official | 623:db79ecd649d0 | 9750 | /** |
| mbed_official | 623:db79ecd649d0 | 9751 | * @} |
| mbed_official | 623:db79ecd649d0 | 9752 | */ |
| mbed_official | 623:db79ecd649d0 | 9753 | |
| mbed_official | 623:db79ecd649d0 | 9754 | |
| mbed_official | 623:db79ecd649d0 | 9755 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 9756 | /* For a painless codes migration between the STM32L4xx device product */ |
| mbed_official | 623:db79ecd649d0 | 9757 | /* lines, the aliases defined below are put in place to overcome the */ |
| mbed_official | 623:db79ecd649d0 | 9758 | /* differences in the interrupt handlers and IRQn definitions. */ |
| mbed_official | 623:db79ecd649d0 | 9759 | /* No need to update developed interrupt code when moving across */ |
| mbed_official | 623:db79ecd649d0 | 9760 | /* product lines within the same STM32L4 Family */ |
| mbed_official | 623:db79ecd649d0 | 9761 | /******************************************************************************/ |
| mbed_official | 623:db79ecd649d0 | 9762 | |
| mbed_official | 623:db79ecd649d0 | 9763 | /* Aliases for __IRQn */ |
| mbed_official | 623:db79ecd649d0 | 9764 | #define TIM8_IRQn TIM8_UP_IRQn |
| mbed_official | 623:db79ecd649d0 | 9765 | |
| mbed_official | 623:db79ecd649d0 | 9766 | /* Aliases for __IRQHandler */ |
| mbed_official | 623:db79ecd649d0 | 9767 | #define TIM8_IRQHandler TIM8_UP_IRQHandler |
| mbed_official | 623:db79ecd649d0 | 9768 | |
| mbed_official | 623:db79ecd649d0 | 9769 | |
| mbed_official | 623:db79ecd649d0 | 9770 | #ifdef __cplusplus |
| mbed_official | 623:db79ecd649d0 | 9771 | } |
| mbed_official | 623:db79ecd649d0 | 9772 | #endif /* __cplusplus */ |
| mbed_official | 623:db79ecd649d0 | 9773 | |
| mbed_official | 623:db79ecd649d0 | 9774 | #endif /* __STM32L476xx_H */ |
| mbed_official | 623:db79ecd649d0 | 9775 | |
| mbed_official | 623:db79ecd649d0 | 9776 | /** |
| mbed_official | 623:db79ecd649d0 | 9777 | * @} |
| mbed_official | 623:db79ecd649d0 | 9778 | */ |
| mbed_official | 623:db79ecd649d0 | 9779 | |
| mbed_official | 623:db79ecd649d0 | 9780 | /** |
| mbed_official | 623:db79ecd649d0 | 9781 | * @} |
| mbed_official | 623:db79ecd649d0 | 9782 | */ |
| mbed_official | 623:db79ecd649d0 | 9783 | |
| mbed_official | 623:db79ecd649d0 | 9784 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |