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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_vref.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Parent:
TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_vref.h@82:6473597d706e 
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_VREF_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_VREF_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 VREF
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * Voltage Reference
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_VREF_TRM - VREF Trim Register
bogdanm 82:6473597d706e 33 * - HW_VREF_SC - VREF Status and Control Register
bogdanm 82:6473597d706e 34 *
bogdanm 82:6473597d706e 35 * - hw_vref_t - Struct containing all module registers.
bogdanm 82:6473597d706e 36 */
bogdanm 82:6473597d706e 37
bogdanm 82:6473597d706e 38 //! @name Module base addresses
bogdanm 82:6473597d706e 39 //@{
bogdanm 82:6473597d706e 40 #ifndef REGS_VREF_BASE
bogdanm 82:6473597d706e 41 #define HW_VREF_INSTANCE_COUNT (1U) //!< Number of instances of the VREF module.
bogdanm 82:6473597d706e 42 #define REGS_VREF_BASE (0x40074000U) //!< Base address for VREF.
bogdanm 82:6473597d706e 43 #endif
bogdanm 82:6473597d706e 44 //@}
bogdanm 82:6473597d706e 45
bogdanm 82:6473597d706e 46 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 47 // HW_VREF_TRM - VREF Trim Register
bogdanm 82:6473597d706e 48 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 49
bogdanm 82:6473597d706e 50 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 51 /*!
bogdanm 82:6473597d706e 52 * @brief HW_VREF_TRM - VREF Trim Register (RW)
bogdanm 82:6473597d706e 53 *
bogdanm 82:6473597d706e 54 * Reset value: 0x00U
bogdanm 82:6473597d706e 55 *
bogdanm 82:6473597d706e 56 * This register contains bits that contain the trim data for the Voltage
bogdanm 82:6473597d706e 57 * Reference.
bogdanm 82:6473597d706e 58 */
bogdanm 82:6473597d706e 59 typedef union _hw_vref_trm
bogdanm 82:6473597d706e 60 {
bogdanm 82:6473597d706e 61 uint8_t U;
bogdanm 82:6473597d706e 62 struct _hw_vref_trm_bitfields
bogdanm 82:6473597d706e 63 {
bogdanm 82:6473597d706e 64 uint8_t TRIM : 6; //!< [5:0] Trim bits
bogdanm 82:6473597d706e 65 uint8_t CHOPEN : 1; //!< [6] Chop oscillator enable. When set,
bogdanm 82:6473597d706e 66 //! internal chopping operation is enabled and the internal analog offset will
bogdanm 82:6473597d706e 67 //! be minimized.
bogdanm 82:6473597d706e 68 uint8_t RESERVED0 : 1; //!< [7]
bogdanm 82:6473597d706e 69 } B;
bogdanm 82:6473597d706e 70 } hw_vref_trm_t;
bogdanm 82:6473597d706e 71 #endif
bogdanm 82:6473597d706e 72
bogdanm 82:6473597d706e 73 /*!
bogdanm 82:6473597d706e 74 * @name Constants and macros for entire VREF_TRM register
bogdanm 82:6473597d706e 75 */
bogdanm 82:6473597d706e 76 //@{
bogdanm 82:6473597d706e 77 #define HW_VREF_TRM_ADDR (REGS_VREF_BASE + 0x0U)
bogdanm 82:6473597d706e 78
bogdanm 82:6473597d706e 79 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 80 #define HW_VREF_TRM (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR)
bogdanm 82:6473597d706e 81 #define HW_VREF_TRM_RD() (HW_VREF_TRM.U)
bogdanm 82:6473597d706e 82 #define HW_VREF_TRM_WR(v) (HW_VREF_TRM.U = (v))
bogdanm 82:6473597d706e 83 #define HW_VREF_TRM_SET(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() | (v)))
bogdanm 82:6473597d706e 84 #define HW_VREF_TRM_CLR(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() & ~(v)))
bogdanm 82:6473597d706e 85 #define HW_VREF_TRM_TOG(v) (HW_VREF_TRM_WR(HW_VREF_TRM_RD() ^ (v)))
bogdanm 82:6473597d706e 86 #endif
bogdanm 82:6473597d706e 87 //@}
bogdanm 82:6473597d706e 88
bogdanm 82:6473597d706e 89 /*
bogdanm 82:6473597d706e 90 * Constants & macros for individual VREF_TRM bitfields
bogdanm 82:6473597d706e 91 */
bogdanm 82:6473597d706e 92
bogdanm 82:6473597d706e 93 /*!
bogdanm 82:6473597d706e 94 * @name Register VREF_TRM, field TRIM[5:0] (RW)
bogdanm 82:6473597d706e 95 *
bogdanm 82:6473597d706e 96 * These bits change the resulting VREF by approximately +/- 0.5 mV for each
bogdanm 82:6473597d706e 97 * step. Min = minimum and max = maximum voltage reference output. For minimum and
bogdanm 82:6473597d706e 98 * maximum voltage reference output values, refer to the Data Sheet for this chip.
bogdanm 82:6473597d706e 99 *
bogdanm 82:6473597d706e 100 * Values:
bogdanm 82:6473597d706e 101 * - 000000 - Min
bogdanm 82:6473597d706e 102 * - 111111 - Max
bogdanm 82:6473597d706e 103 */
bogdanm 82:6473597d706e 104 //@{
bogdanm 82:6473597d706e 105 #define BP_VREF_TRM_TRIM (0U) //!< Bit position for VREF_TRM_TRIM.
bogdanm 82:6473597d706e 106 #define BM_VREF_TRM_TRIM (0x3FU) //!< Bit mask for VREF_TRM_TRIM.
bogdanm 82:6473597d706e 107 #define BS_VREF_TRM_TRIM (6U) //!< Bit field size in bits for VREF_TRM_TRIM.
bogdanm 82:6473597d706e 108
bogdanm 82:6473597d706e 109 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 110 //! @brief Read current value of the VREF_TRM_TRIM field.
bogdanm 82:6473597d706e 111 #define BR_VREF_TRM_TRIM (HW_VREF_TRM.B.TRIM)
bogdanm 82:6473597d706e 112 #endif
bogdanm 82:6473597d706e 113
bogdanm 82:6473597d706e 114 //! @brief Format value for bitfield VREF_TRM_TRIM.
bogdanm 82:6473597d706e 115 #define BF_VREF_TRM_TRIM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_TRIM), uint8_t) & BM_VREF_TRM_TRIM)
bogdanm 82:6473597d706e 116
bogdanm 82:6473597d706e 117 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 118 //! @brief Set the TRIM field to a new value.
bogdanm 82:6473597d706e 119 #define BW_VREF_TRM_TRIM(v) (HW_VREF_TRM_WR((HW_VREF_TRM_RD() & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
bogdanm 82:6473597d706e 120 #endif
bogdanm 82:6473597d706e 121 //@}
bogdanm 82:6473597d706e 122
bogdanm 82:6473597d706e 123 /*!
bogdanm 82:6473597d706e 124 * @name Register VREF_TRM, field CHOPEN[6] (RW)
bogdanm 82:6473597d706e 125 *
bogdanm 82:6473597d706e 126 * This bit is set during factory trimming of the VREF voltage. This bit should
bogdanm 82:6473597d706e 127 * be written to 1 to achieve the performance stated in the data sheet.
bogdanm 82:6473597d706e 128 *
bogdanm 82:6473597d706e 129 * Values:
bogdanm 82:6473597d706e 130 * - 0 - Chop oscillator is disabled.
bogdanm 82:6473597d706e 131 * - 1 - Chop oscillator is enabled.
bogdanm 82:6473597d706e 132 */
bogdanm 82:6473597d706e 133 //@{
bogdanm 82:6473597d706e 134 #define BP_VREF_TRM_CHOPEN (6U) //!< Bit position for VREF_TRM_CHOPEN.
bogdanm 82:6473597d706e 135 #define BM_VREF_TRM_CHOPEN (0x40U) //!< Bit mask for VREF_TRM_CHOPEN.
bogdanm 82:6473597d706e 136 #define BS_VREF_TRM_CHOPEN (1U) //!< Bit field size in bits for VREF_TRM_CHOPEN.
bogdanm 82:6473597d706e 137
bogdanm 82:6473597d706e 138 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 139 //! @brief Read current value of the VREF_TRM_CHOPEN field.
bogdanm 82:6473597d706e 140 #define BR_VREF_TRM_CHOPEN (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN))
bogdanm 82:6473597d706e 141 #endif
bogdanm 82:6473597d706e 142
bogdanm 82:6473597d706e 143 //! @brief Format value for bitfield VREF_TRM_CHOPEN.
bogdanm 82:6473597d706e 144 #define BF_VREF_TRM_CHOPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_TRM_CHOPEN), uint8_t) & BM_VREF_TRM_CHOPEN)
bogdanm 82:6473597d706e 145
bogdanm 82:6473597d706e 146 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 147 //! @brief Set the CHOPEN field to a new value.
bogdanm 82:6473597d706e 148 #define BW_VREF_TRM_CHOPEN(v) (BITBAND_ACCESS8(HW_VREF_TRM_ADDR, BP_VREF_TRM_CHOPEN) = (v))
bogdanm 82:6473597d706e 149 #endif
bogdanm 82:6473597d706e 150 //@}
bogdanm 82:6473597d706e 151
bogdanm 82:6473597d706e 152 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 153 // HW_VREF_SC - VREF Status and Control Register
bogdanm 82:6473597d706e 154 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 155
bogdanm 82:6473597d706e 156 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 157 /*!
bogdanm 82:6473597d706e 158 * @brief HW_VREF_SC - VREF Status and Control Register (RW)
bogdanm 82:6473597d706e 159 *
bogdanm 82:6473597d706e 160 * Reset value: 0x00U
bogdanm 82:6473597d706e 161 *
bogdanm 82:6473597d706e 162 * This register contains the control bits used to enable the internal voltage
bogdanm 82:6473597d706e 163 * reference and to select the buffer mode to be used.
bogdanm 82:6473597d706e 164 */
bogdanm 82:6473597d706e 165 typedef union _hw_vref_sc
bogdanm 82:6473597d706e 166 {
bogdanm 82:6473597d706e 167 uint8_t U;
bogdanm 82:6473597d706e 168 struct _hw_vref_sc_bitfields
bogdanm 82:6473597d706e 169 {
bogdanm 82:6473597d706e 170 uint8_t MODE_LV : 2; //!< [1:0] Buffer Mode selection
bogdanm 82:6473597d706e 171 uint8_t VREFST : 1; //!< [2] Internal Voltage Reference stable
bogdanm 82:6473597d706e 172 uint8_t RESERVED0 : 2; //!< [4:3]
bogdanm 82:6473597d706e 173 uint8_t ICOMPEN : 1; //!< [5] Second order curvature compensation
bogdanm 82:6473597d706e 174 //! enable
bogdanm 82:6473597d706e 175 uint8_t REGEN : 1; //!< [6] Regulator enable
bogdanm 82:6473597d706e 176 uint8_t VREFEN : 1; //!< [7] Internal Voltage Reference enable
bogdanm 82:6473597d706e 177 } B;
bogdanm 82:6473597d706e 178 } hw_vref_sc_t;
bogdanm 82:6473597d706e 179 #endif
bogdanm 82:6473597d706e 180
bogdanm 82:6473597d706e 181 /*!
bogdanm 82:6473597d706e 182 * @name Constants and macros for entire VREF_SC register
bogdanm 82:6473597d706e 183 */
bogdanm 82:6473597d706e 184 //@{
bogdanm 82:6473597d706e 185 #define HW_VREF_SC_ADDR (REGS_VREF_BASE + 0x1U)
bogdanm 82:6473597d706e 186
bogdanm 82:6473597d706e 187 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 188 #define HW_VREF_SC (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR)
bogdanm 82:6473597d706e 189 #define HW_VREF_SC_RD() (HW_VREF_SC.U)
bogdanm 82:6473597d706e 190 #define HW_VREF_SC_WR(v) (HW_VREF_SC.U = (v))
bogdanm 82:6473597d706e 191 #define HW_VREF_SC_SET(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() | (v)))
bogdanm 82:6473597d706e 192 #define HW_VREF_SC_CLR(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() & ~(v)))
bogdanm 82:6473597d706e 193 #define HW_VREF_SC_TOG(v) (HW_VREF_SC_WR(HW_VREF_SC_RD() ^ (v)))
bogdanm 82:6473597d706e 194 #endif
bogdanm 82:6473597d706e 195 //@}
bogdanm 82:6473597d706e 196
bogdanm 82:6473597d706e 197 /*
bogdanm 82:6473597d706e 198 * Constants & macros for individual VREF_SC bitfields
bogdanm 82:6473597d706e 199 */
bogdanm 82:6473597d706e 200
bogdanm 82:6473597d706e 201 /*!
bogdanm 82:6473597d706e 202 * @name Register VREF_SC, field MODE_LV[1:0] (RW)
bogdanm 82:6473597d706e 203 *
bogdanm 82:6473597d706e 204 * These bits select the buffer modes for the Voltage Reference module.
bogdanm 82:6473597d706e 205 *
bogdanm 82:6473597d706e 206 * Values:
bogdanm 82:6473597d706e 207 * - 00 - Bandgap on only, for stabilization and startup
bogdanm 82:6473597d706e 208 * - 01 - High power buffer mode enabled
bogdanm 82:6473597d706e 209 * - 10 - Low-power buffer mode enabled
bogdanm 82:6473597d706e 210 * - 11 - Reserved
bogdanm 82:6473597d706e 211 */
bogdanm 82:6473597d706e 212 //@{
bogdanm 82:6473597d706e 213 #define BP_VREF_SC_MODE_LV (0U) //!< Bit position for VREF_SC_MODE_LV.
bogdanm 82:6473597d706e 214 #define BM_VREF_SC_MODE_LV (0x03U) //!< Bit mask for VREF_SC_MODE_LV.
bogdanm 82:6473597d706e 215 #define BS_VREF_SC_MODE_LV (2U) //!< Bit field size in bits for VREF_SC_MODE_LV.
bogdanm 82:6473597d706e 216
bogdanm 82:6473597d706e 217 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 218 //! @brief Read current value of the VREF_SC_MODE_LV field.
bogdanm 82:6473597d706e 219 #define BR_VREF_SC_MODE_LV (HW_VREF_SC.B.MODE_LV)
bogdanm 82:6473597d706e 220 #endif
bogdanm 82:6473597d706e 221
bogdanm 82:6473597d706e 222 //! @brief Format value for bitfield VREF_SC_MODE_LV.
bogdanm 82:6473597d706e 223 #define BF_VREF_SC_MODE_LV(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_MODE_LV), uint8_t) & BM_VREF_SC_MODE_LV)
bogdanm 82:6473597d706e 224
bogdanm 82:6473597d706e 225 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 226 //! @brief Set the MODE_LV field to a new value.
bogdanm 82:6473597d706e 227 #define BW_VREF_SC_MODE_LV(v) (HW_VREF_SC_WR((HW_VREF_SC_RD() & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
bogdanm 82:6473597d706e 228 #endif
bogdanm 82:6473597d706e 229 //@}
bogdanm 82:6473597d706e 230
bogdanm 82:6473597d706e 231 /*!
bogdanm 82:6473597d706e 232 * @name Register VREF_SC, field VREFST[2] (RO)
bogdanm 82:6473597d706e 233 *
bogdanm 82:6473597d706e 234 * This bit indicates that the bandgap reference within the Voltage Reference
bogdanm 82:6473597d706e 235 * module has completed its startup and stabilization.
bogdanm 82:6473597d706e 236 *
bogdanm 82:6473597d706e 237 * Values:
bogdanm 82:6473597d706e 238 * - 0 - The module is disabled or not stable.
bogdanm 82:6473597d706e 239 * - 1 - The module is stable.
bogdanm 82:6473597d706e 240 */
bogdanm 82:6473597d706e 241 //@{
bogdanm 82:6473597d706e 242 #define BP_VREF_SC_VREFST (2U) //!< Bit position for VREF_SC_VREFST.
bogdanm 82:6473597d706e 243 #define BM_VREF_SC_VREFST (0x04U) //!< Bit mask for VREF_SC_VREFST.
bogdanm 82:6473597d706e 244 #define BS_VREF_SC_VREFST (1U) //!< Bit field size in bits for VREF_SC_VREFST.
bogdanm 82:6473597d706e 245
bogdanm 82:6473597d706e 246 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 247 //! @brief Read current value of the VREF_SC_VREFST field.
bogdanm 82:6473597d706e 248 #define BR_VREF_SC_VREFST (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFST))
bogdanm 82:6473597d706e 249 #endif
bogdanm 82:6473597d706e 250 //@}
bogdanm 82:6473597d706e 251
bogdanm 82:6473597d706e 252 /*!
bogdanm 82:6473597d706e 253 * @name Register VREF_SC, field ICOMPEN[5] (RW)
bogdanm 82:6473597d706e 254 *
bogdanm 82:6473597d706e 255 * This bit is set during factory trimming of the VREF voltage. This bit should
bogdanm 82:6473597d706e 256 * be written to 1 to achieve the performance stated in the data sheet.
bogdanm 82:6473597d706e 257 *
bogdanm 82:6473597d706e 258 * Values:
bogdanm 82:6473597d706e 259 * - 0 - Disabled
bogdanm 82:6473597d706e 260 * - 1 - Enabled
bogdanm 82:6473597d706e 261 */
bogdanm 82:6473597d706e 262 //@{
bogdanm 82:6473597d706e 263 #define BP_VREF_SC_ICOMPEN (5U) //!< Bit position for VREF_SC_ICOMPEN.
bogdanm 82:6473597d706e 264 #define BM_VREF_SC_ICOMPEN (0x20U) //!< Bit mask for VREF_SC_ICOMPEN.
bogdanm 82:6473597d706e 265 #define BS_VREF_SC_ICOMPEN (1U) //!< Bit field size in bits for VREF_SC_ICOMPEN.
bogdanm 82:6473597d706e 266
bogdanm 82:6473597d706e 267 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 268 //! @brief Read current value of the VREF_SC_ICOMPEN field.
bogdanm 82:6473597d706e 269 #define BR_VREF_SC_ICOMPEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN))
bogdanm 82:6473597d706e 270 #endif
bogdanm 82:6473597d706e 271
bogdanm 82:6473597d706e 272 //! @brief Format value for bitfield VREF_SC_ICOMPEN.
bogdanm 82:6473597d706e 273 #define BF_VREF_SC_ICOMPEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_ICOMPEN), uint8_t) & BM_VREF_SC_ICOMPEN)
bogdanm 82:6473597d706e 274
bogdanm 82:6473597d706e 275 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 276 //! @brief Set the ICOMPEN field to a new value.
bogdanm 82:6473597d706e 277 #define BW_VREF_SC_ICOMPEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_ICOMPEN) = (v))
bogdanm 82:6473597d706e 278 #endif
bogdanm 82:6473597d706e 279 //@}
bogdanm 82:6473597d706e 280
bogdanm 82:6473597d706e 281 /*!
bogdanm 82:6473597d706e 282 * @name Register VREF_SC, field REGEN[6] (RW)
bogdanm 82:6473597d706e 283 *
bogdanm 82:6473597d706e 284 * This bit is used to enable the internal 1.75 V regulator to produce a
bogdanm 82:6473597d706e 285 * constant internal voltage supply in order to reduce the sensitivity to external
bogdanm 82:6473597d706e 286 * supply noise and variation. If it is desired to keep the regulator enabled in very
bogdanm 82:6473597d706e 287 * low power modes, refer to the Chip Configuration details for a description on
bogdanm 82:6473597d706e 288 * how this can be achieved. This bit is set during factory trimming of the VREF
bogdanm 82:6473597d706e 289 * voltage. This bit should be written to 1 to achieve the performance stated in
bogdanm 82:6473597d706e 290 * the data sheet.
bogdanm 82:6473597d706e 291 *
bogdanm 82:6473597d706e 292 * Values:
bogdanm 82:6473597d706e 293 * - 0 - Internal 1.75 V regulator is disabled.
bogdanm 82:6473597d706e 294 * - 1 - Internal 1.75 V regulator is enabled.
bogdanm 82:6473597d706e 295 */
bogdanm 82:6473597d706e 296 //@{
bogdanm 82:6473597d706e 297 #define BP_VREF_SC_REGEN (6U) //!< Bit position for VREF_SC_REGEN.
bogdanm 82:6473597d706e 298 #define BM_VREF_SC_REGEN (0x40U) //!< Bit mask for VREF_SC_REGEN.
bogdanm 82:6473597d706e 299 #define BS_VREF_SC_REGEN (1U) //!< Bit field size in bits for VREF_SC_REGEN.
bogdanm 82:6473597d706e 300
bogdanm 82:6473597d706e 301 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 302 //! @brief Read current value of the VREF_SC_REGEN field.
bogdanm 82:6473597d706e 303 #define BR_VREF_SC_REGEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN))
bogdanm 82:6473597d706e 304 #endif
bogdanm 82:6473597d706e 305
bogdanm 82:6473597d706e 306 //! @brief Format value for bitfield VREF_SC_REGEN.
bogdanm 82:6473597d706e 307 #define BF_VREF_SC_REGEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_REGEN), uint8_t) & BM_VREF_SC_REGEN)
bogdanm 82:6473597d706e 308
bogdanm 82:6473597d706e 309 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 310 //! @brief Set the REGEN field to a new value.
bogdanm 82:6473597d706e 311 #define BW_VREF_SC_REGEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_REGEN) = (v))
bogdanm 82:6473597d706e 312 #endif
bogdanm 82:6473597d706e 313 //@}
bogdanm 82:6473597d706e 314
bogdanm 82:6473597d706e 315 /*!
bogdanm 82:6473597d706e 316 * @name Register VREF_SC, field VREFEN[7] (RW)
bogdanm 82:6473597d706e 317 *
bogdanm 82:6473597d706e 318 * This bit is used to enable the bandgap reference within the Voltage Reference
bogdanm 82:6473597d706e 319 * module. After the VREF is enabled, turning off the clock to the VREF module
bogdanm 82:6473597d706e 320 * via the corresponding clock gate register will not disable the VREF. VREF must
bogdanm 82:6473597d706e 321 * be disabled via this VREFEN bit.
bogdanm 82:6473597d706e 322 *
bogdanm 82:6473597d706e 323 * Values:
bogdanm 82:6473597d706e 324 * - 0 - The module is disabled.
bogdanm 82:6473597d706e 325 * - 1 - The module is enabled.
bogdanm 82:6473597d706e 326 */
bogdanm 82:6473597d706e 327 //@{
bogdanm 82:6473597d706e 328 #define BP_VREF_SC_VREFEN (7U) //!< Bit position for VREF_SC_VREFEN.
bogdanm 82:6473597d706e 329 #define BM_VREF_SC_VREFEN (0x80U) //!< Bit mask for VREF_SC_VREFEN.
bogdanm 82:6473597d706e 330 #define BS_VREF_SC_VREFEN (1U) //!< Bit field size in bits for VREF_SC_VREFEN.
bogdanm 82:6473597d706e 331
bogdanm 82:6473597d706e 332 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 333 //! @brief Read current value of the VREF_SC_VREFEN field.
bogdanm 82:6473597d706e 334 #define BR_VREF_SC_VREFEN (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN))
bogdanm 82:6473597d706e 335 #endif
bogdanm 82:6473597d706e 336
bogdanm 82:6473597d706e 337 //! @brief Format value for bitfield VREF_SC_VREFEN.
bogdanm 82:6473597d706e 338 #define BF_VREF_SC_VREFEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_VREF_SC_VREFEN), uint8_t) & BM_VREF_SC_VREFEN)
bogdanm 82:6473597d706e 339
bogdanm 82:6473597d706e 340 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 341 //! @brief Set the VREFEN field to a new value.
bogdanm 82:6473597d706e 342 #define BW_VREF_SC_VREFEN(v) (BITBAND_ACCESS8(HW_VREF_SC_ADDR, BP_VREF_SC_VREFEN) = (v))
bogdanm 82:6473597d706e 343 #endif
bogdanm 82:6473597d706e 344 //@}
bogdanm 82:6473597d706e 345
bogdanm 82:6473597d706e 346 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 347 // hw_vref_t - module struct
bogdanm 82:6473597d706e 348 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 349 /*!
bogdanm 82:6473597d706e 350 * @brief All VREF module registers.
bogdanm 82:6473597d706e 351 */
bogdanm 82:6473597d706e 352 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 353 #pragma pack(1)
bogdanm 82:6473597d706e 354 typedef struct _hw_vref
bogdanm 82:6473597d706e 355 {
bogdanm 82:6473597d706e 356 __IO hw_vref_trm_t TRM; //!< [0x0] VREF Trim Register
bogdanm 82:6473597d706e 357 __IO hw_vref_sc_t SC; //!< [0x1] VREF Status and Control Register
bogdanm 82:6473597d706e 358 } hw_vref_t;
bogdanm 82:6473597d706e 359 #pragma pack()
bogdanm 82:6473597d706e 360
bogdanm 82:6473597d706e 361 //! @brief Macro to access all VREF registers.
bogdanm 82:6473597d706e 362 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 363 //! use the '&' operator, like <code>&HW_VREF</code>.
bogdanm 82:6473597d706e 364 #define HW_VREF (*(hw_vref_t *) REGS_VREF_BASE)
bogdanm 82:6473597d706e 365 #endif
bogdanm 82:6473597d706e 366
bogdanm 82:6473597d706e 367 #endif // __HW_VREF_REGISTERS_H__
bogdanm 82:6473597d706e 368 // v22/130726/0.9
bogdanm 82:6473597d706e 369 // EOF