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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_mcm.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Parent:
TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_mcm.h@82:6473597d706e 
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_MCM_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_MCM_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 MCM
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * Core Platform Miscellaneous Control Module
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
bogdanm 82:6473597d706e 33 * - HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
bogdanm 82:6473597d706e 34 * - HW_MCM_CR - Control Register
bogdanm 82:6473597d706e 35 * - HW_MCM_ISR - Interrupt Status Register
bogdanm 82:6473597d706e 36 * - HW_MCM_ETBCC - ETB Counter Control register
bogdanm 82:6473597d706e 37 * - HW_MCM_ETBRL - ETB Reload register
bogdanm 82:6473597d706e 38 * - HW_MCM_ETBCNT - ETB Counter Value register
bogdanm 82:6473597d706e 39 * - HW_MCM_PID - Process ID register
bogdanm 82:6473597d706e 40 *
bogdanm 82:6473597d706e 41 * - hw_mcm_t - Struct containing all module registers.
bogdanm 82:6473597d706e 42 */
bogdanm 82:6473597d706e 43
bogdanm 82:6473597d706e 44 //! @name Module base addresses
bogdanm 82:6473597d706e 45 //@{
bogdanm 82:6473597d706e 46 #ifndef REGS_MCM_BASE
bogdanm 82:6473597d706e 47 #define HW_MCM_INSTANCE_COUNT (1U) //!< Number of instances of the MCM module.
bogdanm 82:6473597d706e 48 #define REGS_MCM_BASE (0xE0080000U) //!< Base address for MCM.
bogdanm 82:6473597d706e 49 #endif
bogdanm 82:6473597d706e 50 //@}
bogdanm 82:6473597d706e 51
bogdanm 82:6473597d706e 52 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 53 // HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
bogdanm 82:6473597d706e 54 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 55
bogdanm 82:6473597d706e 56 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 57 /*!
bogdanm 82:6473597d706e 58 * @brief HW_MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
bogdanm 82:6473597d706e 59 *
bogdanm 82:6473597d706e 60 * Reset value: 0x001FU
bogdanm 82:6473597d706e 61 *
bogdanm 82:6473597d706e 62 * PLASC is a 16-bit read-only register identifying the presence/absence of bus
bogdanm 82:6473597d706e 63 * slave connections to the device's crossbar switch.
bogdanm 82:6473597d706e 64 */
bogdanm 82:6473597d706e 65 typedef union _hw_mcm_plasc
bogdanm 82:6473597d706e 66 {
bogdanm 82:6473597d706e 67 uint16_t U;
bogdanm 82:6473597d706e 68 struct _hw_mcm_plasc_bitfields
bogdanm 82:6473597d706e 69 {
bogdanm 82:6473597d706e 70 uint16_t ASC : 8; //!< [7:0] Each bit in the ASC field indicates
bogdanm 82:6473597d706e 71 //! whether there is a corresponding connection to the crossbar switch's slave
bogdanm 82:6473597d706e 72 //! input port.
bogdanm 82:6473597d706e 73 uint16_t RESERVED0 : 8; //!< [15:8]
bogdanm 82:6473597d706e 74 } B;
bogdanm 82:6473597d706e 75 } hw_mcm_plasc_t;
bogdanm 82:6473597d706e 76 #endif
bogdanm 82:6473597d706e 77
bogdanm 82:6473597d706e 78 /*!
bogdanm 82:6473597d706e 79 * @name Constants and macros for entire MCM_PLASC register
bogdanm 82:6473597d706e 80 */
bogdanm 82:6473597d706e 81 //@{
bogdanm 82:6473597d706e 82 #define HW_MCM_PLASC_ADDR (REGS_MCM_BASE + 0x8U)
bogdanm 82:6473597d706e 83
bogdanm 82:6473597d706e 84 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 85 #define HW_MCM_PLASC (*(__I hw_mcm_plasc_t *) HW_MCM_PLASC_ADDR)
bogdanm 82:6473597d706e 86 #define HW_MCM_PLASC_RD() (HW_MCM_PLASC.U)
bogdanm 82:6473597d706e 87 #endif
bogdanm 82:6473597d706e 88 //@}
bogdanm 82:6473597d706e 89
bogdanm 82:6473597d706e 90 /*
bogdanm 82:6473597d706e 91 * Constants & macros for individual MCM_PLASC bitfields
bogdanm 82:6473597d706e 92 */
bogdanm 82:6473597d706e 93
bogdanm 82:6473597d706e 94 /*!
bogdanm 82:6473597d706e 95 * @name Register MCM_PLASC, field ASC[7:0] (RO)
bogdanm 82:6473597d706e 96 *
bogdanm 82:6473597d706e 97 * Values:
bogdanm 82:6473597d706e 98 * - 0 - A bus slave connection to AXBS input port n is absent
bogdanm 82:6473597d706e 99 * - 1 - A bus slave connection to AXBS input port n is present
bogdanm 82:6473597d706e 100 */
bogdanm 82:6473597d706e 101 //@{
bogdanm 82:6473597d706e 102 #define BP_MCM_PLASC_ASC (0U) //!< Bit position for MCM_PLASC_ASC.
bogdanm 82:6473597d706e 103 #define BM_MCM_PLASC_ASC (0x00FFU) //!< Bit mask for MCM_PLASC_ASC.
bogdanm 82:6473597d706e 104 #define BS_MCM_PLASC_ASC (8U) //!< Bit field size in bits for MCM_PLASC_ASC.
bogdanm 82:6473597d706e 105
bogdanm 82:6473597d706e 106 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 107 //! @brief Read current value of the MCM_PLASC_ASC field.
bogdanm 82:6473597d706e 108 #define BR_MCM_PLASC_ASC (HW_MCM_PLASC.B.ASC)
bogdanm 82:6473597d706e 109 #endif
bogdanm 82:6473597d706e 110 //@}
bogdanm 82:6473597d706e 111
bogdanm 82:6473597d706e 112 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 113 // HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
bogdanm 82:6473597d706e 114 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 115
bogdanm 82:6473597d706e 116 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 117 /*!
bogdanm 82:6473597d706e 118 * @brief HW_MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
bogdanm 82:6473597d706e 119 *
bogdanm 82:6473597d706e 120 * Reset value: 0x0037U
bogdanm 82:6473597d706e 121 *
bogdanm 82:6473597d706e 122 * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
bogdanm 82:6473597d706e 123 * master connections to the device's crossbar switch.
bogdanm 82:6473597d706e 124 */
bogdanm 82:6473597d706e 125 typedef union _hw_mcm_plamc
bogdanm 82:6473597d706e 126 {
bogdanm 82:6473597d706e 127 uint16_t U;
bogdanm 82:6473597d706e 128 struct _hw_mcm_plamc_bitfields
bogdanm 82:6473597d706e 129 {
bogdanm 82:6473597d706e 130 uint16_t AMC : 8; //!< [7:0] Each bit in the AMC field indicates
bogdanm 82:6473597d706e 131 //! whether there is a corresponding connection to the AXBS master input port.
bogdanm 82:6473597d706e 132 uint16_t RESERVED0 : 8; //!< [15:8]
bogdanm 82:6473597d706e 133 } B;
bogdanm 82:6473597d706e 134 } hw_mcm_plamc_t;
bogdanm 82:6473597d706e 135 #endif
bogdanm 82:6473597d706e 136
bogdanm 82:6473597d706e 137 /*!
bogdanm 82:6473597d706e 138 * @name Constants and macros for entire MCM_PLAMC register
bogdanm 82:6473597d706e 139 */
bogdanm 82:6473597d706e 140 //@{
bogdanm 82:6473597d706e 141 #define HW_MCM_PLAMC_ADDR (REGS_MCM_BASE + 0xAU)
bogdanm 82:6473597d706e 142
bogdanm 82:6473597d706e 143 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 144 #define HW_MCM_PLAMC (*(__I hw_mcm_plamc_t *) HW_MCM_PLAMC_ADDR)
bogdanm 82:6473597d706e 145 #define HW_MCM_PLAMC_RD() (HW_MCM_PLAMC.U)
bogdanm 82:6473597d706e 146 #endif
bogdanm 82:6473597d706e 147 //@}
bogdanm 82:6473597d706e 148
bogdanm 82:6473597d706e 149 /*
bogdanm 82:6473597d706e 150 * Constants & macros for individual MCM_PLAMC bitfields
bogdanm 82:6473597d706e 151 */
bogdanm 82:6473597d706e 152
bogdanm 82:6473597d706e 153 /*!
bogdanm 82:6473597d706e 154 * @name Register MCM_PLAMC, field AMC[7:0] (RO)
bogdanm 82:6473597d706e 155 *
bogdanm 82:6473597d706e 156 * Values:
bogdanm 82:6473597d706e 157 * - 0 - A bus master connection to AXBS input port n is absent
bogdanm 82:6473597d706e 158 * - 1 - A bus master connection to AXBS input port n is present
bogdanm 82:6473597d706e 159 */
bogdanm 82:6473597d706e 160 //@{
bogdanm 82:6473597d706e 161 #define BP_MCM_PLAMC_AMC (0U) //!< Bit position for MCM_PLAMC_AMC.
bogdanm 82:6473597d706e 162 #define BM_MCM_PLAMC_AMC (0x00FFU) //!< Bit mask for MCM_PLAMC_AMC.
bogdanm 82:6473597d706e 163 #define BS_MCM_PLAMC_AMC (8U) //!< Bit field size in bits for MCM_PLAMC_AMC.
bogdanm 82:6473597d706e 164
bogdanm 82:6473597d706e 165 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 166 //! @brief Read current value of the MCM_PLAMC_AMC field.
bogdanm 82:6473597d706e 167 #define BR_MCM_PLAMC_AMC (HW_MCM_PLAMC.B.AMC)
bogdanm 82:6473597d706e 168 #endif
bogdanm 82:6473597d706e 169 //@}
bogdanm 82:6473597d706e 170
bogdanm 82:6473597d706e 171 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 172 // HW_MCM_CR - Control Register
bogdanm 82:6473597d706e 173 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 174
bogdanm 82:6473597d706e 175 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 176 /*!
bogdanm 82:6473597d706e 177 * @brief HW_MCM_CR - Control Register (RW)
bogdanm 82:6473597d706e 178 *
bogdanm 82:6473597d706e 179 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 180 *
bogdanm 82:6473597d706e 181 * CR defines the arbitration and protection schemes for the two system RAM
bogdanm 82:6473597d706e 182 * arrays.
bogdanm 82:6473597d706e 183 */
bogdanm 82:6473597d706e 184 typedef union _hw_mcm_cr
bogdanm 82:6473597d706e 185 {
bogdanm 82:6473597d706e 186 uint32_t U;
bogdanm 82:6473597d706e 187 struct _hw_mcm_cr_bitfields
bogdanm 82:6473597d706e 188 {
bogdanm 82:6473597d706e 189 uint32_t RESERVED0 : 24; //!< [23:0]
bogdanm 82:6473597d706e 190 uint32_t SRAMUAP : 2; //!< [25:24] SRAM_U arbitration priority
bogdanm 82:6473597d706e 191 uint32_t SRAMUWP : 1; //!< [26] SRAM_U write protect
bogdanm 82:6473597d706e 192 uint32_t RESERVED1 : 1; //!< [27]
bogdanm 82:6473597d706e 193 uint32_t SRAMLAP : 2; //!< [29:28] SRAM_L arbitration priority
bogdanm 82:6473597d706e 194 uint32_t SRAMLWP : 1; //!< [30] SRAM_L Write Protect
bogdanm 82:6473597d706e 195 uint32_t RESERVED2 : 1; //!< [31]
bogdanm 82:6473597d706e 196 } B;
bogdanm 82:6473597d706e 197 } hw_mcm_cr_t;
bogdanm 82:6473597d706e 198 #endif
bogdanm 82:6473597d706e 199
bogdanm 82:6473597d706e 200 /*!
bogdanm 82:6473597d706e 201 * @name Constants and macros for entire MCM_CR register
bogdanm 82:6473597d706e 202 */
bogdanm 82:6473597d706e 203 //@{
bogdanm 82:6473597d706e 204 #define HW_MCM_CR_ADDR (REGS_MCM_BASE + 0xCU)
bogdanm 82:6473597d706e 205
bogdanm 82:6473597d706e 206 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 207 #define HW_MCM_CR (*(__IO hw_mcm_cr_t *) HW_MCM_CR_ADDR)
bogdanm 82:6473597d706e 208 #define HW_MCM_CR_RD() (HW_MCM_CR.U)
bogdanm 82:6473597d706e 209 #define HW_MCM_CR_WR(v) (HW_MCM_CR.U = (v))
bogdanm 82:6473597d706e 210 #define HW_MCM_CR_SET(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() | (v)))
bogdanm 82:6473597d706e 211 #define HW_MCM_CR_CLR(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() & ~(v)))
bogdanm 82:6473597d706e 212 #define HW_MCM_CR_TOG(v) (HW_MCM_CR_WR(HW_MCM_CR_RD() ^ (v)))
bogdanm 82:6473597d706e 213 #endif
bogdanm 82:6473597d706e 214 //@}
bogdanm 82:6473597d706e 215
bogdanm 82:6473597d706e 216 /*
bogdanm 82:6473597d706e 217 * Constants & macros for individual MCM_CR bitfields
bogdanm 82:6473597d706e 218 */
bogdanm 82:6473597d706e 219
bogdanm 82:6473597d706e 220 /*!
bogdanm 82:6473597d706e 221 * @name Register MCM_CR, field SRAMUAP[25:24] (RW)
bogdanm 82:6473597d706e 222 *
bogdanm 82:6473597d706e 223 * Defines the arbitration scheme and priority for the processor and SRAM
bogdanm 82:6473597d706e 224 * backdoor accesses to the SRAM_U array.
bogdanm 82:6473597d706e 225 *
bogdanm 82:6473597d706e 226 * Values:
bogdanm 82:6473597d706e 227 * - 00 - Round robin
bogdanm 82:6473597d706e 228 * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
bogdanm 82:6473597d706e 229 * - 10 - Fixed priority. Processor has highest, backdoor has lowest
bogdanm 82:6473597d706e 230 * - 11 - Fixed priority. Backdoor has highest, processor has lowest
bogdanm 82:6473597d706e 231 */
bogdanm 82:6473597d706e 232 //@{
bogdanm 82:6473597d706e 233 #define BP_MCM_CR_SRAMUAP (24U) //!< Bit position for MCM_CR_SRAMUAP.
bogdanm 82:6473597d706e 234 #define BM_MCM_CR_SRAMUAP (0x03000000U) //!< Bit mask for MCM_CR_SRAMUAP.
bogdanm 82:6473597d706e 235 #define BS_MCM_CR_SRAMUAP (2U) //!< Bit field size in bits for MCM_CR_SRAMUAP.
bogdanm 82:6473597d706e 236
bogdanm 82:6473597d706e 237 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 238 //! @brief Read current value of the MCM_CR_SRAMUAP field.
bogdanm 82:6473597d706e 239 #define BR_MCM_CR_SRAMUAP (HW_MCM_CR.B.SRAMUAP)
bogdanm 82:6473597d706e 240 #endif
bogdanm 82:6473597d706e 241
bogdanm 82:6473597d706e 242 //! @brief Format value for bitfield MCM_CR_SRAMUAP.
bogdanm 82:6473597d706e 243 #define BF_MCM_CR_SRAMUAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMUAP), uint32_t) & BM_MCM_CR_SRAMUAP)
bogdanm 82:6473597d706e 244
bogdanm 82:6473597d706e 245 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 246 //! @brief Set the SRAMUAP field to a new value.
bogdanm 82:6473597d706e 247 #define BW_MCM_CR_SRAMUAP(v) (HW_MCM_CR_WR((HW_MCM_CR_RD() & ~BM_MCM_CR_SRAMUAP) | BF_MCM_CR_SRAMUAP(v)))
bogdanm 82:6473597d706e 248 #endif
bogdanm 82:6473597d706e 249 //@}
bogdanm 82:6473597d706e 250
bogdanm 82:6473597d706e 251 /*!
bogdanm 82:6473597d706e 252 * @name Register MCM_CR, field SRAMUWP[26] (RW)
bogdanm 82:6473597d706e 253 *
bogdanm 82:6473597d706e 254 * When this bit is set, writes to SRAM_U array generates a bus error.
bogdanm 82:6473597d706e 255 */
bogdanm 82:6473597d706e 256 //@{
bogdanm 82:6473597d706e 257 #define BP_MCM_CR_SRAMUWP (26U) //!< Bit position for MCM_CR_SRAMUWP.
bogdanm 82:6473597d706e 258 #define BM_MCM_CR_SRAMUWP (0x04000000U) //!< Bit mask for MCM_CR_SRAMUWP.
bogdanm 82:6473597d706e 259 #define BS_MCM_CR_SRAMUWP (1U) //!< Bit field size in bits for MCM_CR_SRAMUWP.
bogdanm 82:6473597d706e 260
bogdanm 82:6473597d706e 261 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 262 //! @brief Read current value of the MCM_CR_SRAMUWP field.
bogdanm 82:6473597d706e 263 #define BR_MCM_CR_SRAMUWP (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMUWP))
bogdanm 82:6473597d706e 264 #endif
bogdanm 82:6473597d706e 265
bogdanm 82:6473597d706e 266 //! @brief Format value for bitfield MCM_CR_SRAMUWP.
bogdanm 82:6473597d706e 267 #define BF_MCM_CR_SRAMUWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMUWP), uint32_t) & BM_MCM_CR_SRAMUWP)
bogdanm 82:6473597d706e 268
bogdanm 82:6473597d706e 269 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 270 //! @brief Set the SRAMUWP field to a new value.
bogdanm 82:6473597d706e 271 #define BW_MCM_CR_SRAMUWP(v) (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMUWP) = (v))
bogdanm 82:6473597d706e 272 #endif
bogdanm 82:6473597d706e 273 //@}
bogdanm 82:6473597d706e 274
bogdanm 82:6473597d706e 275 /*!
bogdanm 82:6473597d706e 276 * @name Register MCM_CR, field SRAMLAP[29:28] (RW)
bogdanm 82:6473597d706e 277 *
bogdanm 82:6473597d706e 278 * Defines the arbitration scheme and priority for the processor and SRAM
bogdanm 82:6473597d706e 279 * backdoor accesses to the SRAM_L array.
bogdanm 82:6473597d706e 280 *
bogdanm 82:6473597d706e 281 * Values:
bogdanm 82:6473597d706e 282 * - 00 - Round robin
bogdanm 82:6473597d706e 283 * - 01 - Special round robin (favors SRAM backoor accesses over the processor)
bogdanm 82:6473597d706e 284 * - 10 - Fixed priority. Processor has highest, backdoor has lowest
bogdanm 82:6473597d706e 285 * - 11 - Fixed priority. Backdoor has highest, processor has lowest
bogdanm 82:6473597d706e 286 */
bogdanm 82:6473597d706e 287 //@{
bogdanm 82:6473597d706e 288 #define BP_MCM_CR_SRAMLAP (28U) //!< Bit position for MCM_CR_SRAMLAP.
bogdanm 82:6473597d706e 289 #define BM_MCM_CR_SRAMLAP (0x30000000U) //!< Bit mask for MCM_CR_SRAMLAP.
bogdanm 82:6473597d706e 290 #define BS_MCM_CR_SRAMLAP (2U) //!< Bit field size in bits for MCM_CR_SRAMLAP.
bogdanm 82:6473597d706e 291
bogdanm 82:6473597d706e 292 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 293 //! @brief Read current value of the MCM_CR_SRAMLAP field.
bogdanm 82:6473597d706e 294 #define BR_MCM_CR_SRAMLAP (HW_MCM_CR.B.SRAMLAP)
bogdanm 82:6473597d706e 295 #endif
bogdanm 82:6473597d706e 296
bogdanm 82:6473597d706e 297 //! @brief Format value for bitfield MCM_CR_SRAMLAP.
bogdanm 82:6473597d706e 298 #define BF_MCM_CR_SRAMLAP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMLAP), uint32_t) & BM_MCM_CR_SRAMLAP)
bogdanm 82:6473597d706e 299
bogdanm 82:6473597d706e 300 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 301 //! @brief Set the SRAMLAP field to a new value.
bogdanm 82:6473597d706e 302 #define BW_MCM_CR_SRAMLAP(v) (HW_MCM_CR_WR((HW_MCM_CR_RD() & ~BM_MCM_CR_SRAMLAP) | BF_MCM_CR_SRAMLAP(v)))
bogdanm 82:6473597d706e 303 #endif
bogdanm 82:6473597d706e 304 //@}
bogdanm 82:6473597d706e 305
bogdanm 82:6473597d706e 306 /*!
bogdanm 82:6473597d706e 307 * @name Register MCM_CR, field SRAMLWP[30] (RW)
bogdanm 82:6473597d706e 308 *
bogdanm 82:6473597d706e 309 * When this bit is set, writes to SRAM_L array generates a bus error.
bogdanm 82:6473597d706e 310 */
bogdanm 82:6473597d706e 311 //@{
bogdanm 82:6473597d706e 312 #define BP_MCM_CR_SRAMLWP (30U) //!< Bit position for MCM_CR_SRAMLWP.
bogdanm 82:6473597d706e 313 #define BM_MCM_CR_SRAMLWP (0x40000000U) //!< Bit mask for MCM_CR_SRAMLWP.
bogdanm 82:6473597d706e 314 #define BS_MCM_CR_SRAMLWP (1U) //!< Bit field size in bits for MCM_CR_SRAMLWP.
bogdanm 82:6473597d706e 315
bogdanm 82:6473597d706e 316 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 317 //! @brief Read current value of the MCM_CR_SRAMLWP field.
bogdanm 82:6473597d706e 318 #define BR_MCM_CR_SRAMLWP (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMLWP))
bogdanm 82:6473597d706e 319 #endif
bogdanm 82:6473597d706e 320
bogdanm 82:6473597d706e 321 //! @brief Format value for bitfield MCM_CR_SRAMLWP.
bogdanm 82:6473597d706e 322 #define BF_MCM_CR_SRAMLWP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_CR_SRAMLWP), uint32_t) & BM_MCM_CR_SRAMLWP)
bogdanm 82:6473597d706e 323
bogdanm 82:6473597d706e 324 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 325 //! @brief Set the SRAMLWP field to a new value.
bogdanm 82:6473597d706e 326 #define BW_MCM_CR_SRAMLWP(v) (BITBAND_ACCESS32(HW_MCM_CR_ADDR, BP_MCM_CR_SRAMLWP) = (v))
bogdanm 82:6473597d706e 327 #endif
bogdanm 82:6473597d706e 328 //@}
bogdanm 82:6473597d706e 329
bogdanm 82:6473597d706e 330 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 331 // HW_MCM_ISR - Interrupt Status Register
bogdanm 82:6473597d706e 332 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 333
bogdanm 82:6473597d706e 334 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 335 /*!
bogdanm 82:6473597d706e 336 * @brief HW_MCM_ISR - Interrupt Status Register (RW)
bogdanm 82:6473597d706e 337 *
bogdanm 82:6473597d706e 338 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 339 */
bogdanm 82:6473597d706e 340 typedef union _hw_mcm_isr
bogdanm 82:6473597d706e 341 {
bogdanm 82:6473597d706e 342 uint32_t U;
bogdanm 82:6473597d706e 343 struct _hw_mcm_isr_bitfields
bogdanm 82:6473597d706e 344 {
bogdanm 82:6473597d706e 345 uint32_t RESERVED0 : 1; //!< [0]
bogdanm 82:6473597d706e 346 uint32_t IRQ : 1; //!< [1] Normal Interrupt Pending
bogdanm 82:6473597d706e 347 uint32_t NMI : 1; //!< [2] Non-maskable Interrupt Pending
bogdanm 82:6473597d706e 348 uint32_t DHREQ : 1; //!< [3] Debug Halt Request Indicator
bogdanm 82:6473597d706e 349 uint32_t RESERVED1 : 4; //!< [7:4]
bogdanm 82:6473597d706e 350 uint32_t FIOC : 1; //!< [8] FPU invalid operation interrupt status
bogdanm 82:6473597d706e 351 uint32_t FDZC : 1; //!< [9] FPU divide-by-zero interrupt status
bogdanm 82:6473597d706e 352 uint32_t FOFC : 1; //!< [10] FPU overflow interrupt status
bogdanm 82:6473597d706e 353 uint32_t FUFC : 1; //!< [11] FPU underflow interrupt status
bogdanm 82:6473597d706e 354 uint32_t FIXC : 1; //!< [12] FPU inexact interrupt status
bogdanm 82:6473597d706e 355 uint32_t RESERVED2 : 2; //!< [14:13]
bogdanm 82:6473597d706e 356 uint32_t FIDC : 1; //!< [15] FPU input denormal interrupt status
bogdanm 82:6473597d706e 357 uint32_t RESERVED3 : 8; //!< [23:16]
bogdanm 82:6473597d706e 358 uint32_t FIOCE : 1; //!< [24] FPU invalid operation interrupt enable
bogdanm 82:6473597d706e 359 uint32_t FDZCE : 1; //!< [25] FPU divide-by-zero interrupt enable
bogdanm 82:6473597d706e 360 uint32_t FOFCE : 1; //!< [26] FPU overflow interrupt enable
bogdanm 82:6473597d706e 361 uint32_t FUFCE : 1; //!< [27] FPU underflow interrupt enable
bogdanm 82:6473597d706e 362 uint32_t FIXCE : 1; //!< [28] FPU inexact interrupt enable
bogdanm 82:6473597d706e 363 uint32_t RESERVED4 : 2; //!< [30:29]
bogdanm 82:6473597d706e 364 uint32_t FIDCE : 1; //!< [31] FPU input denormal interrupt enable
bogdanm 82:6473597d706e 365 } B;
bogdanm 82:6473597d706e 366 } hw_mcm_isr_t;
bogdanm 82:6473597d706e 367 #endif
bogdanm 82:6473597d706e 368
bogdanm 82:6473597d706e 369 /*!
bogdanm 82:6473597d706e 370 * @name Constants and macros for entire MCM_ISR register
bogdanm 82:6473597d706e 371 */
bogdanm 82:6473597d706e 372 //@{
bogdanm 82:6473597d706e 373 #define HW_MCM_ISR_ADDR (REGS_MCM_BASE + 0x10U)
bogdanm 82:6473597d706e 374
bogdanm 82:6473597d706e 375 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 376 #define HW_MCM_ISR (*(__IO hw_mcm_isr_t *) HW_MCM_ISR_ADDR)
bogdanm 82:6473597d706e 377 #define HW_MCM_ISR_RD() (HW_MCM_ISR.U)
bogdanm 82:6473597d706e 378 #define HW_MCM_ISR_WR(v) (HW_MCM_ISR.U = (v))
bogdanm 82:6473597d706e 379 #define HW_MCM_ISR_SET(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() | (v)))
bogdanm 82:6473597d706e 380 #define HW_MCM_ISR_CLR(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() & ~(v)))
bogdanm 82:6473597d706e 381 #define HW_MCM_ISR_TOG(v) (HW_MCM_ISR_WR(HW_MCM_ISR_RD() ^ (v)))
bogdanm 82:6473597d706e 382 #endif
bogdanm 82:6473597d706e 383 //@}
bogdanm 82:6473597d706e 384
bogdanm 82:6473597d706e 385 /*
bogdanm 82:6473597d706e 386 * Constants & macros for individual MCM_ISR bitfields
bogdanm 82:6473597d706e 387 */
bogdanm 82:6473597d706e 388
bogdanm 82:6473597d706e 389 /*!
bogdanm 82:6473597d706e 390 * @name Register MCM_ISR, field IRQ[1] (W1C)
bogdanm 82:6473597d706e 391 *
bogdanm 82:6473597d706e 392 * If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires.
bogdanm 82:6473597d706e 393 *
bogdanm 82:6473597d706e 394 * Values:
bogdanm 82:6473597d706e 395 * - 0 - No pending interrupt
bogdanm 82:6473597d706e 396 * - 1 - Due to the ETB counter expiring, a normal interrupt is pending
bogdanm 82:6473597d706e 397 */
bogdanm 82:6473597d706e 398 //@{
bogdanm 82:6473597d706e 399 #define BP_MCM_ISR_IRQ (1U) //!< Bit position for MCM_ISR_IRQ.
bogdanm 82:6473597d706e 400 #define BM_MCM_ISR_IRQ (0x00000002U) //!< Bit mask for MCM_ISR_IRQ.
bogdanm 82:6473597d706e 401 #define BS_MCM_ISR_IRQ (1U) //!< Bit field size in bits for MCM_ISR_IRQ.
bogdanm 82:6473597d706e 402
bogdanm 82:6473597d706e 403 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 404 //! @brief Read current value of the MCM_ISR_IRQ field.
bogdanm 82:6473597d706e 405 #define BR_MCM_ISR_IRQ (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_IRQ))
bogdanm 82:6473597d706e 406 #endif
bogdanm 82:6473597d706e 407
bogdanm 82:6473597d706e 408 //! @brief Format value for bitfield MCM_ISR_IRQ.
bogdanm 82:6473597d706e 409 #define BF_MCM_ISR_IRQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_IRQ), uint32_t) & BM_MCM_ISR_IRQ)
bogdanm 82:6473597d706e 410
bogdanm 82:6473597d706e 411 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 412 //! @brief Set the IRQ field to a new value.
bogdanm 82:6473597d706e 413 #define BW_MCM_ISR_IRQ(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_IRQ) = (v))
bogdanm 82:6473597d706e 414 #endif
bogdanm 82:6473597d706e 415 //@}
bogdanm 82:6473597d706e 416
bogdanm 82:6473597d706e 417 /*!
bogdanm 82:6473597d706e 418 * @name Register MCM_ISR, field NMI[2] (W1C)
bogdanm 82:6473597d706e 419 *
bogdanm 82:6473597d706e 420 * If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires.
bogdanm 82:6473597d706e 421 *
bogdanm 82:6473597d706e 422 * Values:
bogdanm 82:6473597d706e 423 * - 0 - No pending NMI
bogdanm 82:6473597d706e 424 * - 1 - Due to the ETB counter expiring, an NMI is pending
bogdanm 82:6473597d706e 425 */
bogdanm 82:6473597d706e 426 //@{
bogdanm 82:6473597d706e 427 #define BP_MCM_ISR_NMI (2U) //!< Bit position for MCM_ISR_NMI.
bogdanm 82:6473597d706e 428 #define BM_MCM_ISR_NMI (0x00000004U) //!< Bit mask for MCM_ISR_NMI.
bogdanm 82:6473597d706e 429 #define BS_MCM_ISR_NMI (1U) //!< Bit field size in bits for MCM_ISR_NMI.
bogdanm 82:6473597d706e 430
bogdanm 82:6473597d706e 431 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 432 //! @brief Read current value of the MCM_ISR_NMI field.
bogdanm 82:6473597d706e 433 #define BR_MCM_ISR_NMI (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_NMI))
bogdanm 82:6473597d706e 434 #endif
bogdanm 82:6473597d706e 435
bogdanm 82:6473597d706e 436 //! @brief Format value for bitfield MCM_ISR_NMI.
bogdanm 82:6473597d706e 437 #define BF_MCM_ISR_NMI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_NMI), uint32_t) & BM_MCM_ISR_NMI)
bogdanm 82:6473597d706e 438
bogdanm 82:6473597d706e 439 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 440 //! @brief Set the NMI field to a new value.
bogdanm 82:6473597d706e 441 #define BW_MCM_ISR_NMI(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_NMI) = (v))
bogdanm 82:6473597d706e 442 #endif
bogdanm 82:6473597d706e 443 //@}
bogdanm 82:6473597d706e 444
bogdanm 82:6473597d706e 445 /*!
bogdanm 82:6473597d706e 446 * @name Register MCM_ISR, field DHREQ[3] (RO)
bogdanm 82:6473597d706e 447 *
bogdanm 82:6473597d706e 448 * Indicates that a debug halt request is initiated due to a ETB counter
bogdanm 82:6473597d706e 449 * expiration, ETBCC[2:0] = 3b111 & ETBCV[10:0] = 11h0. This bit is cleared when the
bogdanm 82:6473597d706e 450 * counter is disabled or when the ETB counter is reloaded.
bogdanm 82:6473597d706e 451 *
bogdanm 82:6473597d706e 452 * Values:
bogdanm 82:6473597d706e 453 * - 0 - No debug halt request
bogdanm 82:6473597d706e 454 * - 1 - Debug halt request initiated
bogdanm 82:6473597d706e 455 */
bogdanm 82:6473597d706e 456 //@{
bogdanm 82:6473597d706e 457 #define BP_MCM_ISR_DHREQ (3U) //!< Bit position for MCM_ISR_DHREQ.
bogdanm 82:6473597d706e 458 #define BM_MCM_ISR_DHREQ (0x00000008U) //!< Bit mask for MCM_ISR_DHREQ.
bogdanm 82:6473597d706e 459 #define BS_MCM_ISR_DHREQ (1U) //!< Bit field size in bits for MCM_ISR_DHREQ.
bogdanm 82:6473597d706e 460
bogdanm 82:6473597d706e 461 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 462 //! @brief Read current value of the MCM_ISR_DHREQ field.
bogdanm 82:6473597d706e 463 #define BR_MCM_ISR_DHREQ (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_DHREQ))
bogdanm 82:6473597d706e 464 #endif
bogdanm 82:6473597d706e 465 //@}
bogdanm 82:6473597d706e 466
bogdanm 82:6473597d706e 467 /*!
bogdanm 82:6473597d706e 468 * @name Register MCM_ISR, field FIOC[8] (RO)
bogdanm 82:6473597d706e 469 *
bogdanm 82:6473597d706e 470 * This read-only bit is a copy of the core's FPSCR[IOC] bit and signals an
bogdanm 82:6473597d706e 471 * illegal operation has been detected in the processor's FPU. Once set, this bit
bogdanm 82:6473597d706e 472 * remains set until software clears the FPSCR[IOC] bit.
bogdanm 82:6473597d706e 473 *
bogdanm 82:6473597d706e 474 * Values:
bogdanm 82:6473597d706e 475 * - 0 - No interrupt
bogdanm 82:6473597d706e 476 * - 1 - Interrupt occurred
bogdanm 82:6473597d706e 477 */
bogdanm 82:6473597d706e 478 //@{
bogdanm 82:6473597d706e 479 #define BP_MCM_ISR_FIOC (8U) //!< Bit position for MCM_ISR_FIOC.
bogdanm 82:6473597d706e 480 #define BM_MCM_ISR_FIOC (0x00000100U) //!< Bit mask for MCM_ISR_FIOC.
bogdanm 82:6473597d706e 481 #define BS_MCM_ISR_FIOC (1U) //!< Bit field size in bits for MCM_ISR_FIOC.
bogdanm 82:6473597d706e 482
bogdanm 82:6473597d706e 483 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 484 //! @brief Read current value of the MCM_ISR_FIOC field.
bogdanm 82:6473597d706e 485 #define BR_MCM_ISR_FIOC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOC))
bogdanm 82:6473597d706e 486 #endif
bogdanm 82:6473597d706e 487 //@}
bogdanm 82:6473597d706e 488
bogdanm 82:6473597d706e 489 /*!
bogdanm 82:6473597d706e 490 * @name Register MCM_ISR, field FDZC[9] (RO)
bogdanm 82:6473597d706e 491 *
bogdanm 82:6473597d706e 492 * This read-only bit is a copy of the core's FPSCR[DZC] bit and signals a
bogdanm 82:6473597d706e 493 * divide by zero has been detected in the processor's FPU. Once set, this bit remains
bogdanm 82:6473597d706e 494 * set until software clears the FPSCR[DZC] bit.
bogdanm 82:6473597d706e 495 *
bogdanm 82:6473597d706e 496 * Values:
bogdanm 82:6473597d706e 497 * - 0 - No interrupt
bogdanm 82:6473597d706e 498 * - 1 - Interrupt occurred
bogdanm 82:6473597d706e 499 */
bogdanm 82:6473597d706e 500 //@{
bogdanm 82:6473597d706e 501 #define BP_MCM_ISR_FDZC (9U) //!< Bit position for MCM_ISR_FDZC.
bogdanm 82:6473597d706e 502 #define BM_MCM_ISR_FDZC (0x00000200U) //!< Bit mask for MCM_ISR_FDZC.
bogdanm 82:6473597d706e 503 #define BS_MCM_ISR_FDZC (1U) //!< Bit field size in bits for MCM_ISR_FDZC.
bogdanm 82:6473597d706e 504
bogdanm 82:6473597d706e 505 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 506 //! @brief Read current value of the MCM_ISR_FDZC field.
bogdanm 82:6473597d706e 507 #define BR_MCM_ISR_FDZC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZC))
bogdanm 82:6473597d706e 508 #endif
bogdanm 82:6473597d706e 509 //@}
bogdanm 82:6473597d706e 510
bogdanm 82:6473597d706e 511 /*!
bogdanm 82:6473597d706e 512 * @name Register MCM_ISR, field FOFC[10] (RO)
bogdanm 82:6473597d706e 513 *
bogdanm 82:6473597d706e 514 * This read-only bit is a copy of the core's FPSCR[OFC] bit and signals an
bogdanm 82:6473597d706e 515 * overflow has been detected in the processor's FPU. Once set, this bit remains set
bogdanm 82:6473597d706e 516 * until software clears the FPSCR[OFC] bit.
bogdanm 82:6473597d706e 517 *
bogdanm 82:6473597d706e 518 * Values:
bogdanm 82:6473597d706e 519 * - 0 - No interrupt
bogdanm 82:6473597d706e 520 * - 1 - Interrupt occurred
bogdanm 82:6473597d706e 521 */
bogdanm 82:6473597d706e 522 //@{
bogdanm 82:6473597d706e 523 #define BP_MCM_ISR_FOFC (10U) //!< Bit position for MCM_ISR_FOFC.
bogdanm 82:6473597d706e 524 #define BM_MCM_ISR_FOFC (0x00000400U) //!< Bit mask for MCM_ISR_FOFC.
bogdanm 82:6473597d706e 525 #define BS_MCM_ISR_FOFC (1U) //!< Bit field size in bits for MCM_ISR_FOFC.
bogdanm 82:6473597d706e 526
bogdanm 82:6473597d706e 527 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 528 //! @brief Read current value of the MCM_ISR_FOFC field.
bogdanm 82:6473597d706e 529 #define BR_MCM_ISR_FOFC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFC))
bogdanm 82:6473597d706e 530 #endif
bogdanm 82:6473597d706e 531 //@}
bogdanm 82:6473597d706e 532
bogdanm 82:6473597d706e 533 /*!
bogdanm 82:6473597d706e 534 * @name Register MCM_ISR, field FUFC[11] (RO)
bogdanm 82:6473597d706e 535 *
bogdanm 82:6473597d706e 536 * This read-only bit is a copy of the core's FPSCR[UFC] bit and signals an
bogdanm 82:6473597d706e 537 * underflow has been detected in the processor's FPU. Once set, this bit remains set
bogdanm 82:6473597d706e 538 * until software clears the FPSCR[UFC] bit.
bogdanm 82:6473597d706e 539 *
bogdanm 82:6473597d706e 540 * Values:
bogdanm 82:6473597d706e 541 * - 0 - No interrupt
bogdanm 82:6473597d706e 542 * - 1 - Interrupt occurred
bogdanm 82:6473597d706e 543 */
bogdanm 82:6473597d706e 544 //@{
bogdanm 82:6473597d706e 545 #define BP_MCM_ISR_FUFC (11U) //!< Bit position for MCM_ISR_FUFC.
bogdanm 82:6473597d706e 546 #define BM_MCM_ISR_FUFC (0x00000800U) //!< Bit mask for MCM_ISR_FUFC.
bogdanm 82:6473597d706e 547 #define BS_MCM_ISR_FUFC (1U) //!< Bit field size in bits for MCM_ISR_FUFC.
bogdanm 82:6473597d706e 548
bogdanm 82:6473597d706e 549 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 550 //! @brief Read current value of the MCM_ISR_FUFC field.
bogdanm 82:6473597d706e 551 #define BR_MCM_ISR_FUFC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFC))
bogdanm 82:6473597d706e 552 #endif
bogdanm 82:6473597d706e 553 //@}
bogdanm 82:6473597d706e 554
bogdanm 82:6473597d706e 555 /*!
bogdanm 82:6473597d706e 556 * @name Register MCM_ISR, field FIXC[12] (RO)
bogdanm 82:6473597d706e 557 *
bogdanm 82:6473597d706e 558 * This read-only bit is a copy of the core's FPSCR[IXC] bit and signals an
bogdanm 82:6473597d706e 559 * inexact number has been detected in the processor's FPU. Once set, this bit
bogdanm 82:6473597d706e 560 * remains set until software clears the FPSCR[IXC] bit.
bogdanm 82:6473597d706e 561 *
bogdanm 82:6473597d706e 562 * Values:
bogdanm 82:6473597d706e 563 * - 0 - No interrupt
bogdanm 82:6473597d706e 564 * - 1 - Interrupt occurred
bogdanm 82:6473597d706e 565 */
bogdanm 82:6473597d706e 566 //@{
bogdanm 82:6473597d706e 567 #define BP_MCM_ISR_FIXC (12U) //!< Bit position for MCM_ISR_FIXC.
bogdanm 82:6473597d706e 568 #define BM_MCM_ISR_FIXC (0x00001000U) //!< Bit mask for MCM_ISR_FIXC.
bogdanm 82:6473597d706e 569 #define BS_MCM_ISR_FIXC (1U) //!< Bit field size in bits for MCM_ISR_FIXC.
bogdanm 82:6473597d706e 570
bogdanm 82:6473597d706e 571 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 572 //! @brief Read current value of the MCM_ISR_FIXC field.
bogdanm 82:6473597d706e 573 #define BR_MCM_ISR_FIXC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXC))
bogdanm 82:6473597d706e 574 #endif
bogdanm 82:6473597d706e 575 //@}
bogdanm 82:6473597d706e 576
bogdanm 82:6473597d706e 577 /*!
bogdanm 82:6473597d706e 578 * @name Register MCM_ISR, field FIDC[15] (RO)
bogdanm 82:6473597d706e 579 *
bogdanm 82:6473597d706e 580 * This read-only bit is a copy of the core's FPSCR[IDC] bit and signals input
bogdanm 82:6473597d706e 581 * denormalized number has been detected in the processor's FPU. Once set, this
bogdanm 82:6473597d706e 582 * bit remains set until software clears the FPSCR[IDC] bit.
bogdanm 82:6473597d706e 583 *
bogdanm 82:6473597d706e 584 * Values:
bogdanm 82:6473597d706e 585 * - 0 - No interrupt
bogdanm 82:6473597d706e 586 * - 1 - Interrupt occurred
bogdanm 82:6473597d706e 587 */
bogdanm 82:6473597d706e 588 //@{
bogdanm 82:6473597d706e 589 #define BP_MCM_ISR_FIDC (15U) //!< Bit position for MCM_ISR_FIDC.
bogdanm 82:6473597d706e 590 #define BM_MCM_ISR_FIDC (0x00008000U) //!< Bit mask for MCM_ISR_FIDC.
bogdanm 82:6473597d706e 591 #define BS_MCM_ISR_FIDC (1U) //!< Bit field size in bits for MCM_ISR_FIDC.
bogdanm 82:6473597d706e 592
bogdanm 82:6473597d706e 593 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 594 //! @brief Read current value of the MCM_ISR_FIDC field.
bogdanm 82:6473597d706e 595 #define BR_MCM_ISR_FIDC (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDC))
bogdanm 82:6473597d706e 596 #endif
bogdanm 82:6473597d706e 597 //@}
bogdanm 82:6473597d706e 598
bogdanm 82:6473597d706e 599 /*!
bogdanm 82:6473597d706e 600 * @name Register MCM_ISR, field FIOCE[24] (RW)
bogdanm 82:6473597d706e 601 *
bogdanm 82:6473597d706e 602 * Values:
bogdanm 82:6473597d706e 603 * - 0 - Disable interrupt
bogdanm 82:6473597d706e 604 * - 1 - Enable interrupt
bogdanm 82:6473597d706e 605 */
bogdanm 82:6473597d706e 606 //@{
bogdanm 82:6473597d706e 607 #define BP_MCM_ISR_FIOCE (24U) //!< Bit position for MCM_ISR_FIOCE.
bogdanm 82:6473597d706e 608 #define BM_MCM_ISR_FIOCE (0x01000000U) //!< Bit mask for MCM_ISR_FIOCE.
bogdanm 82:6473597d706e 609 #define BS_MCM_ISR_FIOCE (1U) //!< Bit field size in bits for MCM_ISR_FIOCE.
bogdanm 82:6473597d706e 610
bogdanm 82:6473597d706e 611 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 612 //! @brief Read current value of the MCM_ISR_FIOCE field.
bogdanm 82:6473597d706e 613 #define BR_MCM_ISR_FIOCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOCE))
bogdanm 82:6473597d706e 614 #endif
bogdanm 82:6473597d706e 615
bogdanm 82:6473597d706e 616 //! @brief Format value for bitfield MCM_ISR_FIOCE.
bogdanm 82:6473597d706e 617 #define BF_MCM_ISR_FIOCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIOCE), uint32_t) & BM_MCM_ISR_FIOCE)
bogdanm 82:6473597d706e 618
bogdanm 82:6473597d706e 619 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 620 //! @brief Set the FIOCE field to a new value.
bogdanm 82:6473597d706e 621 #define BW_MCM_ISR_FIOCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIOCE) = (v))
bogdanm 82:6473597d706e 622 #endif
bogdanm 82:6473597d706e 623 //@}
bogdanm 82:6473597d706e 624
bogdanm 82:6473597d706e 625 /*!
bogdanm 82:6473597d706e 626 * @name Register MCM_ISR, field FDZCE[25] (RW)
bogdanm 82:6473597d706e 627 *
bogdanm 82:6473597d706e 628 * Values:
bogdanm 82:6473597d706e 629 * - 0 - Disable interrupt
bogdanm 82:6473597d706e 630 * - 1 - Enable interrupt
bogdanm 82:6473597d706e 631 */
bogdanm 82:6473597d706e 632 //@{
bogdanm 82:6473597d706e 633 #define BP_MCM_ISR_FDZCE (25U) //!< Bit position for MCM_ISR_FDZCE.
bogdanm 82:6473597d706e 634 #define BM_MCM_ISR_FDZCE (0x02000000U) //!< Bit mask for MCM_ISR_FDZCE.
bogdanm 82:6473597d706e 635 #define BS_MCM_ISR_FDZCE (1U) //!< Bit field size in bits for MCM_ISR_FDZCE.
bogdanm 82:6473597d706e 636
bogdanm 82:6473597d706e 637 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 638 //! @brief Read current value of the MCM_ISR_FDZCE field.
bogdanm 82:6473597d706e 639 #define BR_MCM_ISR_FDZCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZCE))
bogdanm 82:6473597d706e 640 #endif
bogdanm 82:6473597d706e 641
bogdanm 82:6473597d706e 642 //! @brief Format value for bitfield MCM_ISR_FDZCE.
bogdanm 82:6473597d706e 643 #define BF_MCM_ISR_FDZCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FDZCE), uint32_t) & BM_MCM_ISR_FDZCE)
bogdanm 82:6473597d706e 644
bogdanm 82:6473597d706e 645 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 646 //! @brief Set the FDZCE field to a new value.
bogdanm 82:6473597d706e 647 #define BW_MCM_ISR_FDZCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FDZCE) = (v))
bogdanm 82:6473597d706e 648 #endif
bogdanm 82:6473597d706e 649 //@}
bogdanm 82:6473597d706e 650
bogdanm 82:6473597d706e 651 /*!
bogdanm 82:6473597d706e 652 * @name Register MCM_ISR, field FOFCE[26] (RW)
bogdanm 82:6473597d706e 653 *
bogdanm 82:6473597d706e 654 * Values:
bogdanm 82:6473597d706e 655 * - 0 - Disable interrupt
bogdanm 82:6473597d706e 656 * - 1 - Enable interrupt
bogdanm 82:6473597d706e 657 */
bogdanm 82:6473597d706e 658 //@{
bogdanm 82:6473597d706e 659 #define BP_MCM_ISR_FOFCE (26U) //!< Bit position for MCM_ISR_FOFCE.
bogdanm 82:6473597d706e 660 #define BM_MCM_ISR_FOFCE (0x04000000U) //!< Bit mask for MCM_ISR_FOFCE.
bogdanm 82:6473597d706e 661 #define BS_MCM_ISR_FOFCE (1U) //!< Bit field size in bits for MCM_ISR_FOFCE.
bogdanm 82:6473597d706e 662
bogdanm 82:6473597d706e 663 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 664 //! @brief Read current value of the MCM_ISR_FOFCE field.
bogdanm 82:6473597d706e 665 #define BR_MCM_ISR_FOFCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFCE))
bogdanm 82:6473597d706e 666 #endif
bogdanm 82:6473597d706e 667
bogdanm 82:6473597d706e 668 //! @brief Format value for bitfield MCM_ISR_FOFCE.
bogdanm 82:6473597d706e 669 #define BF_MCM_ISR_FOFCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FOFCE), uint32_t) & BM_MCM_ISR_FOFCE)
bogdanm 82:6473597d706e 670
bogdanm 82:6473597d706e 671 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 672 //! @brief Set the FOFCE field to a new value.
bogdanm 82:6473597d706e 673 #define BW_MCM_ISR_FOFCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FOFCE) = (v))
bogdanm 82:6473597d706e 674 #endif
bogdanm 82:6473597d706e 675 //@}
bogdanm 82:6473597d706e 676
bogdanm 82:6473597d706e 677 /*!
bogdanm 82:6473597d706e 678 * @name Register MCM_ISR, field FUFCE[27] (RW)
bogdanm 82:6473597d706e 679 *
bogdanm 82:6473597d706e 680 * Values:
bogdanm 82:6473597d706e 681 * - 0 - Disable interrupt
bogdanm 82:6473597d706e 682 * - 1 - Enable interrupt
bogdanm 82:6473597d706e 683 */
bogdanm 82:6473597d706e 684 //@{
bogdanm 82:6473597d706e 685 #define BP_MCM_ISR_FUFCE (27U) //!< Bit position for MCM_ISR_FUFCE.
bogdanm 82:6473597d706e 686 #define BM_MCM_ISR_FUFCE (0x08000000U) //!< Bit mask for MCM_ISR_FUFCE.
bogdanm 82:6473597d706e 687 #define BS_MCM_ISR_FUFCE (1U) //!< Bit field size in bits for MCM_ISR_FUFCE.
bogdanm 82:6473597d706e 688
bogdanm 82:6473597d706e 689 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 690 //! @brief Read current value of the MCM_ISR_FUFCE field.
bogdanm 82:6473597d706e 691 #define BR_MCM_ISR_FUFCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFCE))
bogdanm 82:6473597d706e 692 #endif
bogdanm 82:6473597d706e 693
bogdanm 82:6473597d706e 694 //! @brief Format value for bitfield MCM_ISR_FUFCE.
bogdanm 82:6473597d706e 695 #define BF_MCM_ISR_FUFCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FUFCE), uint32_t) & BM_MCM_ISR_FUFCE)
bogdanm 82:6473597d706e 696
bogdanm 82:6473597d706e 697 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 698 //! @brief Set the FUFCE field to a new value.
bogdanm 82:6473597d706e 699 #define BW_MCM_ISR_FUFCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FUFCE) = (v))
bogdanm 82:6473597d706e 700 #endif
bogdanm 82:6473597d706e 701 //@}
bogdanm 82:6473597d706e 702
bogdanm 82:6473597d706e 703 /*!
bogdanm 82:6473597d706e 704 * @name Register MCM_ISR, field FIXCE[28] (RW)
bogdanm 82:6473597d706e 705 *
bogdanm 82:6473597d706e 706 * Values:
bogdanm 82:6473597d706e 707 * - 0 - Disable interrupt
bogdanm 82:6473597d706e 708 * - 1 - Enable interrupt
bogdanm 82:6473597d706e 709 */
bogdanm 82:6473597d706e 710 //@{
bogdanm 82:6473597d706e 711 #define BP_MCM_ISR_FIXCE (28U) //!< Bit position for MCM_ISR_FIXCE.
bogdanm 82:6473597d706e 712 #define BM_MCM_ISR_FIXCE (0x10000000U) //!< Bit mask for MCM_ISR_FIXCE.
bogdanm 82:6473597d706e 713 #define BS_MCM_ISR_FIXCE (1U) //!< Bit field size in bits for MCM_ISR_FIXCE.
bogdanm 82:6473597d706e 714
bogdanm 82:6473597d706e 715 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 716 //! @brief Read current value of the MCM_ISR_FIXCE field.
bogdanm 82:6473597d706e 717 #define BR_MCM_ISR_FIXCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXCE))
bogdanm 82:6473597d706e 718 #endif
bogdanm 82:6473597d706e 719
bogdanm 82:6473597d706e 720 //! @brief Format value for bitfield MCM_ISR_FIXCE.
bogdanm 82:6473597d706e 721 #define BF_MCM_ISR_FIXCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIXCE), uint32_t) & BM_MCM_ISR_FIXCE)
bogdanm 82:6473597d706e 722
bogdanm 82:6473597d706e 723 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 724 //! @brief Set the FIXCE field to a new value.
bogdanm 82:6473597d706e 725 #define BW_MCM_ISR_FIXCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIXCE) = (v))
bogdanm 82:6473597d706e 726 #endif
bogdanm 82:6473597d706e 727 //@}
bogdanm 82:6473597d706e 728
bogdanm 82:6473597d706e 729 /*!
bogdanm 82:6473597d706e 730 * @name Register MCM_ISR, field FIDCE[31] (RW)
bogdanm 82:6473597d706e 731 *
bogdanm 82:6473597d706e 732 * Values:
bogdanm 82:6473597d706e 733 * - 0 - Disable interrupt
bogdanm 82:6473597d706e 734 * - 1 - Enable interrupt
bogdanm 82:6473597d706e 735 */
bogdanm 82:6473597d706e 736 //@{
bogdanm 82:6473597d706e 737 #define BP_MCM_ISR_FIDCE (31U) //!< Bit position for MCM_ISR_FIDCE.
bogdanm 82:6473597d706e 738 #define BM_MCM_ISR_FIDCE (0x80000000U) //!< Bit mask for MCM_ISR_FIDCE.
bogdanm 82:6473597d706e 739 #define BS_MCM_ISR_FIDCE (1U) //!< Bit field size in bits for MCM_ISR_FIDCE.
bogdanm 82:6473597d706e 740
bogdanm 82:6473597d706e 741 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 742 //! @brief Read current value of the MCM_ISR_FIDCE field.
bogdanm 82:6473597d706e 743 #define BR_MCM_ISR_FIDCE (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDCE))
bogdanm 82:6473597d706e 744 #endif
bogdanm 82:6473597d706e 745
bogdanm 82:6473597d706e 746 //! @brief Format value for bitfield MCM_ISR_FIDCE.
bogdanm 82:6473597d706e 747 #define BF_MCM_ISR_FIDCE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ISR_FIDCE), uint32_t) & BM_MCM_ISR_FIDCE)
bogdanm 82:6473597d706e 748
bogdanm 82:6473597d706e 749 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 750 //! @brief Set the FIDCE field to a new value.
bogdanm 82:6473597d706e 751 #define BW_MCM_ISR_FIDCE(v) (BITBAND_ACCESS32(HW_MCM_ISR_ADDR, BP_MCM_ISR_FIDCE) = (v))
bogdanm 82:6473597d706e 752 #endif
bogdanm 82:6473597d706e 753 //@}
bogdanm 82:6473597d706e 754
bogdanm 82:6473597d706e 755 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 756 // HW_MCM_ETBCC - ETB Counter Control register
bogdanm 82:6473597d706e 757 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 758
bogdanm 82:6473597d706e 759 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 760 /*!
bogdanm 82:6473597d706e 761 * @brief HW_MCM_ETBCC - ETB Counter Control register (RW)
bogdanm 82:6473597d706e 762 *
bogdanm 82:6473597d706e 763 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 764 */
bogdanm 82:6473597d706e 765 typedef union _hw_mcm_etbcc
bogdanm 82:6473597d706e 766 {
bogdanm 82:6473597d706e 767 uint32_t U;
bogdanm 82:6473597d706e 768 struct _hw_mcm_etbcc_bitfields
bogdanm 82:6473597d706e 769 {
bogdanm 82:6473597d706e 770 uint32_t CNTEN : 1; //!< [0] Counter Enable
bogdanm 82:6473597d706e 771 uint32_t RSPT : 2; //!< [2:1] Response Type
bogdanm 82:6473597d706e 772 uint32_t RLRQ : 1; //!< [3] Reload Request
bogdanm 82:6473597d706e 773 uint32_t ETDIS : 1; //!< [4] ETM-To-TPIU Disable
bogdanm 82:6473597d706e 774 uint32_t ITDIS : 1; //!< [5] ITM-To-TPIU Disable
bogdanm 82:6473597d706e 775 uint32_t RESERVED0 : 26; //!< [31:6]
bogdanm 82:6473597d706e 776 } B;
bogdanm 82:6473597d706e 777 } hw_mcm_etbcc_t;
bogdanm 82:6473597d706e 778 #endif
bogdanm 82:6473597d706e 779
bogdanm 82:6473597d706e 780 /*!
bogdanm 82:6473597d706e 781 * @name Constants and macros for entire MCM_ETBCC register
bogdanm 82:6473597d706e 782 */
bogdanm 82:6473597d706e 783 //@{
bogdanm 82:6473597d706e 784 #define HW_MCM_ETBCC_ADDR (REGS_MCM_BASE + 0x14U)
bogdanm 82:6473597d706e 785
bogdanm 82:6473597d706e 786 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 787 #define HW_MCM_ETBCC (*(__IO hw_mcm_etbcc_t *) HW_MCM_ETBCC_ADDR)
bogdanm 82:6473597d706e 788 #define HW_MCM_ETBCC_RD() (HW_MCM_ETBCC.U)
bogdanm 82:6473597d706e 789 #define HW_MCM_ETBCC_WR(v) (HW_MCM_ETBCC.U = (v))
bogdanm 82:6473597d706e 790 #define HW_MCM_ETBCC_SET(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() | (v)))
bogdanm 82:6473597d706e 791 #define HW_MCM_ETBCC_CLR(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() & ~(v)))
bogdanm 82:6473597d706e 792 #define HW_MCM_ETBCC_TOG(v) (HW_MCM_ETBCC_WR(HW_MCM_ETBCC_RD() ^ (v)))
bogdanm 82:6473597d706e 793 #endif
bogdanm 82:6473597d706e 794 //@}
bogdanm 82:6473597d706e 795
bogdanm 82:6473597d706e 796 /*
bogdanm 82:6473597d706e 797 * Constants & macros for individual MCM_ETBCC bitfields
bogdanm 82:6473597d706e 798 */
bogdanm 82:6473597d706e 799
bogdanm 82:6473597d706e 800 /*!
bogdanm 82:6473597d706e 801 * @name Register MCM_ETBCC, field CNTEN[0] (RW)
bogdanm 82:6473597d706e 802 *
bogdanm 82:6473597d706e 803 * Enables the ETB counter.
bogdanm 82:6473597d706e 804 *
bogdanm 82:6473597d706e 805 * Values:
bogdanm 82:6473597d706e 806 * - 0 - ETB counter disabled
bogdanm 82:6473597d706e 807 * - 1 - ETB counter enabled
bogdanm 82:6473597d706e 808 */
bogdanm 82:6473597d706e 809 //@{
bogdanm 82:6473597d706e 810 #define BP_MCM_ETBCC_CNTEN (0U) //!< Bit position for MCM_ETBCC_CNTEN.
bogdanm 82:6473597d706e 811 #define BM_MCM_ETBCC_CNTEN (0x00000001U) //!< Bit mask for MCM_ETBCC_CNTEN.
bogdanm 82:6473597d706e 812 #define BS_MCM_ETBCC_CNTEN (1U) //!< Bit field size in bits for MCM_ETBCC_CNTEN.
bogdanm 82:6473597d706e 813
bogdanm 82:6473597d706e 814 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 815 //! @brief Read current value of the MCM_ETBCC_CNTEN field.
bogdanm 82:6473597d706e 816 #define BR_MCM_ETBCC_CNTEN (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_CNTEN))
bogdanm 82:6473597d706e 817 #endif
bogdanm 82:6473597d706e 818
bogdanm 82:6473597d706e 819 //! @brief Format value for bitfield MCM_ETBCC_CNTEN.
bogdanm 82:6473597d706e 820 #define BF_MCM_ETBCC_CNTEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_CNTEN), uint32_t) & BM_MCM_ETBCC_CNTEN)
bogdanm 82:6473597d706e 821
bogdanm 82:6473597d706e 822 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 823 //! @brief Set the CNTEN field to a new value.
bogdanm 82:6473597d706e 824 #define BW_MCM_ETBCC_CNTEN(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_CNTEN) = (v))
bogdanm 82:6473597d706e 825 #endif
bogdanm 82:6473597d706e 826 //@}
bogdanm 82:6473597d706e 827
bogdanm 82:6473597d706e 828 /*!
bogdanm 82:6473597d706e 829 * @name Register MCM_ETBCC, field RSPT[2:1] (RW)
bogdanm 82:6473597d706e 830 *
bogdanm 82:6473597d706e 831 * Values:
bogdanm 82:6473597d706e 832 * - 00 - No response when the ETB count expires
bogdanm 82:6473597d706e 833 * - 01 - Generate a normal interrupt when the ETB count expires
bogdanm 82:6473597d706e 834 * - 10 - Generate an NMI when the ETB count expires
bogdanm 82:6473597d706e 835 * - 11 - Generate a debug halt when the ETB count expires
bogdanm 82:6473597d706e 836 */
bogdanm 82:6473597d706e 837 //@{
bogdanm 82:6473597d706e 838 #define BP_MCM_ETBCC_RSPT (1U) //!< Bit position for MCM_ETBCC_RSPT.
bogdanm 82:6473597d706e 839 #define BM_MCM_ETBCC_RSPT (0x00000006U) //!< Bit mask for MCM_ETBCC_RSPT.
bogdanm 82:6473597d706e 840 #define BS_MCM_ETBCC_RSPT (2U) //!< Bit field size in bits for MCM_ETBCC_RSPT.
bogdanm 82:6473597d706e 841
bogdanm 82:6473597d706e 842 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 843 //! @brief Read current value of the MCM_ETBCC_RSPT field.
bogdanm 82:6473597d706e 844 #define BR_MCM_ETBCC_RSPT (HW_MCM_ETBCC.B.RSPT)
bogdanm 82:6473597d706e 845 #endif
bogdanm 82:6473597d706e 846
bogdanm 82:6473597d706e 847 //! @brief Format value for bitfield MCM_ETBCC_RSPT.
bogdanm 82:6473597d706e 848 #define BF_MCM_ETBCC_RSPT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_RSPT), uint32_t) & BM_MCM_ETBCC_RSPT)
bogdanm 82:6473597d706e 849
bogdanm 82:6473597d706e 850 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 851 //! @brief Set the RSPT field to a new value.
bogdanm 82:6473597d706e 852 #define BW_MCM_ETBCC_RSPT(v) (HW_MCM_ETBCC_WR((HW_MCM_ETBCC_RD() & ~BM_MCM_ETBCC_RSPT) | BF_MCM_ETBCC_RSPT(v)))
bogdanm 82:6473597d706e 853 #endif
bogdanm 82:6473597d706e 854 //@}
bogdanm 82:6473597d706e 855
bogdanm 82:6473597d706e 856 /*!
bogdanm 82:6473597d706e 857 * @name Register MCM_ETBCC, field RLRQ[3] (RW)
bogdanm 82:6473597d706e 858 *
bogdanm 82:6473597d706e 859 * Reloads the ETB packet counter with the MCM_ETBRL RELOAD value. If IRQ or NMI
bogdanm 82:6473597d706e 860 * interrupts were enabled and an NMI or IRQ interrupt was generated on counter
bogdanm 82:6473597d706e 861 * expiration, setting this bit clears the pending NMI or IRQ interrupt request.
bogdanm 82:6473597d706e 862 * If debug halt was enabled and a debug halt request was asserted on counter
bogdanm 82:6473597d706e 863 * expiration, setting this bit clears the debug halt request.
bogdanm 82:6473597d706e 864 *
bogdanm 82:6473597d706e 865 * Values:
bogdanm 82:6473597d706e 866 * - 0 - No effect
bogdanm 82:6473597d706e 867 * - 1 - Clears pending debug halt, NMI, or IRQ interrupt requests
bogdanm 82:6473597d706e 868 */
bogdanm 82:6473597d706e 869 //@{
bogdanm 82:6473597d706e 870 #define BP_MCM_ETBCC_RLRQ (3U) //!< Bit position for MCM_ETBCC_RLRQ.
bogdanm 82:6473597d706e 871 #define BM_MCM_ETBCC_RLRQ (0x00000008U) //!< Bit mask for MCM_ETBCC_RLRQ.
bogdanm 82:6473597d706e 872 #define BS_MCM_ETBCC_RLRQ (1U) //!< Bit field size in bits for MCM_ETBCC_RLRQ.
bogdanm 82:6473597d706e 873
bogdanm 82:6473597d706e 874 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 875 //! @brief Read current value of the MCM_ETBCC_RLRQ field.
bogdanm 82:6473597d706e 876 #define BR_MCM_ETBCC_RLRQ (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_RLRQ))
bogdanm 82:6473597d706e 877 #endif
bogdanm 82:6473597d706e 878
bogdanm 82:6473597d706e 879 //! @brief Format value for bitfield MCM_ETBCC_RLRQ.
bogdanm 82:6473597d706e 880 #define BF_MCM_ETBCC_RLRQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_RLRQ), uint32_t) & BM_MCM_ETBCC_RLRQ)
bogdanm 82:6473597d706e 881
bogdanm 82:6473597d706e 882 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 883 //! @brief Set the RLRQ field to a new value.
bogdanm 82:6473597d706e 884 #define BW_MCM_ETBCC_RLRQ(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_RLRQ) = (v))
bogdanm 82:6473597d706e 885 #endif
bogdanm 82:6473597d706e 886 //@}
bogdanm 82:6473597d706e 887
bogdanm 82:6473597d706e 888 /*!
bogdanm 82:6473597d706e 889 * @name Register MCM_ETBCC, field ETDIS[4] (RW)
bogdanm 82:6473597d706e 890 *
bogdanm 82:6473597d706e 891 * Disables the trace path from ETM to TPIU.
bogdanm 82:6473597d706e 892 *
bogdanm 82:6473597d706e 893 * Values:
bogdanm 82:6473597d706e 894 * - 0 - ETM-to-TPIU trace path enabled
bogdanm 82:6473597d706e 895 * - 1 - ETM-to-TPIU trace path disabled
bogdanm 82:6473597d706e 896 */
bogdanm 82:6473597d706e 897 //@{
bogdanm 82:6473597d706e 898 #define BP_MCM_ETBCC_ETDIS (4U) //!< Bit position for MCM_ETBCC_ETDIS.
bogdanm 82:6473597d706e 899 #define BM_MCM_ETBCC_ETDIS (0x00000010U) //!< Bit mask for MCM_ETBCC_ETDIS.
bogdanm 82:6473597d706e 900 #define BS_MCM_ETBCC_ETDIS (1U) //!< Bit field size in bits for MCM_ETBCC_ETDIS.
bogdanm 82:6473597d706e 901
bogdanm 82:6473597d706e 902 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 903 //! @brief Read current value of the MCM_ETBCC_ETDIS field.
bogdanm 82:6473597d706e 904 #define BR_MCM_ETBCC_ETDIS (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ETDIS))
bogdanm 82:6473597d706e 905 #endif
bogdanm 82:6473597d706e 906
bogdanm 82:6473597d706e 907 //! @brief Format value for bitfield MCM_ETBCC_ETDIS.
bogdanm 82:6473597d706e 908 #define BF_MCM_ETBCC_ETDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_ETDIS), uint32_t) & BM_MCM_ETBCC_ETDIS)
bogdanm 82:6473597d706e 909
bogdanm 82:6473597d706e 910 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 911 //! @brief Set the ETDIS field to a new value.
bogdanm 82:6473597d706e 912 #define BW_MCM_ETBCC_ETDIS(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ETDIS) = (v))
bogdanm 82:6473597d706e 913 #endif
bogdanm 82:6473597d706e 914 //@}
bogdanm 82:6473597d706e 915
bogdanm 82:6473597d706e 916 /*!
bogdanm 82:6473597d706e 917 * @name Register MCM_ETBCC, field ITDIS[5] (RW)
bogdanm 82:6473597d706e 918 *
bogdanm 82:6473597d706e 919 * Disables the trace path from ITM to TPIU.
bogdanm 82:6473597d706e 920 *
bogdanm 82:6473597d706e 921 * Values:
bogdanm 82:6473597d706e 922 * - 0 - ITM-to-TPIU trace path enabled
bogdanm 82:6473597d706e 923 * - 1 - ITM-to-TPIU trace path disabled
bogdanm 82:6473597d706e 924 */
bogdanm 82:6473597d706e 925 //@{
bogdanm 82:6473597d706e 926 #define BP_MCM_ETBCC_ITDIS (5U) //!< Bit position for MCM_ETBCC_ITDIS.
bogdanm 82:6473597d706e 927 #define BM_MCM_ETBCC_ITDIS (0x00000020U) //!< Bit mask for MCM_ETBCC_ITDIS.
bogdanm 82:6473597d706e 928 #define BS_MCM_ETBCC_ITDIS (1U) //!< Bit field size in bits for MCM_ETBCC_ITDIS.
bogdanm 82:6473597d706e 929
bogdanm 82:6473597d706e 930 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 931 //! @brief Read current value of the MCM_ETBCC_ITDIS field.
bogdanm 82:6473597d706e 932 #define BR_MCM_ETBCC_ITDIS (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ITDIS))
bogdanm 82:6473597d706e 933 #endif
bogdanm 82:6473597d706e 934
bogdanm 82:6473597d706e 935 //! @brief Format value for bitfield MCM_ETBCC_ITDIS.
bogdanm 82:6473597d706e 936 #define BF_MCM_ETBCC_ITDIS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBCC_ITDIS), uint32_t) & BM_MCM_ETBCC_ITDIS)
bogdanm 82:6473597d706e 937
bogdanm 82:6473597d706e 938 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 939 //! @brief Set the ITDIS field to a new value.
bogdanm 82:6473597d706e 940 #define BW_MCM_ETBCC_ITDIS(v) (BITBAND_ACCESS32(HW_MCM_ETBCC_ADDR, BP_MCM_ETBCC_ITDIS) = (v))
bogdanm 82:6473597d706e 941 #endif
bogdanm 82:6473597d706e 942 //@}
bogdanm 82:6473597d706e 943
bogdanm 82:6473597d706e 944 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 945 // HW_MCM_ETBRL - ETB Reload register
bogdanm 82:6473597d706e 946 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 947
bogdanm 82:6473597d706e 948 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 949 /*!
bogdanm 82:6473597d706e 950 * @brief HW_MCM_ETBRL - ETB Reload register (RW)
bogdanm 82:6473597d706e 951 *
bogdanm 82:6473597d706e 952 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 953 */
bogdanm 82:6473597d706e 954 typedef union _hw_mcm_etbrl
bogdanm 82:6473597d706e 955 {
bogdanm 82:6473597d706e 956 uint32_t U;
bogdanm 82:6473597d706e 957 struct _hw_mcm_etbrl_bitfields
bogdanm 82:6473597d706e 958 {
bogdanm 82:6473597d706e 959 uint32_t RELOAD : 11; //!< [10:0] Byte Count Reload Value
bogdanm 82:6473597d706e 960 uint32_t RESERVED0 : 21; //!< [31:11]
bogdanm 82:6473597d706e 961 } B;
bogdanm 82:6473597d706e 962 } hw_mcm_etbrl_t;
bogdanm 82:6473597d706e 963 #endif
bogdanm 82:6473597d706e 964
bogdanm 82:6473597d706e 965 /*!
bogdanm 82:6473597d706e 966 * @name Constants and macros for entire MCM_ETBRL register
bogdanm 82:6473597d706e 967 */
bogdanm 82:6473597d706e 968 //@{
bogdanm 82:6473597d706e 969 #define HW_MCM_ETBRL_ADDR (REGS_MCM_BASE + 0x18U)
bogdanm 82:6473597d706e 970
bogdanm 82:6473597d706e 971 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 972 #define HW_MCM_ETBRL (*(__IO hw_mcm_etbrl_t *) HW_MCM_ETBRL_ADDR)
bogdanm 82:6473597d706e 973 #define HW_MCM_ETBRL_RD() (HW_MCM_ETBRL.U)
bogdanm 82:6473597d706e 974 #define HW_MCM_ETBRL_WR(v) (HW_MCM_ETBRL.U = (v))
bogdanm 82:6473597d706e 975 #define HW_MCM_ETBRL_SET(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() | (v)))
bogdanm 82:6473597d706e 976 #define HW_MCM_ETBRL_CLR(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() & ~(v)))
bogdanm 82:6473597d706e 977 #define HW_MCM_ETBRL_TOG(v) (HW_MCM_ETBRL_WR(HW_MCM_ETBRL_RD() ^ (v)))
bogdanm 82:6473597d706e 978 #endif
bogdanm 82:6473597d706e 979 //@}
bogdanm 82:6473597d706e 980
bogdanm 82:6473597d706e 981 /*
bogdanm 82:6473597d706e 982 * Constants & macros for individual MCM_ETBRL bitfields
bogdanm 82:6473597d706e 983 */
bogdanm 82:6473597d706e 984
bogdanm 82:6473597d706e 985 /*!
bogdanm 82:6473597d706e 986 * @name Register MCM_ETBRL, field RELOAD[10:0] (RW)
bogdanm 82:6473597d706e 987 *
bogdanm 82:6473597d706e 988 * Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4
bogdanm 82:6473597d706e 989 * value to this field results in a bus error.
bogdanm 82:6473597d706e 990 */
bogdanm 82:6473597d706e 991 //@{
bogdanm 82:6473597d706e 992 #define BP_MCM_ETBRL_RELOAD (0U) //!< Bit position for MCM_ETBRL_RELOAD.
bogdanm 82:6473597d706e 993 #define BM_MCM_ETBRL_RELOAD (0x000007FFU) //!< Bit mask for MCM_ETBRL_RELOAD.
bogdanm 82:6473597d706e 994 #define BS_MCM_ETBRL_RELOAD (11U) //!< Bit field size in bits for MCM_ETBRL_RELOAD.
bogdanm 82:6473597d706e 995
bogdanm 82:6473597d706e 996 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 997 //! @brief Read current value of the MCM_ETBRL_RELOAD field.
bogdanm 82:6473597d706e 998 #define BR_MCM_ETBRL_RELOAD (HW_MCM_ETBRL.B.RELOAD)
bogdanm 82:6473597d706e 999 #endif
bogdanm 82:6473597d706e 1000
bogdanm 82:6473597d706e 1001 //! @brief Format value for bitfield MCM_ETBRL_RELOAD.
bogdanm 82:6473597d706e 1002 #define BF_MCM_ETBRL_RELOAD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_ETBRL_RELOAD), uint32_t) & BM_MCM_ETBRL_RELOAD)
bogdanm 82:6473597d706e 1003
bogdanm 82:6473597d706e 1004 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1005 //! @brief Set the RELOAD field to a new value.
bogdanm 82:6473597d706e 1006 #define BW_MCM_ETBRL_RELOAD(v) (HW_MCM_ETBRL_WR((HW_MCM_ETBRL_RD() & ~BM_MCM_ETBRL_RELOAD) | BF_MCM_ETBRL_RELOAD(v)))
bogdanm 82:6473597d706e 1007 #endif
bogdanm 82:6473597d706e 1008 //@}
bogdanm 82:6473597d706e 1009
bogdanm 82:6473597d706e 1010 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1011 // HW_MCM_ETBCNT - ETB Counter Value register
bogdanm 82:6473597d706e 1012 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1013
bogdanm 82:6473597d706e 1014 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1015 /*!
bogdanm 82:6473597d706e 1016 * @brief HW_MCM_ETBCNT - ETB Counter Value register (RO)
bogdanm 82:6473597d706e 1017 *
bogdanm 82:6473597d706e 1018 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 1019 */
bogdanm 82:6473597d706e 1020 typedef union _hw_mcm_etbcnt
bogdanm 82:6473597d706e 1021 {
bogdanm 82:6473597d706e 1022 uint32_t U;
bogdanm 82:6473597d706e 1023 struct _hw_mcm_etbcnt_bitfields
bogdanm 82:6473597d706e 1024 {
bogdanm 82:6473597d706e 1025 uint32_t COUNTER : 11; //!< [10:0] Byte Count Counter Value
bogdanm 82:6473597d706e 1026 uint32_t RESERVED0 : 21; //!< [31:11]
bogdanm 82:6473597d706e 1027 } B;
bogdanm 82:6473597d706e 1028 } hw_mcm_etbcnt_t;
bogdanm 82:6473597d706e 1029 #endif
bogdanm 82:6473597d706e 1030
bogdanm 82:6473597d706e 1031 /*!
bogdanm 82:6473597d706e 1032 * @name Constants and macros for entire MCM_ETBCNT register
bogdanm 82:6473597d706e 1033 */
bogdanm 82:6473597d706e 1034 //@{
bogdanm 82:6473597d706e 1035 #define HW_MCM_ETBCNT_ADDR (REGS_MCM_BASE + 0x1CU)
bogdanm 82:6473597d706e 1036
bogdanm 82:6473597d706e 1037 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1038 #define HW_MCM_ETBCNT (*(__I hw_mcm_etbcnt_t *) HW_MCM_ETBCNT_ADDR)
bogdanm 82:6473597d706e 1039 #define HW_MCM_ETBCNT_RD() (HW_MCM_ETBCNT.U)
bogdanm 82:6473597d706e 1040 #endif
bogdanm 82:6473597d706e 1041 //@}
bogdanm 82:6473597d706e 1042
bogdanm 82:6473597d706e 1043 /*
bogdanm 82:6473597d706e 1044 * Constants & macros for individual MCM_ETBCNT bitfields
bogdanm 82:6473597d706e 1045 */
bogdanm 82:6473597d706e 1046
bogdanm 82:6473597d706e 1047 /*!
bogdanm 82:6473597d706e 1048 * @name Register MCM_ETBCNT, field COUNTER[10:0] (RO)
bogdanm 82:6473597d706e 1049 *
bogdanm 82:6473597d706e 1050 * Indicates the current 0-mod-4 value of the counter.
bogdanm 82:6473597d706e 1051 */
bogdanm 82:6473597d706e 1052 //@{
bogdanm 82:6473597d706e 1053 #define BP_MCM_ETBCNT_COUNTER (0U) //!< Bit position for MCM_ETBCNT_COUNTER.
bogdanm 82:6473597d706e 1054 #define BM_MCM_ETBCNT_COUNTER (0x000007FFU) //!< Bit mask for MCM_ETBCNT_COUNTER.
bogdanm 82:6473597d706e 1055 #define BS_MCM_ETBCNT_COUNTER (11U) //!< Bit field size in bits for MCM_ETBCNT_COUNTER.
bogdanm 82:6473597d706e 1056
bogdanm 82:6473597d706e 1057 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1058 //! @brief Read current value of the MCM_ETBCNT_COUNTER field.
bogdanm 82:6473597d706e 1059 #define BR_MCM_ETBCNT_COUNTER (HW_MCM_ETBCNT.B.COUNTER)
bogdanm 82:6473597d706e 1060 #endif
bogdanm 82:6473597d706e 1061 //@}
bogdanm 82:6473597d706e 1062
bogdanm 82:6473597d706e 1063 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1064 // HW_MCM_PID - Process ID register
bogdanm 82:6473597d706e 1065 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1066
bogdanm 82:6473597d706e 1067 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1068 /*!
bogdanm 82:6473597d706e 1069 * @brief HW_MCM_PID - Process ID register (RW)
bogdanm 82:6473597d706e 1070 *
bogdanm 82:6473597d706e 1071 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 1072 *
bogdanm 82:6473597d706e 1073 * This register drives the M0_PID and M1_PID values in the Memory Protection
bogdanm 82:6473597d706e 1074 * Unit(MPU). System software loads this register before passing control to a given
bogdanm 82:6473597d706e 1075 * user mode process. If the PID of the process does not match the value in this
bogdanm 82:6473597d706e 1076 * register, a bus error occurs. See the MPU chapter for more details.
bogdanm 82:6473597d706e 1077 */
bogdanm 82:6473597d706e 1078 typedef union _hw_mcm_pid
bogdanm 82:6473597d706e 1079 {
bogdanm 82:6473597d706e 1080 uint32_t U;
bogdanm 82:6473597d706e 1081 struct _hw_mcm_pid_bitfields
bogdanm 82:6473597d706e 1082 {
bogdanm 82:6473597d706e 1083 uint32_t PID : 8; //!< [7:0] M0_PID And M1_PID For MPU
bogdanm 82:6473597d706e 1084 uint32_t RESERVED0 : 24; //!< [31:8]
bogdanm 82:6473597d706e 1085 } B;
bogdanm 82:6473597d706e 1086 } hw_mcm_pid_t;
bogdanm 82:6473597d706e 1087 #endif
bogdanm 82:6473597d706e 1088
bogdanm 82:6473597d706e 1089 /*!
bogdanm 82:6473597d706e 1090 * @name Constants and macros for entire MCM_PID register
bogdanm 82:6473597d706e 1091 */
bogdanm 82:6473597d706e 1092 //@{
bogdanm 82:6473597d706e 1093 #define HW_MCM_PID_ADDR (REGS_MCM_BASE + 0x30U)
bogdanm 82:6473597d706e 1094
bogdanm 82:6473597d706e 1095 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1096 #define HW_MCM_PID (*(__IO hw_mcm_pid_t *) HW_MCM_PID_ADDR)
bogdanm 82:6473597d706e 1097 #define HW_MCM_PID_RD() (HW_MCM_PID.U)
bogdanm 82:6473597d706e 1098 #define HW_MCM_PID_WR(v) (HW_MCM_PID.U = (v))
bogdanm 82:6473597d706e 1099 #define HW_MCM_PID_SET(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() | (v)))
bogdanm 82:6473597d706e 1100 #define HW_MCM_PID_CLR(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() & ~(v)))
bogdanm 82:6473597d706e 1101 #define HW_MCM_PID_TOG(v) (HW_MCM_PID_WR(HW_MCM_PID_RD() ^ (v)))
bogdanm 82:6473597d706e 1102 #endif
bogdanm 82:6473597d706e 1103 //@}
bogdanm 82:6473597d706e 1104
bogdanm 82:6473597d706e 1105 /*
bogdanm 82:6473597d706e 1106 * Constants & macros for individual MCM_PID bitfields
bogdanm 82:6473597d706e 1107 */
bogdanm 82:6473597d706e 1108
bogdanm 82:6473597d706e 1109 /*!
bogdanm 82:6473597d706e 1110 * @name Register MCM_PID, field PID[7:0] (RW)
bogdanm 82:6473597d706e 1111 *
bogdanm 82:6473597d706e 1112 * Drives the M0_PID and M1_PID values in the MPU.
bogdanm 82:6473597d706e 1113 */
bogdanm 82:6473597d706e 1114 //@{
bogdanm 82:6473597d706e 1115 #define BP_MCM_PID_PID (0U) //!< Bit position for MCM_PID_PID.
bogdanm 82:6473597d706e 1116 #define BM_MCM_PID_PID (0x000000FFU) //!< Bit mask for MCM_PID_PID.
bogdanm 82:6473597d706e 1117 #define BS_MCM_PID_PID (8U) //!< Bit field size in bits for MCM_PID_PID.
bogdanm 82:6473597d706e 1118
bogdanm 82:6473597d706e 1119 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1120 //! @brief Read current value of the MCM_PID_PID field.
bogdanm 82:6473597d706e 1121 #define BR_MCM_PID_PID (HW_MCM_PID.B.PID)
bogdanm 82:6473597d706e 1122 #endif
bogdanm 82:6473597d706e 1123
bogdanm 82:6473597d706e 1124 //! @brief Format value for bitfield MCM_PID_PID.
bogdanm 82:6473597d706e 1125 #define BF_MCM_PID_PID(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_MCM_PID_PID), uint32_t) & BM_MCM_PID_PID)
bogdanm 82:6473597d706e 1126
bogdanm 82:6473597d706e 1127 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1128 //! @brief Set the PID field to a new value.
bogdanm 82:6473597d706e 1129 #define BW_MCM_PID_PID(v) (HW_MCM_PID_WR((HW_MCM_PID_RD() & ~BM_MCM_PID_PID) | BF_MCM_PID_PID(v)))
bogdanm 82:6473597d706e 1130 #endif
bogdanm 82:6473597d706e 1131 //@}
bogdanm 82:6473597d706e 1132
bogdanm 82:6473597d706e 1133 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1134 // hw_mcm_t - module struct
bogdanm 82:6473597d706e 1135 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 1136 /*!
bogdanm 82:6473597d706e 1137 * @brief All MCM module registers.
bogdanm 82:6473597d706e 1138 */
bogdanm 82:6473597d706e 1139 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 1140 #pragma pack(1)
bogdanm 82:6473597d706e 1141 typedef struct _hw_mcm
bogdanm 82:6473597d706e 1142 {
bogdanm 82:6473597d706e 1143 uint8_t _reserved0[8];
bogdanm 82:6473597d706e 1144 __I hw_mcm_plasc_t PLASC; //!< [0x8] Crossbar Switch (AXBS) Slave Configuration
bogdanm 82:6473597d706e 1145 __I hw_mcm_plamc_t PLAMC; //!< [0xA] Crossbar Switch (AXBS) Master Configuration
bogdanm 82:6473597d706e 1146 __IO hw_mcm_cr_t CR; //!< [0xC] Control Register
bogdanm 82:6473597d706e 1147 __IO hw_mcm_isr_t ISR; //!< [0x10] Interrupt Status Register
bogdanm 82:6473597d706e 1148 __IO hw_mcm_etbcc_t ETBCC; //!< [0x14] ETB Counter Control register
bogdanm 82:6473597d706e 1149 __IO hw_mcm_etbrl_t ETBRL; //!< [0x18] ETB Reload register
bogdanm 82:6473597d706e 1150 __I hw_mcm_etbcnt_t ETBCNT; //!< [0x1C] ETB Counter Value register
bogdanm 82:6473597d706e 1151 uint8_t _reserved1[16];
bogdanm 82:6473597d706e 1152 __IO hw_mcm_pid_t PID; //!< [0x30] Process ID register
bogdanm 82:6473597d706e 1153 } hw_mcm_t;
bogdanm 82:6473597d706e 1154 #pragma pack()
bogdanm 82:6473597d706e 1155
bogdanm 82:6473597d706e 1156 //! @brief Macro to access all MCM registers.
bogdanm 82:6473597d706e 1157 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 1158 //! use the '&' operator, like <code>&HW_MCM</code>.
bogdanm 82:6473597d706e 1159 #define HW_MCM (*(hw_mcm_t *) REGS_MCM_BASE)
bogdanm 82:6473597d706e 1160 #endif
bogdanm 82:6473597d706e 1161
bogdanm 82:6473597d706e 1162 #endif // __HW_MCM_REGISTERS_H__
bogdanm 82:6473597d706e 1163 // v22/130726/0.9
bogdanm 82:6473597d706e 1164 // EOF