Ricardo Benitez / mbed

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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_gpio.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Parent:
TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_gpio.h@82:6473597d706e 
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_GPIO_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_GPIO_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 GPIO
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * General Purpose Input/Output
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_GPIO_PDOR - Port Data Output Register
bogdanm 82:6473597d706e 33 * - HW_GPIO_PSOR - Port Set Output Register
bogdanm 82:6473597d706e 34 * - HW_GPIO_PCOR - Port Clear Output Register
bogdanm 82:6473597d706e 35 * - HW_GPIO_PTOR - Port Toggle Output Register
bogdanm 82:6473597d706e 36 * - HW_GPIO_PDIR - Port Data Input Register
bogdanm 82:6473597d706e 37 * - HW_GPIO_PDDR - Port Data Direction Register
bogdanm 82:6473597d706e 38 *
bogdanm 82:6473597d706e 39 * - hw_gpio_t - Struct containing all module registers.
bogdanm 82:6473597d706e 40 */
bogdanm 82:6473597d706e 41
bogdanm 82:6473597d706e 42 //! @name Module base addresses
bogdanm 82:6473597d706e 43 //@{
bogdanm 82:6473597d706e 44 #ifndef REGS_GPIO_BASE
bogdanm 82:6473597d706e 45 #define HW_GPIO_INSTANCE_COUNT (5U) //!< Number of instances of the GPIO module.
bogdanm 82:6473597d706e 46 #define HW_GPIOA (0U) //!< Instance number for GPIOA.
bogdanm 82:6473597d706e 47 #define HW_GPIOB (1U) //!< Instance number for GPIOB.
bogdanm 82:6473597d706e 48 #define HW_GPIOC (2U) //!< Instance number for GPIOC.
bogdanm 82:6473597d706e 49 #define HW_GPIOD (3U) //!< Instance number for GPIOD.
bogdanm 82:6473597d706e 50 #define HW_GPIOE (4U) //!< Instance number for GPIOE.
bogdanm 82:6473597d706e 51 #define REGS_GPIOA_BASE (0x400FF000U) //!< Base address for GPIOA.
bogdanm 82:6473597d706e 52 #define REGS_GPIOB_BASE (0x400FF040U) //!< Base address for GPIOB.
bogdanm 82:6473597d706e 53 #define REGS_GPIOC_BASE (0x400FF080U) //!< Base address for GPIOC.
bogdanm 82:6473597d706e 54 #define REGS_GPIOD_BASE (0x400FF0C0U) //!< Base address for GPIOD.
bogdanm 82:6473597d706e 55 #define REGS_GPIOE_BASE (0x400FF100U) //!< Base address for GPIOE.
bogdanm 82:6473597d706e 56
bogdanm 82:6473597d706e 57 //! @brief Table of base addresses for GPIO instances.
bogdanm 82:6473597d706e 58 static const uint32_t __g_regs_GPIO_base_addresses[] = {
bogdanm 82:6473597d706e 59 REGS_GPIOA_BASE,
bogdanm 82:6473597d706e 60 REGS_GPIOB_BASE,
bogdanm 82:6473597d706e 61 REGS_GPIOC_BASE,
bogdanm 82:6473597d706e 62 REGS_GPIOD_BASE,
bogdanm 82:6473597d706e 63 REGS_GPIOE_BASE,
bogdanm 82:6473597d706e 64 };
bogdanm 82:6473597d706e 65
bogdanm 82:6473597d706e 66 //! @brief Get the base address of GPIO by instance number.
bogdanm 82:6473597d706e 67 //! @param x GPIO instance number, from 0 through 4.
bogdanm 82:6473597d706e 68 #define REGS_GPIO_BASE(x) (__g_regs_GPIO_base_addresses[(x)])
bogdanm 82:6473597d706e 69
bogdanm 82:6473597d706e 70 //! @brief Get the instance number given a base address.
bogdanm 82:6473597d706e 71 //! @param b Base address for an instance of GPIO.
bogdanm 82:6473597d706e 72 #define REGS_GPIO_INSTANCE(b) ((b) == REGS_GPIOA_BASE ? HW_GPIOA : (b) == REGS_GPIOB_BASE ? HW_GPIOB : (b) == REGS_GPIOC_BASE ? HW_GPIOC : (b) == REGS_GPIOD_BASE ? HW_GPIOD : (b) == REGS_GPIOE_BASE ? HW_GPIOE : 0)
bogdanm 82:6473597d706e 73 #endif
bogdanm 82:6473597d706e 74 //@}
bogdanm 82:6473597d706e 75
bogdanm 82:6473597d706e 76 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 77 // HW_GPIO_PDOR - Port Data Output Register
bogdanm 82:6473597d706e 78 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 79
bogdanm 82:6473597d706e 80 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 81 /*!
bogdanm 82:6473597d706e 82 * @brief HW_GPIO_PDOR - Port Data Output Register (RW)
bogdanm 82:6473597d706e 83 *
bogdanm 82:6473597d706e 84 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 85 *
bogdanm 82:6473597d706e 86 * This register configures the logic levels that are driven on each
bogdanm 82:6473597d706e 87 * general-purpose output pins. Do not modify pin configuration registers associated with
bogdanm 82:6473597d706e 88 * pins not available in your selected package. All unbonded pins not available in
bogdanm 82:6473597d706e 89 * your package will default to DISABLE state for lowest power consumption.
bogdanm 82:6473597d706e 90 */
bogdanm 82:6473597d706e 91 typedef union _hw_gpio_pdor
bogdanm 82:6473597d706e 92 {
bogdanm 82:6473597d706e 93 uint32_t U;
bogdanm 82:6473597d706e 94 struct _hw_gpio_pdor_bitfields
bogdanm 82:6473597d706e 95 {
bogdanm 82:6473597d706e 96 uint32_t PDO : 32; //!< [31:0] Port Data Output
bogdanm 82:6473597d706e 97 } B;
bogdanm 82:6473597d706e 98 } hw_gpio_pdor_t;
bogdanm 82:6473597d706e 99 #endif
bogdanm 82:6473597d706e 100
bogdanm 82:6473597d706e 101 /*!
bogdanm 82:6473597d706e 102 * @name Constants and macros for entire GPIO_PDOR register
bogdanm 82:6473597d706e 103 */
bogdanm 82:6473597d706e 104 //@{
bogdanm 82:6473597d706e 105 #define HW_GPIO_PDOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x0U)
bogdanm 82:6473597d706e 106
bogdanm 82:6473597d706e 107 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 108 #define HW_GPIO_PDOR(x) (*(__IO hw_gpio_pdor_t *) HW_GPIO_PDOR_ADDR(x))
bogdanm 82:6473597d706e 109 #define HW_GPIO_PDOR_RD(x) (HW_GPIO_PDOR(x).U)
bogdanm 82:6473597d706e 110 #define HW_GPIO_PDOR_WR(x, v) (HW_GPIO_PDOR(x).U = (v))
bogdanm 82:6473597d706e 111 #define HW_GPIO_PDOR_SET(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) | (v)))
bogdanm 82:6473597d706e 112 #define HW_GPIO_PDOR_CLR(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) & ~(v)))
bogdanm 82:6473597d706e 113 #define HW_GPIO_PDOR_TOG(x, v) (HW_GPIO_PDOR_WR(x, HW_GPIO_PDOR_RD(x) ^ (v)))
bogdanm 82:6473597d706e 114 #endif
bogdanm 82:6473597d706e 115 //@}
bogdanm 82:6473597d706e 116
bogdanm 82:6473597d706e 117 /*
bogdanm 82:6473597d706e 118 * Constants & macros for individual GPIO_PDOR bitfields
bogdanm 82:6473597d706e 119 */
bogdanm 82:6473597d706e 120
bogdanm 82:6473597d706e 121 /*!
bogdanm 82:6473597d706e 122 * @name Register GPIO_PDOR, field PDO[31:0] (RW)
bogdanm 82:6473597d706e 123 *
bogdanm 82:6473597d706e 124 * Register bits for unbonded pins return a undefined value when read.
bogdanm 82:6473597d706e 125 *
bogdanm 82:6473597d706e 126 * Values:
bogdanm 82:6473597d706e 127 * - 0 - Logic level 0 is driven on pin, provided pin is configured for
bogdanm 82:6473597d706e 128 * general-purpose output.
bogdanm 82:6473597d706e 129 * - 1 - Logic level 1 is driven on pin, provided pin is configured for
bogdanm 82:6473597d706e 130 * general-purpose output.
bogdanm 82:6473597d706e 131 */
bogdanm 82:6473597d706e 132 //@{
bogdanm 82:6473597d706e 133 #define BP_GPIO_PDOR_PDO (0U) //!< Bit position for GPIO_PDOR_PDO.
bogdanm 82:6473597d706e 134 #define BM_GPIO_PDOR_PDO (0xFFFFFFFFU) //!< Bit mask for GPIO_PDOR_PDO.
bogdanm 82:6473597d706e 135 #define BS_GPIO_PDOR_PDO (32U) //!< Bit field size in bits for GPIO_PDOR_PDO.
bogdanm 82:6473597d706e 136
bogdanm 82:6473597d706e 137 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 138 //! @brief Read current value of the GPIO_PDOR_PDO field.
bogdanm 82:6473597d706e 139 #define BR_GPIO_PDOR_PDO(x) (HW_GPIO_PDOR(x).U)
bogdanm 82:6473597d706e 140 #endif
bogdanm 82:6473597d706e 141
bogdanm 82:6473597d706e 142 //! @brief Format value for bitfield GPIO_PDOR_PDO.
bogdanm 82:6473597d706e 143 #define BF_GPIO_PDOR_PDO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDOR_PDO), uint32_t) & BM_GPIO_PDOR_PDO)
bogdanm 82:6473597d706e 144
bogdanm 82:6473597d706e 145 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 146 //! @brief Set the PDO field to a new value.
bogdanm 82:6473597d706e 147 #define BW_GPIO_PDOR_PDO(x, v) (HW_GPIO_PDOR_WR(x, v))
bogdanm 82:6473597d706e 148 #endif
bogdanm 82:6473597d706e 149 //@}
bogdanm 82:6473597d706e 150
bogdanm 82:6473597d706e 151 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 152 // HW_GPIO_PSOR - Port Set Output Register
bogdanm 82:6473597d706e 153 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 154
bogdanm 82:6473597d706e 155 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 156 /*!
bogdanm 82:6473597d706e 157 * @brief HW_GPIO_PSOR - Port Set Output Register (WORZ)
bogdanm 82:6473597d706e 158 *
bogdanm 82:6473597d706e 159 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 160 *
bogdanm 82:6473597d706e 161 * This register configures whether to set the fields of the PDOR.
bogdanm 82:6473597d706e 162 */
bogdanm 82:6473597d706e 163 typedef union _hw_gpio_psor
bogdanm 82:6473597d706e 164 {
bogdanm 82:6473597d706e 165 uint32_t U;
bogdanm 82:6473597d706e 166 struct _hw_gpio_psor_bitfields
bogdanm 82:6473597d706e 167 {
bogdanm 82:6473597d706e 168 uint32_t PTSO : 32; //!< [31:0] Port Set Output
bogdanm 82:6473597d706e 169 } B;
bogdanm 82:6473597d706e 170 } hw_gpio_psor_t;
bogdanm 82:6473597d706e 171 #endif
bogdanm 82:6473597d706e 172
bogdanm 82:6473597d706e 173 /*!
bogdanm 82:6473597d706e 174 * @name Constants and macros for entire GPIO_PSOR register
bogdanm 82:6473597d706e 175 */
bogdanm 82:6473597d706e 176 //@{
bogdanm 82:6473597d706e 177 #define HW_GPIO_PSOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x4U)
bogdanm 82:6473597d706e 178
bogdanm 82:6473597d706e 179 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 180 #define HW_GPIO_PSOR(x) (*(__O hw_gpio_psor_t *) HW_GPIO_PSOR_ADDR(x))
bogdanm 82:6473597d706e 181 #define HW_GPIO_PSOR_RD(x) (HW_GPIO_PSOR(x).U)
bogdanm 82:6473597d706e 182 #define HW_GPIO_PSOR_WR(x, v) (HW_GPIO_PSOR(x).U = (v))
bogdanm 82:6473597d706e 183 #endif
bogdanm 82:6473597d706e 184 //@}
bogdanm 82:6473597d706e 185
bogdanm 82:6473597d706e 186 /*
bogdanm 82:6473597d706e 187 * Constants & macros for individual GPIO_PSOR bitfields
bogdanm 82:6473597d706e 188 */
bogdanm 82:6473597d706e 189
bogdanm 82:6473597d706e 190 /*!
bogdanm 82:6473597d706e 191 * @name Register GPIO_PSOR, field PTSO[31:0] (WORZ)
bogdanm 82:6473597d706e 192 *
bogdanm 82:6473597d706e 193 * Writing to this register will update the contents of the corresponding bit in
bogdanm 82:6473597d706e 194 * the PDOR as follows:
bogdanm 82:6473597d706e 195 *
bogdanm 82:6473597d706e 196 * Values:
bogdanm 82:6473597d706e 197 * - 0 - Corresponding bit in PDORn does not change.
bogdanm 82:6473597d706e 198 * - 1 - Corresponding bit in PDORn is set to logic 1.
bogdanm 82:6473597d706e 199 */
bogdanm 82:6473597d706e 200 //@{
bogdanm 82:6473597d706e 201 #define BP_GPIO_PSOR_PTSO (0U) //!< Bit position for GPIO_PSOR_PTSO.
bogdanm 82:6473597d706e 202 #define BM_GPIO_PSOR_PTSO (0xFFFFFFFFU) //!< Bit mask for GPIO_PSOR_PTSO.
bogdanm 82:6473597d706e 203 #define BS_GPIO_PSOR_PTSO (32U) //!< Bit field size in bits for GPIO_PSOR_PTSO.
bogdanm 82:6473597d706e 204
bogdanm 82:6473597d706e 205 //! @brief Format value for bitfield GPIO_PSOR_PTSO.
bogdanm 82:6473597d706e 206 #define BF_GPIO_PSOR_PTSO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PSOR_PTSO), uint32_t) & BM_GPIO_PSOR_PTSO)
bogdanm 82:6473597d706e 207
bogdanm 82:6473597d706e 208 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 209 //! @brief Set the PTSO field to a new value.
bogdanm 82:6473597d706e 210 #define BW_GPIO_PSOR_PTSO(x, v) (HW_GPIO_PSOR_WR(x, v))
bogdanm 82:6473597d706e 211 #endif
bogdanm 82:6473597d706e 212 //@}
bogdanm 82:6473597d706e 213
bogdanm 82:6473597d706e 214 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 215 // HW_GPIO_PCOR - Port Clear Output Register
bogdanm 82:6473597d706e 216 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 217
bogdanm 82:6473597d706e 218 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 219 /*!
bogdanm 82:6473597d706e 220 * @brief HW_GPIO_PCOR - Port Clear Output Register (WORZ)
bogdanm 82:6473597d706e 221 *
bogdanm 82:6473597d706e 222 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 223 *
bogdanm 82:6473597d706e 224 * This register configures whether to clear the fields of PDOR.
bogdanm 82:6473597d706e 225 */
bogdanm 82:6473597d706e 226 typedef union _hw_gpio_pcor
bogdanm 82:6473597d706e 227 {
bogdanm 82:6473597d706e 228 uint32_t U;
bogdanm 82:6473597d706e 229 struct _hw_gpio_pcor_bitfields
bogdanm 82:6473597d706e 230 {
bogdanm 82:6473597d706e 231 uint32_t PTCO : 32; //!< [31:0] Port Clear Output
bogdanm 82:6473597d706e 232 } B;
bogdanm 82:6473597d706e 233 } hw_gpio_pcor_t;
bogdanm 82:6473597d706e 234 #endif
bogdanm 82:6473597d706e 235
bogdanm 82:6473597d706e 236 /*!
bogdanm 82:6473597d706e 237 * @name Constants and macros for entire GPIO_PCOR register
bogdanm 82:6473597d706e 238 */
bogdanm 82:6473597d706e 239 //@{
bogdanm 82:6473597d706e 240 #define HW_GPIO_PCOR_ADDR(x) (REGS_GPIO_BASE(x) + 0x8U)
bogdanm 82:6473597d706e 241
bogdanm 82:6473597d706e 242 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 243 #define HW_GPIO_PCOR(x) (*(__O hw_gpio_pcor_t *) HW_GPIO_PCOR_ADDR(x))
bogdanm 82:6473597d706e 244 #define HW_GPIO_PCOR_RD(x) (HW_GPIO_PCOR(x).U)
bogdanm 82:6473597d706e 245 #define HW_GPIO_PCOR_WR(x, v) (HW_GPIO_PCOR(x).U = (v))
bogdanm 82:6473597d706e 246 #endif
bogdanm 82:6473597d706e 247 //@}
bogdanm 82:6473597d706e 248
bogdanm 82:6473597d706e 249 /*
bogdanm 82:6473597d706e 250 * Constants & macros for individual GPIO_PCOR bitfields
bogdanm 82:6473597d706e 251 */
bogdanm 82:6473597d706e 252
bogdanm 82:6473597d706e 253 /*!
bogdanm 82:6473597d706e 254 * @name Register GPIO_PCOR, field PTCO[31:0] (WORZ)
bogdanm 82:6473597d706e 255 *
bogdanm 82:6473597d706e 256 * Writing to this register will update the contents of the corresponding bit in
bogdanm 82:6473597d706e 257 * the Port Data Output Register (PDOR) as follows:
bogdanm 82:6473597d706e 258 *
bogdanm 82:6473597d706e 259 * Values:
bogdanm 82:6473597d706e 260 * - 0 - Corresponding bit in PDORn does not change.
bogdanm 82:6473597d706e 261 * - 1 - Corresponding bit in PDORn is cleared to logic 0.
bogdanm 82:6473597d706e 262 */
bogdanm 82:6473597d706e 263 //@{
bogdanm 82:6473597d706e 264 #define BP_GPIO_PCOR_PTCO (0U) //!< Bit position for GPIO_PCOR_PTCO.
bogdanm 82:6473597d706e 265 #define BM_GPIO_PCOR_PTCO (0xFFFFFFFFU) //!< Bit mask for GPIO_PCOR_PTCO.
bogdanm 82:6473597d706e 266 #define BS_GPIO_PCOR_PTCO (32U) //!< Bit field size in bits for GPIO_PCOR_PTCO.
bogdanm 82:6473597d706e 267
bogdanm 82:6473597d706e 268 //! @brief Format value for bitfield GPIO_PCOR_PTCO.
bogdanm 82:6473597d706e 269 #define BF_GPIO_PCOR_PTCO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PCOR_PTCO), uint32_t) & BM_GPIO_PCOR_PTCO)
bogdanm 82:6473597d706e 270
bogdanm 82:6473597d706e 271 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 272 //! @brief Set the PTCO field to a new value.
bogdanm 82:6473597d706e 273 #define BW_GPIO_PCOR_PTCO(x, v) (HW_GPIO_PCOR_WR(x, v))
bogdanm 82:6473597d706e 274 #endif
bogdanm 82:6473597d706e 275 //@}
bogdanm 82:6473597d706e 276
bogdanm 82:6473597d706e 277 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 278 // HW_GPIO_PTOR - Port Toggle Output Register
bogdanm 82:6473597d706e 279 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 280
bogdanm 82:6473597d706e 281 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 282 /*!
bogdanm 82:6473597d706e 283 * @brief HW_GPIO_PTOR - Port Toggle Output Register (WORZ)
bogdanm 82:6473597d706e 284 *
bogdanm 82:6473597d706e 285 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 286 */
bogdanm 82:6473597d706e 287 typedef union _hw_gpio_ptor
bogdanm 82:6473597d706e 288 {
bogdanm 82:6473597d706e 289 uint32_t U;
bogdanm 82:6473597d706e 290 struct _hw_gpio_ptor_bitfields
bogdanm 82:6473597d706e 291 {
bogdanm 82:6473597d706e 292 uint32_t PTTO : 32; //!< [31:0] Port Toggle Output
bogdanm 82:6473597d706e 293 } B;
bogdanm 82:6473597d706e 294 } hw_gpio_ptor_t;
bogdanm 82:6473597d706e 295 #endif
bogdanm 82:6473597d706e 296
bogdanm 82:6473597d706e 297 /*!
bogdanm 82:6473597d706e 298 * @name Constants and macros for entire GPIO_PTOR register
bogdanm 82:6473597d706e 299 */
bogdanm 82:6473597d706e 300 //@{
bogdanm 82:6473597d706e 301 #define HW_GPIO_PTOR_ADDR(x) (REGS_GPIO_BASE(x) + 0xCU)
bogdanm 82:6473597d706e 302
bogdanm 82:6473597d706e 303 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 304 #define HW_GPIO_PTOR(x) (*(__O hw_gpio_ptor_t *) HW_GPIO_PTOR_ADDR(x))
bogdanm 82:6473597d706e 305 #define HW_GPIO_PTOR_RD(x) (HW_GPIO_PTOR(x).U)
bogdanm 82:6473597d706e 306 #define HW_GPIO_PTOR_WR(x, v) (HW_GPIO_PTOR(x).U = (v))
bogdanm 82:6473597d706e 307 #endif
bogdanm 82:6473597d706e 308 //@}
bogdanm 82:6473597d706e 309
bogdanm 82:6473597d706e 310 /*
bogdanm 82:6473597d706e 311 * Constants & macros for individual GPIO_PTOR bitfields
bogdanm 82:6473597d706e 312 */
bogdanm 82:6473597d706e 313
bogdanm 82:6473597d706e 314 /*!
bogdanm 82:6473597d706e 315 * @name Register GPIO_PTOR, field PTTO[31:0] (WORZ)
bogdanm 82:6473597d706e 316 *
bogdanm 82:6473597d706e 317 * Writing to this register will update the contents of the corresponding bit in
bogdanm 82:6473597d706e 318 * the PDOR as follows:
bogdanm 82:6473597d706e 319 *
bogdanm 82:6473597d706e 320 * Values:
bogdanm 82:6473597d706e 321 * - 0 - Corresponding bit in PDORn does not change.
bogdanm 82:6473597d706e 322 * - 1 - Corresponding bit in PDORn is set to the inverse of its existing logic
bogdanm 82:6473597d706e 323 * state.
bogdanm 82:6473597d706e 324 */
bogdanm 82:6473597d706e 325 //@{
bogdanm 82:6473597d706e 326 #define BP_GPIO_PTOR_PTTO (0U) //!< Bit position for GPIO_PTOR_PTTO.
bogdanm 82:6473597d706e 327 #define BM_GPIO_PTOR_PTTO (0xFFFFFFFFU) //!< Bit mask for GPIO_PTOR_PTTO.
bogdanm 82:6473597d706e 328 #define BS_GPIO_PTOR_PTTO (32U) //!< Bit field size in bits for GPIO_PTOR_PTTO.
bogdanm 82:6473597d706e 329
bogdanm 82:6473597d706e 330 //! @brief Format value for bitfield GPIO_PTOR_PTTO.
bogdanm 82:6473597d706e 331 #define BF_GPIO_PTOR_PTTO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PTOR_PTTO), uint32_t) & BM_GPIO_PTOR_PTTO)
bogdanm 82:6473597d706e 332
bogdanm 82:6473597d706e 333 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 334 //! @brief Set the PTTO field to a new value.
bogdanm 82:6473597d706e 335 #define BW_GPIO_PTOR_PTTO(x, v) (HW_GPIO_PTOR_WR(x, v))
bogdanm 82:6473597d706e 336 #endif
bogdanm 82:6473597d706e 337 //@}
bogdanm 82:6473597d706e 338
bogdanm 82:6473597d706e 339 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 340 // HW_GPIO_PDIR - Port Data Input Register
bogdanm 82:6473597d706e 341 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 342
bogdanm 82:6473597d706e 343 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 344 /*!
bogdanm 82:6473597d706e 345 * @brief HW_GPIO_PDIR - Port Data Input Register (RO)
bogdanm 82:6473597d706e 346 *
bogdanm 82:6473597d706e 347 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 348 *
bogdanm 82:6473597d706e 349 * Do not modify pin configuration registers associated with pins not available
bogdanm 82:6473597d706e 350 * in your selected package. All unbonded pins not available in your package will
bogdanm 82:6473597d706e 351 * default to DISABLE state for lowest power consumption.
bogdanm 82:6473597d706e 352 */
bogdanm 82:6473597d706e 353 typedef union _hw_gpio_pdir
bogdanm 82:6473597d706e 354 {
bogdanm 82:6473597d706e 355 uint32_t U;
bogdanm 82:6473597d706e 356 struct _hw_gpio_pdir_bitfields
bogdanm 82:6473597d706e 357 {
bogdanm 82:6473597d706e 358 uint32_t PDI : 32; //!< [31:0] Port Data Input
bogdanm 82:6473597d706e 359 } B;
bogdanm 82:6473597d706e 360 } hw_gpio_pdir_t;
bogdanm 82:6473597d706e 361 #endif
bogdanm 82:6473597d706e 362
bogdanm 82:6473597d706e 363 /*!
bogdanm 82:6473597d706e 364 * @name Constants and macros for entire GPIO_PDIR register
bogdanm 82:6473597d706e 365 */
bogdanm 82:6473597d706e 366 //@{
bogdanm 82:6473597d706e 367 #define HW_GPIO_PDIR_ADDR(x) (REGS_GPIO_BASE(x) + 0x10U)
bogdanm 82:6473597d706e 368
bogdanm 82:6473597d706e 369 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 370 #define HW_GPIO_PDIR(x) (*(__I hw_gpio_pdir_t *) HW_GPIO_PDIR_ADDR(x))
bogdanm 82:6473597d706e 371 #define HW_GPIO_PDIR_RD(x) (HW_GPIO_PDIR(x).U)
bogdanm 82:6473597d706e 372 #endif
bogdanm 82:6473597d706e 373 //@}
bogdanm 82:6473597d706e 374
bogdanm 82:6473597d706e 375 /*
bogdanm 82:6473597d706e 376 * Constants & macros for individual GPIO_PDIR bitfields
bogdanm 82:6473597d706e 377 */
bogdanm 82:6473597d706e 378
bogdanm 82:6473597d706e 379 /*!
bogdanm 82:6473597d706e 380 * @name Register GPIO_PDIR, field PDI[31:0] (RO)
bogdanm 82:6473597d706e 381 *
bogdanm 82:6473597d706e 382 * Reads 0 at the unimplemented pins for a particular device. Pins that are not
bogdanm 82:6473597d706e 383 * configured for a digital function read 0. If the Port Control and Interrupt
bogdanm 82:6473597d706e 384 * module is disabled, then the corresponding bit in PDIR does not update.
bogdanm 82:6473597d706e 385 *
bogdanm 82:6473597d706e 386 * Values:
bogdanm 82:6473597d706e 387 * - 0 - Pin logic level is logic 0, or is not configured for use by digital
bogdanm 82:6473597d706e 388 * function.
bogdanm 82:6473597d706e 389 * - 1 - Pin logic level is logic 1.
bogdanm 82:6473597d706e 390 */
bogdanm 82:6473597d706e 391 //@{
bogdanm 82:6473597d706e 392 #define BP_GPIO_PDIR_PDI (0U) //!< Bit position for GPIO_PDIR_PDI.
bogdanm 82:6473597d706e 393 #define BM_GPIO_PDIR_PDI (0xFFFFFFFFU) //!< Bit mask for GPIO_PDIR_PDI.
bogdanm 82:6473597d706e 394 #define BS_GPIO_PDIR_PDI (32U) //!< Bit field size in bits for GPIO_PDIR_PDI.
bogdanm 82:6473597d706e 395
bogdanm 82:6473597d706e 396 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 397 //! @brief Read current value of the GPIO_PDIR_PDI field.
bogdanm 82:6473597d706e 398 #define BR_GPIO_PDIR_PDI(x) (HW_GPIO_PDIR(x).U)
bogdanm 82:6473597d706e 399 #endif
bogdanm 82:6473597d706e 400 //@}
bogdanm 82:6473597d706e 401
bogdanm 82:6473597d706e 402 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 403 // HW_GPIO_PDDR - Port Data Direction Register
bogdanm 82:6473597d706e 404 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 405
bogdanm 82:6473597d706e 406 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 407 /*!
bogdanm 82:6473597d706e 408 * @brief HW_GPIO_PDDR - Port Data Direction Register (RW)
bogdanm 82:6473597d706e 409 *
bogdanm 82:6473597d706e 410 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 411 *
bogdanm 82:6473597d706e 412 * The PDDR configures the individual port pins for input or output.
bogdanm 82:6473597d706e 413 */
bogdanm 82:6473597d706e 414 typedef union _hw_gpio_pddr
bogdanm 82:6473597d706e 415 {
bogdanm 82:6473597d706e 416 uint32_t U;
bogdanm 82:6473597d706e 417 struct _hw_gpio_pddr_bitfields
bogdanm 82:6473597d706e 418 {
bogdanm 82:6473597d706e 419 uint32_t PDD : 32; //!< [31:0] Port Data Direction
bogdanm 82:6473597d706e 420 } B;
bogdanm 82:6473597d706e 421 } hw_gpio_pddr_t;
bogdanm 82:6473597d706e 422 #endif
bogdanm 82:6473597d706e 423
bogdanm 82:6473597d706e 424 /*!
bogdanm 82:6473597d706e 425 * @name Constants and macros for entire GPIO_PDDR register
bogdanm 82:6473597d706e 426 */
bogdanm 82:6473597d706e 427 //@{
bogdanm 82:6473597d706e 428 #define HW_GPIO_PDDR_ADDR(x) (REGS_GPIO_BASE(x) + 0x14U)
bogdanm 82:6473597d706e 429
bogdanm 82:6473597d706e 430 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 431 #define HW_GPIO_PDDR(x) (*(__IO hw_gpio_pddr_t *) HW_GPIO_PDDR_ADDR(x))
bogdanm 82:6473597d706e 432 #define HW_GPIO_PDDR_RD(x) (HW_GPIO_PDDR(x).U)
bogdanm 82:6473597d706e 433 #define HW_GPIO_PDDR_WR(x, v) (HW_GPIO_PDDR(x).U = (v))
bogdanm 82:6473597d706e 434 #define HW_GPIO_PDDR_SET(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) | (v)))
bogdanm 82:6473597d706e 435 #define HW_GPIO_PDDR_CLR(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) & ~(v)))
bogdanm 82:6473597d706e 436 #define HW_GPIO_PDDR_TOG(x, v) (HW_GPIO_PDDR_WR(x, HW_GPIO_PDDR_RD(x) ^ (v)))
bogdanm 82:6473597d706e 437 #endif
bogdanm 82:6473597d706e 438 //@}
bogdanm 82:6473597d706e 439
bogdanm 82:6473597d706e 440 /*
bogdanm 82:6473597d706e 441 * Constants & macros for individual GPIO_PDDR bitfields
bogdanm 82:6473597d706e 442 */
bogdanm 82:6473597d706e 443
bogdanm 82:6473597d706e 444 /*!
bogdanm 82:6473597d706e 445 * @name Register GPIO_PDDR, field PDD[31:0] (RW)
bogdanm 82:6473597d706e 446 *
bogdanm 82:6473597d706e 447 * Configures individual port pins for input or output.
bogdanm 82:6473597d706e 448 *
bogdanm 82:6473597d706e 449 * Values:
bogdanm 82:6473597d706e 450 * - 0 - Pin is configured as general-purpose input, for the GPIO function.
bogdanm 82:6473597d706e 451 * - 1 - Pin is configured as general-purpose output, for the GPIO function.
bogdanm 82:6473597d706e 452 */
bogdanm 82:6473597d706e 453 //@{
bogdanm 82:6473597d706e 454 #define BP_GPIO_PDDR_PDD (0U) //!< Bit position for GPIO_PDDR_PDD.
bogdanm 82:6473597d706e 455 #define BM_GPIO_PDDR_PDD (0xFFFFFFFFU) //!< Bit mask for GPIO_PDDR_PDD.
bogdanm 82:6473597d706e 456 #define BS_GPIO_PDDR_PDD (32U) //!< Bit field size in bits for GPIO_PDDR_PDD.
bogdanm 82:6473597d706e 457
bogdanm 82:6473597d706e 458 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 459 //! @brief Read current value of the GPIO_PDDR_PDD field.
bogdanm 82:6473597d706e 460 #define BR_GPIO_PDDR_PDD(x) (HW_GPIO_PDDR(x).U)
bogdanm 82:6473597d706e 461 #endif
bogdanm 82:6473597d706e 462
bogdanm 82:6473597d706e 463 //! @brief Format value for bitfield GPIO_PDDR_PDD.
bogdanm 82:6473597d706e 464 #define BF_GPIO_PDDR_PDD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_GPIO_PDDR_PDD), uint32_t) & BM_GPIO_PDDR_PDD)
bogdanm 82:6473597d706e 465
bogdanm 82:6473597d706e 466 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 467 //! @brief Set the PDD field to a new value.
bogdanm 82:6473597d706e 468 #define BW_GPIO_PDDR_PDD(x, v) (HW_GPIO_PDDR_WR(x, v))
bogdanm 82:6473597d706e 469 #endif
bogdanm 82:6473597d706e 470 //@}
bogdanm 82:6473597d706e 471
bogdanm 82:6473597d706e 472 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 473 // hw_gpio_t - module struct
bogdanm 82:6473597d706e 474 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 475 /*!
bogdanm 82:6473597d706e 476 * @brief All GPIO module registers.
bogdanm 82:6473597d706e 477 */
bogdanm 82:6473597d706e 478 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 479 #pragma pack(1)
bogdanm 82:6473597d706e 480 typedef struct _hw_gpio
bogdanm 82:6473597d706e 481 {
bogdanm 82:6473597d706e 482 __IO hw_gpio_pdor_t PDOR; //!< [0x0] Port Data Output Register
bogdanm 82:6473597d706e 483 __O hw_gpio_psor_t PSOR; //!< [0x4] Port Set Output Register
bogdanm 82:6473597d706e 484 __O hw_gpio_pcor_t PCOR; //!< [0x8] Port Clear Output Register
bogdanm 82:6473597d706e 485 __O hw_gpio_ptor_t PTOR; //!< [0xC] Port Toggle Output Register
bogdanm 82:6473597d706e 486 __I hw_gpio_pdir_t PDIR; //!< [0x10] Port Data Input Register
bogdanm 82:6473597d706e 487 __IO hw_gpio_pddr_t PDDR; //!< [0x14] Port Data Direction Register
bogdanm 82:6473597d706e 488 } hw_gpio_t;
bogdanm 82:6473597d706e 489 #pragma pack()
bogdanm 82:6473597d706e 490
bogdanm 82:6473597d706e 491 //! @brief Macro to access all GPIO registers.
bogdanm 82:6473597d706e 492 //! @param x GPIO instance number.
bogdanm 82:6473597d706e 493 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 494 //! use the '&' operator, like <code>&HW_GPIO(0)</code>.
bogdanm 82:6473597d706e 495 #define HW_GPIO(x) (*(hw_gpio_t *) REGS_GPIO_BASE(x))
bogdanm 82:6473597d706e 496 #endif
bogdanm 82:6473597d706e 497
bogdanm 82:6473597d706e 498 #endif // __HW_GPIO_REGISTERS_H__
bogdanm 82:6473597d706e 499 // v22/130726/0.9
bogdanm 82:6473597d706e 500 // EOF