Ricardo Benitez / mbed

meh

Fork of mbed by mbed official

TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_fb.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:
bogdanm
Date:
Fri Sep 12 16:41:52 2014 +0100
Revision:
89:552587b429a1
Parent:
TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_fb.h@82:6473597d706e 
Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 82:6473597d706e 1 /*
bogdanm 82:6473597d706e 2 * Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm 82:6473597d706e 3 * All rights reserved.
bogdanm 82:6473597d706e 4 *
bogdanm 82:6473597d706e 5 * THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm 82:6473597d706e 6 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm 82:6473597d706e 7 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm 82:6473597d706e 8 * SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm 82:6473597d706e 9 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm 82:6473597d706e 10 * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 82:6473597d706e 11 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 82:6473597d706e 12 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm 82:6473597d706e 13 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm 82:6473597d706e 14 * OF SUCH DAMAGE.
bogdanm 82:6473597d706e 15 */
bogdanm 82:6473597d706e 16 /*
bogdanm 82:6473597d706e 17 * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm 82:6473597d706e 18 *
bogdanm 82:6473597d706e 19 * This file was generated automatically and any changes may be lost.
bogdanm 82:6473597d706e 20 */
bogdanm 82:6473597d706e 21 #ifndef __HW_FB_REGISTERS_H__
bogdanm 82:6473597d706e 22 #define __HW_FB_REGISTERS_H__
bogdanm 82:6473597d706e 23
bogdanm 82:6473597d706e 24 #include "regs.h"
bogdanm 82:6473597d706e 25
bogdanm 82:6473597d706e 26 /*
bogdanm 82:6473597d706e 27 * MK64F12 FB
bogdanm 82:6473597d706e 28 *
bogdanm 82:6473597d706e 29 * FlexBus external bus interface
bogdanm 82:6473597d706e 30 *
bogdanm 82:6473597d706e 31 * Registers defined in this header file:
bogdanm 82:6473597d706e 32 * - HW_FB_CSARn - Chip Select Address Register
bogdanm 82:6473597d706e 33 * - HW_FB_CSMRn - Chip Select Mask Register
bogdanm 82:6473597d706e 34 * - HW_FB_CSCRn - Chip Select Control Register
bogdanm 82:6473597d706e 35 * - HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
bogdanm 82:6473597d706e 36 *
bogdanm 82:6473597d706e 37 * - hw_fb_t - Struct containing all module registers.
bogdanm 82:6473597d706e 38 */
bogdanm 82:6473597d706e 39
bogdanm 82:6473597d706e 40 //! @name Module base addresses
bogdanm 82:6473597d706e 41 //@{
bogdanm 82:6473597d706e 42 #ifndef REGS_FB_BASE
bogdanm 82:6473597d706e 43 #define HW_FB_INSTANCE_COUNT (1U) //!< Number of instances of the FB module.
bogdanm 82:6473597d706e 44 #define REGS_FB_BASE (0x4000C000U) //!< Base address for FB.
bogdanm 82:6473597d706e 45 #endif
bogdanm 82:6473597d706e 46 //@}
bogdanm 82:6473597d706e 47
bogdanm 82:6473597d706e 48 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 49 // HW_FB_CSARn - Chip Select Address Register
bogdanm 82:6473597d706e 50 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 51
bogdanm 82:6473597d706e 52 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 53 /*!
bogdanm 82:6473597d706e 54 * @brief HW_FB_CSARn - Chip Select Address Register (RW)
bogdanm 82:6473597d706e 55 *
bogdanm 82:6473597d706e 56 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 57 *
bogdanm 82:6473597d706e 58 * Specifies the associated chip-select's base address.
bogdanm 82:6473597d706e 59 */
bogdanm 82:6473597d706e 60 typedef union _hw_fb_csarn
bogdanm 82:6473597d706e 61 {
bogdanm 82:6473597d706e 62 uint32_t U;
bogdanm 82:6473597d706e 63 struct _hw_fb_csarn_bitfields
bogdanm 82:6473597d706e 64 {
bogdanm 82:6473597d706e 65 uint32_t RESERVED0 : 16; //!< [15:0]
bogdanm 82:6473597d706e 66 uint32_t BA : 16; //!< [31:16] Base Address
bogdanm 82:6473597d706e 67 } B;
bogdanm 82:6473597d706e 68 } hw_fb_csarn_t;
bogdanm 82:6473597d706e 69 #endif
bogdanm 82:6473597d706e 70
bogdanm 82:6473597d706e 71 /*!
bogdanm 82:6473597d706e 72 * @name Constants and macros for entire FB_CSARn register
bogdanm 82:6473597d706e 73 */
bogdanm 82:6473597d706e 74 //@{
bogdanm 82:6473597d706e 75 #define HW_FB_CSARn_COUNT (6U)
bogdanm 82:6473597d706e 76
bogdanm 82:6473597d706e 77 #define HW_FB_CSARn_ADDR(n) (REGS_FB_BASE + 0x0U + (0xCU * n))
bogdanm 82:6473597d706e 78
bogdanm 82:6473597d706e 79 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 80 #define HW_FB_CSARn(n) (*(__IO hw_fb_csarn_t *) HW_FB_CSARn_ADDR(n))
bogdanm 82:6473597d706e 81 #define HW_FB_CSARn_RD(n) (HW_FB_CSARn(n).U)
bogdanm 82:6473597d706e 82 #define HW_FB_CSARn_WR(n, v) (HW_FB_CSARn(n).U = (v))
bogdanm 82:6473597d706e 83 #define HW_FB_CSARn_SET(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) | (v)))
bogdanm 82:6473597d706e 84 #define HW_FB_CSARn_CLR(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) & ~(v)))
bogdanm 82:6473597d706e 85 #define HW_FB_CSARn_TOG(n, v) (HW_FB_CSARn_WR(n, HW_FB_CSARn_RD(n) ^ (v)))
bogdanm 82:6473597d706e 86 #endif
bogdanm 82:6473597d706e 87 //@}
bogdanm 82:6473597d706e 88
bogdanm 82:6473597d706e 89 /*
bogdanm 82:6473597d706e 90 * Constants & macros for individual FB_CSARn bitfields
bogdanm 82:6473597d706e 91 */
bogdanm 82:6473597d706e 92
bogdanm 82:6473597d706e 93 /*!
bogdanm 82:6473597d706e 94 * @name Register FB_CSARn, field BA[31:16] (RW)
bogdanm 82:6473597d706e 95 *
bogdanm 82:6473597d706e 96 * Defines the base address for memory dedicated to the associated chip-select.
bogdanm 82:6473597d706e 97 * BA is compared to bits 31-16 on the internal address bus to determine if the
bogdanm 82:6473597d706e 98 * associated chip-select's memory is being accessed. Because the FlexBus module
bogdanm 82:6473597d706e 99 * is one of the slaves connected to the crossbar switch, it is only accessible
bogdanm 82:6473597d706e 100 * within a certain memory range. See the chip memory map for the applicable
bogdanm 82:6473597d706e 101 * FlexBus "expansion" address range for which the chip-selects can be active. Set the
bogdanm 82:6473597d706e 102 * CSARn and CSMRn registers appropriately before accessing this region.
bogdanm 82:6473597d706e 103 */
bogdanm 82:6473597d706e 104 //@{
bogdanm 82:6473597d706e 105 #define BP_FB_CSARn_BA (16U) //!< Bit position for FB_CSARn_BA.
bogdanm 82:6473597d706e 106 #define BM_FB_CSARn_BA (0xFFFF0000U) //!< Bit mask for FB_CSARn_BA.
bogdanm 82:6473597d706e 107 #define BS_FB_CSARn_BA (16U) //!< Bit field size in bits for FB_CSARn_BA.
bogdanm 82:6473597d706e 108
bogdanm 82:6473597d706e 109 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 110 //! @brief Read current value of the FB_CSARn_BA field.
bogdanm 82:6473597d706e 111 #define BR_FB_CSARn_BA(n) (HW_FB_CSARn(n).B.BA)
bogdanm 82:6473597d706e 112 #endif
bogdanm 82:6473597d706e 113
bogdanm 82:6473597d706e 114 //! @brief Format value for bitfield FB_CSARn_BA.
bogdanm 82:6473597d706e 115 #define BF_FB_CSARn_BA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSARn_BA), uint32_t) & BM_FB_CSARn_BA)
bogdanm 82:6473597d706e 116
bogdanm 82:6473597d706e 117 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 118 //! @brief Set the BA field to a new value.
bogdanm 82:6473597d706e 119 #define BW_FB_CSARn_BA(n, v) (HW_FB_CSARn_WR(n, (HW_FB_CSARn_RD(n) & ~BM_FB_CSARn_BA) | BF_FB_CSARn_BA(v)))
bogdanm 82:6473597d706e 120 #endif
bogdanm 82:6473597d706e 121 //@}
bogdanm 82:6473597d706e 122 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 123 // HW_FB_CSMRn - Chip Select Mask Register
bogdanm 82:6473597d706e 124 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 125
bogdanm 82:6473597d706e 126 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 127 /*!
bogdanm 82:6473597d706e 128 * @brief HW_FB_CSMRn - Chip Select Mask Register (RW)
bogdanm 82:6473597d706e 129 *
bogdanm 82:6473597d706e 130 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 131 *
bogdanm 82:6473597d706e 132 * Specifies the address mask and allowable access types for the associated
bogdanm 82:6473597d706e 133 * chip-select.
bogdanm 82:6473597d706e 134 */
bogdanm 82:6473597d706e 135 typedef union _hw_fb_csmrn
bogdanm 82:6473597d706e 136 {
bogdanm 82:6473597d706e 137 uint32_t U;
bogdanm 82:6473597d706e 138 struct _hw_fb_csmrn_bitfields
bogdanm 82:6473597d706e 139 {
bogdanm 82:6473597d706e 140 uint32_t V : 1; //!< [0] Valid
bogdanm 82:6473597d706e 141 uint32_t RESERVED0 : 7; //!< [7:1]
bogdanm 82:6473597d706e 142 uint32_t WP : 1; //!< [8] Write Protect
bogdanm 82:6473597d706e 143 uint32_t RESERVED1 : 7; //!< [15:9]
bogdanm 82:6473597d706e 144 uint32_t BAM : 16; //!< [31:16] Base Address Mask
bogdanm 82:6473597d706e 145 } B;
bogdanm 82:6473597d706e 146 } hw_fb_csmrn_t;
bogdanm 82:6473597d706e 147 #endif
bogdanm 82:6473597d706e 148
bogdanm 82:6473597d706e 149 /*!
bogdanm 82:6473597d706e 150 * @name Constants and macros for entire FB_CSMRn register
bogdanm 82:6473597d706e 151 */
bogdanm 82:6473597d706e 152 //@{
bogdanm 82:6473597d706e 153 #define HW_FB_CSMRn_COUNT (6U)
bogdanm 82:6473597d706e 154
bogdanm 82:6473597d706e 155 #define HW_FB_CSMRn_ADDR(n) (REGS_FB_BASE + 0x4U + (0xCU * n))
bogdanm 82:6473597d706e 156
bogdanm 82:6473597d706e 157 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 158 #define HW_FB_CSMRn(n) (*(__IO hw_fb_csmrn_t *) HW_FB_CSMRn_ADDR(n))
bogdanm 82:6473597d706e 159 #define HW_FB_CSMRn_RD(n) (HW_FB_CSMRn(n).U)
bogdanm 82:6473597d706e 160 #define HW_FB_CSMRn_WR(n, v) (HW_FB_CSMRn(n).U = (v))
bogdanm 82:6473597d706e 161 #define HW_FB_CSMRn_SET(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) | (v)))
bogdanm 82:6473597d706e 162 #define HW_FB_CSMRn_CLR(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) & ~(v)))
bogdanm 82:6473597d706e 163 #define HW_FB_CSMRn_TOG(n, v) (HW_FB_CSMRn_WR(n, HW_FB_CSMRn_RD(n) ^ (v)))
bogdanm 82:6473597d706e 164 #endif
bogdanm 82:6473597d706e 165 //@}
bogdanm 82:6473597d706e 166
bogdanm 82:6473597d706e 167 /*
bogdanm 82:6473597d706e 168 * Constants & macros for individual FB_CSMRn bitfields
bogdanm 82:6473597d706e 169 */
bogdanm 82:6473597d706e 170
bogdanm 82:6473597d706e 171 /*!
bogdanm 82:6473597d706e 172 * @name Register FB_CSMRn, field V[0] (RW)
bogdanm 82:6473597d706e 173 *
bogdanm 82:6473597d706e 174 * Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid.
bogdanm 82:6473597d706e 175 * Programmed chip-selects do not assert until the V bit is 1b (except for
bogdanm 82:6473597d706e 176 * FB_CS0, which acts as the global chip-select). At reset, FB_CS0 will fire for any
bogdanm 82:6473597d706e 177 * access to the FlexBus memory region. CSMR0[V] must be set as part of the chip
bogdanm 82:6473597d706e 178 * select initialization sequence to allow other chip selects to function as
bogdanm 82:6473597d706e 179 * programmed.
bogdanm 82:6473597d706e 180 *
bogdanm 82:6473597d706e 181 * Values:
bogdanm 82:6473597d706e 182 * - 0 - Chip-select is invalid.
bogdanm 82:6473597d706e 183 * - 1 - Chip-select is valid.
bogdanm 82:6473597d706e 184 */
bogdanm 82:6473597d706e 185 //@{
bogdanm 82:6473597d706e 186 #define BP_FB_CSMRn_V (0U) //!< Bit position for FB_CSMRn_V.
bogdanm 82:6473597d706e 187 #define BM_FB_CSMRn_V (0x00000001U) //!< Bit mask for FB_CSMRn_V.
bogdanm 82:6473597d706e 188 #define BS_FB_CSMRn_V (1U) //!< Bit field size in bits for FB_CSMRn_V.
bogdanm 82:6473597d706e 189
bogdanm 82:6473597d706e 190 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 191 //! @brief Read current value of the FB_CSMRn_V field.
bogdanm 82:6473597d706e 192 #define BR_FB_CSMRn_V(n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V))
bogdanm 82:6473597d706e 193 #endif
bogdanm 82:6473597d706e 194
bogdanm 82:6473597d706e 195 //! @brief Format value for bitfield FB_CSMRn_V.
bogdanm 82:6473597d706e 196 #define BF_FB_CSMRn_V(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_V), uint32_t) & BM_FB_CSMRn_V)
bogdanm 82:6473597d706e 197
bogdanm 82:6473597d706e 198 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 199 //! @brief Set the V field to a new value.
bogdanm 82:6473597d706e 200 #define BW_FB_CSMRn_V(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_V) = (v))
bogdanm 82:6473597d706e 201 #endif
bogdanm 82:6473597d706e 202 //@}
bogdanm 82:6473597d706e 203
bogdanm 82:6473597d706e 204 /*!
bogdanm 82:6473597d706e 205 * @name Register FB_CSMRn, field WP[8] (RW)
bogdanm 82:6473597d706e 206 *
bogdanm 82:6473597d706e 207 * Controls write accesses to the address range in the corresponding CSAR.
bogdanm 82:6473597d706e 208 *
bogdanm 82:6473597d706e 209 * Values:
bogdanm 82:6473597d706e 210 * - 0 - Write accesses are allowed.
bogdanm 82:6473597d706e 211 * - 1 - Write accesses are not allowed. Attempting to write to the range of
bogdanm 82:6473597d706e 212 * addresses for which the WP bit is set results in a bus error termination of
bogdanm 82:6473597d706e 213 * the internal cycle and no external cycle.
bogdanm 82:6473597d706e 214 */
bogdanm 82:6473597d706e 215 //@{
bogdanm 82:6473597d706e 216 #define BP_FB_CSMRn_WP (8U) //!< Bit position for FB_CSMRn_WP.
bogdanm 82:6473597d706e 217 #define BM_FB_CSMRn_WP (0x00000100U) //!< Bit mask for FB_CSMRn_WP.
bogdanm 82:6473597d706e 218 #define BS_FB_CSMRn_WP (1U) //!< Bit field size in bits for FB_CSMRn_WP.
bogdanm 82:6473597d706e 219
bogdanm 82:6473597d706e 220 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 221 //! @brief Read current value of the FB_CSMRn_WP field.
bogdanm 82:6473597d706e 222 #define BR_FB_CSMRn_WP(n) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP))
bogdanm 82:6473597d706e 223 #endif
bogdanm 82:6473597d706e 224
bogdanm 82:6473597d706e 225 //! @brief Format value for bitfield FB_CSMRn_WP.
bogdanm 82:6473597d706e 226 #define BF_FB_CSMRn_WP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_WP), uint32_t) & BM_FB_CSMRn_WP)
bogdanm 82:6473597d706e 227
bogdanm 82:6473597d706e 228 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 229 //! @brief Set the WP field to a new value.
bogdanm 82:6473597d706e 230 #define BW_FB_CSMRn_WP(n, v) (BITBAND_ACCESS32(HW_FB_CSMRn_ADDR(n), BP_FB_CSMRn_WP) = (v))
bogdanm 82:6473597d706e 231 #endif
bogdanm 82:6473597d706e 232 //@}
bogdanm 82:6473597d706e 233
bogdanm 82:6473597d706e 234 /*!
bogdanm 82:6473597d706e 235 * @name Register FB_CSMRn, field BAM[31:16] (RW)
bogdanm 82:6473597d706e 236 *
bogdanm 82:6473597d706e 237 * Defines the associated chip-select's block size by masking address bits.
bogdanm 82:6473597d706e 238 *
bogdanm 82:6473597d706e 239 * Values:
bogdanm 82:6473597d706e 240 * - 0 - The corresponding address bit in CSAR is used in the chip-select decode.
bogdanm 82:6473597d706e 241 * - 1 - The corresponding address bit in CSAR is a don't care in the
bogdanm 82:6473597d706e 242 * chip-select decode.
bogdanm 82:6473597d706e 243 */
bogdanm 82:6473597d706e 244 //@{
bogdanm 82:6473597d706e 245 #define BP_FB_CSMRn_BAM (16U) //!< Bit position for FB_CSMRn_BAM.
bogdanm 82:6473597d706e 246 #define BM_FB_CSMRn_BAM (0xFFFF0000U) //!< Bit mask for FB_CSMRn_BAM.
bogdanm 82:6473597d706e 247 #define BS_FB_CSMRn_BAM (16U) //!< Bit field size in bits for FB_CSMRn_BAM.
bogdanm 82:6473597d706e 248
bogdanm 82:6473597d706e 249 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 250 //! @brief Read current value of the FB_CSMRn_BAM field.
bogdanm 82:6473597d706e 251 #define BR_FB_CSMRn_BAM(n) (HW_FB_CSMRn(n).B.BAM)
bogdanm 82:6473597d706e 252 #endif
bogdanm 82:6473597d706e 253
bogdanm 82:6473597d706e 254 //! @brief Format value for bitfield FB_CSMRn_BAM.
bogdanm 82:6473597d706e 255 #define BF_FB_CSMRn_BAM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSMRn_BAM), uint32_t) & BM_FB_CSMRn_BAM)
bogdanm 82:6473597d706e 256
bogdanm 82:6473597d706e 257 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 258 //! @brief Set the BAM field to a new value.
bogdanm 82:6473597d706e 259 #define BW_FB_CSMRn_BAM(n, v) (HW_FB_CSMRn_WR(n, (HW_FB_CSMRn_RD(n) & ~BM_FB_CSMRn_BAM) | BF_FB_CSMRn_BAM(v)))
bogdanm 82:6473597d706e 260 #endif
bogdanm 82:6473597d706e 261 //@}
bogdanm 82:6473597d706e 262 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 263 // HW_FB_CSCRn - Chip Select Control Register
bogdanm 82:6473597d706e 264 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 265
bogdanm 82:6473597d706e 266 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 267 /*!
bogdanm 82:6473597d706e 268 * @brief HW_FB_CSCRn - Chip Select Control Register (RW)
bogdanm 82:6473597d706e 269 *
bogdanm 82:6473597d706e 270 * Reset value: 0x003FFC00U
bogdanm 82:6473597d706e 271 *
bogdanm 82:6473597d706e 272 * Controls the auto-acknowledge, address setup and hold times, port size, burst
bogdanm 82:6473597d706e 273 * capability, and number of wait states for the associated chip select. To
bogdanm 82:6473597d706e 274 * support the global chip-select (FB_CS0), the CSCR0 reset values differ from the
bogdanm 82:6473597d706e 275 * other CSCRs. The reset value of CSCR0 is as follows: Bits 31-24 are 0b Bit 23-3
bogdanm 82:6473597d706e 276 * are chip-dependent Bits 3-0 are 0b See the chip configuration details for your
bogdanm 82:6473597d706e 277 * particular chip for information on the exact CSCR0 reset value.
bogdanm 82:6473597d706e 278 */
bogdanm 82:6473597d706e 279 typedef union _hw_fb_cscrn
bogdanm 82:6473597d706e 280 {
bogdanm 82:6473597d706e 281 uint32_t U;
bogdanm 82:6473597d706e 282 struct _hw_fb_cscrn_bitfields
bogdanm 82:6473597d706e 283 {
bogdanm 82:6473597d706e 284 uint32_t RESERVED0 : 3; //!< [2:0]
bogdanm 82:6473597d706e 285 uint32_t BSTW : 1; //!< [3] Burst-Write Enable
bogdanm 82:6473597d706e 286 uint32_t BSTR : 1; //!< [4] Burst-Read Enable
bogdanm 82:6473597d706e 287 uint32_t BEM : 1; //!< [5] Byte-Enable Mode
bogdanm 82:6473597d706e 288 uint32_t PS : 2; //!< [7:6] Port Size
bogdanm 82:6473597d706e 289 uint32_t AA : 1; //!< [8] Auto-Acknowledge Enable
bogdanm 82:6473597d706e 290 uint32_t BLS : 1; //!< [9] Byte-Lane Shift
bogdanm 82:6473597d706e 291 uint32_t WS : 6; //!< [15:10] Wait States
bogdanm 82:6473597d706e 292 uint32_t WRAH : 2; //!< [17:16] Write Address Hold or Deselect
bogdanm 82:6473597d706e 293 uint32_t RDAH : 2; //!< [19:18] Read Address Hold or Deselect
bogdanm 82:6473597d706e 294 uint32_t ASET : 2; //!< [21:20] Address Setup
bogdanm 82:6473597d706e 295 uint32_t EXTS : 1; //!< [22]
bogdanm 82:6473597d706e 296 uint32_t SWSEN : 1; //!< [23] Secondary Wait State Enable
bogdanm 82:6473597d706e 297 uint32_t RESERVED1 : 2; //!< [25:24]
bogdanm 82:6473597d706e 298 uint32_t SWS : 6; //!< [31:26] Secondary Wait States
bogdanm 82:6473597d706e 299 } B;
bogdanm 82:6473597d706e 300 } hw_fb_cscrn_t;
bogdanm 82:6473597d706e 301 #endif
bogdanm 82:6473597d706e 302
bogdanm 82:6473597d706e 303 /*!
bogdanm 82:6473597d706e 304 * @name Constants and macros for entire FB_CSCRn register
bogdanm 82:6473597d706e 305 */
bogdanm 82:6473597d706e 306 //@{
bogdanm 82:6473597d706e 307 #define HW_FB_CSCRn_COUNT (6U)
bogdanm 82:6473597d706e 308
bogdanm 82:6473597d706e 309 #define HW_FB_CSCRn_ADDR(n) (REGS_FB_BASE + 0x8U + (0xCU * n))
bogdanm 82:6473597d706e 310
bogdanm 82:6473597d706e 311 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 312 #define HW_FB_CSCRn(n) (*(__IO hw_fb_cscrn_t *) HW_FB_CSCRn_ADDR(n))
bogdanm 82:6473597d706e 313 #define HW_FB_CSCRn_RD(n) (HW_FB_CSCRn(n).U)
bogdanm 82:6473597d706e 314 #define HW_FB_CSCRn_WR(n, v) (HW_FB_CSCRn(n).U = (v))
bogdanm 82:6473597d706e 315 #define HW_FB_CSCRn_SET(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) | (v)))
bogdanm 82:6473597d706e 316 #define HW_FB_CSCRn_CLR(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) & ~(v)))
bogdanm 82:6473597d706e 317 #define HW_FB_CSCRn_TOG(n, v) (HW_FB_CSCRn_WR(n, HW_FB_CSCRn_RD(n) ^ (v)))
bogdanm 82:6473597d706e 318 #endif
bogdanm 82:6473597d706e 319 //@}
bogdanm 82:6473597d706e 320
bogdanm 82:6473597d706e 321 /*
bogdanm 82:6473597d706e 322 * Constants & macros for individual FB_CSCRn bitfields
bogdanm 82:6473597d706e 323 */
bogdanm 82:6473597d706e 324
bogdanm 82:6473597d706e 325 /*!
bogdanm 82:6473597d706e 326 * @name Register FB_CSCRn, field BSTW[3] (RW)
bogdanm 82:6473597d706e 327 *
bogdanm 82:6473597d706e 328 * Specifies whether burst writes are enabled for memory associated with each
bogdanm 82:6473597d706e 329 * chip select.
bogdanm 82:6473597d706e 330 *
bogdanm 82:6473597d706e 331 * Values:
bogdanm 82:6473597d706e 332 * - 0 - Disabled. Data exceeding the specified port size is broken into
bogdanm 82:6473597d706e 333 * individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit
bogdanm 82:6473597d706e 334 * port takes four byte writes.
bogdanm 82:6473597d706e 335 * - 1 - Enabled. Enables burst write of data larger than the specified port
bogdanm 82:6473597d706e 336 * size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit
bogdanm 82:6473597d706e 337 * ports, and line writes to 8-, 16-, and 32-bit ports.
bogdanm 82:6473597d706e 338 */
bogdanm 82:6473597d706e 339 //@{
bogdanm 82:6473597d706e 340 #define BP_FB_CSCRn_BSTW (3U) //!< Bit position for FB_CSCRn_BSTW.
bogdanm 82:6473597d706e 341 #define BM_FB_CSCRn_BSTW (0x00000008U) //!< Bit mask for FB_CSCRn_BSTW.
bogdanm 82:6473597d706e 342 #define BS_FB_CSCRn_BSTW (1U) //!< Bit field size in bits for FB_CSCRn_BSTW.
bogdanm 82:6473597d706e 343
bogdanm 82:6473597d706e 344 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 345 //! @brief Read current value of the FB_CSCRn_BSTW field.
bogdanm 82:6473597d706e 346 #define BR_FB_CSCRn_BSTW(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW))
bogdanm 82:6473597d706e 347 #endif
bogdanm 82:6473597d706e 348
bogdanm 82:6473597d706e 349 //! @brief Format value for bitfield FB_CSCRn_BSTW.
bogdanm 82:6473597d706e 350 #define BF_FB_CSCRn_BSTW(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTW), uint32_t) & BM_FB_CSCRn_BSTW)
bogdanm 82:6473597d706e 351
bogdanm 82:6473597d706e 352 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 353 //! @brief Set the BSTW field to a new value.
bogdanm 82:6473597d706e 354 #define BW_FB_CSCRn_BSTW(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTW) = (v))
bogdanm 82:6473597d706e 355 #endif
bogdanm 82:6473597d706e 356 //@}
bogdanm 82:6473597d706e 357
bogdanm 82:6473597d706e 358 /*!
bogdanm 82:6473597d706e 359 * @name Register FB_CSCRn, field BSTR[4] (RW)
bogdanm 82:6473597d706e 360 *
bogdanm 82:6473597d706e 361 * Specifies whether burst reads are enabled for memory associated with each
bogdanm 82:6473597d706e 362 * chip select.
bogdanm 82:6473597d706e 363 *
bogdanm 82:6473597d706e 364 * Values:
bogdanm 82:6473597d706e 365 * - 0 - Disabled. Data exceeding the specified port size is broken into
bogdanm 82:6473597d706e 366 * individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit
bogdanm 82:6473597d706e 367 * port is broken into four 8-bit reads.
bogdanm 82:6473597d706e 368 * - 1 - Enabled. Enables data burst reads larger than the specified port size,
bogdanm 82:6473597d706e 369 * including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit
bogdanm 82:6473597d706e 370 * ports, and line reads from 8-, 16-, and 32-bit ports.
bogdanm 82:6473597d706e 371 */
bogdanm 82:6473597d706e 372 //@{
bogdanm 82:6473597d706e 373 #define BP_FB_CSCRn_BSTR (4U) //!< Bit position for FB_CSCRn_BSTR.
bogdanm 82:6473597d706e 374 #define BM_FB_CSCRn_BSTR (0x00000010U) //!< Bit mask for FB_CSCRn_BSTR.
bogdanm 82:6473597d706e 375 #define BS_FB_CSCRn_BSTR (1U) //!< Bit field size in bits for FB_CSCRn_BSTR.
bogdanm 82:6473597d706e 376
bogdanm 82:6473597d706e 377 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 378 //! @brief Read current value of the FB_CSCRn_BSTR field.
bogdanm 82:6473597d706e 379 #define BR_FB_CSCRn_BSTR(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR))
bogdanm 82:6473597d706e 380 #endif
bogdanm 82:6473597d706e 381
bogdanm 82:6473597d706e 382 //! @brief Format value for bitfield FB_CSCRn_BSTR.
bogdanm 82:6473597d706e 383 #define BF_FB_CSCRn_BSTR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BSTR), uint32_t) & BM_FB_CSCRn_BSTR)
bogdanm 82:6473597d706e 384
bogdanm 82:6473597d706e 385 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 386 //! @brief Set the BSTR field to a new value.
bogdanm 82:6473597d706e 387 #define BW_FB_CSCRn_BSTR(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BSTR) = (v))
bogdanm 82:6473597d706e 388 #endif
bogdanm 82:6473597d706e 389 //@}
bogdanm 82:6473597d706e 390
bogdanm 82:6473597d706e 391 /*!
bogdanm 82:6473597d706e 392 * @name Register FB_CSCRn, field BEM[5] (RW)
bogdanm 82:6473597d706e 393 *
bogdanm 82:6473597d706e 394 * Specifies whether the corresponding FB_BE is asserted for read accesses.
bogdanm 82:6473597d706e 395 * Certain memories have byte enables that must be asserted during reads and writes.
bogdanm 82:6473597d706e 396 * Write 1b to the BEM bit in the relevant CSCR to provide the appropriate mode
bogdanm 82:6473597d706e 397 * of byte enable support for these SRAMs.
bogdanm 82:6473597d706e 398 *
bogdanm 82:6473597d706e 399 * Values:
bogdanm 82:6473597d706e 400 * - 0 - FB_BE is asserted for data write only.
bogdanm 82:6473597d706e 401 * - 1 - FB_BE is asserted for data read and write accesses.
bogdanm 82:6473597d706e 402 */
bogdanm 82:6473597d706e 403 //@{
bogdanm 82:6473597d706e 404 #define BP_FB_CSCRn_BEM (5U) //!< Bit position for FB_CSCRn_BEM.
bogdanm 82:6473597d706e 405 #define BM_FB_CSCRn_BEM (0x00000020U) //!< Bit mask for FB_CSCRn_BEM.
bogdanm 82:6473597d706e 406 #define BS_FB_CSCRn_BEM (1U) //!< Bit field size in bits for FB_CSCRn_BEM.
bogdanm 82:6473597d706e 407
bogdanm 82:6473597d706e 408 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 409 //! @brief Read current value of the FB_CSCRn_BEM field.
bogdanm 82:6473597d706e 410 #define BR_FB_CSCRn_BEM(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM))
bogdanm 82:6473597d706e 411 #endif
bogdanm 82:6473597d706e 412
bogdanm 82:6473597d706e 413 //! @brief Format value for bitfield FB_CSCRn_BEM.
bogdanm 82:6473597d706e 414 #define BF_FB_CSCRn_BEM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BEM), uint32_t) & BM_FB_CSCRn_BEM)
bogdanm 82:6473597d706e 415
bogdanm 82:6473597d706e 416 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 417 //! @brief Set the BEM field to a new value.
bogdanm 82:6473597d706e 418 #define BW_FB_CSCRn_BEM(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BEM) = (v))
bogdanm 82:6473597d706e 419 #endif
bogdanm 82:6473597d706e 420 //@}
bogdanm 82:6473597d706e 421
bogdanm 82:6473597d706e 422 /*!
bogdanm 82:6473597d706e 423 * @name Register FB_CSCRn, field PS[7:6] (RW)
bogdanm 82:6473597d706e 424 *
bogdanm 82:6473597d706e 425 * Specifies the data port width of the associated chip-select, and determines
bogdanm 82:6473597d706e 426 * where data is driven during write cycles and where data is sampled during read
bogdanm 82:6473597d706e 427 * cycles.
bogdanm 82:6473597d706e 428 *
bogdanm 82:6473597d706e 429 * Values:
bogdanm 82:6473597d706e 430 * - 00 - 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
bogdanm 82:6473597d706e 431 * - 01 - 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when
bogdanm 82:6473597d706e 432 * BLS is 0b, or FB_D[7:0] when BLS is 1b.
bogdanm 82:6473597d706e 433 */
bogdanm 82:6473597d706e 434 //@{
bogdanm 82:6473597d706e 435 #define BP_FB_CSCRn_PS (6U) //!< Bit position for FB_CSCRn_PS.
bogdanm 82:6473597d706e 436 #define BM_FB_CSCRn_PS (0x000000C0U) //!< Bit mask for FB_CSCRn_PS.
bogdanm 82:6473597d706e 437 #define BS_FB_CSCRn_PS (2U) //!< Bit field size in bits for FB_CSCRn_PS.
bogdanm 82:6473597d706e 438
bogdanm 82:6473597d706e 439 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 440 //! @brief Read current value of the FB_CSCRn_PS field.
bogdanm 82:6473597d706e 441 #define BR_FB_CSCRn_PS(n) (HW_FB_CSCRn(n).B.PS)
bogdanm 82:6473597d706e 442 #endif
bogdanm 82:6473597d706e 443
bogdanm 82:6473597d706e 444 //! @brief Format value for bitfield FB_CSCRn_PS.
bogdanm 82:6473597d706e 445 #define BF_FB_CSCRn_PS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_PS), uint32_t) & BM_FB_CSCRn_PS)
bogdanm 82:6473597d706e 446
bogdanm 82:6473597d706e 447 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 448 //! @brief Set the PS field to a new value.
bogdanm 82:6473597d706e 449 #define BW_FB_CSCRn_PS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_PS) | BF_FB_CSCRn_PS(v)))
bogdanm 82:6473597d706e 450 #endif
bogdanm 82:6473597d706e 451 //@}
bogdanm 82:6473597d706e 452
bogdanm 82:6473597d706e 453 /*!
bogdanm 82:6473597d706e 454 * @name Register FB_CSCRn, field AA[8] (RW)
bogdanm 82:6473597d706e 455 *
bogdanm 82:6473597d706e 456 * Asserts the internal transfer acknowledge for accesses specified by the
bogdanm 82:6473597d706e 457 * chip-select address. If AA is 1b for a corresponding FB_CSn and the external system
bogdanm 82:6473597d706e 458 * asserts an external FB_TA before the wait-state countdown asserts the
bogdanm 82:6473597d706e 459 * internal FB_TA, the cycle is terminated. Burst cycles increment the address bus
bogdanm 82:6473597d706e 460 * between each internal termination. This field must be 1b if CSPMCR disables FB_TA.
bogdanm 82:6473597d706e 461 *
bogdanm 82:6473597d706e 462 * Values:
bogdanm 82:6473597d706e 463 * - 0 - Disabled. No internal transfer acknowledge is asserted and the cycle is
bogdanm 82:6473597d706e 464 * terminated externally.
bogdanm 82:6473597d706e 465 * - 1 - Enabled. Internal transfer acknowledge is asserted as specified by WS.
bogdanm 82:6473597d706e 466 */
bogdanm 82:6473597d706e 467 //@{
bogdanm 82:6473597d706e 468 #define BP_FB_CSCRn_AA (8U) //!< Bit position for FB_CSCRn_AA.
bogdanm 82:6473597d706e 469 #define BM_FB_CSCRn_AA (0x00000100U) //!< Bit mask for FB_CSCRn_AA.
bogdanm 82:6473597d706e 470 #define BS_FB_CSCRn_AA (1U) //!< Bit field size in bits for FB_CSCRn_AA.
bogdanm 82:6473597d706e 471
bogdanm 82:6473597d706e 472 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 473 //! @brief Read current value of the FB_CSCRn_AA field.
bogdanm 82:6473597d706e 474 #define BR_FB_CSCRn_AA(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA))
bogdanm 82:6473597d706e 475 #endif
bogdanm 82:6473597d706e 476
bogdanm 82:6473597d706e 477 //! @brief Format value for bitfield FB_CSCRn_AA.
bogdanm 82:6473597d706e 478 #define BF_FB_CSCRn_AA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_AA), uint32_t) & BM_FB_CSCRn_AA)
bogdanm 82:6473597d706e 479
bogdanm 82:6473597d706e 480 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 481 //! @brief Set the AA field to a new value.
bogdanm 82:6473597d706e 482 #define BW_FB_CSCRn_AA(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_AA) = (v))
bogdanm 82:6473597d706e 483 #endif
bogdanm 82:6473597d706e 484 //@}
bogdanm 82:6473597d706e 485
bogdanm 82:6473597d706e 486 /*!
bogdanm 82:6473597d706e 487 * @name Register FB_CSCRn, field BLS[9] (RW)
bogdanm 82:6473597d706e 488 *
bogdanm 82:6473597d706e 489 * Specifies if data on FB_AD appears left-aligned or right-aligned during the
bogdanm 82:6473597d706e 490 * data phase of a FlexBus access.
bogdanm 82:6473597d706e 491 *
bogdanm 82:6473597d706e 492 * Values:
bogdanm 82:6473597d706e 493 * - 0 - Not shifted. Data is left-aligned on FB_AD.
bogdanm 82:6473597d706e 494 * - 1 - Shifted. Data is right-aligned on FB_AD.
bogdanm 82:6473597d706e 495 */
bogdanm 82:6473597d706e 496 //@{
bogdanm 82:6473597d706e 497 #define BP_FB_CSCRn_BLS (9U) //!< Bit position for FB_CSCRn_BLS.
bogdanm 82:6473597d706e 498 #define BM_FB_CSCRn_BLS (0x00000200U) //!< Bit mask for FB_CSCRn_BLS.
bogdanm 82:6473597d706e 499 #define BS_FB_CSCRn_BLS (1U) //!< Bit field size in bits for FB_CSCRn_BLS.
bogdanm 82:6473597d706e 500
bogdanm 82:6473597d706e 501 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 502 //! @brief Read current value of the FB_CSCRn_BLS field.
bogdanm 82:6473597d706e 503 #define BR_FB_CSCRn_BLS(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS))
bogdanm 82:6473597d706e 504 #endif
bogdanm 82:6473597d706e 505
bogdanm 82:6473597d706e 506 //! @brief Format value for bitfield FB_CSCRn_BLS.
bogdanm 82:6473597d706e 507 #define BF_FB_CSCRn_BLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_BLS), uint32_t) & BM_FB_CSCRn_BLS)
bogdanm 82:6473597d706e 508
bogdanm 82:6473597d706e 509 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 510 //! @brief Set the BLS field to a new value.
bogdanm 82:6473597d706e 511 #define BW_FB_CSCRn_BLS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_BLS) = (v))
bogdanm 82:6473597d706e 512 #endif
bogdanm 82:6473597d706e 513 //@}
bogdanm 82:6473597d706e 514
bogdanm 82:6473597d706e 515 /*!
bogdanm 82:6473597d706e 516 * @name Register FB_CSCRn, field WS[15:10] (RW)
bogdanm 82:6473597d706e 517 *
bogdanm 82:6473597d706e 518 * Specifies the number of wait states inserted after FlexBus asserts the
bogdanm 82:6473597d706e 519 * associated chip-select and before an internal transfer acknowledge is generated (WS
bogdanm 82:6473597d706e 520 * = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 wait states).
bogdanm 82:6473597d706e 521 */
bogdanm 82:6473597d706e 522 //@{
bogdanm 82:6473597d706e 523 #define BP_FB_CSCRn_WS (10U) //!< Bit position for FB_CSCRn_WS.
bogdanm 82:6473597d706e 524 #define BM_FB_CSCRn_WS (0x0000FC00U) //!< Bit mask for FB_CSCRn_WS.
bogdanm 82:6473597d706e 525 #define BS_FB_CSCRn_WS (6U) //!< Bit field size in bits for FB_CSCRn_WS.
bogdanm 82:6473597d706e 526
bogdanm 82:6473597d706e 527 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 528 //! @brief Read current value of the FB_CSCRn_WS field.
bogdanm 82:6473597d706e 529 #define BR_FB_CSCRn_WS(n) (HW_FB_CSCRn(n).B.WS)
bogdanm 82:6473597d706e 530 #endif
bogdanm 82:6473597d706e 531
bogdanm 82:6473597d706e 532 //! @brief Format value for bitfield FB_CSCRn_WS.
bogdanm 82:6473597d706e 533 #define BF_FB_CSCRn_WS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WS), uint32_t) & BM_FB_CSCRn_WS)
bogdanm 82:6473597d706e 534
bogdanm 82:6473597d706e 535 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 536 //! @brief Set the WS field to a new value.
bogdanm 82:6473597d706e 537 #define BW_FB_CSCRn_WS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WS) | BF_FB_CSCRn_WS(v)))
bogdanm 82:6473597d706e 538 #endif
bogdanm 82:6473597d706e 539 //@}
bogdanm 82:6473597d706e 540
bogdanm 82:6473597d706e 541 /*!
bogdanm 82:6473597d706e 542 * @name Register FB_CSCRn, field WRAH[17:16] (RW)
bogdanm 82:6473597d706e 543 *
bogdanm 82:6473597d706e 544 * Controls the address, data, and attribute hold time after the termination of
bogdanm 82:6473597d706e 545 * a write cycle that hits in the associated chip-select's address space. The
bogdanm 82:6473597d706e 546 * hold time applies only at the end of a transfer. Therefore, during a burst
bogdanm 82:6473597d706e 547 * transfer or a transfer to a port size smaller than the transfer size, the hold time
bogdanm 82:6473597d706e 548 * is only added after the last bus cycle.
bogdanm 82:6473597d706e 549 *
bogdanm 82:6473597d706e 550 * Values:
bogdanm 82:6473597d706e 551 * - 00 - 1 cycle (default for all but FB_CS0 )
bogdanm 82:6473597d706e 552 * - 01 - 2 cycles
bogdanm 82:6473597d706e 553 * - 10 - 3 cycles
bogdanm 82:6473597d706e 554 * - 11 - 4 cycles (default for FB_CS0 )
bogdanm 82:6473597d706e 555 */
bogdanm 82:6473597d706e 556 //@{
bogdanm 82:6473597d706e 557 #define BP_FB_CSCRn_WRAH (16U) //!< Bit position for FB_CSCRn_WRAH.
bogdanm 82:6473597d706e 558 #define BM_FB_CSCRn_WRAH (0x00030000U) //!< Bit mask for FB_CSCRn_WRAH.
bogdanm 82:6473597d706e 559 #define BS_FB_CSCRn_WRAH (2U) //!< Bit field size in bits for FB_CSCRn_WRAH.
bogdanm 82:6473597d706e 560
bogdanm 82:6473597d706e 561 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 562 //! @brief Read current value of the FB_CSCRn_WRAH field.
bogdanm 82:6473597d706e 563 #define BR_FB_CSCRn_WRAH(n) (HW_FB_CSCRn(n).B.WRAH)
bogdanm 82:6473597d706e 564 #endif
bogdanm 82:6473597d706e 565
bogdanm 82:6473597d706e 566 //! @brief Format value for bitfield FB_CSCRn_WRAH.
bogdanm 82:6473597d706e 567 #define BF_FB_CSCRn_WRAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_WRAH), uint32_t) & BM_FB_CSCRn_WRAH)
bogdanm 82:6473597d706e 568
bogdanm 82:6473597d706e 569 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 570 //! @brief Set the WRAH field to a new value.
bogdanm 82:6473597d706e 571 #define BW_FB_CSCRn_WRAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_WRAH) | BF_FB_CSCRn_WRAH(v)))
bogdanm 82:6473597d706e 572 #endif
bogdanm 82:6473597d706e 573 //@}
bogdanm 82:6473597d706e 574
bogdanm 82:6473597d706e 575 /*!
bogdanm 82:6473597d706e 576 * @name Register FB_CSCRn, field RDAH[19:18] (RW)
bogdanm 82:6473597d706e 577 *
bogdanm 82:6473597d706e 578 * Controls the address and attribute hold time after the termination during a
bogdanm 82:6473597d706e 579 * read cycle that hits in the associated chip-select's address space. The hold
bogdanm 82:6473597d706e 580 * time applies only at the end of a transfer. Therefore, during a burst transfer
bogdanm 82:6473597d706e 581 * or a transfer to a port size smaller than the transfer size, the hold time is
bogdanm 82:6473597d706e 582 * only added after the last bus cycle. The number of cycles the address and
bogdanm 82:6473597d706e 583 * attributes are held after FB_CSn deassertion depends on the value of the AA bit.
bogdanm 82:6473597d706e 584 *
bogdanm 82:6473597d706e 585 * Values:
bogdanm 82:6473597d706e 586 * - 00 - When AA is 0b, 1 cycle. When AA is 1b, 0 cycles.
bogdanm 82:6473597d706e 587 * - 01 - When AA is 0b, 2 cycles. When AA is 1b, 1 cycle.
bogdanm 82:6473597d706e 588 * - 10 - When AA is 0b, 3 cycles. When AA is 1b, 2 cycles.
bogdanm 82:6473597d706e 589 * - 11 - When AA is 0b, 4 cycles. When AA is 1b, 3 cycles.
bogdanm 82:6473597d706e 590 */
bogdanm 82:6473597d706e 591 //@{
bogdanm 82:6473597d706e 592 #define BP_FB_CSCRn_RDAH (18U) //!< Bit position for FB_CSCRn_RDAH.
bogdanm 82:6473597d706e 593 #define BM_FB_CSCRn_RDAH (0x000C0000U) //!< Bit mask for FB_CSCRn_RDAH.
bogdanm 82:6473597d706e 594 #define BS_FB_CSCRn_RDAH (2U) //!< Bit field size in bits for FB_CSCRn_RDAH.
bogdanm 82:6473597d706e 595
bogdanm 82:6473597d706e 596 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 597 //! @brief Read current value of the FB_CSCRn_RDAH field.
bogdanm 82:6473597d706e 598 #define BR_FB_CSCRn_RDAH(n) (HW_FB_CSCRn(n).B.RDAH)
bogdanm 82:6473597d706e 599 #endif
bogdanm 82:6473597d706e 600
bogdanm 82:6473597d706e 601 //! @brief Format value for bitfield FB_CSCRn_RDAH.
bogdanm 82:6473597d706e 602 #define BF_FB_CSCRn_RDAH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_RDAH), uint32_t) & BM_FB_CSCRn_RDAH)
bogdanm 82:6473597d706e 603
bogdanm 82:6473597d706e 604 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 605 //! @brief Set the RDAH field to a new value.
bogdanm 82:6473597d706e 606 #define BW_FB_CSCRn_RDAH(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_RDAH) | BF_FB_CSCRn_RDAH(v)))
bogdanm 82:6473597d706e 607 #endif
bogdanm 82:6473597d706e 608 //@}
bogdanm 82:6473597d706e 609
bogdanm 82:6473597d706e 610 /*!
bogdanm 82:6473597d706e 611 * @name Register FB_CSCRn, field ASET[21:20] (RW)
bogdanm 82:6473597d706e 612 *
bogdanm 82:6473597d706e 613 * Controls when the chip-select is asserted with respect to assertion of a
bogdanm 82:6473597d706e 614 * valid address and attributes.
bogdanm 82:6473597d706e 615 *
bogdanm 82:6473597d706e 616 * Values:
bogdanm 82:6473597d706e 617 * - 00 - Assert FB_CSn on the first rising clock edge after the address is
bogdanm 82:6473597d706e 618 * asserted (default for all but FB_CS0 ).
bogdanm 82:6473597d706e 619 * - 01 - Assert FB_CSn on the second rising clock edge after the address is
bogdanm 82:6473597d706e 620 * asserted.
bogdanm 82:6473597d706e 621 * - 10 - Assert FB_CSn on the third rising clock edge after the address is
bogdanm 82:6473597d706e 622 * asserted.
bogdanm 82:6473597d706e 623 * - 11 - Assert FB_CSn on the fourth rising clock edge after the address is
bogdanm 82:6473597d706e 624 * asserted (default for FB_CS0 ).
bogdanm 82:6473597d706e 625 */
bogdanm 82:6473597d706e 626 //@{
bogdanm 82:6473597d706e 627 #define BP_FB_CSCRn_ASET (20U) //!< Bit position for FB_CSCRn_ASET.
bogdanm 82:6473597d706e 628 #define BM_FB_CSCRn_ASET (0x00300000U) //!< Bit mask for FB_CSCRn_ASET.
bogdanm 82:6473597d706e 629 #define BS_FB_CSCRn_ASET (2U) //!< Bit field size in bits for FB_CSCRn_ASET.
bogdanm 82:6473597d706e 630
bogdanm 82:6473597d706e 631 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 632 //! @brief Read current value of the FB_CSCRn_ASET field.
bogdanm 82:6473597d706e 633 #define BR_FB_CSCRn_ASET(n) (HW_FB_CSCRn(n).B.ASET)
bogdanm 82:6473597d706e 634 #endif
bogdanm 82:6473597d706e 635
bogdanm 82:6473597d706e 636 //! @brief Format value for bitfield FB_CSCRn_ASET.
bogdanm 82:6473597d706e 637 #define BF_FB_CSCRn_ASET(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_ASET), uint32_t) & BM_FB_CSCRn_ASET)
bogdanm 82:6473597d706e 638
bogdanm 82:6473597d706e 639 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 640 //! @brief Set the ASET field to a new value.
bogdanm 82:6473597d706e 641 #define BW_FB_CSCRn_ASET(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_ASET) | BF_FB_CSCRn_ASET(v)))
bogdanm 82:6473597d706e 642 #endif
bogdanm 82:6473597d706e 643 //@}
bogdanm 82:6473597d706e 644
bogdanm 82:6473597d706e 645 /*!
bogdanm 82:6473597d706e 646 * @name Register FB_CSCRn, field EXTS[22] (RW)
bogdanm 82:6473597d706e 647 *
bogdanm 82:6473597d706e 648 * Extended Transfer Start/Extended Address Latch Enable Controls how long FB_TS
bogdanm 82:6473597d706e 649 * /FB_ALE is asserted.
bogdanm 82:6473597d706e 650 *
bogdanm 82:6473597d706e 651 * Values:
bogdanm 82:6473597d706e 652 * - 0 - Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
bogdanm 82:6473597d706e 653 * - 1 - Enabled. FB_TS /FB_ALE remains asserted until the first positive clock
bogdanm 82:6473597d706e 654 * edge after FB_CSn asserts.
bogdanm 82:6473597d706e 655 */
bogdanm 82:6473597d706e 656 //@{
bogdanm 82:6473597d706e 657 #define BP_FB_CSCRn_EXTS (22U) //!< Bit position for FB_CSCRn_EXTS.
bogdanm 82:6473597d706e 658 #define BM_FB_CSCRn_EXTS (0x00400000U) //!< Bit mask for FB_CSCRn_EXTS.
bogdanm 82:6473597d706e 659 #define BS_FB_CSCRn_EXTS (1U) //!< Bit field size in bits for FB_CSCRn_EXTS.
bogdanm 82:6473597d706e 660
bogdanm 82:6473597d706e 661 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 662 //! @brief Read current value of the FB_CSCRn_EXTS field.
bogdanm 82:6473597d706e 663 #define BR_FB_CSCRn_EXTS(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS))
bogdanm 82:6473597d706e 664 #endif
bogdanm 82:6473597d706e 665
bogdanm 82:6473597d706e 666 //! @brief Format value for bitfield FB_CSCRn_EXTS.
bogdanm 82:6473597d706e 667 #define BF_FB_CSCRn_EXTS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_EXTS), uint32_t) & BM_FB_CSCRn_EXTS)
bogdanm 82:6473597d706e 668
bogdanm 82:6473597d706e 669 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 670 //! @brief Set the EXTS field to a new value.
bogdanm 82:6473597d706e 671 #define BW_FB_CSCRn_EXTS(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_EXTS) = (v))
bogdanm 82:6473597d706e 672 #endif
bogdanm 82:6473597d706e 673 //@}
bogdanm 82:6473597d706e 674
bogdanm 82:6473597d706e 675 /*!
bogdanm 82:6473597d706e 676 * @name Register FB_CSCRn, field SWSEN[23] (RW)
bogdanm 82:6473597d706e 677 *
bogdanm 82:6473597d706e 678 * Values:
bogdanm 82:6473597d706e 679 * - 0 - Disabled. A number of wait states (specified by WS) are inserted before
bogdanm 82:6473597d706e 680 * an internal transfer acknowledge is generated for all transfers.
bogdanm 82:6473597d706e 681 * - 1 - Enabled. A number of wait states (specified by SWS) are inserted before
bogdanm 82:6473597d706e 682 * an internal transfer acknowledge is generated for burst transfer
bogdanm 82:6473597d706e 683 * secondary terminations.
bogdanm 82:6473597d706e 684 */
bogdanm 82:6473597d706e 685 //@{
bogdanm 82:6473597d706e 686 #define BP_FB_CSCRn_SWSEN (23U) //!< Bit position for FB_CSCRn_SWSEN.
bogdanm 82:6473597d706e 687 #define BM_FB_CSCRn_SWSEN (0x00800000U) //!< Bit mask for FB_CSCRn_SWSEN.
bogdanm 82:6473597d706e 688 #define BS_FB_CSCRn_SWSEN (1U) //!< Bit field size in bits for FB_CSCRn_SWSEN.
bogdanm 82:6473597d706e 689
bogdanm 82:6473597d706e 690 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 691 //! @brief Read current value of the FB_CSCRn_SWSEN field.
bogdanm 82:6473597d706e 692 #define BR_FB_CSCRn_SWSEN(n) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN))
bogdanm 82:6473597d706e 693 #endif
bogdanm 82:6473597d706e 694
bogdanm 82:6473597d706e 695 //! @brief Format value for bitfield FB_CSCRn_SWSEN.
bogdanm 82:6473597d706e 696 #define BF_FB_CSCRn_SWSEN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWSEN), uint32_t) & BM_FB_CSCRn_SWSEN)
bogdanm 82:6473597d706e 697
bogdanm 82:6473597d706e 698 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 699 //! @brief Set the SWSEN field to a new value.
bogdanm 82:6473597d706e 700 #define BW_FB_CSCRn_SWSEN(n, v) (BITBAND_ACCESS32(HW_FB_CSCRn_ADDR(n), BP_FB_CSCRn_SWSEN) = (v))
bogdanm 82:6473597d706e 701 #endif
bogdanm 82:6473597d706e 702 //@}
bogdanm 82:6473597d706e 703
bogdanm 82:6473597d706e 704 /*!
bogdanm 82:6473597d706e 705 * @name Register FB_CSCRn, field SWS[31:26] (RW)
bogdanm 82:6473597d706e 706 *
bogdanm 82:6473597d706e 707 * Used only when the SWSEN bit is 1b. Specifies the number of wait states
bogdanm 82:6473597d706e 708 * inserted before an internal transfer acknowledge is generated for a burst transfer
bogdanm 82:6473597d706e 709 * (except for the first termination, which is controlled by WS).
bogdanm 82:6473597d706e 710 */
bogdanm 82:6473597d706e 711 //@{
bogdanm 82:6473597d706e 712 #define BP_FB_CSCRn_SWS (26U) //!< Bit position for FB_CSCRn_SWS.
bogdanm 82:6473597d706e 713 #define BM_FB_CSCRn_SWS (0xFC000000U) //!< Bit mask for FB_CSCRn_SWS.
bogdanm 82:6473597d706e 714 #define BS_FB_CSCRn_SWS (6U) //!< Bit field size in bits for FB_CSCRn_SWS.
bogdanm 82:6473597d706e 715
bogdanm 82:6473597d706e 716 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 717 //! @brief Read current value of the FB_CSCRn_SWS field.
bogdanm 82:6473597d706e 718 #define BR_FB_CSCRn_SWS(n) (HW_FB_CSCRn(n).B.SWS)
bogdanm 82:6473597d706e 719 #endif
bogdanm 82:6473597d706e 720
bogdanm 82:6473597d706e 721 //! @brief Format value for bitfield FB_CSCRn_SWS.
bogdanm 82:6473597d706e 722 #define BF_FB_CSCRn_SWS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSCRn_SWS), uint32_t) & BM_FB_CSCRn_SWS)
bogdanm 82:6473597d706e 723
bogdanm 82:6473597d706e 724 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 725 //! @brief Set the SWS field to a new value.
bogdanm 82:6473597d706e 726 #define BW_FB_CSCRn_SWS(n, v) (HW_FB_CSCRn_WR(n, (HW_FB_CSCRn_RD(n) & ~BM_FB_CSCRn_SWS) | BF_FB_CSCRn_SWS(v)))
bogdanm 82:6473597d706e 727 #endif
bogdanm 82:6473597d706e 728 //@}
bogdanm 82:6473597d706e 729
bogdanm 82:6473597d706e 730 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 731 // HW_FB_CSPMCR - Chip Select port Multiplexing Control Register
bogdanm 82:6473597d706e 732 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 733
bogdanm 82:6473597d706e 734 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 735 /*!
bogdanm 82:6473597d706e 736 * @brief HW_FB_CSPMCR - Chip Select port Multiplexing Control Register (RW)
bogdanm 82:6473597d706e 737 *
bogdanm 82:6473597d706e 738 * Reset value: 0x00000000U
bogdanm 82:6473597d706e 739 *
bogdanm 82:6473597d706e 740 * Controls the multiplexing of the FlexBus signals. A bus error occurs when you
bogdanm 82:6473597d706e 741 * do any of the following: Write to a reserved address Write to a reserved
bogdanm 82:6473597d706e 742 * field in this register, or Access this register using a size other than 32 bits.
bogdanm 82:6473597d706e 743 */
bogdanm 82:6473597d706e 744 typedef union _hw_fb_cspmcr
bogdanm 82:6473597d706e 745 {
bogdanm 82:6473597d706e 746 uint32_t U;
bogdanm 82:6473597d706e 747 struct _hw_fb_cspmcr_bitfields
bogdanm 82:6473597d706e 748 {
bogdanm 82:6473597d706e 749 uint32_t RESERVED0 : 12; //!< [11:0]
bogdanm 82:6473597d706e 750 uint32_t GROUP5 : 4; //!< [15:12] FlexBus Signal Group 5 Multiplex
bogdanm 82:6473597d706e 751 //! control
bogdanm 82:6473597d706e 752 uint32_t GROUP4 : 4; //!< [19:16] FlexBus Signal Group 4 Multiplex
bogdanm 82:6473597d706e 753 //! control
bogdanm 82:6473597d706e 754 uint32_t GROUP3 : 4; //!< [23:20] FlexBus Signal Group 3 Multiplex
bogdanm 82:6473597d706e 755 //! control
bogdanm 82:6473597d706e 756 uint32_t GROUP2 : 4; //!< [27:24] FlexBus Signal Group 2 Multiplex
bogdanm 82:6473597d706e 757 //! control
bogdanm 82:6473597d706e 758 uint32_t GROUP1 : 4; //!< [31:28] FlexBus Signal Group 1 Multiplex
bogdanm 82:6473597d706e 759 //! control
bogdanm 82:6473597d706e 760 } B;
bogdanm 82:6473597d706e 761 } hw_fb_cspmcr_t;
bogdanm 82:6473597d706e 762 #endif
bogdanm 82:6473597d706e 763
bogdanm 82:6473597d706e 764 /*!
bogdanm 82:6473597d706e 765 * @name Constants and macros for entire FB_CSPMCR register
bogdanm 82:6473597d706e 766 */
bogdanm 82:6473597d706e 767 //@{
bogdanm 82:6473597d706e 768 #define HW_FB_CSPMCR_ADDR (REGS_FB_BASE + 0x60U)
bogdanm 82:6473597d706e 769
bogdanm 82:6473597d706e 770 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 771 #define HW_FB_CSPMCR (*(__IO hw_fb_cspmcr_t *) HW_FB_CSPMCR_ADDR)
bogdanm 82:6473597d706e 772 #define HW_FB_CSPMCR_RD() (HW_FB_CSPMCR.U)
bogdanm 82:6473597d706e 773 #define HW_FB_CSPMCR_WR(v) (HW_FB_CSPMCR.U = (v))
bogdanm 82:6473597d706e 774 #define HW_FB_CSPMCR_SET(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() | (v)))
bogdanm 82:6473597d706e 775 #define HW_FB_CSPMCR_CLR(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() & ~(v)))
bogdanm 82:6473597d706e 776 #define HW_FB_CSPMCR_TOG(v) (HW_FB_CSPMCR_WR(HW_FB_CSPMCR_RD() ^ (v)))
bogdanm 82:6473597d706e 777 #endif
bogdanm 82:6473597d706e 778 //@}
bogdanm 82:6473597d706e 779
bogdanm 82:6473597d706e 780 /*
bogdanm 82:6473597d706e 781 * Constants & macros for individual FB_CSPMCR bitfields
bogdanm 82:6473597d706e 782 */
bogdanm 82:6473597d706e 783
bogdanm 82:6473597d706e 784 /*!
bogdanm 82:6473597d706e 785 * @name Register FB_CSPMCR, field GROUP5[15:12] (RW)
bogdanm 82:6473597d706e 786 *
bogdanm 82:6473597d706e 787 * Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When
bogdanm 82:6473597d706e 788 * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the
bogdanm 82:6473597d706e 789 * bus hangs during a transfer.
bogdanm 82:6473597d706e 790 *
bogdanm 82:6473597d706e 791 * Values:
bogdanm 82:6473597d706e 792 * - 0000 - FB_TA
bogdanm 82:6473597d706e 793 * - 0001 - FB_CS3 . You must also write 1b to CSCR[AA].
bogdanm 82:6473597d706e 794 * - 0010 - FB_BE_7_0 . You must also write 1b to CSCR[AA].
bogdanm 82:6473597d706e 795 */
bogdanm 82:6473597d706e 796 //@{
bogdanm 82:6473597d706e 797 #define BP_FB_CSPMCR_GROUP5 (12U) //!< Bit position for FB_CSPMCR_GROUP5.
bogdanm 82:6473597d706e 798 #define BM_FB_CSPMCR_GROUP5 (0x0000F000U) //!< Bit mask for FB_CSPMCR_GROUP5.
bogdanm 82:6473597d706e 799 #define BS_FB_CSPMCR_GROUP5 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP5.
bogdanm 82:6473597d706e 800
bogdanm 82:6473597d706e 801 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 802 //! @brief Read current value of the FB_CSPMCR_GROUP5 field.
bogdanm 82:6473597d706e 803 #define BR_FB_CSPMCR_GROUP5 (HW_FB_CSPMCR.B.GROUP5)
bogdanm 82:6473597d706e 804 #endif
bogdanm 82:6473597d706e 805
bogdanm 82:6473597d706e 806 //! @brief Format value for bitfield FB_CSPMCR_GROUP5.
bogdanm 82:6473597d706e 807 #define BF_FB_CSPMCR_GROUP5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP5), uint32_t) & BM_FB_CSPMCR_GROUP5)
bogdanm 82:6473597d706e 808
bogdanm 82:6473597d706e 809 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 810 //! @brief Set the GROUP5 field to a new value.
bogdanm 82:6473597d706e 811 #define BW_FB_CSPMCR_GROUP5(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP5) | BF_FB_CSPMCR_GROUP5(v)))
bogdanm 82:6473597d706e 812 #endif
bogdanm 82:6473597d706e 813 //@}
bogdanm 82:6473597d706e 814
bogdanm 82:6473597d706e 815 /*!
bogdanm 82:6473597d706e 816 * @name Register FB_CSPMCR, field GROUP4[19:16] (RW)
bogdanm 82:6473597d706e 817 *
bogdanm 82:6473597d706e 818 * Controls the multiplexing of the FB_TBST , FB_CS2 , and FB_BE_15_8 signals.
bogdanm 82:6473597d706e 819 *
bogdanm 82:6473597d706e 820 * Values:
bogdanm 82:6473597d706e 821 * - 0000 - FB_TBST
bogdanm 82:6473597d706e 822 * - 0001 - FB_CS2
bogdanm 82:6473597d706e 823 * - 0010 - FB_BE_15_8
bogdanm 82:6473597d706e 824 */
bogdanm 82:6473597d706e 825 //@{
bogdanm 82:6473597d706e 826 #define BP_FB_CSPMCR_GROUP4 (16U) //!< Bit position for FB_CSPMCR_GROUP4.
bogdanm 82:6473597d706e 827 #define BM_FB_CSPMCR_GROUP4 (0x000F0000U) //!< Bit mask for FB_CSPMCR_GROUP4.
bogdanm 82:6473597d706e 828 #define BS_FB_CSPMCR_GROUP4 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP4.
bogdanm 82:6473597d706e 829
bogdanm 82:6473597d706e 830 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 831 //! @brief Read current value of the FB_CSPMCR_GROUP4 field.
bogdanm 82:6473597d706e 832 #define BR_FB_CSPMCR_GROUP4 (HW_FB_CSPMCR.B.GROUP4)
bogdanm 82:6473597d706e 833 #endif
bogdanm 82:6473597d706e 834
bogdanm 82:6473597d706e 835 //! @brief Format value for bitfield FB_CSPMCR_GROUP4.
bogdanm 82:6473597d706e 836 #define BF_FB_CSPMCR_GROUP4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP4), uint32_t) & BM_FB_CSPMCR_GROUP4)
bogdanm 82:6473597d706e 837
bogdanm 82:6473597d706e 838 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 839 //! @brief Set the GROUP4 field to a new value.
bogdanm 82:6473597d706e 840 #define BW_FB_CSPMCR_GROUP4(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP4) | BF_FB_CSPMCR_GROUP4(v)))
bogdanm 82:6473597d706e 841 #endif
bogdanm 82:6473597d706e 842 //@}
bogdanm 82:6473597d706e 843
bogdanm 82:6473597d706e 844 /*!
bogdanm 82:6473597d706e 845 * @name Register FB_CSPMCR, field GROUP3[23:20] (RW)
bogdanm 82:6473597d706e 846 *
bogdanm 82:6473597d706e 847 * Controls the multiplexing of the FB_CS5 , FB_TSIZ1, and FB_BE_23_16 signals.
bogdanm 82:6473597d706e 848 *
bogdanm 82:6473597d706e 849 * Values:
bogdanm 82:6473597d706e 850 * - 0000 - FB_CS5
bogdanm 82:6473597d706e 851 * - 0001 - FB_TSIZ1
bogdanm 82:6473597d706e 852 * - 0010 - FB_BE_23_16
bogdanm 82:6473597d706e 853 */
bogdanm 82:6473597d706e 854 //@{
bogdanm 82:6473597d706e 855 #define BP_FB_CSPMCR_GROUP3 (20U) //!< Bit position for FB_CSPMCR_GROUP3.
bogdanm 82:6473597d706e 856 #define BM_FB_CSPMCR_GROUP3 (0x00F00000U) //!< Bit mask for FB_CSPMCR_GROUP3.
bogdanm 82:6473597d706e 857 #define BS_FB_CSPMCR_GROUP3 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP3.
bogdanm 82:6473597d706e 858
bogdanm 82:6473597d706e 859 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 860 //! @brief Read current value of the FB_CSPMCR_GROUP3 field.
bogdanm 82:6473597d706e 861 #define BR_FB_CSPMCR_GROUP3 (HW_FB_CSPMCR.B.GROUP3)
bogdanm 82:6473597d706e 862 #endif
bogdanm 82:6473597d706e 863
bogdanm 82:6473597d706e 864 //! @brief Format value for bitfield FB_CSPMCR_GROUP3.
bogdanm 82:6473597d706e 865 #define BF_FB_CSPMCR_GROUP3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP3), uint32_t) & BM_FB_CSPMCR_GROUP3)
bogdanm 82:6473597d706e 866
bogdanm 82:6473597d706e 867 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 868 //! @brief Set the GROUP3 field to a new value.
bogdanm 82:6473597d706e 869 #define BW_FB_CSPMCR_GROUP3(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP3) | BF_FB_CSPMCR_GROUP3(v)))
bogdanm 82:6473597d706e 870 #endif
bogdanm 82:6473597d706e 871 //@}
bogdanm 82:6473597d706e 872
bogdanm 82:6473597d706e 873 /*!
bogdanm 82:6473597d706e 874 * @name Register FB_CSPMCR, field GROUP2[27:24] (RW)
bogdanm 82:6473597d706e 875 *
bogdanm 82:6473597d706e 876 * Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals.
bogdanm 82:6473597d706e 877 *
bogdanm 82:6473597d706e 878 * Values:
bogdanm 82:6473597d706e 879 * - 0000 - FB_CS4
bogdanm 82:6473597d706e 880 * - 0001 - FB_TSIZ0
bogdanm 82:6473597d706e 881 * - 0010 - FB_BE_31_24
bogdanm 82:6473597d706e 882 */
bogdanm 82:6473597d706e 883 //@{
bogdanm 82:6473597d706e 884 #define BP_FB_CSPMCR_GROUP2 (24U) //!< Bit position for FB_CSPMCR_GROUP2.
bogdanm 82:6473597d706e 885 #define BM_FB_CSPMCR_GROUP2 (0x0F000000U) //!< Bit mask for FB_CSPMCR_GROUP2.
bogdanm 82:6473597d706e 886 #define BS_FB_CSPMCR_GROUP2 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP2.
bogdanm 82:6473597d706e 887
bogdanm 82:6473597d706e 888 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 889 //! @brief Read current value of the FB_CSPMCR_GROUP2 field.
bogdanm 82:6473597d706e 890 #define BR_FB_CSPMCR_GROUP2 (HW_FB_CSPMCR.B.GROUP2)
bogdanm 82:6473597d706e 891 #endif
bogdanm 82:6473597d706e 892
bogdanm 82:6473597d706e 893 //! @brief Format value for bitfield FB_CSPMCR_GROUP2.
bogdanm 82:6473597d706e 894 #define BF_FB_CSPMCR_GROUP2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP2), uint32_t) & BM_FB_CSPMCR_GROUP2)
bogdanm 82:6473597d706e 895
bogdanm 82:6473597d706e 896 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 897 //! @brief Set the GROUP2 field to a new value.
bogdanm 82:6473597d706e 898 #define BW_FB_CSPMCR_GROUP2(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP2) | BF_FB_CSPMCR_GROUP2(v)))
bogdanm 82:6473597d706e 899 #endif
bogdanm 82:6473597d706e 900 //@}
bogdanm 82:6473597d706e 901
bogdanm 82:6473597d706e 902 /*!
bogdanm 82:6473597d706e 903 * @name Register FB_CSPMCR, field GROUP1[31:28] (RW)
bogdanm 82:6473597d706e 904 *
bogdanm 82:6473597d706e 905 * Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals.
bogdanm 82:6473597d706e 906 *
bogdanm 82:6473597d706e 907 * Values:
bogdanm 82:6473597d706e 908 * - 0000 - FB_ALE
bogdanm 82:6473597d706e 909 * - 0001 - FB_CS1
bogdanm 82:6473597d706e 910 * - 0010 - FB_TS
bogdanm 82:6473597d706e 911 */
bogdanm 82:6473597d706e 912 //@{
bogdanm 82:6473597d706e 913 #define BP_FB_CSPMCR_GROUP1 (28U) //!< Bit position for FB_CSPMCR_GROUP1.
bogdanm 82:6473597d706e 914 #define BM_FB_CSPMCR_GROUP1 (0xF0000000U) //!< Bit mask for FB_CSPMCR_GROUP1.
bogdanm 82:6473597d706e 915 #define BS_FB_CSPMCR_GROUP1 (4U) //!< Bit field size in bits for FB_CSPMCR_GROUP1.
bogdanm 82:6473597d706e 916
bogdanm 82:6473597d706e 917 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 918 //! @brief Read current value of the FB_CSPMCR_GROUP1 field.
bogdanm 82:6473597d706e 919 #define BR_FB_CSPMCR_GROUP1 (HW_FB_CSPMCR.B.GROUP1)
bogdanm 82:6473597d706e 920 #endif
bogdanm 82:6473597d706e 921
bogdanm 82:6473597d706e 922 //! @brief Format value for bitfield FB_CSPMCR_GROUP1.
bogdanm 82:6473597d706e 923 #define BF_FB_CSPMCR_GROUP1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_FB_CSPMCR_GROUP1), uint32_t) & BM_FB_CSPMCR_GROUP1)
bogdanm 82:6473597d706e 924
bogdanm 82:6473597d706e 925 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 926 //! @brief Set the GROUP1 field to a new value.
bogdanm 82:6473597d706e 927 #define BW_FB_CSPMCR_GROUP1(v) (HW_FB_CSPMCR_WR((HW_FB_CSPMCR_RD() & ~BM_FB_CSPMCR_GROUP1) | BF_FB_CSPMCR_GROUP1(v)))
bogdanm 82:6473597d706e 928 #endif
bogdanm 82:6473597d706e 929 //@}
bogdanm 82:6473597d706e 930
bogdanm 82:6473597d706e 931 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 932 // hw_fb_t - module struct
bogdanm 82:6473597d706e 933 //-------------------------------------------------------------------------------------------
bogdanm 82:6473597d706e 934 /*!
bogdanm 82:6473597d706e 935 * @brief All FB module registers.
bogdanm 82:6473597d706e 936 */
bogdanm 82:6473597d706e 937 #ifndef __LANGUAGE_ASM__
bogdanm 82:6473597d706e 938 #pragma pack(1)
bogdanm 82:6473597d706e 939 typedef struct _hw_fb
bogdanm 82:6473597d706e 940 {
bogdanm 82:6473597d706e 941 struct {
bogdanm 82:6473597d706e 942 __IO hw_fb_csarn_t CSARn; //!< [0x0] Chip Select Address Register
bogdanm 82:6473597d706e 943 __IO hw_fb_csmrn_t CSMRn; //!< [0x4] Chip Select Mask Register
bogdanm 82:6473597d706e 944 __IO hw_fb_cscrn_t CSCRn; //!< [0x8] Chip Select Control Register
bogdanm 82:6473597d706e 945 } CS[6];
bogdanm 82:6473597d706e 946 uint8_t _reserved0[24];
bogdanm 82:6473597d706e 947 __IO hw_fb_cspmcr_t CSPMCR; //!< [0x60] Chip Select port Multiplexing Control Register
bogdanm 82:6473597d706e 948 } hw_fb_t;
bogdanm 82:6473597d706e 949 #pragma pack()
bogdanm 82:6473597d706e 950
bogdanm 82:6473597d706e 951 //! @brief Macro to access all FB registers.
bogdanm 82:6473597d706e 952 //! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm 82:6473597d706e 953 //! use the '&' operator, like <code>&HW_FB</code>.
bogdanm 82:6473597d706e 954 #define HW_FB (*(hw_fb_t *) REGS_FB_BASE)
bogdanm 82:6473597d706e 955 #endif
bogdanm 82:6473597d706e 956
bogdanm 82:6473597d706e 957 #endif // __HW_FB_REGISTERS_H__
bogdanm 82:6473597d706e 958 // v22/130726/0.9
bogdanm 82:6473597d706e 959 // EOF