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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_dma.h@89:552587b429a1, 2014-09-12 (annotated)

Committer:: bogdanm
Date:: Fri Sep 12 16:41:52 2014 +0100
Revision:: 89:552587b429a1
Parent:: TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/device/MK64F12/MK64F12_dma.h@82:6473597d706e

Release 89 of the mbed library



Main changes:



- low power optimizations for Nordic targets

- code structure changes for Freescale K64F targets

- bug fixes in various backends

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	82:6473597d706e	1	/*
bogdanm	82:6473597d706e	2	* Copyright (c) 2014, Freescale Semiconductor, Inc.
bogdanm	82:6473597d706e	3	* All rights reserved.
bogdanm	82:6473597d706e	4	*
bogdanm	82:6473597d706e	5	* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
bogdanm	82:6473597d706e	6	* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
bogdanm	82:6473597d706e	7	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
bogdanm	82:6473597d706e	8	* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
bogdanm	82:6473597d706e	9	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
bogdanm	82:6473597d706e	10	* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm	82:6473597d706e	11	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm	82:6473597d706e	12	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
bogdanm	82:6473597d706e	13	* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
bogdanm	82:6473597d706e	14	* OF SUCH DAMAGE.
bogdanm	82:6473597d706e	15	*/
bogdanm	82:6473597d706e	16	/*
bogdanm	82:6473597d706e	17	* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
bogdanm	82:6473597d706e	18	*
bogdanm	82:6473597d706e	19	* This file was generated automatically and any changes may be lost.
bogdanm	82:6473597d706e	20	*/
bogdanm	82:6473597d706e	21	#ifndef __HW_DMA_REGISTERS_H__
bogdanm	82:6473597d706e	22	#define __HW_DMA_REGISTERS_H__
bogdanm	82:6473597d706e	23
bogdanm	82:6473597d706e	24	#include "regs.h"
bogdanm	82:6473597d706e	25
bogdanm	82:6473597d706e	26	/*
bogdanm	82:6473597d706e	27	* MK64F12 DMA
bogdanm	82:6473597d706e	28	*
bogdanm	82:6473597d706e	29	* Enhanced direct memory access controller
bogdanm	82:6473597d706e	30	*
bogdanm	82:6473597d706e	31	* Registers defined in this header file:
bogdanm	82:6473597d706e	32	* - HW_DMA_CR - Control Register
bogdanm	82:6473597d706e	33	* - HW_DMA_ES - Error Status Register
bogdanm	82:6473597d706e	34	* - HW_DMA_ERQ - Enable Request Register
bogdanm	82:6473597d706e	35	* - HW_DMA_EEI - Enable Error Interrupt Register
bogdanm	82:6473597d706e	36	* - HW_DMA_CEEI - Clear Enable Error Interrupt Register
bogdanm	82:6473597d706e	37	* - HW_DMA_SEEI - Set Enable Error Interrupt Register
bogdanm	82:6473597d706e	38	* - HW_DMA_CERQ - Clear Enable Request Register
bogdanm	82:6473597d706e	39	* - HW_DMA_SERQ - Set Enable Request Register
bogdanm	82:6473597d706e	40	* - HW_DMA_CDNE - Clear DONE Status Bit Register
bogdanm	82:6473597d706e	41	* - HW_DMA_SSRT - Set START Bit Register
bogdanm	82:6473597d706e	42	* - HW_DMA_CERR - Clear Error Register
bogdanm	82:6473597d706e	43	* - HW_DMA_CINT - Clear Interrupt Request Register
bogdanm	82:6473597d706e	44	* - HW_DMA_INT - Interrupt Request Register
bogdanm	82:6473597d706e	45	* - HW_DMA_ERR - Error Register
bogdanm	82:6473597d706e	46	* - HW_DMA_HRS - Hardware Request Status Register
bogdanm	82:6473597d706e	47	* - HW_DMA_DCHPRIn - Channel n Priority Register
bogdanm	82:6473597d706e	48	* - HW_DMA_TCDn_SADDR - TCD Source Address
bogdanm	82:6473597d706e	49	* - HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
bogdanm	82:6473597d706e	50	* - HW_DMA_TCDn_ATTR - TCD Transfer Attributes
bogdanm	82:6473597d706e	51	* - HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
bogdanm	82:6473597d706e	52	* - HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
bogdanm	82:6473597d706e	53	* - HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
bogdanm	82:6473597d706e	54	* - HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
bogdanm	82:6473597d706e	55	* - HW_DMA_TCDn_DADDR - TCD Destination Address
bogdanm	82:6473597d706e	56	* - HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
bogdanm	82:6473597d706e	57	* - HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
bogdanm	82:6473597d706e	58	* - HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
bogdanm	82:6473597d706e	59	* - HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
bogdanm	82:6473597d706e	60	* - HW_DMA_TCDn_CSR - TCD Control and Status
bogdanm	82:6473597d706e	61	* - HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
bogdanm	82:6473597d706e	62	* - HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
bogdanm	82:6473597d706e	63	*
bogdanm	82:6473597d706e	64	* - hw_dma_t - Struct containing all module registers.
bogdanm	82:6473597d706e	65	*/
bogdanm	82:6473597d706e	66
bogdanm	82:6473597d706e	67	//! @name Module base addresses
bogdanm	82:6473597d706e	68	//@{
bogdanm	82:6473597d706e	69	#ifndef REGS_DMA_BASE
bogdanm	82:6473597d706e	70	#define HW_DMA_INSTANCE_COUNT (1U) //!< Number of instances of the DMA module.
bogdanm	82:6473597d706e	71	#define HW_DMA0 (0U) //!< Instance number for DMA.
bogdanm	82:6473597d706e	72	#define REGS_DMA0_BASE (0x40008000U) //!< Base address for DMA.
bogdanm	82:6473597d706e	73
bogdanm	82:6473597d706e	74	//! @brief Table of base addresses for DMA instances.
bogdanm	82:6473597d706e	75	static const uint32_t __g_regs_DMA_base_addresses[] = {
bogdanm	82:6473597d706e	76	REGS_DMA0_BASE,
bogdanm	82:6473597d706e	77	};
bogdanm	82:6473597d706e	78
bogdanm	82:6473597d706e	79	//! @brief Get the base address of DMA by instance number.
bogdanm	82:6473597d706e	80	//! @param x DMA instance number, from 0 through 0.
bogdanm	82:6473597d706e	81	#define REGS_DMA_BASE(x) (__g_regs_DMA_base_addresses[(x)])
bogdanm	82:6473597d706e	82
bogdanm	82:6473597d706e	83	//! @brief Get the instance number given a base address.
bogdanm	82:6473597d706e	84	//! @param b Base address for an instance of DMA.
bogdanm	82:6473597d706e	85	#define REGS_DMA_INSTANCE(b) ((b) == REGS_DMA0_BASE ? HW_DMA0 : 0)
bogdanm	82:6473597d706e	86	#endif
bogdanm	82:6473597d706e	87	//@}
bogdanm	82:6473597d706e	88
bogdanm	82:6473597d706e	89	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	90	// HW_DMA_CR - Control Register
bogdanm	82:6473597d706e	91	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	92
bogdanm	82:6473597d706e	93	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	94	/*!
bogdanm	82:6473597d706e	95	* @brief HW_DMA_CR - Control Register (RW)
bogdanm	82:6473597d706e	96	*
bogdanm	82:6473597d706e	97	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	98	*
bogdanm	82:6473597d706e	99	* The CR defines the basic operating configuration of the DMA. Arbitration can
bogdanm	82:6473597d706e	100	* be configured to use either a fixed-priority or a round-robin scheme. For
bogdanm	82:6473597d706e	101	* fixed-priority arbitration, the highest priority channel requesting service is
bogdanm	82:6473597d706e	102	* selected to execute. The channel priority registers assign the priorities; see
bogdanm	82:6473597d706e	103	* the DCHPRIn registers. For round-robin arbitration, the channel priorities are
bogdanm	82:6473597d706e	104	* ignored and channels are cycled through (from high to low channel number)
bogdanm	82:6473597d706e	105	* without regard to priority. For correct operation, writes to the CR register must
bogdanm	82:6473597d706e	106	* be performed only when the DMA channels are inactive; that is, when
bogdanm	82:6473597d706e	107	* TCDn_CSR[ACTIVE] bits are cleared. Minor loop offsets are address offset values added to
bogdanm	82:6473597d706e	108	* the final source address (TCDn_SADDR) or destination address (TCDn_DADDR) upon
bogdanm	82:6473597d706e	109	* minor loop completion. When minor loop offsets are enabled, the minor loop
bogdanm	82:6473597d706e	110	* offset (MLOFF) is added to the final source address (TCDn_SADDR), to the final
bogdanm	82:6473597d706e	111	* destination address (TCDn_DADDR), or to both prior to the addresses being
bogdanm	82:6473597d706e	112	* written back into the TCD. If the major loop is complete, the minor loop offset is
bogdanm	82:6473597d706e	113	* ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are
bogdanm	82:6473597d706e	114	* used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop
bogdanm	82:6473597d706e	115	* mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2
bogdanm	82:6473597d706e	116	* is used to specify multiple fields: a source enable bit (SMLOE) to specify
bogdanm	82:6473597d706e	117	* the minor loop offset should be applied to the source address (TCDn_SADDR) upon
bogdanm	82:6473597d706e	118	* minor loop completion, a destination enable bit (DMLOE) to specify the minor
bogdanm	82:6473597d706e	119	* loop offset should be applied to the destination address (TCDn_DADDR) upon
bogdanm	82:6473597d706e	120	* minor loop completion, and the sign extended minor loop offset value (MLOFF). The
bogdanm	82:6473597d706e	121	* same offset value (MLOFF) is used for both source and destination minor loop
bogdanm	82:6473597d706e	122	* offsets. When either minor loop offset is enabled (SMLOE set or DMLOE set), the
bogdanm	82:6473597d706e	123	* NBYTES field is reduced to 10 bits. When both minor loop offsets are disabled
bogdanm	82:6473597d706e	124	* (SMLOE cleared and DMLOE cleared), the NBYTES field is a 30-bit vector. When
bogdanm	82:6473597d706e	125	* minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are
bogdanm	82:6473597d706e	126	* assigned to the NBYTES field.
bogdanm	82:6473597d706e	127	*/
bogdanm	82:6473597d706e	128	typedef union _hw_dma_cr
bogdanm	82:6473597d706e	129	{
bogdanm	82:6473597d706e	130	uint32_t U;
bogdanm	82:6473597d706e	131	struct _hw_dma_cr_bitfields
bogdanm	82:6473597d706e	132	{
bogdanm	82:6473597d706e	133	uint32_t RESERVED0 : 1; //!< [0] Reserved.
bogdanm	82:6473597d706e	134	uint32_t EDBG : 1; //!< [1] Enable Debug
bogdanm	82:6473597d706e	135	uint32_t ERCA : 1; //!< [2] Enable Round Robin Channel Arbitration
bogdanm	82:6473597d706e	136	uint32_t RESERVED1 : 1; //!< [3] Reserved.
bogdanm	82:6473597d706e	137	uint32_t HOE : 1; //!< [4] Halt On Error
bogdanm	82:6473597d706e	138	uint32_t HALT : 1; //!< [5] Halt DMA Operations
bogdanm	82:6473597d706e	139	uint32_t CLM : 1; //!< [6] Continuous Link Mode
bogdanm	82:6473597d706e	140	uint32_t EMLM : 1; //!< [7] Enable Minor Loop Mapping
bogdanm	82:6473597d706e	141	uint32_t RESERVED2 : 8; //!< [15:8]
bogdanm	82:6473597d706e	142	uint32_t ECX : 1; //!< [16] Error Cancel Transfer
bogdanm	82:6473597d706e	143	uint32_t CX : 1; //!< [17] Cancel Transfer
bogdanm	82:6473597d706e	144	uint32_t RESERVED3 : 14; //!< [31:18]
bogdanm	82:6473597d706e	145	} B;
bogdanm	82:6473597d706e	146	} hw_dma_cr_t;
bogdanm	82:6473597d706e	147	#endif
bogdanm	82:6473597d706e	148
bogdanm	82:6473597d706e	149	/*!
bogdanm	82:6473597d706e	150	* @name Constants and macros for entire DMA_CR register
bogdanm	82:6473597d706e	151	*/
bogdanm	82:6473597d706e	152	//@{
bogdanm	82:6473597d706e	153	#define HW_DMA_CR_ADDR(x) (REGS_DMA_BASE(x) + 0x0U)
bogdanm	82:6473597d706e	154
bogdanm	82:6473597d706e	155	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	156	#define HW_DMA_CR(x) ((__IO hw_dma_cr_t ) HW_DMA_CR_ADDR(x))
bogdanm	82:6473597d706e	157	#define HW_DMA_CR_RD(x) (HW_DMA_CR(x).U)
bogdanm	82:6473597d706e	158	#define HW_DMA_CR_WR(x, v) (HW_DMA_CR(x).U = (v))
bogdanm	82:6473597d706e	159	#define HW_DMA_CR_SET(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) \| (v)))
bogdanm	82:6473597d706e	160	#define HW_DMA_CR_CLR(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	161	#define HW_DMA_CR_TOG(x, v) (HW_DMA_CR_WR(x, HW_DMA_CR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	162	#endif
bogdanm	82:6473597d706e	163	//@}
bogdanm	82:6473597d706e	164
bogdanm	82:6473597d706e	165	/*
bogdanm	82:6473597d706e	166	* Constants & macros for individual DMA_CR bitfields
bogdanm	82:6473597d706e	167	*/
bogdanm	82:6473597d706e	168
bogdanm	82:6473597d706e	169	/*!
bogdanm	82:6473597d706e	170	* @name Register DMA_CR, field EDBG[1] (RW)
bogdanm	82:6473597d706e	171	*
bogdanm	82:6473597d706e	172	* Values:
bogdanm	82:6473597d706e	173	* - 0 - When in debug mode, the DMA continues to operate.
bogdanm	82:6473597d706e	174	* - 1 - When in debug mode, the DMA stalls the start of a new channel.
bogdanm	82:6473597d706e	175	* Executing channels are allowed to complete. Channel execution resumes when the
bogdanm	82:6473597d706e	176	* system exits debug mode or the EDBG bit is cleared.
bogdanm	82:6473597d706e	177	*/
bogdanm	82:6473597d706e	178	//@{
bogdanm	82:6473597d706e	179	#define BP_DMA_CR_EDBG (1U) //!< Bit position for DMA_CR_EDBG.
bogdanm	82:6473597d706e	180	#define BM_DMA_CR_EDBG (0x00000002U) //!< Bit mask for DMA_CR_EDBG.
bogdanm	82:6473597d706e	181	#define BS_DMA_CR_EDBG (1U) //!< Bit field size in bits for DMA_CR_EDBG.
bogdanm	82:6473597d706e	182
bogdanm	82:6473597d706e	183	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	184	//! @brief Read current value of the DMA_CR_EDBG field.
bogdanm	82:6473597d706e	185	#define BR_DMA_CR_EDBG(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG))
bogdanm	82:6473597d706e	186	#endif
bogdanm	82:6473597d706e	187
bogdanm	82:6473597d706e	188	//! @brief Format value for bitfield DMA_CR_EDBG.
bogdanm	82:6473597d706e	189	#define BF_DMA_CR_EDBG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_EDBG), uint32_t) & BM_DMA_CR_EDBG)
bogdanm	82:6473597d706e	190
bogdanm	82:6473597d706e	191	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	192	//! @brief Set the EDBG field to a new value.
bogdanm	82:6473597d706e	193	#define BW_DMA_CR_EDBG(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EDBG) = (v))
bogdanm	82:6473597d706e	194	#endif
bogdanm	82:6473597d706e	195	//@}
bogdanm	82:6473597d706e	196
bogdanm	82:6473597d706e	197	/*!
bogdanm	82:6473597d706e	198	* @name Register DMA_CR, field ERCA[2] (RW)
bogdanm	82:6473597d706e	199	*
bogdanm	82:6473597d706e	200	* Values:
bogdanm	82:6473597d706e	201	* - 0 - Fixed priority arbitration is used for channel selection .
bogdanm	82:6473597d706e	202	* - 1 - Round robin arbitration is used for channel selection .
bogdanm	82:6473597d706e	203	*/
bogdanm	82:6473597d706e	204	//@{
bogdanm	82:6473597d706e	205	#define BP_DMA_CR_ERCA (2U) //!< Bit position for DMA_CR_ERCA.
bogdanm	82:6473597d706e	206	#define BM_DMA_CR_ERCA (0x00000004U) //!< Bit mask for DMA_CR_ERCA.
bogdanm	82:6473597d706e	207	#define BS_DMA_CR_ERCA (1U) //!< Bit field size in bits for DMA_CR_ERCA.
bogdanm	82:6473597d706e	208
bogdanm	82:6473597d706e	209	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	210	//! @brief Read current value of the DMA_CR_ERCA field.
bogdanm	82:6473597d706e	211	#define BR_DMA_CR_ERCA(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA))
bogdanm	82:6473597d706e	212	#endif
bogdanm	82:6473597d706e	213
bogdanm	82:6473597d706e	214	//! @brief Format value for bitfield DMA_CR_ERCA.
bogdanm	82:6473597d706e	215	#define BF_DMA_CR_ERCA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_ERCA), uint32_t) & BM_DMA_CR_ERCA)
bogdanm	82:6473597d706e	216
bogdanm	82:6473597d706e	217	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	218	//! @brief Set the ERCA field to a new value.
bogdanm	82:6473597d706e	219	#define BW_DMA_CR_ERCA(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ERCA) = (v))
bogdanm	82:6473597d706e	220	#endif
bogdanm	82:6473597d706e	221	//@}
bogdanm	82:6473597d706e	222
bogdanm	82:6473597d706e	223	/*!
bogdanm	82:6473597d706e	224	* @name Register DMA_CR, field HOE[4] (RW)
bogdanm	82:6473597d706e	225	*
bogdanm	82:6473597d706e	226	* Values:
bogdanm	82:6473597d706e	227	* - 0 - Normal operation
bogdanm	82:6473597d706e	228	* - 1 - Any error causes the HALT bit to set. Subsequently, all service
bogdanm	82:6473597d706e	229	* requests are ignored until the HALT bit is cleared.
bogdanm	82:6473597d706e	230	*/
bogdanm	82:6473597d706e	231	//@{
bogdanm	82:6473597d706e	232	#define BP_DMA_CR_HOE (4U) //!< Bit position for DMA_CR_HOE.
bogdanm	82:6473597d706e	233	#define BM_DMA_CR_HOE (0x00000010U) //!< Bit mask for DMA_CR_HOE.
bogdanm	82:6473597d706e	234	#define BS_DMA_CR_HOE (1U) //!< Bit field size in bits for DMA_CR_HOE.
bogdanm	82:6473597d706e	235
bogdanm	82:6473597d706e	236	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	237	//! @brief Read current value of the DMA_CR_HOE field.
bogdanm	82:6473597d706e	238	#define BR_DMA_CR_HOE(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE))
bogdanm	82:6473597d706e	239	#endif
bogdanm	82:6473597d706e	240
bogdanm	82:6473597d706e	241	//! @brief Format value for bitfield DMA_CR_HOE.
bogdanm	82:6473597d706e	242	#define BF_DMA_CR_HOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_HOE), uint32_t) & BM_DMA_CR_HOE)
bogdanm	82:6473597d706e	243
bogdanm	82:6473597d706e	244	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	245	//! @brief Set the HOE field to a new value.
bogdanm	82:6473597d706e	246	#define BW_DMA_CR_HOE(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HOE) = (v))
bogdanm	82:6473597d706e	247	#endif
bogdanm	82:6473597d706e	248	//@}
bogdanm	82:6473597d706e	249
bogdanm	82:6473597d706e	250	/*!
bogdanm	82:6473597d706e	251	* @name Register DMA_CR, field HALT[5] (RW)
bogdanm	82:6473597d706e	252	*
bogdanm	82:6473597d706e	253	* Values:
bogdanm	82:6473597d706e	254	* - 0 - Normal operation
bogdanm	82:6473597d706e	255	* - 1 - Stall the start of any new channels. Executing channels are allowed to
bogdanm	82:6473597d706e	256	* complete. Channel execution resumes when this bit is cleared.
bogdanm	82:6473597d706e	257	*/
bogdanm	82:6473597d706e	258	//@{
bogdanm	82:6473597d706e	259	#define BP_DMA_CR_HALT (5U) //!< Bit position for DMA_CR_HALT.
bogdanm	82:6473597d706e	260	#define BM_DMA_CR_HALT (0x00000020U) //!< Bit mask for DMA_CR_HALT.
bogdanm	82:6473597d706e	261	#define BS_DMA_CR_HALT (1U) //!< Bit field size in bits for DMA_CR_HALT.
bogdanm	82:6473597d706e	262
bogdanm	82:6473597d706e	263	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	264	//! @brief Read current value of the DMA_CR_HALT field.
bogdanm	82:6473597d706e	265	#define BR_DMA_CR_HALT(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT))
bogdanm	82:6473597d706e	266	#endif
bogdanm	82:6473597d706e	267
bogdanm	82:6473597d706e	268	//! @brief Format value for bitfield DMA_CR_HALT.
bogdanm	82:6473597d706e	269	#define BF_DMA_CR_HALT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_HALT), uint32_t) & BM_DMA_CR_HALT)
bogdanm	82:6473597d706e	270
bogdanm	82:6473597d706e	271	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	272	//! @brief Set the HALT field to a new value.
bogdanm	82:6473597d706e	273	#define BW_DMA_CR_HALT(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_HALT) = (v))
bogdanm	82:6473597d706e	274	#endif
bogdanm	82:6473597d706e	275	//@}
bogdanm	82:6473597d706e	276
bogdanm	82:6473597d706e	277	/*!
bogdanm	82:6473597d706e	278	* @name Register DMA_CR, field CLM[6] (RW)
bogdanm	82:6473597d706e	279	*
bogdanm	82:6473597d706e	280	* Values:
bogdanm	82:6473597d706e	281	* - 0 - A minor loop channel link made to itself goes through channel
bogdanm	82:6473597d706e	282	* arbitration before being activated again.
bogdanm	82:6473597d706e	283	* - 1 - A minor loop channel link made to itself does not go through channel
bogdanm	82:6473597d706e	284	* arbitration before being activated again. Upon minor loop completion, the
bogdanm	82:6473597d706e	285	* channel activates again if that channel has a minor loop channel link
bogdanm	82:6473597d706e	286	* enabled and the link channel is itself. This effectively applies the minor loop
bogdanm	82:6473597d706e	287	* offsets and restarts the next minor loop.
bogdanm	82:6473597d706e	288	*/
bogdanm	82:6473597d706e	289	//@{
bogdanm	82:6473597d706e	290	#define BP_DMA_CR_CLM (6U) //!< Bit position for DMA_CR_CLM.
bogdanm	82:6473597d706e	291	#define BM_DMA_CR_CLM (0x00000040U) //!< Bit mask for DMA_CR_CLM.
bogdanm	82:6473597d706e	292	#define BS_DMA_CR_CLM (1U) //!< Bit field size in bits for DMA_CR_CLM.
bogdanm	82:6473597d706e	293
bogdanm	82:6473597d706e	294	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	295	//! @brief Read current value of the DMA_CR_CLM field.
bogdanm	82:6473597d706e	296	#define BR_DMA_CR_CLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM))
bogdanm	82:6473597d706e	297	#endif
bogdanm	82:6473597d706e	298
bogdanm	82:6473597d706e	299	//! @brief Format value for bitfield DMA_CR_CLM.
bogdanm	82:6473597d706e	300	#define BF_DMA_CR_CLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_CLM), uint32_t) & BM_DMA_CR_CLM)
bogdanm	82:6473597d706e	301
bogdanm	82:6473597d706e	302	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	303	//! @brief Set the CLM field to a new value.
bogdanm	82:6473597d706e	304	#define BW_DMA_CR_CLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CLM) = (v))
bogdanm	82:6473597d706e	305	#endif
bogdanm	82:6473597d706e	306	//@}
bogdanm	82:6473597d706e	307
bogdanm	82:6473597d706e	308	/*!
bogdanm	82:6473597d706e	309	* @name Register DMA_CR, field EMLM[7] (RW)
bogdanm	82:6473597d706e	310	*
bogdanm	82:6473597d706e	311	* Values:
bogdanm	82:6473597d706e	312	* - 0 - Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
bogdanm	82:6473597d706e	313	* - 1 - Enabled. TCDn.word2 is redefined to include individual enable fields,
bogdanm	82:6473597d706e	314	* an offset field, and the NBYTES field. The individual enable fields allow
bogdanm	82:6473597d706e	315	* the minor loop offset to be applied to the source address, the destination
bogdanm	82:6473597d706e	316	* address, or both. The NBYTES field is reduced when either offset is
bogdanm	82:6473597d706e	317	* enabled.
bogdanm	82:6473597d706e	318	*/
bogdanm	82:6473597d706e	319	//@{
bogdanm	82:6473597d706e	320	#define BP_DMA_CR_EMLM (7U) //!< Bit position for DMA_CR_EMLM.
bogdanm	82:6473597d706e	321	#define BM_DMA_CR_EMLM (0x00000080U) //!< Bit mask for DMA_CR_EMLM.
bogdanm	82:6473597d706e	322	#define BS_DMA_CR_EMLM (1U) //!< Bit field size in bits for DMA_CR_EMLM.
bogdanm	82:6473597d706e	323
bogdanm	82:6473597d706e	324	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	325	//! @brief Read current value of the DMA_CR_EMLM field.
bogdanm	82:6473597d706e	326	#define BR_DMA_CR_EMLM(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM))
bogdanm	82:6473597d706e	327	#endif
bogdanm	82:6473597d706e	328
bogdanm	82:6473597d706e	329	//! @brief Format value for bitfield DMA_CR_EMLM.
bogdanm	82:6473597d706e	330	#define BF_DMA_CR_EMLM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_EMLM), uint32_t) & BM_DMA_CR_EMLM)
bogdanm	82:6473597d706e	331
bogdanm	82:6473597d706e	332	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	333	//! @brief Set the EMLM field to a new value.
bogdanm	82:6473597d706e	334	#define BW_DMA_CR_EMLM(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_EMLM) = (v))
bogdanm	82:6473597d706e	335	#endif
bogdanm	82:6473597d706e	336	//@}
bogdanm	82:6473597d706e	337
bogdanm	82:6473597d706e	338	/*!
bogdanm	82:6473597d706e	339	* @name Register DMA_CR, field ECX[16] (RW)
bogdanm	82:6473597d706e	340	*
bogdanm	82:6473597d706e	341	* Values:
bogdanm	82:6473597d706e	342	* - 0 - Normal operation
bogdanm	82:6473597d706e	343	* - 1 - Cancel the remaining data transfer in the same fashion as the CX bit.
bogdanm	82:6473597d706e	344	* Stop the executing channel and force the minor loop to finish. The cancel
bogdanm	82:6473597d706e	345	* takes effect after the last write of the current read/write sequence. The
bogdanm	82:6473597d706e	346	* ECX bit clears itself after the cancel is honored. In addition to
bogdanm	82:6473597d706e	347	* cancelling the transfer, ECX treats the cancel as an error condition, thus updating
bogdanm	82:6473597d706e	348	* the Error Status register (DMAx_ES) and generating an optional error
bogdanm	82:6473597d706e	349	* interrupt.
bogdanm	82:6473597d706e	350	*/
bogdanm	82:6473597d706e	351	//@{
bogdanm	82:6473597d706e	352	#define BP_DMA_CR_ECX (16U) //!< Bit position for DMA_CR_ECX.
bogdanm	82:6473597d706e	353	#define BM_DMA_CR_ECX (0x00010000U) //!< Bit mask for DMA_CR_ECX.
bogdanm	82:6473597d706e	354	#define BS_DMA_CR_ECX (1U) //!< Bit field size in bits for DMA_CR_ECX.
bogdanm	82:6473597d706e	355
bogdanm	82:6473597d706e	356	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	357	//! @brief Read current value of the DMA_CR_ECX field.
bogdanm	82:6473597d706e	358	#define BR_DMA_CR_ECX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX))
bogdanm	82:6473597d706e	359	#endif
bogdanm	82:6473597d706e	360
bogdanm	82:6473597d706e	361	//! @brief Format value for bitfield DMA_CR_ECX.
bogdanm	82:6473597d706e	362	#define BF_DMA_CR_ECX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_ECX), uint32_t) & BM_DMA_CR_ECX)
bogdanm	82:6473597d706e	363
bogdanm	82:6473597d706e	364	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	365	//! @brief Set the ECX field to a new value.
bogdanm	82:6473597d706e	366	#define BW_DMA_CR_ECX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_ECX) = (v))
bogdanm	82:6473597d706e	367	#endif
bogdanm	82:6473597d706e	368	//@}
bogdanm	82:6473597d706e	369
bogdanm	82:6473597d706e	370	/*!
bogdanm	82:6473597d706e	371	* @name Register DMA_CR, field CX[17] (RW)
bogdanm	82:6473597d706e	372	*
bogdanm	82:6473597d706e	373	* Values:
bogdanm	82:6473597d706e	374	* - 0 - Normal operation
bogdanm	82:6473597d706e	375	* - 1 - Cancel the remaining data transfer. Stop the executing channel and
bogdanm	82:6473597d706e	376	* force the minor loop to finish. The cancel takes effect after the last write
bogdanm	82:6473597d706e	377	* of the current read/write sequence. The CX bit clears itself after the
bogdanm	82:6473597d706e	378	* cancel has been honored. This cancel retires the channel normally as if the
bogdanm	82:6473597d706e	379	* minor loop was completed.
bogdanm	82:6473597d706e	380	*/
bogdanm	82:6473597d706e	381	//@{
bogdanm	82:6473597d706e	382	#define BP_DMA_CR_CX (17U) //!< Bit position for DMA_CR_CX.
bogdanm	82:6473597d706e	383	#define BM_DMA_CR_CX (0x00020000U) //!< Bit mask for DMA_CR_CX.
bogdanm	82:6473597d706e	384	#define BS_DMA_CR_CX (1U) //!< Bit field size in bits for DMA_CR_CX.
bogdanm	82:6473597d706e	385
bogdanm	82:6473597d706e	386	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	387	//! @brief Read current value of the DMA_CR_CX field.
bogdanm	82:6473597d706e	388	#define BR_DMA_CR_CX(x) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX))
bogdanm	82:6473597d706e	389	#endif
bogdanm	82:6473597d706e	390
bogdanm	82:6473597d706e	391	//! @brief Format value for bitfield DMA_CR_CX.
bogdanm	82:6473597d706e	392	#define BF_DMA_CR_CX(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_CR_CX), uint32_t) & BM_DMA_CR_CX)
bogdanm	82:6473597d706e	393
bogdanm	82:6473597d706e	394	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	395	//! @brief Set the CX field to a new value.
bogdanm	82:6473597d706e	396	#define BW_DMA_CR_CX(x, v) (BITBAND_ACCESS32(HW_DMA_CR_ADDR(x), BP_DMA_CR_CX) = (v))
bogdanm	82:6473597d706e	397	#endif
bogdanm	82:6473597d706e	398	//@}
bogdanm	82:6473597d706e	399
bogdanm	82:6473597d706e	400	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	401	// HW_DMA_ES - Error Status Register
bogdanm	82:6473597d706e	402	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	403
bogdanm	82:6473597d706e	404	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	405	/*!
bogdanm	82:6473597d706e	406	* @brief HW_DMA_ES - Error Status Register (RO)
bogdanm	82:6473597d706e	407	*
bogdanm	82:6473597d706e	408	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	409	*
bogdanm	82:6473597d706e	410	* The ES provides information concerning the last recorded channel error.
bogdanm	82:6473597d706e	411	* Channel errors can be caused by: A configuration error, that is: An illegal setting
bogdanm	82:6473597d706e	412	* in the transfer-control descriptor, or An illegal priority register setting
bogdanm	82:6473597d706e	413	* in fixed-arbitration An error termination to a bus master read or write cycle
bogdanm	82:6473597d706e	414	* See the Error Reporting and Handling section for more details.
bogdanm	82:6473597d706e	415	*/
bogdanm	82:6473597d706e	416	typedef union _hw_dma_es
bogdanm	82:6473597d706e	417	{
bogdanm	82:6473597d706e	418	uint32_t U;
bogdanm	82:6473597d706e	419	struct _hw_dma_es_bitfields
bogdanm	82:6473597d706e	420	{
bogdanm	82:6473597d706e	421	uint32_t DBE : 1; //!< [0] Destination Bus Error
bogdanm	82:6473597d706e	422	uint32_t SBE : 1; //!< [1] Source Bus Error
bogdanm	82:6473597d706e	423	uint32_t SGE : 1; //!< [2] Scatter/Gather Configuration Error
bogdanm	82:6473597d706e	424	uint32_t NCE : 1; //!< [3] NBYTES/CITER Configuration Error
bogdanm	82:6473597d706e	425	uint32_t DOE : 1; //!< [4] Destination Offset Error
bogdanm	82:6473597d706e	426	uint32_t DAE : 1; //!< [5] Destination Address Error
bogdanm	82:6473597d706e	427	uint32_t SOE : 1; //!< [6] Source Offset Error
bogdanm	82:6473597d706e	428	uint32_t SAE : 1; //!< [7] Source Address Error
bogdanm	82:6473597d706e	429	uint32_t ERRCHN : 4; //!< [11:8] Error Channel Number or Canceled
bogdanm	82:6473597d706e	430	//! Channel Number
bogdanm	82:6473597d706e	431	uint32_t RESERVED0 : 2; //!< [13:12]
bogdanm	82:6473597d706e	432	uint32_t CPE : 1; //!< [14] Channel Priority Error
bogdanm	82:6473597d706e	433	uint32_t RESERVED1 : 1; //!< [15]
bogdanm	82:6473597d706e	434	uint32_t ECX : 1; //!< [16] Transfer Canceled
bogdanm	82:6473597d706e	435	uint32_t RESERVED2 : 14; //!< [30:17]
bogdanm	82:6473597d706e	436	uint32_t VLD : 1; //!< [31]
bogdanm	82:6473597d706e	437	} B;
bogdanm	82:6473597d706e	438	} hw_dma_es_t;
bogdanm	82:6473597d706e	439	#endif
bogdanm	82:6473597d706e	440
bogdanm	82:6473597d706e	441	/*!
bogdanm	82:6473597d706e	442	* @name Constants and macros for entire DMA_ES register
bogdanm	82:6473597d706e	443	*/
bogdanm	82:6473597d706e	444	//@{
bogdanm	82:6473597d706e	445	#define HW_DMA_ES_ADDR(x) (REGS_DMA_BASE(x) + 0x4U)
bogdanm	82:6473597d706e	446
bogdanm	82:6473597d706e	447	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	448	#define HW_DMA_ES(x) ((__I hw_dma_es_t ) HW_DMA_ES_ADDR(x))
bogdanm	82:6473597d706e	449	#define HW_DMA_ES_RD(x) (HW_DMA_ES(x).U)
bogdanm	82:6473597d706e	450	#endif
bogdanm	82:6473597d706e	451	//@}
bogdanm	82:6473597d706e	452
bogdanm	82:6473597d706e	453	/*
bogdanm	82:6473597d706e	454	* Constants & macros for individual DMA_ES bitfields
bogdanm	82:6473597d706e	455	*/
bogdanm	82:6473597d706e	456
bogdanm	82:6473597d706e	457	/*!
bogdanm	82:6473597d706e	458	* @name Register DMA_ES, field DBE[0] (RO)
bogdanm	82:6473597d706e	459	*
bogdanm	82:6473597d706e	460	* Values:
bogdanm	82:6473597d706e	461	* - 0 - No destination bus error
bogdanm	82:6473597d706e	462	* - 1 - The last recorded error was a bus error on a destination write
bogdanm	82:6473597d706e	463	*/
bogdanm	82:6473597d706e	464	//@{
bogdanm	82:6473597d706e	465	#define BP_DMA_ES_DBE (0U) //!< Bit position for DMA_ES_DBE.
bogdanm	82:6473597d706e	466	#define BM_DMA_ES_DBE (0x00000001U) //!< Bit mask for DMA_ES_DBE.
bogdanm	82:6473597d706e	467	#define BS_DMA_ES_DBE (1U) //!< Bit field size in bits for DMA_ES_DBE.
bogdanm	82:6473597d706e	468
bogdanm	82:6473597d706e	469	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	470	//! @brief Read current value of the DMA_ES_DBE field.
bogdanm	82:6473597d706e	471	#define BR_DMA_ES_DBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DBE))
bogdanm	82:6473597d706e	472	#endif
bogdanm	82:6473597d706e	473	//@}
bogdanm	82:6473597d706e	474
bogdanm	82:6473597d706e	475	/*!
bogdanm	82:6473597d706e	476	* @name Register DMA_ES, field SBE[1] (RO)
bogdanm	82:6473597d706e	477	*
bogdanm	82:6473597d706e	478	* Values:
bogdanm	82:6473597d706e	479	* - 0 - No source bus error
bogdanm	82:6473597d706e	480	* - 1 - The last recorded error was a bus error on a source read
bogdanm	82:6473597d706e	481	*/
bogdanm	82:6473597d706e	482	//@{
bogdanm	82:6473597d706e	483	#define BP_DMA_ES_SBE (1U) //!< Bit position for DMA_ES_SBE.
bogdanm	82:6473597d706e	484	#define BM_DMA_ES_SBE (0x00000002U) //!< Bit mask for DMA_ES_SBE.
bogdanm	82:6473597d706e	485	#define BS_DMA_ES_SBE (1U) //!< Bit field size in bits for DMA_ES_SBE.
bogdanm	82:6473597d706e	486
bogdanm	82:6473597d706e	487	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	488	//! @brief Read current value of the DMA_ES_SBE field.
bogdanm	82:6473597d706e	489	#define BR_DMA_ES_SBE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SBE))
bogdanm	82:6473597d706e	490	#endif
bogdanm	82:6473597d706e	491	//@}
bogdanm	82:6473597d706e	492
bogdanm	82:6473597d706e	493	/*!
bogdanm	82:6473597d706e	494	* @name Register DMA_ES, field SGE[2] (RO)
bogdanm	82:6473597d706e	495	*
bogdanm	82:6473597d706e	496	* Values:
bogdanm	82:6473597d706e	497	* - 0 - No scatter/gather configuration error
bogdanm	82:6473597d706e	498	* - 1 - The last recorded error was a configuration error detected in the
bogdanm	82:6473597d706e	499	* TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather
bogdanm	82:6473597d706e	500	* operation after major loop completion if TCDn_CSR[ESG] is enabled.
bogdanm	82:6473597d706e	501	* TCDn_DLASTSGA is not on a 32 byte boundary.
bogdanm	82:6473597d706e	502	*/
bogdanm	82:6473597d706e	503	//@{
bogdanm	82:6473597d706e	504	#define BP_DMA_ES_SGE (2U) //!< Bit position for DMA_ES_SGE.
bogdanm	82:6473597d706e	505	#define BM_DMA_ES_SGE (0x00000004U) //!< Bit mask for DMA_ES_SGE.
bogdanm	82:6473597d706e	506	#define BS_DMA_ES_SGE (1U) //!< Bit field size in bits for DMA_ES_SGE.
bogdanm	82:6473597d706e	507
bogdanm	82:6473597d706e	508	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	509	//! @brief Read current value of the DMA_ES_SGE field.
bogdanm	82:6473597d706e	510	#define BR_DMA_ES_SGE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SGE))
bogdanm	82:6473597d706e	511	#endif
bogdanm	82:6473597d706e	512	//@}
bogdanm	82:6473597d706e	513
bogdanm	82:6473597d706e	514	/*!
bogdanm	82:6473597d706e	515	* @name Register DMA_ES, field NCE[3] (RO)
bogdanm	82:6473597d706e	516	*
bogdanm	82:6473597d706e	517	* Values:
bogdanm	82:6473597d706e	518	* - 0 - No NBYTES/CITER configuration error
bogdanm	82:6473597d706e	519	* - 1 - The last recorded error was a configuration error detected in the
bogdanm	82:6473597d706e	520	* TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of
bogdanm	82:6473597d706e	521	* TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or
bogdanm	82:6473597d706e	522	* TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
bogdanm	82:6473597d706e	523	*/
bogdanm	82:6473597d706e	524	//@{
bogdanm	82:6473597d706e	525	#define BP_DMA_ES_NCE (3U) //!< Bit position for DMA_ES_NCE.
bogdanm	82:6473597d706e	526	#define BM_DMA_ES_NCE (0x00000008U) //!< Bit mask for DMA_ES_NCE.
bogdanm	82:6473597d706e	527	#define BS_DMA_ES_NCE (1U) //!< Bit field size in bits for DMA_ES_NCE.
bogdanm	82:6473597d706e	528
bogdanm	82:6473597d706e	529	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	530	//! @brief Read current value of the DMA_ES_NCE field.
bogdanm	82:6473597d706e	531	#define BR_DMA_ES_NCE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_NCE))
bogdanm	82:6473597d706e	532	#endif
bogdanm	82:6473597d706e	533	//@}
bogdanm	82:6473597d706e	534
bogdanm	82:6473597d706e	535	/*!
bogdanm	82:6473597d706e	536	* @name Register DMA_ES, field DOE[4] (RO)
bogdanm	82:6473597d706e	537	*
bogdanm	82:6473597d706e	538	* Values:
bogdanm	82:6473597d706e	539	* - 0 - No destination offset configuration error
bogdanm	82:6473597d706e	540	* - 1 - The last recorded error was a configuration error detected in the
bogdanm	82:6473597d706e	541	* TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
bogdanm	82:6473597d706e	542	*/
bogdanm	82:6473597d706e	543	//@{
bogdanm	82:6473597d706e	544	#define BP_DMA_ES_DOE (4U) //!< Bit position for DMA_ES_DOE.
bogdanm	82:6473597d706e	545	#define BM_DMA_ES_DOE (0x00000010U) //!< Bit mask for DMA_ES_DOE.
bogdanm	82:6473597d706e	546	#define BS_DMA_ES_DOE (1U) //!< Bit field size in bits for DMA_ES_DOE.
bogdanm	82:6473597d706e	547
bogdanm	82:6473597d706e	548	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	549	//! @brief Read current value of the DMA_ES_DOE field.
bogdanm	82:6473597d706e	550	#define BR_DMA_ES_DOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DOE))
bogdanm	82:6473597d706e	551	#endif
bogdanm	82:6473597d706e	552	//@}
bogdanm	82:6473597d706e	553
bogdanm	82:6473597d706e	554	/*!
bogdanm	82:6473597d706e	555	* @name Register DMA_ES, field DAE[5] (RO)
bogdanm	82:6473597d706e	556	*
bogdanm	82:6473597d706e	557	* Values:
bogdanm	82:6473597d706e	558	* - 0 - No destination address configuration error
bogdanm	82:6473597d706e	559	* - 1 - The last recorded error was a configuration error detected in the
bogdanm	82:6473597d706e	560	* TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
bogdanm	82:6473597d706e	561	*/
bogdanm	82:6473597d706e	562	//@{
bogdanm	82:6473597d706e	563	#define BP_DMA_ES_DAE (5U) //!< Bit position for DMA_ES_DAE.
bogdanm	82:6473597d706e	564	#define BM_DMA_ES_DAE (0x00000020U) //!< Bit mask for DMA_ES_DAE.
bogdanm	82:6473597d706e	565	#define BS_DMA_ES_DAE (1U) //!< Bit field size in bits for DMA_ES_DAE.
bogdanm	82:6473597d706e	566
bogdanm	82:6473597d706e	567	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	568	//! @brief Read current value of the DMA_ES_DAE field.
bogdanm	82:6473597d706e	569	#define BR_DMA_ES_DAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_DAE))
bogdanm	82:6473597d706e	570	#endif
bogdanm	82:6473597d706e	571	//@}
bogdanm	82:6473597d706e	572
bogdanm	82:6473597d706e	573	/*!
bogdanm	82:6473597d706e	574	* @name Register DMA_ES, field SOE[6] (RO)
bogdanm	82:6473597d706e	575	*
bogdanm	82:6473597d706e	576	* Values:
bogdanm	82:6473597d706e	577	* - 0 - No source offset configuration error
bogdanm	82:6473597d706e	578	* - 1 - The last recorded error was a configuration error detected in the
bogdanm	82:6473597d706e	579	* TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
bogdanm	82:6473597d706e	580	*/
bogdanm	82:6473597d706e	581	//@{
bogdanm	82:6473597d706e	582	#define BP_DMA_ES_SOE (6U) //!< Bit position for DMA_ES_SOE.
bogdanm	82:6473597d706e	583	#define BM_DMA_ES_SOE (0x00000040U) //!< Bit mask for DMA_ES_SOE.
bogdanm	82:6473597d706e	584	#define BS_DMA_ES_SOE (1U) //!< Bit field size in bits for DMA_ES_SOE.
bogdanm	82:6473597d706e	585
bogdanm	82:6473597d706e	586	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	587	//! @brief Read current value of the DMA_ES_SOE field.
bogdanm	82:6473597d706e	588	#define BR_DMA_ES_SOE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SOE))
bogdanm	82:6473597d706e	589	#endif
bogdanm	82:6473597d706e	590	//@}
bogdanm	82:6473597d706e	591
bogdanm	82:6473597d706e	592	/*!
bogdanm	82:6473597d706e	593	* @name Register DMA_ES, field SAE[7] (RO)
bogdanm	82:6473597d706e	594	*
bogdanm	82:6473597d706e	595	* Values:
bogdanm	82:6473597d706e	596	* - 0 - No source address configuration error.
bogdanm	82:6473597d706e	597	* - 1 - The last recorded error was a configuration error detected in the
bogdanm	82:6473597d706e	598	* TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
bogdanm	82:6473597d706e	599	*/
bogdanm	82:6473597d706e	600	//@{
bogdanm	82:6473597d706e	601	#define BP_DMA_ES_SAE (7U) //!< Bit position for DMA_ES_SAE.
bogdanm	82:6473597d706e	602	#define BM_DMA_ES_SAE (0x00000080U) //!< Bit mask for DMA_ES_SAE.
bogdanm	82:6473597d706e	603	#define BS_DMA_ES_SAE (1U) //!< Bit field size in bits for DMA_ES_SAE.
bogdanm	82:6473597d706e	604
bogdanm	82:6473597d706e	605	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	606	//! @brief Read current value of the DMA_ES_SAE field.
bogdanm	82:6473597d706e	607	#define BR_DMA_ES_SAE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_SAE))
bogdanm	82:6473597d706e	608	#endif
bogdanm	82:6473597d706e	609	//@}
bogdanm	82:6473597d706e	610
bogdanm	82:6473597d706e	611	/*!
bogdanm	82:6473597d706e	612	* @name Register DMA_ES, field ERRCHN[11:8] (RO)
bogdanm	82:6473597d706e	613	*
bogdanm	82:6473597d706e	614	* The channel number of the last recorded error (excluding CPE errors) or last
bogdanm	82:6473597d706e	615	* recorded error canceled transfer.
bogdanm	82:6473597d706e	616	*/
bogdanm	82:6473597d706e	617	//@{
bogdanm	82:6473597d706e	618	#define BP_DMA_ES_ERRCHN (8U) //!< Bit position for DMA_ES_ERRCHN.
bogdanm	82:6473597d706e	619	#define BM_DMA_ES_ERRCHN (0x00000F00U) //!< Bit mask for DMA_ES_ERRCHN.
bogdanm	82:6473597d706e	620	#define BS_DMA_ES_ERRCHN (4U) //!< Bit field size in bits for DMA_ES_ERRCHN.
bogdanm	82:6473597d706e	621
bogdanm	82:6473597d706e	622	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	623	//! @brief Read current value of the DMA_ES_ERRCHN field.
bogdanm	82:6473597d706e	624	#define BR_DMA_ES_ERRCHN(x) (HW_DMA_ES(x).B.ERRCHN)
bogdanm	82:6473597d706e	625	#endif
bogdanm	82:6473597d706e	626	//@}
bogdanm	82:6473597d706e	627
bogdanm	82:6473597d706e	628	/*!
bogdanm	82:6473597d706e	629	* @name Register DMA_ES, field CPE[14] (RO)
bogdanm	82:6473597d706e	630	*
bogdanm	82:6473597d706e	631	* Values:
bogdanm	82:6473597d706e	632	* - 0 - No channel priority error
bogdanm	82:6473597d706e	633	* - 1 - The last recorded error was a configuration error in the channel
bogdanm	82:6473597d706e	634	* priorities . Channel priorities are not unique.
bogdanm	82:6473597d706e	635	*/
bogdanm	82:6473597d706e	636	//@{
bogdanm	82:6473597d706e	637	#define BP_DMA_ES_CPE (14U) //!< Bit position for DMA_ES_CPE.
bogdanm	82:6473597d706e	638	#define BM_DMA_ES_CPE (0x00004000U) //!< Bit mask for DMA_ES_CPE.
bogdanm	82:6473597d706e	639	#define BS_DMA_ES_CPE (1U) //!< Bit field size in bits for DMA_ES_CPE.
bogdanm	82:6473597d706e	640
bogdanm	82:6473597d706e	641	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	642	//! @brief Read current value of the DMA_ES_CPE field.
bogdanm	82:6473597d706e	643	#define BR_DMA_ES_CPE(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_CPE))
bogdanm	82:6473597d706e	644	#endif
bogdanm	82:6473597d706e	645	//@}
bogdanm	82:6473597d706e	646
bogdanm	82:6473597d706e	647	/*!
bogdanm	82:6473597d706e	648	* @name Register DMA_ES, field ECX[16] (RO)
bogdanm	82:6473597d706e	649	*
bogdanm	82:6473597d706e	650	* Values:
bogdanm	82:6473597d706e	651	* - 0 - No canceled transfers
bogdanm	82:6473597d706e	652	* - 1 - The last recorded entry was a canceled transfer by the error cancel
bogdanm	82:6473597d706e	653	* transfer input
bogdanm	82:6473597d706e	654	*/
bogdanm	82:6473597d706e	655	//@{
bogdanm	82:6473597d706e	656	#define BP_DMA_ES_ECX (16U) //!< Bit position for DMA_ES_ECX.
bogdanm	82:6473597d706e	657	#define BM_DMA_ES_ECX (0x00010000U) //!< Bit mask for DMA_ES_ECX.
bogdanm	82:6473597d706e	658	#define BS_DMA_ES_ECX (1U) //!< Bit field size in bits for DMA_ES_ECX.
bogdanm	82:6473597d706e	659
bogdanm	82:6473597d706e	660	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	661	//! @brief Read current value of the DMA_ES_ECX field.
bogdanm	82:6473597d706e	662	#define BR_DMA_ES_ECX(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_ECX))
bogdanm	82:6473597d706e	663	#endif
bogdanm	82:6473597d706e	664	//@}
bogdanm	82:6473597d706e	665
bogdanm	82:6473597d706e	666	/*!
bogdanm	82:6473597d706e	667	* @name Register DMA_ES, field VLD[31] (RO)
bogdanm	82:6473597d706e	668	*
bogdanm	82:6473597d706e	669	* Logical OR of all ERR status bits
bogdanm	82:6473597d706e	670	*
bogdanm	82:6473597d706e	671	* Values:
bogdanm	82:6473597d706e	672	* - 0 - No ERR bits are set
bogdanm	82:6473597d706e	673	* - 1 - At least one ERR bit is set indicating a valid error exists that has
bogdanm	82:6473597d706e	674	* not been cleared
bogdanm	82:6473597d706e	675	*/
bogdanm	82:6473597d706e	676	//@{
bogdanm	82:6473597d706e	677	#define BP_DMA_ES_VLD (31U) //!< Bit position for DMA_ES_VLD.
bogdanm	82:6473597d706e	678	#define BM_DMA_ES_VLD (0x80000000U) //!< Bit mask for DMA_ES_VLD.
bogdanm	82:6473597d706e	679	#define BS_DMA_ES_VLD (1U) //!< Bit field size in bits for DMA_ES_VLD.
bogdanm	82:6473597d706e	680
bogdanm	82:6473597d706e	681	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	682	//! @brief Read current value of the DMA_ES_VLD field.
bogdanm	82:6473597d706e	683	#define BR_DMA_ES_VLD(x) (BITBAND_ACCESS32(HW_DMA_ES_ADDR(x), BP_DMA_ES_VLD))
bogdanm	82:6473597d706e	684	#endif
bogdanm	82:6473597d706e	685	//@}
bogdanm	82:6473597d706e	686
bogdanm	82:6473597d706e	687	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	688	// HW_DMA_ERQ - Enable Request Register
bogdanm	82:6473597d706e	689	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	690
bogdanm	82:6473597d706e	691	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	692	/*!
bogdanm	82:6473597d706e	693	* @brief HW_DMA_ERQ - Enable Request Register (RW)
bogdanm	82:6473597d706e	694	*
bogdanm	82:6473597d706e	695	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	696	*
bogdanm	82:6473597d706e	697	* The ERQ register provides a bit map for the 16 implemented channels to enable
bogdanm	82:6473597d706e	698	* the request signal for each channel. The state of any given channel enable is
bogdanm	82:6473597d706e	699	* directly affected by writes to this register; it is also affected by writes
bogdanm	82:6473597d706e	700	* to the SERQ and CERQ. The {S,C}ERQ registers are provided so the request enable
bogdanm	82:6473597d706e	701	* for a single channel can easily be modified without needing to perform a
bogdanm	82:6473597d706e	702	* read-modify-write sequence to the ERQ. DMA request input signals and this enable
bogdanm	82:6473597d706e	703	* request flag must be asserted before a channel's hardware service request is
bogdanm	82:6473597d706e	704	* accepted. The state of the DMA enable request flag does not affect a channel
bogdanm	82:6473597d706e	705	* service request made explicitly through software or a linked channel request.
bogdanm	82:6473597d706e	706	*/
bogdanm	82:6473597d706e	707	typedef union _hw_dma_erq
bogdanm	82:6473597d706e	708	{
bogdanm	82:6473597d706e	709	uint32_t U;
bogdanm	82:6473597d706e	710	struct _hw_dma_erq_bitfields
bogdanm	82:6473597d706e	711	{
bogdanm	82:6473597d706e	712	uint32_t ERQ0 : 1; //!< [0] Enable DMA Request 0
bogdanm	82:6473597d706e	713	uint32_t ERQ1 : 1; //!< [1] Enable DMA Request 1
bogdanm	82:6473597d706e	714	uint32_t ERQ2 : 1; //!< [2] Enable DMA Request 2
bogdanm	82:6473597d706e	715	uint32_t ERQ3 : 1; //!< [3] Enable DMA Request 3
bogdanm	82:6473597d706e	716	uint32_t ERQ4 : 1; //!< [4] Enable DMA Request 4
bogdanm	82:6473597d706e	717	uint32_t ERQ5 : 1; //!< [5] Enable DMA Request 5
bogdanm	82:6473597d706e	718	uint32_t ERQ6 : 1; //!< [6] Enable DMA Request 6
bogdanm	82:6473597d706e	719	uint32_t ERQ7 : 1; //!< [7] Enable DMA Request 7
bogdanm	82:6473597d706e	720	uint32_t ERQ8 : 1; //!< [8] Enable DMA Request 8
bogdanm	82:6473597d706e	721	uint32_t ERQ9 : 1; //!< [9] Enable DMA Request 9
bogdanm	82:6473597d706e	722	uint32_t ERQ10 : 1; //!< [10] Enable DMA Request 10
bogdanm	82:6473597d706e	723	uint32_t ERQ11 : 1; //!< [11] Enable DMA Request 11
bogdanm	82:6473597d706e	724	uint32_t ERQ12 : 1; //!< [12] Enable DMA Request 12
bogdanm	82:6473597d706e	725	uint32_t ERQ13 : 1; //!< [13] Enable DMA Request 13
bogdanm	82:6473597d706e	726	uint32_t ERQ14 : 1; //!< [14] Enable DMA Request 14
bogdanm	82:6473597d706e	727	uint32_t ERQ15 : 1; //!< [15] Enable DMA Request 15
bogdanm	82:6473597d706e	728	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	729	} B;
bogdanm	82:6473597d706e	730	} hw_dma_erq_t;
bogdanm	82:6473597d706e	731	#endif
bogdanm	82:6473597d706e	732
bogdanm	82:6473597d706e	733	/*!
bogdanm	82:6473597d706e	734	* @name Constants and macros for entire DMA_ERQ register
bogdanm	82:6473597d706e	735	*/
bogdanm	82:6473597d706e	736	//@{
bogdanm	82:6473597d706e	737	#define HW_DMA_ERQ_ADDR(x) (REGS_DMA_BASE(x) + 0xCU)
bogdanm	82:6473597d706e	738
bogdanm	82:6473597d706e	739	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	740	#define HW_DMA_ERQ(x) ((__IO hw_dma_erq_t ) HW_DMA_ERQ_ADDR(x))
bogdanm	82:6473597d706e	741	#define HW_DMA_ERQ_RD(x) (HW_DMA_ERQ(x).U)
bogdanm	82:6473597d706e	742	#define HW_DMA_ERQ_WR(x, v) (HW_DMA_ERQ(x).U = (v))
bogdanm	82:6473597d706e	743	#define HW_DMA_ERQ_SET(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) \| (v)))
bogdanm	82:6473597d706e	744	#define HW_DMA_ERQ_CLR(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) & ~(v)))
bogdanm	82:6473597d706e	745	#define HW_DMA_ERQ_TOG(x, v) (HW_DMA_ERQ_WR(x, HW_DMA_ERQ_RD(x) ^ (v)))
bogdanm	82:6473597d706e	746	#endif
bogdanm	82:6473597d706e	747	//@}
bogdanm	82:6473597d706e	748
bogdanm	82:6473597d706e	749	/*
bogdanm	82:6473597d706e	750	* Constants & macros for individual DMA_ERQ bitfields
bogdanm	82:6473597d706e	751	*/
bogdanm	82:6473597d706e	752
bogdanm	82:6473597d706e	753	/*!
bogdanm	82:6473597d706e	754	* @name Register DMA_ERQ, field ERQ0[0] (RW)
bogdanm	82:6473597d706e	755	*
bogdanm	82:6473597d706e	756	* Values:
bogdanm	82:6473597d706e	757	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	758	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	759	*/
bogdanm	82:6473597d706e	760	//@{
bogdanm	82:6473597d706e	761	#define BP_DMA_ERQ_ERQ0 (0U) //!< Bit position for DMA_ERQ_ERQ0.
bogdanm	82:6473597d706e	762	#define BM_DMA_ERQ_ERQ0 (0x00000001U) //!< Bit mask for DMA_ERQ_ERQ0.
bogdanm	82:6473597d706e	763	#define BS_DMA_ERQ_ERQ0 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ0.
bogdanm	82:6473597d706e	764
bogdanm	82:6473597d706e	765	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	766	//! @brief Read current value of the DMA_ERQ_ERQ0 field.
bogdanm	82:6473597d706e	767	#define BR_DMA_ERQ_ERQ0(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0))
bogdanm	82:6473597d706e	768	#endif
bogdanm	82:6473597d706e	769
bogdanm	82:6473597d706e	770	//! @brief Format value for bitfield DMA_ERQ_ERQ0.
bogdanm	82:6473597d706e	771	#define BF_DMA_ERQ_ERQ0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ0), uint32_t) & BM_DMA_ERQ_ERQ0)
bogdanm	82:6473597d706e	772
bogdanm	82:6473597d706e	773	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	774	//! @brief Set the ERQ0 field to a new value.
bogdanm	82:6473597d706e	775	#define BW_DMA_ERQ_ERQ0(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ0) = (v))
bogdanm	82:6473597d706e	776	#endif
bogdanm	82:6473597d706e	777	//@}
bogdanm	82:6473597d706e	778
bogdanm	82:6473597d706e	779	/*!
bogdanm	82:6473597d706e	780	* @name Register DMA_ERQ, field ERQ1[1] (RW)
bogdanm	82:6473597d706e	781	*
bogdanm	82:6473597d706e	782	* Values:
bogdanm	82:6473597d706e	783	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	784	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	785	*/
bogdanm	82:6473597d706e	786	//@{
bogdanm	82:6473597d706e	787	#define BP_DMA_ERQ_ERQ1 (1U) //!< Bit position for DMA_ERQ_ERQ1.
bogdanm	82:6473597d706e	788	#define BM_DMA_ERQ_ERQ1 (0x00000002U) //!< Bit mask for DMA_ERQ_ERQ1.
bogdanm	82:6473597d706e	789	#define BS_DMA_ERQ_ERQ1 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ1.
bogdanm	82:6473597d706e	790
bogdanm	82:6473597d706e	791	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	792	//! @brief Read current value of the DMA_ERQ_ERQ1 field.
bogdanm	82:6473597d706e	793	#define BR_DMA_ERQ_ERQ1(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1))
bogdanm	82:6473597d706e	794	#endif
bogdanm	82:6473597d706e	795
bogdanm	82:6473597d706e	796	//! @brief Format value for bitfield DMA_ERQ_ERQ1.
bogdanm	82:6473597d706e	797	#define BF_DMA_ERQ_ERQ1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ1), uint32_t) & BM_DMA_ERQ_ERQ1)
bogdanm	82:6473597d706e	798
bogdanm	82:6473597d706e	799	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	800	//! @brief Set the ERQ1 field to a new value.
bogdanm	82:6473597d706e	801	#define BW_DMA_ERQ_ERQ1(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ1) = (v))
bogdanm	82:6473597d706e	802	#endif
bogdanm	82:6473597d706e	803	//@}
bogdanm	82:6473597d706e	804
bogdanm	82:6473597d706e	805	/*!
bogdanm	82:6473597d706e	806	* @name Register DMA_ERQ, field ERQ2[2] (RW)
bogdanm	82:6473597d706e	807	*
bogdanm	82:6473597d706e	808	* Values:
bogdanm	82:6473597d706e	809	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	810	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	811	*/
bogdanm	82:6473597d706e	812	//@{
bogdanm	82:6473597d706e	813	#define BP_DMA_ERQ_ERQ2 (2U) //!< Bit position for DMA_ERQ_ERQ2.
bogdanm	82:6473597d706e	814	#define BM_DMA_ERQ_ERQ2 (0x00000004U) //!< Bit mask for DMA_ERQ_ERQ2.
bogdanm	82:6473597d706e	815	#define BS_DMA_ERQ_ERQ2 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ2.
bogdanm	82:6473597d706e	816
bogdanm	82:6473597d706e	817	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	818	//! @brief Read current value of the DMA_ERQ_ERQ2 field.
bogdanm	82:6473597d706e	819	#define BR_DMA_ERQ_ERQ2(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2))
bogdanm	82:6473597d706e	820	#endif
bogdanm	82:6473597d706e	821
bogdanm	82:6473597d706e	822	//! @brief Format value for bitfield DMA_ERQ_ERQ2.
bogdanm	82:6473597d706e	823	#define BF_DMA_ERQ_ERQ2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ2), uint32_t) & BM_DMA_ERQ_ERQ2)
bogdanm	82:6473597d706e	824
bogdanm	82:6473597d706e	825	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	826	//! @brief Set the ERQ2 field to a new value.
bogdanm	82:6473597d706e	827	#define BW_DMA_ERQ_ERQ2(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ2) = (v))
bogdanm	82:6473597d706e	828	#endif
bogdanm	82:6473597d706e	829	//@}
bogdanm	82:6473597d706e	830
bogdanm	82:6473597d706e	831	/*!
bogdanm	82:6473597d706e	832	* @name Register DMA_ERQ, field ERQ3[3] (RW)
bogdanm	82:6473597d706e	833	*
bogdanm	82:6473597d706e	834	* Values:
bogdanm	82:6473597d706e	835	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	836	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	837	*/
bogdanm	82:6473597d706e	838	//@{
bogdanm	82:6473597d706e	839	#define BP_DMA_ERQ_ERQ3 (3U) //!< Bit position for DMA_ERQ_ERQ3.
bogdanm	82:6473597d706e	840	#define BM_DMA_ERQ_ERQ3 (0x00000008U) //!< Bit mask for DMA_ERQ_ERQ3.
bogdanm	82:6473597d706e	841	#define BS_DMA_ERQ_ERQ3 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ3.
bogdanm	82:6473597d706e	842
bogdanm	82:6473597d706e	843	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	844	//! @brief Read current value of the DMA_ERQ_ERQ3 field.
bogdanm	82:6473597d706e	845	#define BR_DMA_ERQ_ERQ3(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3))
bogdanm	82:6473597d706e	846	#endif
bogdanm	82:6473597d706e	847
bogdanm	82:6473597d706e	848	//! @brief Format value for bitfield DMA_ERQ_ERQ3.
bogdanm	82:6473597d706e	849	#define BF_DMA_ERQ_ERQ3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ3), uint32_t) & BM_DMA_ERQ_ERQ3)
bogdanm	82:6473597d706e	850
bogdanm	82:6473597d706e	851	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	852	//! @brief Set the ERQ3 field to a new value.
bogdanm	82:6473597d706e	853	#define BW_DMA_ERQ_ERQ3(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ3) = (v))
bogdanm	82:6473597d706e	854	#endif
bogdanm	82:6473597d706e	855	//@}
bogdanm	82:6473597d706e	856
bogdanm	82:6473597d706e	857	/*!
bogdanm	82:6473597d706e	858	* @name Register DMA_ERQ, field ERQ4[4] (RW)
bogdanm	82:6473597d706e	859	*
bogdanm	82:6473597d706e	860	* Values:
bogdanm	82:6473597d706e	861	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	862	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	863	*/
bogdanm	82:6473597d706e	864	//@{
bogdanm	82:6473597d706e	865	#define BP_DMA_ERQ_ERQ4 (4U) //!< Bit position for DMA_ERQ_ERQ4.
bogdanm	82:6473597d706e	866	#define BM_DMA_ERQ_ERQ4 (0x00000010U) //!< Bit mask for DMA_ERQ_ERQ4.
bogdanm	82:6473597d706e	867	#define BS_DMA_ERQ_ERQ4 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ4.
bogdanm	82:6473597d706e	868
bogdanm	82:6473597d706e	869	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	870	//! @brief Read current value of the DMA_ERQ_ERQ4 field.
bogdanm	82:6473597d706e	871	#define BR_DMA_ERQ_ERQ4(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4))
bogdanm	82:6473597d706e	872	#endif
bogdanm	82:6473597d706e	873
bogdanm	82:6473597d706e	874	//! @brief Format value for bitfield DMA_ERQ_ERQ4.
bogdanm	82:6473597d706e	875	#define BF_DMA_ERQ_ERQ4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ4), uint32_t) & BM_DMA_ERQ_ERQ4)
bogdanm	82:6473597d706e	876
bogdanm	82:6473597d706e	877	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	878	//! @brief Set the ERQ4 field to a new value.
bogdanm	82:6473597d706e	879	#define BW_DMA_ERQ_ERQ4(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ4) = (v))
bogdanm	82:6473597d706e	880	#endif
bogdanm	82:6473597d706e	881	//@}
bogdanm	82:6473597d706e	882
bogdanm	82:6473597d706e	883	/*!
bogdanm	82:6473597d706e	884	* @name Register DMA_ERQ, field ERQ5[5] (RW)
bogdanm	82:6473597d706e	885	*
bogdanm	82:6473597d706e	886	* Values:
bogdanm	82:6473597d706e	887	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	888	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	889	*/
bogdanm	82:6473597d706e	890	//@{
bogdanm	82:6473597d706e	891	#define BP_DMA_ERQ_ERQ5 (5U) //!< Bit position for DMA_ERQ_ERQ5.
bogdanm	82:6473597d706e	892	#define BM_DMA_ERQ_ERQ5 (0x00000020U) //!< Bit mask for DMA_ERQ_ERQ5.
bogdanm	82:6473597d706e	893	#define BS_DMA_ERQ_ERQ5 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ5.
bogdanm	82:6473597d706e	894
bogdanm	82:6473597d706e	895	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	896	//! @brief Read current value of the DMA_ERQ_ERQ5 field.
bogdanm	82:6473597d706e	897	#define BR_DMA_ERQ_ERQ5(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5))
bogdanm	82:6473597d706e	898	#endif
bogdanm	82:6473597d706e	899
bogdanm	82:6473597d706e	900	//! @brief Format value for bitfield DMA_ERQ_ERQ5.
bogdanm	82:6473597d706e	901	#define BF_DMA_ERQ_ERQ5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ5), uint32_t) & BM_DMA_ERQ_ERQ5)
bogdanm	82:6473597d706e	902
bogdanm	82:6473597d706e	903	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	904	//! @brief Set the ERQ5 field to a new value.
bogdanm	82:6473597d706e	905	#define BW_DMA_ERQ_ERQ5(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ5) = (v))
bogdanm	82:6473597d706e	906	#endif
bogdanm	82:6473597d706e	907	//@}
bogdanm	82:6473597d706e	908
bogdanm	82:6473597d706e	909	/*!
bogdanm	82:6473597d706e	910	* @name Register DMA_ERQ, field ERQ6[6] (RW)
bogdanm	82:6473597d706e	911	*
bogdanm	82:6473597d706e	912	* Values:
bogdanm	82:6473597d706e	913	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	914	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	915	*/
bogdanm	82:6473597d706e	916	//@{
bogdanm	82:6473597d706e	917	#define BP_DMA_ERQ_ERQ6 (6U) //!< Bit position for DMA_ERQ_ERQ6.
bogdanm	82:6473597d706e	918	#define BM_DMA_ERQ_ERQ6 (0x00000040U) //!< Bit mask for DMA_ERQ_ERQ6.
bogdanm	82:6473597d706e	919	#define BS_DMA_ERQ_ERQ6 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ6.
bogdanm	82:6473597d706e	920
bogdanm	82:6473597d706e	921	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	922	//! @brief Read current value of the DMA_ERQ_ERQ6 field.
bogdanm	82:6473597d706e	923	#define BR_DMA_ERQ_ERQ6(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6))
bogdanm	82:6473597d706e	924	#endif
bogdanm	82:6473597d706e	925
bogdanm	82:6473597d706e	926	//! @brief Format value for bitfield DMA_ERQ_ERQ6.
bogdanm	82:6473597d706e	927	#define BF_DMA_ERQ_ERQ6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ6), uint32_t) & BM_DMA_ERQ_ERQ6)
bogdanm	82:6473597d706e	928
bogdanm	82:6473597d706e	929	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	930	//! @brief Set the ERQ6 field to a new value.
bogdanm	82:6473597d706e	931	#define BW_DMA_ERQ_ERQ6(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ6) = (v))
bogdanm	82:6473597d706e	932	#endif
bogdanm	82:6473597d706e	933	//@}
bogdanm	82:6473597d706e	934
bogdanm	82:6473597d706e	935	/*!
bogdanm	82:6473597d706e	936	* @name Register DMA_ERQ, field ERQ7[7] (RW)
bogdanm	82:6473597d706e	937	*
bogdanm	82:6473597d706e	938	* Values:
bogdanm	82:6473597d706e	939	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	940	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	941	*/
bogdanm	82:6473597d706e	942	//@{
bogdanm	82:6473597d706e	943	#define BP_DMA_ERQ_ERQ7 (7U) //!< Bit position for DMA_ERQ_ERQ7.
bogdanm	82:6473597d706e	944	#define BM_DMA_ERQ_ERQ7 (0x00000080U) //!< Bit mask for DMA_ERQ_ERQ7.
bogdanm	82:6473597d706e	945	#define BS_DMA_ERQ_ERQ7 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ7.
bogdanm	82:6473597d706e	946
bogdanm	82:6473597d706e	947	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	948	//! @brief Read current value of the DMA_ERQ_ERQ7 field.
bogdanm	82:6473597d706e	949	#define BR_DMA_ERQ_ERQ7(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7))
bogdanm	82:6473597d706e	950	#endif
bogdanm	82:6473597d706e	951
bogdanm	82:6473597d706e	952	//! @brief Format value for bitfield DMA_ERQ_ERQ7.
bogdanm	82:6473597d706e	953	#define BF_DMA_ERQ_ERQ7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ7), uint32_t) & BM_DMA_ERQ_ERQ7)
bogdanm	82:6473597d706e	954
bogdanm	82:6473597d706e	955	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	956	//! @brief Set the ERQ7 field to a new value.
bogdanm	82:6473597d706e	957	#define BW_DMA_ERQ_ERQ7(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ7) = (v))
bogdanm	82:6473597d706e	958	#endif
bogdanm	82:6473597d706e	959	//@}
bogdanm	82:6473597d706e	960
bogdanm	82:6473597d706e	961	/*!
bogdanm	82:6473597d706e	962	* @name Register DMA_ERQ, field ERQ8[8] (RW)
bogdanm	82:6473597d706e	963	*
bogdanm	82:6473597d706e	964	* Values:
bogdanm	82:6473597d706e	965	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	966	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	967	*/
bogdanm	82:6473597d706e	968	//@{
bogdanm	82:6473597d706e	969	#define BP_DMA_ERQ_ERQ8 (8U) //!< Bit position for DMA_ERQ_ERQ8.
bogdanm	82:6473597d706e	970	#define BM_DMA_ERQ_ERQ8 (0x00000100U) //!< Bit mask for DMA_ERQ_ERQ8.
bogdanm	82:6473597d706e	971	#define BS_DMA_ERQ_ERQ8 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ8.
bogdanm	82:6473597d706e	972
bogdanm	82:6473597d706e	973	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	974	//! @brief Read current value of the DMA_ERQ_ERQ8 field.
bogdanm	82:6473597d706e	975	#define BR_DMA_ERQ_ERQ8(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8))
bogdanm	82:6473597d706e	976	#endif
bogdanm	82:6473597d706e	977
bogdanm	82:6473597d706e	978	//! @brief Format value for bitfield DMA_ERQ_ERQ8.
bogdanm	82:6473597d706e	979	#define BF_DMA_ERQ_ERQ8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ8), uint32_t) & BM_DMA_ERQ_ERQ8)
bogdanm	82:6473597d706e	980
bogdanm	82:6473597d706e	981	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	982	//! @brief Set the ERQ8 field to a new value.
bogdanm	82:6473597d706e	983	#define BW_DMA_ERQ_ERQ8(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ8) = (v))
bogdanm	82:6473597d706e	984	#endif
bogdanm	82:6473597d706e	985	//@}
bogdanm	82:6473597d706e	986
bogdanm	82:6473597d706e	987	/*!
bogdanm	82:6473597d706e	988	* @name Register DMA_ERQ, field ERQ9[9] (RW)
bogdanm	82:6473597d706e	989	*
bogdanm	82:6473597d706e	990	* Values:
bogdanm	82:6473597d706e	991	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	992	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	993	*/
bogdanm	82:6473597d706e	994	//@{
bogdanm	82:6473597d706e	995	#define BP_DMA_ERQ_ERQ9 (9U) //!< Bit position for DMA_ERQ_ERQ9.
bogdanm	82:6473597d706e	996	#define BM_DMA_ERQ_ERQ9 (0x00000200U) //!< Bit mask for DMA_ERQ_ERQ9.
bogdanm	82:6473597d706e	997	#define BS_DMA_ERQ_ERQ9 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ9.
bogdanm	82:6473597d706e	998
bogdanm	82:6473597d706e	999	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1000	//! @brief Read current value of the DMA_ERQ_ERQ9 field.
bogdanm	82:6473597d706e	1001	#define BR_DMA_ERQ_ERQ9(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9))
bogdanm	82:6473597d706e	1002	#endif
bogdanm	82:6473597d706e	1003
bogdanm	82:6473597d706e	1004	//! @brief Format value for bitfield DMA_ERQ_ERQ9.
bogdanm	82:6473597d706e	1005	#define BF_DMA_ERQ_ERQ9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ9), uint32_t) & BM_DMA_ERQ_ERQ9)
bogdanm	82:6473597d706e	1006
bogdanm	82:6473597d706e	1007	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1008	//! @brief Set the ERQ9 field to a new value.
bogdanm	82:6473597d706e	1009	#define BW_DMA_ERQ_ERQ9(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ9) = (v))
bogdanm	82:6473597d706e	1010	#endif
bogdanm	82:6473597d706e	1011	//@}
bogdanm	82:6473597d706e	1012
bogdanm	82:6473597d706e	1013	/*!
bogdanm	82:6473597d706e	1014	* @name Register DMA_ERQ, field ERQ10[10] (RW)
bogdanm	82:6473597d706e	1015	*
bogdanm	82:6473597d706e	1016	* Values:
bogdanm	82:6473597d706e	1017	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	1018	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	1019	*/
bogdanm	82:6473597d706e	1020	//@{
bogdanm	82:6473597d706e	1021	#define BP_DMA_ERQ_ERQ10 (10U) //!< Bit position for DMA_ERQ_ERQ10.
bogdanm	82:6473597d706e	1022	#define BM_DMA_ERQ_ERQ10 (0x00000400U) //!< Bit mask for DMA_ERQ_ERQ10.
bogdanm	82:6473597d706e	1023	#define BS_DMA_ERQ_ERQ10 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ10.
bogdanm	82:6473597d706e	1024
bogdanm	82:6473597d706e	1025	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1026	//! @brief Read current value of the DMA_ERQ_ERQ10 field.
bogdanm	82:6473597d706e	1027	#define BR_DMA_ERQ_ERQ10(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10))
bogdanm	82:6473597d706e	1028	#endif
bogdanm	82:6473597d706e	1029
bogdanm	82:6473597d706e	1030	//! @brief Format value for bitfield DMA_ERQ_ERQ10.
bogdanm	82:6473597d706e	1031	#define BF_DMA_ERQ_ERQ10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ10), uint32_t) & BM_DMA_ERQ_ERQ10)
bogdanm	82:6473597d706e	1032
bogdanm	82:6473597d706e	1033	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1034	//! @brief Set the ERQ10 field to a new value.
bogdanm	82:6473597d706e	1035	#define BW_DMA_ERQ_ERQ10(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ10) = (v))
bogdanm	82:6473597d706e	1036	#endif
bogdanm	82:6473597d706e	1037	//@}
bogdanm	82:6473597d706e	1038
bogdanm	82:6473597d706e	1039	/*!
bogdanm	82:6473597d706e	1040	* @name Register DMA_ERQ, field ERQ11[11] (RW)
bogdanm	82:6473597d706e	1041	*
bogdanm	82:6473597d706e	1042	* Values:
bogdanm	82:6473597d706e	1043	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	1044	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	1045	*/
bogdanm	82:6473597d706e	1046	//@{
bogdanm	82:6473597d706e	1047	#define BP_DMA_ERQ_ERQ11 (11U) //!< Bit position for DMA_ERQ_ERQ11.
bogdanm	82:6473597d706e	1048	#define BM_DMA_ERQ_ERQ11 (0x00000800U) //!< Bit mask for DMA_ERQ_ERQ11.
bogdanm	82:6473597d706e	1049	#define BS_DMA_ERQ_ERQ11 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ11.
bogdanm	82:6473597d706e	1050
bogdanm	82:6473597d706e	1051	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1052	//! @brief Read current value of the DMA_ERQ_ERQ11 field.
bogdanm	82:6473597d706e	1053	#define BR_DMA_ERQ_ERQ11(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11))
bogdanm	82:6473597d706e	1054	#endif
bogdanm	82:6473597d706e	1055
bogdanm	82:6473597d706e	1056	//! @brief Format value for bitfield DMA_ERQ_ERQ11.
bogdanm	82:6473597d706e	1057	#define BF_DMA_ERQ_ERQ11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ11), uint32_t) & BM_DMA_ERQ_ERQ11)
bogdanm	82:6473597d706e	1058
bogdanm	82:6473597d706e	1059	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1060	//! @brief Set the ERQ11 field to a new value.
bogdanm	82:6473597d706e	1061	#define BW_DMA_ERQ_ERQ11(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ11) = (v))
bogdanm	82:6473597d706e	1062	#endif
bogdanm	82:6473597d706e	1063	//@}
bogdanm	82:6473597d706e	1064
bogdanm	82:6473597d706e	1065	/*!
bogdanm	82:6473597d706e	1066	* @name Register DMA_ERQ, field ERQ12[12] (RW)
bogdanm	82:6473597d706e	1067	*
bogdanm	82:6473597d706e	1068	* Values:
bogdanm	82:6473597d706e	1069	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	1070	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	1071	*/
bogdanm	82:6473597d706e	1072	//@{
bogdanm	82:6473597d706e	1073	#define BP_DMA_ERQ_ERQ12 (12U) //!< Bit position for DMA_ERQ_ERQ12.
bogdanm	82:6473597d706e	1074	#define BM_DMA_ERQ_ERQ12 (0x00001000U) //!< Bit mask for DMA_ERQ_ERQ12.
bogdanm	82:6473597d706e	1075	#define BS_DMA_ERQ_ERQ12 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ12.
bogdanm	82:6473597d706e	1076
bogdanm	82:6473597d706e	1077	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1078	//! @brief Read current value of the DMA_ERQ_ERQ12 field.
bogdanm	82:6473597d706e	1079	#define BR_DMA_ERQ_ERQ12(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12))
bogdanm	82:6473597d706e	1080	#endif
bogdanm	82:6473597d706e	1081
bogdanm	82:6473597d706e	1082	//! @brief Format value for bitfield DMA_ERQ_ERQ12.
bogdanm	82:6473597d706e	1083	#define BF_DMA_ERQ_ERQ12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ12), uint32_t) & BM_DMA_ERQ_ERQ12)
bogdanm	82:6473597d706e	1084
bogdanm	82:6473597d706e	1085	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1086	//! @brief Set the ERQ12 field to a new value.
bogdanm	82:6473597d706e	1087	#define BW_DMA_ERQ_ERQ12(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ12) = (v))
bogdanm	82:6473597d706e	1088	#endif
bogdanm	82:6473597d706e	1089	//@}
bogdanm	82:6473597d706e	1090
bogdanm	82:6473597d706e	1091	/*!
bogdanm	82:6473597d706e	1092	* @name Register DMA_ERQ, field ERQ13[13] (RW)
bogdanm	82:6473597d706e	1093	*
bogdanm	82:6473597d706e	1094	* Values:
bogdanm	82:6473597d706e	1095	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	1096	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	1097	*/
bogdanm	82:6473597d706e	1098	//@{
bogdanm	82:6473597d706e	1099	#define BP_DMA_ERQ_ERQ13 (13U) //!< Bit position for DMA_ERQ_ERQ13.
bogdanm	82:6473597d706e	1100	#define BM_DMA_ERQ_ERQ13 (0x00002000U) //!< Bit mask for DMA_ERQ_ERQ13.
bogdanm	82:6473597d706e	1101	#define BS_DMA_ERQ_ERQ13 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ13.
bogdanm	82:6473597d706e	1102
bogdanm	82:6473597d706e	1103	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1104	//! @brief Read current value of the DMA_ERQ_ERQ13 field.
bogdanm	82:6473597d706e	1105	#define BR_DMA_ERQ_ERQ13(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13))
bogdanm	82:6473597d706e	1106	#endif
bogdanm	82:6473597d706e	1107
bogdanm	82:6473597d706e	1108	//! @brief Format value for bitfield DMA_ERQ_ERQ13.
bogdanm	82:6473597d706e	1109	#define BF_DMA_ERQ_ERQ13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ13), uint32_t) & BM_DMA_ERQ_ERQ13)
bogdanm	82:6473597d706e	1110
bogdanm	82:6473597d706e	1111	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1112	//! @brief Set the ERQ13 field to a new value.
bogdanm	82:6473597d706e	1113	#define BW_DMA_ERQ_ERQ13(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ13) = (v))
bogdanm	82:6473597d706e	1114	#endif
bogdanm	82:6473597d706e	1115	//@}
bogdanm	82:6473597d706e	1116
bogdanm	82:6473597d706e	1117	/*!
bogdanm	82:6473597d706e	1118	* @name Register DMA_ERQ, field ERQ14[14] (RW)
bogdanm	82:6473597d706e	1119	*
bogdanm	82:6473597d706e	1120	* Values:
bogdanm	82:6473597d706e	1121	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	1122	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	1123	*/
bogdanm	82:6473597d706e	1124	//@{
bogdanm	82:6473597d706e	1125	#define BP_DMA_ERQ_ERQ14 (14U) //!< Bit position for DMA_ERQ_ERQ14.
bogdanm	82:6473597d706e	1126	#define BM_DMA_ERQ_ERQ14 (0x00004000U) //!< Bit mask for DMA_ERQ_ERQ14.
bogdanm	82:6473597d706e	1127	#define BS_DMA_ERQ_ERQ14 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ14.
bogdanm	82:6473597d706e	1128
bogdanm	82:6473597d706e	1129	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1130	//! @brief Read current value of the DMA_ERQ_ERQ14 field.
bogdanm	82:6473597d706e	1131	#define BR_DMA_ERQ_ERQ14(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14))
bogdanm	82:6473597d706e	1132	#endif
bogdanm	82:6473597d706e	1133
bogdanm	82:6473597d706e	1134	//! @brief Format value for bitfield DMA_ERQ_ERQ14.
bogdanm	82:6473597d706e	1135	#define BF_DMA_ERQ_ERQ14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ14), uint32_t) & BM_DMA_ERQ_ERQ14)
bogdanm	82:6473597d706e	1136
bogdanm	82:6473597d706e	1137	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1138	//! @brief Set the ERQ14 field to a new value.
bogdanm	82:6473597d706e	1139	#define BW_DMA_ERQ_ERQ14(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ14) = (v))
bogdanm	82:6473597d706e	1140	#endif
bogdanm	82:6473597d706e	1141	//@}
bogdanm	82:6473597d706e	1142
bogdanm	82:6473597d706e	1143	/*!
bogdanm	82:6473597d706e	1144	* @name Register DMA_ERQ, field ERQ15[15] (RW)
bogdanm	82:6473597d706e	1145	*
bogdanm	82:6473597d706e	1146	* Values:
bogdanm	82:6473597d706e	1147	* - 0 - The DMA request signal for the corresponding channel is disabled
bogdanm	82:6473597d706e	1148	* - 1 - The DMA request signal for the corresponding channel is enabled
bogdanm	82:6473597d706e	1149	*/
bogdanm	82:6473597d706e	1150	//@{
bogdanm	82:6473597d706e	1151	#define BP_DMA_ERQ_ERQ15 (15U) //!< Bit position for DMA_ERQ_ERQ15.
bogdanm	82:6473597d706e	1152	#define BM_DMA_ERQ_ERQ15 (0x00008000U) //!< Bit mask for DMA_ERQ_ERQ15.
bogdanm	82:6473597d706e	1153	#define BS_DMA_ERQ_ERQ15 (1U) //!< Bit field size in bits for DMA_ERQ_ERQ15.
bogdanm	82:6473597d706e	1154
bogdanm	82:6473597d706e	1155	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1156	//! @brief Read current value of the DMA_ERQ_ERQ15 field.
bogdanm	82:6473597d706e	1157	#define BR_DMA_ERQ_ERQ15(x) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15))
bogdanm	82:6473597d706e	1158	#endif
bogdanm	82:6473597d706e	1159
bogdanm	82:6473597d706e	1160	//! @brief Format value for bitfield DMA_ERQ_ERQ15.
bogdanm	82:6473597d706e	1161	#define BF_DMA_ERQ_ERQ15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERQ_ERQ15), uint32_t) & BM_DMA_ERQ_ERQ15)
bogdanm	82:6473597d706e	1162
bogdanm	82:6473597d706e	1163	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1164	//! @brief Set the ERQ15 field to a new value.
bogdanm	82:6473597d706e	1165	#define BW_DMA_ERQ_ERQ15(x, v) (BITBAND_ACCESS32(HW_DMA_ERQ_ADDR(x), BP_DMA_ERQ_ERQ15) = (v))
bogdanm	82:6473597d706e	1166	#endif
bogdanm	82:6473597d706e	1167	//@}
bogdanm	82:6473597d706e	1168
bogdanm	82:6473597d706e	1169	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1170	// HW_DMA_EEI - Enable Error Interrupt Register
bogdanm	82:6473597d706e	1171	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1172
bogdanm	82:6473597d706e	1173	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1174	/*!
bogdanm	82:6473597d706e	1175	* @brief HW_DMA_EEI - Enable Error Interrupt Register (RW)
bogdanm	82:6473597d706e	1176	*
bogdanm	82:6473597d706e	1177	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	1178	*
bogdanm	82:6473597d706e	1179	* The EEI register provides a bit map for the 16 channels to enable the error
bogdanm	82:6473597d706e	1180	* interrupt signal for each channel. The state of any given channel's error
bogdanm	82:6473597d706e	1181	* interrupt enable is directly affected by writes to this register; it is also
bogdanm	82:6473597d706e	1182	* affected by writes to the SEEI and CEEI. The {S,C}EEI are provided so the error
bogdanm	82:6473597d706e	1183	* interrupt enable for a single channel can easily be modified without the need to
bogdanm	82:6473597d706e	1184	* perform a read-modify-write sequence to the EEI register. The DMA error
bogdanm	82:6473597d706e	1185	* indicator and the error interrupt enable flag must be asserted before an error
bogdanm	82:6473597d706e	1186	* interrupt request for a given channel is asserted to the interrupt controller.
bogdanm	82:6473597d706e	1187	*/
bogdanm	82:6473597d706e	1188	typedef union _hw_dma_eei
bogdanm	82:6473597d706e	1189	{
bogdanm	82:6473597d706e	1190	uint32_t U;
bogdanm	82:6473597d706e	1191	struct _hw_dma_eei_bitfields
bogdanm	82:6473597d706e	1192	{
bogdanm	82:6473597d706e	1193	uint32_t EEI0 : 1; //!< [0] Enable Error Interrupt 0
bogdanm	82:6473597d706e	1194	uint32_t EEI1 : 1; //!< [1] Enable Error Interrupt 1
bogdanm	82:6473597d706e	1195	uint32_t EEI2 : 1; //!< [2] Enable Error Interrupt 2
bogdanm	82:6473597d706e	1196	uint32_t EEI3 : 1; //!< [3] Enable Error Interrupt 3
bogdanm	82:6473597d706e	1197	uint32_t EEI4 : 1; //!< [4] Enable Error Interrupt 4
bogdanm	82:6473597d706e	1198	uint32_t EEI5 : 1; //!< [5] Enable Error Interrupt 5
bogdanm	82:6473597d706e	1199	uint32_t EEI6 : 1; //!< [6] Enable Error Interrupt 6
bogdanm	82:6473597d706e	1200	uint32_t EEI7 : 1; //!< [7] Enable Error Interrupt 7
bogdanm	82:6473597d706e	1201	uint32_t EEI8 : 1; //!< [8] Enable Error Interrupt 8
bogdanm	82:6473597d706e	1202	uint32_t EEI9 : 1; //!< [9] Enable Error Interrupt 9
bogdanm	82:6473597d706e	1203	uint32_t EEI10 : 1; //!< [10] Enable Error Interrupt 10
bogdanm	82:6473597d706e	1204	uint32_t EEI11 : 1; //!< [11] Enable Error Interrupt 11
bogdanm	82:6473597d706e	1205	uint32_t EEI12 : 1; //!< [12] Enable Error Interrupt 12
bogdanm	82:6473597d706e	1206	uint32_t EEI13 : 1; //!< [13] Enable Error Interrupt 13
bogdanm	82:6473597d706e	1207	uint32_t EEI14 : 1; //!< [14] Enable Error Interrupt 14
bogdanm	82:6473597d706e	1208	uint32_t EEI15 : 1; //!< [15] Enable Error Interrupt 15
bogdanm	82:6473597d706e	1209	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	1210	} B;
bogdanm	82:6473597d706e	1211	} hw_dma_eei_t;
bogdanm	82:6473597d706e	1212	#endif
bogdanm	82:6473597d706e	1213
bogdanm	82:6473597d706e	1214	/*!
bogdanm	82:6473597d706e	1215	* @name Constants and macros for entire DMA_EEI register
bogdanm	82:6473597d706e	1216	*/
bogdanm	82:6473597d706e	1217	//@{
bogdanm	82:6473597d706e	1218	#define HW_DMA_EEI_ADDR(x) (REGS_DMA_BASE(x) + 0x14U)
bogdanm	82:6473597d706e	1219
bogdanm	82:6473597d706e	1220	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1221	#define HW_DMA_EEI(x) ((__IO hw_dma_eei_t ) HW_DMA_EEI_ADDR(x))
bogdanm	82:6473597d706e	1222	#define HW_DMA_EEI_RD(x) (HW_DMA_EEI(x).U)
bogdanm	82:6473597d706e	1223	#define HW_DMA_EEI_WR(x, v) (HW_DMA_EEI(x).U = (v))
bogdanm	82:6473597d706e	1224	#define HW_DMA_EEI_SET(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) \| (v)))
bogdanm	82:6473597d706e	1225	#define HW_DMA_EEI_CLR(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) & ~(v)))
bogdanm	82:6473597d706e	1226	#define HW_DMA_EEI_TOG(x, v) (HW_DMA_EEI_WR(x, HW_DMA_EEI_RD(x) ^ (v)))
bogdanm	82:6473597d706e	1227	#endif
bogdanm	82:6473597d706e	1228	//@}
bogdanm	82:6473597d706e	1229
bogdanm	82:6473597d706e	1230	/*
bogdanm	82:6473597d706e	1231	* Constants & macros for individual DMA_EEI bitfields
bogdanm	82:6473597d706e	1232	*/
bogdanm	82:6473597d706e	1233
bogdanm	82:6473597d706e	1234	/*!
bogdanm	82:6473597d706e	1235	* @name Register DMA_EEI, field EEI0[0] (RW)
bogdanm	82:6473597d706e	1236	*
bogdanm	82:6473597d706e	1237	* Values:
bogdanm	82:6473597d706e	1238	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1239	* interrupt
bogdanm	82:6473597d706e	1240	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1241	* an error interrupt request
bogdanm	82:6473597d706e	1242	*/
bogdanm	82:6473597d706e	1243	//@{
bogdanm	82:6473597d706e	1244	#define BP_DMA_EEI_EEI0 (0U) //!< Bit position for DMA_EEI_EEI0.
bogdanm	82:6473597d706e	1245	#define BM_DMA_EEI_EEI0 (0x00000001U) //!< Bit mask for DMA_EEI_EEI0.
bogdanm	82:6473597d706e	1246	#define BS_DMA_EEI_EEI0 (1U) //!< Bit field size in bits for DMA_EEI_EEI0.
bogdanm	82:6473597d706e	1247
bogdanm	82:6473597d706e	1248	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1249	//! @brief Read current value of the DMA_EEI_EEI0 field.
bogdanm	82:6473597d706e	1250	#define BR_DMA_EEI_EEI0(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0))
bogdanm	82:6473597d706e	1251	#endif
bogdanm	82:6473597d706e	1252
bogdanm	82:6473597d706e	1253	//! @brief Format value for bitfield DMA_EEI_EEI0.
bogdanm	82:6473597d706e	1254	#define BF_DMA_EEI_EEI0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI0), uint32_t) & BM_DMA_EEI_EEI0)
bogdanm	82:6473597d706e	1255
bogdanm	82:6473597d706e	1256	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1257	//! @brief Set the EEI0 field to a new value.
bogdanm	82:6473597d706e	1258	#define BW_DMA_EEI_EEI0(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI0) = (v))
bogdanm	82:6473597d706e	1259	#endif
bogdanm	82:6473597d706e	1260	//@}
bogdanm	82:6473597d706e	1261
bogdanm	82:6473597d706e	1262	/*!
bogdanm	82:6473597d706e	1263	* @name Register DMA_EEI, field EEI1[1] (RW)
bogdanm	82:6473597d706e	1264	*
bogdanm	82:6473597d706e	1265	* Values:
bogdanm	82:6473597d706e	1266	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1267	* interrupt
bogdanm	82:6473597d706e	1268	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1269	* an error interrupt request
bogdanm	82:6473597d706e	1270	*/
bogdanm	82:6473597d706e	1271	//@{
bogdanm	82:6473597d706e	1272	#define BP_DMA_EEI_EEI1 (1U) //!< Bit position for DMA_EEI_EEI1.
bogdanm	82:6473597d706e	1273	#define BM_DMA_EEI_EEI1 (0x00000002U) //!< Bit mask for DMA_EEI_EEI1.
bogdanm	82:6473597d706e	1274	#define BS_DMA_EEI_EEI1 (1U) //!< Bit field size in bits for DMA_EEI_EEI1.
bogdanm	82:6473597d706e	1275
bogdanm	82:6473597d706e	1276	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1277	//! @brief Read current value of the DMA_EEI_EEI1 field.
bogdanm	82:6473597d706e	1278	#define BR_DMA_EEI_EEI1(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1))
bogdanm	82:6473597d706e	1279	#endif
bogdanm	82:6473597d706e	1280
bogdanm	82:6473597d706e	1281	//! @brief Format value for bitfield DMA_EEI_EEI1.
bogdanm	82:6473597d706e	1282	#define BF_DMA_EEI_EEI1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI1), uint32_t) & BM_DMA_EEI_EEI1)
bogdanm	82:6473597d706e	1283
bogdanm	82:6473597d706e	1284	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1285	//! @brief Set the EEI1 field to a new value.
bogdanm	82:6473597d706e	1286	#define BW_DMA_EEI_EEI1(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI1) = (v))
bogdanm	82:6473597d706e	1287	#endif
bogdanm	82:6473597d706e	1288	//@}
bogdanm	82:6473597d706e	1289
bogdanm	82:6473597d706e	1290	/*!
bogdanm	82:6473597d706e	1291	* @name Register DMA_EEI, field EEI2[2] (RW)
bogdanm	82:6473597d706e	1292	*
bogdanm	82:6473597d706e	1293	* Values:
bogdanm	82:6473597d706e	1294	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1295	* interrupt
bogdanm	82:6473597d706e	1296	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1297	* an error interrupt request
bogdanm	82:6473597d706e	1298	*/
bogdanm	82:6473597d706e	1299	//@{
bogdanm	82:6473597d706e	1300	#define BP_DMA_EEI_EEI2 (2U) //!< Bit position for DMA_EEI_EEI2.
bogdanm	82:6473597d706e	1301	#define BM_DMA_EEI_EEI2 (0x00000004U) //!< Bit mask for DMA_EEI_EEI2.
bogdanm	82:6473597d706e	1302	#define BS_DMA_EEI_EEI2 (1U) //!< Bit field size in bits for DMA_EEI_EEI2.
bogdanm	82:6473597d706e	1303
bogdanm	82:6473597d706e	1304	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1305	//! @brief Read current value of the DMA_EEI_EEI2 field.
bogdanm	82:6473597d706e	1306	#define BR_DMA_EEI_EEI2(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2))
bogdanm	82:6473597d706e	1307	#endif
bogdanm	82:6473597d706e	1308
bogdanm	82:6473597d706e	1309	//! @brief Format value for bitfield DMA_EEI_EEI2.
bogdanm	82:6473597d706e	1310	#define BF_DMA_EEI_EEI2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI2), uint32_t) & BM_DMA_EEI_EEI2)
bogdanm	82:6473597d706e	1311
bogdanm	82:6473597d706e	1312	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1313	//! @brief Set the EEI2 field to a new value.
bogdanm	82:6473597d706e	1314	#define BW_DMA_EEI_EEI2(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI2) = (v))
bogdanm	82:6473597d706e	1315	#endif
bogdanm	82:6473597d706e	1316	//@}
bogdanm	82:6473597d706e	1317
bogdanm	82:6473597d706e	1318	/*!
bogdanm	82:6473597d706e	1319	* @name Register DMA_EEI, field EEI3[3] (RW)
bogdanm	82:6473597d706e	1320	*
bogdanm	82:6473597d706e	1321	* Values:
bogdanm	82:6473597d706e	1322	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1323	* interrupt
bogdanm	82:6473597d706e	1324	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1325	* an error interrupt request
bogdanm	82:6473597d706e	1326	*/
bogdanm	82:6473597d706e	1327	//@{
bogdanm	82:6473597d706e	1328	#define BP_DMA_EEI_EEI3 (3U) //!< Bit position for DMA_EEI_EEI3.
bogdanm	82:6473597d706e	1329	#define BM_DMA_EEI_EEI3 (0x00000008U) //!< Bit mask for DMA_EEI_EEI3.
bogdanm	82:6473597d706e	1330	#define BS_DMA_EEI_EEI3 (1U) //!< Bit field size in bits for DMA_EEI_EEI3.
bogdanm	82:6473597d706e	1331
bogdanm	82:6473597d706e	1332	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1333	//! @brief Read current value of the DMA_EEI_EEI3 field.
bogdanm	82:6473597d706e	1334	#define BR_DMA_EEI_EEI3(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3))
bogdanm	82:6473597d706e	1335	#endif
bogdanm	82:6473597d706e	1336
bogdanm	82:6473597d706e	1337	//! @brief Format value for bitfield DMA_EEI_EEI3.
bogdanm	82:6473597d706e	1338	#define BF_DMA_EEI_EEI3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI3), uint32_t) & BM_DMA_EEI_EEI3)
bogdanm	82:6473597d706e	1339
bogdanm	82:6473597d706e	1340	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1341	//! @brief Set the EEI3 field to a new value.
bogdanm	82:6473597d706e	1342	#define BW_DMA_EEI_EEI3(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI3) = (v))
bogdanm	82:6473597d706e	1343	#endif
bogdanm	82:6473597d706e	1344	//@}
bogdanm	82:6473597d706e	1345
bogdanm	82:6473597d706e	1346	/*!
bogdanm	82:6473597d706e	1347	* @name Register DMA_EEI, field EEI4[4] (RW)
bogdanm	82:6473597d706e	1348	*
bogdanm	82:6473597d706e	1349	* Values:
bogdanm	82:6473597d706e	1350	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1351	* interrupt
bogdanm	82:6473597d706e	1352	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1353	* an error interrupt request
bogdanm	82:6473597d706e	1354	*/
bogdanm	82:6473597d706e	1355	//@{
bogdanm	82:6473597d706e	1356	#define BP_DMA_EEI_EEI4 (4U) //!< Bit position for DMA_EEI_EEI4.
bogdanm	82:6473597d706e	1357	#define BM_DMA_EEI_EEI4 (0x00000010U) //!< Bit mask for DMA_EEI_EEI4.
bogdanm	82:6473597d706e	1358	#define BS_DMA_EEI_EEI4 (1U) //!< Bit field size in bits for DMA_EEI_EEI4.
bogdanm	82:6473597d706e	1359
bogdanm	82:6473597d706e	1360	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1361	//! @brief Read current value of the DMA_EEI_EEI4 field.
bogdanm	82:6473597d706e	1362	#define BR_DMA_EEI_EEI4(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4))
bogdanm	82:6473597d706e	1363	#endif
bogdanm	82:6473597d706e	1364
bogdanm	82:6473597d706e	1365	//! @brief Format value for bitfield DMA_EEI_EEI4.
bogdanm	82:6473597d706e	1366	#define BF_DMA_EEI_EEI4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI4), uint32_t) & BM_DMA_EEI_EEI4)
bogdanm	82:6473597d706e	1367
bogdanm	82:6473597d706e	1368	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1369	//! @brief Set the EEI4 field to a new value.
bogdanm	82:6473597d706e	1370	#define BW_DMA_EEI_EEI4(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI4) = (v))
bogdanm	82:6473597d706e	1371	#endif
bogdanm	82:6473597d706e	1372	//@}
bogdanm	82:6473597d706e	1373
bogdanm	82:6473597d706e	1374	/*!
bogdanm	82:6473597d706e	1375	* @name Register DMA_EEI, field EEI5[5] (RW)
bogdanm	82:6473597d706e	1376	*
bogdanm	82:6473597d706e	1377	* Values:
bogdanm	82:6473597d706e	1378	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1379	* interrupt
bogdanm	82:6473597d706e	1380	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1381	* an error interrupt request
bogdanm	82:6473597d706e	1382	*/
bogdanm	82:6473597d706e	1383	//@{
bogdanm	82:6473597d706e	1384	#define BP_DMA_EEI_EEI5 (5U) //!< Bit position for DMA_EEI_EEI5.
bogdanm	82:6473597d706e	1385	#define BM_DMA_EEI_EEI5 (0x00000020U) //!< Bit mask for DMA_EEI_EEI5.
bogdanm	82:6473597d706e	1386	#define BS_DMA_EEI_EEI5 (1U) //!< Bit field size in bits for DMA_EEI_EEI5.
bogdanm	82:6473597d706e	1387
bogdanm	82:6473597d706e	1388	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1389	//! @brief Read current value of the DMA_EEI_EEI5 field.
bogdanm	82:6473597d706e	1390	#define BR_DMA_EEI_EEI5(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5))
bogdanm	82:6473597d706e	1391	#endif
bogdanm	82:6473597d706e	1392
bogdanm	82:6473597d706e	1393	//! @brief Format value for bitfield DMA_EEI_EEI5.
bogdanm	82:6473597d706e	1394	#define BF_DMA_EEI_EEI5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI5), uint32_t) & BM_DMA_EEI_EEI5)
bogdanm	82:6473597d706e	1395
bogdanm	82:6473597d706e	1396	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1397	//! @brief Set the EEI5 field to a new value.
bogdanm	82:6473597d706e	1398	#define BW_DMA_EEI_EEI5(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI5) = (v))
bogdanm	82:6473597d706e	1399	#endif
bogdanm	82:6473597d706e	1400	//@}
bogdanm	82:6473597d706e	1401
bogdanm	82:6473597d706e	1402	/*!
bogdanm	82:6473597d706e	1403	* @name Register DMA_EEI, field EEI6[6] (RW)
bogdanm	82:6473597d706e	1404	*
bogdanm	82:6473597d706e	1405	* Values:
bogdanm	82:6473597d706e	1406	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1407	* interrupt
bogdanm	82:6473597d706e	1408	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1409	* an error interrupt request
bogdanm	82:6473597d706e	1410	*/
bogdanm	82:6473597d706e	1411	//@{
bogdanm	82:6473597d706e	1412	#define BP_DMA_EEI_EEI6 (6U) //!< Bit position for DMA_EEI_EEI6.
bogdanm	82:6473597d706e	1413	#define BM_DMA_EEI_EEI6 (0x00000040U) //!< Bit mask for DMA_EEI_EEI6.
bogdanm	82:6473597d706e	1414	#define BS_DMA_EEI_EEI6 (1U) //!< Bit field size in bits for DMA_EEI_EEI6.
bogdanm	82:6473597d706e	1415
bogdanm	82:6473597d706e	1416	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1417	//! @brief Read current value of the DMA_EEI_EEI6 field.
bogdanm	82:6473597d706e	1418	#define BR_DMA_EEI_EEI6(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6))
bogdanm	82:6473597d706e	1419	#endif
bogdanm	82:6473597d706e	1420
bogdanm	82:6473597d706e	1421	//! @brief Format value for bitfield DMA_EEI_EEI6.
bogdanm	82:6473597d706e	1422	#define BF_DMA_EEI_EEI6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI6), uint32_t) & BM_DMA_EEI_EEI6)
bogdanm	82:6473597d706e	1423
bogdanm	82:6473597d706e	1424	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1425	//! @brief Set the EEI6 field to a new value.
bogdanm	82:6473597d706e	1426	#define BW_DMA_EEI_EEI6(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI6) = (v))
bogdanm	82:6473597d706e	1427	#endif
bogdanm	82:6473597d706e	1428	//@}
bogdanm	82:6473597d706e	1429
bogdanm	82:6473597d706e	1430	/*!
bogdanm	82:6473597d706e	1431	* @name Register DMA_EEI, field EEI7[7] (RW)
bogdanm	82:6473597d706e	1432	*
bogdanm	82:6473597d706e	1433	* Values:
bogdanm	82:6473597d706e	1434	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1435	* interrupt
bogdanm	82:6473597d706e	1436	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1437	* an error interrupt request
bogdanm	82:6473597d706e	1438	*/
bogdanm	82:6473597d706e	1439	//@{
bogdanm	82:6473597d706e	1440	#define BP_DMA_EEI_EEI7 (7U) //!< Bit position for DMA_EEI_EEI7.
bogdanm	82:6473597d706e	1441	#define BM_DMA_EEI_EEI7 (0x00000080U) //!< Bit mask for DMA_EEI_EEI7.
bogdanm	82:6473597d706e	1442	#define BS_DMA_EEI_EEI7 (1U) //!< Bit field size in bits for DMA_EEI_EEI7.
bogdanm	82:6473597d706e	1443
bogdanm	82:6473597d706e	1444	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1445	//! @brief Read current value of the DMA_EEI_EEI7 field.
bogdanm	82:6473597d706e	1446	#define BR_DMA_EEI_EEI7(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7))
bogdanm	82:6473597d706e	1447	#endif
bogdanm	82:6473597d706e	1448
bogdanm	82:6473597d706e	1449	//! @brief Format value for bitfield DMA_EEI_EEI7.
bogdanm	82:6473597d706e	1450	#define BF_DMA_EEI_EEI7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI7), uint32_t) & BM_DMA_EEI_EEI7)
bogdanm	82:6473597d706e	1451
bogdanm	82:6473597d706e	1452	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1453	//! @brief Set the EEI7 field to a new value.
bogdanm	82:6473597d706e	1454	#define BW_DMA_EEI_EEI7(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI7) = (v))
bogdanm	82:6473597d706e	1455	#endif
bogdanm	82:6473597d706e	1456	//@}
bogdanm	82:6473597d706e	1457
bogdanm	82:6473597d706e	1458	/*!
bogdanm	82:6473597d706e	1459	* @name Register DMA_EEI, field EEI8[8] (RW)
bogdanm	82:6473597d706e	1460	*
bogdanm	82:6473597d706e	1461	* Values:
bogdanm	82:6473597d706e	1462	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1463	* interrupt
bogdanm	82:6473597d706e	1464	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1465	* an error interrupt request
bogdanm	82:6473597d706e	1466	*/
bogdanm	82:6473597d706e	1467	//@{
bogdanm	82:6473597d706e	1468	#define BP_DMA_EEI_EEI8 (8U) //!< Bit position for DMA_EEI_EEI8.
bogdanm	82:6473597d706e	1469	#define BM_DMA_EEI_EEI8 (0x00000100U) //!< Bit mask for DMA_EEI_EEI8.
bogdanm	82:6473597d706e	1470	#define BS_DMA_EEI_EEI8 (1U) //!< Bit field size in bits for DMA_EEI_EEI8.
bogdanm	82:6473597d706e	1471
bogdanm	82:6473597d706e	1472	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1473	//! @brief Read current value of the DMA_EEI_EEI8 field.
bogdanm	82:6473597d706e	1474	#define BR_DMA_EEI_EEI8(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8))
bogdanm	82:6473597d706e	1475	#endif
bogdanm	82:6473597d706e	1476
bogdanm	82:6473597d706e	1477	//! @brief Format value for bitfield DMA_EEI_EEI8.
bogdanm	82:6473597d706e	1478	#define BF_DMA_EEI_EEI8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI8), uint32_t) & BM_DMA_EEI_EEI8)
bogdanm	82:6473597d706e	1479
bogdanm	82:6473597d706e	1480	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1481	//! @brief Set the EEI8 field to a new value.
bogdanm	82:6473597d706e	1482	#define BW_DMA_EEI_EEI8(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI8) = (v))
bogdanm	82:6473597d706e	1483	#endif
bogdanm	82:6473597d706e	1484	//@}
bogdanm	82:6473597d706e	1485
bogdanm	82:6473597d706e	1486	/*!
bogdanm	82:6473597d706e	1487	* @name Register DMA_EEI, field EEI9[9] (RW)
bogdanm	82:6473597d706e	1488	*
bogdanm	82:6473597d706e	1489	* Values:
bogdanm	82:6473597d706e	1490	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1491	* interrupt
bogdanm	82:6473597d706e	1492	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1493	* an error interrupt request
bogdanm	82:6473597d706e	1494	*/
bogdanm	82:6473597d706e	1495	//@{
bogdanm	82:6473597d706e	1496	#define BP_DMA_EEI_EEI9 (9U) //!< Bit position for DMA_EEI_EEI9.
bogdanm	82:6473597d706e	1497	#define BM_DMA_EEI_EEI9 (0x00000200U) //!< Bit mask for DMA_EEI_EEI9.
bogdanm	82:6473597d706e	1498	#define BS_DMA_EEI_EEI9 (1U) //!< Bit field size in bits for DMA_EEI_EEI9.
bogdanm	82:6473597d706e	1499
bogdanm	82:6473597d706e	1500	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1501	//! @brief Read current value of the DMA_EEI_EEI9 field.
bogdanm	82:6473597d706e	1502	#define BR_DMA_EEI_EEI9(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9))
bogdanm	82:6473597d706e	1503	#endif
bogdanm	82:6473597d706e	1504
bogdanm	82:6473597d706e	1505	//! @brief Format value for bitfield DMA_EEI_EEI9.
bogdanm	82:6473597d706e	1506	#define BF_DMA_EEI_EEI9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI9), uint32_t) & BM_DMA_EEI_EEI9)
bogdanm	82:6473597d706e	1507
bogdanm	82:6473597d706e	1508	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1509	//! @brief Set the EEI9 field to a new value.
bogdanm	82:6473597d706e	1510	#define BW_DMA_EEI_EEI9(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI9) = (v))
bogdanm	82:6473597d706e	1511	#endif
bogdanm	82:6473597d706e	1512	//@}
bogdanm	82:6473597d706e	1513
bogdanm	82:6473597d706e	1514	/*!
bogdanm	82:6473597d706e	1515	* @name Register DMA_EEI, field EEI10[10] (RW)
bogdanm	82:6473597d706e	1516	*
bogdanm	82:6473597d706e	1517	* Values:
bogdanm	82:6473597d706e	1518	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1519	* interrupt
bogdanm	82:6473597d706e	1520	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1521	* an error interrupt request
bogdanm	82:6473597d706e	1522	*/
bogdanm	82:6473597d706e	1523	//@{
bogdanm	82:6473597d706e	1524	#define BP_DMA_EEI_EEI10 (10U) //!< Bit position for DMA_EEI_EEI10.
bogdanm	82:6473597d706e	1525	#define BM_DMA_EEI_EEI10 (0x00000400U) //!< Bit mask for DMA_EEI_EEI10.
bogdanm	82:6473597d706e	1526	#define BS_DMA_EEI_EEI10 (1U) //!< Bit field size in bits for DMA_EEI_EEI10.
bogdanm	82:6473597d706e	1527
bogdanm	82:6473597d706e	1528	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1529	//! @brief Read current value of the DMA_EEI_EEI10 field.
bogdanm	82:6473597d706e	1530	#define BR_DMA_EEI_EEI10(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10))
bogdanm	82:6473597d706e	1531	#endif
bogdanm	82:6473597d706e	1532
bogdanm	82:6473597d706e	1533	//! @brief Format value for bitfield DMA_EEI_EEI10.
bogdanm	82:6473597d706e	1534	#define BF_DMA_EEI_EEI10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI10), uint32_t) & BM_DMA_EEI_EEI10)
bogdanm	82:6473597d706e	1535
bogdanm	82:6473597d706e	1536	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1537	//! @brief Set the EEI10 field to a new value.
bogdanm	82:6473597d706e	1538	#define BW_DMA_EEI_EEI10(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI10) = (v))
bogdanm	82:6473597d706e	1539	#endif
bogdanm	82:6473597d706e	1540	//@}
bogdanm	82:6473597d706e	1541
bogdanm	82:6473597d706e	1542	/*!
bogdanm	82:6473597d706e	1543	* @name Register DMA_EEI, field EEI11[11] (RW)
bogdanm	82:6473597d706e	1544	*
bogdanm	82:6473597d706e	1545	* Values:
bogdanm	82:6473597d706e	1546	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1547	* interrupt
bogdanm	82:6473597d706e	1548	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1549	* an error interrupt request
bogdanm	82:6473597d706e	1550	*/
bogdanm	82:6473597d706e	1551	//@{
bogdanm	82:6473597d706e	1552	#define BP_DMA_EEI_EEI11 (11U) //!< Bit position for DMA_EEI_EEI11.
bogdanm	82:6473597d706e	1553	#define BM_DMA_EEI_EEI11 (0x00000800U) //!< Bit mask for DMA_EEI_EEI11.
bogdanm	82:6473597d706e	1554	#define BS_DMA_EEI_EEI11 (1U) //!< Bit field size in bits for DMA_EEI_EEI11.
bogdanm	82:6473597d706e	1555
bogdanm	82:6473597d706e	1556	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1557	//! @brief Read current value of the DMA_EEI_EEI11 field.
bogdanm	82:6473597d706e	1558	#define BR_DMA_EEI_EEI11(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11))
bogdanm	82:6473597d706e	1559	#endif
bogdanm	82:6473597d706e	1560
bogdanm	82:6473597d706e	1561	//! @brief Format value for bitfield DMA_EEI_EEI11.
bogdanm	82:6473597d706e	1562	#define BF_DMA_EEI_EEI11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI11), uint32_t) & BM_DMA_EEI_EEI11)
bogdanm	82:6473597d706e	1563
bogdanm	82:6473597d706e	1564	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1565	//! @brief Set the EEI11 field to a new value.
bogdanm	82:6473597d706e	1566	#define BW_DMA_EEI_EEI11(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI11) = (v))
bogdanm	82:6473597d706e	1567	#endif
bogdanm	82:6473597d706e	1568	//@}
bogdanm	82:6473597d706e	1569
bogdanm	82:6473597d706e	1570	/*!
bogdanm	82:6473597d706e	1571	* @name Register DMA_EEI, field EEI12[12] (RW)
bogdanm	82:6473597d706e	1572	*
bogdanm	82:6473597d706e	1573	* Values:
bogdanm	82:6473597d706e	1574	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1575	* interrupt
bogdanm	82:6473597d706e	1576	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1577	* an error interrupt request
bogdanm	82:6473597d706e	1578	*/
bogdanm	82:6473597d706e	1579	//@{
bogdanm	82:6473597d706e	1580	#define BP_DMA_EEI_EEI12 (12U) //!< Bit position for DMA_EEI_EEI12.
bogdanm	82:6473597d706e	1581	#define BM_DMA_EEI_EEI12 (0x00001000U) //!< Bit mask for DMA_EEI_EEI12.
bogdanm	82:6473597d706e	1582	#define BS_DMA_EEI_EEI12 (1U) //!< Bit field size in bits for DMA_EEI_EEI12.
bogdanm	82:6473597d706e	1583
bogdanm	82:6473597d706e	1584	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1585	//! @brief Read current value of the DMA_EEI_EEI12 field.
bogdanm	82:6473597d706e	1586	#define BR_DMA_EEI_EEI12(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12))
bogdanm	82:6473597d706e	1587	#endif
bogdanm	82:6473597d706e	1588
bogdanm	82:6473597d706e	1589	//! @brief Format value for bitfield DMA_EEI_EEI12.
bogdanm	82:6473597d706e	1590	#define BF_DMA_EEI_EEI12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI12), uint32_t) & BM_DMA_EEI_EEI12)
bogdanm	82:6473597d706e	1591
bogdanm	82:6473597d706e	1592	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1593	//! @brief Set the EEI12 field to a new value.
bogdanm	82:6473597d706e	1594	#define BW_DMA_EEI_EEI12(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI12) = (v))
bogdanm	82:6473597d706e	1595	#endif
bogdanm	82:6473597d706e	1596	//@}
bogdanm	82:6473597d706e	1597
bogdanm	82:6473597d706e	1598	/*!
bogdanm	82:6473597d706e	1599	* @name Register DMA_EEI, field EEI13[13] (RW)
bogdanm	82:6473597d706e	1600	*
bogdanm	82:6473597d706e	1601	* Values:
bogdanm	82:6473597d706e	1602	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1603	* interrupt
bogdanm	82:6473597d706e	1604	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1605	* an error interrupt request
bogdanm	82:6473597d706e	1606	*/
bogdanm	82:6473597d706e	1607	//@{
bogdanm	82:6473597d706e	1608	#define BP_DMA_EEI_EEI13 (13U) //!< Bit position for DMA_EEI_EEI13.
bogdanm	82:6473597d706e	1609	#define BM_DMA_EEI_EEI13 (0x00002000U) //!< Bit mask for DMA_EEI_EEI13.
bogdanm	82:6473597d706e	1610	#define BS_DMA_EEI_EEI13 (1U) //!< Bit field size in bits for DMA_EEI_EEI13.
bogdanm	82:6473597d706e	1611
bogdanm	82:6473597d706e	1612	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1613	//! @brief Read current value of the DMA_EEI_EEI13 field.
bogdanm	82:6473597d706e	1614	#define BR_DMA_EEI_EEI13(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13))
bogdanm	82:6473597d706e	1615	#endif
bogdanm	82:6473597d706e	1616
bogdanm	82:6473597d706e	1617	//! @brief Format value for bitfield DMA_EEI_EEI13.
bogdanm	82:6473597d706e	1618	#define BF_DMA_EEI_EEI13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI13), uint32_t) & BM_DMA_EEI_EEI13)
bogdanm	82:6473597d706e	1619
bogdanm	82:6473597d706e	1620	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1621	//! @brief Set the EEI13 field to a new value.
bogdanm	82:6473597d706e	1622	#define BW_DMA_EEI_EEI13(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI13) = (v))
bogdanm	82:6473597d706e	1623	#endif
bogdanm	82:6473597d706e	1624	//@}
bogdanm	82:6473597d706e	1625
bogdanm	82:6473597d706e	1626	/*!
bogdanm	82:6473597d706e	1627	* @name Register DMA_EEI, field EEI14[14] (RW)
bogdanm	82:6473597d706e	1628	*
bogdanm	82:6473597d706e	1629	* Values:
bogdanm	82:6473597d706e	1630	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1631	* interrupt
bogdanm	82:6473597d706e	1632	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1633	* an error interrupt request
bogdanm	82:6473597d706e	1634	*/
bogdanm	82:6473597d706e	1635	//@{
bogdanm	82:6473597d706e	1636	#define BP_DMA_EEI_EEI14 (14U) //!< Bit position for DMA_EEI_EEI14.
bogdanm	82:6473597d706e	1637	#define BM_DMA_EEI_EEI14 (0x00004000U) //!< Bit mask for DMA_EEI_EEI14.
bogdanm	82:6473597d706e	1638	#define BS_DMA_EEI_EEI14 (1U) //!< Bit field size in bits for DMA_EEI_EEI14.
bogdanm	82:6473597d706e	1639
bogdanm	82:6473597d706e	1640	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1641	//! @brief Read current value of the DMA_EEI_EEI14 field.
bogdanm	82:6473597d706e	1642	#define BR_DMA_EEI_EEI14(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14))
bogdanm	82:6473597d706e	1643	#endif
bogdanm	82:6473597d706e	1644
bogdanm	82:6473597d706e	1645	//! @brief Format value for bitfield DMA_EEI_EEI14.
bogdanm	82:6473597d706e	1646	#define BF_DMA_EEI_EEI14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI14), uint32_t) & BM_DMA_EEI_EEI14)
bogdanm	82:6473597d706e	1647
bogdanm	82:6473597d706e	1648	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1649	//! @brief Set the EEI14 field to a new value.
bogdanm	82:6473597d706e	1650	#define BW_DMA_EEI_EEI14(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI14) = (v))
bogdanm	82:6473597d706e	1651	#endif
bogdanm	82:6473597d706e	1652	//@}
bogdanm	82:6473597d706e	1653
bogdanm	82:6473597d706e	1654	/*!
bogdanm	82:6473597d706e	1655	* @name Register DMA_EEI, field EEI15[15] (RW)
bogdanm	82:6473597d706e	1656	*
bogdanm	82:6473597d706e	1657	* Values:
bogdanm	82:6473597d706e	1658	* - 0 - The error signal for corresponding channel does not generate an error
bogdanm	82:6473597d706e	1659	* interrupt
bogdanm	82:6473597d706e	1660	* - 1 - The assertion of the error signal for corresponding channel generates
bogdanm	82:6473597d706e	1661	* an error interrupt request
bogdanm	82:6473597d706e	1662	*/
bogdanm	82:6473597d706e	1663	//@{
bogdanm	82:6473597d706e	1664	#define BP_DMA_EEI_EEI15 (15U) //!< Bit position for DMA_EEI_EEI15.
bogdanm	82:6473597d706e	1665	#define BM_DMA_EEI_EEI15 (0x00008000U) //!< Bit mask for DMA_EEI_EEI15.
bogdanm	82:6473597d706e	1666	#define BS_DMA_EEI_EEI15 (1U) //!< Bit field size in bits for DMA_EEI_EEI15.
bogdanm	82:6473597d706e	1667
bogdanm	82:6473597d706e	1668	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1669	//! @brief Read current value of the DMA_EEI_EEI15 field.
bogdanm	82:6473597d706e	1670	#define BR_DMA_EEI_EEI15(x) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15))
bogdanm	82:6473597d706e	1671	#endif
bogdanm	82:6473597d706e	1672
bogdanm	82:6473597d706e	1673	//! @brief Format value for bitfield DMA_EEI_EEI15.
bogdanm	82:6473597d706e	1674	#define BF_DMA_EEI_EEI15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_EEI_EEI15), uint32_t) & BM_DMA_EEI_EEI15)
bogdanm	82:6473597d706e	1675
bogdanm	82:6473597d706e	1676	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1677	//! @brief Set the EEI15 field to a new value.
bogdanm	82:6473597d706e	1678	#define BW_DMA_EEI_EEI15(x, v) (BITBAND_ACCESS32(HW_DMA_EEI_ADDR(x), BP_DMA_EEI_EEI15) = (v))
bogdanm	82:6473597d706e	1679	#endif
bogdanm	82:6473597d706e	1680	//@}
bogdanm	82:6473597d706e	1681
bogdanm	82:6473597d706e	1682	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1683	// HW_DMA_CEEI - Clear Enable Error Interrupt Register
bogdanm	82:6473597d706e	1684	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1685
bogdanm	82:6473597d706e	1686	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1687	/*!
bogdanm	82:6473597d706e	1688	* @brief HW_DMA_CEEI - Clear Enable Error Interrupt Register (WO)
bogdanm	82:6473597d706e	1689	*
bogdanm	82:6473597d706e	1690	* Reset value: 0x00U
bogdanm	82:6473597d706e	1691	*
bogdanm	82:6473597d706e	1692	* The CEEI provides a simple memory-mapped mechanism to clear a given bit in
bogdanm	82:6473597d706e	1693	* the EEI to disable the error interrupt for a given channel. The data value on a
bogdanm	82:6473597d706e	1694	* register write causes the corresponding bit in the EEI to be cleared. Setting
bogdanm	82:6473597d706e	1695	* the CAEE bit provides a global clear function, forcing the EEI contents to be
bogdanm	82:6473597d706e	1696	* cleared, disabling all DMA request inputs. If the NOP bit is set, the command
bogdanm	82:6473597d706e	1697	* is ignored. This allows you to write multiple-byte registers as a 32-bit word.
bogdanm	82:6473597d706e	1698	* Reads of this register return all zeroes.
bogdanm	82:6473597d706e	1699	*/
bogdanm	82:6473597d706e	1700	typedef union _hw_dma_ceei
bogdanm	82:6473597d706e	1701	{
bogdanm	82:6473597d706e	1702	uint8_t U;
bogdanm	82:6473597d706e	1703	struct _hw_dma_ceei_bitfields
bogdanm	82:6473597d706e	1704	{
bogdanm	82:6473597d706e	1705	uint8_t CEEI : 4; //!< [3:0] Clear Enable Error Interrupt
bogdanm	82:6473597d706e	1706	uint8_t RESERVED0 : 2; //!< [5:4]
bogdanm	82:6473597d706e	1707	uint8_t CAEE : 1; //!< [6] Clear All Enable Error Interrupts
bogdanm	82:6473597d706e	1708	uint8_t NOP : 1; //!< [7] No Op enable
bogdanm	82:6473597d706e	1709	} B;
bogdanm	82:6473597d706e	1710	} hw_dma_ceei_t;
bogdanm	82:6473597d706e	1711	#endif
bogdanm	82:6473597d706e	1712
bogdanm	82:6473597d706e	1713	/*!
bogdanm	82:6473597d706e	1714	* @name Constants and macros for entire DMA_CEEI register
bogdanm	82:6473597d706e	1715	*/
bogdanm	82:6473597d706e	1716	//@{
bogdanm	82:6473597d706e	1717	#define HW_DMA_CEEI_ADDR(x) (REGS_DMA_BASE(x) + 0x18U)
bogdanm	82:6473597d706e	1718
bogdanm	82:6473597d706e	1719	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1720	#define HW_DMA_CEEI(x) ((__O hw_dma_ceei_t ) HW_DMA_CEEI_ADDR(x))
bogdanm	82:6473597d706e	1721	#define HW_DMA_CEEI_RD(x) (HW_DMA_CEEI(x).U)
bogdanm	82:6473597d706e	1722	#define HW_DMA_CEEI_WR(x, v) (HW_DMA_CEEI(x).U = (v))
bogdanm	82:6473597d706e	1723	#endif
bogdanm	82:6473597d706e	1724	//@}
bogdanm	82:6473597d706e	1725
bogdanm	82:6473597d706e	1726	/*
bogdanm	82:6473597d706e	1727	* Constants & macros for individual DMA_CEEI bitfields
bogdanm	82:6473597d706e	1728	*/
bogdanm	82:6473597d706e	1729
bogdanm	82:6473597d706e	1730	/*!
bogdanm	82:6473597d706e	1731	* @name Register DMA_CEEI, field CEEI[3:0] (WORZ)
bogdanm	82:6473597d706e	1732	*
bogdanm	82:6473597d706e	1733	* Clears the corresponding bit in EEI
bogdanm	82:6473597d706e	1734	*/
bogdanm	82:6473597d706e	1735	//@{
bogdanm	82:6473597d706e	1736	#define BP_DMA_CEEI_CEEI (0U) //!< Bit position for DMA_CEEI_CEEI.
bogdanm	82:6473597d706e	1737	#define BM_DMA_CEEI_CEEI (0x0FU) //!< Bit mask for DMA_CEEI_CEEI.
bogdanm	82:6473597d706e	1738	#define BS_DMA_CEEI_CEEI (4U) //!< Bit field size in bits for DMA_CEEI_CEEI.
bogdanm	82:6473597d706e	1739
bogdanm	82:6473597d706e	1740	//! @brief Format value for bitfield DMA_CEEI_CEEI.
bogdanm	82:6473597d706e	1741	#define BF_DMA_CEEI_CEEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_CEEI), uint8_t) & BM_DMA_CEEI_CEEI)
bogdanm	82:6473597d706e	1742
bogdanm	82:6473597d706e	1743	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1744	//! @brief Set the CEEI field to a new value.
bogdanm	82:6473597d706e	1745	#define BW_DMA_CEEI_CEEI(x, v) (HW_DMA_CEEI_WR(x, (HW_DMA_CEEI_RD(x) & ~BM_DMA_CEEI_CEEI) \| BF_DMA_CEEI_CEEI(v)))
bogdanm	82:6473597d706e	1746	#endif
bogdanm	82:6473597d706e	1747	//@}
bogdanm	82:6473597d706e	1748
bogdanm	82:6473597d706e	1749	/*!
bogdanm	82:6473597d706e	1750	* @name Register DMA_CEEI, field CAEE[6] (WORZ)
bogdanm	82:6473597d706e	1751	*
bogdanm	82:6473597d706e	1752	* Values:
bogdanm	82:6473597d706e	1753	* - 0 - Clear only the EEI bit specified in the CEEI field
bogdanm	82:6473597d706e	1754	* - 1 - Clear all bits in EEI
bogdanm	82:6473597d706e	1755	*/
bogdanm	82:6473597d706e	1756	//@{
bogdanm	82:6473597d706e	1757	#define BP_DMA_CEEI_CAEE (6U) //!< Bit position for DMA_CEEI_CAEE.
bogdanm	82:6473597d706e	1758	#define BM_DMA_CEEI_CAEE (0x40U) //!< Bit mask for DMA_CEEI_CAEE.
bogdanm	82:6473597d706e	1759	#define BS_DMA_CEEI_CAEE (1U) //!< Bit field size in bits for DMA_CEEI_CAEE.
bogdanm	82:6473597d706e	1760
bogdanm	82:6473597d706e	1761	//! @brief Format value for bitfield DMA_CEEI_CAEE.
bogdanm	82:6473597d706e	1762	#define BF_DMA_CEEI_CAEE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_CAEE), uint8_t) & BM_DMA_CEEI_CAEE)
bogdanm	82:6473597d706e	1763
bogdanm	82:6473597d706e	1764	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1765	//! @brief Set the CAEE field to a new value.
bogdanm	82:6473597d706e	1766	#define BW_DMA_CEEI_CAEE(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_CAEE) = (v))
bogdanm	82:6473597d706e	1767	#endif
bogdanm	82:6473597d706e	1768	//@}
bogdanm	82:6473597d706e	1769
bogdanm	82:6473597d706e	1770	/*!
bogdanm	82:6473597d706e	1771	* @name Register DMA_CEEI, field NOP[7] (WORZ)
bogdanm	82:6473597d706e	1772	*
bogdanm	82:6473597d706e	1773	* Values:
bogdanm	82:6473597d706e	1774	* - 0 - Normal operation
bogdanm	82:6473597d706e	1775	* - 1 - No operation, ignore the other bits in this register
bogdanm	82:6473597d706e	1776	*/
bogdanm	82:6473597d706e	1777	//@{
bogdanm	82:6473597d706e	1778	#define BP_DMA_CEEI_NOP (7U) //!< Bit position for DMA_CEEI_NOP.
bogdanm	82:6473597d706e	1779	#define BM_DMA_CEEI_NOP (0x80U) //!< Bit mask for DMA_CEEI_NOP.
bogdanm	82:6473597d706e	1780	#define BS_DMA_CEEI_NOP (1U) //!< Bit field size in bits for DMA_CEEI_NOP.
bogdanm	82:6473597d706e	1781
bogdanm	82:6473597d706e	1782	//! @brief Format value for bitfield DMA_CEEI_NOP.
bogdanm	82:6473597d706e	1783	#define BF_DMA_CEEI_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CEEI_NOP), uint8_t) & BM_DMA_CEEI_NOP)
bogdanm	82:6473597d706e	1784
bogdanm	82:6473597d706e	1785	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1786	//! @brief Set the NOP field to a new value.
bogdanm	82:6473597d706e	1787	#define BW_DMA_CEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CEEI_ADDR(x), BP_DMA_CEEI_NOP) = (v))
bogdanm	82:6473597d706e	1788	#endif
bogdanm	82:6473597d706e	1789	//@}
bogdanm	82:6473597d706e	1790
bogdanm	82:6473597d706e	1791	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1792	// HW_DMA_SEEI - Set Enable Error Interrupt Register
bogdanm	82:6473597d706e	1793	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1794
bogdanm	82:6473597d706e	1795	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1796	/*!
bogdanm	82:6473597d706e	1797	* @brief HW_DMA_SEEI - Set Enable Error Interrupt Register (WO)
bogdanm	82:6473597d706e	1798	*
bogdanm	82:6473597d706e	1799	* Reset value: 0x00U
bogdanm	82:6473597d706e	1800	*
bogdanm	82:6473597d706e	1801	* The SEEI provides a simple memory-mapped mechanism to set a given bit in the
bogdanm	82:6473597d706e	1802	* EEI to enable the error interrupt for a given channel. The data value on a
bogdanm	82:6473597d706e	1803	* register write causes the corresponding bit in the EEI to be set. Setting the
bogdanm	82:6473597d706e	1804	* SAEE bit provides a global set function, forcing the entire EEI contents to be
bogdanm	82:6473597d706e	1805	* set. If the NOP bit is set, the command is ignored. This allows you to write
bogdanm	82:6473597d706e	1806	* multiple-byte registers as a 32-bit word. Reads of this register return all
bogdanm	82:6473597d706e	1807	* zeroes.
bogdanm	82:6473597d706e	1808	*/
bogdanm	82:6473597d706e	1809	typedef union _hw_dma_seei
bogdanm	82:6473597d706e	1810	{
bogdanm	82:6473597d706e	1811	uint8_t U;
bogdanm	82:6473597d706e	1812	struct _hw_dma_seei_bitfields
bogdanm	82:6473597d706e	1813	{
bogdanm	82:6473597d706e	1814	uint8_t SEEI : 4; //!< [3:0] Set Enable Error Interrupt
bogdanm	82:6473597d706e	1815	uint8_t RESERVED0 : 2; //!< [5:4]
bogdanm	82:6473597d706e	1816	uint8_t SAEE : 1; //!< [6] Sets All Enable Error Interrupts
bogdanm	82:6473597d706e	1817	uint8_t NOP : 1; //!< [7] No Op enable
bogdanm	82:6473597d706e	1818	} B;
bogdanm	82:6473597d706e	1819	} hw_dma_seei_t;
bogdanm	82:6473597d706e	1820	#endif
bogdanm	82:6473597d706e	1821
bogdanm	82:6473597d706e	1822	/*!
bogdanm	82:6473597d706e	1823	* @name Constants and macros for entire DMA_SEEI register
bogdanm	82:6473597d706e	1824	*/
bogdanm	82:6473597d706e	1825	//@{
bogdanm	82:6473597d706e	1826	#define HW_DMA_SEEI_ADDR(x) (REGS_DMA_BASE(x) + 0x19U)
bogdanm	82:6473597d706e	1827
bogdanm	82:6473597d706e	1828	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1829	#define HW_DMA_SEEI(x) ((__O hw_dma_seei_t ) HW_DMA_SEEI_ADDR(x))
bogdanm	82:6473597d706e	1830	#define HW_DMA_SEEI_RD(x) (HW_DMA_SEEI(x).U)
bogdanm	82:6473597d706e	1831	#define HW_DMA_SEEI_WR(x, v) (HW_DMA_SEEI(x).U = (v))
bogdanm	82:6473597d706e	1832	#endif
bogdanm	82:6473597d706e	1833	//@}
bogdanm	82:6473597d706e	1834
bogdanm	82:6473597d706e	1835	/*
bogdanm	82:6473597d706e	1836	* Constants & macros for individual DMA_SEEI bitfields
bogdanm	82:6473597d706e	1837	*/
bogdanm	82:6473597d706e	1838
bogdanm	82:6473597d706e	1839	/*!
bogdanm	82:6473597d706e	1840	* @name Register DMA_SEEI, field SEEI[3:0] (WORZ)
bogdanm	82:6473597d706e	1841	*
bogdanm	82:6473597d706e	1842	* Sets the corresponding bit in EEI
bogdanm	82:6473597d706e	1843	*/
bogdanm	82:6473597d706e	1844	//@{
bogdanm	82:6473597d706e	1845	#define BP_DMA_SEEI_SEEI (0U) //!< Bit position for DMA_SEEI_SEEI.
bogdanm	82:6473597d706e	1846	#define BM_DMA_SEEI_SEEI (0x0FU) //!< Bit mask for DMA_SEEI_SEEI.
bogdanm	82:6473597d706e	1847	#define BS_DMA_SEEI_SEEI (4U) //!< Bit field size in bits for DMA_SEEI_SEEI.
bogdanm	82:6473597d706e	1848
bogdanm	82:6473597d706e	1849	//! @brief Format value for bitfield DMA_SEEI_SEEI.
bogdanm	82:6473597d706e	1850	#define BF_DMA_SEEI_SEEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_SEEI), uint8_t) & BM_DMA_SEEI_SEEI)
bogdanm	82:6473597d706e	1851
bogdanm	82:6473597d706e	1852	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1853	//! @brief Set the SEEI field to a new value.
bogdanm	82:6473597d706e	1854	#define BW_DMA_SEEI_SEEI(x, v) (HW_DMA_SEEI_WR(x, (HW_DMA_SEEI_RD(x) & ~BM_DMA_SEEI_SEEI) \| BF_DMA_SEEI_SEEI(v)))
bogdanm	82:6473597d706e	1855	#endif
bogdanm	82:6473597d706e	1856	//@}
bogdanm	82:6473597d706e	1857
bogdanm	82:6473597d706e	1858	/*!
bogdanm	82:6473597d706e	1859	* @name Register DMA_SEEI, field SAEE[6] (WORZ)
bogdanm	82:6473597d706e	1860	*
bogdanm	82:6473597d706e	1861	* Values:
bogdanm	82:6473597d706e	1862	* - 0 - Set only the EEI bit specified in the SEEI field.
bogdanm	82:6473597d706e	1863	* - 1 - Sets all bits in EEI
bogdanm	82:6473597d706e	1864	*/
bogdanm	82:6473597d706e	1865	//@{
bogdanm	82:6473597d706e	1866	#define BP_DMA_SEEI_SAEE (6U) //!< Bit position for DMA_SEEI_SAEE.
bogdanm	82:6473597d706e	1867	#define BM_DMA_SEEI_SAEE (0x40U) //!< Bit mask for DMA_SEEI_SAEE.
bogdanm	82:6473597d706e	1868	#define BS_DMA_SEEI_SAEE (1U) //!< Bit field size in bits for DMA_SEEI_SAEE.
bogdanm	82:6473597d706e	1869
bogdanm	82:6473597d706e	1870	//! @brief Format value for bitfield DMA_SEEI_SAEE.
bogdanm	82:6473597d706e	1871	#define BF_DMA_SEEI_SAEE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_SAEE), uint8_t) & BM_DMA_SEEI_SAEE)
bogdanm	82:6473597d706e	1872
bogdanm	82:6473597d706e	1873	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1874	//! @brief Set the SAEE field to a new value.
bogdanm	82:6473597d706e	1875	#define BW_DMA_SEEI_SAEE(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_SAEE) = (v))
bogdanm	82:6473597d706e	1876	#endif
bogdanm	82:6473597d706e	1877	//@}
bogdanm	82:6473597d706e	1878
bogdanm	82:6473597d706e	1879	/*!
bogdanm	82:6473597d706e	1880	* @name Register DMA_SEEI, field NOP[7] (WORZ)
bogdanm	82:6473597d706e	1881	*
bogdanm	82:6473597d706e	1882	* Values:
bogdanm	82:6473597d706e	1883	* - 0 - Normal operation
bogdanm	82:6473597d706e	1884	* - 1 - No operation, ignore the other bits in this register
bogdanm	82:6473597d706e	1885	*/
bogdanm	82:6473597d706e	1886	//@{
bogdanm	82:6473597d706e	1887	#define BP_DMA_SEEI_NOP (7U) //!< Bit position for DMA_SEEI_NOP.
bogdanm	82:6473597d706e	1888	#define BM_DMA_SEEI_NOP (0x80U) //!< Bit mask for DMA_SEEI_NOP.
bogdanm	82:6473597d706e	1889	#define BS_DMA_SEEI_NOP (1U) //!< Bit field size in bits for DMA_SEEI_NOP.
bogdanm	82:6473597d706e	1890
bogdanm	82:6473597d706e	1891	//! @brief Format value for bitfield DMA_SEEI_NOP.
bogdanm	82:6473597d706e	1892	#define BF_DMA_SEEI_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SEEI_NOP), uint8_t) & BM_DMA_SEEI_NOP)
bogdanm	82:6473597d706e	1893
bogdanm	82:6473597d706e	1894	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1895	//! @brief Set the NOP field to a new value.
bogdanm	82:6473597d706e	1896	#define BW_DMA_SEEI_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SEEI_ADDR(x), BP_DMA_SEEI_NOP) = (v))
bogdanm	82:6473597d706e	1897	#endif
bogdanm	82:6473597d706e	1898	//@}
bogdanm	82:6473597d706e	1899
bogdanm	82:6473597d706e	1900	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1901	// HW_DMA_CERQ - Clear Enable Request Register
bogdanm	82:6473597d706e	1902	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	1903
bogdanm	82:6473597d706e	1904	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1905	/*!
bogdanm	82:6473597d706e	1906	* @brief HW_DMA_CERQ - Clear Enable Request Register (WO)
bogdanm	82:6473597d706e	1907	*
bogdanm	82:6473597d706e	1908	* Reset value: 0x00U
bogdanm	82:6473597d706e	1909	*
bogdanm	82:6473597d706e	1910	* The CERQ provides a simple memory-mapped mechanism to clear a given bit in
bogdanm	82:6473597d706e	1911	* the ERQ to disable the DMA request for a given channel. The data value on a
bogdanm	82:6473597d706e	1912	* register write causes the corresponding bit in the ERQ to be cleared. Setting the
bogdanm	82:6473597d706e	1913	* CAER bit provides a global clear function, forcing the entire contents of the
bogdanm	82:6473597d706e	1914	* ERQ to be cleared, disabling all DMA request inputs. If NOP is set, the
bogdanm	82:6473597d706e	1915	* command is ignored. This allows you to write multiple-byte registers as a 32-bit
bogdanm	82:6473597d706e	1916	* word. Reads of this register return all zeroes.
bogdanm	82:6473597d706e	1917	*/
bogdanm	82:6473597d706e	1918	typedef union _hw_dma_cerq
bogdanm	82:6473597d706e	1919	{
bogdanm	82:6473597d706e	1920	uint8_t U;
bogdanm	82:6473597d706e	1921	struct _hw_dma_cerq_bitfields
bogdanm	82:6473597d706e	1922	{
bogdanm	82:6473597d706e	1923	uint8_t CERQ : 4; //!< [3:0] Clear Enable Request
bogdanm	82:6473597d706e	1924	uint8_t RESERVED0 : 2; //!< [5:4]
bogdanm	82:6473597d706e	1925	uint8_t CAER : 1; //!< [6] Clear All Enable Requests
bogdanm	82:6473597d706e	1926	uint8_t NOP : 1; //!< [7] No Op enable
bogdanm	82:6473597d706e	1927	} B;
bogdanm	82:6473597d706e	1928	} hw_dma_cerq_t;
bogdanm	82:6473597d706e	1929	#endif
bogdanm	82:6473597d706e	1930
bogdanm	82:6473597d706e	1931	/*!
bogdanm	82:6473597d706e	1932	* @name Constants and macros for entire DMA_CERQ register
bogdanm	82:6473597d706e	1933	*/
bogdanm	82:6473597d706e	1934	//@{
bogdanm	82:6473597d706e	1935	#define HW_DMA_CERQ_ADDR(x) (REGS_DMA_BASE(x) + 0x1AU)
bogdanm	82:6473597d706e	1936
bogdanm	82:6473597d706e	1937	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1938	#define HW_DMA_CERQ(x) ((__O hw_dma_cerq_t ) HW_DMA_CERQ_ADDR(x))
bogdanm	82:6473597d706e	1939	#define HW_DMA_CERQ_RD(x) (HW_DMA_CERQ(x).U)
bogdanm	82:6473597d706e	1940	#define HW_DMA_CERQ_WR(x, v) (HW_DMA_CERQ(x).U = (v))
bogdanm	82:6473597d706e	1941	#endif
bogdanm	82:6473597d706e	1942	//@}
bogdanm	82:6473597d706e	1943
bogdanm	82:6473597d706e	1944	/*
bogdanm	82:6473597d706e	1945	* Constants & macros for individual DMA_CERQ bitfields
bogdanm	82:6473597d706e	1946	*/
bogdanm	82:6473597d706e	1947
bogdanm	82:6473597d706e	1948	/*!
bogdanm	82:6473597d706e	1949	* @name Register DMA_CERQ, field CERQ[3:0] (WORZ)
bogdanm	82:6473597d706e	1950	*
bogdanm	82:6473597d706e	1951	* Clears the corresponding bit in ERQ
bogdanm	82:6473597d706e	1952	*/
bogdanm	82:6473597d706e	1953	//@{
bogdanm	82:6473597d706e	1954	#define BP_DMA_CERQ_CERQ (0U) //!< Bit position for DMA_CERQ_CERQ.
bogdanm	82:6473597d706e	1955	#define BM_DMA_CERQ_CERQ (0x0FU) //!< Bit mask for DMA_CERQ_CERQ.
bogdanm	82:6473597d706e	1956	#define BS_DMA_CERQ_CERQ (4U) //!< Bit field size in bits for DMA_CERQ_CERQ.
bogdanm	82:6473597d706e	1957
bogdanm	82:6473597d706e	1958	//! @brief Format value for bitfield DMA_CERQ_CERQ.
bogdanm	82:6473597d706e	1959	#define BF_DMA_CERQ_CERQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_CERQ), uint8_t) & BM_DMA_CERQ_CERQ)
bogdanm	82:6473597d706e	1960
bogdanm	82:6473597d706e	1961	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1962	//! @brief Set the CERQ field to a new value.
bogdanm	82:6473597d706e	1963	#define BW_DMA_CERQ_CERQ(x, v) (HW_DMA_CERQ_WR(x, (HW_DMA_CERQ_RD(x) & ~BM_DMA_CERQ_CERQ) \| BF_DMA_CERQ_CERQ(v)))
bogdanm	82:6473597d706e	1964	#endif
bogdanm	82:6473597d706e	1965	//@}
bogdanm	82:6473597d706e	1966
bogdanm	82:6473597d706e	1967	/*!
bogdanm	82:6473597d706e	1968	* @name Register DMA_CERQ, field CAER[6] (WORZ)
bogdanm	82:6473597d706e	1969	*
bogdanm	82:6473597d706e	1970	* Values:
bogdanm	82:6473597d706e	1971	* - 0 - Clear only the ERQ bit specified in the CERQ field
bogdanm	82:6473597d706e	1972	* - 1 - Clear all bits in ERQ
bogdanm	82:6473597d706e	1973	*/
bogdanm	82:6473597d706e	1974	//@{
bogdanm	82:6473597d706e	1975	#define BP_DMA_CERQ_CAER (6U) //!< Bit position for DMA_CERQ_CAER.
bogdanm	82:6473597d706e	1976	#define BM_DMA_CERQ_CAER (0x40U) //!< Bit mask for DMA_CERQ_CAER.
bogdanm	82:6473597d706e	1977	#define BS_DMA_CERQ_CAER (1U) //!< Bit field size in bits for DMA_CERQ_CAER.
bogdanm	82:6473597d706e	1978
bogdanm	82:6473597d706e	1979	//! @brief Format value for bitfield DMA_CERQ_CAER.
bogdanm	82:6473597d706e	1980	#define BF_DMA_CERQ_CAER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_CAER), uint8_t) & BM_DMA_CERQ_CAER)
bogdanm	82:6473597d706e	1981
bogdanm	82:6473597d706e	1982	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	1983	//! @brief Set the CAER field to a new value.
bogdanm	82:6473597d706e	1984	#define BW_DMA_CERQ_CAER(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_CAER) = (v))
bogdanm	82:6473597d706e	1985	#endif
bogdanm	82:6473597d706e	1986	//@}
bogdanm	82:6473597d706e	1987
bogdanm	82:6473597d706e	1988	/*!
bogdanm	82:6473597d706e	1989	* @name Register DMA_CERQ, field NOP[7] (WORZ)
bogdanm	82:6473597d706e	1990	*
bogdanm	82:6473597d706e	1991	* Values:
bogdanm	82:6473597d706e	1992	* - 0 - Normal operation
bogdanm	82:6473597d706e	1993	* - 1 - No operation, ignore the other bits in this register
bogdanm	82:6473597d706e	1994	*/
bogdanm	82:6473597d706e	1995	//@{
bogdanm	82:6473597d706e	1996	#define BP_DMA_CERQ_NOP (7U) //!< Bit position for DMA_CERQ_NOP.
bogdanm	82:6473597d706e	1997	#define BM_DMA_CERQ_NOP (0x80U) //!< Bit mask for DMA_CERQ_NOP.
bogdanm	82:6473597d706e	1998	#define BS_DMA_CERQ_NOP (1U) //!< Bit field size in bits for DMA_CERQ_NOP.
bogdanm	82:6473597d706e	1999
bogdanm	82:6473597d706e	2000	//! @brief Format value for bitfield DMA_CERQ_NOP.
bogdanm	82:6473597d706e	2001	#define BF_DMA_CERQ_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERQ_NOP), uint8_t) & BM_DMA_CERQ_NOP)
bogdanm	82:6473597d706e	2002
bogdanm	82:6473597d706e	2003	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2004	//! @brief Set the NOP field to a new value.
bogdanm	82:6473597d706e	2005	#define BW_DMA_CERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERQ_ADDR(x), BP_DMA_CERQ_NOP) = (v))
bogdanm	82:6473597d706e	2006	#endif
bogdanm	82:6473597d706e	2007	//@}
bogdanm	82:6473597d706e	2008
bogdanm	82:6473597d706e	2009	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2010	// HW_DMA_SERQ - Set Enable Request Register
bogdanm	82:6473597d706e	2011	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2012
bogdanm	82:6473597d706e	2013	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2014	/*!
bogdanm	82:6473597d706e	2015	* @brief HW_DMA_SERQ - Set Enable Request Register (WO)
bogdanm	82:6473597d706e	2016	*
bogdanm	82:6473597d706e	2017	* Reset value: 0x00U
bogdanm	82:6473597d706e	2018	*
bogdanm	82:6473597d706e	2019	* The SERQ provides a simple memory-mapped mechanism to set a given bit in the
bogdanm	82:6473597d706e	2020	* ERQ to enable the DMA request for a given channel. The data value on a
bogdanm	82:6473597d706e	2021	* register write causes the corresponding bit in the ERQ to be set. Setting the SAER
bogdanm	82:6473597d706e	2022	* bit provides a global set function, forcing the entire contents of ERQ to be
bogdanm	82:6473597d706e	2023	* set. If the NOP bit is set, the command is ignored. This allows you to write
bogdanm	82:6473597d706e	2024	* multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
bogdanm	82:6473597d706e	2025	*/
bogdanm	82:6473597d706e	2026	typedef union _hw_dma_serq
bogdanm	82:6473597d706e	2027	{
bogdanm	82:6473597d706e	2028	uint8_t U;
bogdanm	82:6473597d706e	2029	struct _hw_dma_serq_bitfields
bogdanm	82:6473597d706e	2030	{
bogdanm	82:6473597d706e	2031	uint8_t SERQ : 4; //!< [3:0] Set enable request
bogdanm	82:6473597d706e	2032	uint8_t RESERVED0 : 2; //!< [5:4]
bogdanm	82:6473597d706e	2033	uint8_t SAER : 1; //!< [6] Set All Enable Requests
bogdanm	82:6473597d706e	2034	uint8_t NOP : 1; //!< [7] No Op enable
bogdanm	82:6473597d706e	2035	} B;
bogdanm	82:6473597d706e	2036	} hw_dma_serq_t;
bogdanm	82:6473597d706e	2037	#endif
bogdanm	82:6473597d706e	2038
bogdanm	82:6473597d706e	2039	/*!
bogdanm	82:6473597d706e	2040	* @name Constants and macros for entire DMA_SERQ register
bogdanm	82:6473597d706e	2041	*/
bogdanm	82:6473597d706e	2042	//@{
bogdanm	82:6473597d706e	2043	#define HW_DMA_SERQ_ADDR(x) (REGS_DMA_BASE(x) + 0x1BU)
bogdanm	82:6473597d706e	2044
bogdanm	82:6473597d706e	2045	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2046	#define HW_DMA_SERQ(x) ((__O hw_dma_serq_t ) HW_DMA_SERQ_ADDR(x))
bogdanm	82:6473597d706e	2047	#define HW_DMA_SERQ_RD(x) (HW_DMA_SERQ(x).U)
bogdanm	82:6473597d706e	2048	#define HW_DMA_SERQ_WR(x, v) (HW_DMA_SERQ(x).U = (v))
bogdanm	82:6473597d706e	2049	#endif
bogdanm	82:6473597d706e	2050	//@}
bogdanm	82:6473597d706e	2051
bogdanm	82:6473597d706e	2052	/*
bogdanm	82:6473597d706e	2053	* Constants & macros for individual DMA_SERQ bitfields
bogdanm	82:6473597d706e	2054	*/
bogdanm	82:6473597d706e	2055
bogdanm	82:6473597d706e	2056	/*!
bogdanm	82:6473597d706e	2057	* @name Register DMA_SERQ, field SERQ[3:0] (WORZ)
bogdanm	82:6473597d706e	2058	*
bogdanm	82:6473597d706e	2059	* Sets the corresponding bit in ERQ
bogdanm	82:6473597d706e	2060	*/
bogdanm	82:6473597d706e	2061	//@{
bogdanm	82:6473597d706e	2062	#define BP_DMA_SERQ_SERQ (0U) //!< Bit position for DMA_SERQ_SERQ.
bogdanm	82:6473597d706e	2063	#define BM_DMA_SERQ_SERQ (0x0FU) //!< Bit mask for DMA_SERQ_SERQ.
bogdanm	82:6473597d706e	2064	#define BS_DMA_SERQ_SERQ (4U) //!< Bit field size in bits for DMA_SERQ_SERQ.
bogdanm	82:6473597d706e	2065
bogdanm	82:6473597d706e	2066	//! @brief Format value for bitfield DMA_SERQ_SERQ.
bogdanm	82:6473597d706e	2067	#define BF_DMA_SERQ_SERQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_SERQ), uint8_t) & BM_DMA_SERQ_SERQ)
bogdanm	82:6473597d706e	2068
bogdanm	82:6473597d706e	2069	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2070	//! @brief Set the SERQ field to a new value.
bogdanm	82:6473597d706e	2071	#define BW_DMA_SERQ_SERQ(x, v) (HW_DMA_SERQ_WR(x, (HW_DMA_SERQ_RD(x) & ~BM_DMA_SERQ_SERQ) \| BF_DMA_SERQ_SERQ(v)))
bogdanm	82:6473597d706e	2072	#endif
bogdanm	82:6473597d706e	2073	//@}
bogdanm	82:6473597d706e	2074
bogdanm	82:6473597d706e	2075	/*!
bogdanm	82:6473597d706e	2076	* @name Register DMA_SERQ, field SAER[6] (WORZ)
bogdanm	82:6473597d706e	2077	*
bogdanm	82:6473597d706e	2078	* Values:
bogdanm	82:6473597d706e	2079	* - 0 - Set only the ERQ bit specified in the SERQ field
bogdanm	82:6473597d706e	2080	* - 1 - Set all bits in ERQ
bogdanm	82:6473597d706e	2081	*/
bogdanm	82:6473597d706e	2082	//@{
bogdanm	82:6473597d706e	2083	#define BP_DMA_SERQ_SAER (6U) //!< Bit position for DMA_SERQ_SAER.
bogdanm	82:6473597d706e	2084	#define BM_DMA_SERQ_SAER (0x40U) //!< Bit mask for DMA_SERQ_SAER.
bogdanm	82:6473597d706e	2085	#define BS_DMA_SERQ_SAER (1U) //!< Bit field size in bits for DMA_SERQ_SAER.
bogdanm	82:6473597d706e	2086
bogdanm	82:6473597d706e	2087	//! @brief Format value for bitfield DMA_SERQ_SAER.
bogdanm	82:6473597d706e	2088	#define BF_DMA_SERQ_SAER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_SAER), uint8_t) & BM_DMA_SERQ_SAER)
bogdanm	82:6473597d706e	2089
bogdanm	82:6473597d706e	2090	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2091	//! @brief Set the SAER field to a new value.
bogdanm	82:6473597d706e	2092	#define BW_DMA_SERQ_SAER(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_SAER) = (v))
bogdanm	82:6473597d706e	2093	#endif
bogdanm	82:6473597d706e	2094	//@}
bogdanm	82:6473597d706e	2095
bogdanm	82:6473597d706e	2096	/*!
bogdanm	82:6473597d706e	2097	* @name Register DMA_SERQ, field NOP[7] (WORZ)
bogdanm	82:6473597d706e	2098	*
bogdanm	82:6473597d706e	2099	* Values:
bogdanm	82:6473597d706e	2100	* - 0 - Normal operation
bogdanm	82:6473597d706e	2101	* - 1 - No operation, ignore the other bits in this register
bogdanm	82:6473597d706e	2102	*/
bogdanm	82:6473597d706e	2103	//@{
bogdanm	82:6473597d706e	2104	#define BP_DMA_SERQ_NOP (7U) //!< Bit position for DMA_SERQ_NOP.
bogdanm	82:6473597d706e	2105	#define BM_DMA_SERQ_NOP (0x80U) //!< Bit mask for DMA_SERQ_NOP.
bogdanm	82:6473597d706e	2106	#define BS_DMA_SERQ_NOP (1U) //!< Bit field size in bits for DMA_SERQ_NOP.
bogdanm	82:6473597d706e	2107
bogdanm	82:6473597d706e	2108	//! @brief Format value for bitfield DMA_SERQ_NOP.
bogdanm	82:6473597d706e	2109	#define BF_DMA_SERQ_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SERQ_NOP), uint8_t) & BM_DMA_SERQ_NOP)
bogdanm	82:6473597d706e	2110
bogdanm	82:6473597d706e	2111	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2112	//! @brief Set the NOP field to a new value.
bogdanm	82:6473597d706e	2113	#define BW_DMA_SERQ_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SERQ_ADDR(x), BP_DMA_SERQ_NOP) = (v))
bogdanm	82:6473597d706e	2114	#endif
bogdanm	82:6473597d706e	2115	//@}
bogdanm	82:6473597d706e	2116
bogdanm	82:6473597d706e	2117	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2118	// HW_DMA_CDNE - Clear DONE Status Bit Register
bogdanm	82:6473597d706e	2119	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2120
bogdanm	82:6473597d706e	2121	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2122	/*!
bogdanm	82:6473597d706e	2123	* @brief HW_DMA_CDNE - Clear DONE Status Bit Register (WO)
bogdanm	82:6473597d706e	2124	*
bogdanm	82:6473597d706e	2125	* Reset value: 0x00U
bogdanm	82:6473597d706e	2126	*
bogdanm	82:6473597d706e	2127	* The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in
bogdanm	82:6473597d706e	2128	* the TCD of the given channel. The data value on a register write causes the
bogdanm	82:6473597d706e	2129	* DONE bit in the corresponding transfer control descriptor to be cleared. Setting
bogdanm	82:6473597d706e	2130	* the CADN bit provides a global clear function, forcing all DONE bits to be
bogdanm	82:6473597d706e	2131	* cleared. If the NOP bit is set, the command is ignored. This allows you to write
bogdanm	82:6473597d706e	2132	* multiple-byte registers as a 32-bit word. Reads of this register return all
bogdanm	82:6473597d706e	2133	* zeroes.
bogdanm	82:6473597d706e	2134	*/
bogdanm	82:6473597d706e	2135	typedef union _hw_dma_cdne
bogdanm	82:6473597d706e	2136	{
bogdanm	82:6473597d706e	2137	uint8_t U;
bogdanm	82:6473597d706e	2138	struct _hw_dma_cdne_bitfields
bogdanm	82:6473597d706e	2139	{
bogdanm	82:6473597d706e	2140	uint8_t CDNE : 4; //!< [3:0] Clear DONE Bit
bogdanm	82:6473597d706e	2141	uint8_t RESERVED0 : 2; //!< [5:4]
bogdanm	82:6473597d706e	2142	uint8_t CADN : 1; //!< [6] Clears All DONE Bits
bogdanm	82:6473597d706e	2143	uint8_t NOP : 1; //!< [7] No Op enable
bogdanm	82:6473597d706e	2144	} B;
bogdanm	82:6473597d706e	2145	} hw_dma_cdne_t;
bogdanm	82:6473597d706e	2146	#endif
bogdanm	82:6473597d706e	2147
bogdanm	82:6473597d706e	2148	/*!
bogdanm	82:6473597d706e	2149	* @name Constants and macros for entire DMA_CDNE register
bogdanm	82:6473597d706e	2150	*/
bogdanm	82:6473597d706e	2151	//@{
bogdanm	82:6473597d706e	2152	#define HW_DMA_CDNE_ADDR(x) (REGS_DMA_BASE(x) + 0x1CU)
bogdanm	82:6473597d706e	2153
bogdanm	82:6473597d706e	2154	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2155	#define HW_DMA_CDNE(x) ((__O hw_dma_cdne_t ) HW_DMA_CDNE_ADDR(x))
bogdanm	82:6473597d706e	2156	#define HW_DMA_CDNE_RD(x) (HW_DMA_CDNE(x).U)
bogdanm	82:6473597d706e	2157	#define HW_DMA_CDNE_WR(x, v) (HW_DMA_CDNE(x).U = (v))
bogdanm	82:6473597d706e	2158	#endif
bogdanm	82:6473597d706e	2159	//@}
bogdanm	82:6473597d706e	2160
bogdanm	82:6473597d706e	2161	/*
bogdanm	82:6473597d706e	2162	* Constants & macros for individual DMA_CDNE bitfields
bogdanm	82:6473597d706e	2163	*/
bogdanm	82:6473597d706e	2164
bogdanm	82:6473597d706e	2165	/*!
bogdanm	82:6473597d706e	2166	* @name Register DMA_CDNE, field CDNE[3:0] (WORZ)
bogdanm	82:6473597d706e	2167	*
bogdanm	82:6473597d706e	2168	* Clears the corresponding bit in TCDn_CSR[DONE]
bogdanm	82:6473597d706e	2169	*/
bogdanm	82:6473597d706e	2170	//@{
bogdanm	82:6473597d706e	2171	#define BP_DMA_CDNE_CDNE (0U) //!< Bit position for DMA_CDNE_CDNE.
bogdanm	82:6473597d706e	2172	#define BM_DMA_CDNE_CDNE (0x0FU) //!< Bit mask for DMA_CDNE_CDNE.
bogdanm	82:6473597d706e	2173	#define BS_DMA_CDNE_CDNE (4U) //!< Bit field size in bits for DMA_CDNE_CDNE.
bogdanm	82:6473597d706e	2174
bogdanm	82:6473597d706e	2175	//! @brief Format value for bitfield DMA_CDNE_CDNE.
bogdanm	82:6473597d706e	2176	#define BF_DMA_CDNE_CDNE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_CDNE), uint8_t) & BM_DMA_CDNE_CDNE)
bogdanm	82:6473597d706e	2177
bogdanm	82:6473597d706e	2178	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2179	//! @brief Set the CDNE field to a new value.
bogdanm	82:6473597d706e	2180	#define BW_DMA_CDNE_CDNE(x, v) (HW_DMA_CDNE_WR(x, (HW_DMA_CDNE_RD(x) & ~BM_DMA_CDNE_CDNE) \| BF_DMA_CDNE_CDNE(v)))
bogdanm	82:6473597d706e	2181	#endif
bogdanm	82:6473597d706e	2182	//@}
bogdanm	82:6473597d706e	2183
bogdanm	82:6473597d706e	2184	/*!
bogdanm	82:6473597d706e	2185	* @name Register DMA_CDNE, field CADN[6] (WORZ)
bogdanm	82:6473597d706e	2186	*
bogdanm	82:6473597d706e	2187	* Values:
bogdanm	82:6473597d706e	2188	* - 0 - Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
bogdanm	82:6473597d706e	2189	* - 1 - Clears all bits in TCDn_CSR[DONE]
bogdanm	82:6473597d706e	2190	*/
bogdanm	82:6473597d706e	2191	//@{
bogdanm	82:6473597d706e	2192	#define BP_DMA_CDNE_CADN (6U) //!< Bit position for DMA_CDNE_CADN.
bogdanm	82:6473597d706e	2193	#define BM_DMA_CDNE_CADN (0x40U) //!< Bit mask for DMA_CDNE_CADN.
bogdanm	82:6473597d706e	2194	#define BS_DMA_CDNE_CADN (1U) //!< Bit field size in bits for DMA_CDNE_CADN.
bogdanm	82:6473597d706e	2195
bogdanm	82:6473597d706e	2196	//! @brief Format value for bitfield DMA_CDNE_CADN.
bogdanm	82:6473597d706e	2197	#define BF_DMA_CDNE_CADN(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_CADN), uint8_t) & BM_DMA_CDNE_CADN)
bogdanm	82:6473597d706e	2198
bogdanm	82:6473597d706e	2199	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2200	//! @brief Set the CADN field to a new value.
bogdanm	82:6473597d706e	2201	#define BW_DMA_CDNE_CADN(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_CADN) = (v))
bogdanm	82:6473597d706e	2202	#endif
bogdanm	82:6473597d706e	2203	//@}
bogdanm	82:6473597d706e	2204
bogdanm	82:6473597d706e	2205	/*!
bogdanm	82:6473597d706e	2206	* @name Register DMA_CDNE, field NOP[7] (WORZ)
bogdanm	82:6473597d706e	2207	*
bogdanm	82:6473597d706e	2208	* Values:
bogdanm	82:6473597d706e	2209	* - 0 - Normal operation
bogdanm	82:6473597d706e	2210	* - 1 - No operation, ignore the other bits in this register
bogdanm	82:6473597d706e	2211	*/
bogdanm	82:6473597d706e	2212	//@{
bogdanm	82:6473597d706e	2213	#define BP_DMA_CDNE_NOP (7U) //!< Bit position for DMA_CDNE_NOP.
bogdanm	82:6473597d706e	2214	#define BM_DMA_CDNE_NOP (0x80U) //!< Bit mask for DMA_CDNE_NOP.
bogdanm	82:6473597d706e	2215	#define BS_DMA_CDNE_NOP (1U) //!< Bit field size in bits for DMA_CDNE_NOP.
bogdanm	82:6473597d706e	2216
bogdanm	82:6473597d706e	2217	//! @brief Format value for bitfield DMA_CDNE_NOP.
bogdanm	82:6473597d706e	2218	#define BF_DMA_CDNE_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CDNE_NOP), uint8_t) & BM_DMA_CDNE_NOP)
bogdanm	82:6473597d706e	2219
bogdanm	82:6473597d706e	2220	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2221	//! @brief Set the NOP field to a new value.
bogdanm	82:6473597d706e	2222	#define BW_DMA_CDNE_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CDNE_ADDR(x), BP_DMA_CDNE_NOP) = (v))
bogdanm	82:6473597d706e	2223	#endif
bogdanm	82:6473597d706e	2224	//@}
bogdanm	82:6473597d706e	2225
bogdanm	82:6473597d706e	2226	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2227	// HW_DMA_SSRT - Set START Bit Register
bogdanm	82:6473597d706e	2228	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2229
bogdanm	82:6473597d706e	2230	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2231	/*!
bogdanm	82:6473597d706e	2232	* @brief HW_DMA_SSRT - Set START Bit Register (WO)
bogdanm	82:6473597d706e	2233	*
bogdanm	82:6473597d706e	2234	* Reset value: 0x00U
bogdanm	82:6473597d706e	2235	*
bogdanm	82:6473597d706e	2236	* The SSRT provides a simple memory-mapped mechanism to set the START bit in
bogdanm	82:6473597d706e	2237	* the TCD of the given channel. The data value on a register write causes the
bogdanm	82:6473597d706e	2238	* START bit in the corresponding transfer control descriptor to be set. Setting the
bogdanm	82:6473597d706e	2239	* SAST bit provides a global set function, forcing all START bits to be set. If
bogdanm	82:6473597d706e	2240	* the NOP bit is set, the command is ignored. This allows you to write
bogdanm	82:6473597d706e	2241	* multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
bogdanm	82:6473597d706e	2242	*/
bogdanm	82:6473597d706e	2243	typedef union _hw_dma_ssrt
bogdanm	82:6473597d706e	2244	{
bogdanm	82:6473597d706e	2245	uint8_t U;
bogdanm	82:6473597d706e	2246	struct _hw_dma_ssrt_bitfields
bogdanm	82:6473597d706e	2247	{
bogdanm	82:6473597d706e	2248	uint8_t SSRT : 4; //!< [3:0] Set START Bit
bogdanm	82:6473597d706e	2249	uint8_t RESERVED0 : 2; //!< [5:4]
bogdanm	82:6473597d706e	2250	uint8_t SAST : 1; //!< [6] Set All START Bits (activates all channels)
bogdanm	82:6473597d706e	2251	uint8_t NOP : 1; //!< [7] No Op enable
bogdanm	82:6473597d706e	2252	} B;
bogdanm	82:6473597d706e	2253	} hw_dma_ssrt_t;
bogdanm	82:6473597d706e	2254	#endif
bogdanm	82:6473597d706e	2255
bogdanm	82:6473597d706e	2256	/*!
bogdanm	82:6473597d706e	2257	* @name Constants and macros for entire DMA_SSRT register
bogdanm	82:6473597d706e	2258	*/
bogdanm	82:6473597d706e	2259	//@{
bogdanm	82:6473597d706e	2260	#define HW_DMA_SSRT_ADDR(x) (REGS_DMA_BASE(x) + 0x1DU)
bogdanm	82:6473597d706e	2261
bogdanm	82:6473597d706e	2262	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2263	#define HW_DMA_SSRT(x) ((__O hw_dma_ssrt_t ) HW_DMA_SSRT_ADDR(x))
bogdanm	82:6473597d706e	2264	#define HW_DMA_SSRT_RD(x) (HW_DMA_SSRT(x).U)
bogdanm	82:6473597d706e	2265	#define HW_DMA_SSRT_WR(x, v) (HW_DMA_SSRT(x).U = (v))
bogdanm	82:6473597d706e	2266	#endif
bogdanm	82:6473597d706e	2267	//@}
bogdanm	82:6473597d706e	2268
bogdanm	82:6473597d706e	2269	/*
bogdanm	82:6473597d706e	2270	* Constants & macros for individual DMA_SSRT bitfields
bogdanm	82:6473597d706e	2271	*/
bogdanm	82:6473597d706e	2272
bogdanm	82:6473597d706e	2273	/*!
bogdanm	82:6473597d706e	2274	* @name Register DMA_SSRT, field SSRT[3:0] (WORZ)
bogdanm	82:6473597d706e	2275	*
bogdanm	82:6473597d706e	2276	* Sets the corresponding bit in TCDn_CSR[START]
bogdanm	82:6473597d706e	2277	*/
bogdanm	82:6473597d706e	2278	//@{
bogdanm	82:6473597d706e	2279	#define BP_DMA_SSRT_SSRT (0U) //!< Bit position for DMA_SSRT_SSRT.
bogdanm	82:6473597d706e	2280	#define BM_DMA_SSRT_SSRT (0x0FU) //!< Bit mask for DMA_SSRT_SSRT.
bogdanm	82:6473597d706e	2281	#define BS_DMA_SSRT_SSRT (4U) //!< Bit field size in bits for DMA_SSRT_SSRT.
bogdanm	82:6473597d706e	2282
bogdanm	82:6473597d706e	2283	//! @brief Format value for bitfield DMA_SSRT_SSRT.
bogdanm	82:6473597d706e	2284	#define BF_DMA_SSRT_SSRT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_SSRT), uint8_t) & BM_DMA_SSRT_SSRT)
bogdanm	82:6473597d706e	2285
bogdanm	82:6473597d706e	2286	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2287	//! @brief Set the SSRT field to a new value.
bogdanm	82:6473597d706e	2288	#define BW_DMA_SSRT_SSRT(x, v) (HW_DMA_SSRT_WR(x, (HW_DMA_SSRT_RD(x) & ~BM_DMA_SSRT_SSRT) \| BF_DMA_SSRT_SSRT(v)))
bogdanm	82:6473597d706e	2289	#endif
bogdanm	82:6473597d706e	2290	//@}
bogdanm	82:6473597d706e	2291
bogdanm	82:6473597d706e	2292	/*!
bogdanm	82:6473597d706e	2293	* @name Register DMA_SSRT, field SAST[6] (WORZ)
bogdanm	82:6473597d706e	2294	*
bogdanm	82:6473597d706e	2295	* Values:
bogdanm	82:6473597d706e	2296	* - 0 - Set only the TCDn_CSR[START] bit specified in the SSRT field
bogdanm	82:6473597d706e	2297	* - 1 - Set all bits in TCDn_CSR[START]
bogdanm	82:6473597d706e	2298	*/
bogdanm	82:6473597d706e	2299	//@{
bogdanm	82:6473597d706e	2300	#define BP_DMA_SSRT_SAST (6U) //!< Bit position for DMA_SSRT_SAST.
bogdanm	82:6473597d706e	2301	#define BM_DMA_SSRT_SAST (0x40U) //!< Bit mask for DMA_SSRT_SAST.
bogdanm	82:6473597d706e	2302	#define BS_DMA_SSRT_SAST (1U) //!< Bit field size in bits for DMA_SSRT_SAST.
bogdanm	82:6473597d706e	2303
bogdanm	82:6473597d706e	2304	//! @brief Format value for bitfield DMA_SSRT_SAST.
bogdanm	82:6473597d706e	2305	#define BF_DMA_SSRT_SAST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_SAST), uint8_t) & BM_DMA_SSRT_SAST)
bogdanm	82:6473597d706e	2306
bogdanm	82:6473597d706e	2307	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2308	//! @brief Set the SAST field to a new value.
bogdanm	82:6473597d706e	2309	#define BW_DMA_SSRT_SAST(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_SAST) = (v))
bogdanm	82:6473597d706e	2310	#endif
bogdanm	82:6473597d706e	2311	//@}
bogdanm	82:6473597d706e	2312
bogdanm	82:6473597d706e	2313	/*!
bogdanm	82:6473597d706e	2314	* @name Register DMA_SSRT, field NOP[7] (WORZ)
bogdanm	82:6473597d706e	2315	*
bogdanm	82:6473597d706e	2316	* Values:
bogdanm	82:6473597d706e	2317	* - 0 - Normal operation
bogdanm	82:6473597d706e	2318	* - 1 - No operation, ignore the other bits in this register
bogdanm	82:6473597d706e	2319	*/
bogdanm	82:6473597d706e	2320	//@{
bogdanm	82:6473597d706e	2321	#define BP_DMA_SSRT_NOP (7U) //!< Bit position for DMA_SSRT_NOP.
bogdanm	82:6473597d706e	2322	#define BM_DMA_SSRT_NOP (0x80U) //!< Bit mask for DMA_SSRT_NOP.
bogdanm	82:6473597d706e	2323	#define BS_DMA_SSRT_NOP (1U) //!< Bit field size in bits for DMA_SSRT_NOP.
bogdanm	82:6473597d706e	2324
bogdanm	82:6473597d706e	2325	//! @brief Format value for bitfield DMA_SSRT_NOP.
bogdanm	82:6473597d706e	2326	#define BF_DMA_SSRT_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_SSRT_NOP), uint8_t) & BM_DMA_SSRT_NOP)
bogdanm	82:6473597d706e	2327
bogdanm	82:6473597d706e	2328	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2329	//! @brief Set the NOP field to a new value.
bogdanm	82:6473597d706e	2330	#define BW_DMA_SSRT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_SSRT_ADDR(x), BP_DMA_SSRT_NOP) = (v))
bogdanm	82:6473597d706e	2331	#endif
bogdanm	82:6473597d706e	2332	//@}
bogdanm	82:6473597d706e	2333
bogdanm	82:6473597d706e	2334	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2335	// HW_DMA_CERR - Clear Error Register
bogdanm	82:6473597d706e	2336	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2337
bogdanm	82:6473597d706e	2338	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2339	/*!
bogdanm	82:6473597d706e	2340	* @brief HW_DMA_CERR - Clear Error Register (WO)
bogdanm	82:6473597d706e	2341	*
bogdanm	82:6473597d706e	2342	* Reset value: 0x00U
bogdanm	82:6473597d706e	2343	*
bogdanm	82:6473597d706e	2344	* The CERR provides a simple memory-mapped mechanism to clear a given bit in
bogdanm	82:6473597d706e	2345	* the ERR to disable the error condition flag for a given channel. The given value
bogdanm	82:6473597d706e	2346	* on a register write causes the corresponding bit in the ERR to be cleared.
bogdanm	82:6473597d706e	2347	* Setting the CAEI bit provides a global clear function, forcing the ERR contents
bogdanm	82:6473597d706e	2348	* to be cleared, clearing all channel error indicators. If the NOP bit is set,
bogdanm	82:6473597d706e	2349	* the command is ignored. This allows you to write multiple-byte registers as a
bogdanm	82:6473597d706e	2350	* 32-bit word. Reads of this register return all zeroes.
bogdanm	82:6473597d706e	2351	*/
bogdanm	82:6473597d706e	2352	typedef union _hw_dma_cerr
bogdanm	82:6473597d706e	2353	{
bogdanm	82:6473597d706e	2354	uint8_t U;
bogdanm	82:6473597d706e	2355	struct _hw_dma_cerr_bitfields
bogdanm	82:6473597d706e	2356	{
bogdanm	82:6473597d706e	2357	uint8_t CERR : 4; //!< [3:0] Clear Error Indicator
bogdanm	82:6473597d706e	2358	uint8_t RESERVED0 : 2; //!< [5:4]
bogdanm	82:6473597d706e	2359	uint8_t CAEI : 1; //!< [6] Clear All Error Indicators
bogdanm	82:6473597d706e	2360	uint8_t NOP : 1; //!< [7] No Op enable
bogdanm	82:6473597d706e	2361	} B;
bogdanm	82:6473597d706e	2362	} hw_dma_cerr_t;
bogdanm	82:6473597d706e	2363	#endif
bogdanm	82:6473597d706e	2364
bogdanm	82:6473597d706e	2365	/*!
bogdanm	82:6473597d706e	2366	* @name Constants and macros for entire DMA_CERR register
bogdanm	82:6473597d706e	2367	*/
bogdanm	82:6473597d706e	2368	//@{
bogdanm	82:6473597d706e	2369	#define HW_DMA_CERR_ADDR(x) (REGS_DMA_BASE(x) + 0x1EU)
bogdanm	82:6473597d706e	2370
bogdanm	82:6473597d706e	2371	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2372	#define HW_DMA_CERR(x) ((__O hw_dma_cerr_t ) HW_DMA_CERR_ADDR(x))
bogdanm	82:6473597d706e	2373	#define HW_DMA_CERR_RD(x) (HW_DMA_CERR(x).U)
bogdanm	82:6473597d706e	2374	#define HW_DMA_CERR_WR(x, v) (HW_DMA_CERR(x).U = (v))
bogdanm	82:6473597d706e	2375	#endif
bogdanm	82:6473597d706e	2376	//@}
bogdanm	82:6473597d706e	2377
bogdanm	82:6473597d706e	2378	/*
bogdanm	82:6473597d706e	2379	* Constants & macros for individual DMA_CERR bitfields
bogdanm	82:6473597d706e	2380	*/
bogdanm	82:6473597d706e	2381
bogdanm	82:6473597d706e	2382	/*!
bogdanm	82:6473597d706e	2383	* @name Register DMA_CERR, field CERR[3:0] (WORZ)
bogdanm	82:6473597d706e	2384	*
bogdanm	82:6473597d706e	2385	* Clears the corresponding bit in ERR
bogdanm	82:6473597d706e	2386	*/
bogdanm	82:6473597d706e	2387	//@{
bogdanm	82:6473597d706e	2388	#define BP_DMA_CERR_CERR (0U) //!< Bit position for DMA_CERR_CERR.
bogdanm	82:6473597d706e	2389	#define BM_DMA_CERR_CERR (0x0FU) //!< Bit mask for DMA_CERR_CERR.
bogdanm	82:6473597d706e	2390	#define BS_DMA_CERR_CERR (4U) //!< Bit field size in bits for DMA_CERR_CERR.
bogdanm	82:6473597d706e	2391
bogdanm	82:6473597d706e	2392	//! @brief Format value for bitfield DMA_CERR_CERR.
bogdanm	82:6473597d706e	2393	#define BF_DMA_CERR_CERR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_CERR), uint8_t) & BM_DMA_CERR_CERR)
bogdanm	82:6473597d706e	2394
bogdanm	82:6473597d706e	2395	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2396	//! @brief Set the CERR field to a new value.
bogdanm	82:6473597d706e	2397	#define BW_DMA_CERR_CERR(x, v) (HW_DMA_CERR_WR(x, (HW_DMA_CERR_RD(x) & ~BM_DMA_CERR_CERR) \| BF_DMA_CERR_CERR(v)))
bogdanm	82:6473597d706e	2398	#endif
bogdanm	82:6473597d706e	2399	//@}
bogdanm	82:6473597d706e	2400
bogdanm	82:6473597d706e	2401	/*!
bogdanm	82:6473597d706e	2402	* @name Register DMA_CERR, field CAEI[6] (WORZ)
bogdanm	82:6473597d706e	2403	*
bogdanm	82:6473597d706e	2404	* Values:
bogdanm	82:6473597d706e	2405	* - 0 - Clear only the ERR bit specified in the CERR field
bogdanm	82:6473597d706e	2406	* - 1 - Clear all bits in ERR
bogdanm	82:6473597d706e	2407	*/
bogdanm	82:6473597d706e	2408	//@{
bogdanm	82:6473597d706e	2409	#define BP_DMA_CERR_CAEI (6U) //!< Bit position for DMA_CERR_CAEI.
bogdanm	82:6473597d706e	2410	#define BM_DMA_CERR_CAEI (0x40U) //!< Bit mask for DMA_CERR_CAEI.
bogdanm	82:6473597d706e	2411	#define BS_DMA_CERR_CAEI (1U) //!< Bit field size in bits for DMA_CERR_CAEI.
bogdanm	82:6473597d706e	2412
bogdanm	82:6473597d706e	2413	//! @brief Format value for bitfield DMA_CERR_CAEI.
bogdanm	82:6473597d706e	2414	#define BF_DMA_CERR_CAEI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_CAEI), uint8_t) & BM_DMA_CERR_CAEI)
bogdanm	82:6473597d706e	2415
bogdanm	82:6473597d706e	2416	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2417	//! @brief Set the CAEI field to a new value.
bogdanm	82:6473597d706e	2418	#define BW_DMA_CERR_CAEI(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_CAEI) = (v))
bogdanm	82:6473597d706e	2419	#endif
bogdanm	82:6473597d706e	2420	//@}
bogdanm	82:6473597d706e	2421
bogdanm	82:6473597d706e	2422	/*!
bogdanm	82:6473597d706e	2423	* @name Register DMA_CERR, field NOP[7] (WORZ)
bogdanm	82:6473597d706e	2424	*
bogdanm	82:6473597d706e	2425	* Values:
bogdanm	82:6473597d706e	2426	* - 0 - Normal operation
bogdanm	82:6473597d706e	2427	* - 1 - No operation, ignore the other bits in this register
bogdanm	82:6473597d706e	2428	*/
bogdanm	82:6473597d706e	2429	//@{
bogdanm	82:6473597d706e	2430	#define BP_DMA_CERR_NOP (7U) //!< Bit position for DMA_CERR_NOP.
bogdanm	82:6473597d706e	2431	#define BM_DMA_CERR_NOP (0x80U) //!< Bit mask for DMA_CERR_NOP.
bogdanm	82:6473597d706e	2432	#define BS_DMA_CERR_NOP (1U) //!< Bit field size in bits for DMA_CERR_NOP.
bogdanm	82:6473597d706e	2433
bogdanm	82:6473597d706e	2434	//! @brief Format value for bitfield DMA_CERR_NOP.
bogdanm	82:6473597d706e	2435	#define BF_DMA_CERR_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CERR_NOP), uint8_t) & BM_DMA_CERR_NOP)
bogdanm	82:6473597d706e	2436
bogdanm	82:6473597d706e	2437	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2438	//! @brief Set the NOP field to a new value.
bogdanm	82:6473597d706e	2439	#define BW_DMA_CERR_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CERR_ADDR(x), BP_DMA_CERR_NOP) = (v))
bogdanm	82:6473597d706e	2440	#endif
bogdanm	82:6473597d706e	2441	//@}
bogdanm	82:6473597d706e	2442
bogdanm	82:6473597d706e	2443	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2444	// HW_DMA_CINT - Clear Interrupt Request Register
bogdanm	82:6473597d706e	2445	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2446
bogdanm	82:6473597d706e	2447	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2448	/*!
bogdanm	82:6473597d706e	2449	* @brief HW_DMA_CINT - Clear Interrupt Request Register (WO)
bogdanm	82:6473597d706e	2450	*
bogdanm	82:6473597d706e	2451	* Reset value: 0x00U
bogdanm	82:6473597d706e	2452	*
bogdanm	82:6473597d706e	2453	* The CINT provides a simple, memory-mapped mechanism to clear a given bit in
bogdanm	82:6473597d706e	2454	* the INT to disable the interrupt request for a given channel. The given value
bogdanm	82:6473597d706e	2455	* on a register write causes the corresponding bit in the INT to be cleared.
bogdanm	82:6473597d706e	2456	* Setting the CAIR bit provides a global clear function, forcing the entire contents
bogdanm	82:6473597d706e	2457	* of the INT to be cleared, disabling all DMA interrupt requests. If the NOP
bogdanm	82:6473597d706e	2458	* bit is set, the command is ignored. This allows you to write multiple-byte
bogdanm	82:6473597d706e	2459	* registers as a 32-bit word. Reads of this register return all zeroes.
bogdanm	82:6473597d706e	2460	*/
bogdanm	82:6473597d706e	2461	typedef union _hw_dma_cint
bogdanm	82:6473597d706e	2462	{
bogdanm	82:6473597d706e	2463	uint8_t U;
bogdanm	82:6473597d706e	2464	struct _hw_dma_cint_bitfields
bogdanm	82:6473597d706e	2465	{
bogdanm	82:6473597d706e	2466	uint8_t CINT : 4; //!< [3:0] Clear Interrupt Request
bogdanm	82:6473597d706e	2467	uint8_t RESERVED0 : 2; //!< [5:4]
bogdanm	82:6473597d706e	2468	uint8_t CAIR : 1; //!< [6] Clear All Interrupt Requests
bogdanm	82:6473597d706e	2469	uint8_t NOP : 1; //!< [7] No Op enable
bogdanm	82:6473597d706e	2470	} B;
bogdanm	82:6473597d706e	2471	} hw_dma_cint_t;
bogdanm	82:6473597d706e	2472	#endif
bogdanm	82:6473597d706e	2473
bogdanm	82:6473597d706e	2474	/*!
bogdanm	82:6473597d706e	2475	* @name Constants and macros for entire DMA_CINT register
bogdanm	82:6473597d706e	2476	*/
bogdanm	82:6473597d706e	2477	//@{
bogdanm	82:6473597d706e	2478	#define HW_DMA_CINT_ADDR(x) (REGS_DMA_BASE(x) + 0x1FU)
bogdanm	82:6473597d706e	2479
bogdanm	82:6473597d706e	2480	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2481	#define HW_DMA_CINT(x) ((__O hw_dma_cint_t ) HW_DMA_CINT_ADDR(x))
bogdanm	82:6473597d706e	2482	#define HW_DMA_CINT_RD(x) (HW_DMA_CINT(x).U)
bogdanm	82:6473597d706e	2483	#define HW_DMA_CINT_WR(x, v) (HW_DMA_CINT(x).U = (v))
bogdanm	82:6473597d706e	2484	#endif
bogdanm	82:6473597d706e	2485	//@}
bogdanm	82:6473597d706e	2486
bogdanm	82:6473597d706e	2487	/*
bogdanm	82:6473597d706e	2488	* Constants & macros for individual DMA_CINT bitfields
bogdanm	82:6473597d706e	2489	*/
bogdanm	82:6473597d706e	2490
bogdanm	82:6473597d706e	2491	/*!
bogdanm	82:6473597d706e	2492	* @name Register DMA_CINT, field CINT[3:0] (WORZ)
bogdanm	82:6473597d706e	2493	*
bogdanm	82:6473597d706e	2494	* Clears the corresponding bit in INT
bogdanm	82:6473597d706e	2495	*/
bogdanm	82:6473597d706e	2496	//@{
bogdanm	82:6473597d706e	2497	#define BP_DMA_CINT_CINT (0U) //!< Bit position for DMA_CINT_CINT.
bogdanm	82:6473597d706e	2498	#define BM_DMA_CINT_CINT (0x0FU) //!< Bit mask for DMA_CINT_CINT.
bogdanm	82:6473597d706e	2499	#define BS_DMA_CINT_CINT (4U) //!< Bit field size in bits for DMA_CINT_CINT.
bogdanm	82:6473597d706e	2500
bogdanm	82:6473597d706e	2501	//! @brief Format value for bitfield DMA_CINT_CINT.
bogdanm	82:6473597d706e	2502	#define BF_DMA_CINT_CINT(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_CINT), uint8_t) & BM_DMA_CINT_CINT)
bogdanm	82:6473597d706e	2503
bogdanm	82:6473597d706e	2504	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2505	//! @brief Set the CINT field to a new value.
bogdanm	82:6473597d706e	2506	#define BW_DMA_CINT_CINT(x, v) (HW_DMA_CINT_WR(x, (HW_DMA_CINT_RD(x) & ~BM_DMA_CINT_CINT) \| BF_DMA_CINT_CINT(v)))
bogdanm	82:6473597d706e	2507	#endif
bogdanm	82:6473597d706e	2508	//@}
bogdanm	82:6473597d706e	2509
bogdanm	82:6473597d706e	2510	/*!
bogdanm	82:6473597d706e	2511	* @name Register DMA_CINT, field CAIR[6] (WORZ)
bogdanm	82:6473597d706e	2512	*
bogdanm	82:6473597d706e	2513	* Values:
bogdanm	82:6473597d706e	2514	* - 0 - Clear only the INT bit specified in the CINT field
bogdanm	82:6473597d706e	2515	* - 1 - Clear all bits in INT
bogdanm	82:6473597d706e	2516	*/
bogdanm	82:6473597d706e	2517	//@{
bogdanm	82:6473597d706e	2518	#define BP_DMA_CINT_CAIR (6U) //!< Bit position for DMA_CINT_CAIR.
bogdanm	82:6473597d706e	2519	#define BM_DMA_CINT_CAIR (0x40U) //!< Bit mask for DMA_CINT_CAIR.
bogdanm	82:6473597d706e	2520	#define BS_DMA_CINT_CAIR (1U) //!< Bit field size in bits for DMA_CINT_CAIR.
bogdanm	82:6473597d706e	2521
bogdanm	82:6473597d706e	2522	//! @brief Format value for bitfield DMA_CINT_CAIR.
bogdanm	82:6473597d706e	2523	#define BF_DMA_CINT_CAIR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_CAIR), uint8_t) & BM_DMA_CINT_CAIR)
bogdanm	82:6473597d706e	2524
bogdanm	82:6473597d706e	2525	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2526	//! @brief Set the CAIR field to a new value.
bogdanm	82:6473597d706e	2527	#define BW_DMA_CINT_CAIR(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_CAIR) = (v))
bogdanm	82:6473597d706e	2528	#endif
bogdanm	82:6473597d706e	2529	//@}
bogdanm	82:6473597d706e	2530
bogdanm	82:6473597d706e	2531	/*!
bogdanm	82:6473597d706e	2532	* @name Register DMA_CINT, field NOP[7] (WORZ)
bogdanm	82:6473597d706e	2533	*
bogdanm	82:6473597d706e	2534	* Values:
bogdanm	82:6473597d706e	2535	* - 0 - Normal operation
bogdanm	82:6473597d706e	2536	* - 1 - No operation, ignore the other bits in this register
bogdanm	82:6473597d706e	2537	*/
bogdanm	82:6473597d706e	2538	//@{
bogdanm	82:6473597d706e	2539	#define BP_DMA_CINT_NOP (7U) //!< Bit position for DMA_CINT_NOP.
bogdanm	82:6473597d706e	2540	#define BM_DMA_CINT_NOP (0x80U) //!< Bit mask for DMA_CINT_NOP.
bogdanm	82:6473597d706e	2541	#define BS_DMA_CINT_NOP (1U) //!< Bit field size in bits for DMA_CINT_NOP.
bogdanm	82:6473597d706e	2542
bogdanm	82:6473597d706e	2543	//! @brief Format value for bitfield DMA_CINT_NOP.
bogdanm	82:6473597d706e	2544	#define BF_DMA_CINT_NOP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_CINT_NOP), uint8_t) & BM_DMA_CINT_NOP)
bogdanm	82:6473597d706e	2545
bogdanm	82:6473597d706e	2546	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2547	//! @brief Set the NOP field to a new value.
bogdanm	82:6473597d706e	2548	#define BW_DMA_CINT_NOP(x, v) (BITBAND_ACCESS8(HW_DMA_CINT_ADDR(x), BP_DMA_CINT_NOP) = (v))
bogdanm	82:6473597d706e	2549	#endif
bogdanm	82:6473597d706e	2550	//@}
bogdanm	82:6473597d706e	2551
bogdanm	82:6473597d706e	2552	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2553	// HW_DMA_INT - Interrupt Request Register
bogdanm	82:6473597d706e	2554	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	2555
bogdanm	82:6473597d706e	2556	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2557	/*!
bogdanm	82:6473597d706e	2558	* @brief HW_DMA_INT - Interrupt Request Register (RW)
bogdanm	82:6473597d706e	2559	*
bogdanm	82:6473597d706e	2560	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	2561	*
bogdanm	82:6473597d706e	2562	* The INT register provides a bit map for the 16 channels signaling the
bogdanm	82:6473597d706e	2563	* presence of an interrupt request for each channel. Depending on the appropriate bit
bogdanm	82:6473597d706e	2564	* setting in the transfer-control descriptors, the eDMA engine generates an
bogdanm	82:6473597d706e	2565	* interrupt on data transfer completion. The outputs of this register are directly
bogdanm	82:6473597d706e	2566	* routed to the interrupt controller (INTC). During the interrupt-service routine
bogdanm	82:6473597d706e	2567	* associated with any given channel, it is the software's responsibility to
bogdanm	82:6473597d706e	2568	* clear the appropriate bit, negating the interrupt request. Typically, a write to
bogdanm	82:6473597d706e	2569	* the CINT register in the interrupt service routine is used for this purpose.
bogdanm	82:6473597d706e	2570	* The state of any given channel's interrupt request is directly affected by
bogdanm	82:6473597d706e	2571	* writes to this register; it is also affected by writes to the CINT register. On
bogdanm	82:6473597d706e	2572	* writes to INT, a 1 in any bit position clears the corresponding channel's
bogdanm	82:6473597d706e	2573	* interrupt request. A zero in any bit position has no affect on the corresponding
bogdanm	82:6473597d706e	2574	* channel's current interrupt status. The CINT register is provided so the interrupt
bogdanm	82:6473597d706e	2575	* request for a single channel can easily be cleared without the need to
bogdanm	82:6473597d706e	2576	* perform a read-modify-write sequence to the INT register.
bogdanm	82:6473597d706e	2577	*/
bogdanm	82:6473597d706e	2578	typedef union _hw_dma_int
bogdanm	82:6473597d706e	2579	{
bogdanm	82:6473597d706e	2580	uint32_t U;
bogdanm	82:6473597d706e	2581	struct _hw_dma_int_bitfields
bogdanm	82:6473597d706e	2582	{
bogdanm	82:6473597d706e	2583	uint32_t INT0 : 1; //!< [0] Interrupt Request 0
bogdanm	82:6473597d706e	2584	uint32_t INT1 : 1; //!< [1] Interrupt Request 1
bogdanm	82:6473597d706e	2585	uint32_t INT2 : 1; //!< [2] Interrupt Request 2
bogdanm	82:6473597d706e	2586	uint32_t INT3 : 1; //!< [3] Interrupt Request 3
bogdanm	82:6473597d706e	2587	uint32_t INT4 : 1; //!< [4] Interrupt Request 4
bogdanm	82:6473597d706e	2588	uint32_t INT5 : 1; //!< [5] Interrupt Request 5
bogdanm	82:6473597d706e	2589	uint32_t INT6 : 1; //!< [6] Interrupt Request 6
bogdanm	82:6473597d706e	2590	uint32_t INT7 : 1; //!< [7] Interrupt Request 7
bogdanm	82:6473597d706e	2591	uint32_t INT8 : 1; //!< [8] Interrupt Request 8
bogdanm	82:6473597d706e	2592	uint32_t INT9 : 1; //!< [9] Interrupt Request 9
bogdanm	82:6473597d706e	2593	uint32_t INT10 : 1; //!< [10] Interrupt Request 10
bogdanm	82:6473597d706e	2594	uint32_t INT11 : 1; //!< [11] Interrupt Request 11
bogdanm	82:6473597d706e	2595	uint32_t INT12 : 1; //!< [12] Interrupt Request 12
bogdanm	82:6473597d706e	2596	uint32_t INT13 : 1; //!< [13] Interrupt Request 13
bogdanm	82:6473597d706e	2597	uint32_t INT14 : 1; //!< [14] Interrupt Request 14
bogdanm	82:6473597d706e	2598	uint32_t INT15 : 1; //!< [15] Interrupt Request 15
bogdanm	82:6473597d706e	2599	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	2600	} B;
bogdanm	82:6473597d706e	2601	} hw_dma_int_t;
bogdanm	82:6473597d706e	2602	#endif
bogdanm	82:6473597d706e	2603
bogdanm	82:6473597d706e	2604	/*!
bogdanm	82:6473597d706e	2605	* @name Constants and macros for entire DMA_INT register
bogdanm	82:6473597d706e	2606	*/
bogdanm	82:6473597d706e	2607	//@{
bogdanm	82:6473597d706e	2608	#define HW_DMA_INT_ADDR(x) (REGS_DMA_BASE(x) + 0x24U)
bogdanm	82:6473597d706e	2609
bogdanm	82:6473597d706e	2610	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2611	#define HW_DMA_INT(x) ((__IO hw_dma_int_t ) HW_DMA_INT_ADDR(x))
bogdanm	82:6473597d706e	2612	#define HW_DMA_INT_RD(x) (HW_DMA_INT(x).U)
bogdanm	82:6473597d706e	2613	#define HW_DMA_INT_WR(x, v) (HW_DMA_INT(x).U = (v))
bogdanm	82:6473597d706e	2614	#define HW_DMA_INT_SET(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) \| (v)))
bogdanm	82:6473597d706e	2615	#define HW_DMA_INT_CLR(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) & ~(v)))
bogdanm	82:6473597d706e	2616	#define HW_DMA_INT_TOG(x, v) (HW_DMA_INT_WR(x, HW_DMA_INT_RD(x) ^ (v)))
bogdanm	82:6473597d706e	2617	#endif
bogdanm	82:6473597d706e	2618	//@}
bogdanm	82:6473597d706e	2619
bogdanm	82:6473597d706e	2620	/*
bogdanm	82:6473597d706e	2621	* Constants & macros for individual DMA_INT bitfields
bogdanm	82:6473597d706e	2622	*/
bogdanm	82:6473597d706e	2623
bogdanm	82:6473597d706e	2624	/*!
bogdanm	82:6473597d706e	2625	* @name Register DMA_INT, field INT0[0] (W1C)
bogdanm	82:6473597d706e	2626	*
bogdanm	82:6473597d706e	2627	* Values:
bogdanm	82:6473597d706e	2628	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2629	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2630	*/
bogdanm	82:6473597d706e	2631	//@{
bogdanm	82:6473597d706e	2632	#define BP_DMA_INT_INT0 (0U) //!< Bit position for DMA_INT_INT0.
bogdanm	82:6473597d706e	2633	#define BM_DMA_INT_INT0 (0x00000001U) //!< Bit mask for DMA_INT_INT0.
bogdanm	82:6473597d706e	2634	#define BS_DMA_INT_INT0 (1U) //!< Bit field size in bits for DMA_INT_INT0.
bogdanm	82:6473597d706e	2635
bogdanm	82:6473597d706e	2636	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2637	//! @brief Read current value of the DMA_INT_INT0 field.
bogdanm	82:6473597d706e	2638	#define BR_DMA_INT_INT0(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0))
bogdanm	82:6473597d706e	2639	#endif
bogdanm	82:6473597d706e	2640
bogdanm	82:6473597d706e	2641	//! @brief Format value for bitfield DMA_INT_INT0.
bogdanm	82:6473597d706e	2642	#define BF_DMA_INT_INT0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT0), uint32_t) & BM_DMA_INT_INT0)
bogdanm	82:6473597d706e	2643
bogdanm	82:6473597d706e	2644	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2645	//! @brief Set the INT0 field to a new value.
bogdanm	82:6473597d706e	2646	#define BW_DMA_INT_INT0(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT0) = (v))
bogdanm	82:6473597d706e	2647	#endif
bogdanm	82:6473597d706e	2648	//@}
bogdanm	82:6473597d706e	2649
bogdanm	82:6473597d706e	2650	/*!
bogdanm	82:6473597d706e	2651	* @name Register DMA_INT, field INT1[1] (W1C)
bogdanm	82:6473597d706e	2652	*
bogdanm	82:6473597d706e	2653	* Values:
bogdanm	82:6473597d706e	2654	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2655	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2656	*/
bogdanm	82:6473597d706e	2657	//@{
bogdanm	82:6473597d706e	2658	#define BP_DMA_INT_INT1 (1U) //!< Bit position for DMA_INT_INT1.
bogdanm	82:6473597d706e	2659	#define BM_DMA_INT_INT1 (0x00000002U) //!< Bit mask for DMA_INT_INT1.
bogdanm	82:6473597d706e	2660	#define BS_DMA_INT_INT1 (1U) //!< Bit field size in bits for DMA_INT_INT1.
bogdanm	82:6473597d706e	2661
bogdanm	82:6473597d706e	2662	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2663	//! @brief Read current value of the DMA_INT_INT1 field.
bogdanm	82:6473597d706e	2664	#define BR_DMA_INT_INT1(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1))
bogdanm	82:6473597d706e	2665	#endif
bogdanm	82:6473597d706e	2666
bogdanm	82:6473597d706e	2667	//! @brief Format value for bitfield DMA_INT_INT1.
bogdanm	82:6473597d706e	2668	#define BF_DMA_INT_INT1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT1), uint32_t) & BM_DMA_INT_INT1)
bogdanm	82:6473597d706e	2669
bogdanm	82:6473597d706e	2670	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2671	//! @brief Set the INT1 field to a new value.
bogdanm	82:6473597d706e	2672	#define BW_DMA_INT_INT1(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT1) = (v))
bogdanm	82:6473597d706e	2673	#endif
bogdanm	82:6473597d706e	2674	//@}
bogdanm	82:6473597d706e	2675
bogdanm	82:6473597d706e	2676	/*!
bogdanm	82:6473597d706e	2677	* @name Register DMA_INT, field INT2[2] (W1C)
bogdanm	82:6473597d706e	2678	*
bogdanm	82:6473597d706e	2679	* Values:
bogdanm	82:6473597d706e	2680	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2681	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2682	*/
bogdanm	82:6473597d706e	2683	//@{
bogdanm	82:6473597d706e	2684	#define BP_DMA_INT_INT2 (2U) //!< Bit position for DMA_INT_INT2.
bogdanm	82:6473597d706e	2685	#define BM_DMA_INT_INT2 (0x00000004U) //!< Bit mask for DMA_INT_INT2.
bogdanm	82:6473597d706e	2686	#define BS_DMA_INT_INT2 (1U) //!< Bit field size in bits for DMA_INT_INT2.
bogdanm	82:6473597d706e	2687
bogdanm	82:6473597d706e	2688	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2689	//! @brief Read current value of the DMA_INT_INT2 field.
bogdanm	82:6473597d706e	2690	#define BR_DMA_INT_INT2(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2))
bogdanm	82:6473597d706e	2691	#endif
bogdanm	82:6473597d706e	2692
bogdanm	82:6473597d706e	2693	//! @brief Format value for bitfield DMA_INT_INT2.
bogdanm	82:6473597d706e	2694	#define BF_DMA_INT_INT2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT2), uint32_t) & BM_DMA_INT_INT2)
bogdanm	82:6473597d706e	2695
bogdanm	82:6473597d706e	2696	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2697	//! @brief Set the INT2 field to a new value.
bogdanm	82:6473597d706e	2698	#define BW_DMA_INT_INT2(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT2) = (v))
bogdanm	82:6473597d706e	2699	#endif
bogdanm	82:6473597d706e	2700	//@}
bogdanm	82:6473597d706e	2701
bogdanm	82:6473597d706e	2702	/*!
bogdanm	82:6473597d706e	2703	* @name Register DMA_INT, field INT3[3] (W1C)
bogdanm	82:6473597d706e	2704	*
bogdanm	82:6473597d706e	2705	* Values:
bogdanm	82:6473597d706e	2706	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2707	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2708	*/
bogdanm	82:6473597d706e	2709	//@{
bogdanm	82:6473597d706e	2710	#define BP_DMA_INT_INT3 (3U) //!< Bit position for DMA_INT_INT3.
bogdanm	82:6473597d706e	2711	#define BM_DMA_INT_INT3 (0x00000008U) //!< Bit mask for DMA_INT_INT3.
bogdanm	82:6473597d706e	2712	#define BS_DMA_INT_INT3 (1U) //!< Bit field size in bits for DMA_INT_INT3.
bogdanm	82:6473597d706e	2713
bogdanm	82:6473597d706e	2714	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2715	//! @brief Read current value of the DMA_INT_INT3 field.
bogdanm	82:6473597d706e	2716	#define BR_DMA_INT_INT3(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3))
bogdanm	82:6473597d706e	2717	#endif
bogdanm	82:6473597d706e	2718
bogdanm	82:6473597d706e	2719	//! @brief Format value for bitfield DMA_INT_INT3.
bogdanm	82:6473597d706e	2720	#define BF_DMA_INT_INT3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT3), uint32_t) & BM_DMA_INT_INT3)
bogdanm	82:6473597d706e	2721
bogdanm	82:6473597d706e	2722	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2723	//! @brief Set the INT3 field to a new value.
bogdanm	82:6473597d706e	2724	#define BW_DMA_INT_INT3(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT3) = (v))
bogdanm	82:6473597d706e	2725	#endif
bogdanm	82:6473597d706e	2726	//@}
bogdanm	82:6473597d706e	2727
bogdanm	82:6473597d706e	2728	/*!
bogdanm	82:6473597d706e	2729	* @name Register DMA_INT, field INT4[4] (W1C)
bogdanm	82:6473597d706e	2730	*
bogdanm	82:6473597d706e	2731	* Values:
bogdanm	82:6473597d706e	2732	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2733	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2734	*/
bogdanm	82:6473597d706e	2735	//@{
bogdanm	82:6473597d706e	2736	#define BP_DMA_INT_INT4 (4U) //!< Bit position for DMA_INT_INT4.
bogdanm	82:6473597d706e	2737	#define BM_DMA_INT_INT4 (0x00000010U) //!< Bit mask for DMA_INT_INT4.
bogdanm	82:6473597d706e	2738	#define BS_DMA_INT_INT4 (1U) //!< Bit field size in bits for DMA_INT_INT4.
bogdanm	82:6473597d706e	2739
bogdanm	82:6473597d706e	2740	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2741	//! @brief Read current value of the DMA_INT_INT4 field.
bogdanm	82:6473597d706e	2742	#define BR_DMA_INT_INT4(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4))
bogdanm	82:6473597d706e	2743	#endif
bogdanm	82:6473597d706e	2744
bogdanm	82:6473597d706e	2745	//! @brief Format value for bitfield DMA_INT_INT4.
bogdanm	82:6473597d706e	2746	#define BF_DMA_INT_INT4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT4), uint32_t) & BM_DMA_INT_INT4)
bogdanm	82:6473597d706e	2747
bogdanm	82:6473597d706e	2748	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2749	//! @brief Set the INT4 field to a new value.
bogdanm	82:6473597d706e	2750	#define BW_DMA_INT_INT4(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT4) = (v))
bogdanm	82:6473597d706e	2751	#endif
bogdanm	82:6473597d706e	2752	//@}
bogdanm	82:6473597d706e	2753
bogdanm	82:6473597d706e	2754	/*!
bogdanm	82:6473597d706e	2755	* @name Register DMA_INT, field INT5[5] (W1C)
bogdanm	82:6473597d706e	2756	*
bogdanm	82:6473597d706e	2757	* Values:
bogdanm	82:6473597d706e	2758	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2759	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2760	*/
bogdanm	82:6473597d706e	2761	//@{
bogdanm	82:6473597d706e	2762	#define BP_DMA_INT_INT5 (5U) //!< Bit position for DMA_INT_INT5.
bogdanm	82:6473597d706e	2763	#define BM_DMA_INT_INT5 (0x00000020U) //!< Bit mask for DMA_INT_INT5.
bogdanm	82:6473597d706e	2764	#define BS_DMA_INT_INT5 (1U) //!< Bit field size in bits for DMA_INT_INT5.
bogdanm	82:6473597d706e	2765
bogdanm	82:6473597d706e	2766	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2767	//! @brief Read current value of the DMA_INT_INT5 field.
bogdanm	82:6473597d706e	2768	#define BR_DMA_INT_INT5(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5))
bogdanm	82:6473597d706e	2769	#endif
bogdanm	82:6473597d706e	2770
bogdanm	82:6473597d706e	2771	//! @brief Format value for bitfield DMA_INT_INT5.
bogdanm	82:6473597d706e	2772	#define BF_DMA_INT_INT5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT5), uint32_t) & BM_DMA_INT_INT5)
bogdanm	82:6473597d706e	2773
bogdanm	82:6473597d706e	2774	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2775	//! @brief Set the INT5 field to a new value.
bogdanm	82:6473597d706e	2776	#define BW_DMA_INT_INT5(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT5) = (v))
bogdanm	82:6473597d706e	2777	#endif
bogdanm	82:6473597d706e	2778	//@}
bogdanm	82:6473597d706e	2779
bogdanm	82:6473597d706e	2780	/*!
bogdanm	82:6473597d706e	2781	* @name Register DMA_INT, field INT6[6] (W1C)
bogdanm	82:6473597d706e	2782	*
bogdanm	82:6473597d706e	2783	* Values:
bogdanm	82:6473597d706e	2784	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2785	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2786	*/
bogdanm	82:6473597d706e	2787	//@{
bogdanm	82:6473597d706e	2788	#define BP_DMA_INT_INT6 (6U) //!< Bit position for DMA_INT_INT6.
bogdanm	82:6473597d706e	2789	#define BM_DMA_INT_INT6 (0x00000040U) //!< Bit mask for DMA_INT_INT6.
bogdanm	82:6473597d706e	2790	#define BS_DMA_INT_INT6 (1U) //!< Bit field size in bits for DMA_INT_INT6.
bogdanm	82:6473597d706e	2791
bogdanm	82:6473597d706e	2792	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2793	//! @brief Read current value of the DMA_INT_INT6 field.
bogdanm	82:6473597d706e	2794	#define BR_DMA_INT_INT6(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6))
bogdanm	82:6473597d706e	2795	#endif
bogdanm	82:6473597d706e	2796
bogdanm	82:6473597d706e	2797	//! @brief Format value for bitfield DMA_INT_INT6.
bogdanm	82:6473597d706e	2798	#define BF_DMA_INT_INT6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT6), uint32_t) & BM_DMA_INT_INT6)
bogdanm	82:6473597d706e	2799
bogdanm	82:6473597d706e	2800	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2801	//! @brief Set the INT6 field to a new value.
bogdanm	82:6473597d706e	2802	#define BW_DMA_INT_INT6(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT6) = (v))
bogdanm	82:6473597d706e	2803	#endif
bogdanm	82:6473597d706e	2804	//@}
bogdanm	82:6473597d706e	2805
bogdanm	82:6473597d706e	2806	/*!
bogdanm	82:6473597d706e	2807	* @name Register DMA_INT, field INT7[7] (W1C)
bogdanm	82:6473597d706e	2808	*
bogdanm	82:6473597d706e	2809	* Values:
bogdanm	82:6473597d706e	2810	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2811	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2812	*/
bogdanm	82:6473597d706e	2813	//@{
bogdanm	82:6473597d706e	2814	#define BP_DMA_INT_INT7 (7U) //!< Bit position for DMA_INT_INT7.
bogdanm	82:6473597d706e	2815	#define BM_DMA_INT_INT7 (0x00000080U) //!< Bit mask for DMA_INT_INT7.
bogdanm	82:6473597d706e	2816	#define BS_DMA_INT_INT7 (1U) //!< Bit field size in bits for DMA_INT_INT7.
bogdanm	82:6473597d706e	2817
bogdanm	82:6473597d706e	2818	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2819	//! @brief Read current value of the DMA_INT_INT7 field.
bogdanm	82:6473597d706e	2820	#define BR_DMA_INT_INT7(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7))
bogdanm	82:6473597d706e	2821	#endif
bogdanm	82:6473597d706e	2822
bogdanm	82:6473597d706e	2823	//! @brief Format value for bitfield DMA_INT_INT7.
bogdanm	82:6473597d706e	2824	#define BF_DMA_INT_INT7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT7), uint32_t) & BM_DMA_INT_INT7)
bogdanm	82:6473597d706e	2825
bogdanm	82:6473597d706e	2826	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2827	//! @brief Set the INT7 field to a new value.
bogdanm	82:6473597d706e	2828	#define BW_DMA_INT_INT7(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT7) = (v))
bogdanm	82:6473597d706e	2829	#endif
bogdanm	82:6473597d706e	2830	//@}
bogdanm	82:6473597d706e	2831
bogdanm	82:6473597d706e	2832	/*!
bogdanm	82:6473597d706e	2833	* @name Register DMA_INT, field INT8[8] (W1C)
bogdanm	82:6473597d706e	2834	*
bogdanm	82:6473597d706e	2835	* Values:
bogdanm	82:6473597d706e	2836	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2837	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2838	*/
bogdanm	82:6473597d706e	2839	//@{
bogdanm	82:6473597d706e	2840	#define BP_DMA_INT_INT8 (8U) //!< Bit position for DMA_INT_INT8.
bogdanm	82:6473597d706e	2841	#define BM_DMA_INT_INT8 (0x00000100U) //!< Bit mask for DMA_INT_INT8.
bogdanm	82:6473597d706e	2842	#define BS_DMA_INT_INT8 (1U) //!< Bit field size in bits for DMA_INT_INT8.
bogdanm	82:6473597d706e	2843
bogdanm	82:6473597d706e	2844	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2845	//! @brief Read current value of the DMA_INT_INT8 field.
bogdanm	82:6473597d706e	2846	#define BR_DMA_INT_INT8(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8))
bogdanm	82:6473597d706e	2847	#endif
bogdanm	82:6473597d706e	2848
bogdanm	82:6473597d706e	2849	//! @brief Format value for bitfield DMA_INT_INT8.
bogdanm	82:6473597d706e	2850	#define BF_DMA_INT_INT8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT8), uint32_t) & BM_DMA_INT_INT8)
bogdanm	82:6473597d706e	2851
bogdanm	82:6473597d706e	2852	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2853	//! @brief Set the INT8 field to a new value.
bogdanm	82:6473597d706e	2854	#define BW_DMA_INT_INT8(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT8) = (v))
bogdanm	82:6473597d706e	2855	#endif
bogdanm	82:6473597d706e	2856	//@}
bogdanm	82:6473597d706e	2857
bogdanm	82:6473597d706e	2858	/*!
bogdanm	82:6473597d706e	2859	* @name Register DMA_INT, field INT9[9] (W1C)
bogdanm	82:6473597d706e	2860	*
bogdanm	82:6473597d706e	2861	* Values:
bogdanm	82:6473597d706e	2862	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2863	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2864	*/
bogdanm	82:6473597d706e	2865	//@{
bogdanm	82:6473597d706e	2866	#define BP_DMA_INT_INT9 (9U) //!< Bit position for DMA_INT_INT9.
bogdanm	82:6473597d706e	2867	#define BM_DMA_INT_INT9 (0x00000200U) //!< Bit mask for DMA_INT_INT9.
bogdanm	82:6473597d706e	2868	#define BS_DMA_INT_INT9 (1U) //!< Bit field size in bits for DMA_INT_INT9.
bogdanm	82:6473597d706e	2869
bogdanm	82:6473597d706e	2870	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2871	//! @brief Read current value of the DMA_INT_INT9 field.
bogdanm	82:6473597d706e	2872	#define BR_DMA_INT_INT9(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9))
bogdanm	82:6473597d706e	2873	#endif
bogdanm	82:6473597d706e	2874
bogdanm	82:6473597d706e	2875	//! @brief Format value for bitfield DMA_INT_INT9.
bogdanm	82:6473597d706e	2876	#define BF_DMA_INT_INT9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT9), uint32_t) & BM_DMA_INT_INT9)
bogdanm	82:6473597d706e	2877
bogdanm	82:6473597d706e	2878	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2879	//! @brief Set the INT9 field to a new value.
bogdanm	82:6473597d706e	2880	#define BW_DMA_INT_INT9(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT9) = (v))
bogdanm	82:6473597d706e	2881	#endif
bogdanm	82:6473597d706e	2882	//@}
bogdanm	82:6473597d706e	2883
bogdanm	82:6473597d706e	2884	/*!
bogdanm	82:6473597d706e	2885	* @name Register DMA_INT, field INT10[10] (W1C)
bogdanm	82:6473597d706e	2886	*
bogdanm	82:6473597d706e	2887	* Values:
bogdanm	82:6473597d706e	2888	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2889	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2890	*/
bogdanm	82:6473597d706e	2891	//@{
bogdanm	82:6473597d706e	2892	#define BP_DMA_INT_INT10 (10U) //!< Bit position for DMA_INT_INT10.
bogdanm	82:6473597d706e	2893	#define BM_DMA_INT_INT10 (0x00000400U) //!< Bit mask for DMA_INT_INT10.
bogdanm	82:6473597d706e	2894	#define BS_DMA_INT_INT10 (1U) //!< Bit field size in bits for DMA_INT_INT10.
bogdanm	82:6473597d706e	2895
bogdanm	82:6473597d706e	2896	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2897	//! @brief Read current value of the DMA_INT_INT10 field.
bogdanm	82:6473597d706e	2898	#define BR_DMA_INT_INT10(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10))
bogdanm	82:6473597d706e	2899	#endif
bogdanm	82:6473597d706e	2900
bogdanm	82:6473597d706e	2901	//! @brief Format value for bitfield DMA_INT_INT10.
bogdanm	82:6473597d706e	2902	#define BF_DMA_INT_INT10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT10), uint32_t) & BM_DMA_INT_INT10)
bogdanm	82:6473597d706e	2903
bogdanm	82:6473597d706e	2904	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2905	//! @brief Set the INT10 field to a new value.
bogdanm	82:6473597d706e	2906	#define BW_DMA_INT_INT10(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT10) = (v))
bogdanm	82:6473597d706e	2907	#endif
bogdanm	82:6473597d706e	2908	//@}
bogdanm	82:6473597d706e	2909
bogdanm	82:6473597d706e	2910	/*!
bogdanm	82:6473597d706e	2911	* @name Register DMA_INT, field INT11[11] (W1C)
bogdanm	82:6473597d706e	2912	*
bogdanm	82:6473597d706e	2913	* Values:
bogdanm	82:6473597d706e	2914	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2915	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2916	*/
bogdanm	82:6473597d706e	2917	//@{
bogdanm	82:6473597d706e	2918	#define BP_DMA_INT_INT11 (11U) //!< Bit position for DMA_INT_INT11.
bogdanm	82:6473597d706e	2919	#define BM_DMA_INT_INT11 (0x00000800U) //!< Bit mask for DMA_INT_INT11.
bogdanm	82:6473597d706e	2920	#define BS_DMA_INT_INT11 (1U) //!< Bit field size in bits for DMA_INT_INT11.
bogdanm	82:6473597d706e	2921
bogdanm	82:6473597d706e	2922	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2923	//! @brief Read current value of the DMA_INT_INT11 field.
bogdanm	82:6473597d706e	2924	#define BR_DMA_INT_INT11(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11))
bogdanm	82:6473597d706e	2925	#endif
bogdanm	82:6473597d706e	2926
bogdanm	82:6473597d706e	2927	//! @brief Format value for bitfield DMA_INT_INT11.
bogdanm	82:6473597d706e	2928	#define BF_DMA_INT_INT11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT11), uint32_t) & BM_DMA_INT_INT11)
bogdanm	82:6473597d706e	2929
bogdanm	82:6473597d706e	2930	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2931	//! @brief Set the INT11 field to a new value.
bogdanm	82:6473597d706e	2932	#define BW_DMA_INT_INT11(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT11) = (v))
bogdanm	82:6473597d706e	2933	#endif
bogdanm	82:6473597d706e	2934	//@}
bogdanm	82:6473597d706e	2935
bogdanm	82:6473597d706e	2936	/*!
bogdanm	82:6473597d706e	2937	* @name Register DMA_INT, field INT12[12] (W1C)
bogdanm	82:6473597d706e	2938	*
bogdanm	82:6473597d706e	2939	* Values:
bogdanm	82:6473597d706e	2940	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2941	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2942	*/
bogdanm	82:6473597d706e	2943	//@{
bogdanm	82:6473597d706e	2944	#define BP_DMA_INT_INT12 (12U) //!< Bit position for DMA_INT_INT12.
bogdanm	82:6473597d706e	2945	#define BM_DMA_INT_INT12 (0x00001000U) //!< Bit mask for DMA_INT_INT12.
bogdanm	82:6473597d706e	2946	#define BS_DMA_INT_INT12 (1U) //!< Bit field size in bits for DMA_INT_INT12.
bogdanm	82:6473597d706e	2947
bogdanm	82:6473597d706e	2948	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2949	//! @brief Read current value of the DMA_INT_INT12 field.
bogdanm	82:6473597d706e	2950	#define BR_DMA_INT_INT12(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12))
bogdanm	82:6473597d706e	2951	#endif
bogdanm	82:6473597d706e	2952
bogdanm	82:6473597d706e	2953	//! @brief Format value for bitfield DMA_INT_INT12.
bogdanm	82:6473597d706e	2954	#define BF_DMA_INT_INT12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT12), uint32_t) & BM_DMA_INT_INT12)
bogdanm	82:6473597d706e	2955
bogdanm	82:6473597d706e	2956	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2957	//! @brief Set the INT12 field to a new value.
bogdanm	82:6473597d706e	2958	#define BW_DMA_INT_INT12(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT12) = (v))
bogdanm	82:6473597d706e	2959	#endif
bogdanm	82:6473597d706e	2960	//@}
bogdanm	82:6473597d706e	2961
bogdanm	82:6473597d706e	2962	/*!
bogdanm	82:6473597d706e	2963	* @name Register DMA_INT, field INT13[13] (W1C)
bogdanm	82:6473597d706e	2964	*
bogdanm	82:6473597d706e	2965	* Values:
bogdanm	82:6473597d706e	2966	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2967	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2968	*/
bogdanm	82:6473597d706e	2969	//@{
bogdanm	82:6473597d706e	2970	#define BP_DMA_INT_INT13 (13U) //!< Bit position for DMA_INT_INT13.
bogdanm	82:6473597d706e	2971	#define BM_DMA_INT_INT13 (0x00002000U) //!< Bit mask for DMA_INT_INT13.
bogdanm	82:6473597d706e	2972	#define BS_DMA_INT_INT13 (1U) //!< Bit field size in bits for DMA_INT_INT13.
bogdanm	82:6473597d706e	2973
bogdanm	82:6473597d706e	2974	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2975	//! @brief Read current value of the DMA_INT_INT13 field.
bogdanm	82:6473597d706e	2976	#define BR_DMA_INT_INT13(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13))
bogdanm	82:6473597d706e	2977	#endif
bogdanm	82:6473597d706e	2978
bogdanm	82:6473597d706e	2979	//! @brief Format value for bitfield DMA_INT_INT13.
bogdanm	82:6473597d706e	2980	#define BF_DMA_INT_INT13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT13), uint32_t) & BM_DMA_INT_INT13)
bogdanm	82:6473597d706e	2981
bogdanm	82:6473597d706e	2982	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	2983	//! @brief Set the INT13 field to a new value.
bogdanm	82:6473597d706e	2984	#define BW_DMA_INT_INT13(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT13) = (v))
bogdanm	82:6473597d706e	2985	#endif
bogdanm	82:6473597d706e	2986	//@}
bogdanm	82:6473597d706e	2987
bogdanm	82:6473597d706e	2988	/*!
bogdanm	82:6473597d706e	2989	* @name Register DMA_INT, field INT14[14] (W1C)
bogdanm	82:6473597d706e	2990	*
bogdanm	82:6473597d706e	2991	* Values:
bogdanm	82:6473597d706e	2992	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	2993	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	2994	*/
bogdanm	82:6473597d706e	2995	//@{
bogdanm	82:6473597d706e	2996	#define BP_DMA_INT_INT14 (14U) //!< Bit position for DMA_INT_INT14.
bogdanm	82:6473597d706e	2997	#define BM_DMA_INT_INT14 (0x00004000U) //!< Bit mask for DMA_INT_INT14.
bogdanm	82:6473597d706e	2998	#define BS_DMA_INT_INT14 (1U) //!< Bit field size in bits for DMA_INT_INT14.
bogdanm	82:6473597d706e	2999
bogdanm	82:6473597d706e	3000	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3001	//! @brief Read current value of the DMA_INT_INT14 field.
bogdanm	82:6473597d706e	3002	#define BR_DMA_INT_INT14(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14))
bogdanm	82:6473597d706e	3003	#endif
bogdanm	82:6473597d706e	3004
bogdanm	82:6473597d706e	3005	//! @brief Format value for bitfield DMA_INT_INT14.
bogdanm	82:6473597d706e	3006	#define BF_DMA_INT_INT14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT14), uint32_t) & BM_DMA_INT_INT14)
bogdanm	82:6473597d706e	3007
bogdanm	82:6473597d706e	3008	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3009	//! @brief Set the INT14 field to a new value.
bogdanm	82:6473597d706e	3010	#define BW_DMA_INT_INT14(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT14) = (v))
bogdanm	82:6473597d706e	3011	#endif
bogdanm	82:6473597d706e	3012	//@}
bogdanm	82:6473597d706e	3013
bogdanm	82:6473597d706e	3014	/*!
bogdanm	82:6473597d706e	3015	* @name Register DMA_INT, field INT15[15] (W1C)
bogdanm	82:6473597d706e	3016	*
bogdanm	82:6473597d706e	3017	* Values:
bogdanm	82:6473597d706e	3018	* - 0 - The interrupt request for corresponding channel is cleared
bogdanm	82:6473597d706e	3019	* - 1 - The interrupt request for corresponding channel is active
bogdanm	82:6473597d706e	3020	*/
bogdanm	82:6473597d706e	3021	//@{
bogdanm	82:6473597d706e	3022	#define BP_DMA_INT_INT15 (15U) //!< Bit position for DMA_INT_INT15.
bogdanm	82:6473597d706e	3023	#define BM_DMA_INT_INT15 (0x00008000U) //!< Bit mask for DMA_INT_INT15.
bogdanm	82:6473597d706e	3024	#define BS_DMA_INT_INT15 (1U) //!< Bit field size in bits for DMA_INT_INT15.
bogdanm	82:6473597d706e	3025
bogdanm	82:6473597d706e	3026	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3027	//! @brief Read current value of the DMA_INT_INT15 field.
bogdanm	82:6473597d706e	3028	#define BR_DMA_INT_INT15(x) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15))
bogdanm	82:6473597d706e	3029	#endif
bogdanm	82:6473597d706e	3030
bogdanm	82:6473597d706e	3031	//! @brief Format value for bitfield DMA_INT_INT15.
bogdanm	82:6473597d706e	3032	#define BF_DMA_INT_INT15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_INT_INT15), uint32_t) & BM_DMA_INT_INT15)
bogdanm	82:6473597d706e	3033
bogdanm	82:6473597d706e	3034	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3035	//! @brief Set the INT15 field to a new value.
bogdanm	82:6473597d706e	3036	#define BW_DMA_INT_INT15(x, v) (BITBAND_ACCESS32(HW_DMA_INT_ADDR(x), BP_DMA_INT_INT15) = (v))
bogdanm	82:6473597d706e	3037	#endif
bogdanm	82:6473597d706e	3038	//@}
bogdanm	82:6473597d706e	3039
bogdanm	82:6473597d706e	3040	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3041	// HW_DMA_ERR - Error Register
bogdanm	82:6473597d706e	3042	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3043
bogdanm	82:6473597d706e	3044	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3045	/*!
bogdanm	82:6473597d706e	3046	* @brief HW_DMA_ERR - Error Register (RW)
bogdanm	82:6473597d706e	3047	*
bogdanm	82:6473597d706e	3048	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3049	*
bogdanm	82:6473597d706e	3050	* The ERR provides a bit map for the 16 channels, signaling the presence of an
bogdanm	82:6473597d706e	3051	* error for each channel. The eDMA engine signals the occurrence of an error
bogdanm	82:6473597d706e	3052	* condition by setting the appropriate bit in this register. The outputs of this
bogdanm	82:6473597d706e	3053	* register are enabled by the contents of the EEI, and then routed to the
bogdanm	82:6473597d706e	3054	* interrupt controller. During the execution of the interrupt-service routine associated
bogdanm	82:6473597d706e	3055	* with any DMA errors, it is software's responsibility to clear the appropriate
bogdanm	82:6473597d706e	3056	* bit, negating the error-interrupt request. Typically, a write to the CERR in
bogdanm	82:6473597d706e	3057	* the interrupt-service routine is used for this purpose. The normal DMA channel
bogdanm	82:6473597d706e	3058	* completion indicators (setting the transfer control descriptor DONE flag and
bogdanm	82:6473597d706e	3059	* the possible assertion of an interrupt request) are not affected when an error
bogdanm	82:6473597d706e	3060	* is detected. The contents of this register can also be polled because a
bogdanm	82:6473597d706e	3061	* non-zero value indicates the presence of a channel error regardless of the state of
bogdanm	82:6473597d706e	3062	* the EEI. The state of any given channel's error indicators is affected by
bogdanm	82:6473597d706e	3063	* writes to this register; it is also affected by writes to the CERR. On writes to
bogdanm	82:6473597d706e	3064	* the ERR, a one in any bit position clears the corresponding channel's error
bogdanm	82:6473597d706e	3065	* status. A zero in any bit position has no affect on the corresponding channel's
bogdanm	82:6473597d706e	3066	* current error status. The CERR is provided so the error indicator for a single
bogdanm	82:6473597d706e	3067	* channel can easily be cleared.
bogdanm	82:6473597d706e	3068	*/
bogdanm	82:6473597d706e	3069	typedef union _hw_dma_err
bogdanm	82:6473597d706e	3070	{
bogdanm	82:6473597d706e	3071	uint32_t U;
bogdanm	82:6473597d706e	3072	struct _hw_dma_err_bitfields
bogdanm	82:6473597d706e	3073	{
bogdanm	82:6473597d706e	3074	uint32_t ERR0 : 1; //!< [0] Error In Channel 0
bogdanm	82:6473597d706e	3075	uint32_t ERR1 : 1; //!< [1] Error In Channel 1
bogdanm	82:6473597d706e	3076	uint32_t ERR2 : 1; //!< [2] Error In Channel 2
bogdanm	82:6473597d706e	3077	uint32_t ERR3 : 1; //!< [3] Error In Channel 3
bogdanm	82:6473597d706e	3078	uint32_t ERR4 : 1; //!< [4] Error In Channel 4
bogdanm	82:6473597d706e	3079	uint32_t ERR5 : 1; //!< [5] Error In Channel 5
bogdanm	82:6473597d706e	3080	uint32_t ERR6 : 1; //!< [6] Error In Channel 6
bogdanm	82:6473597d706e	3081	uint32_t ERR7 : 1; //!< [7] Error In Channel 7
bogdanm	82:6473597d706e	3082	uint32_t ERR8 : 1; //!< [8] Error In Channel 8
bogdanm	82:6473597d706e	3083	uint32_t ERR9 : 1; //!< [9] Error In Channel 9
bogdanm	82:6473597d706e	3084	uint32_t ERR10 : 1; //!< [10] Error In Channel 10
bogdanm	82:6473597d706e	3085	uint32_t ERR11 : 1; //!< [11] Error In Channel 11
bogdanm	82:6473597d706e	3086	uint32_t ERR12 : 1; //!< [12] Error In Channel 12
bogdanm	82:6473597d706e	3087	uint32_t ERR13 : 1; //!< [13] Error In Channel 13
bogdanm	82:6473597d706e	3088	uint32_t ERR14 : 1; //!< [14] Error In Channel 14
bogdanm	82:6473597d706e	3089	uint32_t ERR15 : 1; //!< [15] Error In Channel 15
bogdanm	82:6473597d706e	3090	uint32_t RESERVED0 : 16; //!< [31:16]
bogdanm	82:6473597d706e	3091	} B;
bogdanm	82:6473597d706e	3092	} hw_dma_err_t;
bogdanm	82:6473597d706e	3093	#endif
bogdanm	82:6473597d706e	3094
bogdanm	82:6473597d706e	3095	/*!
bogdanm	82:6473597d706e	3096	* @name Constants and macros for entire DMA_ERR register
bogdanm	82:6473597d706e	3097	*/
bogdanm	82:6473597d706e	3098	//@{
bogdanm	82:6473597d706e	3099	#define HW_DMA_ERR_ADDR(x) (REGS_DMA_BASE(x) + 0x2CU)
bogdanm	82:6473597d706e	3100
bogdanm	82:6473597d706e	3101	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3102	#define HW_DMA_ERR(x) ((__IO hw_dma_err_t ) HW_DMA_ERR_ADDR(x))
bogdanm	82:6473597d706e	3103	#define HW_DMA_ERR_RD(x) (HW_DMA_ERR(x).U)
bogdanm	82:6473597d706e	3104	#define HW_DMA_ERR_WR(x, v) (HW_DMA_ERR(x).U = (v))
bogdanm	82:6473597d706e	3105	#define HW_DMA_ERR_SET(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) \| (v)))
bogdanm	82:6473597d706e	3106	#define HW_DMA_ERR_CLR(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) & ~(v)))
bogdanm	82:6473597d706e	3107	#define HW_DMA_ERR_TOG(x, v) (HW_DMA_ERR_WR(x, HW_DMA_ERR_RD(x) ^ (v)))
bogdanm	82:6473597d706e	3108	#endif
bogdanm	82:6473597d706e	3109	//@}
bogdanm	82:6473597d706e	3110
bogdanm	82:6473597d706e	3111	/*
bogdanm	82:6473597d706e	3112	* Constants & macros for individual DMA_ERR bitfields
bogdanm	82:6473597d706e	3113	*/
bogdanm	82:6473597d706e	3114
bogdanm	82:6473597d706e	3115	/*!
bogdanm	82:6473597d706e	3116	* @name Register DMA_ERR, field ERR0[0] (W1C)
bogdanm	82:6473597d706e	3117	*
bogdanm	82:6473597d706e	3118	* Values:
bogdanm	82:6473597d706e	3119	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3120	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3121	*/
bogdanm	82:6473597d706e	3122	//@{
bogdanm	82:6473597d706e	3123	#define BP_DMA_ERR_ERR0 (0U) //!< Bit position for DMA_ERR_ERR0.
bogdanm	82:6473597d706e	3124	#define BM_DMA_ERR_ERR0 (0x00000001U) //!< Bit mask for DMA_ERR_ERR0.
bogdanm	82:6473597d706e	3125	#define BS_DMA_ERR_ERR0 (1U) //!< Bit field size in bits for DMA_ERR_ERR0.
bogdanm	82:6473597d706e	3126
bogdanm	82:6473597d706e	3127	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3128	//! @brief Read current value of the DMA_ERR_ERR0 field.
bogdanm	82:6473597d706e	3129	#define BR_DMA_ERR_ERR0(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0))
bogdanm	82:6473597d706e	3130	#endif
bogdanm	82:6473597d706e	3131
bogdanm	82:6473597d706e	3132	//! @brief Format value for bitfield DMA_ERR_ERR0.
bogdanm	82:6473597d706e	3133	#define BF_DMA_ERR_ERR0(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR0), uint32_t) & BM_DMA_ERR_ERR0)
bogdanm	82:6473597d706e	3134
bogdanm	82:6473597d706e	3135	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3136	//! @brief Set the ERR0 field to a new value.
bogdanm	82:6473597d706e	3137	#define BW_DMA_ERR_ERR0(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR0) = (v))
bogdanm	82:6473597d706e	3138	#endif
bogdanm	82:6473597d706e	3139	//@}
bogdanm	82:6473597d706e	3140
bogdanm	82:6473597d706e	3141	/*!
bogdanm	82:6473597d706e	3142	* @name Register DMA_ERR, field ERR1[1] (W1C)
bogdanm	82:6473597d706e	3143	*
bogdanm	82:6473597d706e	3144	* Values:
bogdanm	82:6473597d706e	3145	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3146	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3147	*/
bogdanm	82:6473597d706e	3148	//@{
bogdanm	82:6473597d706e	3149	#define BP_DMA_ERR_ERR1 (1U) //!< Bit position for DMA_ERR_ERR1.
bogdanm	82:6473597d706e	3150	#define BM_DMA_ERR_ERR1 (0x00000002U) //!< Bit mask for DMA_ERR_ERR1.
bogdanm	82:6473597d706e	3151	#define BS_DMA_ERR_ERR1 (1U) //!< Bit field size in bits for DMA_ERR_ERR1.
bogdanm	82:6473597d706e	3152
bogdanm	82:6473597d706e	3153	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3154	//! @brief Read current value of the DMA_ERR_ERR1 field.
bogdanm	82:6473597d706e	3155	#define BR_DMA_ERR_ERR1(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1))
bogdanm	82:6473597d706e	3156	#endif
bogdanm	82:6473597d706e	3157
bogdanm	82:6473597d706e	3158	//! @brief Format value for bitfield DMA_ERR_ERR1.
bogdanm	82:6473597d706e	3159	#define BF_DMA_ERR_ERR1(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR1), uint32_t) & BM_DMA_ERR_ERR1)
bogdanm	82:6473597d706e	3160
bogdanm	82:6473597d706e	3161	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3162	//! @brief Set the ERR1 field to a new value.
bogdanm	82:6473597d706e	3163	#define BW_DMA_ERR_ERR1(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR1) = (v))
bogdanm	82:6473597d706e	3164	#endif
bogdanm	82:6473597d706e	3165	//@}
bogdanm	82:6473597d706e	3166
bogdanm	82:6473597d706e	3167	/*!
bogdanm	82:6473597d706e	3168	* @name Register DMA_ERR, field ERR2[2] (W1C)
bogdanm	82:6473597d706e	3169	*
bogdanm	82:6473597d706e	3170	* Values:
bogdanm	82:6473597d706e	3171	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3172	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3173	*/
bogdanm	82:6473597d706e	3174	//@{
bogdanm	82:6473597d706e	3175	#define BP_DMA_ERR_ERR2 (2U) //!< Bit position for DMA_ERR_ERR2.
bogdanm	82:6473597d706e	3176	#define BM_DMA_ERR_ERR2 (0x00000004U) //!< Bit mask for DMA_ERR_ERR2.
bogdanm	82:6473597d706e	3177	#define BS_DMA_ERR_ERR2 (1U) //!< Bit field size in bits for DMA_ERR_ERR2.
bogdanm	82:6473597d706e	3178
bogdanm	82:6473597d706e	3179	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3180	//! @brief Read current value of the DMA_ERR_ERR2 field.
bogdanm	82:6473597d706e	3181	#define BR_DMA_ERR_ERR2(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2))
bogdanm	82:6473597d706e	3182	#endif
bogdanm	82:6473597d706e	3183
bogdanm	82:6473597d706e	3184	//! @brief Format value for bitfield DMA_ERR_ERR2.
bogdanm	82:6473597d706e	3185	#define BF_DMA_ERR_ERR2(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR2), uint32_t) & BM_DMA_ERR_ERR2)
bogdanm	82:6473597d706e	3186
bogdanm	82:6473597d706e	3187	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3188	//! @brief Set the ERR2 field to a new value.
bogdanm	82:6473597d706e	3189	#define BW_DMA_ERR_ERR2(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR2) = (v))
bogdanm	82:6473597d706e	3190	#endif
bogdanm	82:6473597d706e	3191	//@}
bogdanm	82:6473597d706e	3192
bogdanm	82:6473597d706e	3193	/*!
bogdanm	82:6473597d706e	3194	* @name Register DMA_ERR, field ERR3[3] (W1C)
bogdanm	82:6473597d706e	3195	*
bogdanm	82:6473597d706e	3196	* Values:
bogdanm	82:6473597d706e	3197	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3198	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3199	*/
bogdanm	82:6473597d706e	3200	//@{
bogdanm	82:6473597d706e	3201	#define BP_DMA_ERR_ERR3 (3U) //!< Bit position for DMA_ERR_ERR3.
bogdanm	82:6473597d706e	3202	#define BM_DMA_ERR_ERR3 (0x00000008U) //!< Bit mask for DMA_ERR_ERR3.
bogdanm	82:6473597d706e	3203	#define BS_DMA_ERR_ERR3 (1U) //!< Bit field size in bits for DMA_ERR_ERR3.
bogdanm	82:6473597d706e	3204
bogdanm	82:6473597d706e	3205	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3206	//! @brief Read current value of the DMA_ERR_ERR3 field.
bogdanm	82:6473597d706e	3207	#define BR_DMA_ERR_ERR3(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3))
bogdanm	82:6473597d706e	3208	#endif
bogdanm	82:6473597d706e	3209
bogdanm	82:6473597d706e	3210	//! @brief Format value for bitfield DMA_ERR_ERR3.
bogdanm	82:6473597d706e	3211	#define BF_DMA_ERR_ERR3(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR3), uint32_t) & BM_DMA_ERR_ERR3)
bogdanm	82:6473597d706e	3212
bogdanm	82:6473597d706e	3213	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3214	//! @brief Set the ERR3 field to a new value.
bogdanm	82:6473597d706e	3215	#define BW_DMA_ERR_ERR3(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR3) = (v))
bogdanm	82:6473597d706e	3216	#endif
bogdanm	82:6473597d706e	3217	//@}
bogdanm	82:6473597d706e	3218
bogdanm	82:6473597d706e	3219	/*!
bogdanm	82:6473597d706e	3220	* @name Register DMA_ERR, field ERR4[4] (W1C)
bogdanm	82:6473597d706e	3221	*
bogdanm	82:6473597d706e	3222	* Values:
bogdanm	82:6473597d706e	3223	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3224	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3225	*/
bogdanm	82:6473597d706e	3226	//@{
bogdanm	82:6473597d706e	3227	#define BP_DMA_ERR_ERR4 (4U) //!< Bit position for DMA_ERR_ERR4.
bogdanm	82:6473597d706e	3228	#define BM_DMA_ERR_ERR4 (0x00000010U) //!< Bit mask for DMA_ERR_ERR4.
bogdanm	82:6473597d706e	3229	#define BS_DMA_ERR_ERR4 (1U) //!< Bit field size in bits for DMA_ERR_ERR4.
bogdanm	82:6473597d706e	3230
bogdanm	82:6473597d706e	3231	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3232	//! @brief Read current value of the DMA_ERR_ERR4 field.
bogdanm	82:6473597d706e	3233	#define BR_DMA_ERR_ERR4(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4))
bogdanm	82:6473597d706e	3234	#endif
bogdanm	82:6473597d706e	3235
bogdanm	82:6473597d706e	3236	//! @brief Format value for bitfield DMA_ERR_ERR4.
bogdanm	82:6473597d706e	3237	#define BF_DMA_ERR_ERR4(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR4), uint32_t) & BM_DMA_ERR_ERR4)
bogdanm	82:6473597d706e	3238
bogdanm	82:6473597d706e	3239	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3240	//! @brief Set the ERR4 field to a new value.
bogdanm	82:6473597d706e	3241	#define BW_DMA_ERR_ERR4(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR4) = (v))
bogdanm	82:6473597d706e	3242	#endif
bogdanm	82:6473597d706e	3243	//@}
bogdanm	82:6473597d706e	3244
bogdanm	82:6473597d706e	3245	/*!
bogdanm	82:6473597d706e	3246	* @name Register DMA_ERR, field ERR5[5] (W1C)
bogdanm	82:6473597d706e	3247	*
bogdanm	82:6473597d706e	3248	* Values:
bogdanm	82:6473597d706e	3249	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3250	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3251	*/
bogdanm	82:6473597d706e	3252	//@{
bogdanm	82:6473597d706e	3253	#define BP_DMA_ERR_ERR5 (5U) //!< Bit position for DMA_ERR_ERR5.
bogdanm	82:6473597d706e	3254	#define BM_DMA_ERR_ERR5 (0x00000020U) //!< Bit mask for DMA_ERR_ERR5.
bogdanm	82:6473597d706e	3255	#define BS_DMA_ERR_ERR5 (1U) //!< Bit field size in bits for DMA_ERR_ERR5.
bogdanm	82:6473597d706e	3256
bogdanm	82:6473597d706e	3257	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3258	//! @brief Read current value of the DMA_ERR_ERR5 field.
bogdanm	82:6473597d706e	3259	#define BR_DMA_ERR_ERR5(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5))
bogdanm	82:6473597d706e	3260	#endif
bogdanm	82:6473597d706e	3261
bogdanm	82:6473597d706e	3262	//! @brief Format value for bitfield DMA_ERR_ERR5.
bogdanm	82:6473597d706e	3263	#define BF_DMA_ERR_ERR5(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR5), uint32_t) & BM_DMA_ERR_ERR5)
bogdanm	82:6473597d706e	3264
bogdanm	82:6473597d706e	3265	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3266	//! @brief Set the ERR5 field to a new value.
bogdanm	82:6473597d706e	3267	#define BW_DMA_ERR_ERR5(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR5) = (v))
bogdanm	82:6473597d706e	3268	#endif
bogdanm	82:6473597d706e	3269	//@}
bogdanm	82:6473597d706e	3270
bogdanm	82:6473597d706e	3271	/*!
bogdanm	82:6473597d706e	3272	* @name Register DMA_ERR, field ERR6[6] (W1C)
bogdanm	82:6473597d706e	3273	*
bogdanm	82:6473597d706e	3274	* Values:
bogdanm	82:6473597d706e	3275	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3276	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3277	*/
bogdanm	82:6473597d706e	3278	//@{
bogdanm	82:6473597d706e	3279	#define BP_DMA_ERR_ERR6 (6U) //!< Bit position for DMA_ERR_ERR6.
bogdanm	82:6473597d706e	3280	#define BM_DMA_ERR_ERR6 (0x00000040U) //!< Bit mask for DMA_ERR_ERR6.
bogdanm	82:6473597d706e	3281	#define BS_DMA_ERR_ERR6 (1U) //!< Bit field size in bits for DMA_ERR_ERR6.
bogdanm	82:6473597d706e	3282
bogdanm	82:6473597d706e	3283	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3284	//! @brief Read current value of the DMA_ERR_ERR6 field.
bogdanm	82:6473597d706e	3285	#define BR_DMA_ERR_ERR6(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6))
bogdanm	82:6473597d706e	3286	#endif
bogdanm	82:6473597d706e	3287
bogdanm	82:6473597d706e	3288	//! @brief Format value for bitfield DMA_ERR_ERR6.
bogdanm	82:6473597d706e	3289	#define BF_DMA_ERR_ERR6(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR6), uint32_t) & BM_DMA_ERR_ERR6)
bogdanm	82:6473597d706e	3290
bogdanm	82:6473597d706e	3291	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3292	//! @brief Set the ERR6 field to a new value.
bogdanm	82:6473597d706e	3293	#define BW_DMA_ERR_ERR6(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR6) = (v))
bogdanm	82:6473597d706e	3294	#endif
bogdanm	82:6473597d706e	3295	//@}
bogdanm	82:6473597d706e	3296
bogdanm	82:6473597d706e	3297	/*!
bogdanm	82:6473597d706e	3298	* @name Register DMA_ERR, field ERR7[7] (W1C)
bogdanm	82:6473597d706e	3299	*
bogdanm	82:6473597d706e	3300	* Values:
bogdanm	82:6473597d706e	3301	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3302	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3303	*/
bogdanm	82:6473597d706e	3304	//@{
bogdanm	82:6473597d706e	3305	#define BP_DMA_ERR_ERR7 (7U) //!< Bit position for DMA_ERR_ERR7.
bogdanm	82:6473597d706e	3306	#define BM_DMA_ERR_ERR7 (0x00000080U) //!< Bit mask for DMA_ERR_ERR7.
bogdanm	82:6473597d706e	3307	#define BS_DMA_ERR_ERR7 (1U) //!< Bit field size in bits for DMA_ERR_ERR7.
bogdanm	82:6473597d706e	3308
bogdanm	82:6473597d706e	3309	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3310	//! @brief Read current value of the DMA_ERR_ERR7 field.
bogdanm	82:6473597d706e	3311	#define BR_DMA_ERR_ERR7(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7))
bogdanm	82:6473597d706e	3312	#endif
bogdanm	82:6473597d706e	3313
bogdanm	82:6473597d706e	3314	//! @brief Format value for bitfield DMA_ERR_ERR7.
bogdanm	82:6473597d706e	3315	#define BF_DMA_ERR_ERR7(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR7), uint32_t) & BM_DMA_ERR_ERR7)
bogdanm	82:6473597d706e	3316
bogdanm	82:6473597d706e	3317	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3318	//! @brief Set the ERR7 field to a new value.
bogdanm	82:6473597d706e	3319	#define BW_DMA_ERR_ERR7(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR7) = (v))
bogdanm	82:6473597d706e	3320	#endif
bogdanm	82:6473597d706e	3321	//@}
bogdanm	82:6473597d706e	3322
bogdanm	82:6473597d706e	3323	/*!
bogdanm	82:6473597d706e	3324	* @name Register DMA_ERR, field ERR8[8] (W1C)
bogdanm	82:6473597d706e	3325	*
bogdanm	82:6473597d706e	3326	* Values:
bogdanm	82:6473597d706e	3327	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3328	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3329	*/
bogdanm	82:6473597d706e	3330	//@{
bogdanm	82:6473597d706e	3331	#define BP_DMA_ERR_ERR8 (8U) //!< Bit position for DMA_ERR_ERR8.
bogdanm	82:6473597d706e	3332	#define BM_DMA_ERR_ERR8 (0x00000100U) //!< Bit mask for DMA_ERR_ERR8.
bogdanm	82:6473597d706e	3333	#define BS_DMA_ERR_ERR8 (1U) //!< Bit field size in bits for DMA_ERR_ERR8.
bogdanm	82:6473597d706e	3334
bogdanm	82:6473597d706e	3335	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3336	//! @brief Read current value of the DMA_ERR_ERR8 field.
bogdanm	82:6473597d706e	3337	#define BR_DMA_ERR_ERR8(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8))
bogdanm	82:6473597d706e	3338	#endif
bogdanm	82:6473597d706e	3339
bogdanm	82:6473597d706e	3340	//! @brief Format value for bitfield DMA_ERR_ERR8.
bogdanm	82:6473597d706e	3341	#define BF_DMA_ERR_ERR8(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR8), uint32_t) & BM_DMA_ERR_ERR8)
bogdanm	82:6473597d706e	3342
bogdanm	82:6473597d706e	3343	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3344	//! @brief Set the ERR8 field to a new value.
bogdanm	82:6473597d706e	3345	#define BW_DMA_ERR_ERR8(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR8) = (v))
bogdanm	82:6473597d706e	3346	#endif
bogdanm	82:6473597d706e	3347	//@}
bogdanm	82:6473597d706e	3348
bogdanm	82:6473597d706e	3349	/*!
bogdanm	82:6473597d706e	3350	* @name Register DMA_ERR, field ERR9[9] (W1C)
bogdanm	82:6473597d706e	3351	*
bogdanm	82:6473597d706e	3352	* Values:
bogdanm	82:6473597d706e	3353	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3354	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3355	*/
bogdanm	82:6473597d706e	3356	//@{
bogdanm	82:6473597d706e	3357	#define BP_DMA_ERR_ERR9 (9U) //!< Bit position for DMA_ERR_ERR9.
bogdanm	82:6473597d706e	3358	#define BM_DMA_ERR_ERR9 (0x00000200U) //!< Bit mask for DMA_ERR_ERR9.
bogdanm	82:6473597d706e	3359	#define BS_DMA_ERR_ERR9 (1U) //!< Bit field size in bits for DMA_ERR_ERR9.
bogdanm	82:6473597d706e	3360
bogdanm	82:6473597d706e	3361	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3362	//! @brief Read current value of the DMA_ERR_ERR9 field.
bogdanm	82:6473597d706e	3363	#define BR_DMA_ERR_ERR9(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9))
bogdanm	82:6473597d706e	3364	#endif
bogdanm	82:6473597d706e	3365
bogdanm	82:6473597d706e	3366	//! @brief Format value for bitfield DMA_ERR_ERR9.
bogdanm	82:6473597d706e	3367	#define BF_DMA_ERR_ERR9(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR9), uint32_t) & BM_DMA_ERR_ERR9)
bogdanm	82:6473597d706e	3368
bogdanm	82:6473597d706e	3369	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3370	//! @brief Set the ERR9 field to a new value.
bogdanm	82:6473597d706e	3371	#define BW_DMA_ERR_ERR9(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR9) = (v))
bogdanm	82:6473597d706e	3372	#endif
bogdanm	82:6473597d706e	3373	//@}
bogdanm	82:6473597d706e	3374
bogdanm	82:6473597d706e	3375	/*!
bogdanm	82:6473597d706e	3376	* @name Register DMA_ERR, field ERR10[10] (W1C)
bogdanm	82:6473597d706e	3377	*
bogdanm	82:6473597d706e	3378	* Values:
bogdanm	82:6473597d706e	3379	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3380	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3381	*/
bogdanm	82:6473597d706e	3382	//@{
bogdanm	82:6473597d706e	3383	#define BP_DMA_ERR_ERR10 (10U) //!< Bit position for DMA_ERR_ERR10.
bogdanm	82:6473597d706e	3384	#define BM_DMA_ERR_ERR10 (0x00000400U) //!< Bit mask for DMA_ERR_ERR10.
bogdanm	82:6473597d706e	3385	#define BS_DMA_ERR_ERR10 (1U) //!< Bit field size in bits for DMA_ERR_ERR10.
bogdanm	82:6473597d706e	3386
bogdanm	82:6473597d706e	3387	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3388	//! @brief Read current value of the DMA_ERR_ERR10 field.
bogdanm	82:6473597d706e	3389	#define BR_DMA_ERR_ERR10(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10))
bogdanm	82:6473597d706e	3390	#endif
bogdanm	82:6473597d706e	3391
bogdanm	82:6473597d706e	3392	//! @brief Format value for bitfield DMA_ERR_ERR10.
bogdanm	82:6473597d706e	3393	#define BF_DMA_ERR_ERR10(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR10), uint32_t) & BM_DMA_ERR_ERR10)
bogdanm	82:6473597d706e	3394
bogdanm	82:6473597d706e	3395	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3396	//! @brief Set the ERR10 field to a new value.
bogdanm	82:6473597d706e	3397	#define BW_DMA_ERR_ERR10(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR10) = (v))
bogdanm	82:6473597d706e	3398	#endif
bogdanm	82:6473597d706e	3399	//@}
bogdanm	82:6473597d706e	3400
bogdanm	82:6473597d706e	3401	/*!
bogdanm	82:6473597d706e	3402	* @name Register DMA_ERR, field ERR11[11] (W1C)
bogdanm	82:6473597d706e	3403	*
bogdanm	82:6473597d706e	3404	* Values:
bogdanm	82:6473597d706e	3405	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3406	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3407	*/
bogdanm	82:6473597d706e	3408	//@{
bogdanm	82:6473597d706e	3409	#define BP_DMA_ERR_ERR11 (11U) //!< Bit position for DMA_ERR_ERR11.
bogdanm	82:6473597d706e	3410	#define BM_DMA_ERR_ERR11 (0x00000800U) //!< Bit mask for DMA_ERR_ERR11.
bogdanm	82:6473597d706e	3411	#define BS_DMA_ERR_ERR11 (1U) //!< Bit field size in bits for DMA_ERR_ERR11.
bogdanm	82:6473597d706e	3412
bogdanm	82:6473597d706e	3413	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3414	//! @brief Read current value of the DMA_ERR_ERR11 field.
bogdanm	82:6473597d706e	3415	#define BR_DMA_ERR_ERR11(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11))
bogdanm	82:6473597d706e	3416	#endif
bogdanm	82:6473597d706e	3417
bogdanm	82:6473597d706e	3418	//! @brief Format value for bitfield DMA_ERR_ERR11.
bogdanm	82:6473597d706e	3419	#define BF_DMA_ERR_ERR11(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR11), uint32_t) & BM_DMA_ERR_ERR11)
bogdanm	82:6473597d706e	3420
bogdanm	82:6473597d706e	3421	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3422	//! @brief Set the ERR11 field to a new value.
bogdanm	82:6473597d706e	3423	#define BW_DMA_ERR_ERR11(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR11) = (v))
bogdanm	82:6473597d706e	3424	#endif
bogdanm	82:6473597d706e	3425	//@}
bogdanm	82:6473597d706e	3426
bogdanm	82:6473597d706e	3427	/*!
bogdanm	82:6473597d706e	3428	* @name Register DMA_ERR, field ERR12[12] (W1C)
bogdanm	82:6473597d706e	3429	*
bogdanm	82:6473597d706e	3430	* Values:
bogdanm	82:6473597d706e	3431	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3432	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3433	*/
bogdanm	82:6473597d706e	3434	//@{
bogdanm	82:6473597d706e	3435	#define BP_DMA_ERR_ERR12 (12U) //!< Bit position for DMA_ERR_ERR12.
bogdanm	82:6473597d706e	3436	#define BM_DMA_ERR_ERR12 (0x00001000U) //!< Bit mask for DMA_ERR_ERR12.
bogdanm	82:6473597d706e	3437	#define BS_DMA_ERR_ERR12 (1U) //!< Bit field size in bits for DMA_ERR_ERR12.
bogdanm	82:6473597d706e	3438
bogdanm	82:6473597d706e	3439	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3440	//! @brief Read current value of the DMA_ERR_ERR12 field.
bogdanm	82:6473597d706e	3441	#define BR_DMA_ERR_ERR12(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12))
bogdanm	82:6473597d706e	3442	#endif
bogdanm	82:6473597d706e	3443
bogdanm	82:6473597d706e	3444	//! @brief Format value for bitfield DMA_ERR_ERR12.
bogdanm	82:6473597d706e	3445	#define BF_DMA_ERR_ERR12(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR12), uint32_t) & BM_DMA_ERR_ERR12)
bogdanm	82:6473597d706e	3446
bogdanm	82:6473597d706e	3447	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3448	//! @brief Set the ERR12 field to a new value.
bogdanm	82:6473597d706e	3449	#define BW_DMA_ERR_ERR12(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR12) = (v))
bogdanm	82:6473597d706e	3450	#endif
bogdanm	82:6473597d706e	3451	//@}
bogdanm	82:6473597d706e	3452
bogdanm	82:6473597d706e	3453	/*!
bogdanm	82:6473597d706e	3454	* @name Register DMA_ERR, field ERR13[13] (W1C)
bogdanm	82:6473597d706e	3455	*
bogdanm	82:6473597d706e	3456	* Values:
bogdanm	82:6473597d706e	3457	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3458	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3459	*/
bogdanm	82:6473597d706e	3460	//@{
bogdanm	82:6473597d706e	3461	#define BP_DMA_ERR_ERR13 (13U) //!< Bit position for DMA_ERR_ERR13.
bogdanm	82:6473597d706e	3462	#define BM_DMA_ERR_ERR13 (0x00002000U) //!< Bit mask for DMA_ERR_ERR13.
bogdanm	82:6473597d706e	3463	#define BS_DMA_ERR_ERR13 (1U) //!< Bit field size in bits for DMA_ERR_ERR13.
bogdanm	82:6473597d706e	3464
bogdanm	82:6473597d706e	3465	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3466	//! @brief Read current value of the DMA_ERR_ERR13 field.
bogdanm	82:6473597d706e	3467	#define BR_DMA_ERR_ERR13(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13))
bogdanm	82:6473597d706e	3468	#endif
bogdanm	82:6473597d706e	3469
bogdanm	82:6473597d706e	3470	//! @brief Format value for bitfield DMA_ERR_ERR13.
bogdanm	82:6473597d706e	3471	#define BF_DMA_ERR_ERR13(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR13), uint32_t) & BM_DMA_ERR_ERR13)
bogdanm	82:6473597d706e	3472
bogdanm	82:6473597d706e	3473	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3474	//! @brief Set the ERR13 field to a new value.
bogdanm	82:6473597d706e	3475	#define BW_DMA_ERR_ERR13(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR13) = (v))
bogdanm	82:6473597d706e	3476	#endif
bogdanm	82:6473597d706e	3477	//@}
bogdanm	82:6473597d706e	3478
bogdanm	82:6473597d706e	3479	/*!
bogdanm	82:6473597d706e	3480	* @name Register DMA_ERR, field ERR14[14] (W1C)
bogdanm	82:6473597d706e	3481	*
bogdanm	82:6473597d706e	3482	* Values:
bogdanm	82:6473597d706e	3483	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3484	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3485	*/
bogdanm	82:6473597d706e	3486	//@{
bogdanm	82:6473597d706e	3487	#define BP_DMA_ERR_ERR14 (14U) //!< Bit position for DMA_ERR_ERR14.
bogdanm	82:6473597d706e	3488	#define BM_DMA_ERR_ERR14 (0x00004000U) //!< Bit mask for DMA_ERR_ERR14.
bogdanm	82:6473597d706e	3489	#define BS_DMA_ERR_ERR14 (1U) //!< Bit field size in bits for DMA_ERR_ERR14.
bogdanm	82:6473597d706e	3490
bogdanm	82:6473597d706e	3491	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3492	//! @brief Read current value of the DMA_ERR_ERR14 field.
bogdanm	82:6473597d706e	3493	#define BR_DMA_ERR_ERR14(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14))
bogdanm	82:6473597d706e	3494	#endif
bogdanm	82:6473597d706e	3495
bogdanm	82:6473597d706e	3496	//! @brief Format value for bitfield DMA_ERR_ERR14.
bogdanm	82:6473597d706e	3497	#define BF_DMA_ERR_ERR14(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR14), uint32_t) & BM_DMA_ERR_ERR14)
bogdanm	82:6473597d706e	3498
bogdanm	82:6473597d706e	3499	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3500	//! @brief Set the ERR14 field to a new value.
bogdanm	82:6473597d706e	3501	#define BW_DMA_ERR_ERR14(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR14) = (v))
bogdanm	82:6473597d706e	3502	#endif
bogdanm	82:6473597d706e	3503	//@}
bogdanm	82:6473597d706e	3504
bogdanm	82:6473597d706e	3505	/*!
bogdanm	82:6473597d706e	3506	* @name Register DMA_ERR, field ERR15[15] (W1C)
bogdanm	82:6473597d706e	3507	*
bogdanm	82:6473597d706e	3508	* Values:
bogdanm	82:6473597d706e	3509	* - 0 - An error in the corresponding channel has not occurred
bogdanm	82:6473597d706e	3510	* - 1 - An error in the corresponding channel has occurred
bogdanm	82:6473597d706e	3511	*/
bogdanm	82:6473597d706e	3512	//@{
bogdanm	82:6473597d706e	3513	#define BP_DMA_ERR_ERR15 (15U) //!< Bit position for DMA_ERR_ERR15.
bogdanm	82:6473597d706e	3514	#define BM_DMA_ERR_ERR15 (0x00008000U) //!< Bit mask for DMA_ERR_ERR15.
bogdanm	82:6473597d706e	3515	#define BS_DMA_ERR_ERR15 (1U) //!< Bit field size in bits for DMA_ERR_ERR15.
bogdanm	82:6473597d706e	3516
bogdanm	82:6473597d706e	3517	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3518	//! @brief Read current value of the DMA_ERR_ERR15 field.
bogdanm	82:6473597d706e	3519	#define BR_DMA_ERR_ERR15(x) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15))
bogdanm	82:6473597d706e	3520	#endif
bogdanm	82:6473597d706e	3521
bogdanm	82:6473597d706e	3522	//! @brief Format value for bitfield DMA_ERR_ERR15.
bogdanm	82:6473597d706e	3523	#define BF_DMA_ERR_ERR15(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_ERR_ERR15), uint32_t) & BM_DMA_ERR_ERR15)
bogdanm	82:6473597d706e	3524
bogdanm	82:6473597d706e	3525	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3526	//! @brief Set the ERR15 field to a new value.
bogdanm	82:6473597d706e	3527	#define BW_DMA_ERR_ERR15(x, v) (BITBAND_ACCESS32(HW_DMA_ERR_ADDR(x), BP_DMA_ERR_ERR15) = (v))
bogdanm	82:6473597d706e	3528	#endif
bogdanm	82:6473597d706e	3529	//@}
bogdanm	82:6473597d706e	3530
bogdanm	82:6473597d706e	3531	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3532	// HW_DMA_HRS - Hardware Request Status Register
bogdanm	82:6473597d706e	3533	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3534
bogdanm	82:6473597d706e	3535	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3536	/*!
bogdanm	82:6473597d706e	3537	* @brief HW_DMA_HRS - Hardware Request Status Register (RO)
bogdanm	82:6473597d706e	3538	*
bogdanm	82:6473597d706e	3539	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	3540	*
bogdanm	82:6473597d706e	3541	* The HRS register provides a bit map for the DMA channels, signaling the
bogdanm	82:6473597d706e	3542	* presence of a hardware request for each channel. The hardware request status bits
bogdanm	82:6473597d706e	3543	* reflect the current state of the register and qualified (via the ERQ fields)
bogdanm	82:6473597d706e	3544	* DMA request signals as seen by the DMA's arbitration logic. This view into the
bogdanm	82:6473597d706e	3545	* hardware request signals may be used for debug purposes. These bits reflect the
bogdanm	82:6473597d706e	3546	* state of the request as seen by the arbitration logic. Therefore, this status
bogdanm	82:6473597d706e	3547	* is affected by the ERQ bits.
bogdanm	82:6473597d706e	3548	*/
bogdanm	82:6473597d706e	3549	typedef union _hw_dma_hrs
bogdanm	82:6473597d706e	3550	{
bogdanm	82:6473597d706e	3551	uint32_t U;
bogdanm	82:6473597d706e	3552	struct _hw_dma_hrs_bitfields
bogdanm	82:6473597d706e	3553	{
bogdanm	82:6473597d706e	3554	uint32_t HRS0 : 1; //!< [0] Hardware Request Status Channel 0
bogdanm	82:6473597d706e	3555	uint32_t HRS1 : 1; //!< [1] Hardware Request Status Channel 1
bogdanm	82:6473597d706e	3556	uint32_t HRS2 : 1; //!< [2] Hardware Request Status Channel 2
bogdanm	82:6473597d706e	3557	uint32_t HRS3 : 1; //!< [3] Hardware Request Status Channel 3
bogdanm	82:6473597d706e	3558	uint32_t HRS4 : 1; //!< [4] Hardware Request Status Channel 4
bogdanm	82:6473597d706e	3559	uint32_t HRS5 : 1; //!< [5] Hardware Request Status Channel 5
bogdanm	82:6473597d706e	3560	uint32_t HRS6 : 1; //!< [6] Hardware Request Status Channel 6
bogdanm	82:6473597d706e	3561	uint32_t HRS7 : 1; //!< [7] Hardware Request Status Channel 7
bogdanm	82:6473597d706e	3562	uint32_t HRS8 : 1; //!< [8] Hardware Request Status Channel 8
bogdanm	82:6473597d706e	3563	uint32_t HRS9 : 1; //!< [9] Hardware Request Status Channel 9
bogdanm	82:6473597d706e	3564	uint32_t HRS10 : 1; //!< [10] Hardware Request Status Channel 10
bogdanm	82:6473597d706e	3565	uint32_t HRS11 : 1; //!< [11] Hardware Request Status Channel 11
bogdanm	82:6473597d706e	3566	uint32_t HRS12 : 1; //!< [12] Hardware Request Status Channel 12
bogdanm	82:6473597d706e	3567	uint32_t HRS13 : 1; //!< [13] Hardware Request Status Channel 13
bogdanm	82:6473597d706e	3568	uint32_t HRS14 : 1; //!< [14] Hardware Request Status Channel 14
bogdanm	82:6473597d706e	3569	uint32_t HRS15 : 1; //!< [15] Hardware Request Status Channel 15
bogdanm	82:6473597d706e	3570	uint32_t RESERVED0 : 16; //!< [31:16] Reserved
bogdanm	82:6473597d706e	3571	} B;
bogdanm	82:6473597d706e	3572	} hw_dma_hrs_t;
bogdanm	82:6473597d706e	3573	#endif
bogdanm	82:6473597d706e	3574
bogdanm	82:6473597d706e	3575	/*!
bogdanm	82:6473597d706e	3576	* @name Constants and macros for entire DMA_HRS register
bogdanm	82:6473597d706e	3577	*/
bogdanm	82:6473597d706e	3578	//@{
bogdanm	82:6473597d706e	3579	#define HW_DMA_HRS_ADDR(x) (REGS_DMA_BASE(x) + 0x34U)
bogdanm	82:6473597d706e	3580
bogdanm	82:6473597d706e	3581	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3582	#define HW_DMA_HRS(x) ((__I hw_dma_hrs_t ) HW_DMA_HRS_ADDR(x))
bogdanm	82:6473597d706e	3583	#define HW_DMA_HRS_RD(x) (HW_DMA_HRS(x).U)
bogdanm	82:6473597d706e	3584	#endif
bogdanm	82:6473597d706e	3585	//@}
bogdanm	82:6473597d706e	3586
bogdanm	82:6473597d706e	3587	/*
bogdanm	82:6473597d706e	3588	* Constants & macros for individual DMA_HRS bitfields
bogdanm	82:6473597d706e	3589	*/
bogdanm	82:6473597d706e	3590
bogdanm	82:6473597d706e	3591	/*!
bogdanm	82:6473597d706e	3592	* @name Register DMA_HRS, field HRS0[0] (RO)
bogdanm	82:6473597d706e	3593	*
bogdanm	82:6473597d706e	3594	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3595	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3596	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3597	*
bogdanm	82:6473597d706e	3598	* Values:
bogdanm	82:6473597d706e	3599	* - 0 - A hardware service request for channel 0 is not present
bogdanm	82:6473597d706e	3600	* - 1 - A hardware service request for channel 0 is present
bogdanm	82:6473597d706e	3601	*/
bogdanm	82:6473597d706e	3602	//@{
bogdanm	82:6473597d706e	3603	#define BP_DMA_HRS_HRS0 (0U) //!< Bit position for DMA_HRS_HRS0.
bogdanm	82:6473597d706e	3604	#define BM_DMA_HRS_HRS0 (0x00000001U) //!< Bit mask for DMA_HRS_HRS0.
bogdanm	82:6473597d706e	3605	#define BS_DMA_HRS_HRS0 (1U) //!< Bit field size in bits for DMA_HRS_HRS0.
bogdanm	82:6473597d706e	3606
bogdanm	82:6473597d706e	3607	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3608	//! @brief Read current value of the DMA_HRS_HRS0 field.
bogdanm	82:6473597d706e	3609	#define BR_DMA_HRS_HRS0(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS0))
bogdanm	82:6473597d706e	3610	#endif
bogdanm	82:6473597d706e	3611	//@}
bogdanm	82:6473597d706e	3612
bogdanm	82:6473597d706e	3613	/*!
bogdanm	82:6473597d706e	3614	* @name Register DMA_HRS, field HRS1[1] (RO)
bogdanm	82:6473597d706e	3615	*
bogdanm	82:6473597d706e	3616	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3617	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3618	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3619	*
bogdanm	82:6473597d706e	3620	* Values:
bogdanm	82:6473597d706e	3621	* - 0 - A hardware service request for channel 1 is not present
bogdanm	82:6473597d706e	3622	* - 1 - A hardware service request for channel 1 is present
bogdanm	82:6473597d706e	3623	*/
bogdanm	82:6473597d706e	3624	//@{
bogdanm	82:6473597d706e	3625	#define BP_DMA_HRS_HRS1 (1U) //!< Bit position for DMA_HRS_HRS1.
bogdanm	82:6473597d706e	3626	#define BM_DMA_HRS_HRS1 (0x00000002U) //!< Bit mask for DMA_HRS_HRS1.
bogdanm	82:6473597d706e	3627	#define BS_DMA_HRS_HRS1 (1U) //!< Bit field size in bits for DMA_HRS_HRS1.
bogdanm	82:6473597d706e	3628
bogdanm	82:6473597d706e	3629	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3630	//! @brief Read current value of the DMA_HRS_HRS1 field.
bogdanm	82:6473597d706e	3631	#define BR_DMA_HRS_HRS1(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS1))
bogdanm	82:6473597d706e	3632	#endif
bogdanm	82:6473597d706e	3633	//@}
bogdanm	82:6473597d706e	3634
bogdanm	82:6473597d706e	3635	/*!
bogdanm	82:6473597d706e	3636	* @name Register DMA_HRS, field HRS2[2] (RO)
bogdanm	82:6473597d706e	3637	*
bogdanm	82:6473597d706e	3638	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3639	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3640	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3641	*
bogdanm	82:6473597d706e	3642	* Values:
bogdanm	82:6473597d706e	3643	* - 0 - A hardware service request for channel 2 is not present
bogdanm	82:6473597d706e	3644	* - 1 - A hardware service request for channel 2 is present
bogdanm	82:6473597d706e	3645	*/
bogdanm	82:6473597d706e	3646	//@{
bogdanm	82:6473597d706e	3647	#define BP_DMA_HRS_HRS2 (2U) //!< Bit position for DMA_HRS_HRS2.
bogdanm	82:6473597d706e	3648	#define BM_DMA_HRS_HRS2 (0x00000004U) //!< Bit mask for DMA_HRS_HRS2.
bogdanm	82:6473597d706e	3649	#define BS_DMA_HRS_HRS2 (1U) //!< Bit field size in bits for DMA_HRS_HRS2.
bogdanm	82:6473597d706e	3650
bogdanm	82:6473597d706e	3651	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3652	//! @brief Read current value of the DMA_HRS_HRS2 field.
bogdanm	82:6473597d706e	3653	#define BR_DMA_HRS_HRS2(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS2))
bogdanm	82:6473597d706e	3654	#endif
bogdanm	82:6473597d706e	3655	//@}
bogdanm	82:6473597d706e	3656
bogdanm	82:6473597d706e	3657	/*!
bogdanm	82:6473597d706e	3658	* @name Register DMA_HRS, field HRS3[3] (RO)
bogdanm	82:6473597d706e	3659	*
bogdanm	82:6473597d706e	3660	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3661	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3662	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3663	*
bogdanm	82:6473597d706e	3664	* Values:
bogdanm	82:6473597d706e	3665	* - 0 - A hardware service request for channel 3 is not present
bogdanm	82:6473597d706e	3666	* - 1 - A hardware service request for channel 3 is present
bogdanm	82:6473597d706e	3667	*/
bogdanm	82:6473597d706e	3668	//@{
bogdanm	82:6473597d706e	3669	#define BP_DMA_HRS_HRS3 (3U) //!< Bit position for DMA_HRS_HRS3.
bogdanm	82:6473597d706e	3670	#define BM_DMA_HRS_HRS3 (0x00000008U) //!< Bit mask for DMA_HRS_HRS3.
bogdanm	82:6473597d706e	3671	#define BS_DMA_HRS_HRS3 (1U) //!< Bit field size in bits for DMA_HRS_HRS3.
bogdanm	82:6473597d706e	3672
bogdanm	82:6473597d706e	3673	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3674	//! @brief Read current value of the DMA_HRS_HRS3 field.
bogdanm	82:6473597d706e	3675	#define BR_DMA_HRS_HRS3(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS3))
bogdanm	82:6473597d706e	3676	#endif
bogdanm	82:6473597d706e	3677	//@}
bogdanm	82:6473597d706e	3678
bogdanm	82:6473597d706e	3679	/*!
bogdanm	82:6473597d706e	3680	* @name Register DMA_HRS, field HRS4[4] (RO)
bogdanm	82:6473597d706e	3681	*
bogdanm	82:6473597d706e	3682	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3683	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3684	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3685	*
bogdanm	82:6473597d706e	3686	* Values:
bogdanm	82:6473597d706e	3687	* - 0 - A hardware service request for channel 4 is not present
bogdanm	82:6473597d706e	3688	* - 1 - A hardware service request for channel 4 is present
bogdanm	82:6473597d706e	3689	*/
bogdanm	82:6473597d706e	3690	//@{
bogdanm	82:6473597d706e	3691	#define BP_DMA_HRS_HRS4 (4U) //!< Bit position for DMA_HRS_HRS4.
bogdanm	82:6473597d706e	3692	#define BM_DMA_HRS_HRS4 (0x00000010U) //!< Bit mask for DMA_HRS_HRS4.
bogdanm	82:6473597d706e	3693	#define BS_DMA_HRS_HRS4 (1U) //!< Bit field size in bits for DMA_HRS_HRS4.
bogdanm	82:6473597d706e	3694
bogdanm	82:6473597d706e	3695	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3696	//! @brief Read current value of the DMA_HRS_HRS4 field.
bogdanm	82:6473597d706e	3697	#define BR_DMA_HRS_HRS4(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS4))
bogdanm	82:6473597d706e	3698	#endif
bogdanm	82:6473597d706e	3699	//@}
bogdanm	82:6473597d706e	3700
bogdanm	82:6473597d706e	3701	/*!
bogdanm	82:6473597d706e	3702	* @name Register DMA_HRS, field HRS5[5] (RO)
bogdanm	82:6473597d706e	3703	*
bogdanm	82:6473597d706e	3704	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3705	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3706	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3707	*
bogdanm	82:6473597d706e	3708	* Values:
bogdanm	82:6473597d706e	3709	* - 0 - A hardware service request for channel 5 is not present
bogdanm	82:6473597d706e	3710	* - 1 - A hardware service request for channel 5 is present
bogdanm	82:6473597d706e	3711	*/
bogdanm	82:6473597d706e	3712	//@{
bogdanm	82:6473597d706e	3713	#define BP_DMA_HRS_HRS5 (5U) //!< Bit position for DMA_HRS_HRS5.
bogdanm	82:6473597d706e	3714	#define BM_DMA_HRS_HRS5 (0x00000020U) //!< Bit mask for DMA_HRS_HRS5.
bogdanm	82:6473597d706e	3715	#define BS_DMA_HRS_HRS5 (1U) //!< Bit field size in bits for DMA_HRS_HRS5.
bogdanm	82:6473597d706e	3716
bogdanm	82:6473597d706e	3717	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3718	//! @brief Read current value of the DMA_HRS_HRS5 field.
bogdanm	82:6473597d706e	3719	#define BR_DMA_HRS_HRS5(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS5))
bogdanm	82:6473597d706e	3720	#endif
bogdanm	82:6473597d706e	3721	//@}
bogdanm	82:6473597d706e	3722
bogdanm	82:6473597d706e	3723	/*!
bogdanm	82:6473597d706e	3724	* @name Register DMA_HRS, field HRS6[6] (RO)
bogdanm	82:6473597d706e	3725	*
bogdanm	82:6473597d706e	3726	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3727	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3728	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3729	*
bogdanm	82:6473597d706e	3730	* Values:
bogdanm	82:6473597d706e	3731	* - 0 - A hardware service request for channel 6 is not present
bogdanm	82:6473597d706e	3732	* - 1 - A hardware service request for channel 6 is present
bogdanm	82:6473597d706e	3733	*/
bogdanm	82:6473597d706e	3734	//@{
bogdanm	82:6473597d706e	3735	#define BP_DMA_HRS_HRS6 (6U) //!< Bit position for DMA_HRS_HRS6.
bogdanm	82:6473597d706e	3736	#define BM_DMA_HRS_HRS6 (0x00000040U) //!< Bit mask for DMA_HRS_HRS6.
bogdanm	82:6473597d706e	3737	#define BS_DMA_HRS_HRS6 (1U) //!< Bit field size in bits for DMA_HRS_HRS6.
bogdanm	82:6473597d706e	3738
bogdanm	82:6473597d706e	3739	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3740	//! @brief Read current value of the DMA_HRS_HRS6 field.
bogdanm	82:6473597d706e	3741	#define BR_DMA_HRS_HRS6(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS6))
bogdanm	82:6473597d706e	3742	#endif
bogdanm	82:6473597d706e	3743	//@}
bogdanm	82:6473597d706e	3744
bogdanm	82:6473597d706e	3745	/*!
bogdanm	82:6473597d706e	3746	* @name Register DMA_HRS, field HRS7[7] (RO)
bogdanm	82:6473597d706e	3747	*
bogdanm	82:6473597d706e	3748	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3749	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3750	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3751	*
bogdanm	82:6473597d706e	3752	* Values:
bogdanm	82:6473597d706e	3753	* - 0 - A hardware service request for channel 7 is not present
bogdanm	82:6473597d706e	3754	* - 1 - A hardware service request for channel 7 is present
bogdanm	82:6473597d706e	3755	*/
bogdanm	82:6473597d706e	3756	//@{
bogdanm	82:6473597d706e	3757	#define BP_DMA_HRS_HRS7 (7U) //!< Bit position for DMA_HRS_HRS7.
bogdanm	82:6473597d706e	3758	#define BM_DMA_HRS_HRS7 (0x00000080U) //!< Bit mask for DMA_HRS_HRS7.
bogdanm	82:6473597d706e	3759	#define BS_DMA_HRS_HRS7 (1U) //!< Bit field size in bits for DMA_HRS_HRS7.
bogdanm	82:6473597d706e	3760
bogdanm	82:6473597d706e	3761	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3762	//! @brief Read current value of the DMA_HRS_HRS7 field.
bogdanm	82:6473597d706e	3763	#define BR_DMA_HRS_HRS7(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS7))
bogdanm	82:6473597d706e	3764	#endif
bogdanm	82:6473597d706e	3765	//@}
bogdanm	82:6473597d706e	3766
bogdanm	82:6473597d706e	3767	/*!
bogdanm	82:6473597d706e	3768	* @name Register DMA_HRS, field HRS8[8] (RO)
bogdanm	82:6473597d706e	3769	*
bogdanm	82:6473597d706e	3770	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3771	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3772	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3773	*
bogdanm	82:6473597d706e	3774	* Values:
bogdanm	82:6473597d706e	3775	* - 0 - A hardware service request for channel 8 is not present
bogdanm	82:6473597d706e	3776	* - 1 - A hardware service request for channel 8 is present
bogdanm	82:6473597d706e	3777	*/
bogdanm	82:6473597d706e	3778	//@{
bogdanm	82:6473597d706e	3779	#define BP_DMA_HRS_HRS8 (8U) //!< Bit position for DMA_HRS_HRS8.
bogdanm	82:6473597d706e	3780	#define BM_DMA_HRS_HRS8 (0x00000100U) //!< Bit mask for DMA_HRS_HRS8.
bogdanm	82:6473597d706e	3781	#define BS_DMA_HRS_HRS8 (1U) //!< Bit field size in bits for DMA_HRS_HRS8.
bogdanm	82:6473597d706e	3782
bogdanm	82:6473597d706e	3783	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3784	//! @brief Read current value of the DMA_HRS_HRS8 field.
bogdanm	82:6473597d706e	3785	#define BR_DMA_HRS_HRS8(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS8))
bogdanm	82:6473597d706e	3786	#endif
bogdanm	82:6473597d706e	3787	//@}
bogdanm	82:6473597d706e	3788
bogdanm	82:6473597d706e	3789	/*!
bogdanm	82:6473597d706e	3790	* @name Register DMA_HRS, field HRS9[9] (RO)
bogdanm	82:6473597d706e	3791	*
bogdanm	82:6473597d706e	3792	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3793	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3794	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3795	*
bogdanm	82:6473597d706e	3796	* Values:
bogdanm	82:6473597d706e	3797	* - 0 - A hardware service request for channel 9 is not present
bogdanm	82:6473597d706e	3798	* - 1 - A hardware service request for channel 9 is present
bogdanm	82:6473597d706e	3799	*/
bogdanm	82:6473597d706e	3800	//@{
bogdanm	82:6473597d706e	3801	#define BP_DMA_HRS_HRS9 (9U) //!< Bit position for DMA_HRS_HRS9.
bogdanm	82:6473597d706e	3802	#define BM_DMA_HRS_HRS9 (0x00000200U) //!< Bit mask for DMA_HRS_HRS9.
bogdanm	82:6473597d706e	3803	#define BS_DMA_HRS_HRS9 (1U) //!< Bit field size in bits for DMA_HRS_HRS9.
bogdanm	82:6473597d706e	3804
bogdanm	82:6473597d706e	3805	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3806	//! @brief Read current value of the DMA_HRS_HRS9 field.
bogdanm	82:6473597d706e	3807	#define BR_DMA_HRS_HRS9(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS9))
bogdanm	82:6473597d706e	3808	#endif
bogdanm	82:6473597d706e	3809	//@}
bogdanm	82:6473597d706e	3810
bogdanm	82:6473597d706e	3811	/*!
bogdanm	82:6473597d706e	3812	* @name Register DMA_HRS, field HRS10[10] (RO)
bogdanm	82:6473597d706e	3813	*
bogdanm	82:6473597d706e	3814	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3815	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3816	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3817	*
bogdanm	82:6473597d706e	3818	* Values:
bogdanm	82:6473597d706e	3819	* - 0 - A hardware service request for channel 10 is not present
bogdanm	82:6473597d706e	3820	* - 1 - A hardware service request for channel 10 is present
bogdanm	82:6473597d706e	3821	*/
bogdanm	82:6473597d706e	3822	//@{
bogdanm	82:6473597d706e	3823	#define BP_DMA_HRS_HRS10 (10U) //!< Bit position for DMA_HRS_HRS10.
bogdanm	82:6473597d706e	3824	#define BM_DMA_HRS_HRS10 (0x00000400U) //!< Bit mask for DMA_HRS_HRS10.
bogdanm	82:6473597d706e	3825	#define BS_DMA_HRS_HRS10 (1U) //!< Bit field size in bits for DMA_HRS_HRS10.
bogdanm	82:6473597d706e	3826
bogdanm	82:6473597d706e	3827	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3828	//! @brief Read current value of the DMA_HRS_HRS10 field.
bogdanm	82:6473597d706e	3829	#define BR_DMA_HRS_HRS10(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS10))
bogdanm	82:6473597d706e	3830	#endif
bogdanm	82:6473597d706e	3831	//@}
bogdanm	82:6473597d706e	3832
bogdanm	82:6473597d706e	3833	/*!
bogdanm	82:6473597d706e	3834	* @name Register DMA_HRS, field HRS11[11] (RO)
bogdanm	82:6473597d706e	3835	*
bogdanm	82:6473597d706e	3836	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3837	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3838	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3839	*
bogdanm	82:6473597d706e	3840	* Values:
bogdanm	82:6473597d706e	3841	* - 0 - A hardware service request for channel 11 is not present
bogdanm	82:6473597d706e	3842	* - 1 - A hardware service request for channel 11 is present
bogdanm	82:6473597d706e	3843	*/
bogdanm	82:6473597d706e	3844	//@{
bogdanm	82:6473597d706e	3845	#define BP_DMA_HRS_HRS11 (11U) //!< Bit position for DMA_HRS_HRS11.
bogdanm	82:6473597d706e	3846	#define BM_DMA_HRS_HRS11 (0x00000800U) //!< Bit mask for DMA_HRS_HRS11.
bogdanm	82:6473597d706e	3847	#define BS_DMA_HRS_HRS11 (1U) //!< Bit field size in bits for DMA_HRS_HRS11.
bogdanm	82:6473597d706e	3848
bogdanm	82:6473597d706e	3849	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3850	//! @brief Read current value of the DMA_HRS_HRS11 field.
bogdanm	82:6473597d706e	3851	#define BR_DMA_HRS_HRS11(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS11))
bogdanm	82:6473597d706e	3852	#endif
bogdanm	82:6473597d706e	3853	//@}
bogdanm	82:6473597d706e	3854
bogdanm	82:6473597d706e	3855	/*!
bogdanm	82:6473597d706e	3856	* @name Register DMA_HRS, field HRS12[12] (RO)
bogdanm	82:6473597d706e	3857	*
bogdanm	82:6473597d706e	3858	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3859	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3860	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3861	*
bogdanm	82:6473597d706e	3862	* Values:
bogdanm	82:6473597d706e	3863	* - 0 - A hardware service request for channel 12 is not present
bogdanm	82:6473597d706e	3864	* - 1 - A hardware service request for channel 12 is present
bogdanm	82:6473597d706e	3865	*/
bogdanm	82:6473597d706e	3866	//@{
bogdanm	82:6473597d706e	3867	#define BP_DMA_HRS_HRS12 (12U) //!< Bit position for DMA_HRS_HRS12.
bogdanm	82:6473597d706e	3868	#define BM_DMA_HRS_HRS12 (0x00001000U) //!< Bit mask for DMA_HRS_HRS12.
bogdanm	82:6473597d706e	3869	#define BS_DMA_HRS_HRS12 (1U) //!< Bit field size in bits for DMA_HRS_HRS12.
bogdanm	82:6473597d706e	3870
bogdanm	82:6473597d706e	3871	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3872	//! @brief Read current value of the DMA_HRS_HRS12 field.
bogdanm	82:6473597d706e	3873	#define BR_DMA_HRS_HRS12(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS12))
bogdanm	82:6473597d706e	3874	#endif
bogdanm	82:6473597d706e	3875	//@}
bogdanm	82:6473597d706e	3876
bogdanm	82:6473597d706e	3877	/*!
bogdanm	82:6473597d706e	3878	* @name Register DMA_HRS, field HRS13[13] (RO)
bogdanm	82:6473597d706e	3879	*
bogdanm	82:6473597d706e	3880	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3881	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3882	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3883	*
bogdanm	82:6473597d706e	3884	* Values:
bogdanm	82:6473597d706e	3885	* - 0 - A hardware service request for channel 13 is not present
bogdanm	82:6473597d706e	3886	* - 1 - A hardware service request for channel 13 is present
bogdanm	82:6473597d706e	3887	*/
bogdanm	82:6473597d706e	3888	//@{
bogdanm	82:6473597d706e	3889	#define BP_DMA_HRS_HRS13 (13U) //!< Bit position for DMA_HRS_HRS13.
bogdanm	82:6473597d706e	3890	#define BM_DMA_HRS_HRS13 (0x00002000U) //!< Bit mask for DMA_HRS_HRS13.
bogdanm	82:6473597d706e	3891	#define BS_DMA_HRS_HRS13 (1U) //!< Bit field size in bits for DMA_HRS_HRS13.
bogdanm	82:6473597d706e	3892
bogdanm	82:6473597d706e	3893	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3894	//! @brief Read current value of the DMA_HRS_HRS13 field.
bogdanm	82:6473597d706e	3895	#define BR_DMA_HRS_HRS13(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS13))
bogdanm	82:6473597d706e	3896	#endif
bogdanm	82:6473597d706e	3897	//@}
bogdanm	82:6473597d706e	3898
bogdanm	82:6473597d706e	3899	/*!
bogdanm	82:6473597d706e	3900	* @name Register DMA_HRS, field HRS14[14] (RO)
bogdanm	82:6473597d706e	3901	*
bogdanm	82:6473597d706e	3902	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3903	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3904	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3905	*
bogdanm	82:6473597d706e	3906	* Values:
bogdanm	82:6473597d706e	3907	* - 0 - A hardware service request for channel 14 is not present
bogdanm	82:6473597d706e	3908	* - 1 - A hardware service request for channel 14 is present
bogdanm	82:6473597d706e	3909	*/
bogdanm	82:6473597d706e	3910	//@{
bogdanm	82:6473597d706e	3911	#define BP_DMA_HRS_HRS14 (14U) //!< Bit position for DMA_HRS_HRS14.
bogdanm	82:6473597d706e	3912	#define BM_DMA_HRS_HRS14 (0x00004000U) //!< Bit mask for DMA_HRS_HRS14.
bogdanm	82:6473597d706e	3913	#define BS_DMA_HRS_HRS14 (1U) //!< Bit field size in bits for DMA_HRS_HRS14.
bogdanm	82:6473597d706e	3914
bogdanm	82:6473597d706e	3915	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3916	//! @brief Read current value of the DMA_HRS_HRS14 field.
bogdanm	82:6473597d706e	3917	#define BR_DMA_HRS_HRS14(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS14))
bogdanm	82:6473597d706e	3918	#endif
bogdanm	82:6473597d706e	3919	//@}
bogdanm	82:6473597d706e	3920
bogdanm	82:6473597d706e	3921	/*!
bogdanm	82:6473597d706e	3922	* @name Register DMA_HRS, field HRS15[15] (RO)
bogdanm	82:6473597d706e	3923	*
bogdanm	82:6473597d706e	3924	* The HRS bit for its respective channel remains asserted for the period when a
bogdanm	82:6473597d706e	3925	* Hardware Request is Present on the Channel. After the Request is completed
bogdanm	82:6473597d706e	3926	* and Channel is free , the HRS bit is automatically cleared by hardware.
bogdanm	82:6473597d706e	3927	*
bogdanm	82:6473597d706e	3928	* Values:
bogdanm	82:6473597d706e	3929	* - 0 - A hardware service request for channel 15 is not present
bogdanm	82:6473597d706e	3930	* - 1 - A hardware service request for channel 15 is present
bogdanm	82:6473597d706e	3931	*/
bogdanm	82:6473597d706e	3932	//@{
bogdanm	82:6473597d706e	3933	#define BP_DMA_HRS_HRS15 (15U) //!< Bit position for DMA_HRS_HRS15.
bogdanm	82:6473597d706e	3934	#define BM_DMA_HRS_HRS15 (0x00008000U) //!< Bit mask for DMA_HRS_HRS15.
bogdanm	82:6473597d706e	3935	#define BS_DMA_HRS_HRS15 (1U) //!< Bit field size in bits for DMA_HRS_HRS15.
bogdanm	82:6473597d706e	3936
bogdanm	82:6473597d706e	3937	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3938	//! @brief Read current value of the DMA_HRS_HRS15 field.
bogdanm	82:6473597d706e	3939	#define BR_DMA_HRS_HRS15(x) (BITBAND_ACCESS32(HW_DMA_HRS_ADDR(x), BP_DMA_HRS_HRS15))
bogdanm	82:6473597d706e	3940	#endif
bogdanm	82:6473597d706e	3941	//@}
bogdanm	82:6473597d706e	3942
bogdanm	82:6473597d706e	3943	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3944	// HW_DMA_DCHPRIn - Channel n Priority Register
bogdanm	82:6473597d706e	3945	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	3946
bogdanm	82:6473597d706e	3947	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3948	/*!
bogdanm	82:6473597d706e	3949	* @brief HW_DMA_DCHPRIn - Channel n Priority Register (RW)
bogdanm	82:6473597d706e	3950	*
bogdanm	82:6473597d706e	3951	* Reset value: 0x00U
bogdanm	82:6473597d706e	3952	*
bogdanm	82:6473597d706e	3953	* When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the
bogdanm	82:6473597d706e	3954	* contents of these registers define the unique priorities associated with each
bogdanm	82:6473597d706e	3955	* channel . The channel priorities are evaluated by numeric value; for example, 0 is
bogdanm	82:6473597d706e	3956	* the lowest priority, 1 is the next priority, then 2, 3, etc. Software must
bogdanm	82:6473597d706e	3957	* program the channel priorities with unique values; otherwise, a configuration
bogdanm	82:6473597d706e	3958	* error is reported. The range of the priority value is limited to the values of 0
bogdanm	82:6473597d706e	3959	* through 15.
bogdanm	82:6473597d706e	3960	*/
bogdanm	82:6473597d706e	3961	typedef union _hw_dma_dchprin
bogdanm	82:6473597d706e	3962	{
bogdanm	82:6473597d706e	3963	uint8_t U;
bogdanm	82:6473597d706e	3964	struct _hw_dma_dchprin_bitfields
bogdanm	82:6473597d706e	3965	{
bogdanm	82:6473597d706e	3966	uint8_t CHPRI : 4; //!< [3:0] Channel n Arbitration Priority
bogdanm	82:6473597d706e	3967	uint8_t RESERVED0 : 2; //!< [5:4]
bogdanm	82:6473597d706e	3968	uint8_t DPA : 1; //!< [6] Disable Preempt Ability
bogdanm	82:6473597d706e	3969	uint8_t ECP : 1; //!< [7] Enable Channel Preemption
bogdanm	82:6473597d706e	3970	} B;
bogdanm	82:6473597d706e	3971	} hw_dma_dchprin_t;
bogdanm	82:6473597d706e	3972	#endif
bogdanm	82:6473597d706e	3973
bogdanm	82:6473597d706e	3974	/*!
bogdanm	82:6473597d706e	3975	* @name Constants and macros for entire DMA_DCHPRIn register
bogdanm	82:6473597d706e	3976	*/
bogdanm	82:6473597d706e	3977	//@{
bogdanm	82:6473597d706e	3978	#define HW_DMA_DCHPRIn_COUNT (16U)
bogdanm	82:6473597d706e	3979
bogdanm	82:6473597d706e	3980	#define HW_DMA_DCHPRIn_ADDR(x, n) (REGS_DMA_BASE(x) + 0x100U + (0x1U * n))
bogdanm	82:6473597d706e	3981
bogdanm	82:6473597d706e	3982	/* DMA channel index to DMA channel priority register array index conversion macro */
bogdanm	82:6473597d706e	3983	#define HW_DMA_DCHPRIn_CHANNEL(n) (((n) & ~0x03U) \| (3 - ((n) & 0x03U)))
bogdanm	82:6473597d706e	3984
bogdanm	82:6473597d706e	3985	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	3986	#define HW_DMA_DCHPRIn(x, n) ((__IO hw_dma_dchprin_t ) HW_DMA_DCHPRIn_ADDR(x, n))
bogdanm	82:6473597d706e	3987	#define HW_DMA_DCHPRIn_RD(x, n) (HW_DMA_DCHPRIn(x, n).U)
bogdanm	82:6473597d706e	3988	#define HW_DMA_DCHPRIn_WR(x, n, v) (HW_DMA_DCHPRIn(x, n).U = (v))
bogdanm	82:6473597d706e	3989	#define HW_DMA_DCHPRIn_SET(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	3990	#define HW_DMA_DCHPRIn_CLR(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	3991	#define HW_DMA_DCHPRIn_TOG(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, HW_DMA_DCHPRIn_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	3992	#endif
bogdanm	82:6473597d706e	3993	//@}
bogdanm	82:6473597d706e	3994
bogdanm	82:6473597d706e	3995	/*
bogdanm	82:6473597d706e	3996	* Constants & macros for individual DMA_DCHPRIn bitfields
bogdanm	82:6473597d706e	3997	*/
bogdanm	82:6473597d706e	3998
bogdanm	82:6473597d706e	3999	/*!
bogdanm	82:6473597d706e	4000	* @name Register DMA_DCHPRIn, field CHPRI[3:0] (RW)
bogdanm	82:6473597d706e	4001	*
bogdanm	82:6473597d706e	4002	* Channel priority when fixed-priority arbitration is enabled Reset value for
bogdanm	82:6473597d706e	4003	* the channel priority fields, CHPRI, is equal to the corresponding channel
bogdanm	82:6473597d706e	4004	* number for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
bogdanm	82:6473597d706e	4005	*/
bogdanm	82:6473597d706e	4006	//@{
bogdanm	82:6473597d706e	4007	#define BP_DMA_DCHPRIn_CHPRI (0U) //!< Bit position for DMA_DCHPRIn_CHPRI.
bogdanm	82:6473597d706e	4008	#define BM_DMA_DCHPRIn_CHPRI (0x0FU) //!< Bit mask for DMA_DCHPRIn_CHPRI.
bogdanm	82:6473597d706e	4009	#define BS_DMA_DCHPRIn_CHPRI (4U) //!< Bit field size in bits for DMA_DCHPRIn_CHPRI.
bogdanm	82:6473597d706e	4010
bogdanm	82:6473597d706e	4011	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4012	//! @brief Read current value of the DMA_DCHPRIn_CHPRI field.
bogdanm	82:6473597d706e	4013	#define BR_DMA_DCHPRIn_CHPRI(x, n) (HW_DMA_DCHPRIn(x, n).B.CHPRI)
bogdanm	82:6473597d706e	4014	#endif
bogdanm	82:6473597d706e	4015
bogdanm	82:6473597d706e	4016	//! @brief Format value for bitfield DMA_DCHPRIn_CHPRI.
bogdanm	82:6473597d706e	4017	#define BF_DMA_DCHPRIn_CHPRI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_CHPRI), uint8_t) & BM_DMA_DCHPRIn_CHPRI)
bogdanm	82:6473597d706e	4018
bogdanm	82:6473597d706e	4019	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4020	//! @brief Set the CHPRI field to a new value.
bogdanm	82:6473597d706e	4021	#define BW_DMA_DCHPRIn_CHPRI(x, n, v) (HW_DMA_DCHPRIn_WR(x, n, (HW_DMA_DCHPRIn_RD(x, n) & ~BM_DMA_DCHPRIn_CHPRI) \| BF_DMA_DCHPRIn_CHPRI(v)))
bogdanm	82:6473597d706e	4022	#endif
bogdanm	82:6473597d706e	4023	//@}
bogdanm	82:6473597d706e	4024
bogdanm	82:6473597d706e	4025	/*!
bogdanm	82:6473597d706e	4026	* @name Register DMA_DCHPRIn, field DPA[6] (RW)
bogdanm	82:6473597d706e	4027	*
bogdanm	82:6473597d706e	4028	* Values:
bogdanm	82:6473597d706e	4029	* - 0 - Channel n can suspend a lower priority channel
bogdanm	82:6473597d706e	4030	* - 1 - Channel n cannot suspend any channel, regardless of channel priority
bogdanm	82:6473597d706e	4031	*/
bogdanm	82:6473597d706e	4032	//@{
bogdanm	82:6473597d706e	4033	#define BP_DMA_DCHPRIn_DPA (6U) //!< Bit position for DMA_DCHPRIn_DPA.
bogdanm	82:6473597d706e	4034	#define BM_DMA_DCHPRIn_DPA (0x40U) //!< Bit mask for DMA_DCHPRIn_DPA.
bogdanm	82:6473597d706e	4035	#define BS_DMA_DCHPRIn_DPA (1U) //!< Bit field size in bits for DMA_DCHPRIn_DPA.
bogdanm	82:6473597d706e	4036
bogdanm	82:6473597d706e	4037	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4038	//! @brief Read current value of the DMA_DCHPRIn_DPA field.
bogdanm	82:6473597d706e	4039	#define BR_DMA_DCHPRIn_DPA(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA))
bogdanm	82:6473597d706e	4040	#endif
bogdanm	82:6473597d706e	4041
bogdanm	82:6473597d706e	4042	//! @brief Format value for bitfield DMA_DCHPRIn_DPA.
bogdanm	82:6473597d706e	4043	#define BF_DMA_DCHPRIn_DPA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_DPA), uint8_t) & BM_DMA_DCHPRIn_DPA)
bogdanm	82:6473597d706e	4044
bogdanm	82:6473597d706e	4045	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4046	//! @brief Set the DPA field to a new value.
bogdanm	82:6473597d706e	4047	#define BW_DMA_DCHPRIn_DPA(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_DPA) = (v))
bogdanm	82:6473597d706e	4048	#endif
bogdanm	82:6473597d706e	4049	//@}
bogdanm	82:6473597d706e	4050
bogdanm	82:6473597d706e	4051	/*!
bogdanm	82:6473597d706e	4052	* @name Register DMA_DCHPRIn, field ECP[7] (RW)
bogdanm	82:6473597d706e	4053	*
bogdanm	82:6473597d706e	4054	* Values:
bogdanm	82:6473597d706e	4055	* - 0 - Channel n cannot be suspended by a higher priority channel's service
bogdanm	82:6473597d706e	4056	* request
bogdanm	82:6473597d706e	4057	* - 1 - Channel n can be temporarily suspended by the service request of a
bogdanm	82:6473597d706e	4058	* higher priority channel
bogdanm	82:6473597d706e	4059	*/
bogdanm	82:6473597d706e	4060	//@{
bogdanm	82:6473597d706e	4061	#define BP_DMA_DCHPRIn_ECP (7U) //!< Bit position for DMA_DCHPRIn_ECP.
bogdanm	82:6473597d706e	4062	#define BM_DMA_DCHPRIn_ECP (0x80U) //!< Bit mask for DMA_DCHPRIn_ECP.
bogdanm	82:6473597d706e	4063	#define BS_DMA_DCHPRIn_ECP (1U) //!< Bit field size in bits for DMA_DCHPRIn_ECP.
bogdanm	82:6473597d706e	4064
bogdanm	82:6473597d706e	4065	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4066	//! @brief Read current value of the DMA_DCHPRIn_ECP field.
bogdanm	82:6473597d706e	4067	#define BR_DMA_DCHPRIn_ECP(x, n) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP))
bogdanm	82:6473597d706e	4068	#endif
bogdanm	82:6473597d706e	4069
bogdanm	82:6473597d706e	4070	//! @brief Format value for bitfield DMA_DCHPRIn_ECP.
bogdanm	82:6473597d706e	4071	#define BF_DMA_DCHPRIn_ECP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_DMA_DCHPRIn_ECP), uint8_t) & BM_DMA_DCHPRIn_ECP)
bogdanm	82:6473597d706e	4072
bogdanm	82:6473597d706e	4073	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4074	//! @brief Set the ECP field to a new value.
bogdanm	82:6473597d706e	4075	#define BW_DMA_DCHPRIn_ECP(x, n, v) (BITBAND_ACCESS8(HW_DMA_DCHPRIn_ADDR(x, n), BP_DMA_DCHPRIn_ECP) = (v))
bogdanm	82:6473597d706e	4076	#endif
bogdanm	82:6473597d706e	4077	//@}
bogdanm	82:6473597d706e	4078
bogdanm	82:6473597d706e	4079	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4080	// HW_DMA_TCDn_SADDR - TCD Source Address
bogdanm	82:6473597d706e	4081	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4082
bogdanm	82:6473597d706e	4083	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4084	/*!
bogdanm	82:6473597d706e	4085	* @brief HW_DMA_TCDn_SADDR - TCD Source Address (RW)
bogdanm	82:6473597d706e	4086	*
bogdanm	82:6473597d706e	4087	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4088	*/
bogdanm	82:6473597d706e	4089	typedef union _hw_dma_tcdn_saddr
bogdanm	82:6473597d706e	4090	{
bogdanm	82:6473597d706e	4091	uint32_t U;
bogdanm	82:6473597d706e	4092	struct _hw_dma_tcdn_saddr_bitfields
bogdanm	82:6473597d706e	4093	{
bogdanm	82:6473597d706e	4094	uint32_t SADDR : 32; //!< [31:0] Source Address
bogdanm	82:6473597d706e	4095	} B;
bogdanm	82:6473597d706e	4096	} hw_dma_tcdn_saddr_t;
bogdanm	82:6473597d706e	4097	#endif
bogdanm	82:6473597d706e	4098
bogdanm	82:6473597d706e	4099	/*!
bogdanm	82:6473597d706e	4100	* @name Constants and macros for entire DMA_TCDn_SADDR register
bogdanm	82:6473597d706e	4101	*/
bogdanm	82:6473597d706e	4102	//@{
bogdanm	82:6473597d706e	4103	#define HW_DMA_TCDn_SADDR_COUNT (16U)
bogdanm	82:6473597d706e	4104
bogdanm	82:6473597d706e	4105	#define HW_DMA_TCDn_SADDR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1000U + (0x20U * n))
bogdanm	82:6473597d706e	4106
bogdanm	82:6473597d706e	4107	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4108	#define HW_DMA_TCDn_SADDR(x, n) ((__IO hw_dma_tcdn_saddr_t ) HW_DMA_TCDn_SADDR_ADDR(x, n))
bogdanm	82:6473597d706e	4109	#define HW_DMA_TCDn_SADDR_RD(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
bogdanm	82:6473597d706e	4110	#define HW_DMA_TCDn_SADDR_WR(x, n, v) (HW_DMA_TCDn_SADDR(x, n).U = (v))
bogdanm	82:6473597d706e	4111	#define HW_DMA_TCDn_SADDR_SET(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	4112	#define HW_DMA_TCDn_SADDR_CLR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	4113	#define HW_DMA_TCDn_SADDR_TOG(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, HW_DMA_TCDn_SADDR_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	4114	#endif
bogdanm	82:6473597d706e	4115	//@}
bogdanm	82:6473597d706e	4116
bogdanm	82:6473597d706e	4117	/*
bogdanm	82:6473597d706e	4118	* Constants & macros for individual DMA_TCDn_SADDR bitfields
bogdanm	82:6473597d706e	4119	*/
bogdanm	82:6473597d706e	4120
bogdanm	82:6473597d706e	4121	/*!
bogdanm	82:6473597d706e	4122	* @name Register DMA_TCDn_SADDR, field SADDR[31:0] (RW)
bogdanm	82:6473597d706e	4123	*
bogdanm	82:6473597d706e	4124	* Memory address pointing to the source data.
bogdanm	82:6473597d706e	4125	*/
bogdanm	82:6473597d706e	4126	//@{
bogdanm	82:6473597d706e	4127	#define BP_DMA_TCDn_SADDR_SADDR (0U) //!< Bit position for DMA_TCDn_SADDR_SADDR.
bogdanm	82:6473597d706e	4128	#define BM_DMA_TCDn_SADDR_SADDR (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_SADDR_SADDR.
bogdanm	82:6473597d706e	4129	#define BS_DMA_TCDn_SADDR_SADDR (32U) //!< Bit field size in bits for DMA_TCDn_SADDR_SADDR.
bogdanm	82:6473597d706e	4130
bogdanm	82:6473597d706e	4131	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4132	//! @brief Read current value of the DMA_TCDn_SADDR_SADDR field.
bogdanm	82:6473597d706e	4133	#define BR_DMA_TCDn_SADDR_SADDR(x, n) (HW_DMA_TCDn_SADDR(x, n).U)
bogdanm	82:6473597d706e	4134	#endif
bogdanm	82:6473597d706e	4135
bogdanm	82:6473597d706e	4136	//! @brief Format value for bitfield DMA_TCDn_SADDR_SADDR.
bogdanm	82:6473597d706e	4137	#define BF_DMA_TCDn_SADDR_SADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_SADDR_SADDR), uint32_t) & BM_DMA_TCDn_SADDR_SADDR)
bogdanm	82:6473597d706e	4138
bogdanm	82:6473597d706e	4139	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4140	//! @brief Set the SADDR field to a new value.
bogdanm	82:6473597d706e	4141	#define BW_DMA_TCDn_SADDR_SADDR(x, n, v) (HW_DMA_TCDn_SADDR_WR(x, n, v))
bogdanm	82:6473597d706e	4142	#endif
bogdanm	82:6473597d706e	4143	//@}
bogdanm	82:6473597d706e	4144	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4145	// HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset
bogdanm	82:6473597d706e	4146	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4147
bogdanm	82:6473597d706e	4148	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4149	/*!
bogdanm	82:6473597d706e	4150	* @brief HW_DMA_TCDn_SOFF - TCD Signed Source Address Offset (RW)
bogdanm	82:6473597d706e	4151	*
bogdanm	82:6473597d706e	4152	* Reset value: 0x0000U
bogdanm	82:6473597d706e	4153	*/
bogdanm	82:6473597d706e	4154	typedef union _hw_dma_tcdn_soff
bogdanm	82:6473597d706e	4155	{
bogdanm	82:6473597d706e	4156	uint16_t U;
bogdanm	82:6473597d706e	4157	struct _hw_dma_tcdn_soff_bitfields
bogdanm	82:6473597d706e	4158	{
bogdanm	82:6473597d706e	4159	uint16_t SOFF : 16; //!< [15:0] Source address signed offset
bogdanm	82:6473597d706e	4160	} B;
bogdanm	82:6473597d706e	4161	} hw_dma_tcdn_soff_t;
bogdanm	82:6473597d706e	4162	#endif
bogdanm	82:6473597d706e	4163
bogdanm	82:6473597d706e	4164	/*!
bogdanm	82:6473597d706e	4165	* @name Constants and macros for entire DMA_TCDn_SOFF register
bogdanm	82:6473597d706e	4166	*/
bogdanm	82:6473597d706e	4167	//@{
bogdanm	82:6473597d706e	4168	#define HW_DMA_TCDn_SOFF_COUNT (16U)
bogdanm	82:6473597d706e	4169
bogdanm	82:6473597d706e	4170	#define HW_DMA_TCDn_SOFF_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1004U + (0x20U * n))
bogdanm	82:6473597d706e	4171
bogdanm	82:6473597d706e	4172	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4173	#define HW_DMA_TCDn_SOFF(x, n) ((__IO hw_dma_tcdn_soff_t ) HW_DMA_TCDn_SOFF_ADDR(x, n))
bogdanm	82:6473597d706e	4174	#define HW_DMA_TCDn_SOFF_RD(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
bogdanm	82:6473597d706e	4175	#define HW_DMA_TCDn_SOFF_WR(x, n, v) (HW_DMA_TCDn_SOFF(x, n).U = (v))
bogdanm	82:6473597d706e	4176	#define HW_DMA_TCDn_SOFF_SET(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	4177	#define HW_DMA_TCDn_SOFF_CLR(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	4178	#define HW_DMA_TCDn_SOFF_TOG(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, HW_DMA_TCDn_SOFF_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	4179	#endif
bogdanm	82:6473597d706e	4180	//@}
bogdanm	82:6473597d706e	4181
bogdanm	82:6473597d706e	4182	/*
bogdanm	82:6473597d706e	4183	* Constants & macros for individual DMA_TCDn_SOFF bitfields
bogdanm	82:6473597d706e	4184	*/
bogdanm	82:6473597d706e	4185
bogdanm	82:6473597d706e	4186	/*!
bogdanm	82:6473597d706e	4187	* @name Register DMA_TCDn_SOFF, field SOFF[15:0] (RW)
bogdanm	82:6473597d706e	4188	*
bogdanm	82:6473597d706e	4189	* Sign-extended offset applied to the current source address to form the
bogdanm	82:6473597d706e	4190	* next-state value as each source read is completed.
bogdanm	82:6473597d706e	4191	*/
bogdanm	82:6473597d706e	4192	//@{
bogdanm	82:6473597d706e	4193	#define BP_DMA_TCDn_SOFF_SOFF (0U) //!< Bit position for DMA_TCDn_SOFF_SOFF.
bogdanm	82:6473597d706e	4194	#define BM_DMA_TCDn_SOFF_SOFF (0xFFFFU) //!< Bit mask for DMA_TCDn_SOFF_SOFF.
bogdanm	82:6473597d706e	4195	#define BS_DMA_TCDn_SOFF_SOFF (16U) //!< Bit field size in bits for DMA_TCDn_SOFF_SOFF.
bogdanm	82:6473597d706e	4196
bogdanm	82:6473597d706e	4197	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4198	//! @brief Read current value of the DMA_TCDn_SOFF_SOFF field.
bogdanm	82:6473597d706e	4199	#define BR_DMA_TCDn_SOFF_SOFF(x, n) (HW_DMA_TCDn_SOFF(x, n).U)
bogdanm	82:6473597d706e	4200	#endif
bogdanm	82:6473597d706e	4201
bogdanm	82:6473597d706e	4202	//! @brief Format value for bitfield DMA_TCDn_SOFF_SOFF.
bogdanm	82:6473597d706e	4203	#define BF_DMA_TCDn_SOFF_SOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_SOFF_SOFF), uint16_t) & BM_DMA_TCDn_SOFF_SOFF)
bogdanm	82:6473597d706e	4204
bogdanm	82:6473597d706e	4205	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4206	//! @brief Set the SOFF field to a new value.
bogdanm	82:6473597d706e	4207	#define BW_DMA_TCDn_SOFF_SOFF(x, n, v) (HW_DMA_TCDn_SOFF_WR(x, n, v))
bogdanm	82:6473597d706e	4208	#endif
bogdanm	82:6473597d706e	4209	//@}
bogdanm	82:6473597d706e	4210	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4211	// HW_DMA_TCDn_ATTR - TCD Transfer Attributes
bogdanm	82:6473597d706e	4212	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4213
bogdanm	82:6473597d706e	4214	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4215	/*!
bogdanm	82:6473597d706e	4216	* @brief HW_DMA_TCDn_ATTR - TCD Transfer Attributes (RW)
bogdanm	82:6473597d706e	4217	*
bogdanm	82:6473597d706e	4218	* Reset value: 0x0000U
bogdanm	82:6473597d706e	4219	*/
bogdanm	82:6473597d706e	4220	typedef union _hw_dma_tcdn_attr
bogdanm	82:6473597d706e	4221	{
bogdanm	82:6473597d706e	4222	uint16_t U;
bogdanm	82:6473597d706e	4223	struct _hw_dma_tcdn_attr_bitfields
bogdanm	82:6473597d706e	4224	{
bogdanm	82:6473597d706e	4225	uint16_t DSIZE : 3; //!< [2:0] Destination Data Transfer Size
bogdanm	82:6473597d706e	4226	uint16_t DMOD : 5; //!< [7:3] Destination Address Modulo
bogdanm	82:6473597d706e	4227	uint16_t SSIZE : 3; //!< [10:8] Source data transfer size
bogdanm	82:6473597d706e	4228	uint16_t SMOD : 5; //!< [15:11] Source Address Modulo.
bogdanm	82:6473597d706e	4229	} B;
bogdanm	82:6473597d706e	4230	} hw_dma_tcdn_attr_t;
bogdanm	82:6473597d706e	4231	#endif
bogdanm	82:6473597d706e	4232
bogdanm	82:6473597d706e	4233	/*!
bogdanm	82:6473597d706e	4234	* @name Constants and macros for entire DMA_TCDn_ATTR register
bogdanm	82:6473597d706e	4235	*/
bogdanm	82:6473597d706e	4236	//@{
bogdanm	82:6473597d706e	4237	#define HW_DMA_TCDn_ATTR_COUNT (16U)
bogdanm	82:6473597d706e	4238
bogdanm	82:6473597d706e	4239	#define HW_DMA_TCDn_ATTR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1006U + (0x20U * n))
bogdanm	82:6473597d706e	4240
bogdanm	82:6473597d706e	4241	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4242	#define HW_DMA_TCDn_ATTR(x, n) ((__IO hw_dma_tcdn_attr_t ) HW_DMA_TCDn_ATTR_ADDR(x, n))
bogdanm	82:6473597d706e	4243	#define HW_DMA_TCDn_ATTR_RD(x, n) (HW_DMA_TCDn_ATTR(x, n).U)
bogdanm	82:6473597d706e	4244	#define HW_DMA_TCDn_ATTR_WR(x, n, v) (HW_DMA_TCDn_ATTR(x, n).U = (v))
bogdanm	82:6473597d706e	4245	#define HW_DMA_TCDn_ATTR_SET(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	4246	#define HW_DMA_TCDn_ATTR_CLR(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	4247	#define HW_DMA_TCDn_ATTR_TOG(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, HW_DMA_TCDn_ATTR_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	4248	#endif
bogdanm	82:6473597d706e	4249	//@}
bogdanm	82:6473597d706e	4250
bogdanm	82:6473597d706e	4251	/*
bogdanm	82:6473597d706e	4252	* Constants & macros for individual DMA_TCDn_ATTR bitfields
bogdanm	82:6473597d706e	4253	*/
bogdanm	82:6473597d706e	4254
bogdanm	82:6473597d706e	4255	/*!
bogdanm	82:6473597d706e	4256	* @name Register DMA_TCDn_ATTR, field DSIZE[2:0] (RW)
bogdanm	82:6473597d706e	4257	*
bogdanm	82:6473597d706e	4258	* See the SSIZE definition
bogdanm	82:6473597d706e	4259	*/
bogdanm	82:6473597d706e	4260	//@{
bogdanm	82:6473597d706e	4261	#define BP_DMA_TCDn_ATTR_DSIZE (0U) //!< Bit position for DMA_TCDn_ATTR_DSIZE.
bogdanm	82:6473597d706e	4262	#define BM_DMA_TCDn_ATTR_DSIZE (0x0007U) //!< Bit mask for DMA_TCDn_ATTR_DSIZE.
bogdanm	82:6473597d706e	4263	#define BS_DMA_TCDn_ATTR_DSIZE (3U) //!< Bit field size in bits for DMA_TCDn_ATTR_DSIZE.
bogdanm	82:6473597d706e	4264
bogdanm	82:6473597d706e	4265	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4266	//! @brief Read current value of the DMA_TCDn_ATTR_DSIZE field.
bogdanm	82:6473597d706e	4267	#define BR_DMA_TCDn_ATTR_DSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DSIZE)
bogdanm	82:6473597d706e	4268	#endif
bogdanm	82:6473597d706e	4269
bogdanm	82:6473597d706e	4270	//! @brief Format value for bitfield DMA_TCDn_ATTR_DSIZE.
bogdanm	82:6473597d706e	4271	#define BF_DMA_TCDn_ATTR_DSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_DSIZE), uint16_t) & BM_DMA_TCDn_ATTR_DSIZE)
bogdanm	82:6473597d706e	4272
bogdanm	82:6473597d706e	4273	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4274	//! @brief Set the DSIZE field to a new value.
bogdanm	82:6473597d706e	4275	#define BW_DMA_TCDn_ATTR_DSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DSIZE) \| BF_DMA_TCDn_ATTR_DSIZE(v)))
bogdanm	82:6473597d706e	4276	#endif
bogdanm	82:6473597d706e	4277	//@}
bogdanm	82:6473597d706e	4278
bogdanm	82:6473597d706e	4279	/*!
bogdanm	82:6473597d706e	4280	* @name Register DMA_TCDn_ATTR, field DMOD[7:3] (RW)
bogdanm	82:6473597d706e	4281	*
bogdanm	82:6473597d706e	4282	* See the SMOD definition
bogdanm	82:6473597d706e	4283	*/
bogdanm	82:6473597d706e	4284	//@{
bogdanm	82:6473597d706e	4285	#define BP_DMA_TCDn_ATTR_DMOD (3U) //!< Bit position for DMA_TCDn_ATTR_DMOD.
bogdanm	82:6473597d706e	4286	#define BM_DMA_TCDn_ATTR_DMOD (0x00F8U) //!< Bit mask for DMA_TCDn_ATTR_DMOD.
bogdanm	82:6473597d706e	4287	#define BS_DMA_TCDn_ATTR_DMOD (5U) //!< Bit field size in bits for DMA_TCDn_ATTR_DMOD.
bogdanm	82:6473597d706e	4288
bogdanm	82:6473597d706e	4289	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4290	//! @brief Read current value of the DMA_TCDn_ATTR_DMOD field.
bogdanm	82:6473597d706e	4291	#define BR_DMA_TCDn_ATTR_DMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.DMOD)
bogdanm	82:6473597d706e	4292	#endif
bogdanm	82:6473597d706e	4293
bogdanm	82:6473597d706e	4294	//! @brief Format value for bitfield DMA_TCDn_ATTR_DMOD.
bogdanm	82:6473597d706e	4295	#define BF_DMA_TCDn_ATTR_DMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_DMOD), uint16_t) & BM_DMA_TCDn_ATTR_DMOD)
bogdanm	82:6473597d706e	4296
bogdanm	82:6473597d706e	4297	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4298	//! @brief Set the DMOD field to a new value.
bogdanm	82:6473597d706e	4299	#define BW_DMA_TCDn_ATTR_DMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_DMOD) \| BF_DMA_TCDn_ATTR_DMOD(v)))
bogdanm	82:6473597d706e	4300	#endif
bogdanm	82:6473597d706e	4301	//@}
bogdanm	82:6473597d706e	4302
bogdanm	82:6473597d706e	4303	/*!
bogdanm	82:6473597d706e	4304	* @name Register DMA_TCDn_ATTR, field SSIZE[10:8] (RW)
bogdanm	82:6473597d706e	4305	*
bogdanm	82:6473597d706e	4306	* The attempted use of a Reserved encoding causes a configuration error.
bogdanm	82:6473597d706e	4307	*
bogdanm	82:6473597d706e	4308	* Values:
bogdanm	82:6473597d706e	4309	* - 000 - 8-bit
bogdanm	82:6473597d706e	4310	* - 001 - 16-bit
bogdanm	82:6473597d706e	4311	* - 010 - 32-bit
bogdanm	82:6473597d706e	4312	* - 011 - Reserved
bogdanm	82:6473597d706e	4313	* - 100 - 16-byte
bogdanm	82:6473597d706e	4314	* - 101 - 32-byte
bogdanm	82:6473597d706e	4315	* - 110 - Reserved
bogdanm	82:6473597d706e	4316	* - 111 - Reserved
bogdanm	82:6473597d706e	4317	*/
bogdanm	82:6473597d706e	4318	//@{
bogdanm	82:6473597d706e	4319	#define BP_DMA_TCDn_ATTR_SSIZE (8U) //!< Bit position for DMA_TCDn_ATTR_SSIZE.
bogdanm	82:6473597d706e	4320	#define BM_DMA_TCDn_ATTR_SSIZE (0x0700U) //!< Bit mask for DMA_TCDn_ATTR_SSIZE.
bogdanm	82:6473597d706e	4321	#define BS_DMA_TCDn_ATTR_SSIZE (3U) //!< Bit field size in bits for DMA_TCDn_ATTR_SSIZE.
bogdanm	82:6473597d706e	4322
bogdanm	82:6473597d706e	4323	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4324	//! @brief Read current value of the DMA_TCDn_ATTR_SSIZE field.
bogdanm	82:6473597d706e	4325	#define BR_DMA_TCDn_ATTR_SSIZE(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SSIZE)
bogdanm	82:6473597d706e	4326	#endif
bogdanm	82:6473597d706e	4327
bogdanm	82:6473597d706e	4328	//! @brief Format value for bitfield DMA_TCDn_ATTR_SSIZE.
bogdanm	82:6473597d706e	4329	#define BF_DMA_TCDn_ATTR_SSIZE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_SSIZE), uint16_t) & BM_DMA_TCDn_ATTR_SSIZE)
bogdanm	82:6473597d706e	4330
bogdanm	82:6473597d706e	4331	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4332	//! @brief Set the SSIZE field to a new value.
bogdanm	82:6473597d706e	4333	#define BW_DMA_TCDn_ATTR_SSIZE(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SSIZE) \| BF_DMA_TCDn_ATTR_SSIZE(v)))
bogdanm	82:6473597d706e	4334	#endif
bogdanm	82:6473597d706e	4335	//@}
bogdanm	82:6473597d706e	4336
bogdanm	82:6473597d706e	4337	/*!
bogdanm	82:6473597d706e	4338	* @name Register DMA_TCDn_ATTR, field SMOD[15:11] (RW)
bogdanm	82:6473597d706e	4339	*
bogdanm	82:6473597d706e	4340	* Values:
bogdanm	82:6473597d706e	4341	* - 0 - Source address modulo feature is disabled
bogdanm	82:6473597d706e	4342	*/
bogdanm	82:6473597d706e	4343	//@{
bogdanm	82:6473597d706e	4344	#define BP_DMA_TCDn_ATTR_SMOD (11U) //!< Bit position for DMA_TCDn_ATTR_SMOD.
bogdanm	82:6473597d706e	4345	#define BM_DMA_TCDn_ATTR_SMOD (0xF800U) //!< Bit mask for DMA_TCDn_ATTR_SMOD.
bogdanm	82:6473597d706e	4346	#define BS_DMA_TCDn_ATTR_SMOD (5U) //!< Bit field size in bits for DMA_TCDn_ATTR_SMOD.
bogdanm	82:6473597d706e	4347
bogdanm	82:6473597d706e	4348	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4349	//! @brief Read current value of the DMA_TCDn_ATTR_SMOD field.
bogdanm	82:6473597d706e	4350	#define BR_DMA_TCDn_ATTR_SMOD(x, n) (HW_DMA_TCDn_ATTR(x, n).B.SMOD)
bogdanm	82:6473597d706e	4351	#endif
bogdanm	82:6473597d706e	4352
bogdanm	82:6473597d706e	4353	//! @brief Format value for bitfield DMA_TCDn_ATTR_SMOD.
bogdanm	82:6473597d706e	4354	#define BF_DMA_TCDn_ATTR_SMOD(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_ATTR_SMOD), uint16_t) & BM_DMA_TCDn_ATTR_SMOD)
bogdanm	82:6473597d706e	4355
bogdanm	82:6473597d706e	4356	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4357	//! @brief Set the SMOD field to a new value.
bogdanm	82:6473597d706e	4358	#define BW_DMA_TCDn_ATTR_SMOD(x, n, v) (HW_DMA_TCDn_ATTR_WR(x, n, (HW_DMA_TCDn_ATTR_RD(x, n) & ~BM_DMA_TCDn_ATTR_SMOD) \| BF_DMA_TCDn_ATTR_SMOD(v)))
bogdanm	82:6473597d706e	4359	#endif
bogdanm	82:6473597d706e	4360	//@}
bogdanm	82:6473597d706e	4361	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4362	// HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled)
bogdanm	82:6473597d706e	4363	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4364
bogdanm	82:6473597d706e	4365	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4366	/*!
bogdanm	82:6473597d706e	4367	* @brief HW_DMA_TCDn_NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) (RW)
bogdanm	82:6473597d706e	4368	*
bogdanm	82:6473597d706e	4369	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4370	*
bogdanm	82:6473597d706e	4371	* This register, or one of the next two registers (TCD_NBYTES_MLOFFNO,
bogdanm	82:6473597d706e	4372	* TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which
bogdanm	82:6473597d706e	4373	* register to use depends on whether minor loop mapping is disabled, enabled but not
bogdanm	82:6473597d706e	4374	* used for this channel, or enabled and used. TCD word 2 is defined as follows
bogdanm	82:6473597d706e	4375	* if: Minor loop mapping is disabled (CR[EMLM] = 0) If minor loop mapping is
bogdanm	82:6473597d706e	4376	* enabled, see the TCD_NBYTES_MLOFFNO and TCD_NBYTES_MLOFFYES register descriptions
bogdanm	82:6473597d706e	4377	* for TCD word 2's definition.
bogdanm	82:6473597d706e	4378	*/
bogdanm	82:6473597d706e	4379	typedef union _hw_dma_tcdn_nbytes_mlno
bogdanm	82:6473597d706e	4380	{
bogdanm	82:6473597d706e	4381	uint32_t U;
bogdanm	82:6473597d706e	4382	struct _hw_dma_tcdn_nbytes_mlno_bitfields
bogdanm	82:6473597d706e	4383	{
bogdanm	82:6473597d706e	4384	uint32_t NBYTES : 32; //!< [31:0] Minor Byte Transfer Count
bogdanm	82:6473597d706e	4385	} B;
bogdanm	82:6473597d706e	4386	} hw_dma_tcdn_nbytes_mlno_t;
bogdanm	82:6473597d706e	4387	#endif
bogdanm	82:6473597d706e	4388
bogdanm	82:6473597d706e	4389	/*!
bogdanm	82:6473597d706e	4390	* @name Constants and macros for entire DMA_TCDn_NBYTES_MLNO register
bogdanm	82:6473597d706e	4391	*/
bogdanm	82:6473597d706e	4392	//@{
bogdanm	82:6473597d706e	4393	#define HW_DMA_TCDn_NBYTES_MLNO_COUNT (16U)
bogdanm	82:6473597d706e	4394
bogdanm	82:6473597d706e	4395	#define HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
bogdanm	82:6473597d706e	4396
bogdanm	82:6473597d706e	4397	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4398	#define HW_DMA_TCDn_NBYTES_MLNO(x, n) ((__IO hw_dma_tcdn_nbytes_mlno_t ) HW_DMA_TCDn_NBYTES_MLNO_ADDR(x, n))
bogdanm	82:6473597d706e	4399	#define HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
bogdanm	82:6473597d706e	4400	#define HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U = (v))
bogdanm	82:6473597d706e	4401	#define HW_DMA_TCDn_NBYTES_MLNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	4402	#define HW_DMA_TCDn_NBYTES_MLNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	4403	#define HW_DMA_TCDn_NBYTES_MLNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLNO_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	4404	#endif
bogdanm	82:6473597d706e	4405	//@}
bogdanm	82:6473597d706e	4406
bogdanm	82:6473597d706e	4407	/*
bogdanm	82:6473597d706e	4408	* Constants & macros for individual DMA_TCDn_NBYTES_MLNO bitfields
bogdanm	82:6473597d706e	4409	*/
bogdanm	82:6473597d706e	4410
bogdanm	82:6473597d706e	4411	/*!
bogdanm	82:6473597d706e	4412	* @name Register DMA_TCDn_NBYTES_MLNO, field NBYTES[31:0] (RW)
bogdanm	82:6473597d706e	4413	*
bogdanm	82:6473597d706e	4414	* Number of bytes to be transferred in each service request of the channel. As
bogdanm	82:6473597d706e	4415	* a channel activates, the appropriate TCD contents load into the eDMA engine,
bogdanm	82:6473597d706e	4416	* and the appropriate reads and writes perform until the minor byte transfer
bogdanm	82:6473597d706e	4417	* count has transferred. This is an indivisible operation and cannot be halted.
bogdanm	82:6473597d706e	4418	* (Although, it may be stalled by using the bandwidth control field, or via
bogdanm	82:6473597d706e	4419	* preemption.) After the minor count is exhausted, the SADDR and DADDR values are
bogdanm	82:6473597d706e	4420	* written back into the TCD memory, the major iteration count is decremented and
bogdanm	82:6473597d706e	4421	* restored to the TCD memory. If the major iteration count is completed, additional
bogdanm	82:6473597d706e	4422	* processing is performed. An NBYTES value of 0x0000_0000 is interpreted as a 4
bogdanm	82:6473597d706e	4423	* GB transfer.
bogdanm	82:6473597d706e	4424	*/
bogdanm	82:6473597d706e	4425	//@{
bogdanm	82:6473597d706e	4426	#define BP_DMA_TCDn_NBYTES_MLNO_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLNO_NBYTES.
bogdanm	82:6473597d706e	4427	#define BM_DMA_TCDn_NBYTES_MLNO_NBYTES (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_NBYTES_MLNO_NBYTES.
bogdanm	82:6473597d706e	4428	#define BS_DMA_TCDn_NBYTES_MLNO_NBYTES (32U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLNO_NBYTES.
bogdanm	82:6473597d706e	4429
bogdanm	82:6473597d706e	4430	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4431	//! @brief Read current value of the DMA_TCDn_NBYTES_MLNO_NBYTES field.
bogdanm	82:6473597d706e	4432	#define BR_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLNO(x, n).U)
bogdanm	82:6473597d706e	4433	#endif
bogdanm	82:6473597d706e	4434
bogdanm	82:6473597d706e	4435	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLNO_NBYTES.
bogdanm	82:6473597d706e	4436	#define BF_DMA_TCDn_NBYTES_MLNO_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLNO_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLNO_NBYTES)
bogdanm	82:6473597d706e	4437
bogdanm	82:6473597d706e	4438	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4439	//! @brief Set the NBYTES field to a new value.
bogdanm	82:6473597d706e	4440	#define BW_DMA_TCDn_NBYTES_MLNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLNO_WR(x, n, v))
bogdanm	82:6473597d706e	4441	#endif
bogdanm	82:6473597d706e	4442	//@}
bogdanm	82:6473597d706e	4443	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4444	// HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
bogdanm	82:6473597d706e	4445	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4446
bogdanm	82:6473597d706e	4447	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4448	/*!
bogdanm	82:6473597d706e	4449	* @brief HW_DMA_TCDn_NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (RW)
bogdanm	82:6473597d706e	4450	*
bogdanm	82:6473597d706e	4451	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4452	*
bogdanm	82:6473597d706e	4453	* One of three registers (this register, TCD_NBYTES_MLNO, or
bogdanm	82:6473597d706e	4454	* TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use
bogdanm	82:6473597d706e	4455	* depends on whether minor loop mapping is disabled, enabled but not used for
bogdanm	82:6473597d706e	4456	* this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
bogdanm	82:6473597d706e	4457	* loop mapping is enabled (CR[EMLM] = 1) and SMLOE = 0 and DMLOE = 0 If minor
bogdanm	82:6473597d706e	4458	* loop mapping is enabled and SMLOE or DMLOE is set, then refer to the
bogdanm	82:6473597d706e	4459	* TCD_NBYTES_MLOFFYES register description. If minor loop mapping is disabled, then refer to
bogdanm	82:6473597d706e	4460	* the TCD_NBYTES_MLNO register description.
bogdanm	82:6473597d706e	4461	*/
bogdanm	82:6473597d706e	4462	typedef union _hw_dma_tcdn_nbytes_mloffno
bogdanm	82:6473597d706e	4463	{
bogdanm	82:6473597d706e	4464	uint32_t U;
bogdanm	82:6473597d706e	4465	struct _hw_dma_tcdn_nbytes_mloffno_bitfields
bogdanm	82:6473597d706e	4466	{
bogdanm	82:6473597d706e	4467	uint32_t NBYTES : 30; //!< [29:0] Minor Byte Transfer Count
bogdanm	82:6473597d706e	4468	uint32_t DMLOE : 1; //!< [30] Destination Minor Loop Offset enable
bogdanm	82:6473597d706e	4469	uint32_t SMLOE : 1; //!< [31] Source Minor Loop Offset Enable
bogdanm	82:6473597d706e	4470	} B;
bogdanm	82:6473597d706e	4471	} hw_dma_tcdn_nbytes_mloffno_t;
bogdanm	82:6473597d706e	4472	#endif
bogdanm	82:6473597d706e	4473
bogdanm	82:6473597d706e	4474	/*!
bogdanm	82:6473597d706e	4475	* @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFNO register
bogdanm	82:6473597d706e	4476	*/
bogdanm	82:6473597d706e	4477	//@{
bogdanm	82:6473597d706e	4478	#define HW_DMA_TCDn_NBYTES_MLOFFNO_COUNT (16U)
bogdanm	82:6473597d706e	4479
bogdanm	82:6473597d706e	4480	#define HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
bogdanm	82:6473597d706e	4481
bogdanm	82:6473597d706e	4482	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4483	#define HW_DMA_TCDn_NBYTES_MLOFFNO(x, n) ((__IO hw_dma_tcdn_nbytes_mloffno_t ) HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n))
bogdanm	82:6473597d706e	4484	#define HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U)
bogdanm	82:6473597d706e	4485	#define HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).U = (v))
bogdanm	82:6473597d706e	4486	#define HW_DMA_TCDn_NBYTES_MLOFFNO_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	4487	#define HW_DMA_TCDn_NBYTES_MLOFFNO_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	4488	#define HW_DMA_TCDn_NBYTES_MLOFFNO_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	4489	#endif
bogdanm	82:6473597d706e	4490	//@}
bogdanm	82:6473597d706e	4491
bogdanm	82:6473597d706e	4492	/*
bogdanm	82:6473597d706e	4493	* Constants & macros for individual DMA_TCDn_NBYTES_MLOFFNO bitfields
bogdanm	82:6473597d706e	4494	*/
bogdanm	82:6473597d706e	4495
bogdanm	82:6473597d706e	4496	/*!
bogdanm	82:6473597d706e	4497	* @name Register DMA_TCDn_NBYTES_MLOFFNO, field NBYTES[29:0] (RW)
bogdanm	82:6473597d706e	4498	*
bogdanm	82:6473597d706e	4499	* Number of bytes to be transferred in each service request of the channel. As
bogdanm	82:6473597d706e	4500	* a channel activates, the appropriate TCD contents load into the eDMA engine,
bogdanm	82:6473597d706e	4501	* and the appropriate reads and writes perform until the minor byte transfer
bogdanm	82:6473597d706e	4502	* count has transferred. This is an indivisible operation and cannot be halted;
bogdanm	82:6473597d706e	4503	* although, it may be stalled by using the bandwidth control field, or via
bogdanm	82:6473597d706e	4504	* preemption. After the minor count is exhausted, the SADDR and DADDR values are written
bogdanm	82:6473597d706e	4505	* back into the TCD memory, the major iteration count is decremented and
bogdanm	82:6473597d706e	4506	* restored to the TCD memory. If the major iteration count is completed, additional
bogdanm	82:6473597d706e	4507	* processing is performed.
bogdanm	82:6473597d706e	4508	*/
bogdanm	82:6473597d706e	4509	//@{
bogdanm	82:6473597d706e	4510	#define BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
bogdanm	82:6473597d706e	4511	#define BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (0x3FFFFFFFU) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
bogdanm	82:6473597d706e	4512	#define BS_DMA_TCDn_NBYTES_MLOFFNO_NBYTES (30U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
bogdanm	82:6473597d706e	4513
bogdanm	82:6473597d706e	4514	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4515	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_NBYTES field.
bogdanm	82:6473597d706e	4516	#define BR_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFNO(x, n).B.NBYTES)
bogdanm	82:6473597d706e	4517	#endif
bogdanm	82:6473597d706e	4518
bogdanm	82:6473597d706e	4519	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_NBYTES.
bogdanm	82:6473597d706e	4520	#define BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES)
bogdanm	82:6473597d706e	4521
bogdanm	82:6473597d706e	4522	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4523	//! @brief Set the NBYTES field to a new value.
bogdanm	82:6473597d706e	4524	#define BW_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFNO_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFNO_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFNO_NBYTES) \| BF_DMA_TCDn_NBYTES_MLOFFNO_NBYTES(v)))
bogdanm	82:6473597d706e	4525	#endif
bogdanm	82:6473597d706e	4526	//@}
bogdanm	82:6473597d706e	4527
bogdanm	82:6473597d706e	4528	/*!
bogdanm	82:6473597d706e	4529	* @name Register DMA_TCDn_NBYTES_MLOFFNO, field DMLOE[30] (RW)
bogdanm	82:6473597d706e	4530	*
bogdanm	82:6473597d706e	4531	* Selects whether the minor loop offset is applied to the destination address
bogdanm	82:6473597d706e	4532	* upon minor loop completion.
bogdanm	82:6473597d706e	4533	*
bogdanm	82:6473597d706e	4534	* Values:
bogdanm	82:6473597d706e	4535	* - 0 - The minor loop offset is not applied to the DADDR
bogdanm	82:6473597d706e	4536	* - 1 - The minor loop offset is applied to the DADDR
bogdanm	82:6473597d706e	4537	*/
bogdanm	82:6473597d706e	4538	//@{
bogdanm	82:6473597d706e	4539	#define BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (30U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
bogdanm	82:6473597d706e	4540	#define BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (0x40000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
bogdanm	82:6473597d706e	4541	#define BS_DMA_TCDn_NBYTES_MLOFFNO_DMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
bogdanm	82:6473597d706e	4542
bogdanm	82:6473597d706e	4543	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4544	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_DMLOE field.
bogdanm	82:6473597d706e	4545	#define BR_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE))
bogdanm	82:6473597d706e	4546	#endif
bogdanm	82:6473597d706e	4547
bogdanm	82:6473597d706e	4548	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_DMLOE.
bogdanm	82:6473597d706e	4549	#define BF_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_DMLOE)
bogdanm	82:6473597d706e	4550
bogdanm	82:6473597d706e	4551	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4552	//! @brief Set the DMLOE field to a new value.
bogdanm	82:6473597d706e	4553	#define BW_DMA_TCDn_NBYTES_MLOFFNO_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_DMLOE) = (v))
bogdanm	82:6473597d706e	4554	#endif
bogdanm	82:6473597d706e	4555	//@}
bogdanm	82:6473597d706e	4556
bogdanm	82:6473597d706e	4557	/*!
bogdanm	82:6473597d706e	4558	* @name Register DMA_TCDn_NBYTES_MLOFFNO, field SMLOE[31] (RW)
bogdanm	82:6473597d706e	4559	*
bogdanm	82:6473597d706e	4560	* Selects whether the minor loop offset is applied to the source address upon
bogdanm	82:6473597d706e	4561	* minor loop completion.
bogdanm	82:6473597d706e	4562	*
bogdanm	82:6473597d706e	4563	* Values:
bogdanm	82:6473597d706e	4564	* - 0 - The minor loop offset is not applied to the SADDR
bogdanm	82:6473597d706e	4565	* - 1 - The minor loop offset is applied to the SADDR
bogdanm	82:6473597d706e	4566	*/
bogdanm	82:6473597d706e	4567	//@{
bogdanm	82:6473597d706e	4568	#define BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (31U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
bogdanm	82:6473597d706e	4569	#define BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (0x80000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
bogdanm	82:6473597d706e	4570	#define BS_DMA_TCDn_NBYTES_MLOFFNO_SMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
bogdanm	82:6473597d706e	4571
bogdanm	82:6473597d706e	4572	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4573	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFNO_SMLOE field.
bogdanm	82:6473597d706e	4574	#define BR_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE))
bogdanm	82:6473597d706e	4575	#endif
bogdanm	82:6473597d706e	4576
bogdanm	82:6473597d706e	4577	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFNO_SMLOE.
bogdanm	82:6473597d706e	4578	#define BF_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFNO_SMLOE)
bogdanm	82:6473597d706e	4579
bogdanm	82:6473597d706e	4580	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4581	//! @brief Set the SMLOE field to a new value.
bogdanm	82:6473597d706e	4582	#define BW_DMA_TCDn_NBYTES_MLOFFNO_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFNO_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFNO_SMLOE) = (v))
bogdanm	82:6473597d706e	4583	#endif
bogdanm	82:6473597d706e	4584	//@}
bogdanm	82:6473597d706e	4585	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4586	// HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
bogdanm	82:6473597d706e	4587	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4588
bogdanm	82:6473597d706e	4589	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4590	/*!
bogdanm	82:6473597d706e	4591	* @brief HW_DMA_TCDn_NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) (RW)
bogdanm	82:6473597d706e	4592	*
bogdanm	82:6473597d706e	4593	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4594	*
bogdanm	82:6473597d706e	4595	* One of three registers (this register, TCD_NBYTES_MLNO, or
bogdanm	82:6473597d706e	4596	* TCD_NBYTES_MLOFFNO), defines the number of bytes to transfer per request. Which register to use
bogdanm	82:6473597d706e	4597	* depends on whether minor loop mapping is disabled, enabled but not used for
bogdanm	82:6473597d706e	4598	* this channel, or enabled and used. TCD word 2 is defined as follows if: Minor
bogdanm	82:6473597d706e	4599	* loop mapping is enabled (CR[EMLM] = 1) and Minor loop offset is enabled (SMLOE
bogdanm	82:6473597d706e	4600	* or DMLOE = 1) If minor loop mapping is enabled and SMLOE and DMLOE are cleared,
bogdanm	82:6473597d706e	4601	* then refer to the TCD_NBYTES_MLOFFNO register description. If minor loop
bogdanm	82:6473597d706e	4602	* mapping is disabled, then refer to the TCD_NBYTES_MLNO register description.
bogdanm	82:6473597d706e	4603	*/
bogdanm	82:6473597d706e	4604	typedef union _hw_dma_tcdn_nbytes_mloffyes
bogdanm	82:6473597d706e	4605	{
bogdanm	82:6473597d706e	4606	uint32_t U;
bogdanm	82:6473597d706e	4607	struct _hw_dma_tcdn_nbytes_mloffyes_bitfields
bogdanm	82:6473597d706e	4608	{
bogdanm	82:6473597d706e	4609	uint32_t NBYTES : 10; //!< [9:0] Minor Byte Transfer Count
bogdanm	82:6473597d706e	4610	uint32_t MLOFF : 20; //!< [29:10] If SMLOE or DMLOE is set, this
bogdanm	82:6473597d706e	4611	//! field represents a sign-extended offset applied to the source or
bogdanm	82:6473597d706e	4612	//! destination address to form the next-state value after the minor loop completes.
bogdanm	82:6473597d706e	4613	uint32_t DMLOE : 1; //!< [30] Destination Minor Loop Offset enable
bogdanm	82:6473597d706e	4614	uint32_t SMLOE : 1; //!< [31] Source Minor Loop Offset Enable
bogdanm	82:6473597d706e	4615	} B;
bogdanm	82:6473597d706e	4616	} hw_dma_tcdn_nbytes_mloffyes_t;
bogdanm	82:6473597d706e	4617	#endif
bogdanm	82:6473597d706e	4618
bogdanm	82:6473597d706e	4619	/*!
bogdanm	82:6473597d706e	4620	* @name Constants and macros for entire DMA_TCDn_NBYTES_MLOFFYES register
bogdanm	82:6473597d706e	4621	*/
bogdanm	82:6473597d706e	4622	//@{
bogdanm	82:6473597d706e	4623	#define HW_DMA_TCDn_NBYTES_MLOFFYES_COUNT (16U)
bogdanm	82:6473597d706e	4624
bogdanm	82:6473597d706e	4625	#define HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1008U + (0x20U * n))
bogdanm	82:6473597d706e	4626
bogdanm	82:6473597d706e	4627	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4628	#define HW_DMA_TCDn_NBYTES_MLOFFYES(x, n) ((__IO hw_dma_tcdn_nbytes_mloffyes_t ) HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n))
bogdanm	82:6473597d706e	4629	#define HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U)
bogdanm	82:6473597d706e	4630	#define HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).U = (v))
bogdanm	82:6473597d706e	4631	#define HW_DMA_TCDn_NBYTES_MLOFFYES_SET(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	4632	#define HW_DMA_TCDn_NBYTES_MLOFFYES_CLR(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	4633	#define HW_DMA_TCDn_NBYTES_MLOFFYES_TOG(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	4634	#endif
bogdanm	82:6473597d706e	4635	//@}
bogdanm	82:6473597d706e	4636
bogdanm	82:6473597d706e	4637	/*
bogdanm	82:6473597d706e	4638	* Constants & macros for individual DMA_TCDn_NBYTES_MLOFFYES bitfields
bogdanm	82:6473597d706e	4639	*/
bogdanm	82:6473597d706e	4640
bogdanm	82:6473597d706e	4641	/*!
bogdanm	82:6473597d706e	4642	* @name Register DMA_TCDn_NBYTES_MLOFFYES, field NBYTES[9:0] (RW)
bogdanm	82:6473597d706e	4643	*
bogdanm	82:6473597d706e	4644	* Number of bytes to be transferred in each service request of the channel. As
bogdanm	82:6473597d706e	4645	* a channel activates, the appropriate TCD contents load into the eDMA engine,
bogdanm	82:6473597d706e	4646	* and the appropriate reads and writes perform until the minor byte transfer
bogdanm	82:6473597d706e	4647	* count has transferred. This is an indivisible operation and cannot be halted.
bogdanm	82:6473597d706e	4648	* (Although, it may be stalled by using the bandwidth control field, or via
bogdanm	82:6473597d706e	4649	* preemption.) After the minor count is exhausted, the SADDR and DADDR values are
bogdanm	82:6473597d706e	4650	* written back into the TCD memory, the major iteration count is decremented and
bogdanm	82:6473597d706e	4651	* restored to the TCD memory. If the major iteration count is completed, additional
bogdanm	82:6473597d706e	4652	* processing is performed.
bogdanm	82:6473597d706e	4653	*/
bogdanm	82:6473597d706e	4654	//@{
bogdanm	82:6473597d706e	4655	#define BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
bogdanm	82:6473597d706e	4656	#define BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (0x000003FFU) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
bogdanm	82:6473597d706e	4657	#define BS_DMA_TCDn_NBYTES_MLOFFYES_NBYTES (10U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
bogdanm	82:6473597d706e	4658
bogdanm	82:6473597d706e	4659	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4660	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_NBYTES field.
bogdanm	82:6473597d706e	4661	#define BR_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.NBYTES)
bogdanm	82:6473597d706e	4662	#endif
bogdanm	82:6473597d706e	4663
bogdanm	82:6473597d706e	4664	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_NBYTES.
bogdanm	82:6473597d706e	4665	#define BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_NBYTES), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES)
bogdanm	82:6473597d706e	4666
bogdanm	82:6473597d706e	4667	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4668	//! @brief Set the NBYTES field to a new value.
bogdanm	82:6473597d706e	4669	#define BW_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_NBYTES) \| BF_DMA_TCDn_NBYTES_MLOFFYES_NBYTES(v)))
bogdanm	82:6473597d706e	4670	#endif
bogdanm	82:6473597d706e	4671	//@}
bogdanm	82:6473597d706e	4672
bogdanm	82:6473597d706e	4673	/*!
bogdanm	82:6473597d706e	4674	* @name Register DMA_TCDn_NBYTES_MLOFFYES, field MLOFF[29:10] (RW)
bogdanm	82:6473597d706e	4675	*/
bogdanm	82:6473597d706e	4676	//@{
bogdanm	82:6473597d706e	4677	#define BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (10U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
bogdanm	82:6473597d706e	4678	#define BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (0x3FFFFC00U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
bogdanm	82:6473597d706e	4679	#define BS_DMA_TCDn_NBYTES_MLOFFYES_MLOFF (20U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
bogdanm	82:6473597d706e	4680
bogdanm	82:6473597d706e	4681	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4682	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_MLOFF field.
bogdanm	82:6473597d706e	4683	#define BR_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n) (HW_DMA_TCDn_NBYTES_MLOFFYES(x, n).B.MLOFF)
bogdanm	82:6473597d706e	4684	#endif
bogdanm	82:6473597d706e	4685
bogdanm	82:6473597d706e	4686	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_MLOFF.
bogdanm	82:6473597d706e	4687	#define BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_MLOFF), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF)
bogdanm	82:6473597d706e	4688
bogdanm	82:6473597d706e	4689	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4690	//! @brief Set the MLOFF field to a new value.
bogdanm	82:6473597d706e	4691	#define BW_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(x, n, v) (HW_DMA_TCDn_NBYTES_MLOFFYES_WR(x, n, (HW_DMA_TCDn_NBYTES_MLOFFYES_RD(x, n) & ~BM_DMA_TCDn_NBYTES_MLOFFYES_MLOFF) \| BF_DMA_TCDn_NBYTES_MLOFFYES_MLOFF(v)))
bogdanm	82:6473597d706e	4692	#endif
bogdanm	82:6473597d706e	4693	//@}
bogdanm	82:6473597d706e	4694
bogdanm	82:6473597d706e	4695	/*!
bogdanm	82:6473597d706e	4696	* @name Register DMA_TCDn_NBYTES_MLOFFYES, field DMLOE[30] (RW)
bogdanm	82:6473597d706e	4697	*
bogdanm	82:6473597d706e	4698	* Selects whether the minor loop offset is applied to the destination address
bogdanm	82:6473597d706e	4699	* upon minor loop completion.
bogdanm	82:6473597d706e	4700	*
bogdanm	82:6473597d706e	4701	* Values:
bogdanm	82:6473597d706e	4702	* - 0 - The minor loop offset is not applied to the DADDR
bogdanm	82:6473597d706e	4703	* - 1 - The minor loop offset is applied to the DADDR
bogdanm	82:6473597d706e	4704	*/
bogdanm	82:6473597d706e	4705	//@{
bogdanm	82:6473597d706e	4706	#define BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (30U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
bogdanm	82:6473597d706e	4707	#define BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (0x40000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
bogdanm	82:6473597d706e	4708	#define BS_DMA_TCDn_NBYTES_MLOFFYES_DMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
bogdanm	82:6473597d706e	4709
bogdanm	82:6473597d706e	4710	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4711	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_DMLOE field.
bogdanm	82:6473597d706e	4712	#define BR_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE))
bogdanm	82:6473597d706e	4713	#endif
bogdanm	82:6473597d706e	4714
bogdanm	82:6473597d706e	4715	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_DMLOE.
bogdanm	82:6473597d706e	4716	#define BF_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_DMLOE)
bogdanm	82:6473597d706e	4717
bogdanm	82:6473597d706e	4718	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4719	//! @brief Set the DMLOE field to a new value.
bogdanm	82:6473597d706e	4720	#define BW_DMA_TCDn_NBYTES_MLOFFYES_DMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_DMLOE) = (v))
bogdanm	82:6473597d706e	4721	#endif
bogdanm	82:6473597d706e	4722	//@}
bogdanm	82:6473597d706e	4723
bogdanm	82:6473597d706e	4724	/*!
bogdanm	82:6473597d706e	4725	* @name Register DMA_TCDn_NBYTES_MLOFFYES, field SMLOE[31] (RW)
bogdanm	82:6473597d706e	4726	*
bogdanm	82:6473597d706e	4727	* Selects whether the minor loop offset is applied to the source address upon
bogdanm	82:6473597d706e	4728	* minor loop completion.
bogdanm	82:6473597d706e	4729	*
bogdanm	82:6473597d706e	4730	* Values:
bogdanm	82:6473597d706e	4731	* - 0 - The minor loop offset is not applied to the SADDR
bogdanm	82:6473597d706e	4732	* - 1 - The minor loop offset is applied to the SADDR
bogdanm	82:6473597d706e	4733	*/
bogdanm	82:6473597d706e	4734	//@{
bogdanm	82:6473597d706e	4735	#define BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (31U) //!< Bit position for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
bogdanm	82:6473597d706e	4736	#define BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (0x80000000U) //!< Bit mask for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
bogdanm	82:6473597d706e	4737	#define BS_DMA_TCDn_NBYTES_MLOFFYES_SMLOE (1U) //!< Bit field size in bits for DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
bogdanm	82:6473597d706e	4738
bogdanm	82:6473597d706e	4739	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4740	//! @brief Read current value of the DMA_TCDn_NBYTES_MLOFFYES_SMLOE field.
bogdanm	82:6473597d706e	4741	#define BR_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE))
bogdanm	82:6473597d706e	4742	#endif
bogdanm	82:6473597d706e	4743
bogdanm	82:6473597d706e	4744	//! @brief Format value for bitfield DMA_TCDn_NBYTES_MLOFFYES_SMLOE.
bogdanm	82:6473597d706e	4745	#define BF_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE), uint32_t) & BM_DMA_TCDn_NBYTES_MLOFFYES_SMLOE)
bogdanm	82:6473597d706e	4746
bogdanm	82:6473597d706e	4747	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4748	//! @brief Set the SMLOE field to a new value.
bogdanm	82:6473597d706e	4749	#define BW_DMA_TCDn_NBYTES_MLOFFYES_SMLOE(x, n, v) (BITBAND_ACCESS32(HW_DMA_TCDn_NBYTES_MLOFFYES_ADDR(x, n), BP_DMA_TCDn_NBYTES_MLOFFYES_SMLOE) = (v))
bogdanm	82:6473597d706e	4750	#endif
bogdanm	82:6473597d706e	4751	//@}
bogdanm	82:6473597d706e	4752	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4753	// HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment
bogdanm	82:6473597d706e	4754	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4755
bogdanm	82:6473597d706e	4756	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4757	/*!
bogdanm	82:6473597d706e	4758	* @brief HW_DMA_TCDn_SLAST - TCD Last Source Address Adjustment (RW)
bogdanm	82:6473597d706e	4759	*
bogdanm	82:6473597d706e	4760	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4761	*/
bogdanm	82:6473597d706e	4762	typedef union _hw_dma_tcdn_slast
bogdanm	82:6473597d706e	4763	{
bogdanm	82:6473597d706e	4764	uint32_t U;
bogdanm	82:6473597d706e	4765	struct _hw_dma_tcdn_slast_bitfields
bogdanm	82:6473597d706e	4766	{
bogdanm	82:6473597d706e	4767	uint32_t SLAST : 32; //!< [31:0] Last source Address Adjustment
bogdanm	82:6473597d706e	4768	} B;
bogdanm	82:6473597d706e	4769	} hw_dma_tcdn_slast_t;
bogdanm	82:6473597d706e	4770	#endif
bogdanm	82:6473597d706e	4771
bogdanm	82:6473597d706e	4772	/*!
bogdanm	82:6473597d706e	4773	* @name Constants and macros for entire DMA_TCDn_SLAST register
bogdanm	82:6473597d706e	4774	*/
bogdanm	82:6473597d706e	4775	//@{
bogdanm	82:6473597d706e	4776	#define HW_DMA_TCDn_SLAST_COUNT (16U)
bogdanm	82:6473597d706e	4777
bogdanm	82:6473597d706e	4778	#define HW_DMA_TCDn_SLAST_ADDR(x, n) (REGS_DMA_BASE(x) + 0x100CU + (0x20U * n))
bogdanm	82:6473597d706e	4779
bogdanm	82:6473597d706e	4780	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4781	#define HW_DMA_TCDn_SLAST(x, n) ((__IO hw_dma_tcdn_slast_t ) HW_DMA_TCDn_SLAST_ADDR(x, n))
bogdanm	82:6473597d706e	4782	#define HW_DMA_TCDn_SLAST_RD(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
bogdanm	82:6473597d706e	4783	#define HW_DMA_TCDn_SLAST_WR(x, n, v) (HW_DMA_TCDn_SLAST(x, n).U = (v))
bogdanm	82:6473597d706e	4784	#define HW_DMA_TCDn_SLAST_SET(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	4785	#define HW_DMA_TCDn_SLAST_CLR(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	4786	#define HW_DMA_TCDn_SLAST_TOG(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, HW_DMA_TCDn_SLAST_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	4787	#endif
bogdanm	82:6473597d706e	4788	//@}
bogdanm	82:6473597d706e	4789
bogdanm	82:6473597d706e	4790	/*
bogdanm	82:6473597d706e	4791	* Constants & macros for individual DMA_TCDn_SLAST bitfields
bogdanm	82:6473597d706e	4792	*/
bogdanm	82:6473597d706e	4793
bogdanm	82:6473597d706e	4794	/*!
bogdanm	82:6473597d706e	4795	* @name Register DMA_TCDn_SLAST, field SLAST[31:0] (RW)
bogdanm	82:6473597d706e	4796	*
bogdanm	82:6473597d706e	4797	* Adjustment value added to the source address at the completion of the major
bogdanm	82:6473597d706e	4798	* iteration count. This value can be applied to restore the source address to the
bogdanm	82:6473597d706e	4799	* initial value, or adjust the address to reference the next data structure.
bogdanm	82:6473597d706e	4800	* This register uses two's complement notation; the overflow bit is discarded.
bogdanm	82:6473597d706e	4801	*/
bogdanm	82:6473597d706e	4802	//@{
bogdanm	82:6473597d706e	4803	#define BP_DMA_TCDn_SLAST_SLAST (0U) //!< Bit position for DMA_TCDn_SLAST_SLAST.
bogdanm	82:6473597d706e	4804	#define BM_DMA_TCDn_SLAST_SLAST (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_SLAST_SLAST.
bogdanm	82:6473597d706e	4805	#define BS_DMA_TCDn_SLAST_SLAST (32U) //!< Bit field size in bits for DMA_TCDn_SLAST_SLAST.
bogdanm	82:6473597d706e	4806
bogdanm	82:6473597d706e	4807	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4808	//! @brief Read current value of the DMA_TCDn_SLAST_SLAST field.
bogdanm	82:6473597d706e	4809	#define BR_DMA_TCDn_SLAST_SLAST(x, n) (HW_DMA_TCDn_SLAST(x, n).U)
bogdanm	82:6473597d706e	4810	#endif
bogdanm	82:6473597d706e	4811
bogdanm	82:6473597d706e	4812	//! @brief Format value for bitfield DMA_TCDn_SLAST_SLAST.
bogdanm	82:6473597d706e	4813	#define BF_DMA_TCDn_SLAST_SLAST(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_SLAST_SLAST), uint32_t) & BM_DMA_TCDn_SLAST_SLAST)
bogdanm	82:6473597d706e	4814
bogdanm	82:6473597d706e	4815	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4816	//! @brief Set the SLAST field to a new value.
bogdanm	82:6473597d706e	4817	#define BW_DMA_TCDn_SLAST_SLAST(x, n, v) (HW_DMA_TCDn_SLAST_WR(x, n, v))
bogdanm	82:6473597d706e	4818	#endif
bogdanm	82:6473597d706e	4819	//@}
bogdanm	82:6473597d706e	4820	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4821	// HW_DMA_TCDn_DADDR - TCD Destination Address
bogdanm	82:6473597d706e	4822	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4823
bogdanm	82:6473597d706e	4824	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4825	/*!
bogdanm	82:6473597d706e	4826	* @brief HW_DMA_TCDn_DADDR - TCD Destination Address (RW)
bogdanm	82:6473597d706e	4827	*
bogdanm	82:6473597d706e	4828	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	4829	*/
bogdanm	82:6473597d706e	4830	typedef union _hw_dma_tcdn_daddr
bogdanm	82:6473597d706e	4831	{
bogdanm	82:6473597d706e	4832	uint32_t U;
bogdanm	82:6473597d706e	4833	struct _hw_dma_tcdn_daddr_bitfields
bogdanm	82:6473597d706e	4834	{
bogdanm	82:6473597d706e	4835	uint32_t DADDR : 32; //!< [31:0] Destination Address
bogdanm	82:6473597d706e	4836	} B;
bogdanm	82:6473597d706e	4837	} hw_dma_tcdn_daddr_t;
bogdanm	82:6473597d706e	4838	#endif
bogdanm	82:6473597d706e	4839
bogdanm	82:6473597d706e	4840	/*!
bogdanm	82:6473597d706e	4841	* @name Constants and macros for entire DMA_TCDn_DADDR register
bogdanm	82:6473597d706e	4842	*/
bogdanm	82:6473597d706e	4843	//@{
bogdanm	82:6473597d706e	4844	#define HW_DMA_TCDn_DADDR_COUNT (16U)
bogdanm	82:6473597d706e	4845
bogdanm	82:6473597d706e	4846	#define HW_DMA_TCDn_DADDR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1010U + (0x20U * n))
bogdanm	82:6473597d706e	4847
bogdanm	82:6473597d706e	4848	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4849	#define HW_DMA_TCDn_DADDR(x, n) ((__IO hw_dma_tcdn_daddr_t ) HW_DMA_TCDn_DADDR_ADDR(x, n))
bogdanm	82:6473597d706e	4850	#define HW_DMA_TCDn_DADDR_RD(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
bogdanm	82:6473597d706e	4851	#define HW_DMA_TCDn_DADDR_WR(x, n, v) (HW_DMA_TCDn_DADDR(x, n).U = (v))
bogdanm	82:6473597d706e	4852	#define HW_DMA_TCDn_DADDR_SET(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	4853	#define HW_DMA_TCDn_DADDR_CLR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	4854	#define HW_DMA_TCDn_DADDR_TOG(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, HW_DMA_TCDn_DADDR_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	4855	#endif
bogdanm	82:6473597d706e	4856	//@}
bogdanm	82:6473597d706e	4857
bogdanm	82:6473597d706e	4858	/*
bogdanm	82:6473597d706e	4859	* Constants & macros for individual DMA_TCDn_DADDR bitfields
bogdanm	82:6473597d706e	4860	*/
bogdanm	82:6473597d706e	4861
bogdanm	82:6473597d706e	4862	/*!
bogdanm	82:6473597d706e	4863	* @name Register DMA_TCDn_DADDR, field DADDR[31:0] (RW)
bogdanm	82:6473597d706e	4864	*
bogdanm	82:6473597d706e	4865	* Memory address pointing to the destination data.
bogdanm	82:6473597d706e	4866	*/
bogdanm	82:6473597d706e	4867	//@{
bogdanm	82:6473597d706e	4868	#define BP_DMA_TCDn_DADDR_DADDR (0U) //!< Bit position for DMA_TCDn_DADDR_DADDR.
bogdanm	82:6473597d706e	4869	#define BM_DMA_TCDn_DADDR_DADDR (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_DADDR_DADDR.
bogdanm	82:6473597d706e	4870	#define BS_DMA_TCDn_DADDR_DADDR (32U) //!< Bit field size in bits for DMA_TCDn_DADDR_DADDR.
bogdanm	82:6473597d706e	4871
bogdanm	82:6473597d706e	4872	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4873	//! @brief Read current value of the DMA_TCDn_DADDR_DADDR field.
bogdanm	82:6473597d706e	4874	#define BR_DMA_TCDn_DADDR_DADDR(x, n) (HW_DMA_TCDn_DADDR(x, n).U)
bogdanm	82:6473597d706e	4875	#endif
bogdanm	82:6473597d706e	4876
bogdanm	82:6473597d706e	4877	//! @brief Format value for bitfield DMA_TCDn_DADDR_DADDR.
bogdanm	82:6473597d706e	4878	#define BF_DMA_TCDn_DADDR_DADDR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_DADDR_DADDR), uint32_t) & BM_DMA_TCDn_DADDR_DADDR)
bogdanm	82:6473597d706e	4879
bogdanm	82:6473597d706e	4880	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4881	//! @brief Set the DADDR field to a new value.
bogdanm	82:6473597d706e	4882	#define BW_DMA_TCDn_DADDR_DADDR(x, n, v) (HW_DMA_TCDn_DADDR_WR(x, n, v))
bogdanm	82:6473597d706e	4883	#endif
bogdanm	82:6473597d706e	4884	//@}
bogdanm	82:6473597d706e	4885	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4886	// HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset
bogdanm	82:6473597d706e	4887	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4888
bogdanm	82:6473597d706e	4889	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4890	/*!
bogdanm	82:6473597d706e	4891	* @brief HW_DMA_TCDn_DOFF - TCD Signed Destination Address Offset (RW)
bogdanm	82:6473597d706e	4892	*
bogdanm	82:6473597d706e	4893	* Reset value: 0x0000U
bogdanm	82:6473597d706e	4894	*/
bogdanm	82:6473597d706e	4895	typedef union _hw_dma_tcdn_doff
bogdanm	82:6473597d706e	4896	{
bogdanm	82:6473597d706e	4897	uint16_t U;
bogdanm	82:6473597d706e	4898	struct _hw_dma_tcdn_doff_bitfields
bogdanm	82:6473597d706e	4899	{
bogdanm	82:6473597d706e	4900	uint16_t DOFF : 16; //!< [15:0] Destination Address Signed offset
bogdanm	82:6473597d706e	4901	} B;
bogdanm	82:6473597d706e	4902	} hw_dma_tcdn_doff_t;
bogdanm	82:6473597d706e	4903	#endif
bogdanm	82:6473597d706e	4904
bogdanm	82:6473597d706e	4905	/*!
bogdanm	82:6473597d706e	4906	* @name Constants and macros for entire DMA_TCDn_DOFF register
bogdanm	82:6473597d706e	4907	*/
bogdanm	82:6473597d706e	4908	//@{
bogdanm	82:6473597d706e	4909	#define HW_DMA_TCDn_DOFF_COUNT (16U)
bogdanm	82:6473597d706e	4910
bogdanm	82:6473597d706e	4911	#define HW_DMA_TCDn_DOFF_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1014U + (0x20U * n))
bogdanm	82:6473597d706e	4912
bogdanm	82:6473597d706e	4913	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4914	#define HW_DMA_TCDn_DOFF(x, n) ((__IO hw_dma_tcdn_doff_t ) HW_DMA_TCDn_DOFF_ADDR(x, n))
bogdanm	82:6473597d706e	4915	#define HW_DMA_TCDn_DOFF_RD(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
bogdanm	82:6473597d706e	4916	#define HW_DMA_TCDn_DOFF_WR(x, n, v) (HW_DMA_TCDn_DOFF(x, n).U = (v))
bogdanm	82:6473597d706e	4917	#define HW_DMA_TCDn_DOFF_SET(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	4918	#define HW_DMA_TCDn_DOFF_CLR(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	4919	#define HW_DMA_TCDn_DOFF_TOG(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, HW_DMA_TCDn_DOFF_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	4920	#endif
bogdanm	82:6473597d706e	4921	//@}
bogdanm	82:6473597d706e	4922
bogdanm	82:6473597d706e	4923	/*
bogdanm	82:6473597d706e	4924	* Constants & macros for individual DMA_TCDn_DOFF bitfields
bogdanm	82:6473597d706e	4925	*/
bogdanm	82:6473597d706e	4926
bogdanm	82:6473597d706e	4927	/*!
bogdanm	82:6473597d706e	4928	* @name Register DMA_TCDn_DOFF, field DOFF[15:0] (RW)
bogdanm	82:6473597d706e	4929	*
bogdanm	82:6473597d706e	4930	* Sign-extended offset applied to the current destination address to form the
bogdanm	82:6473597d706e	4931	* next-state value as each destination write is completed.
bogdanm	82:6473597d706e	4932	*/
bogdanm	82:6473597d706e	4933	//@{
bogdanm	82:6473597d706e	4934	#define BP_DMA_TCDn_DOFF_DOFF (0U) //!< Bit position for DMA_TCDn_DOFF_DOFF.
bogdanm	82:6473597d706e	4935	#define BM_DMA_TCDn_DOFF_DOFF (0xFFFFU) //!< Bit mask for DMA_TCDn_DOFF_DOFF.
bogdanm	82:6473597d706e	4936	#define BS_DMA_TCDn_DOFF_DOFF (16U) //!< Bit field size in bits for DMA_TCDn_DOFF_DOFF.
bogdanm	82:6473597d706e	4937
bogdanm	82:6473597d706e	4938	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4939	//! @brief Read current value of the DMA_TCDn_DOFF_DOFF field.
bogdanm	82:6473597d706e	4940	#define BR_DMA_TCDn_DOFF_DOFF(x, n) (HW_DMA_TCDn_DOFF(x, n).U)
bogdanm	82:6473597d706e	4941	#endif
bogdanm	82:6473597d706e	4942
bogdanm	82:6473597d706e	4943	//! @brief Format value for bitfield DMA_TCDn_DOFF_DOFF.
bogdanm	82:6473597d706e	4944	#define BF_DMA_TCDn_DOFF_DOFF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_DOFF_DOFF), uint16_t) & BM_DMA_TCDn_DOFF_DOFF)
bogdanm	82:6473597d706e	4945
bogdanm	82:6473597d706e	4946	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4947	//! @brief Set the DOFF field to a new value.
bogdanm	82:6473597d706e	4948	#define BW_DMA_TCDn_DOFF_DOFF(x, n, v) (HW_DMA_TCDn_DOFF_WR(x, n, v))
bogdanm	82:6473597d706e	4949	#endif
bogdanm	82:6473597d706e	4950	//@}
bogdanm	82:6473597d706e	4951	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4952	// HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
bogdanm	82:6473597d706e	4953	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	4954
bogdanm	82:6473597d706e	4955	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4956	/*!
bogdanm	82:6473597d706e	4957	* @brief HW_DMA_TCDn_CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
bogdanm	82:6473597d706e	4958	*
bogdanm	82:6473597d706e	4959	* Reset value: 0x0000U
bogdanm	82:6473597d706e	4960	*
bogdanm	82:6473597d706e	4961	* If TCDn_CITER[ELINK] is cleared, the TCDn_CITER register is defined as
bogdanm	82:6473597d706e	4962	* follows.
bogdanm	82:6473597d706e	4963	*/
bogdanm	82:6473597d706e	4964	typedef union _hw_dma_tcdn_citer_elinkno
bogdanm	82:6473597d706e	4965	{
bogdanm	82:6473597d706e	4966	uint16_t U;
bogdanm	82:6473597d706e	4967	struct _hw_dma_tcdn_citer_elinkno_bitfields
bogdanm	82:6473597d706e	4968	{
bogdanm	82:6473597d706e	4969	uint16_t CITER : 15; //!< [14:0] Current Major Iteration Count
bogdanm	82:6473597d706e	4970	uint16_t ELINK : 1; //!< [15] Enable channel-to-channel linking on
bogdanm	82:6473597d706e	4971	//! minor-loop complete
bogdanm	82:6473597d706e	4972	} B;
bogdanm	82:6473597d706e	4973	} hw_dma_tcdn_citer_elinkno_t;
bogdanm	82:6473597d706e	4974	#endif
bogdanm	82:6473597d706e	4975
bogdanm	82:6473597d706e	4976	/*!
bogdanm	82:6473597d706e	4977	* @name Constants and macros for entire DMA_TCDn_CITER_ELINKNO register
bogdanm	82:6473597d706e	4978	*/
bogdanm	82:6473597d706e	4979	//@{
bogdanm	82:6473597d706e	4980	#define HW_DMA_TCDn_CITER_ELINKNO_COUNT (16U)
bogdanm	82:6473597d706e	4981
bogdanm	82:6473597d706e	4982	#define HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1016U + (0x20U * n))
bogdanm	82:6473597d706e	4983
bogdanm	82:6473597d706e	4984	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	4985	#define HW_DMA_TCDn_CITER_ELINKNO(x, n) ((__IO hw_dma_tcdn_citer_elinkno_t ) HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n))
bogdanm	82:6473597d706e	4986	#define HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U)
bogdanm	82:6473597d706e	4987	#define HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO(x, n).U = (v))
bogdanm	82:6473597d706e	4988	#define HW_DMA_TCDn_CITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	4989	#define HW_DMA_TCDn_CITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	4990	#define HW_DMA_TCDn_CITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	4991	#endif
bogdanm	82:6473597d706e	4992	//@}
bogdanm	82:6473597d706e	4993
bogdanm	82:6473597d706e	4994	/*
bogdanm	82:6473597d706e	4995	* Constants & macros for individual DMA_TCDn_CITER_ELINKNO bitfields
bogdanm	82:6473597d706e	4996	*/
bogdanm	82:6473597d706e	4997
bogdanm	82:6473597d706e	4998	/*!
bogdanm	82:6473597d706e	4999	* @name Register DMA_TCDn_CITER_ELINKNO, field CITER[14:0] (RW)
bogdanm	82:6473597d706e	5000	*
bogdanm	82:6473597d706e	5001	* This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
bogdanm	82:6473597d706e	5002	* major loop count for the channel. It is decremented each time the minor loop is
bogdanm	82:6473597d706e	5003	* completed and updated in the transfer control descriptor memory. After the
bogdanm	82:6473597d706e	5004	* major iteration count is exhausted, the channel performs a number of operations
bogdanm	82:6473597d706e	5005	* (e.g., final source and destination address calculations), optionally generating
bogdanm	82:6473597d706e	5006	* an interrupt to signal channel completion before reloading the CITER field
bogdanm	82:6473597d706e	5007	* from the beginning iteration count (BITER) field. When the CITER field is
bogdanm	82:6473597d706e	5008	* initially loaded by software, it must be set to the same value as that contained in
bogdanm	82:6473597d706e	5009	* the BITER field. If the channel is configured to execute a single service
bogdanm	82:6473597d706e	5010	* request, the initial values of BITER and CITER should be 0x0001.
bogdanm	82:6473597d706e	5011	*/
bogdanm	82:6473597d706e	5012	//@{
bogdanm	82:6473597d706e	5013	#define BP_DMA_TCDn_CITER_ELINKNO_CITER (0U) //!< Bit position for DMA_TCDn_CITER_ELINKNO_CITER.
bogdanm	82:6473597d706e	5014	#define BM_DMA_TCDn_CITER_ELINKNO_CITER (0x7FFFU) //!< Bit mask for DMA_TCDn_CITER_ELINKNO_CITER.
bogdanm	82:6473597d706e	5015	#define BS_DMA_TCDn_CITER_ELINKNO_CITER (15U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_CITER.
bogdanm	82:6473597d706e	5016
bogdanm	82:6473597d706e	5017	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5018	//! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_CITER field.
bogdanm	82:6473597d706e	5019	#define BR_DMA_TCDn_CITER_ELINKNO_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKNO(x, n).B.CITER)
bogdanm	82:6473597d706e	5020	#endif
bogdanm	82:6473597d706e	5021
bogdanm	82:6473597d706e	5022	//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_CITER.
bogdanm	82:6473597d706e	5023	#define BF_DMA_TCDn_CITER_ELINKNO_CITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKNO_CITER), uint16_t) & BM_DMA_TCDn_CITER_ELINKNO_CITER)
bogdanm	82:6473597d706e	5024
bogdanm	82:6473597d706e	5025	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5026	//! @brief Set the CITER field to a new value.
bogdanm	82:6473597d706e	5027	#define BW_DMA_TCDn_CITER_ELINKNO_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_CITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKNO_CITER) \| BF_DMA_TCDn_CITER_ELINKNO_CITER(v)))
bogdanm	82:6473597d706e	5028	#endif
bogdanm	82:6473597d706e	5029	//@}
bogdanm	82:6473597d706e	5030
bogdanm	82:6473597d706e	5031	/*!
bogdanm	82:6473597d706e	5032	* @name Register DMA_TCDn_CITER_ELINKNO, field ELINK[15] (RW)
bogdanm	82:6473597d706e	5033	*
bogdanm	82:6473597d706e	5034	* As the channel completes the minor loop, this flag enables linking to another
bogdanm	82:6473597d706e	5035	* channel, defined by the LINKCH field. The link target channel initiates a
bogdanm	82:6473597d706e	5036	* channel service request via an internal mechanism that sets the TCDn_CSR[START]
bogdanm	82:6473597d706e	5037	* bit of the specified channel. If channel linking is disabled, the CITER value
bogdanm	82:6473597d706e	5038	* is extended to 15 bits in place of a link channel number. If the major loop is
bogdanm	82:6473597d706e	5039	* exhausted, this link mechanism is suppressed in favor of the MAJORELINK
bogdanm	82:6473597d706e	5040	* channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
bogdanm	82:6473597d706e	5041	* configuration error is reported.
bogdanm	82:6473597d706e	5042	*
bogdanm	82:6473597d706e	5043	* Values:
bogdanm	82:6473597d706e	5044	* - 0 - The channel-to-channel linking is disabled
bogdanm	82:6473597d706e	5045	* - 1 - The channel-to-channel linking is enabled
bogdanm	82:6473597d706e	5046	*/
bogdanm	82:6473597d706e	5047	//@{
bogdanm	82:6473597d706e	5048	#define BP_DMA_TCDn_CITER_ELINKNO_ELINK (15U) //!< Bit position for DMA_TCDn_CITER_ELINKNO_ELINK.
bogdanm	82:6473597d706e	5049	#define BM_DMA_TCDn_CITER_ELINKNO_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_CITER_ELINKNO_ELINK.
bogdanm	82:6473597d706e	5050	#define BS_DMA_TCDn_CITER_ELINKNO_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKNO_ELINK.
bogdanm	82:6473597d706e	5051
bogdanm	82:6473597d706e	5052	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5053	//! @brief Read current value of the DMA_TCDn_CITER_ELINKNO_ELINK field.
bogdanm	82:6473597d706e	5054	#define BR_DMA_TCDn_CITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK))
bogdanm	82:6473597d706e	5055	#endif
bogdanm	82:6473597d706e	5056
bogdanm	82:6473597d706e	5057	//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKNO_ELINK.
bogdanm	82:6473597d706e	5058	#define BF_DMA_TCDn_CITER_ELINKNO_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKNO_ELINK), uint16_t) & BM_DMA_TCDn_CITER_ELINKNO_ELINK)
bogdanm	82:6473597d706e	5059
bogdanm	82:6473597d706e	5060	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5061	//! @brief Set the ELINK field to a new value.
bogdanm	82:6473597d706e	5062	#define BW_DMA_TCDn_CITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKNO_ELINK) = (v))
bogdanm	82:6473597d706e	5063	#endif
bogdanm	82:6473597d706e	5064	//@}
bogdanm	82:6473597d706e	5065	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5066	// HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
bogdanm	82:6473597d706e	5067	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5068
bogdanm	82:6473597d706e	5069	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5070	/*!
bogdanm	82:6473597d706e	5071	* @brief HW_DMA_TCDn_CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
bogdanm	82:6473597d706e	5072	*
bogdanm	82:6473597d706e	5073	* Reset value: 0x0000U
bogdanm	82:6473597d706e	5074	*
bogdanm	82:6473597d706e	5075	* If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows.
bogdanm	82:6473597d706e	5076	*/
bogdanm	82:6473597d706e	5077	typedef union _hw_dma_tcdn_citer_elinkyes
bogdanm	82:6473597d706e	5078	{
bogdanm	82:6473597d706e	5079	uint16_t U;
bogdanm	82:6473597d706e	5080	struct _hw_dma_tcdn_citer_elinkyes_bitfields
bogdanm	82:6473597d706e	5081	{
bogdanm	82:6473597d706e	5082	uint16_t CITER : 9; //!< [8:0] Current Major Iteration Count
bogdanm	82:6473597d706e	5083	uint16_t LINKCH : 4; //!< [12:9] Link Channel Number
bogdanm	82:6473597d706e	5084	uint16_t RESERVED0 : 2; //!< [14:13]
bogdanm	82:6473597d706e	5085	uint16_t ELINK : 1; //!< [15] Enable channel-to-channel linking on
bogdanm	82:6473597d706e	5086	//! minor-loop complete
bogdanm	82:6473597d706e	5087	} B;
bogdanm	82:6473597d706e	5088	} hw_dma_tcdn_citer_elinkyes_t;
bogdanm	82:6473597d706e	5089	#endif
bogdanm	82:6473597d706e	5090
bogdanm	82:6473597d706e	5091	/*!
bogdanm	82:6473597d706e	5092	* @name Constants and macros for entire DMA_TCDn_CITER_ELINKYES register
bogdanm	82:6473597d706e	5093	*/
bogdanm	82:6473597d706e	5094	//@{
bogdanm	82:6473597d706e	5095	#define HW_DMA_TCDn_CITER_ELINKYES_COUNT (16U)
bogdanm	82:6473597d706e	5096
bogdanm	82:6473597d706e	5097	#define HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1016U + (0x20U * n))
bogdanm	82:6473597d706e	5098
bogdanm	82:6473597d706e	5099	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5100	#define HW_DMA_TCDn_CITER_ELINKYES(x, n) ((__IO hw_dma_tcdn_citer_elinkyes_t ) HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n))
bogdanm	82:6473597d706e	5101	#define HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U)
bogdanm	82:6473597d706e	5102	#define HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES(x, n).U = (v))
bogdanm	82:6473597d706e	5103	#define HW_DMA_TCDn_CITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	5104	#define HW_DMA_TCDn_CITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	5105	#define HW_DMA_TCDn_CITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	5106	#endif
bogdanm	82:6473597d706e	5107	//@}
bogdanm	82:6473597d706e	5108
bogdanm	82:6473597d706e	5109	/*
bogdanm	82:6473597d706e	5110	* Constants & macros for individual DMA_TCDn_CITER_ELINKYES bitfields
bogdanm	82:6473597d706e	5111	*/
bogdanm	82:6473597d706e	5112
bogdanm	82:6473597d706e	5113	/*!
bogdanm	82:6473597d706e	5114	* @name Register DMA_TCDn_CITER_ELINKYES, field CITER[8:0] (RW)
bogdanm	82:6473597d706e	5115	*
bogdanm	82:6473597d706e	5116	* This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current
bogdanm	82:6473597d706e	5117	* major loop count for the channel. It is decremented each time the minor loop is
bogdanm	82:6473597d706e	5118	* completed and updated in the transfer control descriptor memory. After the
bogdanm	82:6473597d706e	5119	* major iteration count is exhausted, the channel performs a number of operations
bogdanm	82:6473597d706e	5120	* (e.g., final source and destination address calculations), optionally generating
bogdanm	82:6473597d706e	5121	* an interrupt to signal channel completion before reloading the CITER field
bogdanm	82:6473597d706e	5122	* from the beginning iteration count (BITER) field. When the CITER field is
bogdanm	82:6473597d706e	5123	* initially loaded by software, it must be set to the same value as that contained in
bogdanm	82:6473597d706e	5124	* the BITER field. If the channel is configured to execute a single service
bogdanm	82:6473597d706e	5125	* request, the initial values of BITER and CITER should be 0x0001.
bogdanm	82:6473597d706e	5126	*/
bogdanm	82:6473597d706e	5127	//@{
bogdanm	82:6473597d706e	5128	#define BP_DMA_TCDn_CITER_ELINKYES_CITER (0U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_CITER.
bogdanm	82:6473597d706e	5129	#define BM_DMA_TCDn_CITER_ELINKYES_CITER (0x01FFU) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_CITER.
bogdanm	82:6473597d706e	5130	#define BS_DMA_TCDn_CITER_ELINKYES_CITER (9U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_CITER.
bogdanm	82:6473597d706e	5131
bogdanm	82:6473597d706e	5132	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5133	//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_CITER field.
bogdanm	82:6473597d706e	5134	#define BR_DMA_TCDn_CITER_ELINKYES_CITER(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.CITER)
bogdanm	82:6473597d706e	5135	#endif
bogdanm	82:6473597d706e	5136
bogdanm	82:6473597d706e	5137	//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_CITER.
bogdanm	82:6473597d706e	5138	#define BF_DMA_TCDn_CITER_ELINKYES_CITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_CITER), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_CITER)
bogdanm	82:6473597d706e	5139
bogdanm	82:6473597d706e	5140	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5141	//! @brief Set the CITER field to a new value.
bogdanm	82:6473597d706e	5142	#define BW_DMA_TCDn_CITER_ELINKYES_CITER(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_CITER) \| BF_DMA_TCDn_CITER_ELINKYES_CITER(v)))
bogdanm	82:6473597d706e	5143	#endif
bogdanm	82:6473597d706e	5144	//@}
bogdanm	82:6473597d706e	5145
bogdanm	82:6473597d706e	5146	/*!
bogdanm	82:6473597d706e	5147	* @name Register DMA_TCDn_CITER_ELINKYES, field LINKCH[12:9] (RW)
bogdanm	82:6473597d706e	5148	*
bogdanm	82:6473597d706e	5149	* If channel-to-channel linking is enabled (ELINK = 1), then after the minor
bogdanm	82:6473597d706e	5150	* loop is exhausted, the eDMA engine initiates a channel service request to the
bogdanm	82:6473597d706e	5151	* channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
bogdanm	82:6473597d706e	5152	*/
bogdanm	82:6473597d706e	5153	//@{
bogdanm	82:6473597d706e	5154	#define BP_DMA_TCDn_CITER_ELINKYES_LINKCH (9U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_LINKCH.
bogdanm	82:6473597d706e	5155	#define BM_DMA_TCDn_CITER_ELINKYES_LINKCH (0x1E00U) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_LINKCH.
bogdanm	82:6473597d706e	5156	#define BS_DMA_TCDn_CITER_ELINKYES_LINKCH (4U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_LINKCH.
bogdanm	82:6473597d706e	5157
bogdanm	82:6473597d706e	5158	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5159	//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_LINKCH field.
bogdanm	82:6473597d706e	5160	#define BR_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_CITER_ELINKYES(x, n).B.LINKCH)
bogdanm	82:6473597d706e	5161	#endif
bogdanm	82:6473597d706e	5162
bogdanm	82:6473597d706e	5163	//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_LINKCH.
bogdanm	82:6473597d706e	5164	#define BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_LINKCH), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_LINKCH)
bogdanm	82:6473597d706e	5165
bogdanm	82:6473597d706e	5166	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5167	//! @brief Set the LINKCH field to a new value.
bogdanm	82:6473597d706e	5168	#define BW_DMA_TCDn_CITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_CITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_CITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_CITER_ELINKYES_LINKCH) \| BF_DMA_TCDn_CITER_ELINKYES_LINKCH(v)))
bogdanm	82:6473597d706e	5169	#endif
bogdanm	82:6473597d706e	5170	//@}
bogdanm	82:6473597d706e	5171
bogdanm	82:6473597d706e	5172	/*!
bogdanm	82:6473597d706e	5173	* @name Register DMA_TCDn_CITER_ELINKYES, field ELINK[15] (RW)
bogdanm	82:6473597d706e	5174	*
bogdanm	82:6473597d706e	5175	* As the channel completes the minor loop, this flag enables linking to another
bogdanm	82:6473597d706e	5176	* channel, defined by the LINKCH field. The link target channel initiates a
bogdanm	82:6473597d706e	5177	* channel service request via an internal mechanism that sets the TCDn_CSR[START]
bogdanm	82:6473597d706e	5178	* bit of the specified channel. If channel linking is disabled, the CITER value
bogdanm	82:6473597d706e	5179	* is extended to 15 bits in place of a link channel number. If the major loop is
bogdanm	82:6473597d706e	5180	* exhausted, this link mechanism is suppressed in favor of the MAJORELINK
bogdanm	82:6473597d706e	5181	* channel linking. This bit must be equal to the BITER[ELINK] bit; otherwise, a
bogdanm	82:6473597d706e	5182	* configuration error is reported.
bogdanm	82:6473597d706e	5183	*
bogdanm	82:6473597d706e	5184	* Values:
bogdanm	82:6473597d706e	5185	* - 0 - The channel-to-channel linking is disabled
bogdanm	82:6473597d706e	5186	* - 1 - The channel-to-channel linking is enabled
bogdanm	82:6473597d706e	5187	*/
bogdanm	82:6473597d706e	5188	//@{
bogdanm	82:6473597d706e	5189	#define BP_DMA_TCDn_CITER_ELINKYES_ELINK (15U) //!< Bit position for DMA_TCDn_CITER_ELINKYES_ELINK.
bogdanm	82:6473597d706e	5190	#define BM_DMA_TCDn_CITER_ELINKYES_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_CITER_ELINKYES_ELINK.
bogdanm	82:6473597d706e	5191	#define BS_DMA_TCDn_CITER_ELINKYES_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_CITER_ELINKYES_ELINK.
bogdanm	82:6473597d706e	5192
bogdanm	82:6473597d706e	5193	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5194	//! @brief Read current value of the DMA_TCDn_CITER_ELINKYES_ELINK field.
bogdanm	82:6473597d706e	5195	#define BR_DMA_TCDn_CITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK))
bogdanm	82:6473597d706e	5196	#endif
bogdanm	82:6473597d706e	5197
bogdanm	82:6473597d706e	5198	//! @brief Format value for bitfield DMA_TCDn_CITER_ELINKYES_ELINK.
bogdanm	82:6473597d706e	5199	#define BF_DMA_TCDn_CITER_ELINKYES_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CITER_ELINKYES_ELINK), uint16_t) & BM_DMA_TCDn_CITER_ELINKYES_ELINK)
bogdanm	82:6473597d706e	5200
bogdanm	82:6473597d706e	5201	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5202	//! @brief Set the ELINK field to a new value.
bogdanm	82:6473597d706e	5203	#define BW_DMA_TCDn_CITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_CITER_ELINKYES_ELINK) = (v))
bogdanm	82:6473597d706e	5204	#endif
bogdanm	82:6473597d706e	5205	//@}
bogdanm	82:6473597d706e	5206	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5207	// HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address
bogdanm	82:6473597d706e	5208	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5209
bogdanm	82:6473597d706e	5210	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5211	/*!
bogdanm	82:6473597d706e	5212	* @brief HW_DMA_TCDn_DLASTSGA - TCD Last Destination Address Adjustment/Scatter Gather Address (RW)
bogdanm	82:6473597d706e	5213	*
bogdanm	82:6473597d706e	5214	* Reset value: 0x00000000U
bogdanm	82:6473597d706e	5215	*/
bogdanm	82:6473597d706e	5216	typedef union _hw_dma_tcdn_dlastsga
bogdanm	82:6473597d706e	5217	{
bogdanm	82:6473597d706e	5218	uint32_t U;
bogdanm	82:6473597d706e	5219	struct _hw_dma_tcdn_dlastsga_bitfields
bogdanm	82:6473597d706e	5220	{
bogdanm	82:6473597d706e	5221	uint32_t DLASTSGA : 32; //!< [31:0]
bogdanm	82:6473597d706e	5222	} B;
bogdanm	82:6473597d706e	5223	} hw_dma_tcdn_dlastsga_t;
bogdanm	82:6473597d706e	5224	#endif
bogdanm	82:6473597d706e	5225
bogdanm	82:6473597d706e	5226	/*!
bogdanm	82:6473597d706e	5227	* @name Constants and macros for entire DMA_TCDn_DLASTSGA register
bogdanm	82:6473597d706e	5228	*/
bogdanm	82:6473597d706e	5229	//@{
bogdanm	82:6473597d706e	5230	#define HW_DMA_TCDn_DLASTSGA_COUNT (16U)
bogdanm	82:6473597d706e	5231
bogdanm	82:6473597d706e	5232	#define HW_DMA_TCDn_DLASTSGA_ADDR(x, n) (REGS_DMA_BASE(x) + 0x1018U + (0x20U * n))
bogdanm	82:6473597d706e	5233
bogdanm	82:6473597d706e	5234	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5235	#define HW_DMA_TCDn_DLASTSGA(x, n) ((__IO hw_dma_tcdn_dlastsga_t ) HW_DMA_TCDn_DLASTSGA_ADDR(x, n))
bogdanm	82:6473597d706e	5236	#define HW_DMA_TCDn_DLASTSGA_RD(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
bogdanm	82:6473597d706e	5237	#define HW_DMA_TCDn_DLASTSGA_WR(x, n, v) (HW_DMA_TCDn_DLASTSGA(x, n).U = (v))
bogdanm	82:6473597d706e	5238	#define HW_DMA_TCDn_DLASTSGA_SET(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	5239	#define HW_DMA_TCDn_DLASTSGA_CLR(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	5240	#define HW_DMA_TCDn_DLASTSGA_TOG(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, HW_DMA_TCDn_DLASTSGA_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	5241	#endif
bogdanm	82:6473597d706e	5242	//@}
bogdanm	82:6473597d706e	5243
bogdanm	82:6473597d706e	5244	/*
bogdanm	82:6473597d706e	5245	* Constants & macros for individual DMA_TCDn_DLASTSGA bitfields
bogdanm	82:6473597d706e	5246	*/
bogdanm	82:6473597d706e	5247
bogdanm	82:6473597d706e	5248	/*!
bogdanm	82:6473597d706e	5249	* @name Register DMA_TCDn_DLASTSGA, field DLASTSGA[31:0] (RW)
bogdanm	82:6473597d706e	5250	*
bogdanm	82:6473597d706e	5251	* Destination last address adjustment or the memory address for the next
bogdanm	82:6473597d706e	5252	* transfer control descriptor to be loaded into this channel (scatter/gather). If
bogdanm	82:6473597d706e	5253	* (TCDn_CSR[ESG] = 0), then: Adjustment value added to the destination address at
bogdanm	82:6473597d706e	5254	* the completion of the major iteration count. This value can apply to restore the
bogdanm	82:6473597d706e	5255	* destination address to the initial value or adjust the address to reference
bogdanm	82:6473597d706e	5256	* the next data structure. This field uses two's complement notation for the
bogdanm	82:6473597d706e	5257	* final destination address adjustment. Otherwise: This address points to the
bogdanm	82:6473597d706e	5258	* beginning of a 0-modulo-32-byte region containing the next transfer control
bogdanm	82:6473597d706e	5259	* descriptor to be loaded into this channel. This channel reload is performed as the
bogdanm	82:6473597d706e	5260	* major iteration count completes. The scatter/gather address must be
bogdanm	82:6473597d706e	5261	* 0-modulo-32-byte, else a configuration error is reported.
bogdanm	82:6473597d706e	5262	*/
bogdanm	82:6473597d706e	5263	//@{
bogdanm	82:6473597d706e	5264	#define BP_DMA_TCDn_DLASTSGA_DLASTSGA (0U) //!< Bit position for DMA_TCDn_DLASTSGA_DLASTSGA.
bogdanm	82:6473597d706e	5265	#define BM_DMA_TCDn_DLASTSGA_DLASTSGA (0xFFFFFFFFU) //!< Bit mask for DMA_TCDn_DLASTSGA_DLASTSGA.
bogdanm	82:6473597d706e	5266	#define BS_DMA_TCDn_DLASTSGA_DLASTSGA (32U) //!< Bit field size in bits for DMA_TCDn_DLASTSGA_DLASTSGA.
bogdanm	82:6473597d706e	5267
bogdanm	82:6473597d706e	5268	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5269	//! @brief Read current value of the DMA_TCDn_DLASTSGA_DLASTSGA field.
bogdanm	82:6473597d706e	5270	#define BR_DMA_TCDn_DLASTSGA_DLASTSGA(x, n) (HW_DMA_TCDn_DLASTSGA(x, n).U)
bogdanm	82:6473597d706e	5271	#endif
bogdanm	82:6473597d706e	5272
bogdanm	82:6473597d706e	5273	//! @brief Format value for bitfield DMA_TCDn_DLASTSGA_DLASTSGA.
bogdanm	82:6473597d706e	5274	#define BF_DMA_TCDn_DLASTSGA_DLASTSGA(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint32_t) << BP_DMA_TCDn_DLASTSGA_DLASTSGA), uint32_t) & BM_DMA_TCDn_DLASTSGA_DLASTSGA)
bogdanm	82:6473597d706e	5275
bogdanm	82:6473597d706e	5276	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5277	//! @brief Set the DLASTSGA field to a new value.
bogdanm	82:6473597d706e	5278	#define BW_DMA_TCDn_DLASTSGA_DLASTSGA(x, n, v) (HW_DMA_TCDn_DLASTSGA_WR(x, n, v))
bogdanm	82:6473597d706e	5279	#endif
bogdanm	82:6473597d706e	5280	//@}
bogdanm	82:6473597d706e	5281	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5282	// HW_DMA_TCDn_CSR - TCD Control and Status
bogdanm	82:6473597d706e	5283	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5284
bogdanm	82:6473597d706e	5285	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5286	/*!
bogdanm	82:6473597d706e	5287	* @brief HW_DMA_TCDn_CSR - TCD Control and Status (RW)
bogdanm	82:6473597d706e	5288	*
bogdanm	82:6473597d706e	5289	* Reset value: 0x0000U
bogdanm	82:6473597d706e	5290	*/
bogdanm	82:6473597d706e	5291	typedef union _hw_dma_tcdn_csr
bogdanm	82:6473597d706e	5292	{
bogdanm	82:6473597d706e	5293	uint16_t U;
bogdanm	82:6473597d706e	5294	struct _hw_dma_tcdn_csr_bitfields
bogdanm	82:6473597d706e	5295	{
bogdanm	82:6473597d706e	5296	uint16_t START : 1; //!< [0] Channel Start
bogdanm	82:6473597d706e	5297	uint16_t INTMAJOR : 1; //!< [1] Enable an interrupt when major
bogdanm	82:6473597d706e	5298	//! iteration count completes
bogdanm	82:6473597d706e	5299	uint16_t INTHALF : 1; //!< [2] Enable an interrupt when major counter
bogdanm	82:6473597d706e	5300	//! is half complete.
bogdanm	82:6473597d706e	5301	uint16_t DREQ : 1; //!< [3] Disable Request
bogdanm	82:6473597d706e	5302	uint16_t ESG : 1; //!< [4] Enable Scatter/Gather Processing
bogdanm	82:6473597d706e	5303	uint16_t MAJORELINK : 1; //!< [5] Enable channel-to-channel linking
bogdanm	82:6473597d706e	5304	//! on major loop complete
bogdanm	82:6473597d706e	5305	uint16_t ACTIVE : 1; //!< [6] Channel Active
bogdanm	82:6473597d706e	5306	uint16_t DONE : 1; //!< [7] Channel Done
bogdanm	82:6473597d706e	5307	uint16_t MAJORLINKCH : 4; //!< [11:8] Link Channel Number
bogdanm	82:6473597d706e	5308	uint16_t RESERVED0 : 2; //!< [13:12]
bogdanm	82:6473597d706e	5309	uint16_t BWC : 2; //!< [15:14] Bandwidth Control
bogdanm	82:6473597d706e	5310	} B;
bogdanm	82:6473597d706e	5311	} hw_dma_tcdn_csr_t;
bogdanm	82:6473597d706e	5312	#endif
bogdanm	82:6473597d706e	5313
bogdanm	82:6473597d706e	5314	/*!
bogdanm	82:6473597d706e	5315	* @name Constants and macros for entire DMA_TCDn_CSR register
bogdanm	82:6473597d706e	5316	*/
bogdanm	82:6473597d706e	5317	//@{
bogdanm	82:6473597d706e	5318	#define HW_DMA_TCDn_CSR_COUNT (16U)
bogdanm	82:6473597d706e	5319
bogdanm	82:6473597d706e	5320	#define HW_DMA_TCDn_CSR_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101CU + (0x20U * n))
bogdanm	82:6473597d706e	5321
bogdanm	82:6473597d706e	5322	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5323	#define HW_DMA_TCDn_CSR(x, n) ((__IO hw_dma_tcdn_csr_t ) HW_DMA_TCDn_CSR_ADDR(x, n))
bogdanm	82:6473597d706e	5324	#define HW_DMA_TCDn_CSR_RD(x, n) (HW_DMA_TCDn_CSR(x, n).U)
bogdanm	82:6473597d706e	5325	#define HW_DMA_TCDn_CSR_WR(x, n, v) (HW_DMA_TCDn_CSR(x, n).U = (v))
bogdanm	82:6473597d706e	5326	#define HW_DMA_TCDn_CSR_SET(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	5327	#define HW_DMA_TCDn_CSR_CLR(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	5328	#define HW_DMA_TCDn_CSR_TOG(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, HW_DMA_TCDn_CSR_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	5329	#endif
bogdanm	82:6473597d706e	5330	//@}
bogdanm	82:6473597d706e	5331
bogdanm	82:6473597d706e	5332	/*
bogdanm	82:6473597d706e	5333	* Constants & macros for individual DMA_TCDn_CSR bitfields
bogdanm	82:6473597d706e	5334	*/
bogdanm	82:6473597d706e	5335
bogdanm	82:6473597d706e	5336	/*!
bogdanm	82:6473597d706e	5337	* @name Register DMA_TCDn_CSR, field START[0] (RW)
bogdanm	82:6473597d706e	5338	*
bogdanm	82:6473597d706e	5339	* If this flag is set, the channel is requesting service. The eDMA hardware
bogdanm	82:6473597d706e	5340	* automatically clears this flag after the channel begins execution.
bogdanm	82:6473597d706e	5341	*
bogdanm	82:6473597d706e	5342	* Values:
bogdanm	82:6473597d706e	5343	* - 0 - The channel is not explicitly started
bogdanm	82:6473597d706e	5344	* - 1 - The channel is explicitly started via a software initiated service
bogdanm	82:6473597d706e	5345	* request
bogdanm	82:6473597d706e	5346	*/
bogdanm	82:6473597d706e	5347	//@{
bogdanm	82:6473597d706e	5348	#define BP_DMA_TCDn_CSR_START (0U) //!< Bit position for DMA_TCDn_CSR_START.
bogdanm	82:6473597d706e	5349	#define BM_DMA_TCDn_CSR_START (0x0001U) //!< Bit mask for DMA_TCDn_CSR_START.
bogdanm	82:6473597d706e	5350	#define BS_DMA_TCDn_CSR_START (1U) //!< Bit field size in bits for DMA_TCDn_CSR_START.
bogdanm	82:6473597d706e	5351
bogdanm	82:6473597d706e	5352	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5353	//! @brief Read current value of the DMA_TCDn_CSR_START field.
bogdanm	82:6473597d706e	5354	#define BR_DMA_TCDn_CSR_START(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START))
bogdanm	82:6473597d706e	5355	#endif
bogdanm	82:6473597d706e	5356
bogdanm	82:6473597d706e	5357	//! @brief Format value for bitfield DMA_TCDn_CSR_START.
bogdanm	82:6473597d706e	5358	#define BF_DMA_TCDn_CSR_START(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_START), uint16_t) & BM_DMA_TCDn_CSR_START)
bogdanm	82:6473597d706e	5359
bogdanm	82:6473597d706e	5360	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5361	//! @brief Set the START field to a new value.
bogdanm	82:6473597d706e	5362	#define BW_DMA_TCDn_CSR_START(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_START) = (v))
bogdanm	82:6473597d706e	5363	#endif
bogdanm	82:6473597d706e	5364	//@}
bogdanm	82:6473597d706e	5365
bogdanm	82:6473597d706e	5366	/*!
bogdanm	82:6473597d706e	5367	* @name Register DMA_TCDn_CSR, field INTMAJOR[1] (RW)
bogdanm	82:6473597d706e	5368	*
bogdanm	82:6473597d706e	5369	* If this flag is set, the channel generates an interrupt request by setting
bogdanm	82:6473597d706e	5370	* the appropriate bit in the INT when the current major iteration count reaches
bogdanm	82:6473597d706e	5371	* zero.
bogdanm	82:6473597d706e	5372	*
bogdanm	82:6473597d706e	5373	* Values:
bogdanm	82:6473597d706e	5374	* - 0 - The end-of-major loop interrupt is disabled
bogdanm	82:6473597d706e	5375	* - 1 - The end-of-major loop interrupt is enabled
bogdanm	82:6473597d706e	5376	*/
bogdanm	82:6473597d706e	5377	//@{
bogdanm	82:6473597d706e	5378	#define BP_DMA_TCDn_CSR_INTMAJOR (1U) //!< Bit position for DMA_TCDn_CSR_INTMAJOR.
bogdanm	82:6473597d706e	5379	#define BM_DMA_TCDn_CSR_INTMAJOR (0x0002U) //!< Bit mask for DMA_TCDn_CSR_INTMAJOR.
bogdanm	82:6473597d706e	5380	#define BS_DMA_TCDn_CSR_INTMAJOR (1U) //!< Bit field size in bits for DMA_TCDn_CSR_INTMAJOR.
bogdanm	82:6473597d706e	5381
bogdanm	82:6473597d706e	5382	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5383	//! @brief Read current value of the DMA_TCDn_CSR_INTMAJOR field.
bogdanm	82:6473597d706e	5384	#define BR_DMA_TCDn_CSR_INTMAJOR(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR))
bogdanm	82:6473597d706e	5385	#endif
bogdanm	82:6473597d706e	5386
bogdanm	82:6473597d706e	5387	//! @brief Format value for bitfield DMA_TCDn_CSR_INTMAJOR.
bogdanm	82:6473597d706e	5388	#define BF_DMA_TCDn_CSR_INTMAJOR(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_INTMAJOR), uint16_t) & BM_DMA_TCDn_CSR_INTMAJOR)
bogdanm	82:6473597d706e	5389
bogdanm	82:6473597d706e	5390	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5391	//! @brief Set the INTMAJOR field to a new value.
bogdanm	82:6473597d706e	5392	#define BW_DMA_TCDn_CSR_INTMAJOR(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTMAJOR) = (v))
bogdanm	82:6473597d706e	5393	#endif
bogdanm	82:6473597d706e	5394	//@}
bogdanm	82:6473597d706e	5395
bogdanm	82:6473597d706e	5396	/*!
bogdanm	82:6473597d706e	5397	* @name Register DMA_TCDn_CSR, field INTHALF[2] (RW)
bogdanm	82:6473597d706e	5398	*
bogdanm	82:6473597d706e	5399	* If this flag is set, the channel generates an interrupt request by setting
bogdanm	82:6473597d706e	5400	* the appropriate bit in the INT register when the current major iteration count
bogdanm	82:6473597d706e	5401	* reaches the halfway point. Specifically, the comparison performed by the eDMA
bogdanm	82:6473597d706e	5402	* engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
bogdanm	82:6473597d706e	5403	* provided to support double-buffered (aka ping-pong) schemes or other types of data
bogdanm	82:6473597d706e	5404	* movement where the processor needs an early indication of the transfer's
bogdanm	82:6473597d706e	5405	* progress. If BITER is set, do not use INTHALF. Use INTMAJOR instead.
bogdanm	82:6473597d706e	5406	*
bogdanm	82:6473597d706e	5407	* Values:
bogdanm	82:6473597d706e	5408	* - 0 - The half-point interrupt is disabled
bogdanm	82:6473597d706e	5409	* - 1 - The half-point interrupt is enabled
bogdanm	82:6473597d706e	5410	*/
bogdanm	82:6473597d706e	5411	//@{
bogdanm	82:6473597d706e	5412	#define BP_DMA_TCDn_CSR_INTHALF (2U) //!< Bit position for DMA_TCDn_CSR_INTHALF.
bogdanm	82:6473597d706e	5413	#define BM_DMA_TCDn_CSR_INTHALF (0x0004U) //!< Bit mask for DMA_TCDn_CSR_INTHALF.
bogdanm	82:6473597d706e	5414	#define BS_DMA_TCDn_CSR_INTHALF (1U) //!< Bit field size in bits for DMA_TCDn_CSR_INTHALF.
bogdanm	82:6473597d706e	5415
bogdanm	82:6473597d706e	5416	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5417	//! @brief Read current value of the DMA_TCDn_CSR_INTHALF field.
bogdanm	82:6473597d706e	5418	#define BR_DMA_TCDn_CSR_INTHALF(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF))
bogdanm	82:6473597d706e	5419	#endif
bogdanm	82:6473597d706e	5420
bogdanm	82:6473597d706e	5421	//! @brief Format value for bitfield DMA_TCDn_CSR_INTHALF.
bogdanm	82:6473597d706e	5422	#define BF_DMA_TCDn_CSR_INTHALF(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_INTHALF), uint16_t) & BM_DMA_TCDn_CSR_INTHALF)
bogdanm	82:6473597d706e	5423
bogdanm	82:6473597d706e	5424	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5425	//! @brief Set the INTHALF field to a new value.
bogdanm	82:6473597d706e	5426	#define BW_DMA_TCDn_CSR_INTHALF(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_INTHALF) = (v))
bogdanm	82:6473597d706e	5427	#endif
bogdanm	82:6473597d706e	5428	//@}
bogdanm	82:6473597d706e	5429
bogdanm	82:6473597d706e	5430	/*!
bogdanm	82:6473597d706e	5431	* @name Register DMA_TCDn_CSR, field DREQ[3] (RW)
bogdanm	82:6473597d706e	5432	*
bogdanm	82:6473597d706e	5433	* If this flag is set, the eDMA hardware automatically clears the corresponding
bogdanm	82:6473597d706e	5434	* ERQ bit when the current major iteration count reaches zero.
bogdanm	82:6473597d706e	5435	*
bogdanm	82:6473597d706e	5436	* Values:
bogdanm	82:6473597d706e	5437	* - 0 - The channel's ERQ bit is not affected
bogdanm	82:6473597d706e	5438	* - 1 - The channel's ERQ bit is cleared when the major loop is complete
bogdanm	82:6473597d706e	5439	*/
bogdanm	82:6473597d706e	5440	//@{
bogdanm	82:6473597d706e	5441	#define BP_DMA_TCDn_CSR_DREQ (3U) //!< Bit position for DMA_TCDn_CSR_DREQ.
bogdanm	82:6473597d706e	5442	#define BM_DMA_TCDn_CSR_DREQ (0x0008U) //!< Bit mask for DMA_TCDn_CSR_DREQ.
bogdanm	82:6473597d706e	5443	#define BS_DMA_TCDn_CSR_DREQ (1U) //!< Bit field size in bits for DMA_TCDn_CSR_DREQ.
bogdanm	82:6473597d706e	5444
bogdanm	82:6473597d706e	5445	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5446	//! @brief Read current value of the DMA_TCDn_CSR_DREQ field.
bogdanm	82:6473597d706e	5447	#define BR_DMA_TCDn_CSR_DREQ(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ))
bogdanm	82:6473597d706e	5448	#endif
bogdanm	82:6473597d706e	5449
bogdanm	82:6473597d706e	5450	//! @brief Format value for bitfield DMA_TCDn_CSR_DREQ.
bogdanm	82:6473597d706e	5451	#define BF_DMA_TCDn_CSR_DREQ(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_DREQ), uint16_t) & BM_DMA_TCDn_CSR_DREQ)
bogdanm	82:6473597d706e	5452
bogdanm	82:6473597d706e	5453	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5454	//! @brief Set the DREQ field to a new value.
bogdanm	82:6473597d706e	5455	#define BW_DMA_TCDn_CSR_DREQ(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DREQ) = (v))
bogdanm	82:6473597d706e	5456	#endif
bogdanm	82:6473597d706e	5457	//@}
bogdanm	82:6473597d706e	5458
bogdanm	82:6473597d706e	5459	/*!
bogdanm	82:6473597d706e	5460	* @name Register DMA_TCDn_CSR, field ESG[4] (RW)
bogdanm	82:6473597d706e	5461	*
bogdanm	82:6473597d706e	5462	* As the channel completes the major loop, this flag enables scatter/gather
bogdanm	82:6473597d706e	5463	* processing in the current channel. If enabled, the eDMA engine uses DLASTSGA as a
bogdanm	82:6473597d706e	5464	* memory pointer to a 0-modulo-32 address containing a 32-byte data structure
bogdanm	82:6473597d706e	5465	* loaded as the transfer control descriptor into the local memory. To support the
bogdanm	82:6473597d706e	5466	* dynamic scatter/gather coherency model, this field is forced to zero when
bogdanm	82:6473597d706e	5467	* written to while the TCDn_CSR[DONE] bit is set.
bogdanm	82:6473597d706e	5468	*
bogdanm	82:6473597d706e	5469	* Values:
bogdanm	82:6473597d706e	5470	* - 0 - The current channel's TCD is normal format.
bogdanm	82:6473597d706e	5471	* - 1 - The current channel's TCD specifies a scatter gather format. The
bogdanm	82:6473597d706e	5472	* DLASTSGA field provides a memory pointer to the next TCD to be loaded into this
bogdanm	82:6473597d706e	5473	* channel after the major loop completes its execution.
bogdanm	82:6473597d706e	5474	*/
bogdanm	82:6473597d706e	5475	//@{
bogdanm	82:6473597d706e	5476	#define BP_DMA_TCDn_CSR_ESG (4U) //!< Bit position for DMA_TCDn_CSR_ESG.
bogdanm	82:6473597d706e	5477	#define BM_DMA_TCDn_CSR_ESG (0x0010U) //!< Bit mask for DMA_TCDn_CSR_ESG.
bogdanm	82:6473597d706e	5478	#define BS_DMA_TCDn_CSR_ESG (1U) //!< Bit field size in bits for DMA_TCDn_CSR_ESG.
bogdanm	82:6473597d706e	5479
bogdanm	82:6473597d706e	5480	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5481	//! @brief Read current value of the DMA_TCDn_CSR_ESG field.
bogdanm	82:6473597d706e	5482	#define BR_DMA_TCDn_CSR_ESG(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG))
bogdanm	82:6473597d706e	5483	#endif
bogdanm	82:6473597d706e	5484
bogdanm	82:6473597d706e	5485	//! @brief Format value for bitfield DMA_TCDn_CSR_ESG.
bogdanm	82:6473597d706e	5486	#define BF_DMA_TCDn_CSR_ESG(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_ESG), uint16_t) & BM_DMA_TCDn_CSR_ESG)
bogdanm	82:6473597d706e	5487
bogdanm	82:6473597d706e	5488	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5489	//! @brief Set the ESG field to a new value.
bogdanm	82:6473597d706e	5490	#define BW_DMA_TCDn_CSR_ESG(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ESG) = (v))
bogdanm	82:6473597d706e	5491	#endif
bogdanm	82:6473597d706e	5492	//@}
bogdanm	82:6473597d706e	5493
bogdanm	82:6473597d706e	5494	/*!
bogdanm	82:6473597d706e	5495	* @name Register DMA_TCDn_CSR, field MAJORELINK[5] (RW)
bogdanm	82:6473597d706e	5496	*
bogdanm	82:6473597d706e	5497	* As the channel completes the major loop, this flag enables the linking to
bogdanm	82:6473597d706e	5498	* another channel, defined by MAJORLINKCH. The link target channel initiates a
bogdanm	82:6473597d706e	5499	* channel service request via an internal mechanism that sets the TCDn_CSR[START]
bogdanm	82:6473597d706e	5500	* bit of the specified channel. To support the dynamic linking coherency model,
bogdanm	82:6473597d706e	5501	* this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set.
bogdanm	82:6473597d706e	5502	*
bogdanm	82:6473597d706e	5503	* Values:
bogdanm	82:6473597d706e	5504	* - 0 - The channel-to-channel linking is disabled
bogdanm	82:6473597d706e	5505	* - 1 - The channel-to-channel linking is enabled
bogdanm	82:6473597d706e	5506	*/
bogdanm	82:6473597d706e	5507	//@{
bogdanm	82:6473597d706e	5508	#define BP_DMA_TCDn_CSR_MAJORELINK (5U) //!< Bit position for DMA_TCDn_CSR_MAJORELINK.
bogdanm	82:6473597d706e	5509	#define BM_DMA_TCDn_CSR_MAJORELINK (0x0020U) //!< Bit mask for DMA_TCDn_CSR_MAJORELINK.
bogdanm	82:6473597d706e	5510	#define BS_DMA_TCDn_CSR_MAJORELINK (1U) //!< Bit field size in bits for DMA_TCDn_CSR_MAJORELINK.
bogdanm	82:6473597d706e	5511
bogdanm	82:6473597d706e	5512	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5513	//! @brief Read current value of the DMA_TCDn_CSR_MAJORELINK field.
bogdanm	82:6473597d706e	5514	#define BR_DMA_TCDn_CSR_MAJORELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK))
bogdanm	82:6473597d706e	5515	#endif
bogdanm	82:6473597d706e	5516
bogdanm	82:6473597d706e	5517	//! @brief Format value for bitfield DMA_TCDn_CSR_MAJORELINK.
bogdanm	82:6473597d706e	5518	#define BF_DMA_TCDn_CSR_MAJORELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_MAJORELINK), uint16_t) & BM_DMA_TCDn_CSR_MAJORELINK)
bogdanm	82:6473597d706e	5519
bogdanm	82:6473597d706e	5520	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5521	//! @brief Set the MAJORELINK field to a new value.
bogdanm	82:6473597d706e	5522	#define BW_DMA_TCDn_CSR_MAJORELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_MAJORELINK) = (v))
bogdanm	82:6473597d706e	5523	#endif
bogdanm	82:6473597d706e	5524	//@}
bogdanm	82:6473597d706e	5525
bogdanm	82:6473597d706e	5526	/*!
bogdanm	82:6473597d706e	5527	* @name Register DMA_TCDn_CSR, field ACTIVE[6] (RW)
bogdanm	82:6473597d706e	5528	*
bogdanm	82:6473597d706e	5529	* This flag signals the channel is currently in execution. It is set when
bogdanm	82:6473597d706e	5530	* channel service begins, and the eDMA clears it as the minor loop completes or if
bogdanm	82:6473597d706e	5531	* any error condition is detected. This bit resets to zero.
bogdanm	82:6473597d706e	5532	*/
bogdanm	82:6473597d706e	5533	//@{
bogdanm	82:6473597d706e	5534	#define BP_DMA_TCDn_CSR_ACTIVE (6U) //!< Bit position for DMA_TCDn_CSR_ACTIVE.
bogdanm	82:6473597d706e	5535	#define BM_DMA_TCDn_CSR_ACTIVE (0x0040U) //!< Bit mask for DMA_TCDn_CSR_ACTIVE.
bogdanm	82:6473597d706e	5536	#define BS_DMA_TCDn_CSR_ACTIVE (1U) //!< Bit field size in bits for DMA_TCDn_CSR_ACTIVE.
bogdanm	82:6473597d706e	5537
bogdanm	82:6473597d706e	5538	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5539	//! @brief Read current value of the DMA_TCDn_CSR_ACTIVE field.
bogdanm	82:6473597d706e	5540	#define BR_DMA_TCDn_CSR_ACTIVE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE))
bogdanm	82:6473597d706e	5541	#endif
bogdanm	82:6473597d706e	5542
bogdanm	82:6473597d706e	5543	//! @brief Format value for bitfield DMA_TCDn_CSR_ACTIVE.
bogdanm	82:6473597d706e	5544	#define BF_DMA_TCDn_CSR_ACTIVE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_ACTIVE), uint16_t) & BM_DMA_TCDn_CSR_ACTIVE)
bogdanm	82:6473597d706e	5545
bogdanm	82:6473597d706e	5546	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5547	//! @brief Set the ACTIVE field to a new value.
bogdanm	82:6473597d706e	5548	#define BW_DMA_TCDn_CSR_ACTIVE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_ACTIVE) = (v))
bogdanm	82:6473597d706e	5549	#endif
bogdanm	82:6473597d706e	5550	//@}
bogdanm	82:6473597d706e	5551
bogdanm	82:6473597d706e	5552	/*!
bogdanm	82:6473597d706e	5553	* @name Register DMA_TCDn_CSR, field DONE[7] (RW)
bogdanm	82:6473597d706e	5554	*
bogdanm	82:6473597d706e	5555	* This flag indicates the eDMA has completed the major loop. The eDMA engine
bogdanm	82:6473597d706e	5556	* sets it as the CITER count reaches zero; The software clears it, or the hardware
bogdanm	82:6473597d706e	5557	* when the channel is activated. This bit must be cleared to write the
bogdanm	82:6473597d706e	5558	* MAJORELINK or ESG bits.
bogdanm	82:6473597d706e	5559	*/
bogdanm	82:6473597d706e	5560	//@{
bogdanm	82:6473597d706e	5561	#define BP_DMA_TCDn_CSR_DONE (7U) //!< Bit position for DMA_TCDn_CSR_DONE.
bogdanm	82:6473597d706e	5562	#define BM_DMA_TCDn_CSR_DONE (0x0080U) //!< Bit mask for DMA_TCDn_CSR_DONE.
bogdanm	82:6473597d706e	5563	#define BS_DMA_TCDn_CSR_DONE (1U) //!< Bit field size in bits for DMA_TCDn_CSR_DONE.
bogdanm	82:6473597d706e	5564
bogdanm	82:6473597d706e	5565	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5566	//! @brief Read current value of the DMA_TCDn_CSR_DONE field.
bogdanm	82:6473597d706e	5567	#define BR_DMA_TCDn_CSR_DONE(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE))
bogdanm	82:6473597d706e	5568	#endif
bogdanm	82:6473597d706e	5569
bogdanm	82:6473597d706e	5570	//! @brief Format value for bitfield DMA_TCDn_CSR_DONE.
bogdanm	82:6473597d706e	5571	#define BF_DMA_TCDn_CSR_DONE(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_DONE), uint16_t) & BM_DMA_TCDn_CSR_DONE)
bogdanm	82:6473597d706e	5572
bogdanm	82:6473597d706e	5573	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5574	//! @brief Set the DONE field to a new value.
bogdanm	82:6473597d706e	5575	#define BW_DMA_TCDn_CSR_DONE(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_CSR_ADDR(x, n), BP_DMA_TCDn_CSR_DONE) = (v))
bogdanm	82:6473597d706e	5576	#endif
bogdanm	82:6473597d706e	5577	//@}
bogdanm	82:6473597d706e	5578
bogdanm	82:6473597d706e	5579	/*!
bogdanm	82:6473597d706e	5580	* @name Register DMA_TCDn_CSR, field MAJORLINKCH[11:8] (RW)
bogdanm	82:6473597d706e	5581	*
bogdanm	82:6473597d706e	5582	* If (MAJORELINK = 0) then No channel-to-channel linking (or chaining) is
bogdanm	82:6473597d706e	5583	* performed after the major loop counter is exhausted. else After the major loop
bogdanm	82:6473597d706e	5584	* counter is exhausted, the eDMA engine initiates a channel service request at the
bogdanm	82:6473597d706e	5585	* channel defined by these six bits by setting that channel's TCDn_CSR[START] bit.
bogdanm	82:6473597d706e	5586	*/
bogdanm	82:6473597d706e	5587	//@{
bogdanm	82:6473597d706e	5588	#define BP_DMA_TCDn_CSR_MAJORLINKCH (8U) //!< Bit position for DMA_TCDn_CSR_MAJORLINKCH.
bogdanm	82:6473597d706e	5589	#define BM_DMA_TCDn_CSR_MAJORLINKCH (0x0F00U) //!< Bit mask for DMA_TCDn_CSR_MAJORLINKCH.
bogdanm	82:6473597d706e	5590	#define BS_DMA_TCDn_CSR_MAJORLINKCH (4U) //!< Bit field size in bits for DMA_TCDn_CSR_MAJORLINKCH.
bogdanm	82:6473597d706e	5591
bogdanm	82:6473597d706e	5592	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5593	//! @brief Read current value of the DMA_TCDn_CSR_MAJORLINKCH field.
bogdanm	82:6473597d706e	5594	#define BR_DMA_TCDn_CSR_MAJORLINKCH(x, n) (HW_DMA_TCDn_CSR(x, n).B.MAJORLINKCH)
bogdanm	82:6473597d706e	5595	#endif
bogdanm	82:6473597d706e	5596
bogdanm	82:6473597d706e	5597	//! @brief Format value for bitfield DMA_TCDn_CSR_MAJORLINKCH.
bogdanm	82:6473597d706e	5598	#define BF_DMA_TCDn_CSR_MAJORLINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_MAJORLINKCH), uint16_t) & BM_DMA_TCDn_CSR_MAJORLINKCH)
bogdanm	82:6473597d706e	5599
bogdanm	82:6473597d706e	5600	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5601	//! @brief Set the MAJORLINKCH field to a new value.
bogdanm	82:6473597d706e	5602	#define BW_DMA_TCDn_CSR_MAJORLINKCH(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_MAJORLINKCH) \| BF_DMA_TCDn_CSR_MAJORLINKCH(v)))
bogdanm	82:6473597d706e	5603	#endif
bogdanm	82:6473597d706e	5604	//@}
bogdanm	82:6473597d706e	5605
bogdanm	82:6473597d706e	5606	/*!
bogdanm	82:6473597d706e	5607	* @name Register DMA_TCDn_CSR, field BWC[15:14] (RW)
bogdanm	82:6473597d706e	5608	*
bogdanm	82:6473597d706e	5609	* Throttles the amount of bus bandwidth consumed by the eDMA. In general, as
bogdanm	82:6473597d706e	5610	* the eDMA processes the minor loop, it continuously generates read/write
bogdanm	82:6473597d706e	5611	* sequences until the minor count is exhausted. This field forces the eDMA to stall
bogdanm	82:6473597d706e	5612	* after the completion of each read/write access to control the bus request
bogdanm	82:6473597d706e	5613	* bandwidth seen by the crossbar switch. If the source and destination sizes are equal,
bogdanm	82:6473597d706e	5614	* this field is ignored between the first and second transfers and after the
bogdanm	82:6473597d706e	5615	* last write of each minor loop. This behavior is a side effect of reducing
bogdanm	82:6473597d706e	5616	* start-up latency.
bogdanm	82:6473597d706e	5617	*
bogdanm	82:6473597d706e	5618	* Values:
bogdanm	82:6473597d706e	5619	* - 00 - No eDMA engine stalls
bogdanm	82:6473597d706e	5620	* - 01 - Reserved
bogdanm	82:6473597d706e	5621	* - 10 - eDMA engine stalls for 4 cycles after each r/w
bogdanm	82:6473597d706e	5622	* - 11 - eDMA engine stalls for 8 cycles after each r/w
bogdanm	82:6473597d706e	5623	*/
bogdanm	82:6473597d706e	5624	//@{
bogdanm	82:6473597d706e	5625	#define BP_DMA_TCDn_CSR_BWC (14U) //!< Bit position for DMA_TCDn_CSR_BWC.
bogdanm	82:6473597d706e	5626	#define BM_DMA_TCDn_CSR_BWC (0xC000U) //!< Bit mask for DMA_TCDn_CSR_BWC.
bogdanm	82:6473597d706e	5627	#define BS_DMA_TCDn_CSR_BWC (2U) //!< Bit field size in bits for DMA_TCDn_CSR_BWC.
bogdanm	82:6473597d706e	5628
bogdanm	82:6473597d706e	5629	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5630	//! @brief Read current value of the DMA_TCDn_CSR_BWC field.
bogdanm	82:6473597d706e	5631	#define BR_DMA_TCDn_CSR_BWC(x, n) (HW_DMA_TCDn_CSR(x, n).B.BWC)
bogdanm	82:6473597d706e	5632	#endif
bogdanm	82:6473597d706e	5633
bogdanm	82:6473597d706e	5634	//! @brief Format value for bitfield DMA_TCDn_CSR_BWC.
bogdanm	82:6473597d706e	5635	#define BF_DMA_TCDn_CSR_BWC(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_CSR_BWC), uint16_t) & BM_DMA_TCDn_CSR_BWC)
bogdanm	82:6473597d706e	5636
bogdanm	82:6473597d706e	5637	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5638	//! @brief Set the BWC field to a new value.
bogdanm	82:6473597d706e	5639	#define BW_DMA_TCDn_CSR_BWC(x, n, v) (HW_DMA_TCDn_CSR_WR(x, n, (HW_DMA_TCDn_CSR_RD(x, n) & ~BM_DMA_TCDn_CSR_BWC) \| BF_DMA_TCDn_CSR_BWC(v)))
bogdanm	82:6473597d706e	5640	#endif
bogdanm	82:6473597d706e	5641	//@}
bogdanm	82:6473597d706e	5642	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5643	// HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
bogdanm	82:6473597d706e	5644	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5645
bogdanm	82:6473597d706e	5646	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5647	/*!
bogdanm	82:6473597d706e	5648	* @brief HW_DMA_TCDn_BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (RW)
bogdanm	82:6473597d706e	5649	*
bogdanm	82:6473597d706e	5650	* Reset value: 0x0000U
bogdanm	82:6473597d706e	5651	*
bogdanm	82:6473597d706e	5652	* If the TCDn_BITER[ELINK] bit is cleared, the TCDn_BITER register is defined
bogdanm	82:6473597d706e	5653	* as follows.
bogdanm	82:6473597d706e	5654	*/
bogdanm	82:6473597d706e	5655	typedef union _hw_dma_tcdn_biter_elinkno
bogdanm	82:6473597d706e	5656	{
bogdanm	82:6473597d706e	5657	uint16_t U;
bogdanm	82:6473597d706e	5658	struct _hw_dma_tcdn_biter_elinkno_bitfields
bogdanm	82:6473597d706e	5659	{
bogdanm	82:6473597d706e	5660	uint16_t BITER : 15; //!< [14:0] Starting Major Iteration Count
bogdanm	82:6473597d706e	5661	uint16_t ELINK : 1; //!< [15] Enables channel-to-channel linking on
bogdanm	82:6473597d706e	5662	//! minor loop complete
bogdanm	82:6473597d706e	5663	} B;
bogdanm	82:6473597d706e	5664	} hw_dma_tcdn_biter_elinkno_t;
bogdanm	82:6473597d706e	5665	#endif
bogdanm	82:6473597d706e	5666
bogdanm	82:6473597d706e	5667	/*!
bogdanm	82:6473597d706e	5668	* @name Constants and macros for entire DMA_TCDn_BITER_ELINKNO register
bogdanm	82:6473597d706e	5669	*/
bogdanm	82:6473597d706e	5670	//@{
bogdanm	82:6473597d706e	5671	#define HW_DMA_TCDn_BITER_ELINKNO_COUNT (16U)
bogdanm	82:6473597d706e	5672
bogdanm	82:6473597d706e	5673	#define HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101EU + (0x20U * n))
bogdanm	82:6473597d706e	5674
bogdanm	82:6473597d706e	5675	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5676	#define HW_DMA_TCDn_BITER_ELINKNO(x, n) ((__IO hw_dma_tcdn_biter_elinkno_t ) HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n))
bogdanm	82:6473597d706e	5677	#define HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U)
bogdanm	82:6473597d706e	5678	#define HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO(x, n).U = (v))
bogdanm	82:6473597d706e	5679	#define HW_DMA_TCDn_BITER_ELINKNO_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	5680	#define HW_DMA_TCDn_BITER_ELINKNO_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	5681	#define HW_DMA_TCDn_BITER_ELINKNO_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	5682	#endif
bogdanm	82:6473597d706e	5683	//@}
bogdanm	82:6473597d706e	5684
bogdanm	82:6473597d706e	5685	/*
bogdanm	82:6473597d706e	5686	* Constants & macros for individual DMA_TCDn_BITER_ELINKNO bitfields
bogdanm	82:6473597d706e	5687	*/
bogdanm	82:6473597d706e	5688
bogdanm	82:6473597d706e	5689	/*!
bogdanm	82:6473597d706e	5690	* @name Register DMA_TCDn_BITER_ELINKNO, field BITER[14:0] (RW)
bogdanm	82:6473597d706e	5691	*
bogdanm	82:6473597d706e	5692	* As the transfer control descriptor is first loaded by software, this 9-bit
bogdanm	82:6473597d706e	5693	* (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
bogdanm	82:6473597d706e	5694	* field. As the major iteration count is exhausted, the contents of this field
bogdanm	82:6473597d706e	5695	* are reloaded into the CITER field. When the software loads the TCD, this field
bogdanm	82:6473597d706e	5696	* must be set equal to the corresponding CITER field; otherwise, a configuration
bogdanm	82:6473597d706e	5697	* error is reported. As the major iteration count is exhausted, the contents of
bogdanm	82:6473597d706e	5698	* this field is reloaded into the CITER field. If the channel is configured to
bogdanm	82:6473597d706e	5699	* execute a single service request, the initial values of BITER and CITER should
bogdanm	82:6473597d706e	5700	* be 0x0001.
bogdanm	82:6473597d706e	5701	*/
bogdanm	82:6473597d706e	5702	//@{
bogdanm	82:6473597d706e	5703	#define BP_DMA_TCDn_BITER_ELINKNO_BITER (0U) //!< Bit position for DMA_TCDn_BITER_ELINKNO_BITER.
bogdanm	82:6473597d706e	5704	#define BM_DMA_TCDn_BITER_ELINKNO_BITER (0x7FFFU) //!< Bit mask for DMA_TCDn_BITER_ELINKNO_BITER.
bogdanm	82:6473597d706e	5705	#define BS_DMA_TCDn_BITER_ELINKNO_BITER (15U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_BITER.
bogdanm	82:6473597d706e	5706
bogdanm	82:6473597d706e	5707	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5708	//! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_BITER field.
bogdanm	82:6473597d706e	5709	#define BR_DMA_TCDn_BITER_ELINKNO_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKNO(x, n).B.BITER)
bogdanm	82:6473597d706e	5710	#endif
bogdanm	82:6473597d706e	5711
bogdanm	82:6473597d706e	5712	//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_BITER.
bogdanm	82:6473597d706e	5713	#define BF_DMA_TCDn_BITER_ELINKNO_BITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKNO_BITER), uint16_t) & BM_DMA_TCDn_BITER_ELINKNO_BITER)
bogdanm	82:6473597d706e	5714
bogdanm	82:6473597d706e	5715	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5716	//! @brief Set the BITER field to a new value.
bogdanm	82:6473597d706e	5717	#define BW_DMA_TCDn_BITER_ELINKNO_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKNO_WR(x, n, (HW_DMA_TCDn_BITER_ELINKNO_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKNO_BITER) \| BF_DMA_TCDn_BITER_ELINKNO_BITER(v)))
bogdanm	82:6473597d706e	5718	#endif
bogdanm	82:6473597d706e	5719	//@}
bogdanm	82:6473597d706e	5720
bogdanm	82:6473597d706e	5721	/*!
bogdanm	82:6473597d706e	5722	* @name Register DMA_TCDn_BITER_ELINKNO, field ELINK[15] (RW)
bogdanm	82:6473597d706e	5723	*
bogdanm	82:6473597d706e	5724	* As the channel completes the minor loop, this flag enables the linking to
bogdanm	82:6473597d706e	5725	* another channel, defined by BITER[LINKCH]. The link target channel initiates a
bogdanm	82:6473597d706e	5726	* channel service request via an internal mechanism that sets the TCDn_CSR[START]
bogdanm	82:6473597d706e	5727	* bit of the specified channel. If channel linking is disabled, the BITER value
bogdanm	82:6473597d706e	5728	* extends to 15 bits in place of a link channel number. If the major loop is
bogdanm	82:6473597d706e	5729	* exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
bogdanm	82:6473597d706e	5730	* linking. When the software loads the TCD, this field must be set equal to the
bogdanm	82:6473597d706e	5731	* corresponding CITER field; otherwise, a configuration error is reported. As the
bogdanm	82:6473597d706e	5732	* major iteration count is exhausted, the contents of this field is reloaded
bogdanm	82:6473597d706e	5733	* into the CITER field.
bogdanm	82:6473597d706e	5734	*
bogdanm	82:6473597d706e	5735	* Values:
bogdanm	82:6473597d706e	5736	* - 0 - The channel-to-channel linking is disabled
bogdanm	82:6473597d706e	5737	* - 1 - The channel-to-channel linking is enabled
bogdanm	82:6473597d706e	5738	*/
bogdanm	82:6473597d706e	5739	//@{
bogdanm	82:6473597d706e	5740	#define BP_DMA_TCDn_BITER_ELINKNO_ELINK (15U) //!< Bit position for DMA_TCDn_BITER_ELINKNO_ELINK.
bogdanm	82:6473597d706e	5741	#define BM_DMA_TCDn_BITER_ELINKNO_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_BITER_ELINKNO_ELINK.
bogdanm	82:6473597d706e	5742	#define BS_DMA_TCDn_BITER_ELINKNO_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKNO_ELINK.
bogdanm	82:6473597d706e	5743
bogdanm	82:6473597d706e	5744	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5745	//! @brief Read current value of the DMA_TCDn_BITER_ELINKNO_ELINK field.
bogdanm	82:6473597d706e	5746	#define BR_DMA_TCDn_BITER_ELINKNO_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK))
bogdanm	82:6473597d706e	5747	#endif
bogdanm	82:6473597d706e	5748
bogdanm	82:6473597d706e	5749	//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKNO_ELINK.
bogdanm	82:6473597d706e	5750	#define BF_DMA_TCDn_BITER_ELINKNO_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKNO_ELINK), uint16_t) & BM_DMA_TCDn_BITER_ELINKNO_ELINK)
bogdanm	82:6473597d706e	5751
bogdanm	82:6473597d706e	5752	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5753	//! @brief Set the ELINK field to a new value.
bogdanm	82:6473597d706e	5754	#define BW_DMA_TCDn_BITER_ELINKNO_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKNO_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKNO_ELINK) = (v))
bogdanm	82:6473597d706e	5755	#endif
bogdanm	82:6473597d706e	5756	//@}
bogdanm	82:6473597d706e	5757	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5758	// HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
bogdanm	82:6473597d706e	5759	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5760
bogdanm	82:6473597d706e	5761	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5762	/*!
bogdanm	82:6473597d706e	5763	* @brief HW_DMA_TCDn_BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (RW)
bogdanm	82:6473597d706e	5764	*
bogdanm	82:6473597d706e	5765	* Reset value: 0x0000U
bogdanm	82:6473597d706e	5766	*
bogdanm	82:6473597d706e	5767	* If the TCDn_BITER[ELINK] bit is set, the TCDn_BITER register is defined as
bogdanm	82:6473597d706e	5768	* follows.
bogdanm	82:6473597d706e	5769	*/
bogdanm	82:6473597d706e	5770	typedef union _hw_dma_tcdn_biter_elinkyes
bogdanm	82:6473597d706e	5771	{
bogdanm	82:6473597d706e	5772	uint16_t U;
bogdanm	82:6473597d706e	5773	struct _hw_dma_tcdn_biter_elinkyes_bitfields
bogdanm	82:6473597d706e	5774	{
bogdanm	82:6473597d706e	5775	uint16_t BITER : 9; //!< [8:0] Starting Major Iteration Count
bogdanm	82:6473597d706e	5776	uint16_t LINKCH : 4; //!< [12:9] Link Channel Number
bogdanm	82:6473597d706e	5777	uint16_t RESERVED0 : 2; //!< [14:13]
bogdanm	82:6473597d706e	5778	uint16_t ELINK : 1; //!< [15] Enables channel-to-channel linking on
bogdanm	82:6473597d706e	5779	//! minor loop complete
bogdanm	82:6473597d706e	5780	} B;
bogdanm	82:6473597d706e	5781	} hw_dma_tcdn_biter_elinkyes_t;
bogdanm	82:6473597d706e	5782	#endif
bogdanm	82:6473597d706e	5783
bogdanm	82:6473597d706e	5784	/*!
bogdanm	82:6473597d706e	5785	* @name Constants and macros for entire DMA_TCDn_BITER_ELINKYES register
bogdanm	82:6473597d706e	5786	*/
bogdanm	82:6473597d706e	5787	//@{
bogdanm	82:6473597d706e	5788	#define HW_DMA_TCDn_BITER_ELINKYES_COUNT (16U)
bogdanm	82:6473597d706e	5789
bogdanm	82:6473597d706e	5790	#define HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n) (REGS_DMA_BASE(x) + 0x101EU + (0x20U * n))
bogdanm	82:6473597d706e	5791
bogdanm	82:6473597d706e	5792	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5793	#define HW_DMA_TCDn_BITER_ELINKYES(x, n) ((__IO hw_dma_tcdn_biter_elinkyes_t ) HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n))
bogdanm	82:6473597d706e	5794	#define HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U)
bogdanm	82:6473597d706e	5795	#define HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES(x, n).U = (v))
bogdanm	82:6473597d706e	5796	#define HW_DMA_TCDn_BITER_ELINKYES_SET(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) \| (v)))
bogdanm	82:6473597d706e	5797	#define HW_DMA_TCDn_BITER_ELINKYES_CLR(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~(v)))
bogdanm	82:6473597d706e	5798	#define HW_DMA_TCDn_BITER_ELINKYES_TOG(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) ^ (v)))
bogdanm	82:6473597d706e	5799	#endif
bogdanm	82:6473597d706e	5800	//@}
bogdanm	82:6473597d706e	5801
bogdanm	82:6473597d706e	5802	/*
bogdanm	82:6473597d706e	5803	* Constants & macros for individual DMA_TCDn_BITER_ELINKYES bitfields
bogdanm	82:6473597d706e	5804	*/
bogdanm	82:6473597d706e	5805
bogdanm	82:6473597d706e	5806	/*!
bogdanm	82:6473597d706e	5807	* @name Register DMA_TCDn_BITER_ELINKYES, field BITER[8:0] (RW)
bogdanm	82:6473597d706e	5808	*
bogdanm	82:6473597d706e	5809	* As the transfer control descriptor is first loaded by software, this 9-bit
bogdanm	82:6473597d706e	5810	* (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER
bogdanm	82:6473597d706e	5811	* field. As the major iteration count is exhausted, the contents of this field
bogdanm	82:6473597d706e	5812	* are reloaded into the CITER field. When the software loads the TCD, this field
bogdanm	82:6473597d706e	5813	* must be set equal to the corresponding CITER field; otherwise, a configuration
bogdanm	82:6473597d706e	5814	* error is reported. As the major iteration count is exhausted, the contents of
bogdanm	82:6473597d706e	5815	* this field is reloaded into the CITER field. If the channel is configured to
bogdanm	82:6473597d706e	5816	* execute a single service request, the initial values of BITER and CITER should
bogdanm	82:6473597d706e	5817	* be 0x0001.
bogdanm	82:6473597d706e	5818	*/
bogdanm	82:6473597d706e	5819	//@{
bogdanm	82:6473597d706e	5820	#define BP_DMA_TCDn_BITER_ELINKYES_BITER (0U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_BITER.
bogdanm	82:6473597d706e	5821	#define BM_DMA_TCDn_BITER_ELINKYES_BITER (0x01FFU) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_BITER.
bogdanm	82:6473597d706e	5822	#define BS_DMA_TCDn_BITER_ELINKYES_BITER (9U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_BITER.
bogdanm	82:6473597d706e	5823
bogdanm	82:6473597d706e	5824	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5825	//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_BITER field.
bogdanm	82:6473597d706e	5826	#define BR_DMA_TCDn_BITER_ELINKYES_BITER(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.BITER)
bogdanm	82:6473597d706e	5827	#endif
bogdanm	82:6473597d706e	5828
bogdanm	82:6473597d706e	5829	//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_BITER.
bogdanm	82:6473597d706e	5830	#define BF_DMA_TCDn_BITER_ELINKYES_BITER(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_BITER), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_BITER)
bogdanm	82:6473597d706e	5831
bogdanm	82:6473597d706e	5832	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5833	//! @brief Set the BITER field to a new value.
bogdanm	82:6473597d706e	5834	#define BW_DMA_TCDn_BITER_ELINKYES_BITER(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_BITER) \| BF_DMA_TCDn_BITER_ELINKYES_BITER(v)))
bogdanm	82:6473597d706e	5835	#endif
bogdanm	82:6473597d706e	5836	//@}
bogdanm	82:6473597d706e	5837
bogdanm	82:6473597d706e	5838	/*!
bogdanm	82:6473597d706e	5839	* @name Register DMA_TCDn_BITER_ELINKYES, field LINKCH[12:9] (RW)
bogdanm	82:6473597d706e	5840	*
bogdanm	82:6473597d706e	5841	* If channel-to-channel linking is enabled (ELINK = 1), then after the minor
bogdanm	82:6473597d706e	5842	* loop is exhausted, the eDMA engine initiates a channel service request at the
bogdanm	82:6473597d706e	5843	* channel defined by these four bits by setting that channel's TCDn_CSR[START]
bogdanm	82:6473597d706e	5844	* bit. When the software loads the TCD, this field must be set equal to the
bogdanm	82:6473597d706e	5845	* corresponding CITER field; otherwise, a configuration error is reported. As the major
bogdanm	82:6473597d706e	5846	* iteration count is exhausted, the contents of this field is reloaded into the
bogdanm	82:6473597d706e	5847	* CITER field.
bogdanm	82:6473597d706e	5848	*/
bogdanm	82:6473597d706e	5849	//@{
bogdanm	82:6473597d706e	5850	#define BP_DMA_TCDn_BITER_ELINKYES_LINKCH (9U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_LINKCH.
bogdanm	82:6473597d706e	5851	#define BM_DMA_TCDn_BITER_ELINKYES_LINKCH (0x1E00U) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_LINKCH.
bogdanm	82:6473597d706e	5852	#define BS_DMA_TCDn_BITER_ELINKYES_LINKCH (4U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_LINKCH.
bogdanm	82:6473597d706e	5853
bogdanm	82:6473597d706e	5854	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5855	//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_LINKCH field.
bogdanm	82:6473597d706e	5856	#define BR_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n) (HW_DMA_TCDn_BITER_ELINKYES(x, n).B.LINKCH)
bogdanm	82:6473597d706e	5857	#endif
bogdanm	82:6473597d706e	5858
bogdanm	82:6473597d706e	5859	//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_LINKCH.
bogdanm	82:6473597d706e	5860	#define BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_LINKCH), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_LINKCH)
bogdanm	82:6473597d706e	5861
bogdanm	82:6473597d706e	5862	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5863	//! @brief Set the LINKCH field to a new value.
bogdanm	82:6473597d706e	5864	#define BW_DMA_TCDn_BITER_ELINKYES_LINKCH(x, n, v) (HW_DMA_TCDn_BITER_ELINKYES_WR(x, n, (HW_DMA_TCDn_BITER_ELINKYES_RD(x, n) & ~BM_DMA_TCDn_BITER_ELINKYES_LINKCH) \| BF_DMA_TCDn_BITER_ELINKYES_LINKCH(v)))
bogdanm	82:6473597d706e	5865	#endif
bogdanm	82:6473597d706e	5866	//@}
bogdanm	82:6473597d706e	5867
bogdanm	82:6473597d706e	5868	/*!
bogdanm	82:6473597d706e	5869	* @name Register DMA_TCDn_BITER_ELINKYES, field ELINK[15] (RW)
bogdanm	82:6473597d706e	5870	*
bogdanm	82:6473597d706e	5871	* As the channel completes the minor loop, this flag enables the linking to
bogdanm	82:6473597d706e	5872	* another channel, defined by BITER[LINKCH]. The link target channel initiates a
bogdanm	82:6473597d706e	5873	* channel service request via an internal mechanism that sets the TCDn_CSR[START]
bogdanm	82:6473597d706e	5874	* bit of the specified channel. If channel linking disables, the BITER value
bogdanm	82:6473597d706e	5875	* extends to 15 bits in place of a link channel number. If the major loop is
bogdanm	82:6473597d706e	5876	* exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel
bogdanm	82:6473597d706e	5877	* linking. When the software loads the TCD, this field must be set equal to the
bogdanm	82:6473597d706e	5878	* corresponding CITER field; otherwise, a configuration error is reported. As the
bogdanm	82:6473597d706e	5879	* major iteration count is exhausted, the contents of this field is reloaded into
bogdanm	82:6473597d706e	5880	* the CITER field.
bogdanm	82:6473597d706e	5881	*
bogdanm	82:6473597d706e	5882	* Values:
bogdanm	82:6473597d706e	5883	* - 0 - The channel-to-channel linking is disabled
bogdanm	82:6473597d706e	5884	* - 1 - The channel-to-channel linking is enabled
bogdanm	82:6473597d706e	5885	*/
bogdanm	82:6473597d706e	5886	//@{
bogdanm	82:6473597d706e	5887	#define BP_DMA_TCDn_BITER_ELINKYES_ELINK (15U) //!< Bit position for DMA_TCDn_BITER_ELINKYES_ELINK.
bogdanm	82:6473597d706e	5888	#define BM_DMA_TCDn_BITER_ELINKYES_ELINK (0x8000U) //!< Bit mask for DMA_TCDn_BITER_ELINKYES_ELINK.
bogdanm	82:6473597d706e	5889	#define BS_DMA_TCDn_BITER_ELINKYES_ELINK (1U) //!< Bit field size in bits for DMA_TCDn_BITER_ELINKYES_ELINK.
bogdanm	82:6473597d706e	5890
bogdanm	82:6473597d706e	5891	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5892	//! @brief Read current value of the DMA_TCDn_BITER_ELINKYES_ELINK field.
bogdanm	82:6473597d706e	5893	#define BR_DMA_TCDn_BITER_ELINKYES_ELINK(x, n) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK))
bogdanm	82:6473597d706e	5894	#endif
bogdanm	82:6473597d706e	5895
bogdanm	82:6473597d706e	5896	//! @brief Format value for bitfield DMA_TCDn_BITER_ELINKYES_ELINK.
bogdanm	82:6473597d706e	5897	#define BF_DMA_TCDn_BITER_ELINKYES_ELINK(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint16_t) << BP_DMA_TCDn_BITER_ELINKYES_ELINK), uint16_t) & BM_DMA_TCDn_BITER_ELINKYES_ELINK)
bogdanm	82:6473597d706e	5898
bogdanm	82:6473597d706e	5899	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5900	//! @brief Set the ELINK field to a new value.
bogdanm	82:6473597d706e	5901	#define BW_DMA_TCDn_BITER_ELINKYES_ELINK(x, n, v) (BITBAND_ACCESS16(HW_DMA_TCDn_BITER_ELINKYES_ADDR(x, n), BP_DMA_TCDn_BITER_ELINKYES_ELINK) = (v))
bogdanm	82:6473597d706e	5902	#endif
bogdanm	82:6473597d706e	5903	//@}
bogdanm	82:6473597d706e	5904
bogdanm	82:6473597d706e	5905	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5906	// hw_dma_t - module struct
bogdanm	82:6473597d706e	5907	//-------------------------------------------------------------------------------------------
bogdanm	82:6473597d706e	5908	/*!
bogdanm	82:6473597d706e	5909	* @brief All DMA module registers.
bogdanm	82:6473597d706e	5910	*/
bogdanm	82:6473597d706e	5911	#ifndef __LANGUAGE_ASM__
bogdanm	82:6473597d706e	5912	#pragma pack(1)
bogdanm	82:6473597d706e	5913	typedef struct _hw_dma
bogdanm	82:6473597d706e	5914	{
bogdanm	82:6473597d706e	5915	__IO hw_dma_cr_t CR; //!< [0x0] Control Register
bogdanm	82:6473597d706e	5916	__I hw_dma_es_t ES; //!< [0x4] Error Status Register
bogdanm	82:6473597d706e	5917	uint8_t _reserved0[4];
bogdanm	82:6473597d706e	5918	__IO hw_dma_erq_t ERQ; //!< [0xC] Enable Request Register
bogdanm	82:6473597d706e	5919	uint8_t _reserved1[4];
bogdanm	82:6473597d706e	5920	__IO hw_dma_eei_t EEI; //!< [0x14] Enable Error Interrupt Register
bogdanm	82:6473597d706e	5921	__O hw_dma_ceei_t CEEI; //!< [0x18] Clear Enable Error Interrupt Register
bogdanm	82:6473597d706e	5922	__O hw_dma_seei_t SEEI; //!< [0x19] Set Enable Error Interrupt Register
bogdanm	82:6473597d706e	5923	__O hw_dma_cerq_t CERQ; //!< [0x1A] Clear Enable Request Register
bogdanm	82:6473597d706e	5924	__O hw_dma_serq_t SERQ; //!< [0x1B] Set Enable Request Register
bogdanm	82:6473597d706e	5925	__O hw_dma_cdne_t CDNE; //!< [0x1C] Clear DONE Status Bit Register
bogdanm	82:6473597d706e	5926	__O hw_dma_ssrt_t SSRT; //!< [0x1D] Set START Bit Register
bogdanm	82:6473597d706e	5927	__O hw_dma_cerr_t CERR; //!< [0x1E] Clear Error Register
bogdanm	82:6473597d706e	5928	__O hw_dma_cint_t CINT; //!< [0x1F] Clear Interrupt Request Register
bogdanm	82:6473597d706e	5929	uint8_t _reserved2[4];
bogdanm	82:6473597d706e	5930	__IO hw_dma_int_t INT; //!< [0x24] Interrupt Request Register
bogdanm	82:6473597d706e	5931	uint8_t _reserved3[4];
bogdanm	82:6473597d706e	5932	__IO hw_dma_err_t ERR; //!< [0x2C] Error Register
bogdanm	82:6473597d706e	5933	uint8_t _reserved4[4];
bogdanm	82:6473597d706e	5934	__I hw_dma_hrs_t HRS; //!< [0x34] Hardware Request Status Register
bogdanm	82:6473597d706e	5935	uint8_t _reserved5[200];
bogdanm	82:6473597d706e	5936	__IO hw_dma_dchprin_t DCHPRIn[16]; //!< [0x100] Channel n Priority Register
bogdanm	82:6473597d706e	5937	uint8_t _reserved6[3824];
bogdanm	82:6473597d706e	5938	struct {
bogdanm	82:6473597d706e	5939	__IO hw_dma_tcdn_saddr_t TCDn_SADDR; //!< [0x1000] TCD Source Address
bogdanm	82:6473597d706e	5940	__IO hw_dma_tcdn_soff_t TCDn_SOFF; //!< [0x1004] TCD Signed Source Address Offset
bogdanm	82:6473597d706e	5941	__IO hw_dma_tcdn_attr_t TCDn_ATTR; //!< [0x1006] TCD Transfer Attributes
bogdanm	82:6473597d706e	5942	union {
bogdanm	82:6473597d706e	5943	__IO hw_dma_tcdn_nbytes_mlno_t TCDn_NBYTES_MLNO; //!< [0x1008] TCD Minor Byte Count (Minor Loop Disabled)
bogdanm	82:6473597d706e	5944	__IO hw_dma_tcdn_nbytes_mloffno_t TCDn_NBYTES_MLOFFNO; //!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
bogdanm	82:6473597d706e	5945	__IO hw_dma_tcdn_nbytes_mloffyes_t TCDn_NBYTES_MLOFFYES; //!< [0x1008] TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
bogdanm	82:6473597d706e	5946	};
bogdanm	82:6473597d706e	5947	__IO hw_dma_tcdn_slast_t TCDn_SLAST; //!< [0x100C] TCD Last Source Address Adjustment
bogdanm	82:6473597d706e	5948	__IO hw_dma_tcdn_daddr_t TCDn_DADDR; //!< [0x1010] TCD Destination Address
bogdanm	82:6473597d706e	5949	__IO hw_dma_tcdn_doff_t TCDn_DOFF; //!< [0x1014] TCD Signed Destination Address Offset
bogdanm	82:6473597d706e	5950	union {
bogdanm	82:6473597d706e	5951	__IO hw_dma_tcdn_citer_elinkno_t TCDn_CITER_ELINKNO; //!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
bogdanm	82:6473597d706e	5952	__IO hw_dma_tcdn_citer_elinkyes_t TCDn_CITER_ELINKYES; //!< [0x1016] TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
bogdanm	82:6473597d706e	5953	};
bogdanm	82:6473597d706e	5954	__IO hw_dma_tcdn_dlastsga_t TCDn_DLASTSGA; //!< [0x1018] TCD Last Destination Address Adjustment/Scatter Gather Address
bogdanm	82:6473597d706e	5955	__IO hw_dma_tcdn_csr_t TCDn_CSR; //!< [0x101C] TCD Control and Status
bogdanm	82:6473597d706e	5956	union {
bogdanm	82:6473597d706e	5957	__IO hw_dma_tcdn_biter_elinkno_t TCDn_BITER_ELINKNO; //!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
bogdanm	82:6473597d706e	5958	__IO hw_dma_tcdn_biter_elinkyes_t TCDn_BITER_ELINKYES; //!< [0x101E] TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
bogdanm	82:6473597d706e	5959	};
bogdanm	82:6473597d706e	5960	} TCD[16];
bogdanm	82:6473597d706e	5961	} hw_dma_t;
bogdanm	82:6473597d706e	5962	#pragma pack()
bogdanm	82:6473597d706e	5963
bogdanm	82:6473597d706e	5964	//! @brief Macro to access all DMA registers.
bogdanm	82:6473597d706e	5965	//! @param x DMA instance number.
bogdanm	82:6473597d706e	5966	//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
bogdanm	82:6473597d706e	5967	//! use the '&' operator, like <code>&HW_DMA(0)</code>.
bogdanm	82:6473597d706e	5968	#define HW_DMA(x) ((hw_dma_t ) REGS_DMA_BASE(x))
bogdanm	82:6473597d706e	5969	#endif
bogdanm	82:6473597d706e	5970
bogdanm	82:6473597d706e	5971	#endif // __HW_DMA_REGISTERS_H__
bogdanm	82:6473597d706e	5972	// v22/130726/0.9
bogdanm	82:6473597d706e	5973	// EOF

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Type:	Library
Created:	05 Apr 2016
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TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_MCU_K64F/device/MK64F12/MK64F12_dma.h@89:552587b429a1, 2014-09-12 (annotated)

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